├── .gitignore ├── .readthedocs.yml ├── LICENSE ├── MANIFEST.in ├── README.md ├── doc ├── Makefile ├── _build │ └── .keep_me ├── _static │ └── .keep_me ├── _templates │ └── .keep_me ├── conf.py ├── fhdl.rst ├── index.rst ├── introduction.rst ├── migen_logo.png ├── migen_logo.svg ├── migen_logo_white.png ├── reference.rst ├── requirements.txt ├── simulation.rst └── synthesis.rst ├── examples ├── basic │ ├── arrays.py │ ├── fsm.py │ ├── graycounter.py │ ├── instance.py │ ├── local_cd.py │ ├── memory.py │ ├── namer.py │ ├── psync.py │ ├── record.py │ ├── reslice.py │ ├── tristate.py │ └── two_dividers.py └── sim │ ├── basic1.py │ ├── basic2.py │ ├── display.py │ ├── fir.py │ └── memory.py ├── migen ├── __init__.py ├── build │ ├── __init__.py │ ├── altera │ │ ├── __init__.py │ │ ├── common.py │ │ ├── platform.py │ │ ├── programmer.py │ │ └── quartus.py │ ├── fpgalink_programmer.py │ ├── generic_platform.py │ ├── generic_programmer.py │ ├── lattice │ │ ├── __init__.py │ │ ├── common.py │ │ ├── diamond.py │ │ ├── icestorm.py │ │ ├── platform.py │ │ ├── programmer.py │ │ └── trellis.py │ ├── openocd.py │ ├── platforms │ │ ├── __init__.py │ │ ├── ac701.py │ │ ├── afc3v1.py │ │ ├── apf27.py │ │ ├── apf51.py │ │ ├── apf6sp.py │ │ ├── arty_a7.py │ │ ├── arty_s7.py │ │ ├── coraz7.py │ │ ├── de0cv.py │ │ ├── de0nano.py │ │ ├── de0nanosoc.py │ │ ├── de10lite.py │ │ ├── digilent_genesys2.py │ │ ├── ebaz4205.py │ │ ├── ice40_hx1k_blink_evn.py │ │ ├── ice40_hx8k_b_evn.py │ │ ├── ice40_up5k_b_evn.py │ │ ├── icebreaker.py │ │ ├── icestick.py │ │ ├── kc705.py │ │ ├── kcu105.py │ │ ├── lx9_microboard.py │ │ ├── m1.py │ │ ├── max1000.py │ │ ├── mercury.py │ │ ├── mimasv2.py │ │ ├── minispartan6.py │ │ ├── mixxeo.py │ │ ├── ml605.py │ │ ├── mystorm_blackice.py │ │ ├── mystorm_blackice_ii.py │ │ ├── papilio_pro.py │ │ ├── pipistrello.py │ │ ├── qm_xc6slx16_sdram.py │ │ ├── quickfeather.py │ │ ├── redpitaya.py │ │ ├── rhino.py │ │ ├── sinara │ │ │ ├── __init__.py │ │ │ ├── efc.py │ │ │ ├── humpback.py │ │ │ ├── kasli.py │ │ │ ├── kasli_soc.py │ │ │ ├── metlino.py │ │ │ ├── phaser.py │ │ │ ├── sayma_amc.py │ │ │ ├── sayma_amc2.py │ │ │ ├── sayma_rtm.py │ │ │ └── sayma_rtm2.py │ │ ├── tinyfpga_a.py │ │ ├── tinyfpga_b.py │ │ ├── tinyfpga_bx.py │ │ ├── upduino_v1.py │ │ ├── usrp_b100.py │ │ ├── versa.py │ │ ├── versaecp55g.py │ │ ├── zc706.py │ │ ├── zedboard.py │ │ └── ztex_115d.py │ ├── quicklogic │ │ ├── __init__.py │ │ ├── platform.py │ │ ├── programmer.py │ │ └── quicklogic.py │ ├── tools.py │ └── xilinx │ │ ├── __init__.py │ │ ├── common.py │ │ ├── ise.py │ │ ├── platform.py │ │ ├── programmer.py │ │ ├── symbiflow.py │ │ └── vivado.py ├── fhdl │ ├── __init__.py │ ├── bitcontainer.py │ ├── conv_output.py │ ├── decorators.py │ ├── edif.py │ ├── module.py │ ├── namer.py │ ├── simplify.py │ ├── specials.py │ ├── structure.py │ ├── tools.py │ ├── tracer.py │ ├── verilog.py │ └── visit.py ├── genlib │ ├── __init__.py │ ├── cdc.py │ ├── coding.py │ ├── divider.py │ ├── fifo.py │ ├── fsm.py │ ├── io.py │ ├── misc.py │ ├── record.py │ ├── resetsync.py │ ├── roundrobin.py │ └── sort.py ├── sim │ ├── __init__.py │ ├── core.py │ └── vcd.py ├── test │ ├── __init__.py │ ├── support.py │ ├── test_bitslip.py │ ├── test_coding.py │ ├── test_constant.py │ ├── test_divider.py │ ├── test_examples.py │ ├── test_fifo.py │ ├── test_fsm.py │ ├── test_passive.py │ ├── test_platform.py │ ├── test_signed.py │ ├── test_size.py │ ├── test_sort.py │ └── test_vcd.py └── util │ ├── __init__.py │ ├── misc.py │ └── treeviz.py ├── pyproject.toml └── tools └── strace_tailor.sh /.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__ 2 | *.pyc 3 | *.egg-info/ 4 | vpi/*.o 5 | vpi/migensim.vpi 6 | *.vcd 7 | doc/_build 8 | /build/ 9 | -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- 1 | requirements_file: doc/requirements.txt 2 | python: 3 | version: 3.5 4 | setup_py_install: true 5 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (C) 2011-2020 M-Labs Limited. 2 | 3 | Redistribution and use in source and binary forms, with or without modification, 4 | are permitted provided that the following conditions are met: 5 | 6 | 1. Redistributions of source code must retain the above copyright notice, this 7 | list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright notice, 9 | this list of conditions and the following disclaimer in the documentation 10 | and/or other materials provided with the distribution. 11 | 12 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 13 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 14 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 15 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 16 | ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 17 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 18 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 | ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 21 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | 24 | Other authors retain ownership of their contributions. If a submission can 25 | reasonably be considered independently copyrightable, it's yours and we 26 | encourage you to claim it with appropriate copyright notices. This submission 27 | then falls under the "otherwise noted" category. All submissions are strongly 28 | encouraged to use the two-clause BSD license reproduced above. 29 | -------------------------------------------------------------------------------- /MANIFEST.in: -------------------------------------------------------------------------------- 1 | include LICENSE 2 | include tools/strace_tailor.sh 3 | graft examples 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ### Migen (Milkymist generator) 2 | 3 | migen logo 4 | 5 | #### A Python toolbox for building complex digital hardware 6 | 7 | Despite being faster than schematics entry, hardware design with Verilog and 8 | VHDL remains tedious and inefficient for several reasons. The event-driven 9 | model introduces issues and manual coding that are unnecessary for synchronous 10 | circuits, which represent the lion's share of today's logic designs. Counter- 11 | intuitive arithmetic rules result in steeper learning curves and provide a 12 | fertile ground for subtle bugs in designs. Finally, support for procedural 13 | generation of logic (metaprogramming) through "generate" statements is very 14 | limited and restricts the ways code can be made generic, reused and organized. 15 | 16 | To address those issues, we have developed the **Migen FHDL** library that 17 | replaces the event-driven paradigm with the notions of combinatorial and 18 | synchronous statements, has arithmetic rules that make integers always behave 19 | like mathematical integers, and most importantly allows the design's logic to 20 | be constructed by a Python program. This last point enables hardware designers 21 | to take advantage of the richness of the Python language - object oriented 22 | programming, function parameters, generators, operator overloading, libraries, 23 | etc. - to build well organized, reusable and elegant designs. 24 | 25 | Other Migen libraries are built on FHDL and provide various tools such as a 26 | system-on-chip interconnect infrastructure, a dataflow programming system, a 27 | more traditional high-level synthesizer that compiles Python routines into 28 | state machines with datapaths, and a simulator that allows test benches to be 29 | written in Python. 30 | 31 | See the doc/ folder for more technical information. 32 | 33 | Migen is designed for Python 3.5. Note that Migen is **not** spelled MiGen. 34 | 35 | #### Quick Links 36 | 37 | Code repository: 38 | https://github.com/m-labs/migen 39 | 40 | System-on-chip design based on Migen: 41 | https://github.com/m-labs/misoc 42 | 43 | Online documentation: 44 | https://m-labs.hk/migen/manual/ 45 | 46 | #### Quick intro 47 | 48 | ```python 49 | from migen import * 50 | from migen.build.platforms import m1 51 | plat = m1.Platform() 52 | led = plat.request("user_led") 53 | m = Module() 54 | counter = Signal(26) 55 | m.comb += led.eq(counter[25]) 56 | m.sync += counter.eq(counter + 1) 57 | plat.build(m) 58 | ``` 59 | 60 | #### License 61 | 62 | Migen is released under the very permissive two-clause BSD license. Under the 63 | terms of this license, you are authorized to use Migen for closed-source 64 | proprietary designs. 65 | Even though we do not require you to do so, those things are awesome, so please 66 | do them if possible: 67 | * tell us that you are using Migen 68 | * put the Migen logo (doc/migen_logo.svg) on the page of a product using it, 69 | with a link to http://m-labs.hk 70 | * cite Migen in publications related to research it has helped 71 | * send us feedback and suggestions for improvements 72 | * send us bug reports when something goes wrong 73 | * send us the modifications and improvements you have done to Migen. The use 74 | of "git format-patch" is recommended. If your submission is large and 75 | complex and/or you are not sure how to proceed, feel free to discuss it on 76 | the mailing list or IRC (#m-labs on Freenode) beforehand. 77 | 78 | See LICENSE file for full copyright and license info. You can contact us on the 79 | public mailing list devel [AT] lists.m-labs.hk. 80 | 81 | "Electricity! It's like magic!" 82 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line. 5 | SPHINXOPTS = 6 | SPHINXBUILD = sphinx-build 7 | PAPER = 8 | BUILDDIR = _build 9 | 10 | # Internal variables. 11 | PAPEROPT_a4 = -D latex_paper_size=a4 12 | PAPEROPT_letter = -D latex_paper_size=letter 13 | ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) . 14 | 15 | .PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest 16 | 17 | help: 18 | @echo "Please use \`make ' where is one of" 19 | @echo " html to make standalone HTML files" 20 | @echo " dirhtml to make HTML files named index.html in directories" 21 | @echo " singlehtml to make a single large HTML file" 22 | @echo " pickle to make pickle files" 23 | @echo " json to make JSON files" 24 | @echo " htmlhelp to make HTML files and a HTML help project" 25 | @echo " qthelp to make HTML files and a qthelp project" 26 | @echo " devhelp to make HTML files and a Devhelp project" 27 | @echo " epub to make an epub" 28 | @echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter" 29 | @echo " latexpdf to make LaTeX files and run them through pdflatex" 30 | @echo " text to make text files" 31 | @echo " man to make manual pages" 32 | @echo " changes to make an overview of all changed/added/deprecated items" 33 | @echo " linkcheck to check all external links for integrity" 34 | @echo " doctest to run all doctests embedded in the documentation (if enabled)" 35 | 36 | clean: 37 | -rm -rf $(BUILDDIR)/* 38 | 39 | html: 40 | $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html 41 | @echo 42 | @echo "Build finished. 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This results in more elegant and easily maintained designs and reduces the incidence of human errors. 7 | 8 | .. _background: 9 | 10 | Background 11 | ********** 12 | 13 | Even though the Milkymist system-on-chip [mm]_ had many successes, it suffers from several limitations stemming from its implementation in manually written Verilog HDL: 14 | 15 | .. [mm] https://m-labs.hk/gateware/m1/ 16 | 17 | #. The "event-driven" paradigm of today's dominant hardware descriptions languages (Verilog and VHDL, collectively referred to as "V*HDL" in the rest of this document) is often too general. Today's FPGA architectures are optimized for the implementation of fully synchronous circuits. This means that the bulk of the code for an efficient FPGA design falls into three categories: 18 | 19 | #. Combinatorial statements 20 | #. Synchronous statements 21 | #. Initialization of registers at reset 22 | 23 | V*HDL do not follow this organization. This means that a lot of repetitive manual coding is needed, which brings sources of human errors, petty issues, and confusion for beginners: 24 | 25 | #. wire vs. reg in Verilog 26 | #. forgetting to initialize a register at reset 27 | #. deciding whether a combinatorial statement must go into a process/always block or not 28 | #. simulation mismatches with combinatorial processes/always blocks 29 | #. and more... 30 | 31 | A little-known fact about FPGAs is that many of them have the ability to initialize their registers from the bitstream contents. This can be done in a portable and standard way using an "initial" block in Verilog, and by affecting a value at the signal declaration in VHDL. This renders an explicit reset signal unnecessary in practice in some cases, which opens the way for further design optimization. However, this form of initialization is entirely not synthesizable for ASIC targets, and it is not easy to switch between the two forms of reset using V*HDL. 32 | 33 | #. V*HDL support for composite types is very limited. Signals having a record type in VHDL are unidirectional, which makes them clumsy to use e.g. in bus interfaces. There is no record type support in Verilog, which means that a lot of copy-and-paste has to be done when forwarding grouped signals. 34 | 35 | #. V*HDL support for procedurally generated logic is extremely limited. The most advanced forms of procedural generation of synthesizable logic that V*HDL offers are CPP-style directives in Verilog, combinatorial functions, and ``generate`` statements. Nothing really fancy, and it shows. To give a few examples: 36 | 37 | #. Building highly flexible bus interconnect is not possible. Even arbitrating any given number of bus masters for commonplace protocols such as Wishbone is difficult with the tools that V*HDL puts at our disposal. 38 | #. Building a memory infrastructure (including bus interconnect, bridges and caches) that can automatically adapt itself at compile-time to any word size of the SDRAM is clumsy and tedious. 39 | #. Building register banks for control, status and interrupt management of cores can also largely benefit from automation. 40 | #. Many hardware acceleration problems can fit into the dataflow programming model. Manual dataflow implementation in V*HDL has, again, a lot of redundancy and potential for human errors. See the Milkymist texture mapping unit [mthesis]_ [mxcell]_ for an example of this. The amount of detail to deal with manually also makes the design space exploration difficult, and therefore hinders the design of efficient architectures. 41 | #. Pre-computation of values, such as filter coefficients for DSP or even simply trigonometric tables, must often be done using external tools whose results are copy-and-pasted (in the best case, automatically) into the V*HDL source. 42 | 43 | .. [mthesis] https://m-labs.hk/thesis/thesis.pdf 44 | .. [mxcell] https://www.xilinx.com/publications/archives/xcell/Xcell77.pdf p30-35 45 | 46 | Enter Migen, a Python toolbox for building complex digital hardware. We could have designed a brand new programming language, but that would have been reinventing the wheel instead of being able to benefit from Python's rich features and immense library. The price to pay is a slightly cluttered syntax at times when writing descriptions in FHDL, but we believe this is totally acceptable, particularly when compared to VHDL ;-) 47 | 48 | Migen is made up of several related components: 49 | 50 | #. the base language, FHDL 51 | #. a library of small generic cores 52 | #. a simulator 53 | #. a build system 54 | 55 | Installing Migen 56 | **************** 57 | 58 | Either run ``python3 -m pip install .`` or simply set ``PYTHONPATH`` to the root of the source directory. 59 | 60 | If you wish to contribute patches, the suggested way to install is; 61 | #. Clone from the git repository at https://github.com/m-labs/migen 62 | #. Install using the ``-e`` pip option, or set ``PYTHONPATH`` to the root of the checked-out directory. 63 | #. Edit the code in your git checkout. 64 | 65 | Alternative install methods 66 | =========================== 67 | 68 | * Migen is available for the Anaconda Python distribution. The package can be found at at https://anaconda.org/m-labs/migen 69 | * Migen can be referenced in a requirements.txt file (used for ``pip install -r requirements.txt``) via ``-e git+https://github.com/m-labs/migen.git#egg=migen``. See the pip documentation for more information. 70 | 71 | Feedback 72 | ******** 73 | Feedback concerning Migen or this manual should be sent to the M-Labs forum at https://forum.m-labs.hk or in GitHub issues. 74 | -------------------------------------------------------------------------------- /doc/migen_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/m-labs/migen/b92717a918c4d274d37f6eaff0c57ad689468173/doc/migen_logo.png -------------------------------------------------------------------------------- /doc/migen_logo_white.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/m-labs/migen/b92717a918c4d274d37f6eaff0c57ad689468173/doc/migen_logo_white.png -------------------------------------------------------------------------------- /doc/reference.rst: -------------------------------------------------------------------------------- 1 | API reference 2 | ============= 3 | 4 | :mod:`fhdl.structure` module 5 | ---------------------------- 6 | 7 | .. automodule:: migen.fhdl.structure 8 | :members: 9 | :show-inheritance: 10 | 11 | :mod:`fhdl.bitcontainer` module 12 | ------------------------------- 13 | 14 | .. automodule:: migen.fhdl.bitcontainer 15 | :members: 16 | :show-inheritance: 17 | 18 | :mod:`genlib.fifo` module 19 | ------------------------- 20 | 21 | .. automodule:: migen.genlib.fifo 22 | :members: 23 | :show-inheritance: 24 | 25 | :mod:`genlib.coding` module 26 | --------------------------- 27 | 28 | .. automodule:: migen.genlib.coding 29 | :members: 30 | :show-inheritance: 31 | 32 | :mod:`genlib.sort` module 33 | ------------------------- 34 | 35 | .. automodule:: migen.genlib.sort 36 | :members: 37 | :show-inheritance: 38 | 39 | :mod:`genlib.fsm` module 40 | ------------------------- 41 | 42 | .. automodule:: migen.genlib.fsm 43 | :members: 44 | :show-inheritance: 45 | -------------------------------------------------------------------------------- /doc/requirements.txt: -------------------------------------------------------------------------------- 1 | Pygments 2 | docutils 3 | setuptools 4 | sphinx 5 | sphinx_rtd_theme 6 | -------------------------------------------------------------------------------- /doc/simulation.rst: -------------------------------------------------------------------------------- 1 | Simulating a Migen design 2 | ######################### 3 | 4 | Migen allows you to easily simulate your FHDL design and interface it with arbitrary Python code. The simulator is written in pure Python and interprets the FHDL structure directly without using an external Verilog simulator. 5 | 6 | Migen lets you write testbenches using Python's generator functions. Such testbenches execute concurrently with the FHDL simulator, and communicate with it using the ``yield`` statement. There are four basic patterns: 7 | 8 | #. Reads: the state of the signal at the current time can be queried using ``(yield signal)``; 9 | #. Writes: the state of the signal after the next clock cycle can be set using ``(yield signal.eq(value))``; 10 | #. Clocking: simulation can be advanced by one clock cycle using ``yield``; 11 | #. Composition: control can be transferred to another testbench function using ``yield from run_other()``. 12 | 13 | A testbench can be run using the ``run_simulation`` function from ``migen.sim``; ``run_simulation(dut, bench)`` runs the generator function ``bench`` against the logic defined in an FHDL module ``dut``. 14 | 15 | Passing the ``vcd_name="file.vcd"`` argument to ``run_simulation`` will cause it to write a VCD 16 | dump of the signals inside ``dut`` to ``file.vcd``. 17 | 18 | Examples 19 | ******** 20 | 21 | For example, consider this module:: 22 | 23 | class ORGate(Module): 24 | def __init__(self): 25 | self.a = Signal() 26 | self.b = Signal() 27 | self.x = Signal() 28 | 29 | ### 30 | 31 | self.comb += self.x.eq(self.a | self.b) 32 | 33 | It could be simulated together with the following testbench:: 34 | 35 | dut = ORGate() 36 | 37 | def testbench(): 38 | yield dut.a.eq(0) 39 | yield dut.b.eq(0) 40 | yield 41 | assert (yield dut.x) == 0 42 | 43 | yield dut.a.eq(0) 44 | yield dut.b.eq(1) 45 | yield 46 | assert (yield dut.x) == 1 47 | 48 | run_simulation(dut, testbench()) 49 | 50 | This is, of course, quite verbose, and individual steps can be factored into a separate function:: 51 | 52 | dut = ORGate() 53 | 54 | def check_case(a, b, x): 55 | yield dut.a.eq(a) 56 | yield dut.b.eq(b) 57 | yield 58 | assert (yield dut.x) == x 59 | 60 | def testbench(): 61 | yield from check_case(0, 0, 0) 62 | yield from check_case(0, 1, 1) 63 | yield from check_case(1, 0, 1) 64 | yield from check_case(1, 1, 1) 65 | 66 | run_simulation(dut, testbench()) 67 | 68 | Pitfalls 69 | ******** 70 | 71 | There are, unfortunately, some basic mistakes that can produce very puzzling results. 72 | 73 | When calling other testbenches, it is important to not forget the ``yield from``. If it is omitted, the call would silently do nothing. 74 | 75 | When writing to a signal, it is important that nothing else should drive the signal concurrently. If that is not the case, the write would silently do nothing. 76 | -------------------------------------------------------------------------------- /doc/synthesis.rst: -------------------------------------------------------------------------------- 1 | Synthesizing a Migen design 2 | ########################### 3 | 4 | [To be written] 5 | -------------------------------------------------------------------------------- /examples/basic/arrays.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | 5 | class Example(Module): 6 | def __init__(self): 7 | dx = 2 8 | dy = 2 9 | 10 | x = Signal(max=dx) 11 | y = Signal(max=dy) 12 | out = Signal() 13 | 14 | my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy)) 15 | self.comb += out.eq(my_2d_array[x][y]) 16 | 17 | we = Signal() 18 | inp = Signal() 19 | self.sync += If(we, 20 | my_2d_array[x][y].eq(inp) 21 | ) 22 | 23 | ina = Array(Signal() for a in range(dx)) 24 | outa = Array(Signal() for a in range(dy)) 25 | self.specials += Instance("test", o_O=outa[y], i_I=ina[x]) 26 | 27 | if __name__ == "__main__": 28 | print(verilog.convert(Example())) 29 | -------------------------------------------------------------------------------- /examples/basic/fsm.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | class Example(Module): 5 | def __init__(self): 6 | self.s = Signal() 7 | self.counter = Signal(8) 8 | x = Array(Signal(name="a") for i in range(7)) 9 | 10 | myfsm = FSM() 11 | self.submodules += myfsm 12 | 13 | myfsm.act("FOO", 14 | self.s.eq(1), 15 | NextState("BAR") 16 | ) 17 | myfsm.act("BAR", 18 | self.s.eq(0), 19 | NextValue(self.counter, self.counter + 1), 20 | NextValue(x[self.counter], 89), 21 | NextState("FOO") 22 | ) 23 | 24 | self.be = myfsm.before_entering("FOO") 25 | self.ae = myfsm.after_entering("FOO") 26 | self.bl = myfsm.before_leaving("FOO") 27 | self.al = myfsm.after_leaving("FOO") 28 | 29 | if __name__ == "__main__": 30 | example = Example() 31 | print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al})) 32 | -------------------------------------------------------------------------------- /examples/basic/graycounter.py: -------------------------------------------------------------------------------- 1 | from random import Random 2 | 3 | from migen import * 4 | from migen.genlib.cdc import GrayCounter 5 | 6 | 7 | def tb(dut): 8 | prng = Random(7345) 9 | for i in range(35): 10 | print("{0:0{1}b} CE={2} bin={3}".format((yield dut.q), 11 | len(dut.q), (yield dut.ce), (yield dut.q_binary))) 12 | yield dut.ce.eq(prng.getrandbits(1)) 13 | yield 14 | 15 | 16 | if __name__ == "__main__": 17 | dut = GrayCounter(3) 18 | run_simulation(dut, tb(dut), vcd_name="graycounter.vcd") 19 | -------------------------------------------------------------------------------- /examples/basic/instance.py: -------------------------------------------------------------------------------- 1 | import subprocess 2 | 3 | from migen import * 4 | from migen.fhdl.verilog import convert 5 | 6 | 7 | # Create a parent module with two instances of a child module. 8 | # Bind input ports to first module and output ports to second, 9 | # and create internal signals to connect the first module to the 10 | # second. 11 | class ParentModule(Module): 12 | def __init__(self): 13 | self.inputs = [Signal(x+1, name="input{}".format(x)) for x in range(4)] 14 | self.trans = [Signal(x+1) for x in range(4)] 15 | self.outputs = [Signal(x+1, name="output{}".format(x)) for x in range(4)] 16 | self.io = set(self.inputs) | set(self.outputs) 17 | i = Instance("ChildModule", 18 | i_master_clk=ClockSignal(), 19 | i_master_rst=ResetSignal(), 20 | i_input0=self.inputs[0], 21 | i_input1=self.inputs[1], 22 | i_input2=self.inputs[2], 23 | i_input3=self.inputs[3], 24 | o_output0=self.trans[0], 25 | o_output1=self.trans[1], 26 | o_output2=self.trans[2], 27 | o_output3=self.trans[3] 28 | ) 29 | j = Instance("ChildModule", 30 | i_master_clk=ClockSignal(), 31 | i_master_rst=ResetSignal(), 32 | i_input0=self.trans[0], 33 | i_input1=self.trans[1], 34 | i_input2=self.trans[2], 35 | i_input3=self.trans[3], 36 | o_output0=self.outputs[0], 37 | o_output1=self.outputs[1], 38 | o_output2=self.outputs[2], 39 | o_output3=self.outputs[3] 40 | ) 41 | self.specials += i, j 42 | 43 | 44 | class ChildModule(Module): 45 | def __init__(self): 46 | self.inputs = [Signal(x+1, name_override="input{}".format(x)) for x in range(4)] 47 | self.outputs = [Signal(x+1, name_override="output{}".format(x)) for x in range(4)] 48 | self.io = set() 49 | for x in range(4): 50 | self.sync.master += self.outputs[x].eq(self.inputs[x]) 51 | self.io = self.io.union(self.inputs) 52 | self.io = self.io.union(self.outputs) 53 | 54 | 55 | # Generate RTL for the parent module and the submodule, run through 56 | # icarus for a syntax check 57 | def test_instance_module(): 58 | sub = ChildModule() 59 | convert(sub, sub.io, name="ChildModule").write("ChildModule.v") 60 | 61 | im = ParentModule() 62 | convert(im, im.io, name="ParentModule").write("ParentModule.v") 63 | 64 | subprocess.check_call(["iverilog", "-W", "all", 65 | "ParentModule.v", "ChildModule.v"]) 66 | 67 | if __name__ == "__main__": 68 | test_instance_module() 69 | -------------------------------------------------------------------------------- /examples/basic/local_cd.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | from migen.genlib.divider import Divider 4 | 5 | 6 | class CDM(Module): 7 | def __init__(self): 8 | self.submodules.divider = Divider(5) 9 | self.clock_domains.cd_sys = ClockDomain(reset_less=True) 10 | 11 | 12 | class MultiMod(Module): 13 | def __init__(self): 14 | self.submodules.foo = CDM() 15 | self.submodules.bar = CDM() 16 | 17 | if __name__ == "__main__": 18 | mm = MultiMod() 19 | print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk})) 20 | -------------------------------------------------------------------------------- /examples/basic/memory.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | 5 | class Example(Module): 6 | def __init__(self): 7 | self.specials.mem = Memory(32, 100, init=[5, 18, 32]) 8 | p1 = self.mem.get_port(write_capable=True, we_granularity=8) 9 | p2 = self.mem.get_port(has_re=True, clock_domain="rd") 10 | self.specials += p1, p2 11 | self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w, 12 | p2.adr, p2.dat_r, p2.re} 13 | 14 | 15 | if __name__ == "__main__": 16 | example = Example() 17 | print(verilog.convert(example, example.ios)) 18 | -------------------------------------------------------------------------------- /examples/basic/namer.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | from functools import reduce 5 | from operator import or_ 6 | 7 | 8 | def gen_list(n): 9 | s = [Signal() for i in range(n)] 10 | return s 11 | 12 | 13 | def gen_2list(n): 14 | s = [Signal(2) for i in range(n)] 15 | return s 16 | 17 | 18 | class Foo: 19 | def __init__(self): 20 | la = gen_list(3) 21 | lb = gen_2list(2) 22 | self.sigs = la + lb 23 | 24 | 25 | class Bar: 26 | def __init__(self): 27 | self.sigs = gen_list(2) 28 | 29 | 30 | class Example(Module): 31 | def __init__(self): 32 | a = [Bar() for x in range(3)] 33 | b = [Foo() for x in range(3)] 34 | c = b 35 | b = [Bar() for x in range(2)] 36 | 37 | output = Signal() 38 | allsigs = [] 39 | for lst in [a, b, c]: 40 | for obj in lst: 41 | allsigs.extend(obj.sigs) 42 | self.comb += output.eq(reduce(or_, allsigs)) 43 | 44 | print(verilog.convert(Example())) 45 | -------------------------------------------------------------------------------- /examples/basic/psync.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.build.xilinx.common import XilinxMultiReg 3 | from migen.build.xilinx.vivado import XilinxVivadoToolchain 4 | from migen.fhdl import verilog 5 | from migen.genlib.cdc import * 6 | 7 | if __name__ == "__main__": 8 | ps = PulseSynchronizer("from", "to") 9 | v = verilog.convert(ps, {ps.i, ps.o}, 10 | special_overrides={MultiReg: XilinxMultiReg}, 11 | attr_translate=XilinxVivadoToolchain.attr_translate) 12 | print(v) 13 | -------------------------------------------------------------------------------- /examples/basic/record.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | 5 | L = [ 6 | ("position", [ 7 | ("x", 10, DIR_M_TO_S), 8 | ("y", 10, DIR_M_TO_S), 9 | ]), 10 | ("color", 32, DIR_M_TO_S), 11 | ("stb", 1, DIR_M_TO_S), 12 | ("ack", 1, DIR_S_TO_M) 13 | ] 14 | 15 | 16 | class Test(Module): 17 | def __init__(self): 18 | master = Record(L) 19 | slave = Record(L) 20 | self.comb += master.connect(slave) 21 | 22 | 23 | if __name__ == "__main__": 24 | print(verilog.convert(Test())) 25 | print(layout_len(L)) 26 | print(layout_partial(L, "position/x", "color")) 27 | -------------------------------------------------------------------------------- /examples/basic/reslice.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | 5 | class Example(Module): 6 | def __init__(self): 7 | a = Signal(3) 8 | b = Signal(4) 9 | c = Signal(5) 10 | d = Signal(7) 11 | s1 = c[:3][:2] 12 | s2 = Cat(a, b)[:6] 13 | s3 = Cat(s1, s2)[-5:] 14 | self.comb += s3.eq(0) 15 | self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3])) 16 | 17 | 18 | if __name__ == "__main__": 19 | print(verilog.convert(Example())) 20 | -------------------------------------------------------------------------------- /examples/basic/tristate.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | 5 | class Example(Module): 6 | def __init__(self, n=6): 7 | self.pad = Signal(n) 8 | self.t = TSTriple(n) 9 | self.specials += self.t.get_tristate(self.pad) 10 | 11 | if __name__ == "__main__": 12 | e = Example() 13 | print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i})) 14 | -------------------------------------------------------------------------------- /examples/basic/two_dividers.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | from migen.genlib import divider 4 | 5 | 6 | @ResetInserter() 7 | @CEInserter() 8 | class Example(Module): 9 | def __init__(self, width): 10 | d1 = divider.Divider(width) 11 | d2 = divider.Divider(width) 12 | self.submodules += d1, d2 13 | self.ios = { 14 | d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i, 15 | d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i} 16 | 17 | if __name__ == "__main__": 18 | example = Example(16) 19 | print(verilog.convert(example, example.ios | {example.ce, example.reset})) 20 | -------------------------------------------------------------------------------- /examples/sim/basic1.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | 3 | 4 | # Our simple counter, which increments at every cycle. 5 | class Counter(Module): 6 | def __init__(self): 7 | self.count = Signal(4) 8 | 9 | # At each cycle, increase the value of the count signal. 10 | # We do it with convertible/synthesizable FHDL code. 11 | self.sync += self.count.eq(self.count + 1) 12 | 13 | 14 | # Simply read the count signal and print it. 15 | # The output is: 16 | # Count: 0 17 | # Count: 1 18 | # Count: 2 19 | # ... 20 | def counter_test(dut): 21 | for i in range(20): 22 | print((yield dut.count)) # read and print 23 | yield # next clock cycle 24 | # simulation ends with this generator 25 | 26 | 27 | if __name__ == "__main__": 28 | dut = Counter() 29 | run_simulation(dut, counter_test(dut), vcd_name="basic1.vcd") 30 | -------------------------------------------------------------------------------- /examples/sim/basic2.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | 3 | 4 | # A slightly more elaborate counter. 5 | # Has a clock enable (CE) signal, counts on more bits 6 | # and resets with a negative number. 7 | class Counter(Module): 8 | def __init__(self): 9 | self.ce = Signal() 10 | # Demonstrate negative numbers and signals larger than 32 bits. 11 | self.count = Signal((37, True), reset=-5) 12 | 13 | self.sync += If(self.ce, self.count.eq(self.count + 1)) 14 | 15 | 16 | def counter_test(dut): 17 | for cycle in range(20): 18 | # Only assert CE every second cycle. 19 | # => each counter value is held for two cycles. 20 | if cycle % 2: 21 | yield dut.ce.eq(0) # This is how you write to a signal. 22 | else: 23 | yield dut.ce.eq(1) 24 | print("Cycle: {} Count: {}".format(cycle, (yield dut.count))) 25 | yield 26 | 27 | # Output is: 28 | # Cycle: 0 Count: -5 29 | # Cycle: 1 Count: -5 30 | # Cycle: 2 Count: -4 31 | # Cycle: 3 Count: -4 32 | # Cycle: 4 Count: -3 33 | # ... 34 | 35 | if __name__ == "__main__": 36 | dut = Counter() 37 | run_simulation(dut, counter_test(dut), vcd_name="basic2.vcd") 38 | -------------------------------------------------------------------------------- /examples/sim/display.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | 3 | 4 | class DisplayTest(Module): 5 | def __init__(self): 6 | count = Signal(8) 7 | self.sync += count.eq(count + 1) 8 | self.sync += Display("Count: 0x%02x", count) 9 | 10 | 11 | def generator(dut): 12 | for i in range(32): 13 | yield 14 | 15 | if __name__ == "__main__": 16 | dut = DisplayTest() 17 | run_simulation(dut, generator(dut)) 18 | -------------------------------------------------------------------------------- /examples/sim/fir.py: -------------------------------------------------------------------------------- 1 | from functools import reduce 2 | from operator import add 3 | 4 | from math import cos, pi 5 | from scipy import signal 6 | import matplotlib.pyplot as plt 7 | 8 | from migen import * 9 | from migen.fhdl import verilog 10 | 11 | 12 | # A synthesizable FIR filter. 13 | class FIR(Module): 14 | def __init__(self, coef, wsize=16): 15 | self.coef = coef 16 | self.wsize = wsize 17 | self.i = Signal((self.wsize, True)) 18 | self.o = Signal((self.wsize, True)) 19 | 20 | ### 21 | 22 | muls = [] 23 | src = self.i 24 | for c in self.coef: 25 | sreg = Signal((self.wsize, True)) 26 | self.sync += sreg.eq(src) 27 | src = sreg 28 | c_fp = int(c*2**(self.wsize - 1)) 29 | muls.append(c_fp*sreg) 30 | sum_full = Signal((2*self.wsize-1, True)) 31 | self.sync += sum_full.eq(reduce(add, muls)) 32 | self.comb += self.o.eq(sum_full >> self.wsize-1) 33 | 34 | 35 | # A test bench for our FIR filter. 36 | # Generates a sine wave at the input and records the output. 37 | def fir_tb(dut, frequency, inputs, outputs): 38 | f = 2**(dut.wsize - 1) 39 | for cycle in range(200): 40 | v = 0.1*cos(2*pi*frequency*cycle) 41 | yield dut.i.eq(int(f*v)) 42 | inputs.append(v) 43 | outputs.append((yield dut.o)/f) 44 | yield 45 | 46 | 47 | if __name__ == "__main__": 48 | # Compute filter coefficients with SciPy. 49 | coef = signal.remez(30, [0, 0.1, 0.2, 0.4, 0.45, 0.5], [0, 1, 0]) 50 | 51 | # Simulate for different frequencies and concatenate 52 | # the results. 53 | in_signals = [] 54 | out_signals = [] 55 | for frequency in [0.05, 0.1, 0.25]: 56 | dut = FIR(coef) 57 | tb = fir_tb(dut, frequency, in_signals, out_signals) 58 | run_simulation(dut, tb) 59 | 60 | # Plot data from the input and output waveforms. 61 | plt.plot(in_signals) 62 | plt.plot(out_signals) 63 | plt.show() 64 | 65 | # Print the Verilog source for the filter. 66 | fir = FIR(coef) 67 | print(verilog.convert(fir, ios={fir.i, fir.o})) 68 | -------------------------------------------------------------------------------- /examples/sim/memory.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | 3 | 4 | class Mem(Module): 5 | def __init__(self): 6 | # Initialize the beginning of the memory with integers 7 | # from 0 to 19. 8 | self.specials.mem = Memory(16, 2**12, init=list(range(20))) 9 | 10 | 11 | def memory_test(dut): 12 | # write (only first 5 values) 13 | for i in range(5): 14 | yield dut.mem[i].eq(42 + i) 15 | # remember: values are written after the tick, and read before the tick. 16 | # wait one tick for the memory to update. 17 | yield 18 | # read what we have written, plus some initialization data 19 | for i in range(10): 20 | value = yield dut.mem[i] 21 | print(value) 22 | 23 | 24 | if __name__ == "__main__": 25 | dut = Mem() 26 | run_simulation(dut, memory_test(dut)) 27 | -------------------------------------------------------------------------------- /migen/__init__.py: -------------------------------------------------------------------------------- 1 | from migen.fhdl.structure import * 2 | from migen.fhdl.module import * 3 | from migen.fhdl.specials import * 4 | from migen.fhdl.bitcontainer import * 5 | from migen.fhdl.decorators import * 6 | from migen.fhdl.simplify import * 7 | 8 | from migen.sim import * 9 | 10 | from migen.genlib.record import * 11 | from migen.genlib.fsm import * 12 | -------------------------------------------------------------------------------- /migen/build/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/m-labs/migen/b92717a918c4d274d37f6eaff0c57ad689468173/migen/build/__init__.py -------------------------------------------------------------------------------- /migen/build/altera/__init__.py: -------------------------------------------------------------------------------- 1 | from migen.build.altera.platform import AlteraPlatform 2 | from migen.build.altera.programmer import USBBlaster 3 | -------------------------------------------------------------------------------- /migen/build/altera/common.py: -------------------------------------------------------------------------------- 1 | from migen.fhdl.module import Module 2 | from migen.fhdl.specials import Instance 3 | from migen.genlib.io import DifferentialInput, DifferentialOutput 4 | 5 | 6 | class AlteraDifferentialInputImpl(Module): 7 | def __init__(self, i_p, i_n, o): 8 | self.specials += Instance("ALT_INBUF_DIFF", 9 | name="ibuf_diff", 10 | i_i=i_p, 11 | i_ibar=i_n, 12 | o_o=o) 13 | 14 | 15 | class AlteraDifferentialInput: 16 | @staticmethod 17 | def lower(dr): 18 | return AlteraDifferentialInputImpl(dr.i_p, dr.i_n, dr.o) 19 | 20 | 21 | class AlteraDifferentialOutputImpl(Module): 22 | def __init__(self, i, o_p, o_n): 23 | self.specials += Instance("ALT_OUTBUF_DIFF", 24 | name="obuf_diff", 25 | i_i=i, 26 | o_o=o_p, 27 | o_obar=o_n) 28 | 29 | 30 | class AlteraDifferentialOutput: 31 | @staticmethod 32 | def lower(dr): 33 | return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) 34 | 35 | 36 | altera_special_overrides = { 37 | DifferentialInput: AlteraDifferentialInput, 38 | DifferentialOutput: AlteraDifferentialOutput 39 | } 40 | -------------------------------------------------------------------------------- /migen/build/altera/platform.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import GenericPlatform 2 | from migen.build.altera import common, quartus 3 | 4 | 5 | class AlteraPlatform(GenericPlatform): 6 | bitstream_ext = ".sof" 7 | create_rbf = True 8 | 9 | def __init__(self, *args, toolchain="quartus", **kwargs): 10 | GenericPlatform.__init__(self, *args, **kwargs) 11 | if toolchain == "quartus": 12 | self.toolchain = quartus.AlteraQuartusToolchain() 13 | else: 14 | raise ValueError("Unknown toolchain") 15 | 16 | def get_verilog(self, *args, special_overrides=dict(), **kwargs): 17 | so = dict(common.altera_special_overrides) 18 | so.update(special_overrides) 19 | return GenericPlatform.get_verilog(self, *args, special_overrides=so, 20 | **kwargs) 21 | 22 | def build(self, *args, **kwargs): 23 | return self.toolchain.build(self, *args, **kwargs) 24 | 25 | def add_period_constraint(self, clk, period): 26 | if hasattr(clk, "p"): 27 | clk = clk.p 28 | self.toolchain.add_period_constraint(self, clk, period) 29 | -------------------------------------------------------------------------------- /migen/build/altera/programmer.py: -------------------------------------------------------------------------------- 1 | import subprocess 2 | 3 | from migen.build.generic_programmer import GenericProgrammer 4 | 5 | 6 | class USBBlaster(GenericProgrammer): 7 | needs_bitreverse = False 8 | 9 | def __init__(self, cable_name="USB-Blaster", device_id=1): 10 | self.cable_name = cable_name 11 | self.device_id = device_id 12 | 13 | def load_bitstream(self, bitstream_file, cable_suffix=""): 14 | subprocess.call(["quartus_pgm", "-m", "jtag", "-c", 15 | "{}{}".format(self.cable_name, cable_suffix), "-o", 16 | "p;{}@{}".format(bitstream_file, self.device_id)]) 17 | -------------------------------------------------------------------------------- /migen/build/fpgalink_programmer.py: -------------------------------------------------------------------------------- 1 | import os 2 | 3 | from migen.build.generic_programmer import GenericProgrammer 4 | from migen.build.xilinx.programmer import _create_xsvf 5 | 6 | try: 7 | import fl 8 | except ImportError: 9 | import fpgalink3 as fl 10 | 11 | fl.flInitialise(0) 12 | 13 | 14 | class FPGALink(GenericProgrammer): 15 | """Using the fpgalink library from makestuff 16 | 17 | You will need fpgalink library installed from 18 | https://github.com/makestuff/libfpgalink 19 | """ 20 | 21 | needs_bitreverse = False 22 | 23 | def __init__(self, initial_vidpid=None, pin_cfg="D0D2D3D4", 24 | fpgalink_vidpid="1D50:602B:0002", flash_proxy_basename=None): 25 | """ 26 | Parameters 27 | ---------- 28 | initial_vidpid : string 29 | The USB vendor and product id of the device before fpgalink 30 | firmware is loaded onto the device. 31 | 32 | Format is vid:pid as 4 digit hex numbers. 33 | 34 | pin_cfg : string 35 | FPGALink pin configuration string describing how the JTAG interface 36 | is hooked up to the programmer. 37 | 38 | fpgalink_vidpid : string 39 | The USB vendor, product and device id of the device after the 40 | fpgalink firmware is loaded onto the device. 41 | 42 | Format is vid:pid:did as 4 digit hex numbers. 43 | Defaults to 1D50:602B:0002 which is the makestuff FPGALink device. 44 | """ 45 | GenericProgrammer.__init__(self, flash_proxy_basename) 46 | self.initial_vidpid = initial_vidpid 47 | self.fpgalink_vidpid = fpgalink_vidpid 48 | self.pin_cfg = pin_cfg 49 | 50 | def open_device(self): 51 | ivp = self.initial_vidpid 52 | vp = self.fpgalink_vidpid 53 | 54 | print("Attempting to open connection to FPGALink device", vp, "...") 55 | try: 56 | handle = fl.flOpen(self.fpgalink_vidpid) 57 | except fl.FLException as ex: 58 | if not ivp: 59 | raise FLException( 60 | "Could not open FPGALink device at {0} and" 61 | " no initial VID:PID was supplied".format(vp)) 62 | 63 | print("Loading firmware into %s..." % ivp) 64 | fl.flLoadStandardFirmware(ivp, vp) 65 | 66 | print("Awaiting renumeration...") 67 | if not fl.flAwaitDevice(vp, 600): 68 | raise fl.FLException( 69 | "FPGALink device did not renumerate properly" 70 | " as {0}".format(vp)) 71 | 72 | print("Attempting to open connection to FPGALink device", vp, 73 | "again...") 74 | handle = fl.flOpen(vp) 75 | 76 | # Only Nero capable hardware support doing programming. 77 | assert fl.flIsNeroCapable(handle) 78 | print("Cable connection opened.") 79 | return handle 80 | 81 | def load_bitstream(self, bitstream_file): 82 | n = 27 83 | 84 | xsvf_file = os.path.splitext(bitstream_file)[0]+'.xsvf' 85 | print("\nGenerating xsvf formatted bitstream") 86 | print("="*n) 87 | if os.path.exists(xsvf_file): 88 | os.unlink(xsvf_file) 89 | _create_xsvf(bitstream_file, xsvf_file) 90 | print("\n"+"="*n+"\n") 91 | 92 | print("Programming %s to device." % xsvf_file) 93 | print("="*n) 94 | handle = self.open_device() 95 | print("Programming device...") 96 | fl.flProgram(handle, "J:"+self.pin_cfg, progFile=xsvf_file) 97 | print("Programming successful!") 98 | print("="*n+"\n") 99 | fl.flClose(handle) 100 | 101 | def flash(self, address, data_file): 102 | raise NotImplementedError("Not supported yet.") 103 | -------------------------------------------------------------------------------- /migen/build/generic_programmer.py: -------------------------------------------------------------------------------- 1 | import os, sys 2 | from migen.build import tools 3 | 4 | 5 | class GenericProgrammer: 6 | def __init__(self, flash_proxy_basename=None): 7 | self.flash_proxy_basename = flash_proxy_basename 8 | self.flash_proxy_dirs = [ 9 | "~/.migen", "/usr/local/share/migen", "/usr/share/migen", 10 | "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs"] 11 | 12 | def set_flash_proxy_dir(self, flash_proxy_dir): 13 | if flash_proxy_dir is not None: 14 | self.flash_proxy_dirs = [flash_proxy_dir] 15 | 16 | def find_flash_proxy(self): 17 | for d in self.flash_proxy_dirs: 18 | fulldir = os.path.abspath(os.path.expanduser(d)) 19 | fullname = os.path.join(fulldir, self.flash_proxy_basename) 20 | if os.path.exists(fullname): 21 | return fullname 22 | raise OSError("Failed to find flash proxy bitstream") 23 | 24 | # must be overloaded by specific programmer 25 | def load_bitstream(self, bitstream_file): 26 | raise NotImplementedError 27 | 28 | # must be overloaded by specific programmer 29 | def flash(self, address, data_file): 30 | raise NotImplementedError 31 | -------------------------------------------------------------------------------- /migen/build/lattice/__init__.py: -------------------------------------------------------------------------------- 1 | from migen.build.lattice.platform import LatticePlatform 2 | from migen.build.lattice.programmer import LatticeProgrammer 3 | -------------------------------------------------------------------------------- /migen/build/lattice/platform.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import GenericPlatform 2 | from migen.build.lattice import common, diamond, icestorm, trellis 3 | 4 | 5 | class LatticePlatform(GenericPlatform): 6 | bitstream_ext = ".bit" 7 | 8 | def __init__(self, *args, toolchain="diamond", **kwargs): 9 | GenericPlatform.__init__(self, *args, **kwargs) 10 | if toolchain == "diamond": 11 | self.toolchain = diamond.LatticeDiamondToolchain() 12 | elif toolchain == "trellis": 13 | self.toolchain = trellis.LatticeTrellisToolchain() 14 | elif toolchain == "icestorm": 15 | self.bitstream_ext = ".bin" 16 | self.toolchain = icestorm.LatticeIceStormToolchain() 17 | else: 18 | raise ValueError("Unknown toolchain") 19 | 20 | def get_verilog(self, *args, special_overrides=dict(), **kwargs): 21 | so = dict() # No common overrides between ECP and ice40. 22 | so.update(self.toolchain.special_overrides) 23 | so.update(special_overrides) 24 | return GenericPlatform.get_verilog(self, *args, special_overrides=so, 25 | attr_translate=self.toolchain.attr_translate, 26 | **kwargs) 27 | 28 | def build(self, *args, **kwargs): 29 | return self.toolchain.build(self, *args, **kwargs) 30 | 31 | def add_period_constraint(self, clk, period): 32 | if hasattr(clk, "p"): 33 | clk = clk.p 34 | self.toolchain.add_period_constraint(self, clk, period) 35 | -------------------------------------------------------------------------------- /migen/build/lattice/programmer.py: -------------------------------------------------------------------------------- 1 | import os 2 | import subprocess 3 | 4 | from migen.build.generic_programmer import GenericProgrammer 5 | from migen.build import tools 6 | 7 | 8 | class LatticeProgrammer(GenericProgrammer): 9 | needs_bitreverse = False 10 | 11 | def __init__(self, xcf_template): 12 | self.xcf_template = xcf_template 13 | 14 | def load_bitstream(self, bitstream_file): 15 | xcf_file = bitstream_file.replace(".bit", ".xcf") 16 | xcf_content = self.xcf_template.format(bitstream_file=bitstream_file) 17 | tools.write_to_file(xcf_file, xcf_content) 18 | subprocess.call(["pgrcmd", "-infile", xcf_file]) 19 | 20 | 21 | class IceStormProgrammer(GenericProgrammer): 22 | needs_bitreverse = False 23 | 24 | def flash(self, address, bitstream_file): 25 | subprocess.call(["iceprog", "-o", str(address), bitstream_file]) 26 | 27 | def load_bitstream(self, bitstream_file): 28 | subprocess.call(["iceprog", "-S", bitstream_file]) 29 | 30 | 31 | class IceBurnProgrammer(GenericProgrammer): 32 | def __init__(self, iceburn_path): 33 | GenericProgrammer.__init__(self) 34 | self.iceburn = iceburn_path 35 | 36 | needs_bitreverse = False 37 | 38 | def load_bitstream(self, bitstream_file): 39 | subprocess.call([self.iceburn, "-evw", bitstream_file]) 40 | 41 | 42 | class TinyFpgaBProgrammer(GenericProgrammer): 43 | needs_bitreverse = False 44 | 45 | # The default flash address you probably want is 0x30000; the image at 46 | # address 0 is for the bootloader. 47 | def flash(self, address, bitstream_file): 48 | subprocess.call(["tinyfpgab", "-a", str(address), "-p", 49 | bitstream_file]) 50 | 51 | # Force user image to boot if a user reset tinyfpga, the bootloader 52 | # is active, and the user image need not be reprogrammed. 53 | def boot(self): 54 | subprocess.call(["tinyfpgab", "-b"]) 55 | 56 | 57 | # Different bootloader protocol requires different application. In the basic 58 | # case, command-line arguments are the same. Note that this programmer can 59 | # also be used with TinyFPGA B2 if you have updated its bootloader. 60 | class TinyProgProgrammer(GenericProgrammer): 61 | needs_bitreverse = False 62 | 63 | # You probably want to pass address="None" for this programmer 64 | # unless you know what you're doing. 65 | def flash(self, address, bitstream_file, user_data=False): 66 | if address is None: 67 | if not user_data: 68 | # tinyprog looks at spi flash metadata to figure out where to 69 | # program your bitstream. 70 | subprocess.call(["tinyprog", "-p", bitstream_file]) 71 | else: 72 | # Ditto with user data. 73 | subprocess.call(["tinyprog", "-u", bitstream_file]) 74 | else: 75 | # Provide override so user can program wherever they wish. 76 | subprocess.call(["tinyprog", "-a", str(address), "-p", 77 | bitstream_file]) 78 | 79 | # Force user image to boot if a user reset tinyfpga, the bootloader 80 | # is active, and the user image need not be reprogrammed. 81 | def boot(self): 82 | subprocess.call(["tinyprog", "-b"]) 83 | 84 | 85 | class MyStormProgrammer(GenericProgrammer): 86 | def __init__(self, serial_port): 87 | self.serial_port = serial_port 88 | 89 | def load_bitstream(self, bitstream_file): 90 | import serial 91 | with serial.Serial(self.serial_port) as port: 92 | with open(bitstream_file, "rb") as f: 93 | port.write(f.read()) 94 | -------------------------------------------------------------------------------- /migen/build/openocd.py: -------------------------------------------------------------------------------- 1 | import subprocess 2 | 3 | from migen.build.generic_programmer import GenericProgrammer 4 | 5 | 6 | class OpenOCD(GenericProgrammer): 7 | needs_bitreverse = False 8 | 9 | def __init__(self, config, flash_proxy_basename=None): 10 | GenericProgrammer.__init__(self, flash_proxy_basename) 11 | self.config = config 12 | 13 | def load_bitstream(self, bitstream): 14 | script = "; ".join([ 15 | "init", 16 | "pld load 0 {{{}}}".format(bitstream), 17 | "exit", 18 | ]) 19 | subprocess.call(["openocd", "-f", self.config, "-c", script]) 20 | 21 | def flash(self, address, data): 22 | flash_proxy = self.find_flash_proxy() 23 | script = "; ".join([ 24 | "init", 25 | "jtagspi_init 0 {{{}}}".format(flash_proxy), 26 | "jtagspi_program {{{}}} 0x{:x}".format(data, address), 27 | "fpga_program", 28 | "exit" 29 | ]) 30 | subprocess.call(["openocd", "-f", self.config, "-c", script]) 31 | -------------------------------------------------------------------------------- /migen/build/platforms/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/m-labs/migen/b92717a918c4d274d37f6eaff0c57ad689468173/migen/build/platforms/__init__.py -------------------------------------------------------------------------------- /migen/build/platforms/arty_s7.py: -------------------------------------------------------------------------------- 1 | # This file is Copyright (c) 2018 William D. Jones 2 | # License: BSD 3 | 4 | from migen.build.generic_platform import * 5 | from migen.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer 6 | 7 | _io = [ 8 | ("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")), 9 | ("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")), 10 | ("user_led", 2, Pins("E13"), IOStandard("LVCMOS33")), 11 | ("user_led", 3, Pins("H15"), IOStandard("LVCMOS33")), 12 | 13 | ("rgb_led", 0, 14 | Subsignal("r", Pins("J15")), 15 | Subsignal("g", Pins("G17")), 16 | Subsignal("b", Pins("F15")), 17 | IOStandard("LVCMOS33") 18 | ), 19 | 20 | ("rgb_led", 1, 21 | Subsignal("r", Pins("E15")), 22 | Subsignal("g", Pins("F18")), 23 | Subsignal("b", Pins("E14")), 24 | IOStandard("LVCMOS33") 25 | ), 26 | 27 | ("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")), 28 | ("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")), 29 | ("user_sw", 2, Pins("G18"), IOStandard("LVCMOS33")), 30 | ("user_sw", 3, Pins("M5"), IOStandard("LVCMOS33")), 31 | 32 | ("user_btn", 0, Pins("G15"), IOStandard("LVCMOS33")), 33 | ("user_btn", 1, Pins("K16"), IOStandard("LVCMOS33")), 34 | ("user_btn", 2, Pins("J16"), IOStandard("LVCMOS33")), 35 | ("user_btn", 3, Pins("H13"), IOStandard("LVCMOS33")), 36 | 37 | ("clk100", 0, Pins("R2"), IOStandard("SSTL135")), 38 | 39 | ("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")), 40 | 41 | ("serial", 0, 42 | Subsignal("tx", Pins("R12")), 43 | Subsignal("rx", Pins("V12")), 44 | IOStandard("LVCMOS33")), 45 | 46 | ("spi", 0, 47 | Subsignal("clk", Pins("G16")), 48 | Subsignal("cs_n", Pins("H16")), 49 | Subsignal("mosi", Pins("H17")), 50 | Subsignal("miso", Pins("K14")), 51 | IOStandard("LVCMOS33") 52 | ), 53 | 54 | ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 55 | Subsignal("cs_n", Pins("M13")), 56 | Subsignal("dq", Pins("K17", "K18", "L14", "M15")), 57 | IOStandard("LVCMOS33") 58 | ), 59 | ("spiflash", 0, # clock needs to be accessed through STARTUPE2 60 | Subsignal("cs_n", Pins("M13")), 61 | Subsignal("mosi", Pins("K17")), 62 | Subsignal("miso", Pins("K18")), 63 | Subsignal("wp", Pins("L14")), 64 | Subsignal("hold", Pins("M15")), 65 | IOStandard("LVCMOS33") 66 | ), 67 | 68 | ("ddram", 0, 69 | Subsignal("a", Pins( 70 | "U2 R4 V2 V4 T3 R7 V6 T6", 71 | "U7 V7 P6 T5 R6 U6"), 72 | IOStandard("SSTL135")), 73 | Subsignal("ba", Pins("V5 T1 U3"), IOStandard("SSTL135")), 74 | Subsignal("ras_n", Pins("U1"), IOStandard("SSTL135")), 75 | Subsignal("cas_n", Pins("V3"), IOStandard("SSTL135")), 76 | Subsignal("we_n", Pins("P7"), IOStandard("SSTL135")), 77 | Subsignal("cs_n", Pins("R3"), IOStandard("SSTL135")), 78 | Subsignal("dm", Pins("K4 M3"), IOStandard("SSTL135")), 79 | Subsignal("dq", Pins( 80 | "K2 K3 L4 M6 K6 M4 L5 L6", 81 | "N4 R1 N1 N5 M2 P1 M1 P2"), 82 | IOStandard("SSTL135"), 83 | Misc("IN_TERM=UNTUNED_SPLIT_40")), 84 | Subsignal("dqs_p", Pins("K1 N3"), IOStandard("DIFF_SSTL135")), 85 | Subsignal("dqs_n", Pins("L1 N2"), IOStandard("DIFF_SSTL135")), 86 | Subsignal("clk_p", Pins("R5"), IOStandard("DIFF_SSTL135")), 87 | Subsignal("clk_n", Pins("T4"), IOStandard("DIFF_SSTL135")), 88 | Subsignal("cke", Pins("T2"), IOStandard("SSTL135")), 89 | Subsignal("odt", Pins("P5"), IOStandard("SSTL135")), 90 | Subsignal("reset_n", Pins("J6"), IOStandard("SSTL135")), 91 | Misc("SLEW=FAST"), 92 | ), 93 | 94 | ] 95 | 96 | _connectors = [ 97 | ("pmoda", "L17 L18 M14 N14 M16 M17 M18 N18"), 98 | ("pmodb", "P17 P18 R18 T18 P14 P15 N15 P16"), 99 | ("pmodc", "U15 V16 U17 U18 U16 P13 R13 V14"), 100 | ("pmodd", "V15 U12 V13 T12 T13 R11 T11 U11") 101 | ] 102 | 103 | class Platform(XilinxPlatform): 104 | default_clk_name = "clk100" 105 | default_clk_period = 10.0 106 | 107 | def __init__(self, toolchain="vivado", programmer="vivado"): 108 | XilinxPlatform.__init__(self, "xc7s50csga324-1", _io, _connectors, 109 | toolchain=toolchain) 110 | self.toolchain.bitstream_commands = \ 111 | ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] 112 | self.toolchain.additional_commands = \ 113 | ["write_cfgmem -force -format bin -interface spix4 -size 16 " 114 | "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] 115 | self.programmer = programmer 116 | self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]") 117 | 118 | def create_programmer(self): 119 | if self.programmer == "xc3sprog": 120 | return XC3SProg("nexys4") 121 | elif self.programmer == "vivado": 122 | return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") 123 | else: 124 | raise ValueError("{} programmer is not supported" 125 | .format(self.programmer)) 126 | -------------------------------------------------------------------------------- /migen/build/platforms/coraz7.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.xilinx import XilinxPlatform 3 | 4 | 5 | # https://github.com/Digilent/Cora-Z7-10-base-linux/blob/master/src/constraints/Cora-Z7-10-Master.xdc 6 | _io = [ 7 | ("sys_clk", 0, Pins("H16"), IOStandard("LVCMOS33")), 8 | 9 | # LED0: B, G, R 10 | ("user_led", 0, Pins("L15 G17 N15"), IOStandard("LVCMOS33")), 11 | # LED1: B, G, R 12 | ("user_led", 1, Pins("G14 L14 M15"), IOStandard("LVCMOS33")), 13 | 14 | ("user_btn", 0, Pins("D20"), IOStandard("LVCMOS33")), 15 | ("user_btn", 1, Pins("D19"), IOStandard("LVCMOS33")), 16 | 17 | # A 18 | ("pmod", 0, Pins("Y18 Y19 Y16 Y17 U18 U19 W18 W19"), IOStandard("LVCMOS33")), 19 | # B 20 | ("pmod", 1, Pins("W14 Y14 T11 T10 V16 W16 V12 W13"), IOStandard("LVCMOS33")), 21 | 22 | ("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33")), 23 | 24 | ("user_dio", 1, Pins("L19"), IOStandard("LVCMOS33")), 25 | ("user_dio", 2, Pins("M19"), IOStandard("LVCMOS33")), 26 | ("user_dio", 3, Pins("N20"), IOStandard("LVCMOS33")), 27 | ("user_dio", 4, Pins("P20"), IOStandard("LVCMOS33")), 28 | ("user_dio", 5, Pins("P19"), IOStandard("LVCMOS33")), 29 | ("user_dio", 6, Pins("R19"), IOStandard("LVCMOS33")), 30 | ("user_dio", 7, Pins("T20"), IOStandard("LVCMOS33")), 31 | ("user_dio", 8, Pins("T19"), IOStandard("LVCMOS33")), 32 | ("user_dio", 9, Pins("U20"), IOStandard("LVCMOS33")), 33 | ("user_dio", 10, Pins("V20"), IOStandard("LVCMOS33")), 34 | ("user_dio", 11, Pins("W20"), IOStandard("LVCMOS33")), 35 | ("user_dio", 12, Pins("K19"), IOStandard("LVCMOS33")), 36 | ] 37 | 38 | DEVICE_VARIANTS = { 39 | "07s": "xc7z007s-clg400-1", 40 | "10": "xc7z010-clg400-1", 41 | } 42 | 43 | # Digilent Cora Z7-07S, and Z7-10 44 | class Platform(XilinxPlatform): 45 | default_clk_name = "sys_clk" 46 | default_clk_period = 8 47 | 48 | def __init__(self, device_variant="10"): 49 | device = DEVICE_VARIANTS[device_variant] 50 | XilinxPlatform.__init__(self, device, _io, toolchain="vivado") 51 | -------------------------------------------------------------------------------- /migen/build/platforms/de0cv.py: -------------------------------------------------------------------------------- 1 | # This file is Copyright (c) 2016 Ivan Uvarov 2 | # License: BSD 3 | # 4 | # Note: This file maps only the buttons, switches, LEDs and GPIO headers; 5 | # the actual devboard has much more than that. 6 | 7 | from migen.build.generic_platform import * 8 | from migen.build.altera import AlteraPlatform 9 | from migen.build.altera.programmer import USBBlaster 10 | 11 | 12 | _io = [ 13 | ("clk50", 0, Pins("M9"), IOStandard("3.3-V LVTTL")), 14 | ("clk50", 1, Pins("H13"), IOStandard("3.3-V LVTTL")), 15 | ("clk50", 2, Pins("E10"), IOStandard("3.3-V LVTTL")), 16 | ("clk50", 3, Pins("V15"), IOStandard("3.3-V LVTTL")), 17 | 18 | ("user_led", 0, Pins("AA2"), IOStandard("3.3-V LVTTL")), 19 | ("user_led", 1, Pins("AA1"), IOStandard("3.3-V LVTTL")), 20 | ("user_led", 2, Pins("W2"), IOStandard("3.3-V LVTTL")), 21 | ("user_led", 3, Pins("Y3"), IOStandard("3.3-V LVTTL")), 22 | ("user_led", 4, Pins("N2"), IOStandard("3.3-V LVTTL")), 23 | ("user_led", 5, Pins("N1"), IOStandard("3.3-V LVTTL")), 24 | ("user_led", 6, Pins("U2"), IOStandard("3.3-V LVTTL")), 25 | ("user_led", 7, Pins("U1"), IOStandard("3.3-V LVTTL")), 26 | ("user_led", 8, Pins("L2"), IOStandard("3.3-V LVTTL")), 27 | ("user_led", 9, Pins("L1"), IOStandard("3.3-V LVTTL")), 28 | 29 | 30 | ("seven_seg", 0, Pins("U21 V21 W22 W21 Y22 Y21 AA22"), IOStandard("3.3-V LVTTL")), 31 | ("seven_seg", 1, Pins("AA20 AB20 AA19 AA18 AB18 AA17 U22"), IOStandard("3.3-V LVTTL")), 32 | ("seven_seg", 2, Pins("Y19 AB17 AA10 Y14 V14 AB22 AB21"), IOStandard("3.3-V LVTTL")), 33 | ("seven_seg", 3, Pins("Y16 W16 Y17 V16 U17 V18 V19"), IOStandard("3.3-V LVTTL")), 34 | ("seven_seg", 4, Pins("U20 Y20 V20 U16 U15 Y15 P9"), IOStandard("3.3-V LVTTL")), 35 | ("seven_seg", 5, Pins("N9 M8 T14 P14 C1 C2 W19"), IOStandard("3.3-V LVTTL")), 36 | 37 | 38 | ("key", 0, Pins("U7"), IOStandard("3.3-V LVTTL")), 39 | ("key", 1, Pins("W9"), IOStandard("3.3-V LVTTL")), 40 | ("key", 2, Pins("M7"), IOStandard("3.3-V LVTTL")), 41 | ("key", 3, Pins("M6"), IOStandard("3.3-V LVTTL")), 42 | 43 | ("sw", 0, Pins("U13"), IOStandard("3.3-V LVTTL")), 44 | ("sw", 1, Pins("V13"), IOStandard("3.3-V LVTTL")), 45 | ("sw", 2, Pins("T13"), IOStandard("3.3-V LVTTL")), 46 | ("sw", 3, Pins("T12"), IOStandard("3.3-V LVTTL")), 47 | ("sw", 4, Pins("AA15"), IOStandard("3.3-V LVTTL")), 48 | ("sw", 5, Pins("AB15"), IOStandard("3.3-V LVTTL")), 49 | ("sw", 6, Pins("AA14"), IOStandard("3.3-V LVTTL")), 50 | ("sw", 7, Pins("AA13"), IOStandard("3.3-V LVTTL")), 51 | ("sw", 8, Pins("AB13"), IOStandard("3.3-V LVTTL")), 52 | ("sw", 9, Pins("AB12"), IOStandard("3.3-V LVTTL")), 53 | 54 | 55 | ("gpio_0", 0, 56 | Pins("N16 B16 M16 C16 D17 K20 K21 K22 M20 M21 N21 R22 R21 T22 N20 N19 M22 P19 L22 P17 P16 M18 L18 L17 L19 K17 K19 P18 R15 R17 R16 T20 T19 T18 T17 T15"), 57 | IOStandard("3.3-V LVTTL") 58 | ), 59 | ("gpio_1", 0, 60 | Pins("H16 A12 H15 B12 A13 B13 C13 D13 G18 G17 H18 J18 J19 G11 H10 J11 H14 A15 J13 L8 A14 B15 C15 E14 E15 E16 F14 F15 F13 F12 G16 G15 G13 G12 J17 K16"), 61 | IOStandard("3.3-V LVTTL") 62 | ), 63 | ] 64 | 65 | 66 | class Platform(AlteraPlatform): 67 | default_clk_name = "clk50" 68 | default_clk_period = 20 69 | 70 | def __init__(self): 71 | AlteraPlatform.__init__(self, "5CEBA4F23C7", _io) 72 | 73 | def create_programmer(self): 74 | return USBBlaster() 75 | -------------------------------------------------------------------------------- /migen/build/platforms/de0nano.py: -------------------------------------------------------------------------------- 1 | # This file is Copyright (c) 2013 Florent Kermarrec 2 | # License: BSD 3 | 4 | from migen.build.generic_platform import * 5 | from migen.build.altera import AlteraPlatform 6 | from migen.build.altera.programmer import USBBlaster 7 | 8 | 9 | _io = [ 10 | ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")), 11 | 12 | ("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")), 13 | ("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")), 14 | ("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")), 15 | ("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")), 16 | ("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")), 17 | ("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")), 18 | ("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")), 19 | ("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")), 20 | 21 | ("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")), 22 | ("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")), 23 | 24 | ("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")), 25 | ("sw", 1, Pins("T8"), IOStandard("3.3-V LVTTL")), 26 | ("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")), 27 | ("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")), 28 | 29 | ("serial", 0, 30 | Subsignal("tx", Pins("D3"), IOStandard("3.3-V LVTTL")), 31 | Subsignal("rx", Pins("C3"), IOStandard("3.3-V LVTTL")) 32 | ), 33 | 34 | ("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")), 35 | ("sdram", 0, 36 | Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")), 37 | Subsignal("ba", Pins("M7 M6")), 38 | Subsignal("cs_n", Pins("P6")), 39 | Subsignal("cke", Pins("L7")), 40 | Subsignal("ras_n", Pins("L2")), 41 | Subsignal("cas_n", Pins("L1")), 42 | Subsignal("we_n", Pins("C2")), 43 | Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")), 44 | Subsignal("dm", Pins("R6 T5")), 45 | IOStandard("3.3-V LVTTL") 46 | ), 47 | 48 | ("epcs", 0, 49 | Subsignal("data0", Pins("H2")), 50 | Subsignal("dclk", Pins("H1")), 51 | Subsignal("ncs0", Pins("D2")), 52 | Subsignal("asd0", Pins("C1")), 53 | IOStandard("3.3-V LVTTL") 54 | ), 55 | 56 | ("i2c", 0, 57 | Subsignal("sclk", Pins("F2")), 58 | Subsignal("sdat", Pins("F1")), 59 | IOStandard("3.3-V LVTTL") 60 | ), 61 | 62 | ("g_sensor", 0, 63 | Subsignal("cs_n", Pins("G5")), 64 | Subsignal("int", Pins("M2")), 65 | IOStandard("3.3-V LVTTL") 66 | ), 67 | 68 | ("adc", 0, 69 | Subsignal("cs_n", Pins("A10")), 70 | Subsignal("saddr", Pins("B10")), 71 | Subsignal("sclk", Pins("B14")), 72 | Subsignal("sdat", Pins("A9")), 73 | IOStandard("3.3-V LVTTL") 74 | ), 75 | 76 | ("gpio_0", 0, 77 | Pins("D3 C3 A2 A3 B3 B4 A4 B5 A5 D5 B6 A6 B7 D6 A7 C6", 78 | "C8 E6 E7 D8 E8 F8 F9 E9 C9 D9 E11 E10 C11 B11 A12 D11", 79 | "D12 B12"), 80 | IOStandard("3.3-V LVTTL") 81 | ), 82 | ("gpio_1", 0, 83 | Pins("F13 T15 T14 T13 R13 T12 R12 T11 T10 R11 P11 R10 N12 P9 N9 N11", 84 | "L16 K16 R16 L15 P15 P16 R14 N16 N15 P14 L14 N14 M10 L13 J16 K15", 85 | "J13 J14"), 86 | IOStandard("3.3-V LVTTL") 87 | ), 88 | ("gpio_2", 0, 89 | Pins("A14 B16 C14 C16 C15 D16 D15 D14 F15 F16 F14 G16 G15"), 90 | IOStandard("3.3-V LVTTL") 91 | ), 92 | ] 93 | 94 | 95 | class Platform(AlteraPlatform): 96 | default_clk_name = "clk50" 97 | default_clk_period = 20 98 | 99 | def __init__(self): 100 | AlteraPlatform.__init__(self, "EP4CE22F17C6", _io) 101 | 102 | def create_programmer(self): 103 | return USBBlaster() 104 | -------------------------------------------------------------------------------- /migen/build/platforms/de10lite.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.altera import AlteraPlatform 3 | from migen.build.altera.programmer import USBBlaster 4 | 5 | 6 | _io = [ 7 | ("clk10", 0, Pins("N5"), IOStandard("3.3-V LVTTL")), 8 | ("clk50", 0, Pins("P11"), IOStandard("3.3-V LVTTL")), 9 | ("clk50", 1, Pins("N14"), IOStandard("3.3-V LVTTL")), 10 | 11 | ("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")), 12 | ("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")), 13 | ("user_led", 2, Pins("A10"), IOStandard("3.3-V LVTTL")), 14 | ("user_led", 3, Pins("B10"), IOStandard("3.3-V LVTTL")), 15 | ("user_led", 4, Pins("D13"), IOStandard("3.3-V LVTTL")), 16 | ("user_led", 5, Pins("C13"), IOStandard("3.3-V LVTTL")), 17 | ("user_led", 6, Pins("E14"), IOStandard("3.3-V LVTTL")), 18 | ("user_led", 7, Pins("D14"), IOStandard("3.3-V LVTTL")), 19 | ("user_led", 8, Pins("A11"), IOStandard("3.3-V LVTTL")), 20 | ("user_led", 9, Pins("B11"), IOStandard("3.3-V LVTTL")), 21 | 22 | ("user_btn", 0, Pins("B8"), IOStandard("3.3-V LVTTL")), 23 | ("user_btn", 1, Pins("A7"), IOStandard("3.3-V LVTTL")), 24 | 25 | ("user_sw", 0, Pins("C10"), IOStandard("3.3-V LVTTL")), 26 | ("user_sw", 1, Pins("C11"), IOStandard("3.3-V LVTTL")), 27 | ("user_sw", 2, Pins("D12"), IOStandard("3.3-V LVTTL")), 28 | ("user_sw", 3, Pins("C12"), IOStandard("3.3-V LVTTL")), 29 | ("user_sw", 4, Pins("A12"), IOStandard("3.3-V LVTTL")), 30 | ("user_sw", 5, Pins("B12"), IOStandard("3.3-V LVTTL")), 31 | ("user_sw", 6, Pins("A13"), IOStandard("3.3-V LVTTL")), 32 | ("user_sw", 7, Pins("A14"), IOStandard("3.3-V LVTTL")), 33 | ("user_sw", 8, Pins("B14"), IOStandard("3.3-V LVTTL")), 34 | ("user_sw", 9, Pins("F15"), IOStandard("3.3-V LVTTL")), 35 | 36 | # 7-segment displays 37 | ("seven_seg", 0, Pins("C14 E15 C15 C16 E16 D17 C17 D15"), IOStandard("3.3-V LVTTL")), 38 | ("seven_seg", 1, Pins("C18 D18 E18 B16 A17 A18 B17 A16"), IOStandard("3.3-V LVTTL")), 39 | ("seven_seg", 2, Pins("B20 A20 B19 A21 B21 C22 B22 A19"), IOStandard("3.3-V LVTTL")), 40 | ("seven_seg", 3, Pins("F21 E22 E21 C19 C20 D19 E17 D22"), IOStandard("3.3-V LVTTL")), 41 | ("seven_seg", 4, Pins("F18 E20 E19 J18 H19 F19 F20 F17"), IOStandard("3.3-V LVTTL")), 42 | ("seven_seg", 5, Pins("J20 K20 L18 N18 M20 N19 N20 L19"), IOStandard("3.3-V LVTTL")), 43 | 44 | 45 | ("gpio_0", 0, 46 | Pins("V10 W10 V9 W9 V8 W8 V7 W7 W6 V5 W5 AA15 AA14 W13 W12 AB13 AB12 Y11 AB11 W11 AB10 AA10 AA9 Y8 AA8 Y7 AA7 Y6 AA6 Y5 AA5 Y4 AB3 Y3 AB2 AA2"), 47 | IOStandard("3.3-V LVTTL") 48 | ), 49 | ("gpio_1", 0, 50 | Pins("AB5 AB6 AB7 AB8 AB9 Y10 AA11 AA12 AB17 AA17 AB19 AA19 Y19 AB20 AB21 AA20 F16"), 51 | IOStandard("3.3-V LVTTL") 52 | ), 53 | 54 | ("vga_out", 0, 55 | Subsignal("hsync_n", Pins("N3")), 56 | Subsignal("vsync_n", Pins("N1")), 57 | Subsignal("r", Pins("AA1 V1 Y2 Y1")), 58 | Subsignal("g", Pins("W1 T2 R2 R1")), 59 | Subsignal("b", Pins("P1 T1 P4 N2")), 60 | IOStandard("3.3-V LVTTL") 61 | ), 62 | 63 | ("sdram_clock", 0, Pins("L14"), IOStandard("3.3-V LVTTL")), 64 | ("sdram", 0, 65 | Subsignal("a", Pins("U17 W19 V18 U18 U19 T18 T19 R18 P18 P19 T20 P20 R20")), 66 | Subsignal("ba", Pins("T21 T22")), 67 | Subsignal("cs_n", Pins("U20")), 68 | Subsignal("cke", Pins("N22")), 69 | Subsignal("ras_n", Pins("U22")), 70 | Subsignal("cas_n", Pins("U21")), 71 | Subsignal("we_n", Pins("V20")), 72 | Subsignal("dq", Pins("Y21 Y20 AA22 AA21 Y22 W22 W20 V21 P21 J22 H21 H22 G22 G20 G19 F22")), 73 | Subsignal("dm", Pins("V22 J21")), 74 | IOStandard("3.3-V LVTTL") 75 | ), 76 | 77 | ("accelerometer", 0, 78 | Subsignal("int1", Pins("Y14")), 79 | Subsignal("int1", Pins("Y13")), 80 | Subsignal("mosi", Pins("V11")), 81 | Subsignal("miso", Pins("V12")), 82 | Subsignal("clk", Pins("AB15")), 83 | Subsignal("cs_n", Pins("AB16")), 84 | IOStandard("3.3-V LVTTL") 85 | ) 86 | ] 87 | 88 | 89 | class Platform(AlteraPlatform): 90 | default_clk_name = "clk50" 91 | default_clk_period = 20 92 | create_rbf = False 93 | 94 | def __init__(self): 95 | AlteraPlatform.__init__(self, "10M50DAF484C7G", _io) 96 | 97 | def create_programmer(self): 98 | return USBBlaster() 99 | -------------------------------------------------------------------------------- /migen/build/platforms/ebaz4205.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.xilinx import XilinxPlatform 3 | 4 | 5 | _io = [ 6 | # Green and Red LEDs 7 | ("user_led", 0, Pins("W13"), IOStandard("LVCMOS33")), 8 | ("user_led", 1, Pins("W14"), IOStandard("LVCMOS33")), 9 | # Push Buttons 10 | ("user_btn", 0, Pins("A17"), IOStandard("LVCMOS33")), 11 | ("user_btn", 1, Pins("A14"), IOStandard("LVCMOS33")), 12 | # UART 13 | ( 14 | "serial", 15 | 0, 16 | Subsignal("tx", Pins("A16")), 17 | Subsignal("rx", Pins("F15")), 18 | IOStandard("LVCMOS33"), 19 | ), 20 | # SD Card 21 | ( 22 | "sdcard", 23 | 0, 24 | Subsignal("detect", Pins("A12"), Misc("PULLUP True")), 25 | Subsignal("data", Pins("E12 A9 F13 B15")), 26 | Subsignal("cmd", Pins("C17")), 27 | Subsignal("clk", Pins("D14")), 28 | Subsignal("cd", Pins("B15")), 29 | IOStandard("LVCMOS33"), 30 | Misc("SLEW=FAST"), 31 | ), 32 | # NAND Flash 33 | ( 34 | "nandflash", 35 | 0, 36 | Subsignal("nand_data", Pins("A6 A5 B7 E8 B5 E9 C6 D9")), 37 | Subsignal("nand_ce", Pins("E6")), 38 | Subsignal("nand_re", Pins("D5")), 39 | Subsignal("nand_we", Pins("D6")), 40 | Subsignal("nand_ale", Pins("B8")), 41 | Subsignal("nand_cle", Pins("D8")), 42 | Subsignal("nand_rb", Pins("C5")), 43 | IOStandard("LVCMOS33"), 44 | ), 45 | # ETH PHY 46 | ( 47 | "gmii", 48 | 0, 49 | Subsignal("rxd", Pins("Y16 V16 V17 Y17")), 50 | Subsignal("txd", Pins("W18 Y18 V18 Y19")), 51 | Subsignal("rx_clk", Pins("U14")), 52 | Subsignal("tx_clk", Pins("U15")), 53 | Subsignal("rx_dv", Pins("W16")), 54 | Subsignal("tx_en", Pins("W19")), 55 | IOStandard("LVCMOS33"), 56 | ), 57 | ( 58 | "mdio", 59 | 0, 60 | Subsignal("mdio", Pins("Y14")), 61 | Subsignal("mdc", Pins("W15")), 62 | IOStandard("LVCMOS33"), 63 | ), 64 | ] 65 | 66 | # DATA1-3 2x10 2.0mm Pitch 67 | # J3 and J5 1x4 2.54mm Pitch 68 | _connectors = [ 69 | ( 70 | "DATA1", 71 | { 72 | "DATA1-5": "A20", 73 | "DATA1-6": "H16", 74 | "DATA1-7": "B19", 75 | "DATA1-8": "B20", 76 | "DATA1-9": "C20", 77 | "DATA1-11": "H17", 78 | "DATA1-13": "D20", 79 | "DATA1-14": "D18", 80 | "DATA1-15": "H18", 81 | "DATA1-16": "D19", 82 | "DATA1-17": "F20", 83 | "DATA1-18": "E19", 84 | "DATA1-19": "F19", 85 | "DATA1-20": "K17", 86 | }, 87 | ), 88 | ( 89 | "DATA2", 90 | { 91 | "DATA2-5": "G20", 92 | "DATA2-6": "J18", 93 | "DATA2-7": "G19", 94 | "DATA2-8": "H20", 95 | "DATA2-9": "J19", 96 | "DATA2-11": "K18", 97 | "DATA2-13": "K19", 98 | "DATA2-14": "J20", 99 | "DATA2-15": "L16", 100 | "DATA2-16": "L19", 101 | "DATA2-17": "M18", 102 | "DATA2-18": "L20", 103 | "DATA2-19": "M20", 104 | "DATA2-20": "L17", 105 | }, 106 | ), 107 | ( 108 | "DATA3", 109 | { 110 | "DATA3-5": "M19", 111 | "DATA3-6": "N20", 112 | "DATA3-7": "P18", 113 | "DATA3-8": "M17", 114 | "DATA3-9": "N17", 115 | "DATA3-11": "P20", 116 | "DATA3-13": "R18", 117 | "DATA3-14": "R19", 118 | "DATA3-15": "P19", 119 | "DATA3-16": "T20", 120 | "DATA3-17": "U20", 121 | "DATA3-18": "T19", 122 | "DATA3-19": "V20", 123 | "DATA3-20": "U19", 124 | }, 125 | ), 126 | ( 127 | "J3", 128 | { 129 | "J3-4-TX": "U12", 130 | "J3-3-RX": "V13", 131 | }, 132 | "J5", 133 | { 134 | "J5-4-TX": "V12", 135 | "J5-3-RX": "V15", 136 | }, 137 | ), 138 | ] 139 | 140 | 141 | class Platform(XilinxPlatform): 142 | def __init__(self): 143 | XilinxPlatform.__init__( 144 | self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado" 145 | ) 146 | -------------------------------------------------------------------------------- /migen/build/platforms/ice40_hx1k_blink_evn.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import IceBurnProgrammer 4 | 5 | 6 | _io = [ 7 | ("user_led", 0, Pins("59"), IOStandard("LVCMOS33")), 8 | ("user_led", 1, Pins("56"), IOStandard("LVCMOS33")), 9 | ("user_led", 2, Pins("53"), IOStandard("LVCMOS33")), 10 | ("user_led", 3, Pins("51"), IOStandard("LVCMOS33")), 11 | 12 | ("user_btn", 0, Pins("60"), IOStandard("LVCMOS33")), 13 | ("user_btn", 1, Pins("57"), IOStandard("LVCMOS33")), 14 | ("user_btn", 2, Pins("54"), IOStandard("LVCMOS33")), 15 | ("user_btn", 3, Pins("52"), IOStandard("LVCMOS33")), 16 | 17 | ("clk3p3", 0, Pins("13"), IOStandard("LVCMOS33")) 18 | ] 19 | 20 | 21 | class Platform(LatticePlatform): 22 | default_clk_name = "clk3p3" 23 | default_clk_period = 303.0303 24 | 25 | def __init__(self): 26 | LatticePlatform.__init__(self, "ice40-hx1k-vq100", _io, 27 | toolchain="icestorm") 28 | 29 | def create_programmer(self, iceburn_path="./iCEburn.py"): 30 | return IceBurnProgrammer(iceburn_path) 31 | -------------------------------------------------------------------------------- /migen/build/platforms/ice40_hx8k_b_evn.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import IceStormProgrammer 4 | 5 | 6 | _io = [ 7 | ("user_led", 0, Pins("B5"), IOStandard("LVCMOS33")), 8 | ("user_led", 1, Pins("B4"), IOStandard("LVCMOS33")), 9 | ("user_led", 2, Pins("A2"), IOStandard("LVCMOS33")), 10 | ("user_led", 3, Pins("A1"), IOStandard("LVCMOS33")), 11 | ("user_led", 4, Pins("C5"), IOStandard("LVCMOS33")), 12 | ("user_led", 5, Pins("C4"), IOStandard("LVCMOS33")), 13 | ("user_led", 6, Pins("B3"), IOStandard("LVCMOS33")), 14 | ("user_led", 7, Pins("C3"), IOStandard("LVCMOS33")), 15 | 16 | ("serial", 0, 17 | Subsignal("rx", Pins("B10")), 18 | Subsignal("tx", Pins("B12"), Misc("PULLUP")), 19 | Subsignal("rts", Pins("B13"), Misc("PULLUP")), 20 | Subsignal("cts", Pins("A15"), Misc("PULLUP")), 21 | Subsignal("dtr", Pins("A16"), Misc("PULLUP")), 22 | Subsignal("dsr", Pins("B14"), Misc("PULLUP")), 23 | Subsignal("dcd", Pins("B15"), Misc("PULLUP")), 24 | IOStandard("LVCMOS33"), 25 | ), 26 | 27 | ("spiflash", 0, 28 | Subsignal("cs_n", Pins("R12"), IOStandard("LVCMOS33")), 29 | Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")), 30 | Subsignal("mosi", Pins("P12"), IOStandard("LVCMOS33")), 31 | Subsignal("miso", Pins("P11"), IOStandard("LVCMOS33")), 32 | ), 33 | 34 | ("clk12", 0, Pins("J3"), IOStandard("LVCMOS33")) 35 | ] 36 | 37 | 38 | class Platform(LatticePlatform): 39 | default_clk_name = "clk12" 40 | default_clk_period = 83.333 41 | 42 | def __init__(self): 43 | LatticePlatform.__init__(self, "ice40-hx8k-ct256", _io, 44 | toolchain="icestorm") 45 | 46 | def create_programmer(self): 47 | return IceStormProgrammer() 48 | -------------------------------------------------------------------------------- /migen/build/platforms/ice40_up5k_b_evn.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import IceStormProgrammer 4 | 5 | 6 | _io = [ 7 | ("rgb_led", 0, 8 | Subsignal("r", Pins("41")), 9 | Subsignal("g", Pins("40")), 10 | Subsignal("b", Pins("39")), 11 | IOStandard("LVCMOS33") 12 | ), 13 | 14 | ("user_sw", 0, Pins("23"), IOStandard("LVCMOS33")), 15 | ("user_sw", 1, Pins("25"), IOStandard("LVCMOS33")), 16 | ("user_sw", 2, Pins("34"), IOStandard("LVCMOS33")), 17 | ("user_sw", 3, Pins("43"), IOStandard("LVCMOS33")), 18 | 19 | ("clk12", 0, Pins("35"), IOStandard("LVCMOS33")) 20 | ] 21 | 22 | spiflash = [ 23 | # Only usable in PROG FLASH mode and J7 attached (see PCB silkscreen). 24 | ("spiflash", 0, 25 | Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), 26 | Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), 27 | Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")), 28 | Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")), 29 | ), 30 | ] 31 | 32 | serial = [ 33 | ("serial", 0, 34 | Subsignal("tx", Pins("J2:0")), 35 | Subsignal("rx", Pins("J2:1")), 36 | IOStandard("LVCMOS33") 37 | ) 38 | ] 39 | 40 | 41 | _connectors = [ 42 | # Many pins on the AARDVARK, PMOD, J52/HEADER A, and J2/HEADER B connectors 43 | # are multiplexed with other I/O or connector pins. For completeness, all 44 | # pins are exposed here except Vdd, NC, and GND. Pin order is as specified 45 | # on the schematic (except for PMOD, which uses Digilent's numbering). 46 | 47 | # AARDVARK connector omitted- although sysCONFIG pins are exposed on this 48 | # header (which can be used as GPIO), it is meant for flashing using an 49 | # external programmer rather than as an I/O port. 50 | 51 | # PMOD connector shares pins with sysCONFIG- make sure to remove jumper 52 | # J7 if using the PMOD. TODO: Perhaps it would be better to split into two 53 | # single 6-pin PMODs. 54 | # 55 | # PMOD pinout (using ICE40 pin names): 56 | # 1, 2, 3, 4- SPI_SS, SPI_SI, SPI_SO, SPI_SCK 57 | # 5, 6, 7, 8- Free 58 | ("PMOD", "16 17 14 15 27 26 32 31"), 59 | 60 | # J52 exposes LEDs and sysCONFIG pins (yet again). Make sure to remove 61 | # jumper J7 if using the PMOD. Pin order is as follows (right to left): 62 | # 12 10 8 6 4 2 63 | # 11 9 7 5 3 1 64 | # 65 | # J52's pinout (using ICE40 pin names for SPI flash): 66 | # 1, 2- Vdd 67 | # 3, 4- rgb_led.b, SPI_SI 68 | # 5, 6- rgb_led.g, SPI_SO 69 | # 7, 8- GND, SPI_SCK 70 | # 9, 10- rgb_led.r, SPI_SS 71 | # 11, 12- GND 72 | # 3 4 5 6 8 9 10 73 | ("J52", "39 17 40 14 15 41 16"), 74 | 75 | # Pin order of J2, and J3 are as follows (left to right/top to bottom): 76 | # 2 4 6 8 10 12 14 16 18 20 77 | # 1 3 5 7 9 11 13 15 17 19 78 | # 79 | # J2's pinout is shared by many things. Entire pinout listed follows: 80 | # 1, 2- Vdd 81 | # 3, 4- user_sw0, NC 82 | # 5, 6- user_sw1, NC 83 | # 7, 8- PMOD D5, Free 84 | # 9, 10- PMOD D4, Free 85 | # 11, 12- PMOD D6, Free 86 | # 13, 14- PMOD D7, Free 87 | # 15, 16- Free, 12.00 clock 88 | # 17, 18- user_sw2, GND 89 | # 19, 20- user_sw3, GND 90 | # 3 5 7 8 9 10 11 12 13 14 15 16 17 19 91 | ("J2", "23 25 26 36 27 42 32 38 31 28 37 35 34 43"), 92 | 93 | # Bank2: 4 3 48 45 47 44 46 2 94 | # Bank1: 12 21 13 20 19 18 11 10 9 6 95 | # J3's pinout is all Free, except 1 (Vdd) and 19 (GND). 96 | # 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 97 | ("J3", "12 4 21 3 13 48 20 45 19 47 18 44 11 46 10 2 9 6"), 98 | ] 99 | 100 | 101 | class Platform(LatticePlatform): 102 | default_clk_name = "clk12" 103 | default_clk_period = 83.333 104 | 105 | def __init__(self): 106 | LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, 107 | toolchain="icestorm") 108 | 109 | def create_programmer(self): 110 | return IceStormProgrammer() 111 | -------------------------------------------------------------------------------- /migen/build/platforms/icebreaker.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import IceStormProgrammer 4 | 5 | 6 | _io = [ 7 | ("user_led_n", 0, Pins("11"), IOStandard("LVCMOS33")), 8 | ("user_led_n", 1, Pins("37"), IOStandard("LVCMOS33")), 9 | # Color-specific aliases 10 | ("user_ledr_n", 0, Pins("11"), IOStandard("LVCMOS33")), 11 | ("user_ledg_n", 0, Pins("37"), IOStandard("LVCMOS33")), 12 | ("user_btn_n", 0, Pins("10"), IOStandard("LVCMOS33")), 13 | 14 | ("serial", 0, 15 | Subsignal("rx", Pins("6")), 16 | Subsignal("tx", Pins("9"), Misc("PULLUP")), 17 | IOStandard("LVCMOS33") 18 | ), 19 | 20 | ("spiflash", 0, 21 | Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), 22 | Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), 23 | Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")), 24 | Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")), 25 | Subsignal("wp", Pins("12"), IOStandard("LVCMOS33")), 26 | Subsignal("hold", Pins("13"), IOStandard("LVCMOS33")), 27 | ), 28 | 29 | ("spiflash4x", 0, 30 | Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), 31 | Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), 32 | Subsignal("dq", Pins("14 17 12 13"), IOStandard("LVCMOS33")), 33 | ), 34 | 35 | ("clk12", 0, Pins("35"), IOStandard("LVCMOS33")) 36 | ] 37 | 38 | _connectors = [ 39 | ("PMOD1A", "4 2 47 45 3 48 46 44"), 40 | ("PMOD1B", "43 38 34 31 42 36 32 28"), 41 | ("PMOD2", "27 25 21 19 26 23 20 18") 42 | ] 43 | 44 | # The attached LED/button section can be either used standalone or as a PMOD. 45 | # Attach to platform using: 46 | # plat.add_extension(break_off_pmod) 47 | # pmod_btn = plat.request("user_btn") 48 | break_off_pmod = [ 49 | ("user_btn", 0, Pins("PMOD2:6"), IOStandard("LVCMOS33")), 50 | ("user_btn", 1, Pins("PMOD2:3"), IOStandard("LVCMOS33")), 51 | ("user_btn", 2, Pins("PMOD2:7"), IOStandard("LVCMOS33")), 52 | 53 | ("user_led", 0, Pins("PMOD2:4"), IOStandard("LVCMOS33")), 54 | ("user_led", 1, Pins("PMOD2:0"), IOStandard("LVCMOS33")), 55 | ("user_led", 2, Pins("PMOD2:1"), IOStandard("LVCMOS33")), 56 | ("user_led", 3, Pins("PMOD2:5"), IOStandard("LVCMOS33")), 57 | ("user_led", 4, Pins("PMOD2:2"), IOStandard("LVCMOS33")), 58 | 59 | # Color-specific aliases 60 | ("user_ledr", 0, Pins("PMOD2:4"), IOStandard("LVCMOS33")), 61 | ("user_ledg", 0, Pins("PMOD2:0"), IOStandard("LVCMOS33")), 62 | ("user_ledg", 1, Pins("PMOD2:1"), IOStandard("LVCMOS33")), 63 | ("user_ledg", 2, Pins("PMOD2:5"), IOStandard("LVCMOS33")), 64 | ("user_ledg", 3, Pins("PMOD2:2"), IOStandard("LVCMOS33")) 65 | ] 66 | 67 | 68 | class Platform(LatticePlatform): 69 | default_clk_name = "clk12" 70 | default_clk_period = 83.333 71 | 72 | def __init__(self): 73 | LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, 74 | toolchain="icestorm") 75 | 76 | def create_programmer(self): 77 | return IceStormProgrammer() 78 | -------------------------------------------------------------------------------- /migen/build/platforms/icestick.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import IceStormProgrammer 4 | 5 | 6 | _io = [ 7 | ("user_led", 0, Pins("99"), IOStandard("LVCMOS33")), 8 | ("user_led", 1, Pins("98"), IOStandard("LVCMOS33")), 9 | ("user_led", 2, Pins("97"), IOStandard("LVCMOS33")), 10 | ("user_led", 3, Pins("96"), IOStandard("LVCMOS33")), 11 | ("user_led", 4, Pins("95"), IOStandard("LVCMOS33")), 12 | 13 | ("serial", 0, 14 | Subsignal("rx", Pins("9")), 15 | Subsignal("tx", Pins("8"), Misc("PULLUP")), 16 | Subsignal("rts", Pins("7"), Misc("PULLUP")), 17 | Subsignal("cts", Pins("4"), Misc("PULLUP")), 18 | Subsignal("dtr", Pins("3"), Misc("PULLUP")), 19 | Subsignal("dsr", Pins("2"), Misc("PULLUP")), 20 | Subsignal("dcd", Pins("1"), Misc("PULLUP")), 21 | IOStandard("LVTTL"), 22 | ), 23 | 24 | ("irda", 0, 25 | Subsignal("rx", Pins("106")), 26 | Subsignal("tx", Pins("105")), 27 | Subsignal("sd", Pins("107")), 28 | IOStandard("LVCMOS33") 29 | ), 30 | 31 | ("spiflash", 0, 32 | Subsignal("cs_n", Pins("71"), IOStandard("LVCMOS33")), 33 | Subsignal("clk", Pins("70"), IOStandard("LVCMOS33")), 34 | Subsignal("mosi", Pins("67"), IOStandard("LVCMOS33")), 35 | Subsignal("miso", Pins("68"), IOStandard("LVCMOS33")) 36 | ), 37 | 38 | ("clk12", 0, Pins("21"), IOStandard("LVCMOS33")) 39 | ] 40 | 41 | _connectors = [ 42 | ("GPIO0", "44 45 47 48 56 60 61 62"), 43 | ("GPIO1", "119 118 117 116 115 114 113 112"), 44 | ("PMOD", "78 79 80 81 87 88 90 91") 45 | ] 46 | 47 | 48 | class Platform(LatticePlatform): 49 | default_clk_name = "clk12" 50 | default_clk_period = 83.333 51 | 52 | def __init__(self): 53 | LatticePlatform.__init__(self, "ice40-hx1k-tq144", _io, _connectors, 54 | toolchain="icestorm") 55 | 56 | def create_programmer(self): 57 | return IceStormProgrammer() 58 | -------------------------------------------------------------------------------- /migen/build/platforms/max1000.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.altera import AlteraPlatform 3 | from migen.build.altera.programmer import USBBlaster 4 | 5 | 6 | _io = [ 7 | ("clk12", 0, Pins("H6"), IOStandard("3.3-V LVTTL")), 8 | 9 | ("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")), 10 | ("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")), 11 | ("user_led", 2, Pins("A11"), IOStandard("3.3-V LVTTL")), 12 | ("user_led", 3, Pins("A10"), IOStandard("3.3-V LVTTL")), 13 | ("user_led", 4, Pins("B10"), IOStandard("3.3-V LVTTL")), 14 | ("user_led", 5, Pins("C9"), IOStandard("3.3-V LVTTL")), 15 | ("user_led", 6, Pins("C10"), IOStandard("3.3-V LVTTL")), 16 | ("user_led", 7, Pins("D8"), IOStandard("3.3-V LVTTL")), 17 | 18 | ("sw", 0, Pins("E6"), IOStandard("3.3-V LVTTL")), 19 | 20 | ("serial", 0, 21 | Subsignal("tx", Pins("B4"), IOStandard("3.3-V LVTTL")), 22 | Subsignal("rx", Pins("A4"), IOStandard("3.3-V LVTTL")), 23 | Subsignal("rts", Pins("A6"), IOStandard("3.3-V LVTTL")), 24 | Subsignal("cts", Pins("B5"), IOStandard("3.3-V LVTTL")), 25 | Subsignal("dtr", Pins("A7"), IOStandard("3.3-V LVTTL")), 26 | Subsignal("dsr", Pins("B6"), IOStandard("3.3-V LVTTL")) 27 | ), 28 | 29 | ("sdram_clock", 0, Pins("M9"), IOStandard("3.3-V LVTTL")), 30 | ("sdram", 0, 31 | Subsignal("a", Pins("K6 M5 N5 J8 N10 M11 N9 L10 M13 N8 N4 M10 L11 M12")), 32 | Subsignal("ba", Pins("N6 K8")), 33 | Subsignal("cs_n", Pins("M4")), 34 | Subsignal("cke", Pins("M8")), 35 | Subsignal("ras_n", Pins("M7")), 36 | Subsignal("cas_n", Pins("N7")), 37 | Subsignal("we_n", Pins("K7")), 38 | Subsignal("dq", Pins("D11 G10 F10 F9 E10 D9 G9 F8 F13 E12 E13 D12 C12 B12 B13 A12")), 39 | Subsignal("dm", Pins("E9 F12")), 40 | IOStandard("3.3-V LVTTL") 41 | ), 42 | 43 | ("accelerometer", 0, 44 | Subsignal("int1", Pins("J5")), 45 | Subsignal("int1", Pins("L4")), 46 | Subsignal("mosi", Pins("J7")), 47 | Subsignal("miso", Pins("K5")), 48 | Subsignal("clk", Pins("J6")), 49 | Subsignal("cs_n", Pins("L5")), 50 | IOStandard("3.3-V LVTTL") 51 | ), 52 | 53 | ("spiflash", 0, 54 | Subsignal("cs_n", Pins("B3")), 55 | Subsignal("clk", Pins("A3")), 56 | Subsignal("dio0", Pins("A2")), 57 | Subsignal("dio1", Pins("B2")), 58 | Subsignal("dio2", Pins("C4")), 59 | Subsignal("dio3", Pins("B9")), 60 | IOStandard("3.3-V LVTTL") 61 | ), 62 | 63 | # J1 connector 64 | ("gpio_0", 0, 65 | Pins("D3 E1 C2 C1 D1 E3 F1 E4 H8 K10 H5 H4 J1 J2"), 66 | IOStandard("3.3-V LVTTL") 67 | ), 68 | 69 | # J2 connector 70 | ("gpio_1", 0, 71 | Pins("L12 J12 J13 K11 K12 J10 H10 H13 G12 B11 G13"), 72 | IOStandard("3.3-V LVTTL") 73 | ), 74 | 75 | ("pmod", 0, 76 | Subsignal("d", Pins("F15 F16 C17 C18 F14 G14 D17 D18")), 77 | IOStandard("3.3-V LVTTL") 78 | ) 79 | ] 80 | 81 | 82 | class Platform(AlteraPlatform): 83 | default_clk_name = "clk12" 84 | default_clk_period = 83.333 85 | create_rbf = False 86 | 87 | def __init__(self): 88 | AlteraPlatform.__init__(self, "10M08SAU169C8G", _io) 89 | 90 | def create_programmer(self): 91 | return USBBlaster() 92 | -------------------------------------------------------------------------------- /migen/build/platforms/minispartan6.py: -------------------------------------------------------------------------------- 1 | # This file is Copyright (c) 2015 Matt O'Gorman 2 | # License: BSD 3 | 4 | from migen.build.generic_platform import * 5 | from migen.build.xilinx import XilinxPlatform 6 | from migen.build.xilinx.programmer import XC3SProg, FpgaProg 7 | 8 | 9 | _io = [ 10 | ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")), 11 | ("user_led", 1, Pins("N9"), IOStandard("LVCMOS33")), 12 | ("user_led", 2, Pins("M9"), IOStandard("LVCMOS33")), 13 | ("user_led", 3, Pins("P9"), IOStandard("LVCMOS33")), 14 | ("user_led", 4, Pins("T8"), IOStandard("LVCMOS33")), 15 | ("user_led", 5, Pins("N8"), IOStandard("LVCMOS33")), 16 | ("user_led", 6, Pins("P8"), IOStandard("LVCMOS33")), 17 | ("user_led", 7, Pins("P7"), IOStandard("LVCMOS33")), 18 | 19 | ("user_sw", 0, Pins("L1"), IOStandard("LVCMOS33"), Misc("PULLUP")), 20 | ("user_sw", 1, Pins("L3"), IOStandard("LVCMOS33"), Misc("PULLUP")), 21 | ("user_sw", 2, Pins("L4"), IOStandard("LVCMOS33"), Misc("PULLUP")), 22 | ("user_sw", 3, Pins("L5"), IOStandard("LVCMOS33"), Misc("PULLUP")), 23 | 24 | ("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")), 25 | ("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")), 26 | 27 | ("spiflash", 0, 28 | Subsignal("cs_n", Pins("T3"), IOStandard("LVCMOS33")), 29 | Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")), 30 | Subsignal("mosi", Pins("T10"), IOStandard("LVCMOS33")), 31 | Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33")) 32 | ), 33 | 34 | ("adc", 0, 35 | Subsignal("cs_n", Pins("F6"), IOStandard("LVCMOS33")), 36 | Subsignal("clk", Pins("G6"), IOStandard("LVCMOS33")), 37 | Subsignal("mosi", Pins("H4"), IOStandard("LVCMOS33")), 38 | Subsignal("miso", Pins("H5"), IOStandard("LVCMOS33")) 39 | ), 40 | 41 | ("serial", 0, 42 | Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1 43 | Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0 44 | ), 45 | 46 | ("audio", 0, 47 | Subsignal("a0", Pins("B8"), IOStandard("LVCMOS33")), 48 | Subsignal("a1", Pins("A8"), IOStandard("LVCMOS33")) 49 | ), 50 | 51 | ("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), 52 | ("sdram", 0, 53 | Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")), 54 | Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")), 55 | Subsignal("we_n", Pins("R5")), 56 | Subsignal("ras_n", Pins("R2")), 57 | Subsignal("cas_n", Pins("T4")), 58 | Subsignal("cs_n", Pins("R1")), 59 | Subsignal("cke", Pins("H16")), 60 | Subsignal("ba", Pins("R14 T14")), 61 | Subsignal("dm", Pins("T5 F15")), 62 | IOStandard("LVCMOS33"), Misc("SLEW=FAST") 63 | ), 64 | 65 | ("usb_fifo", 0, 66 | Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")), 67 | Subsignal("rxf_n", Pins("N3")), 68 | Subsignal("txe_n", Pins("N1")), 69 | Subsignal("rd_n", Pins("M1")), 70 | Subsignal("wr_n", Pins("M2")), 71 | Subsignal("siwua", Pins("M3")), 72 | IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST") 73 | ), 74 | 75 | ("sd", 0, 76 | Subsignal("sck", Pins("L12")), 77 | Subsignal("d3", Pins("K12")), 78 | Subsignal("d", Pins("M10")), 79 | Subsignal("d1", Pins("L10")), 80 | Subsignal("d2", Pins("J11")), 81 | Subsignal("cmd", Pins("K11")), 82 | IOStandard("LVCMOS33") 83 | ), 84 | 85 | ("dvi_in", 0, 86 | Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")), 87 | Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")), 88 | Subsignal("data_p", Pins("C7 B6 B5"), IOStandard("TMDS_33")), 89 | Subsignal("data_n", Pins("A7 A6 A5"), IOStandard("TMDS_33")), 90 | Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")), 91 | Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33")) 92 | ), 93 | 94 | ("dvi_out", 0, 95 | Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")), 96 | Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")), 97 | Subsignal("data_p", Pins("C13 B12 C11"), IOStandard("TMDS_33")), 98 | Subsignal("data_n", Pins("A13 A12 A11"), IOStandard("TMDS_33")), 99 | ) 100 | ] 101 | 102 | _connectors = [ 103 | ("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"), 104 | ("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"), 105 | ("C", "J13 J12 K14 L14 L13 M14 M13 N14 M12 N12 P12 M11"), 106 | ("D", "D6 C6 E6 C5"), 107 | ("E", "D5 A4 G5 A3 B3 A2 B2 C3 C2 D3 D1 E3"), 108 | ("F", "E2 E1 E4 F4 F5 G3 F3 G1 H3 H1 H2 J1") 109 | ] 110 | 111 | 112 | class Platform(XilinxPlatform): 113 | default_clk_name = "clk32" 114 | default_clk_period = 31.25 115 | 116 | def __init__(self, device="xc6slx9", programmer="xc3sprog"): 117 | self.programmer = programmer 118 | XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors) 119 | 120 | def create_programmer(self): 121 | if self.programmer == "xc3sprog": 122 | return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit") 123 | elif self.programmer == "fpgaprog": 124 | return FpgaProg() 125 | else: 126 | raise ValueError("{} programmer is not supported".format(programmer)) 127 | -------------------------------------------------------------------------------- /migen/build/platforms/ml605.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.xilinx import XilinxPlatform 3 | 4 | 5 | _io = [ 6 | # System clock (Differential 200MHz) 7 | ("clk200", 0, 8 | Subsignal("p", Pins("J9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), 9 | Subsignal("n", Pins("H9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")) 10 | ), 11 | 12 | # User clock (66MHz) 13 | ("clk66", 0, Pins("U23"), IOStandard("LVCMOS25")), 14 | 15 | # CPU reset switch 16 | ("cpu_reset", 0, Pins("H10"), IOStandard("SSTL15")), 17 | 18 | # LEDs 19 | ("user_led", 0, Pins("AC22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), 20 | ("user_led", 1, Pins("AC24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), 21 | ("user_led", 2, Pins("AE22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), 22 | ("user_led", 3, Pins("AE23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), 23 | ("user_led", 4, Pins("AB23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), 24 | ("user_led", 5, Pins("AG23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), 25 | ("user_led", 6, Pins("AE24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), 26 | ("user_led", 7, Pins("AD24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), 27 | 28 | # USB-to-UART 29 | ("serial", 0, 30 | Subsignal("tx", Pins("J25"), IOStandard("LVCMOS25")), 31 | Subsignal("rx", Pins("J24"), IOStandard("LVCMOS25")) 32 | ), 33 | 34 | # 10/100/1000 Tri-Speed Ethernet PHY 35 | ("eth_clocks", 0, 36 | Subsignal("rx", Pins("AP11")), 37 | Subsignal("tx", Pins("AD12")), 38 | IOStandard("LVCMOS25") 39 | ), 40 | ("eth", 0, 41 | Subsignal("rst_n", Pins("AH13")), 42 | Subsignal("rx_dv", Pins("AM13")), 43 | Subsignal("rx_er", Pins("AG12")), 44 | Subsignal("rx_data", Pins("AN13 AF14 AE14 AN12 AM12 AD11 AC12 AC13")), 45 | Subsignal("tx_en", Pins("AJ10")), 46 | Subsignal("tx_er", Pins("AH10")), 47 | Subsignal("tx_data", Pins("AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11")), 48 | Subsignal("col", Pins("AK13")), 49 | Subsignal("crs", Pins("AL13")), 50 | IOStandard("LVCMOS25") 51 | ) 52 | ] 53 | 54 | 55 | class Platform(XilinxPlatform): 56 | default_clk_name = "clk200" 57 | default_clk_period = 5 58 | 59 | def __init__(self): 60 | XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io) 61 | -------------------------------------------------------------------------------- /migen/build/platforms/mystorm_blackice.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import Subsignal, Pins, IOStandard 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import MyStormProgrammer 4 | 5 | 6 | _io = [ 7 | ("sram", 0, 8 | Subsignal("adr", Pins("137 138 139 141 142 42 43 44 73 74 75 76 115", 9 | "116 117 118 119 78 62")), 10 | Subsignal("dat", Pins("135 134 130 128 125 124 122 121 61 60 56 55 52", 11 | "49 48 47")), 12 | Subsignal("oe", Pins("45")), 13 | Subsignal("we", Pins("120")), 14 | Subsignal("cs", Pins("136")), 15 | IOStandard("LVCMOS33"), 16 | ), 17 | 18 | ("clk100", 0, Pins("129"), IOStandard("LVCMOS33")), 19 | 20 | ("mmc", 0, 21 | Subsignal("dat", Pins("63 64 39 38")), 22 | Subsignal("cmd", Pins("41")), 23 | Subsignal("clk", Pins("37")), 24 | IOStandard("LVCMOS33"), 25 | ), 26 | 27 | ("serial", 0, 28 | Subsignal("rx", Pins("88")), 29 | Subsignal("tx", Pins("85")), 30 | Subsignal("rts", Pins("91")), 31 | Subsignal("cts", Pins("94")), 32 | IOStandard("LVCMOS33"), 33 | ), 34 | 35 | ("user_btn", 0, Pins("63"), IOStandard("LVCMOS33")), 36 | ("user_btn", 1, Pins("64"), IOStandard("LVCMOS33")), 37 | 38 | ("user_sw", 0, Pins("37"), IOStandard("LVCMOS33")), 39 | ("user_sw", 1, Pins("38"), IOStandard("LVCMOS33")), 40 | ("user_sw", 2, Pins("39"), IOStandard("LVCMOS33")), 41 | ("user_sw", 3, Pins("41"), IOStandard("LVCMOS33")), 42 | 43 | ("user_led", 0, Pins("71"), IOStandard("LVCMOS33")), 44 | ("user_led", 1, Pins("67"), IOStandard("LVCMOS33")), 45 | ("user_led", 2, Pins("68"), IOStandard("LVCMOS33")), 46 | ("user_led", 3, Pins("70"), IOStandard("LVCMOS33")), 47 | 48 | ("done", 0, Pins("52"), IOStandard("LVCMOS33")), 49 | ("dbg1", 0, Pins("49"), IOStandard("LVCMOS33")), 50 | ("greset", 0, Pins("128"), IOStandard("LVCMOS33")), 51 | ] 52 | 53 | _connectors = [ 54 | ("pmod0", "94 91 88 85"), 55 | ("pmod1", "95 93 90 87"), 56 | ("pmod2", "105 102 99 97"), 57 | ("pmod3", "104 101 98 96"), 58 | ("pmod4", "143 114 112 107"), 59 | ("pmod5", "144 113 110 106"), 60 | ("pmod6", "10 9 2 1"), 61 | ("pmod7", "8 7 4 3"), 62 | ("pmod8", "20 19 16 15"), 63 | ("pmod9", "18 17 12 11"), 64 | ("pmod10", "34 33 22 21"), 65 | ("pmod11", "32 31 26 25"), 66 | ("pmod12", "29 28 24 23"), 67 | ("pmod13", "71 67 68 70"), 68 | ] 69 | 70 | 71 | class Platform(LatticePlatform): 72 | default_clk_name = "clk100" 73 | default_clk_period = 10 74 | 75 | def __init__(self): 76 | LatticePlatform.__init__(self, "ice40-hx8k-tq144:4k", 77 | _io, _connectors, toolchain="icestorm") 78 | 79 | def create_programmer(self, serial_port="/dev/ttyACM0"): 80 | return MyStormProgrammer(serial_port) 81 | -------------------------------------------------------------------------------- /migen/build/platforms/mystorm_blackice_ii.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import Subsignal, Pins, IOStandard 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import MyStormProgrammer 4 | 5 | 6 | _io = [ 7 | ("sram", 0, 8 | Subsignal("adr", Pins("137 138 139 141 142 42 43 44 73 74 75 76 115", 9 | "116 117 118 119 78")), 10 | Subsignal("dat", Pins("136 135 134 130 125 124 122 121 62 61 60 56 55", 11 | "48 47 45")), 12 | Subsignal("oe", Pins("29")), 13 | Subsignal("we", Pins("120")), 14 | Subsignal("cs", Pins("23")), 15 | Subsignal("ub", Pins("28")), 16 | Subsignal("lb", Pins("24")), 17 | IOStandard("LVCMOS33"), 18 | ), 19 | 20 | ("clk100", 0, Pins("129"), IOStandard("LVCMOS33")), 21 | 22 | ("mmc", 0, 23 | Subsignal("dat", Pins("63 64 39 38")), 24 | Subsignal("cmd", Pins("41")), 25 | Subsignal("clk", Pins("37")), 26 | IOStandard("LVCMOS33"), 27 | ), 28 | 29 | ("serial", 0, 30 | Subsignal("rx", Pins("88")), 31 | Subsignal("tx", Pins("85")), 32 | Subsignal("rts", Pins("91")), 33 | Subsignal("cts", Pins("94")), 34 | IOStandard("LVCMOS33"), 35 | ), 36 | 37 | ("user_btn", 0, Pins("63"), IOStandard("LVCMOS33")), 38 | ("user_btn", 1, Pins("64"), IOStandard("LVCMOS33")), 39 | 40 | ("user_sw", 0, Pins("37"), IOStandard("LVCMOS33")), 41 | ("user_sw", 1, Pins("38"), IOStandard("LVCMOS33")), 42 | ("user_sw", 2, Pins("39"), IOStandard("LVCMOS33")), 43 | ("user_sw", 3, Pins("41"), IOStandard("LVCMOS33")), 44 | 45 | ("user_led", 0, Pins("71"), IOStandard("LVCMOS33")), 46 | ("user_led", 1, Pins("67"), IOStandard("LVCMOS33")), 47 | ("user_led", 2, Pins("68"), IOStandard("LVCMOS33")), 48 | ("user_led", 3, Pins("70"), IOStandard("LVCMOS33")), 49 | 50 | ("done", 0, Pins("52"), IOStandard("LVCMOS33")), 51 | ("dbg1", 0, Pins("49"), IOStandard("LVCMOS33")), 52 | ("greset", 0, Pins("128"), IOStandard("LVCMOS33")), 53 | ] 54 | 55 | _connectors = [ 56 | ("pmod0", "94 91 88 85"), 57 | ("pmod1", "95 93 90 87"), 58 | ("pmod2", "105 102 99 97"), 59 | ("pmod3", "104 101 98 96"), 60 | ("pmod4", "143 114 112 107"), 61 | ("pmod5", "144 113 110 106"), 62 | ("pmod6", "10 9 2 1"), 63 | ("pmod7", "8 7 4 3"), 64 | ("pmod8", "20 19 16 15"), 65 | ("pmod9", "18 17 12 11"), 66 | ("pmod10", "34 33 22 21"), 67 | ("pmod11", "32 31 26 25"), 68 | ("pmod12", "37 38 39 41"), 69 | ("pmod13", "71 67 68 70"), 70 | ] 71 | 72 | 73 | class Platform(LatticePlatform): 74 | default_clk_name = "clk100" 75 | default_clk_period = 10 76 | 77 | def __init__(self): 78 | LatticePlatform.__init__(self, "ice40-hx8k-tq144:4k", 79 | _io, _connectors, toolchain="icestorm") 80 | 81 | def create_programmer(self, serial_port="/dev/ttyACM0"): 82 | return MyStormProgrammer(serial_port) 83 | -------------------------------------------------------------------------------- /migen/build/platforms/papilio_pro.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.xilinx import XilinxPlatform 3 | from migen.build.xilinx.programmer import XC3SProg 4 | 5 | 6 | _io = [ 7 | ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), 8 | 9 | ("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")), 10 | 11 | ("serial", 0, 12 | Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), 13 | Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP")) 14 | ), 15 | 16 | ("spiflash", 0, 17 | Subsignal("cs_n", Pins("P38")), 18 | Subsignal("clk", Pins("P70")), 19 | Subsignal("mosi", Pins("P64")), 20 | Subsignal("miso", Pins("P65"), Misc("PULLUP")), 21 | IOStandard("LVCMOS33"), Misc("SLEW=FAST") 22 | ), 23 | ("spiflash2x", 0, 24 | Subsignal("cs_n", Pins("P38")), 25 | Subsignal("clk", Pins("P70")), 26 | Subsignal("dq", Pins("P64", "P65")), 27 | IOStandard("LVCMOS33"), Misc("SLEW=FAST") 28 | ), 29 | 30 | ("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), 31 | ("sdram", 0, 32 | Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44", 33 | "P43 P41 P40 P141 P35 P34")), 34 | Subsignal("ba", Pins("P143 P142")), 35 | Subsignal("cs_n", Pins("P1")), 36 | Subsignal("cke", Pins("P33")), 37 | Subsignal("ras_n", Pins("P2")), 38 | Subsignal("cas_n", Pins("P5")), 39 | Subsignal("we_n", Pins("P6")), 40 | Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")), 41 | Subsignal("dm", Pins("P7 P17")), 42 | IOStandard("LVCMOS33"), Misc("SLEW=FAST") 43 | ) 44 | ] 45 | 46 | _connectors = [ 47 | ("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"), 48 | ("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"), 49 | ("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134") 50 | ] 51 | 52 | 53 | class Platform(XilinxPlatform): 54 | default_clk_name = "clk32" 55 | default_clk_period = 31.25 56 | 57 | def __init__(self): 58 | XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors) 59 | 60 | def create_programmer(self): 61 | return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit") 62 | -------------------------------------------------------------------------------- /migen/build/platforms/pipistrello.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.xilinx import XilinxPlatform 3 | from migen.build.xilinx.programmer import XC3SProg 4 | 5 | 6 | _io = [ 7 | ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi 8 | ("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at hdmi 9 | ("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd 10 | ("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd 11 | ("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb 12 | 13 | ("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")), 14 | 15 | ("clk50", 0, Pins("H17"), IOStandard("LVTTL")), 16 | 17 | ("serial", 0, 18 | Subsignal("tx", Pins("A10")), 19 | Subsignal("rx", Pins("A11"), Misc("PULLUP")), 20 | Subsignal("cts", Pins("C10"), Misc("PULLUP")), 21 | Subsignal("rts", Pins("A9"), Misc("PULLUP")), 22 | IOStandard("LVTTL"), 23 | ), 24 | 25 | ("usb_fifo", 0, 26 | Subsignal("data", Pins("A11 A10 C10 A9 B9 A8 B8 A7")), 27 | Subsignal("rxf_n", Pins("C7")), 28 | Subsignal("txe_n", Pins("A6")), 29 | Subsignal("rd_n", Pins("B6")), 30 | Subsignal("wr_n", Pins("A5")), 31 | Subsignal("siwua", Pins("C5")), 32 | IOStandard("LVTTL"), 33 | ), 34 | 35 | ("hdmi", 0, 36 | Subsignal("clk_p", Pins("U5"), IOStandard("TMDS_33")), 37 | Subsignal("clk_n", Pins("V5"), IOStandard("TMDS_33")), 38 | Subsignal("data0_p", Pins("T6"), IOStandard("TMDS_33")), 39 | Subsignal("data0_n", Pins("V6"), IOStandard("TMDS_33")), 40 | Subsignal("data1_p", Pins("U7"), IOStandard("TMDS_33")), 41 | Subsignal("data1_n", Pins("V7"), IOStandard("TMDS_33")), 42 | Subsignal("data2_p", Pins("U8"), IOStandard("TMDS_33")), 43 | Subsignal("data2_n", Pins("V8"), IOStandard("TMDS_33")), 44 | Subsignal("scl", Pins("V9"), IOStandard("I2C")), 45 | Subsignal("sda", Pins("T9"), IOStandard("I2C")), 46 | Subsignal("hpd_notif", Pins("R8"), IOStandard("LVTTL")), 47 | ), 48 | 49 | ("spiflash", 0, 50 | Subsignal("cs_n", Pins("V3")), 51 | Subsignal("clk", Pins("R15")), 52 | Subsignal("mosi", Pins("T13")), 53 | Subsignal("miso", Pins("R13"), Misc("PULLUP")), 54 | Subsignal("wp", Pins("T14")), 55 | Subsignal("hold", Pins("V14")), 56 | IOStandard("LVTTL"), Misc("SLEW=FAST") 57 | ), 58 | 59 | ("spiflash2x", 0, 60 | Subsignal("cs_n", Pins("V3")), 61 | Subsignal("clk", Pins("R15")), 62 | Subsignal("dq", Pins("T13 R13"), Misc("PULLUP")), 63 | Subsignal("wp", Pins("T14")), 64 | Subsignal("hold", Pins("V14")), 65 | IOStandard("LVTTL"), Misc("SLEW=FAST") 66 | ), 67 | 68 | ("spiflash4x", 0, 69 | Subsignal("cs_n", Pins("V3")), 70 | Subsignal("clk", Pins("R15")), 71 | Subsignal("dq", Pins("T13 R13 T14 V14"), Misc("PULLUP")), 72 | IOStandard("LVTTL"), Misc("SLEW=FAST") 73 | ), 74 | 75 | ("mmc", 0, 76 | Subsignal("clk", Pins("A3")), 77 | Subsignal("cmd", Pins("B3"), Misc("PULLUP")), 78 | Subsignal("dat", Pins("B4 A4 B2 A2"), Misc("PULLUP")), 79 | IOStandard("SDIO") 80 | ), 81 | 82 | ("mmc_spi", 0, 83 | Subsignal("cs_n", Pins("A2"), Misc("PULLUP")), 84 | Subsignal("clk", Pins("A3")), 85 | Subsignal("mosi", Pins("B3")), 86 | Subsignal("miso", Pins("B4"), Misc("PULLUP")), 87 | IOStandard("SDIO") 88 | ), 89 | 90 | ("audio", 0, 91 | Subsignal("l", Pins("R7"), Misc("SLEW=SLOW")), 92 | Subsignal("r", Pins("T7"), Misc("SLEW=SLOW")), 93 | IOStandard("LVTTL"), 94 | ), 95 | 96 | ("ddram_clock", 0, 97 | Subsignal("p", Pins("G3")), 98 | Subsignal("n", Pins("G1")), 99 | IOStandard("MOBILE_DDR") 100 | ), 101 | 102 | ("ddram", 0, 103 | Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")), 104 | Subsignal("ba", Pins("F2 F1")), 105 | Subsignal("cke", Pins("H7")), 106 | Subsignal("ras_n", Pins("L5")), 107 | Subsignal("cas_n", Pins("K5")), 108 | Subsignal("we_n", Pins("E3")), 109 | Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")), 110 | Subsignal("dqs", Pins("L4 P2")), 111 | Subsignal("dm", Pins("K3 K4")), 112 | IOStandard("MOBILE_DDR") 113 | ) 114 | ] 115 | 116 | _connectors = [ 117 | ("A", "U18 T17 P17 P16 N16 N17 M16 L15 L17 K15 K17 J16 H15 H18 F18 D18"), 118 | ("B", "C18 E18 G18 H16 J18 K18 K16 L18 L16 M18 N18 N15 P15 P18 T18 U17"), 119 | ("C", "F17 F16 E16 G16 F15 G14 F14 H14 H13 J13 G13 H12 K14 K13 K12 L12"), 120 | ("PMOD", "D9 C8 D6 C4 B11 C9 D8 C6"), 121 | ] 122 | 123 | 124 | class Platform(XilinxPlatform): 125 | default_clk_name = "clk50" 126 | default_clk_period = 20 127 | 128 | def __init__(self): 129 | XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors) 130 | self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6" 131 | 132 | def create_programmer(self): 133 | return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit") 134 | -------------------------------------------------------------------------------- /migen/build/platforms/qm_xc6slx16_sdram.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.xilinx import XilinxPlatform 3 | 4 | 5 | _io = [ 6 | ("user_led", 1, Pins("T9"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), 7 | ("user_led", 3, Pins("R9"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), 8 | 9 | ("clk50", 0, Pins("A10"), IOStandard("LVCMOS33")), 10 | 11 | ("serial", 0, 12 | Subsignal("tx", Pins("P12"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), 13 | Subsignal("rx", Pins("M11"), IOStandard("LVCMOS33"), Misc("PULLUP")) 14 | ), 15 | 16 | ("spiflash", 0, 17 | Subsignal("cs_n", Pins("T3")), 18 | Subsignal("clk", Pins("R11")), 19 | Subsignal("mosi", Pins("T10")), 20 | Subsignal("miso", Pins("P10"), Misc("PULLUP")), 21 | IOStandard("LVCMOS33"), Misc("SLEW=FAST") 22 | ), 23 | 24 | ("sdram_clock", 0, Pins("H1"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), 25 | ("sdram", 0, 26 | Subsignal("a", Pins("L4 M3 M4 N3 R2 R1 P2 P1 N1 M1 L3 L1 K1")), 27 | Subsignal("ba", Pins("K3 K2")), 28 | Subsignal("cs_n", Pins("J3")), 29 | Subsignal("cke", Pins("J1")), 30 | Subsignal("ras_n", Pins("J4")), 31 | Subsignal("cas_n", Pins("H3")), 32 | Subsignal("we_n", Pins("G3")), 33 | Subsignal("dq", Pins("A3 A2 B3 B2 C3 C2 D3 E3 G1 F1 F2 E1 E2 D1 C1 B1")), 34 | Subsignal("dm", Pins("F3 H2")), 35 | IOStandard("LVCMOS33"), Misc("SLEW=FAST") 36 | ) 37 | ] 38 | 39 | _connectors = [ 40 | ("U7", "- - - - - - - E12 E13 B15 B16 C15 C16 D14 D16 E15 E16 F15 F16 G11 F12 " + 41 | "F14 F13 G16 G14 H15 H16 G12 H11 H13 H14 J14 J16 J11 J12 K14 J13 K15 K16 " + 42 | "L16 L14 K11 K12 M15 M16 N14 N16 M13 M14 L12 L13 P15 P16 R15 R16 R14 T15 " + 43 | "T13 T14 T12 R12"), 44 | ("U8", "- - - - - - - A14 B14 C13 A13 B12 A12 C11 A11 B10 A9 C9 A8 B8 A7 C7 A6 " + 45 | "B6 A5 B5 A4 E10 C10 E11 F10 F9 D9 C8 D8 E7 E6 F7 C6 D6 M6 P4 N5 P5 N6 M7 " + 46 | "P6 N8 L7 P9 T4 T5 R5 T6 T7 N9 M9 M10 P11 P12 M11"), #P12 M11 used as serial 47 | ] 48 | 49 | 50 | class Platform(XilinxPlatform): 51 | default_clk_name = "clk50" 52 | default_clk_period = 50 53 | 54 | def __init__(self): 55 | XilinxPlatform.__init__(self, "xc6slx16-ftg256", _io, _connectors) 56 | 57 | -------------------------------------------------------------------------------- /migen/build/platforms/quickfeather.py: -------------------------------------------------------------------------------- 1 | # This file is Copyright (c) 2020 Antmicro 2 | 3 | from migen.build.generic_platform import * 4 | from migen.build.quicklogic import QuicklogicPlatform, JLinkProgrammer, OpenOCD 5 | 6 | _io = [ 7 | ("rgb_led", 0, 8 | Subsignal("r", Pins("34")), 9 | Subsignal("g", Pins("39")), 10 | Subsignal("b", Pins("38")), 11 | IOStandard("LVCMOS33"), 12 | ), 13 | ("i2c", 0, 14 | Subsignal("scl", Pins("4")), 15 | Subsignal("sda", Pins("5")), 16 | IOStandard("LVCMOS33"), 17 | ), 18 | ("accel", 0, 19 | Subsignal("int", Pins("2")), 20 | IOStandard("LVCMOS33"), 21 | ), 22 | ("user_btn", 0, Pins("62"), IOStandard("LVCMOS33")), 23 | ("serial_debug", 0, 24 | Subsignal("clk", Pins("54")), 25 | Subsignal("data", Pins("53")), 26 | IOStandard("LVCMOS33"), 27 | ), 28 | ("spi", 0, 29 | Subsignal("clk", Pins("20")), 30 | Subsignal("mosi", Pins("16")), 31 | Subsignal("miso", Pins("17")), 32 | IOStandard("LVCMOS33"), 33 | ), 34 | ("serial", 0, 35 | Subsignal("tx", Pins("8")), 36 | Subsignal("rx", Pins("9")), 37 | IOStandard("LVCMOS33"), 38 | ), 39 | ] 40 | 41 | _connectors = [ 42 | ("J2", "28 22 21 37 36 42 40 7"), 43 | ("J3", "6 55 31 25 47 41"), 44 | ("J8", "27 26 33 32 23 57 56 3 64 63 61 59"), 45 | ] 46 | 47 | class Platform(QuicklogicPlatform): 48 | default_clk_name = "IO_CLK" 49 | default_clk_period = 10.00 50 | 51 | def __init__(self, programmer="jlink"): 52 | QuicklogicPlatform.__init__(self, "quickfeather", _io, _connectors, 53 | toolchain="quicklogic") 54 | self.programmer = programmer 55 | 56 | def create_programmer(self): 57 | if self.programmer == "jlink": 58 | return JLinkProgrammer() 59 | elif self.programmer == "openocd": 60 | return OpenOCD() 61 | else: 62 | raise ValueError("{} programmer is not supported" 63 | .format(self.programmer)) 64 | -------------------------------------------------------------------------------- /migen/build/platforms/redpitaya.py: -------------------------------------------------------------------------------- 1 | # From redpid, copyright 2014-2020 Robert Jordens 2 | # https://github.com/quartiq/redpid 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # 1. Redistributions of source code must retain the above copyright notice, 8 | # this list of conditions and the following disclaimer. 9 | # 10 | # 2. Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 | # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 18 | # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 | # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 | # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 | # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 | # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 | # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 | # POSSIBILITY OF SUCH DAMAGE. 25 | 26 | from migen.build.generic_platform import * 27 | from migen.build.xilinx import XilinxPlatform 28 | 29 | _io = [ 30 | ("user_led", i, Pins(p), IOStandard("LVCMOS33"), 31 | Drive(4), Misc("SLEW SLOW")) for i, p in enumerate( 32 | "F16 F17 G15 H15 K14 G14 J15 J14".split()) 33 | ] 34 | 35 | _io += [ 36 | ("clk125", 0, 37 | Subsignal("p", Pins("U18")), 38 | Subsignal("n", Pins("U19")), 39 | IOStandard("DIFF_HSTL_I_18") 40 | ), 41 | 42 | ("adc", 0, 43 | Subsignal("clk", Pins("N20 P20"), Misc("SLEW=FAST"), Drive(8)), 44 | Subsignal("cdcs", Pins("V18"), Misc("SLEW=FAST"), Drive(8)), 45 | Subsignal("data_a", Pins("V17 U17 Y17 W16 Y16 W15 W14 Y14 " 46 | "W13 V12 V13 T14 T15 V15 T16 V16"), 47 | ), 48 | Subsignal("data_b", Pins("T17 R16 R18 P16 P18 N17 R19 T20 " 49 | "T19 U20 V20 W20 W19 Y19 W18 Y18"), 50 | ), 51 | IOStandard("LVCMOS18") 52 | ), 53 | 54 | ("dac", 0, 55 | Subsignal("data", Pins("M19 M20 L19 L20 K19 J19 J20 H20 " 56 | "G19 G20 F19 F20 D20 D19"), 57 | Misc("SLEW=SLOW"), Drive(4)), 58 | Subsignal("wrt", Pins("M17"), Drive(8), Misc("SLEW=FAST")), 59 | Subsignal("sel", Pins("N16"), Drive(8), Misc("SLEW=FAST")), 60 | Subsignal("rst", Pins("N15"), Drive(8), Misc("SLEW=FAST")), 61 | Subsignal("clk", Pins("M18"), Drive(8), Misc("SLEW=FAST")), 62 | IOStandard("LVCMOS33") 63 | ), 64 | 65 | ("pwm", 0, Pins("T10"), IOStandard("LVCMOS18"), 66 | Drive(12), Misc("SLEW=FAST")), 67 | ("pwm", 1, Pins("T11"), IOStandard("LVCMOS18"), 68 | Drive(12), Misc("SLEW=FAST")), 69 | ("pwm", 2, Pins("P15"), IOStandard("LVCMOS18"), 70 | Drive(12), Misc("SLEW=FAST")), 71 | ("pwm", 3, Pins("U13"), IOStandard("LVCMOS18"), 72 | Drive(12), Misc("SLEW=FAST")), 73 | 74 | ("xadc", 0, 75 | Subsignal("p", Pins("C20 E17 B19 E18 K9")), 76 | Subsignal("n", Pins("B20 D18 A20 E19 L10")), 77 | IOStandard("LVCMOS33") 78 | ), 79 | 80 | ("exp", 0, 81 | Subsignal("p", Pins("G17 H16 J18 K17 L14 L16 K16 M14")), 82 | Subsignal("n", Pins("G18 H17 H18 K18 L15 L17 J16 M15")), 83 | IOStandard("LVCMOS33"), 84 | ), 85 | 86 | ("sata", 0, 87 | Subsignal("rx_p", Pins("T12")), 88 | Subsignal("rx_n", Pins("U12")), 89 | Subsignal("tx_p", Pins("U14")), 90 | Subsignal("tx_n", Pins("U15")), 91 | IOStandard("DIFF_SSTL18_I") 92 | ), 93 | 94 | ("sata", 1, 95 | Subsignal("rx_p", Pins("P14")), 96 | Subsignal("rx_n", Pins("R14")), 97 | Subsignal("tx_p", Pins("N18")), 98 | Subsignal("tx_n", Pins("P19")), 99 | IOStandard("DIFF_SSTL18_I") 100 | ), 101 | ] 102 | 103 | 104 | class Platform(XilinxPlatform): 105 | def __init__(self): 106 | XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, 107 | toolchain="vivado") 108 | -------------------------------------------------------------------------------- /migen/build/platforms/sinara/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/m-labs/migen/b92717a918c4d274d37f6eaff0c57ad689468173/migen/build/platforms/sinara/__init__.py -------------------------------------------------------------------------------- /migen/build/platforms/tinyfpga_b.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import TinyFpgaBProgrammer 4 | 5 | _io = [ 6 | ("usb", 0, 7 | Subsignal("d_p", Pins("A3")), 8 | Subsignal("d_n", Pins("A4")), 9 | IOStandard("LVCMOS33") 10 | ), 11 | 12 | ("spiflash", 0, 13 | Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), 14 | Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), 15 | Subsignal("mosi", Pins("G6"), IOStandard("LVCMOS33")), 16 | Subsignal("miso", Pins("H7"), IOStandard("LVCMOS33")) 17 | ), 18 | 19 | ("clk16", 0, Pins("B4"), IOStandard("LVCMOS33")) 20 | ] 21 | 22 | _connectors = [ 23 | # B2-J1, Pins 4-13 24 | # D9-C9, Pins 18-19, Pins 21-24 25 | # E8, Pin 20 (Input only) 26 | ("GPIO", "B2 A2 A1 B1 C1 D1 E1 G1 H1 J1 D9 C9 A9 A8 A7 A6"), 27 | ("GBIN", "E8") 28 | ] 29 | 30 | 31 | # Default peripherals 32 | serial = [ 33 | ("serial", 0, 34 | Subsignal("tx", Pins("GPIO:0")), 35 | Subsignal("rx", Pins("GPIO:1")), 36 | IOStandard("LVCMOS33") 37 | ) 38 | ] 39 | 40 | 41 | class Platform(LatticePlatform): 42 | default_clk_name = "clk16" 43 | default_clk_period = 62.5 44 | 45 | def __init__(self): 46 | LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, 47 | toolchain="icestorm") 48 | 49 | def create_programmer(self): 50 | return TinyFpgaBProgrammer() 51 | -------------------------------------------------------------------------------- /migen/build/platforms/tinyfpga_bx.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.lattice import LatticePlatform 3 | from migen.build.lattice.programmer import TinyProgProgrammer 4 | 5 | _io = [ 6 | ("user_led", 0, Pins("B3"), IOStandard("LVCMOS33")), 7 | 8 | ("usb", 0, 9 | Subsignal("d_p", Pins("B4")), 10 | Subsignal("d_n", Pins("A4")), 11 | Subsignal("pullup", Pins("A3")), 12 | IOStandard("LVCMOS33") 13 | ), 14 | 15 | ("spiflash", 0, 16 | Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), 17 | Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), 18 | Subsignal("mosi", Pins("G6"), IOStandard("LVCMOS33")), 19 | Subsignal("miso", Pins("H7"), IOStandard("LVCMOS33")), 20 | Subsignal("wp", Pins("H4"), IOStandard("LVCMOS33")), 21 | Subsignal("hold", Pins("J8"), IOStandard("LVCMOS33")) 22 | ), 23 | 24 | ("spiflash4x", 0, 25 | Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), 26 | Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), 27 | Subsignal("dq", Pins("G6 H7 H4 J8"), IOStandard("LVCMOS33")) 28 | ), 29 | 30 | ("clk16", 0, Pins("B2"), IOStandard("LVCMOS33")) 31 | ] 32 | 33 | _connectors = [ 34 | # A2-H2, Pins 1-13 35 | # H9-A6, Pins 14-24 36 | # G1-J2, Pins 25-31 37 | ("GPIO", "A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2 H9 D9 D8 C9 A9 B8 A8 B7 A7 B6 A6"), 38 | ("EXTRA", "G1 J3 J4 G9 J9 E8 J2") 39 | ] 40 | 41 | 42 | # Default peripherals 43 | serial = [ 44 | ("serial", 0, 45 | Subsignal("tx", Pins("GPIO:0")), 46 | Subsignal("rx", Pins("GPIO:1")), 47 | IOStandard("LVCMOS33") 48 | ) 49 | ] 50 | 51 | 52 | class Platform(LatticePlatform): 53 | default_clk_name = "clk16" 54 | default_clk_period = 62.5 55 | 56 | def __init__(self): 57 | LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, 58 | toolchain="icestorm") 59 | 60 | def create_programmer(self): 61 | return TinyProgProgrammer() 62 | -------------------------------------------------------------------------------- /migen/build/platforms/upduino_v1.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.build.generic_platform import * 3 | from migen.build.lattice import LatticePlatform 4 | from migen.build.lattice.programmer import IceStormProgrammer 5 | 6 | 7 | _io = [ 8 | ("rgb_led", 0, 9 | Subsignal("r", Pins("41")), 10 | Subsignal("g", Pins("40")), 11 | Subsignal("b", Pins("39")), 12 | IOStandard("LVCMOS33") 13 | ), 14 | ] 15 | 16 | spiflash = [ 17 | # Only usable in PROG FLASH mode - see JP2 header 18 | ("spiflash", 0, 19 | Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), 20 | Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), 21 | Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")), 22 | Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")), 23 | ), 24 | ] 25 | 26 | 27 | _connectors = [ 28 | 29 | # JP5's pinout is all Free, except 1 (3.3V) and 2 (GND). 30 | # 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 | ("JP5", "23 25 26 27 32 35 31 37 34 43 36 42 38 28"), 32 | 33 | # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 34 | ("JP6", "12 21 13 19 18 11 9 6 44 4 3 48 45 47 46 2"), 35 | ] 36 | 37 | class MachClock(Module): 38 | def __init__(self, period, out): 39 | self.specials += Instance("SB_HFOSC", 40 | i_CLKHFPU=C(1), 41 | i_CLKHFEN=C(1), 42 | o_CLKHF=out 43 | ) 44 | 45 | class HfoscRouting(Module): 46 | def __init__(self): 47 | self.hfosc_used = False # Only one default clock, 48 | self.mach_clk_sig = Signal() 49 | 50 | def mk_clk(self, name, clk_period): 51 | if not self.hfosc_used: 52 | self.mach_clk_sig.name_override = name 53 | self.submodules.mclk = MachClock(clk_period, self.mach_clk_sig) 54 | self.hfosc_used = True 55 | else: 56 | raise ConstraintError 57 | return self.mach_clk_sig 58 | 59 | class Platform(LatticePlatform): 60 | default_clk_name = "sb_hfosc" 61 | default_clk_period = 48 62 | 63 | def __init__(self): 64 | self.sb_hfosc_routing = HfoscRouting() # Internal oscillator routing. 65 | LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, 66 | toolchain="icestorm") 67 | 68 | def request(self, *args, **kwargs): 69 | try: 70 | sig = GenericPlatform.request(self, *args, **kwargs) 71 | except ConstraintError: 72 | # ICE40UP5K internal clock 73 | if args[0] == "sb_hfosc": 74 | # Do not add to self.constraint_manager.matched because we 75 | # don't want this signal to become part of the UCF. 76 | sig = self.sb_hfosc_routing.mk_clk("sb_hfosc", 48) 77 | return sig 78 | 79 | def do_finalize(self, f, *args, **kwargs): 80 | f += self.sb_hfosc_routing.get_fragment() 81 | 82 | # Handle cases where hfosc is default not default. 83 | if self.default_clk_name != "sb_hfosc": 84 | GenericPlatform.do_finalize(self, f, *args, **kwargs) 85 | 86 | if self.default_clk_name == "sb_hfosc": 87 | self.default_clk_period = 48 88 | -------------------------------------------------------------------------------- /migen/build/platforms/versa.py: -------------------------------------------------------------------------------- 1 | # This file is Copyright (c) 2013 Florent Kermarrec 2 | # License: BSD 3 | 4 | from migen.build.generic_platform import * 5 | from migen.build.lattice import LatticePlatform 6 | from migen.build.lattice.programmer import LatticeProgrammer 7 | 8 | 9 | _io = [ 10 | ("clk100", 0, Pins("L5"), IOStandard("LVDS25")), 11 | ("rst_n", 0, Pins("A21"), IOStandard("LVCMOS33")), 12 | 13 | ("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")), 14 | ("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")), 15 | ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33")), 16 | ("user_led", 3, Pins("U19"), IOStandard("LVCMOS33")), 17 | ("user_led", 4, Pins("W19"), IOStandard("LVCMOS33")), 18 | ("user_led", 5, Pins("V19"), IOStandard("LVCMOS33")), 19 | ("user_led", 6, Pins("AB20"), IOStandard("LVCMOS33")), 20 | ("user_led", 7, Pins("AA20"), IOStandard("LVCMOS33")), 21 | 22 | ("user_dip_btn", 0, Pins("J7"), IOStandard("LVCMOS15")), 23 | ("user_dip_btn", 1, Pins("J6"), IOStandard("LVCMOS15")), 24 | ("user_dip_btn", 2, Pins("H2"), IOStandard("LVCMOS15")), 25 | ("user_dip_btn", 3, Pins("H3"), IOStandard("LVCMOS15")), 26 | ("user_dip_btn", 4, Pins("J3"), IOStandard("LVCMOS15")), 27 | ("user_dip_btn", 5, Pins("K3"), IOStandard("LVCMOS15")), 28 | ("user_dip_btn", 6, Pins("J2"), IOStandard("LVCMOS15")), 29 | ("user_dip_btn", 7, Pins("J1"), IOStandard("LVCMOS15")), 30 | 31 | ("serial", 0, 32 | Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")), # X4 IO0 33 | Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")), # X4 IO1 34 | ), 35 | 36 | ("eth_clocks", 0, 37 | Subsignal("tx", Pins("C12")), 38 | Subsignal("gtx", Pins("M2")), 39 | Subsignal("rx", Pins("L4")), 40 | IOStandard("LVCMOS33") 41 | ), 42 | ("eth", 0, 43 | Subsignal("rst_n", Pins("L3")), 44 | Subsignal("mdio", Pins("L2")), 45 | Subsignal("mdc", Pins("V4")), 46 | Subsignal("rx_dv", Pins("M1")), 47 | Subsignal("rx_er", Pins("M4")), 48 | Subsignal("rx_data", Pins("M5 N1 N6 P6 T2 R2 P5 P3")), 49 | Subsignal("tx_en", Pins("V3")), 50 | Subsignal("tx_data", Pins("V1 U1 R3 P1 N5 N3 N4 N2")), 51 | Subsignal("col", Pins("R1")), 52 | Subsignal("crs", Pins("P4")), 53 | IOStandard("LVCMOS33") 54 | ), 55 | 56 | ("eth_clocks", 1, 57 | Subsignal("tx", Pins("M21")), 58 | Subsignal("gtx", Pins("M19")), 59 | Subsignal("rx", Pins("N19")), 60 | IOStandard("LVCMOS33") 61 | ), 62 | ("eth", 1, 63 | Subsignal("rst_n", Pins("R21")), 64 | Subsignal("mdio", Pins("U16")), 65 | Subsignal("mdc", Pins("Y18")), 66 | Subsignal("rx_dv", Pins("U15")), 67 | Subsignal("rx_er", Pins("V20")), 68 | Subsignal("rx_data", Pins("AB17 AA17 R19 V21 T17 R18 W21 Y21")), 69 | Subsignal("tx_en", Pins("V22")), 70 | Subsignal("tx_data", Pins("W22 R16 P17 Y22 T21 U22 P20 U20")), 71 | Subsignal("col", Pins("N18")), 72 | Subsignal("crs", Pins("P19")), 73 | IOStandard("LVCMOS33") 74 | ), 75 | ] 76 | 77 | 78 | class Platform(LatticePlatform): 79 | default_clk_name = "clk100" 80 | default_clk_period = 10 81 | 82 | def __init__(self, **kwargs): 83 | LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io, **kwargs) 84 | 85 | def do_finalize(self, fragment): 86 | LatticePlatform.do_finalize(self, fragment) 87 | try: 88 | self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0) 89 | except ConstraintError: 90 | pass 91 | try: 92 | self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0) 93 | except ConstraintError: 94 | pass 95 | 96 | def create_programmer(self): 97 | return LatticeProgrammer() 98 | -------------------------------------------------------------------------------- /migen/build/platforms/ztex_115d.py: -------------------------------------------------------------------------------- 1 | from migen.build.generic_platform import * 2 | from migen.build.xilinx import XilinxPlatform 3 | 4 | 5 | _io = [ 6 | ("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")), 7 | ("clk_if", 0, Pins("K20"), IOStandard("LVCMOS33")), 8 | ("rst", 0, Pins("A18")), 9 | # PROG_B and DONE: AA1 U16 10 | 11 | ("fx2", 0, 12 | Subsignal("sloe", Pins("U15"), Drive(12)), # M1 13 | Subsignal("slrd", Pins("N22"), Drive(12)), 14 | Subsignal("slwr", Pins("M22"), Drive(12)), 15 | Subsignal("pktend", Pins("AB5"), Drive(12)), # CSO 16 | Subsignal("fifoadr", Pins("W17 Y18"), Drive(12)), # CCLK M0 17 | Subsignal("cont", Pins("G20")), 18 | Subsignal("fd", Pins("Y17 V13 W13 AA8 AB8 W6 Y6 Y9 " 19 | "V21 V22 U20 U22 R20 R22 P18 P19")), 20 | Subsignal("flag", Pins("F20 F19 F18 AB17")), # - - - CSI/MOSI 21 | Subsignal("rdy25", Pins("M21 K21 K22 J21")), 22 | Subsignal("ctl35", Pins("D19 E20 N20")), 23 | Subsignal("int45", Pins("C18 V17")), 24 | Subsignal("pc", Pins("G20 T10 V5 AB9 G19 H20 H19 H18")), 25 | # - DOUT/BUSY INIT_B RDWR_B DO CS CLK DI 26 | IOStandard("LVCMOS33")), 27 | 28 | ("mm", 0, 29 | Subsignal("a", Pins("M20 M19 M18 N19 T19 T21 T22 R19 ", 30 | "P20 P21 P22 J22 H21 H22 G22 F21")), 31 | Subsignal("d", Pins("D20 C20 C19 B21 B20 J19 K19 L19"), Drive(2)), 32 | Subsignal("wr_n", Pins("C22")), 33 | Subsignal("rd_n", Pins("D21")), 34 | Subsignal("psen_n", Pins("D22")), 35 | IOStandard("LVCMOS33")), 36 | 37 | ("serial", 0, 38 | Subsignal("tx", Pins("B22"), Misc("SLEW=QUIETIO")), 39 | Subsignal("rx", Pins("A21"), Misc("PULLDOWN")), 40 | IOStandard("LVCMOS33")), 41 | 42 | ("ddram_clock", 0, 43 | Subsignal("p", Pins("F2"), Misc("OUT_TERM=UNTUNED_50")), 44 | Subsignal("n", Pins("F1"), Misc("OUT_TERM=UNTUNED_50")), 45 | IOStandard("SSTL18_II")), 46 | 47 | ("ddram", 0, 48 | Subsignal("dqs", Pins("L3 T2"), IOStandard("SSTL18_II"), # DIFF_ 49 | Misc("IN_TERM=NONE")), 50 | Subsignal("dqs_n", Pins("L1 T1"), IOStandard("SSTL18_II"), # DIFF_ 51 | Misc("IN_TERM=NONE")), 52 | Subsignal("dm", Pins("H1 H2"), Misc("OUT_TERM=UNTUNED_50")), 53 | Subsignal("dq", Pins("M1 M2 J1 K2 J3 K1 N3 N1 " 54 | "U1 U3 P1 R3 P2 R1 V2 V1"), Misc("IN_TERM=NONE")), 55 | Subsignal("ras_n", Pins("N4"), Misc("OUT_TERM=UNTUNED_50")), 56 | Subsignal("cas_n", Pins("P3"), Misc("OUT_TERM=UNTUNED_50")), 57 | Subsignal("a", Pins("M5 K6 B1 J4 L4 K3 M4 K5 G3 G1 K4 C3 C1"), 58 | Misc("OUT_TERM=UNTUNED_50")), 59 | Subsignal("ba", Pins("E3 E1 D1"), Misc("OUT_TERM=UNTUNED_50")), 60 | Subsignal("cke", Pins("J6"), Misc("OUT_TERM=UNTUNED_50")), 61 | Subsignal("cs_n", Pins("H6")), # NC! 62 | Subsignal("odt", Pins("M3"), Misc("OUT_TERM=UNTUNED_50")), 63 | Subsignal("we_n", Pins("D2")), 64 | Subsignal("rzq", Pins("AA2")), 65 | Subsignal("zio", Pins("Y2")), 66 | IOStandard("SSTL18_II")), 67 | 68 | ("i2c", 0, 69 | Subsignal("scl", Pins("F22")), 70 | Subsignal("sda", Pins("E22")), 71 | IOStandard("LVCMOS33")), 72 | 73 | ("sd", 0, 74 | Subsignal("sck", Pins("H11")), 75 | Subsignal("d3", Pins("H14")), 76 | Subsignal("d", Pins("P10")), 77 | Subsignal("d1", Pins("T18")), 78 | Subsignal("d2", Pins("R17")), 79 | Subsignal("cmd", Pins("H13")), 80 | IOStandard("LVCMOS33")), 81 | 82 | ] 83 | 84 | 85 | class Platform(XilinxPlatform): 86 | default_clk_name = "clk_if" 87 | default_clk_period = 20 88 | 89 | def __init__(self): 90 | XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io) 91 | self.add_platform_command(""" 92 | CONFIG VCCAUX = "2.5"; 93 | """) 94 | 95 | def do_finalize(self, fragment): 96 | XilinxPlatform.do_finalize(self, fragment) 97 | 98 | try: 99 | clk_if = self.lookup_request("clk_if") 100 | clk_fx = self.lookup_request("clk_fx") 101 | self.add_platform_command(""" 102 | NET "{clk_if}" TNM_NET = "GRPclk_if"; 103 | NET "{clk_fx}" TNM_NET = "GRPclk_fx"; 104 | TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%; 105 | TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%; 106 | TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY; 107 | TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY; 108 | """, clk_if=clk_if, clk_fx=clk_fx) 109 | except ConstraintError: 110 | pass 111 | -------------------------------------------------------------------------------- /migen/build/quicklogic/__init__.py: -------------------------------------------------------------------------------- 1 | from migen.build.quicklogic.platform import QuicklogicPlatform 2 | from migen.build.quicklogic.programmer import JLinkProgrammer, OpenOCD 3 | 4 | -------------------------------------------------------------------------------- /migen/build/quicklogic/platform.py: -------------------------------------------------------------------------------- 1 | import os 2 | import shutil 3 | 4 | from migen.build.generic_platform import GenericPlatform 5 | from migen.build.quicklogic import quicklogic 6 | 7 | class QuicklogicPlatform(GenericPlatform): 8 | bitstream_ext = ".bit" 9 | 10 | def __init__(self, *args, toolchain="quicklogic", **kwargs): 11 | GenericPlatform.__init__(self, *args, **kwargs) 12 | self.edifs = set() 13 | self.ips = set() 14 | 15 | self.board_type = "ql-eos-s3_wlcsp" 16 | if self.device == "chandalar": 17 | self.part = "PD64" 18 | elif self.device == "quickfeather": 19 | self.part = "PU64" 20 | else: 21 | raise ValueError("Unknown device") 22 | 23 | if toolchain == "quicklogic": 24 | self.toolchain = quicklogic.QuicklogicToolchain() 25 | else: 26 | raise ValueError("Unknown toolchain") 27 | 28 | def add_edif(self, filename): 29 | self.edifs.add((os.path.abspath(filename))) 30 | 31 | def add_ip(self, filename): 32 | self.ips.add((os.path.abspath(filename))) 33 | 34 | def copy_ips(self, build_dir, subdir="ip"): 35 | copied_ips = set() 36 | 37 | target = os.path.join(build_dir, subdir) 38 | os.makedirs(target, exist_ok=True) 39 | for filename in self.ips: 40 | path = os.path.join(subdir, os.path.basename(filename)) 41 | dest = os.path.join(build_dir, path) 42 | shutil.copyfile(filename, dest) 43 | copied_ips.add(path) 44 | 45 | return copied_ips 46 | 47 | def get_verilog(self, *args, special_overrides=dict(), **kwargs): 48 | return GenericPlatform.get_verilog(self, *args, 49 | attr_translate=self.toolchain.attr_translate, **kwargs) 50 | 51 | def get_edif(self, fragment, **kwargs): 52 | return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Quicklogic", self.device, **kwargs) 53 | 54 | def build(self, *args, **kwargs): 55 | return self.toolchain.build(self, *args, **kwargs) 56 | 57 | def add_period_constraint(self, clk, period): 58 | if hasattr(clk, "p"): 59 | clk = clk.p 60 | self.toolchain.add_period_constraint(self, clk, period) 61 | 62 | def add_false_path_constraint(self, from_, to): 63 | if hasattr(from_, "p"): 64 | from_ = from_.p 65 | if hasattr(to, "p"): 66 | to = to.p 67 | self.toolchain.add_false_path_constraint(self, from_, to) 68 | 69 | def do_finalize(self, fragment, *args, **kwargs): 70 | super().do_finalize(fragment, *args, **kwargs) 71 | -------------------------------------------------------------------------------- /migen/build/quicklogic/programmer.py: -------------------------------------------------------------------------------- 1 | import os 2 | import sys 3 | import subprocess 4 | 5 | from migen.build.generic_programmer import GenericProgrammer 6 | 7 | # This programmer requires OpenOCD with support for eos-s3 8 | # it has not been merged with mainline yet, but is available at: 9 | # https://github.com/antmicro/openocd/tree/eos-s3-support 10 | class OpenOCD(GenericProgrammer): 11 | 12 | def __init__(self, flash_proxy_basename=None): 13 | GenericProgrammer.__init__(self, flash_proxy_basename) 14 | 15 | def load_bitstream(self, bitstream_file): 16 | bitstream_folder = os.path.dirname(bitstream_file) 17 | top_path = bitstream_folder + "/top.cfg" 18 | subprocess.call(["python", "-m", "quicklogic_fasm.bitstream_to_openocd", bitstream_file, top_path]) 19 | try: 20 | openocd_proc = subprocess.Popen(["openocd", "-s", "tcl", 21 | "-f", "interface/ftdi/antmicro-ftdi-adapter.cfg", 22 | "-f", "interface/ftdi/swd-resistor-hack.cfg", 23 | "-f", "board/quicklogic_quickfeather.cfg", 24 | "-f", top_path]) 25 | gdb_commands = ["tar rem :3333", "monitor reset halt", "monitor load_bitstream"] 26 | gdb_output_path = bitstream_folder + "/gdb.commands" 27 | with open(gdb_output_path, 'w') as f: 28 | f.write("\n".join(gdb_commands)) 29 | path_env = os.environ['PATH'].split(":") 30 | import glob 31 | gdb = None 32 | for path in path_env: 33 | gdb_glob = glob.glob(path + '/arm-*-eabi-gdb') 34 | if len(gdb_glob): 35 | gdb = gdb_glob[0].strip() 36 | break; 37 | if gdb is None: 38 | raise Exception("No arm-*-eabi-gdb found in PATH") 39 | subprocess.call([gdb, "-x", gdb_output_path]) 40 | except Exception as e: 41 | openocd_proc.kill() 42 | raise e 43 | 44 | class JLinkProgrammer(GenericProgrammer): 45 | 46 | def __init__(self, flash_proxy_basename=None): 47 | GenericProgrammer.__init__(self, flash_proxy_basename) 48 | 49 | def load_bitstream(self, bitstream_file): 50 | bitstream_folder = os.path.dirname(bitstream_file) 51 | jlink_output_path = bitstream_folder + "/top.jlink" 52 | jlink_output_reset_path = bitstream_folder + "/top_reset.jlink" 53 | subprocess.call(["python", "-m", "quicklogic_fasm.bitstream_to_jlink", bitstream_file, jlink_output_path]) 54 | with open(jlink_output_path, 'r') as f: 55 | with open(jlink_output_reset_path,'w') as f2: # add reset command at the beginning 56 | f2.write("r\n") 57 | f2.write(f.read()) 58 | 59 | subprocess.call(["JLinkExe", "-Device", "Cortex-M4", "-If", "SWD", "-Speed", "4000", "-commandFile", jlink_output_reset_path]) 60 | -------------------------------------------------------------------------------- /migen/build/tools.py: -------------------------------------------------------------------------------- 1 | import os 2 | import struct 3 | import re 4 | import subprocess 5 | import sys 6 | import ctypes 7 | 8 | 9 | def language_by_filename(name): 10 | extension = name.rsplit(".")[-1] 11 | if extension in ["v", "vh", "vo", "sv", "svh"]: 12 | return "verilog" 13 | if extension in ["vhd", "vhdl", "vho"]: 14 | return "vhdl" 15 | return None 16 | 17 | 18 | def write_to_file(filename, contents, force_unix=False): 19 | newline = None 20 | if force_unix: 21 | newline = "\n" 22 | with open(filename, "w", newline=newline) as f: 23 | f.write(contents) 24 | 25 | 26 | def sub_rules(line, rules, max_matches=1): 27 | for pattern, color in rules: 28 | line, matches = re.subn(pattern, color, line, max_matches) 29 | max_matches -= matches 30 | if not max_matches: 31 | break 32 | return line 33 | 34 | 35 | def subprocess_call_filtered(command, rules, *, max_matches=1, **kwargs): 36 | with subprocess.Popen(command, stdout=subprocess.PIPE, 37 | universal_newlines=True, bufsize=1, 38 | **kwargs) as proc: 39 | with open(proc.stdout.fileno(), errors="ignore", closefd=False) as stdout: 40 | for line in stdout: 41 | print(sub_rules(line, rules, max_matches), end="") 42 | return proc.wait() 43 | -------------------------------------------------------------------------------- /migen/build/xilinx/__init__.py: -------------------------------------------------------------------------------- 1 | from migen.build.xilinx.platform import XilinxPlatform 2 | from migen.build.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept 3 | -------------------------------------------------------------------------------- /migen/build/xilinx/platform.py: -------------------------------------------------------------------------------- 1 | import os 2 | import shutil 3 | 4 | from migen.build.generic_platform import GenericPlatform 5 | from migen.build.xilinx import common, vivado, ise, symbiflow 6 | 7 | 8 | class XilinxPlatform(GenericPlatform): 9 | bitstream_ext = ".bit" 10 | 11 | def __init__(self, *args, toolchain="ise", **kwargs): 12 | GenericPlatform.__init__(self, *args, **kwargs) 13 | self.edifs = set() 14 | self.ips = set() 15 | if toolchain == "ise": 16 | self.toolchain = ise.XilinxISEToolchain() 17 | elif toolchain == "vivado": 18 | self.toolchain = vivado.XilinxVivadoToolchain() 19 | elif toolchain == "symbiflow": 20 | self.toolchain = symbiflow.SymbiflowToolchain() 21 | else: 22 | raise ValueError("Unknown toolchain") 23 | 24 | def add_edif(self, filename): 25 | self.edifs.add((os.path.abspath(filename))) 26 | 27 | def add_ip(self, filename): 28 | self.ips.add((os.path.abspath(filename))) 29 | 30 | def copy_ips(self, build_dir, subdir="ip"): 31 | copied_ips = set() 32 | 33 | target = os.path.join(build_dir, subdir) 34 | os.makedirs(target, exist_ok=True) 35 | for filename in self.ips: 36 | path = os.path.join(subdir, os.path.basename(filename)) 37 | dest = os.path.join(build_dir, path) 38 | shutil.copyfile(filename, dest) 39 | copied_ips.add(path) 40 | 41 | return copied_ips 42 | 43 | def get_verilog(self, *args, special_overrides=dict(), **kwargs): 44 | so = dict(common.xilinx_special_overrides) 45 | if self.device[:3] == "xc6": 46 | so.update(common.xilinx_s6_special_overrides) 47 | if self.device[:3] == "xc7": 48 | so.update(common.xilinx_s7_special_overrides) 49 | if self.device[:4] == "xcku": 50 | so.update(common.xilinx_ku_special_overrides) 51 | so.update(special_overrides) 52 | return GenericPlatform.get_verilog(self, *args, 53 | special_overrides=so, attr_translate=self.toolchain.attr_translate, **kwargs) 54 | 55 | def get_edif(self, fragment, **kwargs): 56 | return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs) 57 | 58 | def build(self, *args, **kwargs): 59 | return self.toolchain.build(self, *args, **kwargs) 60 | 61 | def add_period_constraint(self, clk, period): 62 | if hasattr(clk, "p"): 63 | clk = clk.p 64 | self.toolchain.add_period_constraint(self, clk, period) 65 | 66 | def add_false_path_constraint(self, from_, to): 67 | if hasattr(from_, "p"): 68 | from_ = from_.p 69 | if hasattr(to, "p"): 70 | to = to.p 71 | self.toolchain.add_false_path_constraint(self, from_, to) 72 | 73 | def do_finalize(self, fragment, *args, **kwargs): 74 | # Do not create period constraint directly on default clock when using Symbiflow 75 | if not isinstance(self.toolchain, symbiflow.SymbiflowToolchain): 76 | super().do_finalize(fragment, *args, **kwargs) 77 | -------------------------------------------------------------------------------- /migen/fhdl/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/m-labs/migen/b92717a918c4d274d37f6eaff0c57ad689468173/migen/fhdl/__init__.py -------------------------------------------------------------------------------- /migen/fhdl/bitcontainer.py: -------------------------------------------------------------------------------- 1 | from migen.fhdl import structure as f 2 | 3 | 4 | __all__ = ["log2_int", "bits_for", "value_bits_sign"] 5 | 6 | 7 | def log2_int(n, need_pow2=True): 8 | if n == 0: 9 | return 0 10 | r = (n - 1).bit_length() 11 | if need_pow2 and (1 << r) != n: 12 | raise ValueError("Not a power of 2") 13 | return r 14 | 15 | 16 | def bits_for(n, require_sign_bit=False): 17 | if n > 0: 18 | r = log2_int(n + 1, False) 19 | else: 20 | require_sign_bit = True 21 | r = log2_int(-n, False) 22 | if require_sign_bit: 23 | r += 1 24 | return r 25 | 26 | 27 | def _bitwise_binary_bits_sign(a, b): 28 | if not a[1] and not b[1]: 29 | # both operands unsigned 30 | return max(a[0], b[0]), False 31 | elif a[1] and b[1]: 32 | # both operands signed 33 | return max(a[0], b[0]), True 34 | elif not a[1] and b[1]: 35 | # first operand unsigned (add sign bit), second operand signed 36 | return max(a[0] + 1, b[0]), True 37 | else: 38 | # first signed, second operand unsigned (add sign bit) 39 | return max(a[0], b[0] + 1), True 40 | 41 | 42 | def value_bits_sign(v): 43 | """Bit length and signedness of a value. 44 | 45 | Parameters 46 | ---------- 47 | v : Value 48 | 49 | Returns 50 | ------- 51 | int, bool 52 | Number of bits required to store `v` or available in `v`, followed by 53 | whether `v` has a sign bit (included in the bit count). 54 | 55 | Examples 56 | -------- 57 | >>> value_bits_sign(f.Signal(8)) 58 | 8, False 59 | >>> value_bits_sign(C(0xaa)) 60 | 8, False 61 | """ 62 | if isinstance(v, (f.Constant, f.Signal)): 63 | return v.nbits, v.signed 64 | elif isinstance(v, (f.ClockSignal, f.ResetSignal)): 65 | return 1, False 66 | elif isinstance(v, f._Operator): 67 | obs = list(map(value_bits_sign, v.operands)) 68 | if v.op == "+" or v.op == "-": 69 | if len(obs) == 1: 70 | if v.op == "-" and not obs[0][1]: 71 | return obs[0][0] + 1, True 72 | else: 73 | return obs[0] 74 | n, s = _bitwise_binary_bits_sign(*obs) 75 | return n + 1, s 76 | elif v.op == "*": 77 | if not obs[0][1] and not obs[1][1]: 78 | # both operands unsigned 79 | return obs[0][0] + obs[1][0], False 80 | elif obs[0][1] and obs[1][1]: 81 | # both operands signed 82 | return obs[0][0] + obs[1][0] - 1, True 83 | else: 84 | # one operand signed, the other unsigned (add sign bit) 85 | return obs[0][0] + obs[1][0] + 1 - 1, True 86 | elif v.op == "<<<": 87 | if obs[1][1]: 88 | extra = 2**(obs[1][0] - 1) - 1 89 | else: 90 | extra = 2**obs[1][0] - 1 91 | return obs[0][0] + extra, obs[0][1] 92 | elif v.op == ">>>": 93 | if obs[1][1]: 94 | extra = 2**(obs[1][0] - 1) 95 | else: 96 | extra = 0 97 | return obs[0][0] + extra, obs[0][1] 98 | elif v.op == "&" or v.op == "^" or v.op == "|": 99 | return _bitwise_binary_bits_sign(*obs) 100 | elif (v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" or 101 | v.op == ">" or v.op == ">="): 102 | return 1, False 103 | elif v.op == "~": 104 | return obs[0] 105 | elif v.op == "m": 106 | return _bitwise_binary_bits_sign(obs[1], obs[2]) 107 | else: 108 | raise TypeError 109 | elif isinstance(v, f._Slice): 110 | return v.stop - v.start, False 111 | elif isinstance(v, f._Part): 112 | return v.width, False 113 | elif isinstance(v, f.Cat): 114 | return sum(value_bits_sign(sv)[0] for sv in v.l), False 115 | elif isinstance(v, f.Replicate): 116 | return (value_bits_sign(v.v)[0])*v.n, False 117 | elif isinstance(v, f._ArrayProxy): 118 | bsc = list(map(value_bits_sign, v.choices)) 119 | return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc) 120 | else: 121 | raise TypeError("Can not calculate bit length of {} {}".format( 122 | type(v), v)) 123 | -------------------------------------------------------------------------------- /migen/fhdl/conv_output.py: -------------------------------------------------------------------------------- 1 | from operator import itemgetter 2 | 3 | 4 | class ConvOutput: 5 | def __init__(self): 6 | self.main_source = "" 7 | self.data_files = dict() 8 | 9 | def set_main_source(self, src): 10 | self.main_source = src 11 | 12 | def add_data_file(self, filename_base, content): 13 | filename = filename_base 14 | i = 1 15 | while filename in self.data_files: 16 | parts = filename_base.split(".", maxsplit=1) 17 | parts[0] += "_" + str(i) 18 | filename = ".".join(parts) 19 | i += 1 20 | self.data_files[filename] = content 21 | return filename 22 | 23 | def __str__(self): 24 | r = self.main_source + "\n" 25 | for filename, content in sorted(self.data_files.items(), 26 | key=itemgetter(0)): 27 | r += filename + ":\n" + content 28 | return r 29 | 30 | def write(self, main_filename): 31 | with open(main_filename, "w") as f: 32 | f.write(self.main_source) 33 | for filename, content in self.data_files.items(): 34 | with open(filename, "w") as f: 35 | f.write(content) 36 | -------------------------------------------------------------------------------- /migen/fhdl/decorators.py: -------------------------------------------------------------------------------- 1 | from migen.fhdl.structure import * 2 | from migen.fhdl.module import Module 3 | from migen.fhdl.tools import insert_reset, rename_clock_domain 4 | 5 | 6 | __all__ = ["CEInserter", "ResetInserter", "ClockDomainsRenamer", 7 | "ModuleTransformer"] 8 | 9 | 10 | class ModuleTransformer: 11 | # overload this in derived classes 12 | def transform_instance(self, i): 13 | pass 14 | 15 | # overload this in derived classes 16 | def transform_fragment(self, i, f): 17 | pass 18 | 19 | def wrap_class(self, victim): 20 | class Wrapped(victim): 21 | def __init__(i, *args, **kwargs): 22 | victim.__init__(i, *args, **kwargs) 23 | self.transform_instance(i) 24 | 25 | def get_fragment(i): 26 | f = victim.get_fragment(i) 27 | self.transform_fragment(i, f) 28 | return f 29 | 30 | Wrapped.__name__ = victim.__name__ 31 | Wrapped.__doc__ = victim.__doc__ 32 | Wrapped.__module__ = victim.__module__ 33 | return Wrapped 34 | 35 | def wrap_instance(self, victim): 36 | self.transform_instance(victim) 37 | orig_get_fragment = victim.get_fragment 38 | 39 | def get_fragment(): 40 | f = orig_get_fragment() 41 | self.transform_fragment(victim, f) 42 | return f 43 | 44 | victim.get_fragment = get_fragment 45 | return victim 46 | 47 | def __call__(self, victim): 48 | if isinstance(victim, Module): 49 | return self.wrap_instance(victim) 50 | else: 51 | return self.wrap_class(victim) 52 | 53 | 54 | class ControlInserter(ModuleTransformer): 55 | control_name = None # override this 56 | 57 | def __init__(self, clock_domains=None): 58 | self.clock_domains = clock_domains 59 | 60 | def transform_instance(self, i): 61 | if self.clock_domains is None: 62 | ctl = Signal(name=self.control_name) 63 | assert not hasattr(i, self.control_name) 64 | setattr(i, self.control_name, ctl) 65 | else: 66 | for cd in self.clock_domains: 67 | name = self.control_name + "_" + cd 68 | ctl = Signal(name=name) 69 | assert not hasattr(i, name) 70 | setattr(i, name, ctl) 71 | 72 | def transform_fragment(self, i, f): 73 | if self.clock_domains is None: 74 | if not f.sync: 75 | return 76 | if len(f.sync) > 1: 77 | raise ValueError("Control signal clock domains must be specified when module has more than one domain") 78 | cdn = list(f.sync.keys())[0] 79 | to_insert = [(getattr(i, self.control_name), cdn)] 80 | else: 81 | to_insert = [(getattr(i, self.control_name + "_" + cdn), cdn) 82 | for cdn in self.clock_domains] 83 | self.transform_fragment_insert(i, f, to_insert) 84 | 85 | 86 | class CEInserter(ControlInserter): 87 | control_name = "ce" 88 | 89 | def transform_fragment_insert(self, i, f, to_insert): 90 | for ce, cdn in to_insert: 91 | f.sync[cdn] = [If(ce, *f.sync[cdn])] 92 | 93 | 94 | class ResetInserter(ControlInserter): 95 | control_name = "reset" 96 | 97 | def transform_fragment_insert(self, i, f, to_insert): 98 | for reset, cdn in to_insert: 99 | f.sync[cdn] = insert_reset(reset, f.sync[cdn]) 100 | 101 | 102 | class ClockDomainsRenamer(ModuleTransformer): 103 | def __init__(self, cd_remapping): 104 | if isinstance(cd_remapping, str): 105 | cd_remapping = {"sys": cd_remapping} 106 | self.cd_remapping = cd_remapping 107 | 108 | def transform_fragment(self, i, f): 109 | for old, new in self.cd_remapping.items(): 110 | rename_clock_domain(f, old, new) 111 | -------------------------------------------------------------------------------- /migen/fhdl/tracer.py: -------------------------------------------------------------------------------- 1 | import inspect 2 | from sys import version_info 3 | from opcode import opname 4 | from collections import defaultdict 5 | 6 | # All opcodes are 2 bytes in length in Python 3.6 7 | def _bytecode_length_version_guard(old_len): 8 | return old_len if version_info[1] < 6 else 2 9 | 10 | _call_opcodes = { 11 | "CALL_FUNCTION" : _bytecode_length_version_guard(3), 12 | "CALL_FUNCTION_KW" : _bytecode_length_version_guard(3), 13 | } 14 | 15 | if version_info[1] < 6: 16 | _call_opcodes["CALL_FUNCTION_VAR"] = 3 17 | _call_opcodes["CALL_FUNCTION_VAR_KW"] = 3 18 | elif version_info[1] < 7: 19 | _call_opcodes["CALL_FUNCTION_EX"] = 2 20 | else: 21 | _call_opcodes["CALL_FUNCTION_EX"] = 2 22 | _call_opcodes["CALL_METHOD"] = 2 23 | _call_opcodes["CALL_METHOD_KW"] = 2 24 | _call_opcodes["CALL"] = 2 25 | _call_opcodes["CALL_KW"] = 2 26 | 27 | _load_build_opcodes = { 28 | "LOAD_GLOBAL" : _bytecode_length_version_guard(3), 29 | "LOAD_NAME" : _bytecode_length_version_guard(3), 30 | "LOAD_ATTR" : _bytecode_length_version_guard(3), 31 | "LOAD_FAST" : _bytecode_length_version_guard(3), 32 | "LOAD_DEREF" : _bytecode_length_version_guard(3), 33 | "DUP_TOP" : _bytecode_length_version_guard(1), 34 | "BUILD_LIST" : _bytecode_length_version_guard(3), 35 | "CACHE" : _bytecode_length_version_guard(3), 36 | "COPY" : _bytecode_length_version_guard(3), 37 | } 38 | 39 | 40 | def get_var_name(frame): 41 | code = frame.f_code 42 | call_index = frame.f_lasti 43 | while call_index > 0 and opname[code.co_code[call_index]] == "CACHE": 44 | call_index -= 2 45 | while True: 46 | call_opc = opname[code.co_code[call_index]] 47 | if call_opc in("EXTENDED_ARG",): 48 | call_index += 2 49 | else: 50 | break 51 | if call_opc not in _call_opcodes: 52 | return None 53 | index = call_index+_call_opcodes[call_opc] 54 | while True: 55 | opc = opname[code.co_code[index]] 56 | if opc == "STORE_NAME" or opc == "STORE_ATTR": 57 | name_index = int(code.co_code[index+1]) 58 | return code.co_names[name_index] 59 | elif opc == "STORE_FAST": 60 | name_index = int(code.co_code[index+1]) 61 | return code.co_varnames[name_index] 62 | elif opc == "STORE_DEREF": 63 | name_index = int(code.co_code[index+1]) 64 | if name_index < code.co_nlocals: 65 | return code.co_varnames[name_index] 66 | name_index -= code.co_nlocals 67 | if name_index < len(code.co_cellvars): 68 | return code.co_cellvars[name_index] 69 | name_index -= len(code.co_cellvars) 70 | return code.co_freevars[name_index] 71 | elif opc in _load_build_opcodes: 72 | index += _load_build_opcodes[opc] 73 | else: 74 | return None 75 | 76 | 77 | def remove_underscore(s): 78 | if len(s) > 2 and s[0] == "_" and s[1] != "_": 79 | s = s[1:] 80 | return s 81 | 82 | 83 | def get_obj_var_name(override=None, default=None): 84 | if override: 85 | return override 86 | 87 | frame = inspect.currentframe().f_back 88 | # We can be called via derived classes. Go back the stack frames 89 | # until we reach the first class that does not inherit from us. 90 | ourclass = frame.f_locals["self"].__class__ 91 | while "self" in frame.f_locals and isinstance(frame.f_locals["self"], ourclass): 92 | frame = frame.f_back 93 | 94 | vn = get_var_name(frame) 95 | if vn is None: 96 | vn = default 97 | else: 98 | vn = remove_underscore(vn) 99 | return vn 100 | 101 | name_to_idx = defaultdict(int) 102 | classname_to_objs = dict() 103 | 104 | 105 | def index_id(l, obj): 106 | for n, e in enumerate(l): 107 | if id(e) == id(obj): 108 | return n 109 | raise ValueError 110 | 111 | 112 | def trace_back(varname=None): 113 | l = [] 114 | frame = inspect.currentframe().f_back.f_back 115 | while frame is not None: 116 | if varname is None: 117 | varname = get_var_name(frame) 118 | if varname is not None: 119 | varname = remove_underscore(varname) 120 | l.insert(0, (varname, name_to_idx[varname])) 121 | name_to_idx[varname] += 1 122 | 123 | try: 124 | obj = frame.f_locals["self"] 125 | except KeyError: 126 | obj = None 127 | if hasattr(obj, "__del__"): 128 | obj = None 129 | 130 | if obj is None: 131 | if varname is not None: 132 | coname = frame.f_code.co_name 133 | if coname == "": 134 | modules = frame.f_globals["__name__"] 135 | modules = modules.split(".") 136 | coname = modules[len(modules)-1] 137 | coname = remove_underscore(coname) 138 | l.insert(0, (coname, name_to_idx[coname])) 139 | name_to_idx[coname] += 1 140 | else: 141 | classname = obj.__class__.__name__.lower() 142 | try: 143 | objs = classname_to_objs[classname] 144 | except KeyError: 145 | classname_to_objs[classname] = [obj] 146 | idx = 0 147 | else: 148 | try: 149 | idx = index_id(objs, obj) 150 | except ValueError: 151 | idx = len(objs) 152 | objs.append(obj) 153 | classname = remove_underscore(classname) 154 | l.insert(0, (classname, idx)) 155 | 156 | varname = None 157 | frame = frame.f_back 158 | return l 159 | -------------------------------------------------------------------------------- /migen/genlib/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/m-labs/migen/b92717a918c4d274d37f6eaff0c57ad689468173/migen/genlib/__init__.py -------------------------------------------------------------------------------- /migen/genlib/coding.py: -------------------------------------------------------------------------------- 1 | """ 2 | Encoders and decoders between binary and one-hot representation 3 | """ 4 | 5 | from migen.fhdl.structure import * 6 | from migen.fhdl.module import Module 7 | 8 | 9 | class Encoder(Module): 10 | """Encode one-hot to binary 11 | 12 | If `n` is low, the `o` th bit in `i` is asserted, else none or 13 | multiple bits are asserted. 14 | 15 | Parameters 16 | ---------- 17 | width : int 18 | Bit width of the input 19 | 20 | Attributes 21 | ---------- 22 | i : Signal(width), in 23 | One-hot input 24 | o : Signal(max=width), out 25 | Encoded binary 26 | n : Signal(1), out 27 | Invalid, either none or multiple input bits are asserted 28 | """ 29 | def __init__(self, width): 30 | self.i = Signal(width) # one-hot 31 | self.o = Signal(max=max(2, width)) # binary 32 | self.n = Signal() # invalid: none or multiple 33 | act = dict((1< 1: 19 | cases = {} 20 | for i in range(n): 21 | switch = [] 22 | for j in reversed(range(i+1, i+n)): 23 | t = j % n 24 | switch = [ 25 | If(self.request[t], 26 | self.grant.eq(t) 27 | ).Else( 28 | *switch 29 | ) 30 | ] 31 | if self.switch_policy == SP_WITHDRAW: 32 | case = [If(~self.request[i], *switch)] 33 | else: 34 | case = switch 35 | cases[i] = case 36 | statement = Case(self.grant, cases) 37 | if self.switch_policy == SP_CE: 38 | statement = If(self.ce, statement) 39 | self.sync += statement 40 | else: 41 | self.comb += self.grant.eq(0) 42 | -------------------------------------------------------------------------------- /migen/genlib/sort.py: -------------------------------------------------------------------------------- 1 | from migen.fhdl.structure import * 2 | from migen.fhdl.module import Module 3 | 4 | 5 | class BitonicSort(Module): 6 | """Combinatorial sorting network 7 | 8 | The Bitonic sort is implemented as a combinatorial sort using 9 | comparators and multiplexers. Its asymptotic complexity (in terms of 10 | number of comparators/muxes) is O(n log(n)**2), like mergesort or 11 | shellsort. 12 | 13 | http://www.dps.uibk.ac.at/~cosenza/teaching/gpu/sort-batcher.pdf 14 | 15 | http://www.inf.fh-flensburg.de/lang/algorithmen/sortieren/bitonic/bitonicen.htm 16 | 17 | http://www.myhdl.org/doku.php/cookbook:bitonic 18 | 19 | Parameters 20 | ---------- 21 | n : int 22 | Number of inputs and output signals. 23 | m : int 24 | Bit width of inputs and outputs. Or a tuple of `(m, signed)`. 25 | ascending : bool 26 | Sort direction. `True` if input is to be sorted ascending, 27 | `False` for descending. Defaults to ascending. 28 | 29 | Attributes 30 | ---------- 31 | i : list of Signals, in 32 | Input values, each `m` wide. 33 | o : list of Signals, out 34 | Output values, sorted, each `m` bits wide. 35 | """ 36 | def __init__(self, n, m, ascending=True): 37 | self.i = [Signal(m) for i in range(n)] 38 | self.o = [Signal(m) for i in range(n)] 39 | self._sort(self.i, self.o, int(ascending), m) 40 | 41 | def _sort_two(self, i0, i1, o0, o1, dir): 42 | self.comb += [ 43 | o0.eq(i0), 44 | o1.eq(i1), 45 | If(dir == (i0 > i1), 46 | o0.eq(i1), 47 | o1.eq(i0), 48 | )] 49 | 50 | def _merge(self, i, o, dir, m): 51 | n = len(i) 52 | k = n//2 53 | if n > 1: 54 | t = [Signal(m) for j in range(n)] 55 | for j in range(k): 56 | self._sort_two(i[j], i[j + k], t[j], t[j + k], dir) 57 | self._merge(t[:k], o[:k], dir, m) 58 | self._merge(t[k:], o[k:], dir, m) 59 | else: 60 | self.comb += o[0].eq(i[0]) 61 | 62 | def _sort(self, i, o, dir, m): 63 | n = len(i) 64 | k = n//2 65 | if n > 1: 66 | t = [Signal(m) for j in range(n)] 67 | self._sort(i[:k], t[:k], 1, m) # ascending 68 | self._sort(i[k:], t[k:], 0, m) # descending 69 | self._merge(t, o, dir, m) 70 | else: 71 | self.comb += o[0].eq(i[0]) 72 | -------------------------------------------------------------------------------- /migen/sim/__init__.py: -------------------------------------------------------------------------------- 1 | from migen.sim.core import Simulator, run_simulation, passive 2 | -------------------------------------------------------------------------------- /migen/sim/vcd.py: -------------------------------------------------------------------------------- 1 | from itertools import count 2 | import tempfile 3 | import os 4 | from collections import OrderedDict 5 | import shutil 6 | 7 | from migen.fhdl.namer import build_namespace 8 | 9 | 10 | def vcd_codes(): 11 | codechars = [chr(i) for i in range(33, 127)] 12 | for n in count(): 13 | q, r = divmod(n, len(codechars)) 14 | code = codechars[r] 15 | while q > 0: 16 | q, r = divmod(q, len(codechars)) 17 | code = codechars[r] + code 18 | yield code 19 | 20 | 21 | class VCDWriter: 22 | def __init__(self, filename, module_name=None): 23 | self.filename = filename 24 | self.module_name = module_name 25 | self.buffer_file = tempfile.TemporaryFile( 26 | dir=os.path.dirname(filename), mode="w+") 27 | self.codegen = vcd_codes() 28 | self.codes = OrderedDict() 29 | self.signal_values = dict() 30 | self.t = 0 31 | 32 | def _get_code(self, signal): 33 | try: 34 | code = self.codes[signal] 35 | except KeyError: 36 | code = next(self.codegen) 37 | self.codes[signal] = code 38 | return code 39 | 40 | def _write_primitive_value(self, f, signal, value): 41 | l = len(signal) 42 | if value < 0: 43 | value += 2**l 44 | if l > 1: 45 | fmtstr = "b{:0" + str(l) + "b} {}\n" 46 | else: 47 | fmtstr = "{}{}\n" 48 | code = self._get_code(signal) 49 | f.write(fmtstr.format(value, code)) 50 | 51 | def _write_enum_value(self, f, signal, value): 52 | val = "b" 53 | for c in signal._enumeration[value].encode(): 54 | val += "{:08b}".format(c) 55 | code = self._get_code(signal) 56 | f.write("{} {}\n".format(val, code)) 57 | 58 | def _write_value(self, f, signal, value): 59 | if hasattr(signal, "_enumeration"): 60 | self._write_enum_value(self.buffer_file, signal, value) 61 | else: 62 | self._write_primitive_value(self.buffer_file, signal, value) 63 | 64 | def set(self, signal, value): 65 | if signal not in self.signal_values or self.signal_values[signal] != value: 66 | self._write_value(self.buffer_file, signal, value) 67 | self.signal_values[signal] = value 68 | 69 | def delay(self, delay): 70 | self.t += delay 71 | self.buffer_file.write("#{}\n".format(self.t)) 72 | 73 | def close(self): 74 | out = open(self.filename, "w") 75 | try: 76 | if self.module_name: 77 | out.write("$scope module {name} $end\n".format(name=self.module_name)) 78 | ns = build_namespace(self.codes.keys()) 79 | for signal, code in self.codes.items(): 80 | name = ns.get_name(signal) 81 | if hasattr(signal, "_enumeration"): 82 | size = max([len(v) for v in signal._enumeration.values()])*8 83 | else: 84 | size = len(signal) 85 | out.write("$var wire {size} {code} {name} $end\n" 86 | .format(name=name, code=code, size=size)) 87 | if self.module_name: 88 | out.write("$enddefinitions $end\n") 89 | out.write("$dumpvars\n") 90 | for signal in self.codes.keys(): 91 | self._write_value(out, signal, signal.reset.value) 92 | out.write("$end\n") 93 | out.write("#0\n") 94 | 95 | self.buffer_file.seek(0) 96 | shutil.copyfileobj(self.buffer_file, out) 97 | self.buffer_file.close() 98 | finally: 99 | out.close() 100 | 101 | 102 | class DummyVCDWriter: 103 | def set(self, signal, value): 104 | pass 105 | 106 | def delay(self, delay): 107 | pass 108 | 109 | def close(self): 110 | pass 111 | -------------------------------------------------------------------------------- /migen/test/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/m-labs/migen/b92717a918c4d274d37f6eaff0c57ad689468173/migen/test/__init__.py -------------------------------------------------------------------------------- /migen/test/support.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.fhdl import verilog 3 | 4 | 5 | class SimCase: 6 | def setUp(self, *args, **kwargs): 7 | self.tb = self.TestBench(*args, **kwargs) 8 | 9 | def test_to_verilog(self): 10 | verilog.convert(self.tb) 11 | 12 | def run_with(self, generator): 13 | run_simulation(self.tb, generator) 14 | -------------------------------------------------------------------------------- /migen/test/test_bitslip.py: -------------------------------------------------------------------------------- 1 | import unittest 2 | import random 3 | 4 | from migen import * 5 | from migen.genlib.misc import BitSlip 6 | 7 | 8 | class BitSlipModel: 9 | def __init__(self, data_width, latency): 10 | self.data_width = data_width 11 | self.latency = latency 12 | 13 | def simulate(self, bitslip, sequence): 14 | # prepare sequence for simulation 15 | s = [0]*self.latency 16 | for d in sequence: 17 | s.append(d) 18 | # simulate bitslip 19 | r = [] 20 | for i in range(len(s)-1): 21 | v = (s[i+1] << self.data_width) | s[i] 22 | v = v >> bitslip 23 | v &= 2**self.data_width-1 24 | r.append(v) 25 | return r 26 | 27 | 28 | def main_generator(dut): 29 | dut.o_sequence = [] 30 | yield dut.value.eq(dut.bitslip) 31 | for i, data in enumerate(dut.i_sequence): 32 | yield dut.i.eq(data) 33 | dut.o_sequence.append((yield dut.o)) 34 | yield 35 | 36 | 37 | class TestBitSlip(unittest.TestCase): 38 | def bitslip_test(self, data_width, length=128): 39 | prng = random.Random(42) 40 | sequence = [prng.randrange(2**data_width) for i in range(length)] 41 | 42 | for i in range(data_width): 43 | dut = BitSlip(data_width) 44 | dut.bitslip = i 45 | dut.i_sequence = sequence 46 | run_simulation(dut, main_generator(dut)) 47 | 48 | model = BitSlipModel(data_width, 4) 49 | m_sequence = model.simulate(i, sequence) 50 | 51 | self.assertEqual(dut.o_sequence, m_sequence[:len(dut.o_sequence)]) 52 | 53 | def test_bitslip_4b(self): 54 | self.bitslip_test(4) 55 | 56 | def test_bitslip_8b(self): 57 | self.bitslip_test(8) 58 | 59 | def test_bitslip_16b(self): 60 | self.bitslip_test(16) 61 | 62 | def test_bitslip_32b(self): 63 | self.bitslip_test(32) 64 | 65 | def test_bitslip_64b(self): 66 | self.bitslip_test(64) 67 | 68 | def test_bitslip_128b(self): 69 | self.bitslip_test(128) 70 | -------------------------------------------------------------------------------- /migen/test/test_coding.py: -------------------------------------------------------------------------------- 1 | import unittest 2 | 3 | from migen import * 4 | from migen.genlib.coding import * 5 | 6 | from migen.test.support import SimCase 7 | 8 | 9 | class EncCase(SimCase, unittest.TestCase): 10 | class TestBench(Module): 11 | def __init__(self): 12 | self.submodules.dut = Encoder(8) 13 | 14 | def test_sizes(self): 15 | self.assertEqual(len(self.tb.dut.i), 8) 16 | self.assertEqual(len(self.tb.dut.o), 3) 17 | self.assertEqual(len(self.tb.dut.n), 1) 18 | 19 | def test_run_sequence(self): 20 | seq = list(range(1<<8)) 21 | def gen(): 22 | for _ in range(256): 23 | if seq: 24 | yield self.tb.dut.i.eq(seq.pop(0)) 25 | if (yield self.tb.dut.n): 26 | self.assertNotIn((yield self.tb.dut.i), [1< 0: 55 | self.assertEqual(i & 1<<(o - 1), 0) 56 | self.assertGreaterEqual(i, 1< 0: 110 | self.assertEqual(i & 1<<(o - 1), 0) 111 | self.assertGreaterEqual(i, 1< q, 14 | lambda p, q: p >= q, 15 | lambda p, q: p < q, 16 | lambda p, q: p <= q, 17 | lambda p, q: p == q, 18 | lambda p, q: p != q, 19 | ] 20 | self.vals = [] 21 | for asign in 1, -1: 22 | for bsign in 1, -1: 23 | for f in comps: 24 | r = Signal() 25 | r0 = f(asign*self.a, bsign*self.b) 26 | self.comb += r.eq(r0) 27 | self.vals.append((asign, bsign, f, r, r0.op)) 28 | 29 | def test_comparisons(self): 30 | def gen(): 31 | for i in range(-4, 4): 32 | yield self.tb.a.eq(i) 33 | yield self.tb.b.eq(i) 34 | a = yield self.tb.a 35 | b = yield self.tb.b 36 | for asign, bsign, f, r, op in self.tb.vals: 37 | r, r0 = (yield r), f(asign*a, bsign*b) 38 | self.assertEqual(r, int(r0), 39 | "got {}, want {}*{} {} {}*{} = {}".format( 40 | r, asign, a, op, bsign, b, r0)) 41 | yield 42 | self.run_with(gen()) 43 | -------------------------------------------------------------------------------- /migen/test/test_size.py: -------------------------------------------------------------------------------- 1 | import unittest 2 | 3 | from migen import * 4 | 5 | 6 | def _same_slices(a, b): 7 | return a.value is b.value and a.start == b.start and a.stop == b.stop 8 | 9 | 10 | class SignalSizeCase(unittest.TestCase): 11 | def setUp(self): 12 | self.i = C(0xaa) 13 | self.j = C(-127) 14 | self.s = Signal((13, True)) 15 | 16 | def test_len(self): 17 | self.assertEqual(len(self.s), 13) 18 | self.assertEqual(len(self.i), 8) 19 | self.assertEqual(len(self.j), 8) 20 | -------------------------------------------------------------------------------- /migen/test/test_sort.py: -------------------------------------------------------------------------------- 1 | import unittest 2 | from random import randrange 3 | 4 | from migen import * 5 | from migen.genlib.sort import * 6 | 7 | from migen.test.support import SimCase 8 | 9 | 10 | class BitonicCase(SimCase, unittest.TestCase): 11 | class TestBench(Module): 12 | def __init__(self): 13 | self.submodules.dut = BitonicSort(8, 4, ascending=True) 14 | 15 | def test_sizes(self): 16 | self.assertEqual(len(self.tb.dut.i), 8) 17 | self.assertEqual(len(self.tb.dut.o), 8) 18 | for i in range(8): 19 | self.assertEqual(len(self.tb.dut.i[i]), 4) 20 | self.assertEqual(len(self.tb.dut.o[i]), 4) 21 | 22 | def test_sort(self): 23 | def gen(): 24 | for repeat in range(20): 25 | for i in self.tb.dut.i: 26 | yield i.eq(randrange(1<=65.5"] 41 | build-backend = "setuptools.build_meta" 42 | -------------------------------------------------------------------------------- /tools/strace_tailor.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # Copyright Robert Jordens 2014,2015 3 | 4 | # assuming your xilinx toolchain lives in /opt/Xilinx, 5 | # run `strace_tailor.sh /opt/Xilinx/ [synthesis script] [options]`, 6 | # e.g. for the pipistrello target of misoc: 7 | # strace_tailor.sh /opt/Xilinx/ ./make.py -t pipistrello build-bitstream 8 | # then in your current directory, `opt/Xilinx/*` is the 9 | # minimal toolchain required for this synthesis script run. 10 | 11 | PREFIX=$1 12 | shift 13 | strace -e trace=file,process -f -o strace.log $@ 14 | sed -n 's|^.*"\('"$PREFIX"'[^"]*\)".*$|\1|p' strace.log \ 15 | | sort | uniq | xargs -d '\n' \ 16 | cp --parent --no-dereference --preserve=all -t . 17 | --------------------------------------------------------------------------------