├── README ├── core ├── Manifest.py ├── tdc.vhd ├── tdc_channel.vhd ├── tdc_channelbank.vhd ├── tdc_channelbank_multi.vhd ├── tdc_channelbank_single.vhd ├── tdc_controller.vhd ├── tdc_delayline.vhd ├── tdc_divider.vhd ├── tdc_freqc.vhd ├── tdc_lbc.vhd ├── tdc_ordertaps.vhd ├── tdc_package.vhd ├── tdc_psync.vhd └── tdc_ringosc.vhd ├── demo ├── boards │ └── spec │ │ ├── rotest │ │ ├── Makefile │ │ ├── build │ │ │ └── .keep_me │ │ ├── rotest.ucf │ │ ├── rotest.vhd │ │ └── rotest.xst │ │ ├── rtl │ │ ├── lm32_include.v │ │ ├── setup.v │ │ └── system.v │ │ ├── sources.mak │ │ └── synthesis │ │ ├── Makefile.xst │ │ ├── build │ │ └── .keep_me │ │ ├── common.mak │ │ ├── common.ucf │ │ ├── floorplan_oscillators.py │ │ ├── load.cmd │ │ ├── system.xst │ │ └── xst.ucf ├── cores │ ├── bram │ │ ├── doc │ │ │ ├── Makefile │ │ │ └── bram.tex │ │ └── rtl │ │ │ └── bram.v │ ├── conbus │ │ ├── doc │ │ │ ├── Makefile │ │ │ └── conbus.tex │ │ ├── rtl │ │ │ ├── conbus.v │ │ │ └── conbus_arb.v │ │ └── test │ │ │ ├── Makefile │ │ │ ├── master.v │ │ │ ├── slave.v │ │ │ └── tb_conbus.v │ ├── csrbrg │ │ ├── rtl │ │ │ └── csrbrg.v │ │ └── test │ │ │ ├── Makefile │ │ │ └── tb_csrbrg.v │ ├── lm32 │ │ ├── CHANGELOG │ │ ├── doc │ │ │ ├── ds_icon.jpg │ │ │ ├── ds_icon_ast.jpg │ │ │ ├── dsb_icon.jpg │ │ │ ├── lever40.css │ │ │ ├── lever40_ns.css │ │ │ ├── lm32.htm │ │ │ ├── lm32_archman.pdf │ │ │ └── qm_icon.jpg │ │ └── rtl │ │ │ ├── JTAGB.v │ │ │ ├── er1.v │ │ │ ├── jtag_cores.v │ │ │ ├── jtag_lm32.v │ │ │ ├── lm32_adder.v │ │ │ ├── lm32_addsub.v │ │ │ ├── lm32_cpu.v │ │ │ ├── lm32_dcache.v │ │ │ ├── lm32_debug.v │ │ │ ├── lm32_decoder.v │ │ │ ├── lm32_functions.v │ │ │ ├── lm32_icache.v │ │ │ ├── lm32_instruction_unit.v │ │ │ ├── lm32_interrupt.v │ │ │ ├── lm32_jtag.v │ │ │ ├── lm32_load_store_unit.v │ │ │ ├── lm32_logic_op.v │ │ │ ├── lm32_mc_arithmetic.v │ │ │ ├── lm32_monitor.v │ │ │ ├── lm32_monitor_ram.v │ │ │ ├── lm32_multiplier.v │ │ │ ├── lm32_ram.v │ │ │ ├── lm32_shifter.v │ │ │ ├── lm32_top.v │ │ │ ├── lm32_trace.v │ │ │ ├── spiprog.v │ │ │ ├── typea.v │ │ │ └── typeb.v │ ├── sysctl │ │ ├── doc │ │ │ ├── Makefile │ │ │ └── sysctl.tex │ │ └── rtl │ │ │ └── sysctl.v │ └── uart │ │ ├── doc │ │ ├── Makefile │ │ └── uart.tex │ │ └── rtl │ │ ├── uart.v │ │ └── uart_transceiver.v ├── software │ ├── demo │ │ ├── Makefile │ │ ├── crt0.S │ │ ├── dac.c │ │ ├── dac.h │ │ ├── linker.ld │ │ ├── main.c │ │ ├── tdc.c │ │ ├── tdc.h │ │ ├── temperature.c │ │ ├── temperature.h │ │ ├── udelay.c │ │ └── udelay.h │ ├── include.mak │ ├── include │ │ ├── assert.h │ │ ├── console.h │ │ ├── crc.h │ │ ├── ctype.h │ │ ├── endian.h │ │ ├── hw │ │ │ ├── common.h │ │ │ ├── gpio.h │ │ │ ├── interrupts.h │ │ │ ├── sysctl.h │ │ │ ├── tdc.h │ │ │ └── uart.h │ │ ├── inttypes.h │ │ ├── irq.h │ │ ├── limits.h │ │ ├── stdarg.h │ │ ├── stdio.h │ │ ├── stdlib.h │ │ ├── string.h │ │ ├── system.h │ │ └── uart.h │ ├── libbase │ │ ├── Makefile │ │ ├── _ashlsi3.S │ │ ├── _ashrsi3.S │ │ ├── _divsi3.c │ │ ├── _lshrsi3.S │ │ ├── _modsi3.c │ │ ├── _mulsi3.c │ │ ├── _udivmodsi4.c │ │ ├── _udivsi3.c │ │ ├── _umodsi3.c │ │ ├── console.c │ │ ├── crc16.c │ │ ├── crc32.c │ │ ├── irq.S │ │ ├── libc.c │ │ ├── libgcc_lm32.h │ │ ├── milieu.h │ │ ├── system.c │ │ ├── uart-async.c │ │ ├── uart.c │ │ └── vsnprintf-nofloat.c │ └── update_depend.sh └── tools │ ├── Makefile │ ├── bin2hex.c │ ├── crc32.c │ ├── flterm.c │ └── sfl.h ├── doc ├── Makefile ├── block.dia ├── block.pdf ├── delaystruct.dia ├── delaystruct.pdf ├── dtdc.dia ├── dtdc.pdf ├── floorplan.png ├── ht_cal1.csv ├── ht_cal2.csv ├── ht_nocal.csv ├── input_routes.png ├── lt_cal1.csv ├── lt_cal2.csv ├── lutdiff.py ├── mhist.py ├── rofreq.csv ├── rofreq.py ├── series3a.csv ├── series3a_his.csv ├── series3a_lut.csv ├── tdc.tex ├── testreport.tex └── tweaklist.sty ├── hostif ├── Manifest.py ├── genconn.py ├── genwb.py ├── tdc_hostif.vhd ├── tdc_hostif_package.vhd └── tdc_wb.vhd ├── ordertaps.py └── tb ├── controller ├── simulate.sh └── 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