├── .gitignore ├── .mxproject ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32F1xx │ │ │ ├── Include │ │ │ ├── stm32f103xb.h │ │ │ ├── stm32f1xx.h │ │ │ └── system_stm32f1xx.h │ │ │ └── License.md │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ └── LICENSE.txt └── STM32F1xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32f1xx_hal.h │ ├── stm32f1xx_hal_cortex.h │ ├── stm32f1xx_hal_def.h │ ├── stm32f1xx_hal_dma.h │ ├── stm32f1xx_hal_dma_ex.h │ ├── stm32f1xx_hal_exti.h │ ├── stm32f1xx_hal_flash.h │ ├── stm32f1xx_hal_flash_ex.h │ ├── stm32f1xx_hal_gpio.h │ ├── stm32f1xx_hal_gpio_ex.h │ ├── stm32f1xx_hal_pwr.h │ ├── stm32f1xx_hal_rcc.h │ ├── stm32f1xx_hal_rcc_ex.h │ ├── stm32f1xx_hal_tim.h │ ├── stm32f1xx_hal_tim_ex.h │ ├── stm32f1xx_ll_bus.h │ ├── stm32f1xx_ll_cortex.h │ ├── stm32f1xx_ll_dma.h │ ├── stm32f1xx_ll_exti.h │ ├── stm32f1xx_ll_gpio.h │ ├── stm32f1xx_ll_pwr.h │ ├── stm32f1xx_ll_rcc.h │ ├── stm32f1xx_ll_system.h │ └── stm32f1xx_ll_utils.h │ ├── License.md │ └── Src │ ├── stm32f1xx_hal.c │ ├── stm32f1xx_hal_cortex.c │ ├── stm32f1xx_hal_dma.c │ ├── stm32f1xx_hal_exti.c │ ├── stm32f1xx_hal_flash.c │ ├── stm32f1xx_hal_flash_ex.c │ ├── stm32f1xx_hal_gpio.c │ ├── stm32f1xx_hal_gpio_ex.c │ ├── stm32f1xx_hal_pwr.c │ ├── stm32f1xx_hal_rcc.c │ ├── stm32f1xx_hal_rcc_ex.c │ ├── stm32f1xx_hal_tim.c │ └── stm32f1xx_hal_tim_ex.c ├── Inc ├── main.h ├── stm32f1xx_hal_conf.h └── stm32f1xx_it.h ├── LICENSE ├── Makefile ├── README.md ├── STM32F103C8Tx_FLASH.ld ├── Src ├── main.c ├── stm32f1xx_hal_msp.c ├── stm32f1xx_it.c └── system_stm32f1xx.c ├── config.ioc └── startup_stm32f103xb.s /.gitignore: -------------------------------------------------------------------------------- 1 | .vscode/ 2 | build/ -------------------------------------------------------------------------------- /.mxproject: -------------------------------------------------------------------------------- 1 | [PreviousLibFiles] 2 | LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xb.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; 3 | 4 | [PreviousUsedMakefileFiles] 5 | SourceFiles=Src\main.c;Src\stm32f1xx_it.c;Src\stm32f1xx_hal_msp.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Src\system_stm32f1xx.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Src\system_stm32f1xx.c;;; 6 | HeaderPath=Drivers\STM32F1xx_HAL_Driver\Inc;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F1xx\Include;Drivers\CMSIS\Include;Inc; 7 | CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;USE_HAL_DRIVER; 8 | 9 | [] 10 | SourceFiles=;; 11 | 12 | [PreviousGenFiles] 13 | HeaderPath=..\Inc 14 | HeaderFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h; 15 | SourcePath=..\Src 16 | SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; 17 | 18 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. 6 | * 7 | * The file is the unique include file that the application programmer 8 | * is using in the C source code, usually in main.c. This file contains: 9 | * - Configuration section that allows to select: 10 | * - The STM32F1xx device used in the target application 11 | * - To use or not the peripheral's drivers in application code(i.e. 12 | * code will be based on direct access to peripheral's registers 13 | * rather than drivers API), this option is controlled by 14 | * "#define USE_HAL_DRIVER" 15 | * 16 | ****************************************************************************** 17 | * @attention 18 | * 19 | * Copyright (c) 2017-2021 STMicroelectronics. 20 | * All rights reserved. 21 | * 22 | * This software is licensed under terms that can be found in the LICENSE file 23 | * in the root directory of this software component. 24 | * If no LICENSE file comes with this software, it is provided AS-IS. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /** @addtogroup CMSIS 30 | * @{ 31 | */ 32 | 33 | /** @addtogroup stm32f1xx 34 | * @{ 35 | */ 36 | 37 | #ifndef __STM32F1XX_H 38 | #define __STM32F1XX_H 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif /* __cplusplus */ 43 | 44 | /** @addtogroup Library_configuration_section 45 | * @{ 46 | */ 47 | 48 | /** 49 | * @brief STM32 Family 50 | */ 51 | #if !defined (STM32F1) 52 | #define STM32F1 53 | #endif /* STM32F1 */ 54 | 55 | /* Uncomment the line below according to the target STM32L device used in your 56 | application 57 | */ 58 | 59 | #if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ 60 | !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ 61 | !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) 62 | /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ 63 | /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ 64 | /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ 65 | /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ 66 | /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ 67 | /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ 68 | /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ 69 | /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ 70 | /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ 71 | /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ 72 | /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ 73 | /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ 74 | /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ 75 | /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ 76 | #endif 77 | 78 | /* Tip: To avoid modifying this file each time you need to switch between these 79 | devices, you can define the device in your toolchain compiler preprocessor. 80 | */ 81 | 82 | #if !defined (USE_HAL_DRIVER) 83 | /** 84 | * @brief Comment the line below if you will not use the peripherals drivers. 85 | In this case, these drivers will not be included and the application code will 86 | be based on direct access to peripherals registers 87 | */ 88 | /*#define USE_HAL_DRIVER */ 89 | #endif /* USE_HAL_DRIVER */ 90 | 91 | /** 92 | * @brief CMSIS Device version number 93 | */ 94 | #define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ 95 | #define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ 96 | #define __STM32F1_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ 97 | #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ 98 | #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ 99 | |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ 100 | |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ 101 | |(__STM32F1_CMSIS_VERSION_RC)) 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** @addtogroup Device_Included 108 | * @{ 109 | */ 110 | 111 | #if defined(STM32F100xB) 112 | #include "stm32f100xb.h" 113 | #elif defined(STM32F100xE) 114 | #include "stm32f100xe.h" 115 | #elif defined(STM32F101x6) 116 | #include "stm32f101x6.h" 117 | #elif defined(STM32F101xB) 118 | #include "stm32f101xb.h" 119 | #elif defined(STM32F101xE) 120 | #include "stm32f101xe.h" 121 | #elif defined(STM32F101xG) 122 | #include "stm32f101xg.h" 123 | #elif defined(STM32F102x6) 124 | #include "stm32f102x6.h" 125 | #elif defined(STM32F102xB) 126 | #include "stm32f102xb.h" 127 | #elif defined(STM32F103x6) 128 | #include "stm32f103x6.h" 129 | #elif defined(STM32F103xB) 130 | #include "stm32f103xb.h" 131 | #elif defined(STM32F103xE) 132 | #include "stm32f103xe.h" 133 | #elif defined(STM32F103xG) 134 | #include "stm32f103xg.h" 135 | #elif defined(STM32F105xC) 136 | #include "stm32f105xc.h" 137 | #elif defined(STM32F107xC) 138 | #include "stm32f107xc.h" 139 | #else 140 | #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" 141 | #endif 142 | 143 | /** 144 | * @} 145 | */ 146 | 147 | /** @addtogroup Exported_types 148 | * @{ 149 | */ 150 | typedef enum 151 | { 152 | RESET = 0, 153 | SET = !RESET 154 | } FlagStatus, ITStatus; 155 | 156 | typedef enum 157 | { 158 | DISABLE = 0, 159 | ENABLE = !DISABLE 160 | } FunctionalState; 161 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 162 | 163 | typedef enum 164 | { 165 | SUCCESS = 0U, 166 | ERROR = !SUCCESS 167 | } ErrorStatus; 168 | 169 | /** 170 | * @} 171 | */ 172 | 173 | 174 | /** @addtogroup Exported_macros 175 | * @{ 176 | */ 177 | #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 178 | 179 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 180 | 181 | #define READ_BIT(REG, BIT) ((REG) & (BIT)) 182 | 183 | #define CLEAR_REG(REG) ((REG) = (0x0)) 184 | 185 | #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 186 | 187 | #define READ_REG(REG) ((REG)) 188 | 189 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 190 | 191 | #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) 192 | 193 | /* Use of CMSIS compiler intrinsics for register exclusive access */ 194 | /* Atomic 32-bit register access macro to set one or several bits */ 195 | #define ATOMIC_SET_BIT(REG, BIT) \ 196 | do { \ 197 | uint32_t val; \ 198 | do { \ 199 | val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ 200 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 201 | } while(0) 202 | 203 | /* Atomic 32-bit register access macro to clear one or several bits */ 204 | #define ATOMIC_CLEAR_BIT(REG, BIT) \ 205 | do { \ 206 | uint32_t val; \ 207 | do { \ 208 | val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ 209 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 210 | } while(0) 211 | 212 | /* Atomic 32-bit register access macro to clear and set one or several bits */ 213 | #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 214 | do { \ 215 | uint32_t val; \ 216 | do { \ 217 | val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ 218 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 219 | } while(0) 220 | 221 | /* Atomic 16-bit register access macro to set one or several bits */ 222 | #define ATOMIC_SETH_BIT(REG, BIT) \ 223 | do { \ 224 | uint16_t val; \ 225 | do { \ 226 | val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ 227 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 228 | } while(0) 229 | 230 | /* Atomic 16-bit register access macro to clear one or several bits */ 231 | #define ATOMIC_CLEARH_BIT(REG, BIT) \ 232 | do { \ 233 | uint16_t val; \ 234 | do { \ 235 | val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ 236 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 237 | } while(0) 238 | 239 | /* Atomic 16-bit register access macro to clear and set one or several bits */ 240 | #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ 241 | do { \ 242 | uint16_t val; \ 243 | do { \ 244 | val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ 245 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 246 | } while(0) 247 | 248 | 249 | /** 250 | * @} 251 | */ 252 | 253 | #if defined (USE_HAL_DRIVER) 254 | #include "stm32f1xx_hal.h" 255 | #endif /* USE_HAL_DRIVER */ 256 | 257 | 258 | #ifdef __cplusplus 259 | } 260 | #endif /* __cplusplus */ 261 | 262 | #endif /* __STM32F1xx_H */ 263 | /** 264 | * @} 265 | */ 266 | 267 | /** 268 | * @} 269 | */ 270 | 271 | 272 | 273 | 274 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f1xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2017-2021 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /** @addtogroup CMSIS 20 | * @{ 21 | */ 22 | 23 | /** @addtogroup stm32f10x_system 24 | * @{ 25 | */ 26 | 27 | /** 28 | * @brief Define to prevent recursive inclusion 29 | */ 30 | #ifndef __SYSTEM_STM32F10X_H 31 | #define __SYSTEM_STM32F10X_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /** @addtogroup STM32F10x_System_Includes 38 | * @{ 39 | */ 40 | 41 | /** 42 | * @} 43 | */ 44 | 45 | 46 | /** @addtogroup STM32F10x_System_Exported_types 47 | * @{ 48 | */ 49 | 50 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 51 | extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ 52 | extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @addtogroup STM32F10x_System_Exported_Constants 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @addtogroup STM32F10x_System_Exported_Macros 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @addtogroup STM32F10x_System_Exported_Functions 75 | * @{ 76 | */ 77 | 78 | extern void SystemInit(void); 79 | extern void SystemCoreClockUpdate(void); 80 | /** 81 | * @} 82 | */ 83 | 84 | #ifdef __cplusplus 85 | } 86 | #endif 87 | 88 | #endif /*__SYSTEM_STM32F10X_H */ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** 95 | * @} 96 | */ 97 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/License.md: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [2019] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6 (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 41 | #include "cmsis_armclang.h" 42 | 43 | 44 | /* 45 | * GNU Compiler 46 | */ 47 | #elif defined ( __GNUC__ ) 48 | #include "cmsis_gcc.h" 49 | 50 | 51 | /* 52 | * IAR Compiler 53 | */ 54 | #elif defined ( __ICCARM__ ) 55 | #include 56 | 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined ( __TI_ARM__ ) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 97 | #endif 98 | #ifndef __UNALIGNED_UINT16_WRITE 99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT16_READ 103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 105 | #endif 106 | #ifndef __UNALIGNED_UINT32_WRITE 107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 109 | #endif 110 | #ifndef __UNALIGNED_UINT32_READ 111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 113 | #endif 114 | #ifndef __ALIGNED 115 | #define __ALIGNED(x) __attribute__((aligned(x))) 116 | #endif 117 | #ifndef __RESTRICT 118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 119 | #define __RESTRICT 120 | #endif 121 | 122 | 123 | /* 124 | * TASKING Compiler 125 | */ 126 | #elif defined ( __TASKING__ ) 127 | /* 128 | * The CMSIS functions have been implemented as intrinsics in the compiler. 129 | * Please use "carm -?i" to get an up to date list of all intrinsics, 130 | * Including the CMSIS ones. 131 | */ 132 | 133 | #ifndef __ASM 134 | #define __ASM __asm 135 | #endif 136 | #ifndef __INLINE 137 | #define __INLINE inline 138 | #endif 139 | #ifndef __STATIC_INLINE 140 | #define __STATIC_INLINE static inline 141 | #endif 142 | #ifndef __STATIC_FORCEINLINE 143 | #define __STATIC_FORCEINLINE __STATIC_INLINE 144 | #endif 145 | #ifndef __NO_RETURN 146 | #define __NO_RETURN __attribute__((noreturn)) 147 | #endif 148 | #ifndef __USED 149 | #define __USED __attribute__((used)) 150 | #endif 151 | #ifndef __WEAK 152 | #define __WEAK __attribute__((weak)) 153 | #endif 154 | #ifndef __PACKED 155 | #define __PACKED __packed__ 156 | #endif 157 | #ifndef __PACKED_STRUCT 158 | #define __PACKED_STRUCT struct __packed__ 159 | #endif 160 | #ifndef __PACKED_UNION 161 | #define __PACKED_UNION union __packed__ 162 | #endif 163 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 164 | struct __packed__ T_UINT32 { uint32_t v; }; 165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 166 | #endif 167 | #ifndef __UNALIGNED_UINT16_WRITE 168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 170 | #endif 171 | #ifndef __UNALIGNED_UINT16_READ 172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 174 | #endif 175 | #ifndef __UNALIGNED_UINT32_WRITE 176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 178 | #endif 179 | #ifndef __UNALIGNED_UINT32_READ 180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 182 | #endif 183 | #ifndef __ALIGNED 184 | #define __ALIGNED(x) __align(x) 185 | #endif 186 | #ifndef __RESTRICT 187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 188 | #define __RESTRICT 189 | #endif 190 | 191 | 192 | /* 193 | * COSMIC Compiler 194 | */ 195 | #elif defined ( __CSMC__ ) 196 | #include 197 | 198 | #ifndef __ASM 199 | #define __ASM _asm 200 | #endif 201 | #ifndef __INLINE 202 | #define __INLINE inline 203 | #endif 204 | #ifndef __STATIC_INLINE 205 | #define __STATIC_INLINE static inline 206 | #endif 207 | #ifndef __STATIC_FORCEINLINE 208 | #define __STATIC_FORCEINLINE __STATIC_INLINE 209 | #endif 210 | #ifndef __NO_RETURN 211 | // NO RETURN is automatically detected hence no warning here 212 | #define __NO_RETURN 213 | #endif 214 | #ifndef __USED 215 | #warning No compiler specific solution for __USED. __USED is ignored. 216 | #define __USED 217 | #endif 218 | #ifndef __WEAK 219 | #define __WEAK __weak 220 | #endif 221 | #ifndef __PACKED 222 | #define __PACKED @packed 223 | #endif 224 | #ifndef __PACKED_STRUCT 225 | #define __PACKED_STRUCT @packed struct 226 | #endif 227 | #ifndef __PACKED_UNION 228 | #define __PACKED_UNION @packed union 229 | #endif 230 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 231 | @packed struct T_UINT32 { uint32_t v; }; 232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 233 | #endif 234 | #ifndef __UNALIGNED_UINT16_WRITE 235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 237 | #endif 238 | #ifndef __UNALIGNED_UINT16_READ 239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 241 | #endif 242 | #ifndef __UNALIGNED_UINT32_WRITE 243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 245 | #endif 246 | #ifndef __UNALIGNED_UINT32_READ 247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 249 | #endif 250 | #ifndef __ALIGNED 251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 252 | #define __ALIGNED(x) 253 | #endif 254 | #ifndef __RESTRICT 255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 256 | #define __RESTRICT 257 | #endif 258 | 259 | 260 | #else 261 | #error Unknown compiler. 262 | #endif 263 | 264 | 265 | #endif /* __CMSIS_COMPILER_H */ 266 | 267 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.2 5 | * @date 19. April 2017 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 107 | 108 | /** 109 | * MPU Region Attribute and Size Register Value 110 | * 111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 114 | * \param IsShareable Region is shareable between multiple bus masters. 115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 117 | * \param SubRegionDisable Sub-region disable field. 118 | * \param Size Region size of the region to be configured, for example 4K, 8K. 119 | */ 120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 122 | 123 | /** 124 | * MPU Memory Access Attribute for strongly ordered memory. 125 | * - TEX: 000b 126 | * - Shareable 127 | * - Non-cacheable 128 | * - Non-bufferable 129 | */ 130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 131 | 132 | /** 133 | * MPU Memory Access Attribute for device memory. 134 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 135 | * - Shareable or non-shareable 136 | * - Non-cacheable 137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 138 | * 139 | * \param IsShareable Configures the device memory as shareable or non-shareable. 140 | */ 141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 142 | 143 | /** 144 | * MPU Memory Access Attribute for normal memory. 145 | * - TEX: 1BBb (reflecting outer cacheability rules) 146 | * - Shareable or non-shareable 147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 149 | * 150 | * \param OuterCp Configures the outer cache policy. 151 | * \param InnerCp Configures the inner cache policy. 152 | * \param IsShareable Configures the memory as shareable or non-shareable. 153 | */ 154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 155 | 156 | /** 157 | * MPU Memory Access Attribute non-cacheable policy. 158 | */ 159 | #define ARM_MPU_CACHEP_NOCACHE 0U 160 | 161 | /** 162 | * MPU Memory Access Attribute write-back, write and read allocate policy. 163 | */ 164 | #define ARM_MPU_CACHEP_WB_WRA 1U 165 | 166 | /** 167 | * MPU Memory Access Attribute write-through, no write allocate policy. 168 | */ 169 | #define ARM_MPU_CACHEP_WT_NWA 2U 170 | 171 | /** 172 | * MPU Memory Access Attribute write-back, no write allocate policy. 173 | */ 174 | #define ARM_MPU_CACHEP_WB_NWA 3U 175 | 176 | 177 | /** 178 | * Struct for a single MPU Region 179 | */ 180 | typedef struct { 181 | uint32_t RBAR; //!< The region base address register value (RBAR) 182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 183 | } ARM_MPU_Region_t; 184 | 185 | /** Enable the MPU. 186 | * \param MPU_Control Default access permissions for unconfigured regions. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 189 | { 190 | __DSB(); 191 | __ISB(); 192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 195 | #endif 196 | } 197 | 198 | /** Disable the MPU. 199 | */ 200 | __STATIC_INLINE void ARM_MPU_Disable(void) 201 | { 202 | __DSB(); 203 | __ISB(); 204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 206 | #endif 207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 208 | } 209 | 210 | /** Clear and disable the given MPU region. 211 | * \param rnr Region number to be cleared. 212 | */ 213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 214 | { 215 | MPU->RNR = rnr; 216 | MPU->RASR = 0U; 217 | } 218 | 219 | /** Configure an MPU region. 220 | * \param rbar Value for RBAR register. 221 | * \param rsar Value for RSAR register. 222 | */ 223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 224 | { 225 | MPU->RBAR = rbar; 226 | MPU->RASR = rasr; 227 | } 228 | 229 | /** Configure the given MPU region. 230 | * \param rnr Region number to be configured. 231 | * \param rbar Value for RBAR register. 232 | * \param rsar Value for RSAR register. 233 | */ 234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 235 | { 236 | MPU->RNR = rnr; 237 | MPU->RBAR = rbar; 238 | MPU->RASR = rasr; 239 | } 240 | 241 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 242 | * \param dst Destination data is copied to. 243 | * \param src Source data is copied from. 244 | * \param len Amount of data words to be copied. 245 | */ 246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 247 | { 248 | uint32_t i; 249 | for (i = 0U; i < len; ++i) 250 | { 251 | dst[i] = src[i]; 252 | } 253 | } 254 | 255 | /** Load the given number of MPU regions from a table. 256 | * \param table Pointer to the MPU configuration table. 257 | * \param cnt Amount of regions to be configured. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 260 | { 261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 262 | while (cnt > MPU_TYPE_RALIASES) { 263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 264 | table += MPU_TYPE_RALIASES; 265 | cnt -= MPU_TYPE_RALIASES; 266 | } 267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 268 | } 269 | 270 | #endif 271 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct { 108 | uint32_t RBAR; /*!< Region Base Address Register value */ 109 | uint32_t RLAR; /*!< Region Limit Address Register value */ 110 | } ARM_MPU_Region_t; 111 | 112 | /** Enable the MPU. 113 | * \param MPU_Control Default access permissions for unconfigured regions. 114 | */ 115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 116 | { 117 | __DSB(); 118 | __ISB(); 119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 122 | #endif 123 | } 124 | 125 | /** Disable the MPU. 126 | */ 127 | __STATIC_INLINE void ARM_MPU_Disable(void) 128 | { 129 | __DSB(); 130 | __ISB(); 131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 133 | #endif 134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 135 | } 136 | 137 | #ifdef MPU_NS 138 | /** Enable the Non-secure MPU. 139 | * \param MPU_Control Default access permissions for unconfigured regions. 140 | */ 141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 142 | { 143 | __DSB(); 144 | __ISB(); 145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 148 | #endif 149 | } 150 | 151 | /** Disable the Non-secure MPU. 152 | */ 153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 154 | { 155 | __DSB(); 156 | __ISB(); 157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 159 | #endif 160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 161 | } 162 | #endif 163 | 164 | /** Set the memory attribute encoding to the given MPU. 165 | * \param mpu Pointer to the MPU to be configured. 166 | * \param idx The attribute index to be set [0-7] 167 | * \param attr The attribute value to be set. 168 | */ 169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 170 | { 171 | const uint8_t reg = idx / 4U; 172 | const uint32_t pos = ((idx % 4U) * 8U); 173 | const uint32_t mask = 0xFFU << pos; 174 | 175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 176 | return; // invalid index 177 | } 178 | 179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 180 | } 181 | 182 | /** Set the memory attribute encoding. 183 | * \param idx The attribute index to be set [0-7] 184 | * \param attr The attribute value to be set. 185 | */ 186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 187 | { 188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 189 | } 190 | 191 | #ifdef MPU_NS 192 | /** Set the memory attribute encoding to the Non-secure MPU. 193 | * \param idx The attribute index to be set [0-7] 194 | * \param attr The attribute value to be set. 195 | */ 196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 197 | { 198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 199 | } 200 | #endif 201 | 202 | /** Clear and disable the given MPU region of the given MPU. 203 | * \param mpu Pointer to MPU to be used. 204 | * \param rnr Region number to be cleared. 205 | */ 206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 207 | { 208 | mpu->RNR = rnr; 209 | mpu->RLAR = 0U; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | ARM_MPU_ClrRegionEx(MPU, rnr); 218 | } 219 | 220 | #ifdef MPU_NS 221 | /** Clear and disable the given Non-secure MPU region. 222 | * \param rnr Region number to be cleared. 223 | */ 224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 225 | { 226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 227 | } 228 | #endif 229 | 230 | /** Configure the given MPU region of the given MPU. 231 | * \param mpu Pointer to MPU to be used. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rlar Value for RLAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 237 | { 238 | mpu->RNR = rnr; 239 | mpu->RBAR = rbar; 240 | mpu->RLAR = rlar; 241 | } 242 | 243 | /** Configure the given MPU region. 244 | * \param rnr Region number to be configured. 245 | * \param rbar Value for RBAR register. 246 | * \param rlar Value for RLAR register. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 249 | { 250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 251 | } 252 | 253 | #ifdef MPU_NS 254 | /** Configure the given Non-secure MPU region. 255 | * \param rnr Region number to be configured. 256 | * \param rbar Value for RBAR register. 257 | * \param rlar Value for RLAR register. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 260 | { 261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 262 | } 263 | #endif 264 | 265 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 266 | * \param dst Destination data is copied to. 267 | * \param src Source data is copied from. 268 | * \param len Amount of data words to be copied. 269 | */ 270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 271 | { 272 | uint32_t i; 273 | for (i = 0U; i < len; ++i) 274 | { 275 | dst[i] = src[i]; 276 | } 277 | } 278 | 279 | /** Load the given number of MPU regions from a table to the given MPU. 280 | * \param mpu Pointer to the MPU registers to be used. 281 | * \param rnr First region number to be configured. 282 | * \param table Pointer to the MPU configuration table. 283 | * \param cnt Amount of regions to be configured. 284 | */ 285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 286 | { 287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 288 | if (cnt == 1U) { 289 | mpu->RNR = rnr; 290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 291 | } else { 292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 294 | 295 | mpu->RNR = rnrBase; 296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 299 | table += c; 300 | cnt -= c; 301 | rnrOffset = 0U; 302 | rnrBase += MPU_TYPE_RALIASES; 303 | mpu->RNR = rnrBase; 304 | } 305 | 306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 307 | } 308 | } 309 | 310 | /** Load the given number of MPU regions from a table. 311 | * \param rnr First region number to be configured. 312 | * \param table Pointer to the MPU configuration table. 313 | * \param cnt Amount of regions to be configured. 314 | */ 315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 316 | { 317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 318 | } 319 | 320 | #ifdef MPU_NS 321 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 322 | * \param rnr First region number to be configured. 323 | * \param table Pointer to the MPU configuration table. 324 | * \param cnt Amount of regions to be configured. 325 | */ 326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 327 | { 328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 329 | } 330 | #endif 331 | 332 | #endif 333 | 334 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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-------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal.h 4 | * @author MCD Application Team 5 | * @brief This file contains all the functions prototypes for the HAL 6 | * module driver. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F1xx_HAL_H 22 | #define __STM32F1xx_HAL_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f1xx_hal_conf.h" 30 | 31 | /** @addtogroup STM32F1xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup HAL 36 | * @{ 37 | */ 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | 41 | /** @defgroup HAL_Exported_Constants HAL Exported Constants 42 | * @{ 43 | */ 44 | 45 | /** @defgroup HAL_TICK_FREQ Tick Frequency 46 | * @{ 47 | */ 48 | typedef enum 49 | { 50 | HAL_TICK_FREQ_10HZ = 100U, 51 | HAL_TICK_FREQ_100HZ = 10U, 52 | HAL_TICK_FREQ_1KHZ = 1U, 53 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 54 | } HAL_TickFreqTypeDef; 55 | /** 56 | * @} 57 | */ 58 | /* Exported types ------------------------------------------------------------*/ 59 | extern __IO uint32_t uwTick; 60 | extern uint32_t uwTickPrio; 61 | extern HAL_TickFreqTypeDef uwTickFreq; 62 | 63 | /** 64 | * @} 65 | */ 66 | /* Exported macro ------------------------------------------------------------*/ 67 | /** @defgroup HAL_Exported_Macros HAL Exported Macros 68 | * @{ 69 | */ 70 | 71 | /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode 72 | * @brief Freeze/Unfreeze Peripherals in Debug mode 73 | * Note: On devices STM32F10xx8 and STM32F10xxB, 74 | * STM32F101xC/D/E and STM32F103xC/D/E, 75 | * STM32F101xF/G and STM32F103xF/G 76 | * STM32F10xx4 and STM32F10xx6 77 | * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in 78 | * debug mode (not accessible by the user software in normal mode). 79 | * Refer to errata sheet of these devices for more details. 80 | * @{ 81 | */ 82 | 83 | /* Peripherals on APB1 */ 84 | /** 85 | * @brief TIM2 Peripherals Debug mode 86 | */ 87 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) 88 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) 89 | 90 | /** 91 | * @brief TIM3 Peripherals Debug mode 92 | */ 93 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) 94 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) 95 | 96 | #if defined (DBGMCU_CR_DBG_TIM4_STOP) 97 | /** 98 | * @brief TIM4 Peripherals Debug mode 99 | */ 100 | #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) 101 | #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) 102 | #endif 103 | 104 | #if defined (DBGMCU_CR_DBG_TIM5_STOP) 105 | /** 106 | * @brief TIM5 Peripherals Debug mode 107 | */ 108 | #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) 109 | #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) 110 | #endif 111 | 112 | #if defined (DBGMCU_CR_DBG_TIM6_STOP) 113 | /** 114 | * @brief TIM6 Peripherals Debug mode 115 | */ 116 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) 117 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) 118 | #endif 119 | 120 | #if defined (DBGMCU_CR_DBG_TIM7_STOP) 121 | /** 122 | * @brief TIM7 Peripherals Debug mode 123 | */ 124 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) 125 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) 126 | #endif 127 | 128 | #if defined (DBGMCU_CR_DBG_TIM12_STOP) 129 | /** 130 | * @brief TIM12 Peripherals Debug mode 131 | */ 132 | #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) 133 | #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) 134 | #endif 135 | 136 | #if defined (DBGMCU_CR_DBG_TIM13_STOP) 137 | /** 138 | * @brief TIM13 Peripherals Debug mode 139 | */ 140 | #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) 141 | #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) 142 | #endif 143 | 144 | #if defined (DBGMCU_CR_DBG_TIM14_STOP) 145 | /** 146 | * @brief TIM14 Peripherals Debug mode 147 | */ 148 | #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) 149 | #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) 150 | #endif 151 | 152 | /** 153 | * @brief WWDG Peripherals Debug mode 154 | */ 155 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) 156 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) 157 | 158 | /** 159 | * @brief IWDG Peripherals Debug mode 160 | */ 161 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) 162 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) 163 | 164 | /** 165 | * @brief I2C1 Peripherals Debug mode 166 | */ 167 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) 168 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) 169 | 170 | #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 171 | /** 172 | * @brief I2C2 Peripherals Debug mode 173 | */ 174 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 175 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 176 | #endif 177 | 178 | #if defined (DBGMCU_CR_DBG_CAN1_STOP) 179 | /** 180 | * @brief CAN1 Peripherals Debug mode 181 | */ 182 | #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) 183 | #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) 184 | #endif 185 | 186 | #if defined (DBGMCU_CR_DBG_CAN2_STOP) 187 | /** 188 | * @brief CAN2 Peripherals Debug mode 189 | */ 190 | #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) 191 | #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) 192 | #endif 193 | 194 | /* Peripherals on APB2 */ 195 | #if defined (DBGMCU_CR_DBG_TIM1_STOP) 196 | /** 197 | * @brief TIM1 Peripherals Debug mode 198 | */ 199 | #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) 200 | #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) 201 | #endif 202 | 203 | #if defined (DBGMCU_CR_DBG_TIM8_STOP) 204 | /** 205 | * @brief TIM8 Peripherals Debug mode 206 | */ 207 | #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) 208 | #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) 209 | #endif 210 | 211 | #if defined (DBGMCU_CR_DBG_TIM9_STOP) 212 | /** 213 | * @brief TIM9 Peripherals Debug mode 214 | */ 215 | #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) 216 | #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) 217 | #endif 218 | 219 | #if defined (DBGMCU_CR_DBG_TIM10_STOP) 220 | /** 221 | * @brief TIM10 Peripherals Debug mode 222 | */ 223 | #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) 224 | #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) 225 | #endif 226 | 227 | #if defined (DBGMCU_CR_DBG_TIM11_STOP) 228 | /** 229 | * @brief TIM11 Peripherals Debug mode 230 | */ 231 | #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) 232 | #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) 233 | #endif 234 | 235 | 236 | #if defined (DBGMCU_CR_DBG_TIM15_STOP) 237 | /** 238 | * @brief TIM15 Peripherals Debug mode 239 | */ 240 | #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) 241 | #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) 242 | #endif 243 | 244 | #if defined (DBGMCU_CR_DBG_TIM16_STOP) 245 | /** 246 | * @brief TIM16 Peripherals Debug mode 247 | */ 248 | #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) 249 | #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) 250 | #endif 251 | 252 | #if defined (DBGMCU_CR_DBG_TIM17_STOP) 253 | /** 254 | * @brief TIM17 Peripherals Debug mode 255 | */ 256 | #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) 257 | #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) 258 | #endif 259 | 260 | /** 261 | * @} 262 | */ 263 | 264 | /** @defgroup HAL_Private_Macros HAL Private Macros 265 | * @{ 266 | */ 267 | #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 268 | ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 269 | ((FREQ) == HAL_TICK_FREQ_1KHZ)) 270 | /** 271 | * @} 272 | */ 273 | 274 | /* Exported functions --------------------------------------------------------*/ 275 | /** @addtogroup HAL_Exported_Functions 276 | * @{ 277 | */ 278 | /** @addtogroup HAL_Exported_Functions_Group1 279 | * @{ 280 | */ 281 | /* Initialization and de-initialization functions ******************************/ 282 | HAL_StatusTypeDef HAL_Init(void); 283 | HAL_StatusTypeDef HAL_DeInit(void); 284 | void HAL_MspInit(void); 285 | void HAL_MspDeInit(void); 286 | HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 287 | /** 288 | * @} 289 | */ 290 | 291 | /** @addtogroup HAL_Exported_Functions_Group2 292 | * @{ 293 | */ 294 | /* Peripheral Control functions ************************************************/ 295 | void HAL_IncTick(void); 296 | void HAL_Delay(uint32_t Delay); 297 | uint32_t HAL_GetTick(void); 298 | uint32_t HAL_GetTickPrio(void); 299 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 300 | HAL_TickFreqTypeDef HAL_GetTickFreq(void); 301 | void HAL_SuspendTick(void); 302 | void HAL_ResumeTick(void); 303 | uint32_t HAL_GetHalVersion(void); 304 | uint32_t HAL_GetREVID(void); 305 | uint32_t HAL_GetDEVID(void); 306 | uint32_t HAL_GetUIDw0(void); 307 | uint32_t HAL_GetUIDw1(void); 308 | uint32_t HAL_GetUIDw2(void); 309 | void HAL_DBGMCU_EnableDBGSleepMode(void); 310 | void HAL_DBGMCU_DisableDBGSleepMode(void); 311 | void HAL_DBGMCU_EnableDBGStopMode(void); 312 | void HAL_DBGMCU_DisableDBGStopMode(void); 313 | void HAL_DBGMCU_EnableDBGStandbyMode(void); 314 | void HAL_DBGMCU_DisableDBGStandbyMode(void); 315 | /** 316 | * @} 317 | */ 318 | 319 | /** 320 | * @} 321 | */ 322 | 323 | /** 324 | * @} 325 | */ 326 | /* Private types -------------------------------------------------------------*/ 327 | /* Private variables ---------------------------------------------------------*/ 328 | /** @defgroup HAL_Private_Variables HAL Private Variables 329 | * @{ 330 | */ 331 | /** 332 | * @} 333 | */ 334 | /* Private constants ---------------------------------------------------------*/ 335 | /** @defgroup HAL_Private_Constants HAL Private Constants 336 | * @{ 337 | */ 338 | /** 339 | * @} 340 | */ 341 | /* Private macros ------------------------------------------------------------*/ 342 | /* Private functions ---------------------------------------------------------*/ 343 | /** 344 | * @} 345 | */ 346 | 347 | /** 348 | * @} 349 | */ 350 | 351 | #ifdef __cplusplus 352 | } 353 | #endif 354 | 355 | #endif /* __STM32F1xx_HAL_H */ 356 | 357 | 358 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F1xx_HAL_DEF 22 | #define __STM32F1xx_HAL_DEF 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f1xx.h" 30 | #include "Legacy/stm32_hal_legacy.h" 31 | #include 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | 35 | /** 36 | * @brief HAL Status structures definition 37 | */ 38 | typedef enum 39 | { 40 | HAL_OK = 0x00U, 41 | HAL_ERROR = 0x01U, 42 | HAL_BUSY = 0x02U, 43 | HAL_TIMEOUT = 0x03U 44 | } HAL_StatusTypeDef; 45 | 46 | /** 47 | * @brief HAL Lock structures definition 48 | */ 49 | typedef enum 50 | { 51 | HAL_UNLOCKED = 0x00U, 52 | HAL_LOCKED = 0x01U 53 | } HAL_LockTypeDef; 54 | 55 | /* Exported macro ------------------------------------------------------------*/ 56 | #define HAL_MAX_DELAY 0xFFFFFFFFU 57 | 58 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) 59 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 60 | 61 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 62 | do{ \ 63 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 64 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 65 | } while(0U) 66 | 67 | #if !defined(UNUSED) 68 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 69 | #endif /* UNUSED */ 70 | 71 | /** @brief Reset the Handle's State field. 72 | * @param __HANDLE__ specifies the Peripheral Handle. 73 | * @note This macro can be used for the following purpose: 74 | * - When the Handle is declared as local variable; before passing it as parameter 75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 76 | * to set to 0 the Handle's "State" field. 77 | * Otherwise, "State" field may have any random value and the first time the function 78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 79 | * (i.e. HAL_PPP_MspInit() will not be executed). 80 | * - When there is a need to reconfigure the low level hardware: instead of calling 81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 84 | * @retval None 85 | */ 86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 87 | 88 | #if (USE_RTOS == 1U) 89 | /* Reserved for future use */ 90 | #error "USE_RTOS should be 0 in the current HAL release" 91 | #else 92 | #define __HAL_LOCK(__HANDLE__) \ 93 | do{ \ 94 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 95 | { \ 96 | return HAL_BUSY; \ 97 | } \ 98 | else \ 99 | { \ 100 | (__HANDLE__)->Lock = HAL_LOCKED; \ 101 | } \ 102 | }while (0U) 103 | 104 | #define __HAL_UNLOCK(__HANDLE__) \ 105 | do{ \ 106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 107 | }while (0U) 108 | #endif /* USE_RTOS */ 109 | 110 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 111 | #ifndef __weak 112 | #define __weak __attribute__((weak)) 113 | #endif 114 | #ifndef __packed 115 | #define __packed __attribute__((packed)) 116 | #endif 117 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 118 | #ifndef __weak 119 | #define __weak __attribute__((weak)) 120 | #endif /* __weak */ 121 | #ifndef __packed 122 | #define __packed __attribute__((__packed__)) 123 | #endif /* __packed */ 124 | #endif /* __GNUC__ */ 125 | 126 | 127 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 128 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 129 | #ifndef __ALIGN_BEGIN 130 | #define __ALIGN_BEGIN 131 | #endif 132 | #ifndef __ALIGN_END 133 | #define __ALIGN_END __attribute__ ((aligned (4))) 134 | #endif 135 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 136 | #ifndef __ALIGN_END 137 | #define __ALIGN_END __attribute__ ((aligned (4))) 138 | #endif /* __ALIGN_END */ 139 | #ifndef __ALIGN_BEGIN 140 | #define __ALIGN_BEGIN 141 | #endif /* __ALIGN_BEGIN */ 142 | #else 143 | #ifndef __ALIGN_END 144 | #define __ALIGN_END 145 | #endif /* __ALIGN_END */ 146 | #ifndef __ALIGN_BEGIN 147 | #if defined (__CC_ARM) /* ARM Compiler V5*/ 148 | #define __ALIGN_BEGIN __align(4) 149 | #elif defined (__ICCARM__) /* IAR Compiler */ 150 | #define __ALIGN_BEGIN 151 | #endif /* __CC_ARM */ 152 | #endif /* __ALIGN_BEGIN */ 153 | #endif /* __GNUC__ */ 154 | 155 | 156 | /** 157 | * @brief __RAM_FUNC definition 158 | */ 159 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 160 | /* ARM Compiler V4/V5 and V6 161 | -------------------------- 162 | RAM functions are defined using the toolchain options. 163 | Functions that are executed in RAM should reside in a separate source module. 164 | Using the 'Options for File' dialog you can simply change the 'Code / Const' 165 | area of a module to a memory space in physical RAM. 166 | Available memory areas are declared in the 'Target' tab of the 'Options for Target' 167 | dialog. 168 | */ 169 | #define __RAM_FUNC 170 | 171 | #elif defined ( __ICCARM__ ) 172 | /* ICCARM Compiler 173 | --------------- 174 | RAM functions are defined using a specific toolchain keyword "__ramfunc". 175 | */ 176 | #define __RAM_FUNC __ramfunc 177 | 178 | #elif defined ( __GNUC__ ) 179 | /* GNU Compiler 180 | ------------ 181 | RAM functions are defined using a specific toolchain attribute 182 | "__attribute__((section(".RamFunc")))". 183 | */ 184 | #define __RAM_FUNC __attribute__((section(".RamFunc"))) 185 | 186 | #endif 187 | 188 | /** 189 | * @brief __NOINLINE definition 190 | */ 191 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 192 | /* ARM V4/V5 and V6 & GNU Compiler 193 | ------------------------------- 194 | */ 195 | #define __NOINLINE __attribute__ ( (noinline) ) 196 | 197 | #elif defined ( __ICCARM__ ) 198 | /* ICCARM Compiler 199 | --------------- 200 | */ 201 | #define __NOINLINE _Pragma("optimize = no_inline") 202 | 203 | #endif 204 | 205 | #ifdef __cplusplus 206 | } 207 | #endif 208 | 209 | #endif /* ___STM32F1xx_HAL_DEF */ 210 | 211 | 212 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_exti.h 4 | * @author MCD Application Team 5 | * @brief Header file of EXTI HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2019 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32F1xx_HAL_EXTI_H 21 | #define STM32F1xx_HAL_EXTI_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32f1xx_hal_def.h" 29 | 30 | /** @addtogroup STM32F1xx_HAL_Driver 31 | * @{ 32 | */ 33 | 34 | /** @defgroup EXTI EXTI 35 | * @brief EXTI HAL module driver 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | 41 | /** @defgroup EXTI_Exported_Types EXTI Exported Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief HAL EXTI common Callback ID enumeration definition 47 | */ 48 | typedef enum 49 | { 50 | HAL_EXTI_COMMON_CB_ID = 0x00U 51 | } EXTI_CallbackIDTypeDef; 52 | 53 | /** 54 | * @brief EXTI Handle structure definition 55 | */ 56 | typedef struct 57 | { 58 | uint32_t Line; /*!< Exti line number */ 59 | void (* PendingCallback)(void); /*!< Exti pending callback */ 60 | } EXTI_HandleTypeDef; 61 | 62 | /** 63 | * @brief EXTI Configuration structure definition 64 | */ 65 | typedef struct 66 | { 67 | uint32_t Line; /*!< The Exti line to be configured. This parameter 68 | can be a value of @ref EXTI_Line */ 69 | uint32_t Mode; /*!< The Exit Mode to be configured for a core. 70 | This parameter can be a combination of @ref EXTI_Mode */ 71 | uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter 72 | can be a value of @ref EXTI_Trigger */ 73 | uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. 74 | This parameter is only possible for line 0 to 15. It 75 | can be a value of @ref EXTI_GPIOSel */ 76 | } EXTI_ConfigTypeDef; 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /* Exported constants --------------------------------------------------------*/ 83 | /** @defgroup EXTI_Exported_Constants EXTI Exported Constants 84 | * @{ 85 | */ 86 | 87 | /** @defgroup EXTI_Line EXTI Line 88 | * @{ 89 | */ 90 | #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ 91 | #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ 92 | #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ 93 | #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ 94 | #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ 95 | #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ 96 | #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ 97 | #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ 98 | #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ 99 | #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ 100 | #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ 101 | #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ 102 | #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ 103 | #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ 104 | #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ 105 | #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ 106 | #define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ 107 | #define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ 108 | #if defined(EXTI_IMR_IM18) 109 | #define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ 110 | #endif /* EXTI_IMR_IM18 */ 111 | #if defined(EXTI_IMR_IM19) 112 | #define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ 113 | #endif /* EXTI_IMR_IM19 */ 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @defgroup EXTI_Mode EXTI Mode 120 | * @{ 121 | */ 122 | #define EXTI_MODE_NONE 0x00000000u 123 | #define EXTI_MODE_INTERRUPT 0x00000001u 124 | #define EXTI_MODE_EVENT 0x00000002u 125 | /** 126 | * @} 127 | */ 128 | 129 | /** @defgroup EXTI_Trigger EXTI Trigger 130 | * @{ 131 | */ 132 | #define EXTI_TRIGGER_NONE 0x00000000u 133 | #define EXTI_TRIGGER_RISING 0x00000001u 134 | #define EXTI_TRIGGER_FALLING 0x00000002u 135 | #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) 136 | /** 137 | * @} 138 | */ 139 | 140 | /** @defgroup EXTI_GPIOSel EXTI GPIOSel 141 | * @brief 142 | * @{ 143 | */ 144 | #define EXTI_GPIOA 0x00000000u 145 | #define EXTI_GPIOB 0x00000001u 146 | #define EXTI_GPIOC 0x00000002u 147 | #define EXTI_GPIOD 0x00000003u 148 | #if defined (GPIOE) 149 | #define EXTI_GPIOE 0x00000004u 150 | #endif /* GPIOE */ 151 | #if defined (GPIOF) 152 | #define EXTI_GPIOF 0x00000005u 153 | #endif /* GPIOF */ 154 | #if defined (GPIOG) 155 | #define EXTI_GPIOG 0x00000006u 156 | #endif /* GPIOG */ 157 | /** 158 | * @} 159 | */ 160 | 161 | /** 162 | * @} 163 | */ 164 | 165 | /* Exported macro ------------------------------------------------------------*/ 166 | /** @defgroup EXTI_Exported_Macros EXTI Exported Macros 167 | * @{ 168 | */ 169 | 170 | /** 171 | * @} 172 | */ 173 | 174 | /* Private constants --------------------------------------------------------*/ 175 | /** @defgroup EXTI_Private_Constants EXTI Private Constants 176 | * @{ 177 | */ 178 | /** 179 | * @brief EXTI Line property definition 180 | */ 181 | #define EXTI_PROPERTY_SHIFT 24u 182 | #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) 183 | #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) 184 | #define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) 185 | 186 | /** 187 | * @brief EXTI bit usage 188 | */ 189 | #define EXTI_PIN_MASK 0x0000001Fu 190 | 191 | /** 192 | * @brief EXTI Mask for interrupt & event mode 193 | */ 194 | #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) 195 | 196 | /** 197 | * @brief EXTI Mask for trigger possibilities 198 | */ 199 | #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) 200 | 201 | /** 202 | * @brief EXTI Line number 203 | */ 204 | #if defined(EXTI_IMR_IM19) 205 | #define EXTI_LINE_NB 20UL 206 | #elif defined(EXTI_IMR_IM18) 207 | #define EXTI_LINE_NB 19UL 208 | #else /* EXTI_IMR_IM17 */ 209 | #define EXTI_LINE_NB 18UL 210 | #endif /* EXTI_IMR_IM19 */ 211 | /** 212 | * @} 213 | */ 214 | 215 | /* Private macros ------------------------------------------------------------*/ 216 | /** @defgroup EXTI_Private_Macros EXTI Private Macros 217 | * @{ 218 | */ 219 | #define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ 220 | ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ 221 | (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ 222 | (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) 223 | 224 | #define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ 225 | (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) 226 | 227 | #define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) 228 | 229 | #define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) 230 | 231 | #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) 232 | 233 | #if defined (GPIOG) 234 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ 235 | ((__PORT__) == EXTI_GPIOB) || \ 236 | ((__PORT__) == EXTI_GPIOC) || \ 237 | ((__PORT__) == EXTI_GPIOD) || \ 238 | ((__PORT__) == EXTI_GPIOE) || \ 239 | ((__PORT__) == EXTI_GPIOF) || \ 240 | ((__PORT__) == EXTI_GPIOG)) 241 | #elif defined (GPIOF) 242 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ 243 | ((__PORT__) == EXTI_GPIOB) || \ 244 | ((__PORT__) == EXTI_GPIOC) || \ 245 | ((__PORT__) == EXTI_GPIOD) || \ 246 | ((__PORT__) == EXTI_GPIOE) || \ 247 | ((__PORT__) == EXTI_GPIOF)) 248 | #elif defined (GPIOE) 249 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ 250 | ((__PORT__) == EXTI_GPIOB) || \ 251 | ((__PORT__) == EXTI_GPIOC) || \ 252 | ((__PORT__) == EXTI_GPIOD) || \ 253 | ((__PORT__) == EXTI_GPIOE)) 254 | #else 255 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ 256 | ((__PORT__) == EXTI_GPIOB) || \ 257 | ((__PORT__) == EXTI_GPIOC) || \ 258 | ((__PORT__) == EXTI_GPIOD)) 259 | #endif /* GPIOG */ 260 | 261 | #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) 262 | 263 | /** 264 | * @} 265 | */ 266 | 267 | /* Exported functions --------------------------------------------------------*/ 268 | /** @defgroup EXTI_Exported_Functions EXTI Exported Functions 269 | * @brief EXTI Exported Functions 270 | * @{ 271 | */ 272 | 273 | /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions 274 | * @brief Configuration functions 275 | * @{ 276 | */ 277 | /* Configuration functions ****************************************************/ 278 | HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); 279 | HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); 280 | HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); 281 | HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); 282 | HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); 283 | /** 284 | * @} 285 | */ 286 | 287 | /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions 288 | * @brief IO operation functions 289 | * @{ 290 | */ 291 | /* IO operation functions *****************************************************/ 292 | void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); 293 | uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); 294 | void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); 295 | void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); 296 | 297 | /** 298 | * @} 299 | */ 300 | 301 | /** 302 | * @} 303 | */ 304 | 305 | /** 306 | * @} 307 | */ 308 | 309 | /** 310 | * @} 311 | */ 312 | 313 | #ifdef __cplusplus 314 | } 315 | #endif 316 | 317 | #endif /* STM32F1xx_HAL_EXTI_H */ 318 | 319 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_flash.h 4 | * @author MCD Application Team 5 | * @brief Header file of Flash HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file in 13 | * the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | ****************************************************************************** 16 | */ 17 | 18 | /* Define to prevent recursive inclusion -------------------------------------*/ 19 | #ifndef __STM32F1xx_HAL_FLASH_H 20 | #define __STM32F1xx_HAL_FLASH_H 21 | 22 | #ifdef __cplusplus 23 | extern "C" { 24 | #endif 25 | 26 | /* Includes ------------------------------------------------------------------*/ 27 | #include "stm32f1xx_hal_def.h" 28 | 29 | /** @addtogroup STM32F1xx_HAL_Driver 30 | * @{ 31 | */ 32 | 33 | /** @addtogroup FLASH 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup FLASH_Private_Constants 38 | * @{ 39 | */ 40 | #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ 41 | /** 42 | * @} 43 | */ 44 | 45 | /** @addtogroup FLASH_Private_Macros 46 | * @{ 47 | */ 48 | 49 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ 50 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ 51 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) 52 | 53 | #if defined(FLASH_ACR_LATENCY) 54 | #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ 55 | ((__LATENCY__) == FLASH_LATENCY_1) || \ 56 | ((__LATENCY__) == FLASH_LATENCY_2)) 57 | 58 | #else 59 | #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) 60 | #endif /* FLASH_ACR_LATENCY */ 61 | /** 62 | * @} 63 | */ 64 | 65 | /* Exported types ------------------------------------------------------------*/ 66 | /** @defgroup FLASH_Exported_Types FLASH Exported Types 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @brief FLASH Procedure structure definition 72 | */ 73 | typedef enum 74 | { 75 | FLASH_PROC_NONE = 0U, 76 | FLASH_PROC_PAGEERASE = 1U, 77 | FLASH_PROC_MASSERASE = 2U, 78 | FLASH_PROC_PROGRAMHALFWORD = 3U, 79 | FLASH_PROC_PROGRAMWORD = 4U, 80 | FLASH_PROC_PROGRAMDOUBLEWORD = 5U 81 | } FLASH_ProcedureTypeDef; 82 | 83 | /** 84 | * @brief FLASH handle Structure definition 85 | */ 86 | typedef struct 87 | { 88 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 89 | 90 | __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ 91 | 92 | __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ 93 | 94 | __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ 95 | 96 | HAL_LockTypeDef Lock; /*!< FLASH locking object */ 97 | 98 | __IO uint32_t ErrorCode; /*!< FLASH error code 99 | This parameter can be a value of @ref FLASH_Error_Codes */ 100 | } FLASH_ProcessTypeDef; 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /* Exported constants --------------------------------------------------------*/ 107 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 108 | * @{ 109 | */ 110 | 111 | /** @defgroup FLASH_Error_Codes FLASH Error Codes 112 | * @{ 113 | */ 114 | 115 | #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ 116 | #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ 117 | #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ 118 | #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ 119 | 120 | /** 121 | * @} 122 | */ 123 | 124 | /** @defgroup FLASH_Type_Program FLASH Type Program 125 | * @{ 126 | */ 127 | #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) 181 | 182 | /** 183 | * @brief Disable the FLASH half cycle access. 184 | * @note half cycle access can only be used with a low-frequency clock of less than 185 | 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. 186 | * @retval None 187 | */ 188 | #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) 189 | 190 | /** 191 | * @} 192 | */ 193 | 194 | #if defined(FLASH_ACR_LATENCY) 195 | /** @defgroup FLASH_EM_Latency FLASH Latency 196 | * @brief macros to handle FLASH Latency 197 | * @{ 198 | */ 199 | 200 | /** 201 | * @brief Set the FLASH Latency. 202 | * @param __LATENCY__ FLASH Latency 203 | * The value of this parameter depend on device used within the same series 204 | * @retval None 205 | */ 206 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) 207 | 208 | 209 | /** 210 | * @brief Get the FLASH Latency. 211 | * @retval FLASH Latency 212 | * The value of this parameter depend on device used within the same series 213 | */ 214 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 215 | 216 | /** 217 | * @} 218 | */ 219 | 220 | #endif /* FLASH_ACR_LATENCY */ 221 | /** @defgroup FLASH_Prefetch FLASH Prefetch 222 | * @brief macros to handle FLASH Prefetch buffer 223 | * @{ 224 | */ 225 | /** 226 | * @brief Enable the FLASH prefetch buffer. 227 | * @retval None 228 | */ 229 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) 230 | 231 | /** 232 | * @brief Disable the FLASH prefetch buffer. 233 | * @retval None 234 | */ 235 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) 236 | 237 | /** 238 | * @} 239 | */ 240 | 241 | /** 242 | * @} 243 | */ 244 | 245 | /* Include FLASH HAL Extended module */ 246 | #include "stm32f1xx_hal_flash_ex.h" 247 | 248 | /* Exported functions --------------------------------------------------------*/ 249 | /** @addtogroup FLASH_Exported_Functions 250 | * @{ 251 | */ 252 | 253 | /** @addtogroup FLASH_Exported_Functions_Group1 254 | * @{ 255 | */ 256 | /* IO operation functions *****************************************************/ 257 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 258 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 259 | 260 | /* FLASH IRQ handler function */ 261 | void HAL_FLASH_IRQHandler(void); 262 | /* Callbacks in non blocking modes */ 263 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 264 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 265 | 266 | /** 267 | * @} 268 | */ 269 | 270 | /** @addtogroup FLASH_Exported_Functions_Group2 271 | * @{ 272 | */ 273 | /* Peripheral Control functions ***********************************************/ 274 | HAL_StatusTypeDef HAL_FLASH_Unlock(void); 275 | HAL_StatusTypeDef HAL_FLASH_Lock(void); 276 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 277 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 278 | void HAL_FLASH_OB_Launch(void); 279 | 280 | /** 281 | * @} 282 | */ 283 | 284 | /** @addtogroup FLASH_Exported_Functions_Group3 285 | * @{ 286 | */ 287 | /* Peripheral State and Error functions ***************************************/ 288 | uint32_t HAL_FLASH_GetError(void); 289 | 290 | /** 291 | * @} 292 | */ 293 | 294 | /** 295 | * @} 296 | */ 297 | 298 | /* Private function -------------------------------------------------*/ 299 | /** @addtogroup FLASH_Private_Functions 300 | * @{ 301 | */ 302 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 303 | #if defined(FLASH_BANK2_END) 304 | HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); 305 | #endif /* FLASH_BANK2_END */ 306 | 307 | /** 308 | * @} 309 | */ 310 | 311 | /** 312 | * @} 313 | */ 314 | 315 | /** 316 | * @} 317 | */ 318 | 319 | #ifdef __cplusplus 320 | } 321 | #endif 322 | 323 | #endif /* __STM32F1xx_HAL_FLASH_H */ 324 | 325 | 326 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_gpio.h 4 | * @author MCD Application Team 5 | * @brief Header file of GPIO HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32F1xx_HAL_GPIO_H 21 | #define STM32F1xx_HAL_GPIO_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32f1xx_hal_def.h" 29 | 30 | /** @addtogroup STM32F1xx_HAL_Driver 31 | * @{ 32 | */ 33 | 34 | /** @addtogroup GPIO 35 | * @{ 36 | */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /** @defgroup GPIO_Exported_Types GPIO Exported Types 40 | * @{ 41 | */ 42 | 43 | /** 44 | * @brief GPIO Init structure definition 45 | */ 46 | typedef struct 47 | { 48 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured. 49 | This parameter can be any value of @ref GPIO_pins_define */ 50 | 51 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 52 | This parameter can be a value of @ref GPIO_mode_define */ 53 | 54 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. 55 | This parameter can be a value of @ref GPIO_pull_define */ 56 | 57 | uint32_t Speed; /*!< Specifies the speed for the selected pins. 58 | This parameter can be a value of @ref GPIO_speed_define */ 59 | } GPIO_InitTypeDef; 60 | 61 | /** 62 | * @brief GPIO Bit SET and Bit RESET enumeration 63 | */ 64 | typedef enum 65 | { 66 | GPIO_PIN_RESET = 0u, 67 | GPIO_PIN_SET 68 | } GPIO_PinState; 69 | /** 70 | * @} 71 | */ 72 | 73 | /* Exported constants --------------------------------------------------------*/ 74 | 75 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants 76 | * @{ 77 | */ 78 | 79 | /** @defgroup GPIO_pins_define GPIO pins define 80 | * @{ 81 | */ 82 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ 83 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ 84 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ 85 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ 86 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ 87 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ 88 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ 89 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ 90 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ 91 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ 92 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ 93 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ 94 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ 95 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ 96 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ 97 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ 98 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ 99 | 100 | #define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */ 101 | /** 102 | * @} 103 | */ 104 | 105 | /** @defgroup GPIO_mode_define GPIO mode define 106 | * @brief GPIO Configuration Mode 107 | * Elements values convention: 0xX0yz00YZ 108 | * - X : GPIO mode or EXTI Mode 109 | * - y : External IT or Event trigger detection 110 | * - z : IO configuration on External IT or Event 111 | * - Y : Output type (Push Pull or Open Drain) 112 | * - Z : IO Direction mode (Input, Output, Alternate or Analog) 113 | * @{ 114 | */ 115 | #define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */ 116 | #define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */ 117 | #define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */ 118 | #define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */ 119 | #define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */ 120 | #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ 121 | 122 | #define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */ 123 | 124 | #define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */ 125 | #define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */ 126 | #define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 127 | 128 | #define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */ 129 | #define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */ 130 | #define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */ 131 | 132 | /** 133 | * @} 134 | */ 135 | 136 | /** @defgroup GPIO_speed_define GPIO speed define 137 | * @brief GPIO Output Maximum frequency 138 | * @{ 139 | */ 140 | #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ 141 | #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ 142 | #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ 143 | 144 | /** 145 | * @} 146 | */ 147 | 148 | /** @defgroup GPIO_pull_define GPIO pull define 149 | * @brief GPIO Pull-Up or Pull-Down Activation 150 | * @{ 151 | */ 152 | #define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ 153 | #define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ 154 | #define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ 155 | /** 156 | * @} 157 | */ 158 | 159 | /** 160 | * @} 161 | */ 162 | 163 | /* Exported macro ------------------------------------------------------------*/ 164 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros 165 | * @{ 166 | */ 167 | 168 | /** 169 | * @brief Checks whether the specified EXTI line flag is set or not. 170 | * @param __EXTI_LINE__: specifies the EXTI line flag to check. 171 | * This parameter can be GPIO_PIN_x where x can be(0..15) 172 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 173 | */ 174 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 175 | 176 | /** 177 | * @brief Clears the EXTI's line pending flags. 178 | * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. 179 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 180 | * @retval None 181 | */ 182 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 183 | 184 | /** 185 | * @brief Checks whether the specified EXTI line is asserted or not. 186 | * @param __EXTI_LINE__: specifies the EXTI line to check. 187 | * This parameter can be GPIO_PIN_x where x can be(0..15) 188 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 189 | */ 190 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 191 | 192 | /** 193 | * @brief Clears the EXTI's line pending bits. 194 | * @param __EXTI_LINE__: specifies the EXTI lines to clear. 195 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 196 | * @retval None 197 | */ 198 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 199 | 200 | /** 201 | * @brief Generates a Software interrupt on selected EXTI line. 202 | * @param __EXTI_LINE__: specifies the EXTI line to check. 203 | * This parameter can be GPIO_PIN_x where x can be(0..15) 204 | * @retval None 205 | */ 206 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) 207 | /** 208 | * @} 209 | */ 210 | 211 | /* Include GPIO HAL Extension module */ 212 | #include "stm32f1xx_hal_gpio_ex.h" 213 | 214 | /* Exported functions --------------------------------------------------------*/ 215 | /** @addtogroup GPIO_Exported_Functions 216 | * @{ 217 | */ 218 | 219 | /** @addtogroup GPIO_Exported_Functions_Group1 220 | * @{ 221 | */ 222 | /* Initialization and de-initialization functions *****************************/ 223 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); 224 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); 225 | /** 226 | * @} 227 | */ 228 | 229 | /** @addtogroup GPIO_Exported_Functions_Group2 230 | * @{ 231 | */ 232 | /* IO operation functions *****************************************************/ 233 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 234 | void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); 235 | void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 236 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 237 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); 238 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); 239 | 240 | /** 241 | * @} 242 | */ 243 | 244 | /** 245 | * @} 246 | */ 247 | /* Private types -------------------------------------------------------------*/ 248 | /* Private variables ---------------------------------------------------------*/ 249 | /* Private constants ---------------------------------------------------------*/ 250 | /** @defgroup GPIO_Private_Constants GPIO Private Constants 251 | * @{ 252 | */ 253 | 254 | /** 255 | * @} 256 | */ 257 | 258 | /* Private macros ------------------------------------------------------------*/ 259 | /** @defgroup GPIO_Private_Macros GPIO Private Macros 260 | * @{ 261 | */ 262 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) 263 | #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u)) 264 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ 265 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ 266 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ 267 | ((MODE) == GPIO_MODE_AF_PP) ||\ 268 | ((MODE) == GPIO_MODE_AF_OD) ||\ 269 | ((MODE) == GPIO_MODE_IT_RISING) ||\ 270 | ((MODE) == GPIO_MODE_IT_FALLING) ||\ 271 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ 272 | ((MODE) == GPIO_MODE_EVT_RISING) ||\ 273 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\ 274 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ 275 | ((MODE) == GPIO_MODE_ANALOG)) 276 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ 277 | ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) 278 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ 279 | ((PULL) == GPIO_PULLDOWN)) 280 | /** 281 | * @} 282 | */ 283 | 284 | /* Private functions ---------------------------------------------------------*/ 285 | /** @defgroup GPIO_Private_Functions GPIO Private Functions 286 | * @{ 287 | */ 288 | 289 | /** 290 | * @} 291 | */ 292 | 293 | /** 294 | * @} 295 | */ 296 | 297 | /** 298 | * @} 299 | */ 300 | 301 | #ifdef __cplusplus 302 | } 303 | #endif 304 | 305 | #endif /* STM32F1xx_HAL_GPIO_H */ 306 | 307 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_pwr.h 4 | * @author MCD Application Team 5 | * @brief Header file of PWR HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef __STM32F1xx_HAL_PWR_H 21 | #define __STM32F1xx_HAL_PWR_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32f1xx_hal_def.h" 29 | 30 | /** @addtogroup STM32F1xx_HAL_Driver 31 | * @{ 32 | */ 33 | 34 | /** @addtogroup PWR 35 | * @{ 36 | */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | 40 | /** @defgroup PWR_Exported_Types PWR Exported Types 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief PWR PVD configuration structure definition 46 | */ 47 | typedef struct 48 | { 49 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. 50 | This parameter can be a value of @ref PWR_PVD_detection_level */ 51 | 52 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 53 | This parameter can be a value of @ref PWR_PVD_Mode */ 54 | }PWR_PVDTypeDef; 55 | 56 | 57 | /** 58 | * @} 59 | */ 60 | 61 | 62 | /* Internal constants --------------------------------------------------------*/ 63 | 64 | /** @addtogroup PWR_Private_Constants 65 | * @{ 66 | */ 67 | 68 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | 75 | /* Exported constants --------------------------------------------------------*/ 76 | 77 | /** @defgroup PWR_Exported_Constants PWR Exported Constants 78 | * @{ 79 | */ 80 | 81 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level 82 | * @{ 83 | */ 84 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 85 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 86 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 87 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 88 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 89 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 90 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 91 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 92 | 93 | /** 94 | * @} 95 | */ 96 | 97 | /** @defgroup PWR_PVD_Mode PWR PVD Mode 98 | * @{ 99 | */ 100 | #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ 101 | #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ 102 | #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ 103 | #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 104 | #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ 105 | #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ 106 | #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ 107 | 108 | /** 109 | * @} 110 | */ 111 | 112 | 113 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins 114 | * @{ 115 | */ 116 | 117 | #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode 124 | * @{ 125 | */ 126 | #define PWR_MAINREGULATOR_ON 0x00000000U 127 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS 128 | 129 | /** 130 | * @} 131 | */ 132 | 133 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 134 | * @{ 135 | */ 136 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) 137 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) 138 | 139 | /** 140 | * @} 141 | */ 142 | 143 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 144 | * @{ 145 | */ 146 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) 147 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** @defgroup PWR_Flag PWR Flag 154 | * @{ 155 | */ 156 | #define PWR_FLAG_WU PWR_CSR_WUF 157 | #define PWR_FLAG_SB PWR_CSR_SBF 158 | #define PWR_FLAG_PVDO PWR_CSR_PVDO 159 | 160 | 161 | /** 162 | * @} 163 | */ 164 | 165 | /** 166 | * @} 167 | */ 168 | 169 | /* Exported macro ------------------------------------------------------------*/ 170 | /** @defgroup PWR_Exported_Macros PWR Exported Macros 171 | * @{ 172 | */ 173 | 174 | /** @brief Check PWR flag is set or not. 175 | * @param __FLAG__: specifies the flag to check. 176 | * This parameter can be one of the following values: 177 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 178 | * was received from the WKUP pin or from the RTC alarm 179 | * An additional wakeup event is detected if the WKUP pin is enabled 180 | * (by setting the EWUP bit) when the WKUP pin level is already high. 181 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was 182 | * resumed from StandBy mode. 183 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 184 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 185 | * For this reason, this bit is equal to 0 after Standby or reset 186 | * until the PVDE bit is set. 187 | * @retval The new state of __FLAG__ (TRUE or FALSE). 188 | */ 189 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) 190 | 191 | /** @brief Clear the PWR's pending flags. 192 | * @param __FLAG__: specifies the flag to clear. 193 | * This parameter can be one of the following values: 194 | * @arg PWR_FLAG_WU: Wake Up flag 195 | * @arg PWR_FLAG_SB: StandBy flag 196 | */ 197 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) 198 | 199 | /** 200 | * @brief Enable interrupt on PVD Exti Line 16. 201 | * @retval None. 202 | */ 203 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) 204 | 205 | /** 206 | * @brief Disable interrupt on PVD Exti Line 16. 207 | * @retval None. 208 | */ 209 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) 210 | 211 | /** 212 | * @brief Enable event on PVD Exti Line 16. 213 | * @retval None. 214 | */ 215 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) 216 | 217 | /** 218 | * @brief Disable event on PVD Exti Line 16. 219 | * @retval None. 220 | */ 221 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) 222 | 223 | 224 | /** 225 | * @brief PVD EXTI line configuration: set falling edge trigger. 226 | * @retval None. 227 | */ 228 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 229 | 230 | 231 | /** 232 | * @brief Disable the PVD Extended Interrupt Falling Trigger. 233 | * @retval None. 234 | */ 235 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 236 | 237 | 238 | /** 239 | * @brief PVD EXTI line configuration: set rising edge trigger. 240 | * @retval None. 241 | */ 242 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 243 | 244 | /** 245 | * @brief Disable the PVD Extended Interrupt Rising Trigger. 246 | * This parameter can be: 247 | * @retval None. 248 | */ 249 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 250 | 251 | /** 252 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. 253 | * @retval None. 254 | */ 255 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 256 | 257 | /** 258 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 259 | * This parameter can be: 260 | * @retval None. 261 | */ 262 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 263 | 264 | 265 | 266 | /** 267 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. 268 | * @retval EXTI PVD Line Status. 269 | */ 270 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) 271 | 272 | /** 273 | * @brief Clear the PVD EXTI flag. 274 | * @retval None. 275 | */ 276 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) 277 | 278 | /** 279 | * @brief Generate a Software interrupt on selected EXTI line. 280 | * @retval None. 281 | */ 282 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) 283 | /** 284 | * @} 285 | */ 286 | 287 | /* Private macro -------------------------------------------------------------*/ 288 | /** @defgroup PWR_Private_Macros PWR Private Macros 289 | * @{ 290 | */ 291 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ 292 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ 293 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ 294 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 295 | 296 | 297 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ 298 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ 299 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ 300 | ((MODE) == PWR_PVD_MODE_NORMAL)) 301 | 302 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) 303 | 304 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ 305 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 306 | 307 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 308 | 309 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 310 | 311 | /** 312 | * @} 313 | */ 314 | 315 | 316 | 317 | /* Exported functions --------------------------------------------------------*/ 318 | 319 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions 320 | * @{ 321 | */ 322 | 323 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 324 | * @{ 325 | */ 326 | 327 | /* Initialization and de-initialization functions *******************************/ 328 | void HAL_PWR_DeInit(void); 329 | void HAL_PWR_EnableBkUpAccess(void); 330 | void HAL_PWR_DisableBkUpAccess(void); 331 | 332 | /** 333 | * @} 334 | */ 335 | 336 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 337 | * @{ 338 | */ 339 | 340 | /* Peripheral Control functions ************************************************/ 341 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); 342 | /* #define HAL_PWR_ConfigPVD 12*/ 343 | void HAL_PWR_EnablePVD(void); 344 | void HAL_PWR_DisablePVD(void); 345 | 346 | /* WakeUp pins configuration functions ****************************************/ 347 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); 348 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 349 | 350 | /* Low Power modes configuration functions ************************************/ 351 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 352 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 353 | void HAL_PWR_EnterSTANDBYMode(void); 354 | 355 | void HAL_PWR_EnableSleepOnExit(void); 356 | void HAL_PWR_DisableSleepOnExit(void); 357 | void HAL_PWR_EnableSEVOnPend(void); 358 | void HAL_PWR_DisableSEVOnPend(void); 359 | 360 | 361 | 362 | void HAL_PWR_PVD_IRQHandler(void); 363 | void HAL_PWR_PVDCallback(void); 364 | /** 365 | * @} 366 | */ 367 | 368 | /** 369 | * @} 370 | */ 371 | 372 | /** 373 | * @} 374 | */ 375 | 376 | /** 377 | * @} 378 | */ 379 | 380 | #ifdef __cplusplus 381 | } 382 | #endif 383 | 384 | 385 | #endif /* __STM32F1xx_HAL_PWR_H */ 386 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_tim_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of TIM HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32F1xx_HAL_TIM_EX_H 21 | #define STM32F1xx_HAL_TIM_EX_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32f1xx_hal_def.h" 29 | 30 | /** @addtogroup STM32F1xx_HAL_Driver 31 | * @{ 32 | */ 33 | 34 | /** @addtogroup TIMEx 35 | * @{ 36 | */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types 40 | * @{ 41 | */ 42 | 43 | /** 44 | * @brief TIM Hall sensor Configuration Structure definition 45 | */ 46 | 47 | typedef struct 48 | { 49 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 50 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 51 | 52 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 53 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 54 | 55 | uint32_t IC1Filter; /*!< Specifies the input capture filter. 56 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 57 | 58 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 59 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 60 | } TIM_HallSensor_InitTypeDef; 61 | /** 62 | * @} 63 | */ 64 | /* End of exported types -----------------------------------------------------*/ 65 | 66 | /* Exported constants --------------------------------------------------------*/ 67 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants 68 | * @{ 69 | */ 70 | 71 | /** @defgroup TIMEx_Remap TIM Extended Remapping 72 | * @{ 73 | */ 74 | /** 75 | * @} 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | /* End of exported constants -------------------------------------------------*/ 82 | 83 | /* Exported macro ------------------------------------------------------------*/ 84 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros 85 | * @{ 86 | */ 87 | 88 | /** 89 | * @} 90 | */ 91 | /* End of exported macro -----------------------------------------------------*/ 92 | 93 | /* Private macro -------------------------------------------------------------*/ 94 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros 95 | * @{ 96 | */ 97 | 98 | /** 99 | * @} 100 | */ 101 | /* End of private macro ------------------------------------------------------*/ 102 | 103 | /* Exported functions --------------------------------------------------------*/ 104 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions 105 | * @{ 106 | */ 107 | 108 | /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 109 | * @brief Timer Hall Sensor functions 110 | * @{ 111 | */ 112 | /* Timer Hall Sensor functions **********************************************/ 113 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); 114 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); 115 | 116 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); 117 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); 118 | 119 | /* Blocking mode: Polling */ 120 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); 121 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); 122 | /* Non-Blocking mode: Interrupt */ 123 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); 124 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); 125 | /* Non-Blocking mode: DMA */ 126 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 127 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); 128 | /** 129 | * @} 130 | */ 131 | 132 | /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions 133 | * @brief Timer Complementary Output Compare functions 134 | * @{ 135 | */ 136 | /* Timer Complementary Output Compare functions *****************************/ 137 | /* Blocking mode: Polling */ 138 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 139 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 140 | 141 | /* Non-Blocking mode: Interrupt */ 142 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 143 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 144 | 145 | /* Non-Blocking mode: DMA */ 146 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 147 | uint16_t Length); 148 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 149 | /** 150 | * @} 151 | */ 152 | 153 | /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions 154 | * @brief Timer Complementary PWM functions 155 | * @{ 156 | */ 157 | /* Timer Complementary PWM functions ****************************************/ 158 | /* Blocking mode: Polling */ 159 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 160 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 161 | 162 | /* Non-Blocking mode: Interrupt */ 163 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 164 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 165 | /* Non-Blocking mode: DMA */ 166 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 167 | uint16_t Length); 168 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 169 | /** 170 | * @} 171 | */ 172 | 173 | /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions 174 | * @brief Timer Complementary One Pulse functions 175 | * @{ 176 | */ 177 | /* Timer Complementary One Pulse functions **********************************/ 178 | /* Blocking mode: Polling */ 179 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 180 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 181 | 182 | /* Non-Blocking mode: Interrupt */ 183 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 184 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 185 | /** 186 | * @} 187 | */ 188 | 189 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions 190 | * @brief Peripheral Control functions 191 | * @{ 192 | */ 193 | /* Extended Control functions ************************************************/ 194 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 195 | uint32_t CommutationSource); 196 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 197 | uint32_t CommutationSource); 198 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 199 | uint32_t CommutationSource); 200 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, 201 | const TIM_MasterConfigTypeDef *sMasterConfig); 202 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 203 | const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); 204 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); 205 | /** 206 | * @} 207 | */ 208 | 209 | /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 210 | * @brief Extended Callbacks functions 211 | * @{ 212 | */ 213 | /* Extended Callback **********************************************************/ 214 | void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); 215 | void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); 216 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); 217 | /** 218 | * @} 219 | */ 220 | 221 | /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 222 | * @brief Extended Peripheral State functions 223 | * @{ 224 | */ 225 | /* Extended Peripheral State functions ***************************************/ 226 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); 227 | HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); 228 | /** 229 | * @} 230 | */ 231 | 232 | /** 233 | * @} 234 | */ 235 | /* End of exported functions -------------------------------------------------*/ 236 | 237 | /* Private functions----------------------------------------------------------*/ 238 | /** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions 239 | * @{ 240 | */ 241 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); 242 | void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); 243 | /** 244 | * @} 245 | */ 246 | /* End of private functions --------------------------------------------------*/ 247 | 248 | /** 249 | * @} 250 | */ 251 | 252 | /** 253 | * @} 254 | */ 255 | 256 | #ifdef __cplusplus 257 | } 258 | #endif 259 | 260 | 261 | #endif /* STM32F1xx_HAL_TIM_EX_H */ 262 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_ll_utils.h 4 | * @author MCD Application Team 5 | * @brief Header file of UTILS LL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | @verbatim 18 | ============================================================================== 19 | ##### How to use this driver ##### 20 | ============================================================================== 21 | [..] 22 | The LL UTILS driver contains a set of generic APIs that can be 23 | used by user: 24 | (+) Device electronic signature 25 | (+) Timing functions 26 | (+) PLL configuration functions 27 | 28 | @endverbatim 29 | ****************************************************************************** 30 | */ 31 | 32 | /* Define to prevent recursive inclusion -------------------------------------*/ 33 | #ifndef __STM32F1xx_LL_UTILS_H 34 | #define __STM32F1xx_LL_UTILS_H 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /* Includes ------------------------------------------------------------------*/ 41 | #include "stm32f1xx.h" 42 | 43 | /** @addtogroup STM32F1xx_LL_Driver 44 | * @{ 45 | */ 46 | 47 | /** @defgroup UTILS_LL UTILS 48 | * @{ 49 | */ 50 | 51 | /* Private types -------------------------------------------------------------*/ 52 | /* Private variables ---------------------------------------------------------*/ 53 | 54 | /* Private constants ---------------------------------------------------------*/ 55 | /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants 56 | * @{ 57 | */ 58 | 59 | /* Max delay can be used in LL_mDelay */ 60 | #define LL_MAX_DELAY 0xFFFFFFFFU 61 | 62 | /** 63 | * @brief Unique device ID register base address 64 | */ 65 | #define UID_BASE_ADDRESS UID_BASE 66 | 67 | /** 68 | * @brief Flash size data register base address 69 | */ 70 | #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /* Private macros ------------------------------------------------------------*/ 77 | /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros 78 | * @{ 79 | */ 80 | /** 81 | * @} 82 | */ 83 | /* Exported types ------------------------------------------------------------*/ 84 | /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures 85 | * @{ 86 | */ 87 | /** 88 | * @brief UTILS PLL structure definition 89 | */ 90 | typedef struct 91 | { 92 | uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. 93 | This parameter can be a value of @ref RCC_LL_EC_PLL_MUL 94 | 95 | This feature can be modified afterwards using unitary function 96 | @ref LL_RCC_PLL_ConfigDomain_SYS(). */ 97 | 98 | uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. 99 | This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV 100 | 101 | This feature can be modified afterwards using unitary function 102 | @ref LL_RCC_PLL_ConfigDomain_SYS(). */ 103 | } LL_UTILS_PLLInitTypeDef; 104 | 105 | /** 106 | * @brief UTILS System, AHB and APB buses clock configuration structure definition 107 | */ 108 | typedef struct 109 | { 110 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 111 | This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV 112 | 113 | This feature can be modified afterwards using unitary function 114 | @ref LL_RCC_SetAHBPrescaler(). */ 115 | 116 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 117 | This parameter can be a value of @ref RCC_LL_EC_APB1_DIV 118 | 119 | This feature can be modified afterwards using unitary function 120 | @ref LL_RCC_SetAPB1Prescaler(). */ 121 | 122 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 123 | This parameter can be a value of @ref RCC_LL_EC_APB2_DIV 124 | 125 | This feature can be modified afterwards using unitary function 126 | @ref LL_RCC_SetAPB2Prescaler(). */ 127 | 128 | } LL_UTILS_ClkInitTypeDef; 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /* Exported constants --------------------------------------------------------*/ 135 | /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants 136 | * @{ 137 | */ 138 | 139 | /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation 140 | * @{ 141 | */ 142 | #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ 143 | #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ 144 | /** 145 | * @} 146 | */ 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /* Exported macro ------------------------------------------------------------*/ 153 | 154 | /* Exported functions --------------------------------------------------------*/ 155 | /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions 156 | * @{ 157 | */ 158 | 159 | /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE 160 | * @{ 161 | */ 162 | 163 | /** 164 | * @brief Get Word0 of the unique device identifier (UID based on 96 bits) 165 | * @retval UID[31:0] 166 | */ 167 | __STATIC_INLINE uint32_t LL_GetUID_Word0(void) 168 | { 169 | return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); 170 | } 171 | 172 | /** 173 | * @brief Get Word1 of the unique device identifier (UID based on 96 bits) 174 | * @retval UID[63:32] 175 | */ 176 | __STATIC_INLINE uint32_t LL_GetUID_Word1(void) 177 | { 178 | return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); 179 | } 180 | 181 | /** 182 | * @brief Get Word2 of the unique device identifier (UID based on 96 bits) 183 | * @retval UID[95:64] 184 | */ 185 | __STATIC_INLINE uint32_t LL_GetUID_Word2(void) 186 | { 187 | return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); 188 | } 189 | 190 | /** 191 | * @brief Get Flash memory size 192 | * @note This bitfield indicates the size of the device Flash memory expressed in 193 | * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. 194 | * @retval FLASH_SIZE[15:0]: Flash memory size 195 | */ 196 | __STATIC_INLINE uint32_t LL_GetFlashSize(void) 197 | { 198 | return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); 199 | } 200 | 201 | 202 | /** 203 | * @} 204 | */ 205 | 206 | /** @defgroup UTILS_LL_EF_DELAY DELAY 207 | * @{ 208 | */ 209 | 210 | /** 211 | * @brief This function configures the Cortex-M SysTick source of the time base. 212 | * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) 213 | * @note When a RTOS is used, it is recommended to avoid changing the SysTick 214 | * configuration by calling this function, for a delay use rather osDelay RTOS service. 215 | * @param Ticks Number of ticks 216 | * @retval None 217 | */ 218 | __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) 219 | { 220 | /* Configure the SysTick to have interrupt in 1ms time base */ 221 | SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ 222 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 223 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 224 | SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ 225 | } 226 | 227 | void LL_Init1msTick(uint32_t HCLKFrequency); 228 | void LL_mDelay(uint32_t Delay); 229 | 230 | /** 231 | * @} 232 | */ 233 | 234 | /** @defgroup UTILS_EF_SYSTEM SYSTEM 235 | * @{ 236 | */ 237 | 238 | void LL_SetSystemCoreClock(uint32_t HCLKFrequency); 239 | #if defined(FLASH_ACR_LATENCY) 240 | ErrorStatus LL_SetFlashLatency(uint32_t Frequency); 241 | #endif /* FLASH_ACR_LATENCY */ 242 | ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, 243 | LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 244 | ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, 245 | LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 246 | #if defined(RCC_PLL2_SUPPORT) 247 | ErrorStatus LL_PLL_ConfigSystemClock_PLL2(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, 248 | LL_UTILS_PLLInitTypeDef *UTILS_PLL2InitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 249 | #endif /* RCC_PLL2_SUPPORT */ 250 | /** 251 | * @} 252 | */ 253 | 254 | /** 255 | * @} 256 | */ 257 | 258 | /** 259 | * @} 260 | */ 261 | 262 | /** 263 | * @} 264 | */ 265 | 266 | #ifdef __cplusplus 267 | } 268 | #endif 269 | 270 | #endif /* __STM32F1xx_LL_UTILS_H */ 271 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/License.md: -------------------------------------------------------------------------------- 1 | Copyright 2016 STMicroelectronics. 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without modification, 5 | are permitted provided that the following conditions are met: 6 | 7 | 1. Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | 2. Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | 14 | 3. Neither the name of the copyright holder nor the names of its contributors 15 | may be used to endorse or promote products derived from this software without 16 | specific prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 19 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 22 | ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 | ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_gpio_ex.c 4 | * @author MCD Application Team 5 | * @brief GPIO Extension HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. 8 | * + Extended features functions 9 | * 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2016 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | @verbatim 22 | ============================================================================== 23 | ##### GPIO Peripheral extension features ##### 24 | ============================================================================== 25 | [..] GPIO module on STM32F1 family, manage also the AFIO register: 26 | (+) Possibility to use the EVENTOUT Cortex feature 27 | 28 | ##### How to use this driver ##### 29 | ============================================================================== 30 | [..] This driver provides functions to use EVENTOUT Cortex feature 31 | (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() 32 | (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() 33 | (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() 34 | 35 | @endverbatim 36 | ****************************************************************************** 37 | */ 38 | 39 | /* Includes ------------------------------------------------------------------*/ 40 | #include "stm32f1xx_hal.h" 41 | 42 | /** @addtogroup STM32F1xx_HAL_Driver 43 | * @{ 44 | */ 45 | 46 | /** @defgroup GPIOEx GPIOEx 47 | * @brief GPIO HAL module driver 48 | * @{ 49 | */ 50 | 51 | #ifdef HAL_GPIO_MODULE_ENABLED 52 | 53 | /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions 54 | * @{ 55 | */ 56 | 57 | /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions 58 | * @brief Extended features functions 59 | * 60 | @verbatim 61 | ============================================================================== 62 | ##### Extended features functions ##### 63 | ============================================================================== 64 | [..] This section provides functions allowing to: 65 | (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() 66 | (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() 67 | (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() 68 | 69 | @endverbatim 70 | * @{ 71 | */ 72 | 73 | /** 74 | * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. 75 | * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. 76 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. 77 | * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. 78 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. 79 | * @retval None 80 | */ 81 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) 82 | { 83 | /* Verify the parameters */ 84 | assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); 85 | assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); 86 | 87 | /* Apply the new configuration */ 88 | MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); 89 | } 90 | 91 | /** 92 | * @brief Enables the Event Output. 93 | * @retval None 94 | */ 95 | void HAL_GPIOEx_EnableEventout(void) 96 | { 97 | SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 98 | } 99 | 100 | /** 101 | * @brief Disables the Event Output. 102 | * @retval None 103 | */ 104 | void HAL_GPIOEx_DisableEventout(void) 105 | { 106 | CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 107 | } 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | #endif /* HAL_GPIO_MODULE_ENABLED */ 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** 124 | * @} 125 | */ 126 | 127 | -------------------------------------------------------------------------------- /Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __MAIN_H 23 | #define __MAIN_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f1xx_hal.h" 31 | 32 | /* Private includes ----------------------------------------------------------*/ 33 | /* USER CODE BEGIN Includes */ 34 | 35 | /* USER CODE END Includes */ 36 | 37 | /* Exported types ------------------------------------------------------------*/ 38 | /* USER CODE BEGIN ET */ 39 | 40 | /* USER CODE END ET */ 41 | 42 | /* Exported constants --------------------------------------------------------*/ 43 | /* USER CODE BEGIN EC */ 44 | 45 | /* USER CODE END EC */ 46 | 47 | /* Exported macro ------------------------------------------------------------*/ 48 | /* USER CODE BEGIN EM */ 49 | 50 | /* USER CODE END EM */ 51 | 52 | /* Exported functions prototypes ---------------------------------------------*/ 53 | void Error_Handler(void); 54 | 55 | /* USER CODE BEGIN EFP */ 56 | 57 | /* USER CODE END EFP */ 58 | 59 | /* Private defines -----------------------------------------------------------*/ 60 | 61 | /* USER CODE BEGIN Private defines */ 62 | 63 | /* USER CODE END Private defines */ 64 | 65 | #ifdef __cplusplus 66 | } 67 | #endif 68 | 69 | #endif /* __MAIN_H */ 70 | -------------------------------------------------------------------------------- /Inc/stm32f1xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2023 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F1xx_IT_H 22 | #define __STM32F1xx_IT_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Private includes ----------------------------------------------------------*/ 29 | /* USER CODE BEGIN Includes */ 30 | 31 | /* USER CODE END Includes */ 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN ET */ 35 | 36 | /* USER CODE END ET */ 37 | 38 | /* Exported constants --------------------------------------------------------*/ 39 | /* USER CODE BEGIN EC */ 40 | 41 | /* USER CODE END EC */ 42 | 43 | /* Exported macro ------------------------------------------------------------*/ 44 | /* USER CODE BEGIN EM */ 45 | 46 | /* USER CODE END EM */ 47 | 48 | /* Exported functions prototypes ---------------------------------------------*/ 49 | void NMI_Handler(void); 50 | void HardFault_Handler(void); 51 | void MemManage_Handler(void); 52 | void BusFault_Handler(void); 53 | void UsageFault_Handler(void); 54 | void SVC_Handler(void); 55 | void DebugMon_Handler(void); 56 | void PendSV_Handler(void); 57 | void SysTick_Handler(void); 58 | /* USER CODE BEGIN EFP */ 59 | 60 | /* USER CODE END EFP */ 61 | 62 | #ifdef __cplusplus 63 | } 64 | #endif 65 | 66 | #endif /* __STM32F1xx_IT_H */ 67 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Meysam Parvizi 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ########################################################################################################################## 2 | # File automatically-generated by tool: [projectgenerator] version: [4.1.0] date: [Thu Oct 05 16:01:13 GMT+03:30 2023] 3 | ########################################################################################################################## 4 | 5 | # ------------------------------------------------ 6 | # Generic Makefile (based on gcc) 7 | # 8 | # ChangeLog : 9 | # 2017-02-10 - Several enhancements + project update mode 10 | # 2015-07-22 - first version 11 | # ------------------------------------------------ 12 | 13 | ###################################### 14 | # target 15 | ###################################### 16 | TARGET = config 17 | 18 | 19 | ###################################### 20 | # building variables 21 | ###################################### 22 | # debug build? 23 | DEBUG = 1 24 | # optimization 25 | OPT = -Og 26 | 27 | 28 | ####################################### 29 | # paths 30 | ####################################### 31 | # Build path 32 | BUILD_DIR = build 33 | 34 | ###################################### 35 | # source 36 | ###################################### 37 | # C sources 38 | C_SOURCES = \ 39 | Src/main.c \ 40 | Src/stm32f1xx_it.c \ 41 | Src/stm32f1xx_hal_msp.c \ 42 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \ 43 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \ 44 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \ 45 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c \ 46 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \ 47 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \ 48 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \ 49 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \ 50 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \ 51 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \ 52 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \ 53 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \ 54 | Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \ 55 | Src/system_stm32f1xx.c 56 | 57 | # ASM sources 58 | ASM_SOURCES = \ 59 | startup_stm32f103xb.s 60 | 61 | 62 | ####################################### 63 | # binaries 64 | ####################################### 65 | PREFIX = arm-none-eabi- 66 | # The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) 67 | # either it can be added to the PATH environment variable. 68 | ifdef GCC_PATH 69 | CC = $(GCC_PATH)/$(PREFIX)gcc 70 | AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp 71 | CP = $(GCC_PATH)/$(PREFIX)objcopy 72 | SZ = $(GCC_PATH)/$(PREFIX)size 73 | else 74 | CC = $(PREFIX)gcc 75 | AS = $(PREFIX)gcc -x assembler-with-cpp 76 | CP = $(PREFIX)objcopy 77 | SZ = $(PREFIX)size 78 | endif 79 | HEX = $(CP) -O ihex 80 | BIN = $(CP) -O binary -S 81 | 82 | ####################################### 83 | # CFLAGS 84 | ####################################### 85 | # cpu 86 | CPU = -mcpu=cortex-m3 87 | 88 | # fpu 89 | # NONE for Cortex-M0/M0+/M3 90 | 91 | # float-abi 92 | 93 | 94 | # mcu 95 | MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) 96 | 97 | # macros for gcc 98 | # AS defines 99 | AS_DEFS = 100 | 101 | # C defines 102 | C_DEFS = \ 103 | -DUSE_HAL_DRIVER \ 104 | -DSTM32F103xB 105 | 106 | 107 | # AS includes 108 | AS_INCLUDES = 109 | 110 | # C includes 111 | C_INCLUDES = \ 112 | -IInc \ 113 | -IDrivers/STM32F1xx_HAL_Driver/Inc \ 114 | -IDrivers/STM32F1xx_HAL_Driver/Inc/Legacy \ 115 | -IDrivers/CMSIS/Device/ST/STM32F1xx/Include \ 116 | -IDrivers/CMSIS/Include 117 | 118 | 119 | # compile gcc flags 120 | ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 121 | 122 | CFLAGS += $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 123 | 124 | ifeq ($(DEBUG), 1) 125 | CFLAGS += -g -gdwarf-2 126 | endif 127 | 128 | 129 | # Generate dependency information 130 | CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" 131 | 132 | 133 | ####################################### 134 | # LDFLAGS 135 | ####################################### 136 | # link script 137 | LDSCRIPT = STM32F103C8Tx_FLASH.ld 138 | 139 | # libraries 140 | LIBS = -lc -lm -lnosys 141 | LIBDIR = 142 | LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections 143 | 144 | # default action: build all 145 | all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin 146 | 147 | 148 | ####################################### 149 | # build the application 150 | ####################################### 151 | # list of objects 152 | OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) 153 | vpath %.c $(sort $(dir $(C_SOURCES))) 154 | # list of ASM program objects 155 | OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) 156 | vpath %.s $(sort $(dir $(ASM_SOURCES))) 157 | 158 | $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 159 | $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ 160 | 161 | $(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) 162 | $(AS) -c $(CFLAGS) $< -o $@ 163 | 164 | $(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile 165 | $(CC) $(OBJECTS) $(LDFLAGS) -o $@ 166 | $(SZ) $@ 167 | 168 | $(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 169 | $(HEX) $< $@ 170 | 171 | $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 172 | $(BIN) $< $@ 173 | 174 | $(BUILD_DIR): 175 | mkdir $@ 176 | 177 | ####################################### 178 | # clean up 179 | ####################################### 180 | clean: 181 | -rm -fR $(BUILD_DIR) 182 | 183 | ####################################### 184 | # dependencies 185 | ####################################### 186 | -include $(wildcard $(BUILD_DIR)/*.d) 187 | 188 | 189 | ########### ADDED BY ME :) ############ 190 | 191 | flash: $(BUILD_DIR)/$(TARGET).bin 192 | st-flash write $(BUILD_DIR)/$(TARGET).bin 0x8000000 193 | 194 | erase: 195 | st-flash erase 196 | 197 | openocd-flash: $(BUILD_DIR)/$(TARGET).bin 198 | openocd -f interface/stlink.cfg -f board/stm32f103c8_blue_pill.cfg -c "init" -c "reset halt" -c "flash write_image erase $(BUILD_DIR)/$(TARGET).bin 0x08000000" -c "reset run" -c "exit" 199 | 200 | openocd-erase: 201 | openocd -f interface/stlink.cfg -f board/stm32f103c8_blue_pill.cfg -c "init" -c "reset halt" -c "flash erase_sector 0 0 last" -c "reset run" -c "exit" 202 | 203 | # *** EOF *** 204 | -------------------------------------------------------------------------------- /STM32F103C8Tx_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** Author : STM32CubeMX 8 | ** 9 | ** Abstract : Linker script for STM32F103C8Tx series 10 | ** 64Kbytes FLASH and 20Kbytes RAM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used. 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** Distribution: The file is distributed “as is,” without any warranty 20 | ** of any kind. 21 | ** 22 | ***************************************************************************** 23 | ** @attention 24 | ** 25 | **

© COPYRIGHT(c) 2019 STMicroelectronics

26 | ** 27 | ** Redistribution and use in source and binary forms, with or without modification, 28 | ** are permitted provided that the following conditions are met: 29 | ** 1. Redistributions of source code must retain the above copyright notice, 30 | ** this list of conditions and the following disclaimer. 31 | ** 2. Redistributions in binary form must reproduce the above copyright notice, 32 | ** this list of conditions and the following disclaimer in the documentation 33 | ** and/or other materials provided with the distribution. 34 | ** 3. Neither the name of STMicroelectronics nor the names of its contributors 35 | ** may be used to endorse or promote products derived from this software 36 | ** without specific prior written permission. 37 | ** 38 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 39 | ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 | ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 41 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 42 | ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 | ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 44 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 45 | ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 46 | ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | ** 49 | ***************************************************************************** 50 | */ 51 | 52 | /* Entry Point */ 53 | ENTRY(Reset_Handler) 54 | 55 | /* Highest address of the user mode stack */ 56 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ 57 | /* Generate a link error if heap and stack don't fit into RAM */ 58 | _Min_Heap_Size = 0x200; /* required amount of heap */ 59 | _Min_Stack_Size = 0x400; /* required amount of stack */ 60 | 61 | /* Specify the memory areas */ 62 | MEMORY 63 | { 64 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K 65 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K 66 | } 67 | 68 | /* Define output sections */ 69 | SECTIONS 70 | { 71 | /* The startup code goes first into FLASH */ 72 | .isr_vector : 73 | { 74 | . = ALIGN(4); 75 | KEEP(*(.isr_vector)) /* Startup code */ 76 | . = ALIGN(4); 77 | } >FLASH 78 | 79 | /* The program code and other data goes into FLASH */ 80 | .text : 81 | { 82 | . = ALIGN(4); 83 | *(.text) /* .text sections (code) */ 84 | *(.text*) /* .text* sections (code) */ 85 | *(.glue_7) /* glue arm to thumb code */ 86 | *(.glue_7t) /* glue thumb to arm code */ 87 | *(.eh_frame) 88 | 89 | KEEP (*(.init)) 90 | KEEP (*(.fini)) 91 | 92 | . = ALIGN(4); 93 | _etext = .; /* define a global symbols at end of code */ 94 | } >FLASH 95 | 96 | /* Constant data goes into FLASH */ 97 | .rodata : 98 | { 99 | . = ALIGN(4); 100 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 101 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 102 | . = ALIGN(4); 103 | } >FLASH 104 | 105 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH 106 | .ARM : { 107 | __exidx_start = .; 108 | *(.ARM.exidx*) 109 | __exidx_end = .; 110 | } >FLASH 111 | 112 | .preinit_array : 113 | { 114 | PROVIDE_HIDDEN (__preinit_array_start = .); 115 | KEEP (*(.preinit_array*)) 116 | PROVIDE_HIDDEN (__preinit_array_end = .); 117 | } >FLASH 118 | .init_array : 119 | { 120 | PROVIDE_HIDDEN (__init_array_start = .); 121 | KEEP (*(SORT(.init_array.*))) 122 | KEEP (*(.init_array*)) 123 | PROVIDE_HIDDEN (__init_array_end = .); 124 | } >FLASH 125 | .fini_array : 126 | { 127 | PROVIDE_HIDDEN (__fini_array_start = .); 128 | KEEP (*(SORT(.fini_array.*))) 129 | KEEP (*(.fini_array*)) 130 | PROVIDE_HIDDEN (__fini_array_end = .); 131 | } >FLASH 132 | 133 | /* used by the startup to initialize data */ 134 | _sidata = LOADADDR(.data); 135 | 136 | /* Initialized data sections goes into RAM, load LMA copy after code */ 137 | .data : 138 | { 139 | . = ALIGN(4); 140 | _sdata = .; /* create a global symbol at data start */ 141 | *(.data) /* .data sections */ 142 | *(.data*) /* .data* sections */ 143 | 144 | . = ALIGN(4); 145 | _edata = .; /* define a global symbol at data end */ 146 | } >RAM AT> FLASH 147 | 148 | 149 | /* Uninitialized data section */ 150 | . = ALIGN(4); 151 | .bss : 152 | { 153 | /* This is used by the startup in order to initialize the .bss secion */ 154 | _sbss = .; /* define a global symbol at bss start */ 155 | __bss_start__ = _sbss; 156 | *(.bss) 157 | *(.bss*) 158 | *(COMMON) 159 | 160 | . = ALIGN(4); 161 | _ebss = .; /* define a global symbol at bss end */ 162 | __bss_end__ = _ebss; 163 | } >RAM 164 | 165 | /* User_heap_stack section, used to check that there is enough RAM left */ 166 | ._user_heap_stack : 167 | { 168 | . = ALIGN(8); 169 | PROVIDE ( end = . ); 170 | PROVIDE ( _end = . ); 171 | . = . + _Min_Heap_Size; 172 | . = . + _Min_Stack_Size; 173 | . = ALIGN(8); 174 | } >RAM 175 | 176 | 177 | 178 | /* Remove information from the standard libraries */ 179 | /DISCARD/ : 180 | { 181 | libc.a ( * ) 182 | libm.a ( * ) 183 | libgcc.a ( * ) 184 | } 185 | 186 | .ARM.attributes 0 : { *(.ARM.attributes) } 187 | } 188 | 189 | 190 | -------------------------------------------------------------------------------- /Src/stm32f1xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_hal_msp.c 5 | * @brief This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2023 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | 24 | /* USER CODE BEGIN Includes */ 25 | 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | /** 62 | * Initializes the Global MSP. 63 | */ 64 | void HAL_MspInit(void) 65 | { 66 | /* USER CODE BEGIN MspInit 0 */ 67 | 68 | /* USER CODE END MspInit 0 */ 69 | 70 | __HAL_RCC_AFIO_CLK_ENABLE(); 71 | __HAL_RCC_PWR_CLK_ENABLE(); 72 | 73 | /* System interrupt init*/ 74 | 75 | /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 76 | */ 77 | __HAL_AFIO_REMAP_SWJ_NOJTAG(); 78 | 79 | /* USER CODE BEGIN MspInit 1 */ 80 | 81 | /* USER CODE END MspInit 1 */ 82 | } 83 | 84 | /* USER CODE BEGIN 1 */ 85 | 86 | /* USER CODE END 1 */ 87 | -------------------------------------------------------------------------------- /Src/stm32f1xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2023 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | #include "stm32f1xx_it.h" 23 | /* Private includes ----------------------------------------------------------*/ 24 | /* USER CODE BEGIN Includes */ 25 | /* USER CODE END Includes */ 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* USER CODE BEGIN TD */ 29 | 30 | /* USER CODE END TD */ 31 | 32 | /* Private define ------------------------------------------------------------*/ 33 | /* USER CODE BEGIN PD */ 34 | 35 | /* USER CODE END PD */ 36 | 37 | /* Private macro -------------------------------------------------------------*/ 38 | /* USER CODE BEGIN PM */ 39 | 40 | /* USER CODE END PM */ 41 | 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* USER CODE BEGIN PV */ 44 | 45 | /* USER CODE END PV */ 46 | 47 | /* Private function prototypes -----------------------------------------------*/ 48 | /* USER CODE BEGIN PFP */ 49 | 50 | /* USER CODE END PFP */ 51 | 52 | /* Private user code ---------------------------------------------------------*/ 53 | /* USER CODE BEGIN 0 */ 54 | 55 | /* USER CODE END 0 */ 56 | 57 | /* External variables --------------------------------------------------------*/ 58 | 59 | /* USER CODE BEGIN EV */ 60 | 61 | /* USER CODE END EV */ 62 | 63 | /******************************************************************************/ 64 | /* Cortex-M3 Processor Interruption and Exception Handlers */ 65 | /******************************************************************************/ 66 | /** 67 | * @brief This function handles Non maskable interrupt. 68 | */ 69 | void NMI_Handler(void) 70 | { 71 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 72 | 73 | /* USER CODE END NonMaskableInt_IRQn 0 */ 74 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 75 | while (1) 76 | { 77 | } 78 | /* USER CODE END NonMaskableInt_IRQn 1 */ 79 | } 80 | 81 | /** 82 | * @brief This function handles Hard fault interrupt. 83 | */ 84 | void HardFault_Handler(void) 85 | { 86 | /* USER CODE BEGIN HardFault_IRQn 0 */ 87 | 88 | /* USER CODE END HardFault_IRQn 0 */ 89 | while (1) 90 | { 91 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 92 | /* USER CODE END W1_HardFault_IRQn 0 */ 93 | } 94 | } 95 | 96 | /** 97 | * @brief This function handles Memory management fault. 98 | */ 99 | void MemManage_Handler(void) 100 | { 101 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 102 | 103 | /* USER CODE END MemoryManagement_IRQn 0 */ 104 | while (1) 105 | { 106 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 107 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 108 | } 109 | } 110 | 111 | /** 112 | * @brief This function handles Prefetch fault, memory access fault. 113 | */ 114 | void BusFault_Handler(void) 115 | { 116 | /* USER CODE BEGIN BusFault_IRQn 0 */ 117 | 118 | /* USER CODE END BusFault_IRQn 0 */ 119 | while (1) 120 | { 121 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 122 | /* USER CODE END W1_BusFault_IRQn 0 */ 123 | } 124 | } 125 | 126 | /** 127 | * @brief This function handles Undefined instruction or illegal state. 128 | */ 129 | void UsageFault_Handler(void) 130 | { 131 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 132 | 133 | /* USER CODE END UsageFault_IRQn 0 */ 134 | while (1) 135 | { 136 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 137 | /* USER CODE END W1_UsageFault_IRQn 0 */ 138 | } 139 | } 140 | 141 | /** 142 | * @brief This function handles System service call via SWI instruction. 143 | */ 144 | void SVC_Handler(void) 145 | { 146 | /* USER CODE BEGIN SVCall_IRQn 0 */ 147 | 148 | /* USER CODE END SVCall_IRQn 0 */ 149 | /* USER CODE BEGIN SVCall_IRQn 1 */ 150 | 151 | /* USER CODE END SVCall_IRQn 1 */ 152 | } 153 | 154 | /** 155 | * @brief This function handles Debug monitor. 156 | */ 157 | void DebugMon_Handler(void) 158 | { 159 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 160 | 161 | /* USER CODE END DebugMonitor_IRQn 0 */ 162 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 163 | 164 | /* USER CODE END DebugMonitor_IRQn 1 */ 165 | } 166 | 167 | /** 168 | * @brief This function handles Pendable request for system service. 169 | */ 170 | void PendSV_Handler(void) 171 | { 172 | /* USER CODE BEGIN PendSV_IRQn 0 */ 173 | 174 | /* USER CODE END PendSV_IRQn 0 */ 175 | /* USER CODE BEGIN PendSV_IRQn 1 */ 176 | 177 | /* USER CODE END PendSV_IRQn 1 */ 178 | } 179 | 180 | /** 181 | * @brief This function handles System tick timer. 182 | */ 183 | void SysTick_Handler(void) 184 | { 185 | /* USER CODE BEGIN SysTick_IRQn 0 */ 186 | 187 | /* USER CODE END SysTick_IRQn 0 */ 188 | HAL_IncTick(); 189 | /* USER CODE BEGIN SysTick_IRQn 1 */ 190 | 191 | /* USER CODE END SysTick_IRQn 1 */ 192 | } 193 | 194 | /******************************************************************************/ 195 | /* STM32F1xx Peripheral Interrupt Handlers */ 196 | /* Add here the Interrupt Handlers for the used peripherals. */ 197 | /* For the available peripheral interrupt handler names, */ 198 | /* please refer to the startup file (startup_stm32f1xx.s). */ 199 | /******************************************************************************/ 200 | 201 | /* USER CODE BEGIN 1 */ 202 | 203 | /* USER CODE END 1 */ 204 | -------------------------------------------------------------------------------- /config.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | CAD.formats=[] 3 | CAD.pinconfig=Dual 4 | CAD.provider= 5 | File.Version=6 6 | GPIO.groupedBy=Group By Peripherals 7 | KeepUserPlacement=false 8 | Mcu.CPN=STM32F103C8T6 9 | Mcu.Family=STM32F1 10 | Mcu.IP0=NVIC 11 | Mcu.IP1=RCC 12 | Mcu.IP2=SYS 13 | Mcu.IPNb=3 14 | Mcu.Name=STM32F103C(8-B)Tx 15 | Mcu.Package=LQFP48 16 | Mcu.Pin0=PC14-OSC32_IN 17 | Mcu.Pin1=PD0-OSC_IN 18 | Mcu.Pin2=PD1-OSC_OUT 19 | Mcu.Pin3=PA13 20 | Mcu.Pin4=PA14 21 | Mcu.Pin5=VP_SYS_VS_Systick 22 | Mcu.PinsNb=6 23 | Mcu.ThirdPartyNb=0 24 | Mcu.UserConstants= 25 | Mcu.UserName=STM32F103C8Tx 26 | MxCube.Version=6.9.2 27 | MxDb.Version=DB.6.0.92 28 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 29 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 30 | NVIC.ForceEnableDMAVector=true 31 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 32 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 33 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 34 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 35 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 36 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 37 | NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false 38 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false 39 | PA13.Mode=Serial_Wire 40 | PA13.Signal=SYS_JTMS-SWDIO 41 | PA14.Mode=Serial_Wire 42 | PA14.Signal=SYS_JTCK-SWCLK 43 | PC14-OSC32_IN.GPIOParameters=GPIO_Speed 44 | PC14-OSC32_IN.GPIO_Speed=GPIO_SPEED_FREQ_HIGH 45 | PC14-OSC32_IN.Locked=true 46 | PC14-OSC32_IN.Signal=EVENTOUT 47 | PD0-OSC_IN.Mode=HSE-External-Oscillator 48 | PD0-OSC_IN.Signal=RCC_OSC_IN 49 | PD1-OSC_OUT.Mode=HSE-External-Oscillator 50 | PD1-OSC_OUT.Signal=RCC_OSC_OUT 51 | PinOutPanel.RotationAngle=0 52 | ProjectManager.AskForMigrate=true 53 | ProjectManager.BackupPrevious=false 54 | ProjectManager.CompilerOptimize=6 55 | ProjectManager.ComputerToolchain=false 56 | ProjectManager.CoupleFile=false 57 | ProjectManager.CustomerFirmwarePackage= 58 | ProjectManager.DefaultFWLocation=true 59 | ProjectManager.DeletePrevious=true 60 | ProjectManager.DeviceId=STM32F103C8Tx 61 | ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.5 62 | ProjectManager.FreePins=false 63 | ProjectManager.HalAssertFull=false 64 | ProjectManager.HeapSize=0x200 65 | ProjectManager.KeepUserCode=true 66 | ProjectManager.LastFirmware=false 67 | ProjectManager.LibraryCopy=1 68 | ProjectManager.MainLocation=Src 69 | ProjectManager.NoMain=false 70 | ProjectManager.PreviousToolchain= 71 | ProjectManager.ProjectBuild=false 72 | ProjectManager.ProjectFileName=config.ioc 73 | ProjectManager.ProjectName=config 74 | ProjectManager.ProjectStructure= 75 | ProjectManager.RegisterCallBack= 76 | ProjectManager.StackSize=0x400 77 | ProjectManager.TargetToolchain=Makefile 78 | ProjectManager.ToolChainLocation= 79 | ProjectManager.UAScriptAfterPath= 80 | ProjectManager.UAScriptBeforePath= 81 | ProjectManager.UnderRoot=false 82 | ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true 83 | RCC.ADCFreqValue=72000000 84 | RCC.AHBFreq_Value=144000000 85 | RCC.APB1Freq_Value=144000000 86 | RCC.APB1TimFreq_Value=144000000 87 | RCC.APB2Freq_Value=144000000 88 | RCC.APB2TimFreq_Value=144000000 89 | RCC.FCLKCortexFreq_Value=144000000 90 | RCC.FamilyName=M 91 | RCC.HCLKFreq_Value=144000000 92 | RCC.HSE_VALUE=16000000 93 | RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RCC_MCOSource,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value 94 | RCC.MCOFreq_Value=72000000 95 | RCC.PLLCLKFreq_Value=144000000 96 | RCC.PLLMCOFreq_Value=72000000 97 | RCC.PLLMUL=RCC_PLL_MUL9 98 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE 99 | RCC.RCC_MCOSource=RCC_MCO1SOURCE_PLLCLK 100 | RCC.SYSCLKFreq_VALUE=144000000 101 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 102 | RCC.TimSysFreq_Value=144000000 103 | RCC.USBFreq_Value=144000000 104 | RCC.VCOOutput2Freq_Value=16000000 105 | VP_SYS_VS_Systick.Mode=SysTick 106 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 107 | board=custom 108 | -------------------------------------------------------------------------------- /startup_stm32f103xb.s: -------------------------------------------------------------------------------- 1 | /** 2 | *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ 3 | * @file startup_stm32f103xb.s 4 | * @author MCD Application Team 5 | * @brief STM32F103xB Devices vector table for Atollic toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Configure the clock system 11 | * - Branches to main in the C library (which eventually 12 | * calls main()). 13 | * After Reset the Cortex-M3 processor is in Thread mode, 14 | * priority is Privileged, and the Stack is set to Main. 15 | ****************************************************************************** 16 | * @attention 17 | * 18 | *

© Copyright (c) 2017 STMicroelectronics. 19 | * All rights reserved.

20 | * 21 | * This software component is licensed by ST under BSD 3-Clause license, 22 | * the "License"; You may not use this file except in compliance with the 23 | * License. You may obtain a copy of the License at: 24 | * opensource.org/licenses/BSD-3-Clause 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | .syntax unified 30 | .cpu cortex-m3 31 | .fpu softvfp 32 | .thumb 33 | 34 | .global g_pfnVectors 35 | .global Default_Handler 36 | 37 | /* start address for the initialization values of the .data section. 38 | defined in linker script */ 39 | .word _sidata 40 | /* start address for the .data section. defined in linker script */ 41 | .word _sdata 42 | /* end address for the .data section. defined in linker script */ 43 | .word _edata 44 | /* start address for the .bss section. defined in linker script */ 45 | .word _sbss 46 | /* end address for the .bss section. defined in linker script */ 47 | .word _ebss 48 | 49 | .equ BootRAM, 0xF108F85F 50 | /** 51 | * @brief This is the code that gets called when the processor first 52 | * starts execution following a reset event. Only the absolutely 53 | * necessary set is performed, after which the application 54 | * supplied main() routine is called. 55 | * @param None 56 | * @retval : None 57 | */ 58 | 59 | .section .text.Reset_Handler 60 | .weak Reset_Handler 61 | .type Reset_Handler, %function 62 | Reset_Handler: 63 | 64 | /* Copy the data segment initializers from flash to SRAM */ 65 | ldr r0, =_sdata 66 | ldr r1, =_edata 67 | ldr r2, =_sidata 68 | movs r3, #0 69 | b LoopCopyDataInit 70 | 71 | CopyDataInit: 72 | ldr r4, [r2, r3] 73 | str r4, [r0, r3] 74 | adds r3, r3, #4 75 | 76 | LoopCopyDataInit: 77 | adds r4, r0, r3 78 | cmp r4, r1 79 | bcc CopyDataInit 80 | 81 | /* Zero fill the bss segment. */ 82 | ldr r2, =_sbss 83 | ldr r4, =_ebss 84 | movs r3, #0 85 | b LoopFillZerobss 86 | 87 | FillZerobss: 88 | str r3, [r2] 89 | adds r2, r2, #4 90 | 91 | LoopFillZerobss: 92 | cmp r2, r4 93 | bcc FillZerobss 94 | 95 | /* Call the clock system intitialization function.*/ 96 | bl SystemInit 97 | /* Call static constructors */ 98 | bl __libc_init_array 99 | /* Call the application's entry point.*/ 100 | bl main 101 | bx lr 102 | .size Reset_Handler, .-Reset_Handler 103 | 104 | /** 105 | * @brief This is the code that gets called when the processor receives an 106 | * unexpected interrupt. This simply enters an infinite loop, preserving 107 | * the system state for examination by a debugger. 108 | * 109 | * @param None 110 | * @retval : None 111 | */ 112 | .section .text.Default_Handler,"ax",%progbits 113 | Default_Handler: 114 | Infinite_Loop: 115 | b Infinite_Loop 116 | .size Default_Handler, .-Default_Handler 117 | /****************************************************************************** 118 | * 119 | * The minimal vector table for a Cortex M3. Note that the proper constructs 120 | * must be placed on this to ensure that it ends up at physical address 121 | * 0x0000.0000. 122 | * 123 | ******************************************************************************/ 124 | .section .isr_vector,"a",%progbits 125 | .type g_pfnVectors, %object 126 | .size g_pfnVectors, .-g_pfnVectors 127 | 128 | 129 | g_pfnVectors: 130 | 131 | .word _estack 132 | .word Reset_Handler 133 | .word NMI_Handler 134 | .word HardFault_Handler 135 | .word MemManage_Handler 136 | .word BusFault_Handler 137 | .word UsageFault_Handler 138 | .word 0 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word SVC_Handler 143 | .word DebugMon_Handler 144 | .word 0 145 | .word PendSV_Handler 146 | .word SysTick_Handler 147 | .word WWDG_IRQHandler 148 | .word PVD_IRQHandler 149 | .word TAMPER_IRQHandler 150 | .word RTC_IRQHandler 151 | .word FLASH_IRQHandler 152 | .word RCC_IRQHandler 153 | .word EXTI0_IRQHandler 154 | .word EXTI1_IRQHandler 155 | .word EXTI2_IRQHandler 156 | .word EXTI3_IRQHandler 157 | .word EXTI4_IRQHandler 158 | .word DMA1_Channel1_IRQHandler 159 | .word DMA1_Channel2_IRQHandler 160 | .word DMA1_Channel3_IRQHandler 161 | .word DMA1_Channel4_IRQHandler 162 | .word DMA1_Channel5_IRQHandler 163 | .word DMA1_Channel6_IRQHandler 164 | .word DMA1_Channel7_IRQHandler 165 | .word ADC1_2_IRQHandler 166 | .word USB_HP_CAN1_TX_IRQHandler 167 | .word USB_LP_CAN1_RX0_IRQHandler 168 | .word CAN1_RX1_IRQHandler 169 | .word CAN1_SCE_IRQHandler 170 | .word EXTI9_5_IRQHandler 171 | .word TIM1_BRK_IRQHandler 172 | .word TIM1_UP_IRQHandler 173 | .word TIM1_TRG_COM_IRQHandler 174 | .word TIM1_CC_IRQHandler 175 | .word TIM2_IRQHandler 176 | .word TIM3_IRQHandler 177 | .word TIM4_IRQHandler 178 | .word I2C1_EV_IRQHandler 179 | .word I2C1_ER_IRQHandler 180 | .word I2C2_EV_IRQHandler 181 | .word I2C2_ER_IRQHandler 182 | .word SPI1_IRQHandler 183 | .word SPI2_IRQHandler 184 | .word USART1_IRQHandler 185 | .word USART2_IRQHandler 186 | .word USART3_IRQHandler 187 | .word EXTI15_10_IRQHandler 188 | .word RTC_Alarm_IRQHandler 189 | .word USBWakeUp_IRQHandler 190 | .word 0 191 | .word 0 192 | .word 0 193 | .word 0 194 | .word 0 195 | .word 0 196 | .word 0 197 | .word BootRAM /* @0x108. This is for boot in RAM mode for 198 | STM32F10x Medium Density devices. */ 199 | 200 | /******************************************************************************* 201 | * 202 | * Provide weak aliases for each Exception handler to the Default_Handler. 203 | * As they are weak aliases, any function with the same name will override 204 | * this definition. 205 | * 206 | *******************************************************************************/ 207 | 208 | .weak NMI_Handler 209 | .thumb_set NMI_Handler,Default_Handler 210 | 211 | .weak HardFault_Handler 212 | .thumb_set HardFault_Handler,Default_Handler 213 | 214 | .weak MemManage_Handler 215 | .thumb_set MemManage_Handler,Default_Handler 216 | 217 | .weak BusFault_Handler 218 | .thumb_set BusFault_Handler,Default_Handler 219 | 220 | .weak UsageFault_Handler 221 | .thumb_set UsageFault_Handler,Default_Handler 222 | 223 | .weak SVC_Handler 224 | .thumb_set SVC_Handler,Default_Handler 225 | 226 | .weak DebugMon_Handler 227 | .thumb_set DebugMon_Handler,Default_Handler 228 | 229 | .weak PendSV_Handler 230 | .thumb_set PendSV_Handler,Default_Handler 231 | 232 | .weak SysTick_Handler 233 | .thumb_set SysTick_Handler,Default_Handler 234 | 235 | .weak WWDG_IRQHandler 236 | .thumb_set WWDG_IRQHandler,Default_Handler 237 | 238 | .weak PVD_IRQHandler 239 | .thumb_set PVD_IRQHandler,Default_Handler 240 | 241 | .weak TAMPER_IRQHandler 242 | .thumb_set TAMPER_IRQHandler,Default_Handler 243 | 244 | .weak RTC_IRQHandler 245 | .thumb_set RTC_IRQHandler,Default_Handler 246 | 247 | .weak FLASH_IRQHandler 248 | .thumb_set FLASH_IRQHandler,Default_Handler 249 | 250 | .weak RCC_IRQHandler 251 | .thumb_set RCC_IRQHandler,Default_Handler 252 | 253 | .weak EXTI0_IRQHandler 254 | .thumb_set EXTI0_IRQHandler,Default_Handler 255 | 256 | .weak EXTI1_IRQHandler 257 | .thumb_set EXTI1_IRQHandler,Default_Handler 258 | 259 | .weak EXTI2_IRQHandler 260 | .thumb_set EXTI2_IRQHandler,Default_Handler 261 | 262 | .weak EXTI3_IRQHandler 263 | .thumb_set EXTI3_IRQHandler,Default_Handler 264 | 265 | .weak EXTI4_IRQHandler 266 | .thumb_set EXTI4_IRQHandler,Default_Handler 267 | 268 | .weak DMA1_Channel1_IRQHandler 269 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 270 | 271 | .weak DMA1_Channel2_IRQHandler 272 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 273 | 274 | .weak DMA1_Channel3_IRQHandler 275 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 276 | 277 | .weak DMA1_Channel4_IRQHandler 278 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 279 | 280 | .weak DMA1_Channel5_IRQHandler 281 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 282 | 283 | .weak DMA1_Channel6_IRQHandler 284 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 285 | 286 | .weak DMA1_Channel7_IRQHandler 287 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 288 | 289 | .weak ADC1_2_IRQHandler 290 | .thumb_set ADC1_2_IRQHandler,Default_Handler 291 | 292 | .weak USB_HP_CAN1_TX_IRQHandler 293 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 294 | 295 | .weak USB_LP_CAN1_RX0_IRQHandler 296 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 297 | 298 | .weak CAN1_RX1_IRQHandler 299 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 300 | 301 | .weak CAN1_SCE_IRQHandler 302 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 303 | 304 | .weak EXTI9_5_IRQHandler 305 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 306 | 307 | .weak TIM1_BRK_IRQHandler 308 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 309 | 310 | .weak TIM1_UP_IRQHandler 311 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 312 | 313 | .weak TIM1_TRG_COM_IRQHandler 314 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 315 | 316 | .weak TIM1_CC_IRQHandler 317 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 318 | 319 | .weak TIM2_IRQHandler 320 | .thumb_set TIM2_IRQHandler,Default_Handler 321 | 322 | .weak TIM3_IRQHandler 323 | .thumb_set TIM3_IRQHandler,Default_Handler 324 | 325 | .weak TIM4_IRQHandler 326 | .thumb_set TIM4_IRQHandler,Default_Handler 327 | 328 | .weak I2C1_EV_IRQHandler 329 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 330 | 331 | .weak I2C1_ER_IRQHandler 332 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 333 | 334 | .weak I2C2_EV_IRQHandler 335 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 336 | 337 | .weak I2C2_ER_IRQHandler 338 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 339 | 340 | .weak SPI1_IRQHandler 341 | .thumb_set SPI1_IRQHandler,Default_Handler 342 | 343 | .weak SPI2_IRQHandler 344 | .thumb_set SPI2_IRQHandler,Default_Handler 345 | 346 | .weak USART1_IRQHandler 347 | .thumb_set USART1_IRQHandler,Default_Handler 348 | 349 | .weak USART2_IRQHandler 350 | .thumb_set USART2_IRQHandler,Default_Handler 351 | 352 | .weak USART3_IRQHandler 353 | .thumb_set USART3_IRQHandler,Default_Handler 354 | 355 | .weak EXTI15_10_IRQHandler 356 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 357 | 358 | .weak RTC_Alarm_IRQHandler 359 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler 360 | 361 | .weak USBWakeUp_IRQHandler 362 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 363 | 364 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 365 | 366 | --------------------------------------------------------------------------------