├── .gitignore ├── DEV_LOG.md ├── HW ├── Quartus-Qsys-Ip-search-path_linux-location.md ├── QuartusProjects │ ├── .gitignore │ ├── Common │ │ ├── I2C_Controller.v │ │ ├── I2C_HDMI_Config.v │ │ ├── I2C_WRITE_WDATA.v │ │ ├── adc_ltc2308.v │ │ ├── adc_ltc2308_fifo.sv │ │ ├── bidir_io.sv │ │ ├── capsense.sv │ │ ├── firmware_id.vhd │ │ ├── gpio_adr_decoder_reg.sv │ │ ├── hdmi_config.qip │ │ ├── led_blinker.sv │ │ ├── top_io_modules.sv │ │ └── top_modules.qip │ ├── DE0_Nano_SoC_Cramps │ │ ├── .gitignore │ │ ├── DE0_Nano_SoC_Cramps.ipx │ │ ├── DE0_Nano_SoC_Cramps.qpf │ │ ├── DE0_Nano_SoC_Cramps.qsf │ │ ├── DE0_Nano_SoC_Cramps.sdc │ │ ├── DE0_Nano_SoC_Cramps.sv │ │ ├── Makefile │ │ ├── build.sh │ │ ├── generate_hps_qsys_header.sh │ │ ├── hps_common_board_info.xml │ │ ├── soc_system.qsys │ │ └── soc_system_board_info.xml │ ├── DE0_Nano_SoC_DB25 │ │ ├── .gitignore │ │ ├── DE0_Nano_DB25_board_info.xml │ │ ├── DE0_Nano_SoC_DB25.ipx │ │ ├── DE0_Nano_SoC_DB25.qpf │ │ ├── DE0_Nano_SoC_DB25.qsf │ │ ├── DE0_Nano_SoC_DB25.vhd │ │ ├── Makefile │ │ ├── build.sh │ │ ├── generate_hps_qsys_header.sh │ │ ├── hostmot2_cfg.vhd.in │ │ ├── hps_common_board_info.xml │ │ ├── soc_system.qsys │ │ └── soc_system_pkg.vhd │ ├── DE10_Nano_Commands.md │ ├── DE10_Nano_FB_Cramps │ │ ├── .gitignore │ │ ├── DE10_Nano_FB_Cramps.ipx │ │ ├── DE10_Nano_FB_Cramps.out.sdc │ │ ├── DE10_Nano_FB_Cramps.qpf │ │ ├── DE10_Nano_FB_Cramps.qsf │ │ ├── DE10_Nano_FB_Cramps.sdc │ │ ├── DE10_Nano_FB_Cramps.sv │ │ ├── Makefile │ │ ├── audio_pll.xml │ │ ├── build.sh │ │ ├── hps_common_board_info.xml │ │ ├── soc_system.ipx │ │ ├── soc_system.qsys │ │ ├── soc_system_board_info.xml │ │ └── sys_pll.xml │ ├── DE10_Nano_SoC_FB_DB25 │ │ ├── DE10_Nano_SoC_FB_DB25.qpf │ │ ├── DE10_Nano_SoC_FB_DB25.qsf │ │ ├── DE10_Nano_SoC_FB_DB25.sdc │ │ ├── DE10_Nano_SoC_FB_DB25.vhd │ │ ├── Makefile │ │ ├── README.md │ │ ├── build.sh │ │ ├── generate_hps_qsys_header.sh │ │ ├── hostmot2_cfg.vhd.in │ │ ├── hps_common_board_info.xml │ │ ├── soc_system.ipx │ │ ├── soc_system.qsys │ │ ├── soc_system_board_info.xml │ │ └── soc_system_pkg.vhd │ └── DE1_SOC_GHRD │ │ ├── Makefile │ │ ├── generate_hps_qsys_header.sh │ │ ├── ghrd.sv │ │ ├── hps_clock_info.xml │ │ ├── hps_common_board_info.xml │ │ ├── soc_system.ipx │ │ ├── soc_system.jdi │ │ ├── soc_system.qpf │ │ ├── soc_system.qsf │ │ ├── soc_system.qsys │ │ ├── soc_system_board_info.xml │ │ └── soc_system_timing.sdc ├── README.BuildSystem.txt ├── README.machinetalk-protobuf ├── README.md ├── VivadoProjects │ ├── .gitignore │ ├── Readme.md │ ├── avnet │ │ └── ultra96 │ │ │ ├── const │ │ │ ├── PIN_ULTR_36.vhd │ │ │ └── ultra96_pinmap.xdc │ │ │ ├── scripts │ │ │ ├── soc_system-v2.tcl │ │ │ └── soc_system.tcl │ │ │ ├── ultra96v1-mk-2019.1.bsp │ │ │ ├── ultra96v1_config │ │ │ ├── ultra96v2-mk-2019.1.bsp │ │ │ └── ultra96v2_config │ ├── bif │ │ └── all.bif.in │ ├── make_bitfile.sh │ ├── make_mpsoc_boot.sh │ ├── microzed │ │ └── microzed_jd2cb │ │ │ ├── 7z010_config │ │ │ ├── 7z020_config │ │ │ ├── const │ │ │ ├── PIN_MJD2CB_32.vhd │ │ │ └── microzed_jd2cb_pinmap.xdc │ │ │ ├── dts │ │ │ └── microzed_jd2cb_ol.dts.in │ │ │ ├── ip │ │ │ ├── hm2_ip_wrap_jd2 │ │ │ │ ├── component.xml │ │ │ │ ├── src │ │ │ │ │ ├── hostmot2.vhd │ │ │ │ │ ├── hostmot2_ip_wrap.vhd │ │ │ │ │ ├── inp_deb.vhd │ │ │ │ │ ├── jdcb_io.vhd │ │ │ │ │ ├── reduction_pkg.vhd │ │ │ │ │ └── sig_delay.vhd │ │ │ │ └── xgui │ │ │ │ │ └── HostMot2_ip_wrap_jd2_v1_0.tcl │ │ │ └── jd2_mad_logic │ │ │ │ ├── component.xml │ │ │ │ ├── jd2.com_user_jd2_mad_logic_1.zip │ │ │ │ ├── src │ │ │ │ ├── inp_deb.vhd │ │ │ │ ├── jdcb_ins.vhd │ │ │ │ ├── reduction_pkg.vhd │ │ │ │ └── sig_delay.vhd │ │ │ │ └── xgui │ │ │ │ └── jd2_mad_logic_v1.tcl │ │ │ └── scripts │ │ │ └── mzed_jd2cb_bd.tcl │ ├── myirtech │ │ ├── fz3 │ │ │ ├── const │ │ │ │ ├── PIN_FZ3_36.vhd │ │ │ │ └── fz3_pinmap.xdc │ │ │ ├── fz3-mk-2019.1.bsp │ │ │ ├── fz3_config │ │ │ └── scripts │ │ │ │ └── soc_system.tcl │ │ └── ultramyir │ │ │ ├── const │ │ │ ├── PIN_ULTRAMYIR_36.vhd │ │ │ └── ultramyir_pinmap.xdc │ │ │ ├── scripts │ │ │ └── soc_system.tcl │ │ │ ├── ultramyir-mk-2019.1.bsp │ │ │ ├── ultramyir_config │ │ │ └── ultramyir_xczu3eg.tcl │ ├── ultra96.tcl │ ├── xilinx │ │ └── kr260 │ │ │ ├── README.md │ │ │ ├── const │ │ │ ├── PIN_KR260_36.vhd │ │ │ ├── kr260_pinmap.xdc │ │ │ └── soc_system.tcl │ │ │ ├── dts │ │ │ └── kria_kr260_ol.dts.in │ │ │ ├── kr260_config │ │ │ └── scripts │ │ │ └── soc_system.tcl │ ├── zturn │ │ ├── zturn_jd2cb │ │ │ ├── 7z010_config │ │ │ ├── 7z020_config │ │ │ ├── const │ │ │ │ ├── PIN_ZJD2CB_36.vhd │ │ │ │ └── zturn_jd2cb_pinmap.xdc │ │ │ ├── dts │ │ │ │ └── zturn_jd2cb_ol.dts.in │ │ │ ├── ip │ │ │ │ └── jd2_mad_logic │ │ │ │ │ ├── component.xml │ │ │ │ │ ├── src │ │ │ │ │ ├── inp_deb.vhd │ │ │ │ │ ├── jdcb_ins.vhd │ │ │ │ │ ├── reduction_pkg.vhd │ │ │ │ │ └── sig_delay.vhd │ │ │ │ │ └── xgui │ │ │ │ │ └── jd2_mad_logic_v1.tcl │ │ │ └── scripts │ │ │ │ └── zturn_jd2cb_bd.tcl │ │ └── zturn_ztio │ │ │ ├── 7z010_config │ │ │ ├── 7z020_config │ │ │ ├── const │ │ │ ├── PIN_ZTIO_34.vhd │ │ │ └── zturn_ztio_pinmap.xdc │ │ │ ├── dts │ │ │ └── zturn_ztio_ol.dts.in │ │ │ └── scripts │ │ │ └── zturn_ztio_bd.tcl │ ├── zynq_bp.tcl.in │ └── zynqmp_bp.tcl.in ├── cv-ip │ ├── ADC_LTC2308_FIFO │ │ ├── README.md │ │ ├── adc1stp1-set-counter.jpg │ │ ├── adc_data_fifo.qip │ │ ├── adc_data_fifo.v │ │ ├── adc_ltc2308.v │ │ ├── adc_ltc2308_fifo.v │ │ ├── adc_ltc2308_hw.tcl │ │ └── greybox_tmp │ │ │ └── cbx_args.txt │ ├── altsource_probe │ │ ├── hps_reset.qip │ │ ├── hps_reset.v │ │ └── hps_reset_bb.v │ ├── axi_reg │ │ ├── AXI_Reg_Rd.vhd │ │ ├── AXI_Reg_Wr.vhd │ │ ├── Reg_Pkg.vhd │ │ └── axi_conduit.vhd │ ├── cv_ip_pkg.vhd │ ├── debounce │ │ └── debounce.v │ ├── edge_detect │ │ └── altera_edge_detector.v │ ├── hm2reg_io │ │ ├── hm2reg_io.v │ │ ├── hm2reg_io_hw.tcl │ │ └── machinekiticon.png │ ├── intr_capturer │ │ ├── intr_capturer.v │ │ └── intr_capturer_hw.tcl │ └── presets │ │ ├── 1366x769-HDMI.qprs │ │ ├── 15-inch-touch-lvds.qprs │ │ ├── 15-inch_touch-lvds.qprs │ │ ├── B156XTT01.qprs │ │ ├── HDMI_1024x768.qprs │ │ ├── HDMI_15-i-lvds-1366x768.qprs │ │ ├── LP101WX1.qprs │ │ ├── VESA_1368x768@60.qprs │ │ ├── de1_soc-fb.qprs │ │ ├── de1_soc_fb.qprs │ │ └── vga1024x768.qprs ├── cv-megawizard │ ├── SRL16E.vhd │ ├── lpm-ip │ │ ├── lpm_mux16.cmp │ │ ├── lpm_mux16.qip │ │ ├── lpm_mux16.vhd │ │ ├── lpm_mux16_inst.vhd │ │ ├── lpm_shiftreg16.cmp │ │ ├── lpm_shiftreg16.qip │ │ ├── lpm_shiftreg16.vhd │ │ └── lpm_shiftreg16_inst.vhd │ └── lpm_pack.vhd ├── firmware-tag │ ├── .gitignore │ ├── DE0_Nano_SoC_Cramps.py │ ├── DE0_Nano_SoC_DB25.py │ ├── DE10_Nano_FB_Cramps.py │ ├── DE10_Nano_SoC_FB_DB25.py │ ├── FWID_FZ3_36.py │ ├── FWID_KR260_36.py │ ├── FWID_MJD2CB_32.py │ ├── FWID_ULTRA96_36.py │ ├── FWID_ULTRAMYIR_36.py │ ├── FWID_ZJD2CB_36.py │ ├── FWID_ZTIO_34.py │ ├── Makefile │ ├── genfwid.py │ ├── mif.py │ ├── output.txt │ └── util.py ├── hm2 │ ├── .gitignore │ ├── OutputInteg.vhd │ ├── adpram.vhd │ ├── b32qcondmac.vhd │ ├── b32qcondmac2w.vhd │ ├── binosc.vhd │ ├── biss.vhd │ ├── biss_loop.vhd │ ├── boutreg.vhd │ ├── bufferedspi.vhd │ ├── config │ │ ├── DE0_Nano_SoC_DB25 │ │ │ ├── DE0_Nano_SoC_DB25_card.vhd │ │ │ ├── PIN_4s6p1q_GPIO_GPIO_GPIO.vhd │ │ │ ├── PIN_7I76_7I76_7I76_7I76.vhd │ │ │ ├── PIN_7I76_7I85S_GPIO_GPIO.vhd │ │ │ ├── PIN_7I77_7I76_GPIO_GPIO.vhd │ │ │ ├── PIN_A_Volkov.vhd │ │ │ ├── PIN_G540_G540_GPIO_GPIO.vhd │ │ │ └── hm2_DE0_Nano_SoC_DB25.qip │ │ ├── DExx_Nano_xxx_Cramps │ │ │ ├── PIN_3x24.vhd │ │ │ ├── PIN_3x24_cap.vhd │ │ │ ├── PIN_3x24_cap_enc.vhd │ │ │ ├── PIN_3x24_cap_enc_bspi.vhd │ │ │ ├── PIN_3x24_cap_enc_dbspi.vhd │ │ │ ├── PIN_st_fpga_soc_dc1G.vhd │ │ │ ├── PIN_st_fpga_soc_dc1f_ss.vhd │ │ │ ├── atlas_3x24.sv │ │ │ ├── atlas_3x24_cap.sv │ │ │ ├── atlas_3x24_cap_enc.sv │ │ │ ├── atlas_3x24_cap_enc_bspi.sv │ │ │ ├── atlas_3x24_cap_enc_dbspi.sv │ │ │ ├── atlas_st_fpga_soc_dc1G.sv │ │ │ ├── atlas_st_fpga_soc_dc1f_ss.sv │ │ │ ├── hm3_DExx_Nano_xxx_Cramps.in │ │ │ ├── hm3_pin_config.in │ │ │ ├── hostmot3_cfg.vhd │ │ │ └── readme.md │ │ ├── IDROMConst.vhd │ │ ├── PIN_7I74x2_34.vhd │ │ ├── PIN_7I76_7I76_7I76_7I76_no_irq.vhd │ │ ├── PIN_DRINGx2_34.vhd │ │ ├── PIN_G540x2_34.vhd │ │ ├── PIN_G540x2_34_irq.vhd │ │ ├── PIN_SV8NA.vhd │ │ ├── hm2_i25_G540x2_34_config.qip │ │ ├── hm2_i25_G540x2_34_irq_config.qip │ │ ├── i25_x9card.vhd │ │ └── i25_x9u_card.vhd │ ├── d8o8.vhd │ ├── d8o8sqw.vhd │ ├── d8o8sqws.vhd │ ├── daqfifo16.vhd │ ├── dpram.vhd │ ├── drqlogic.vhd │ ├── fanucabs.vhd │ ├── functions │ │ ├── CountPinsInRange.vhd │ │ ├── InputPinsPerModule.vhd │ │ ├── MaxIOPinsPerModule.vhd │ │ ├── MaxInputPinsPerModule.vhd │ │ ├── MaxOutputPinsPerModule.vhd │ │ ├── MaxPinsPerModule.vhd │ │ ├── ModuleExists.vhd │ │ ├── NumberOfModules.vhd │ │ ├── PinExists.vhd │ │ ├── decodedstrobe.vhd │ │ ├── decodedstrobe2.vhd │ │ ├── hm2_functions.qip │ │ ├── log2.vhd │ │ └── oneofndecode.vhd │ ├── hm2_socfpga.qip │ ├── hm3_socfpga.qip │ ├── hmtimers.vhd │ ├── hostmot2.vhd │ ├── hostmot3.vhd │ ├── hostmotid.vhd │ ├── idrom.vhd │ ├── idrom_tools.vhd │ ├── irqlogic.vhd │ ├── irqlogics.vhd │ ├── irqlogics_periodic.vhd │ ├── kubstepgenz.vhd │ ├── kubstepgenzi.vhd │ ├── pktuartr.vhd │ ├── pktuartx.vhd │ ├── pwmpdmgenh.vhd │ ├── pwmrefh.vhd │ ├── qcounterate.vhd │ ├── qcounteratesk.vhd │ ├── qcountersf.vhd │ ├── qcountersfp.vhd │ ├── resolver.vhd │ ├── resolverdaq2.vhd │ ├── resrom.vhd │ ├── resroms.vhd │ ├── scalercounter.vhd │ ├── scalertimer.vhd │ ├── serialhm2.vhd │ ├── simplespix.vhd │ ├── simplessi.vhd │ ├── sine16.vhd │ ├── srl16delay.vhd │ ├── sserialwa.vhd │ ├── sslbpram.vhd │ ├── sslbprom.vhd │ ├── syncwavegen.vhd │ ├── threephasepwm.vhd │ ├── timestamp.vhd │ ├── twiddle.vhd │ ├── twidrom.vhd │ ├── uartr.vhd │ ├── uartr8.vhd │ ├── uartx.vhd │ ├── uartx8.vhd │ ├── ubrategen.vhd │ ├── watchdog.vhd │ ├── wavegen.vhd │ ├── waveram.vhd │ ├── wordpr.vhd │ ├── wordrb.vhd │ └── wrappers │ │ ├── MakeBSPIs.vhd │ │ ├── MakeDBSPIs.vhd │ │ ├── MakeHm2Dpllmods.vhd │ │ ├── MakeIOPorts.vhd │ │ ├── MakeMuxedQCounters.vhd │ │ ├── MakePwmgens.vhd │ │ ├── MakeQCounters.vhd │ │ ├── MakeSPIs.vhd │ │ ├── MakeSSIs.vhd │ │ ├── MakeSSerials.vhd │ │ ├── MakeStepgens.vhd │ │ └── MakeTPPWMGens.vhd ├── machinetalk-protobuf │ ├── .gitignore │ ├── .npmignore │ ├── LICENSE │ ├── Makefile │ ├── README.md │ ├── dist │ │ ├── README.md │ │ ├── machinetalk-protobuf.js │ │ ├── machinetalk-protobuf.min.js │ │ ├── machinetalk-protobuf.min.js.gz │ │ └── machinetalk-protobuf.min.map.json │ ├── js │ │ ├── examples │ │ │ ├── decoding_message_container.js │ │ │ └── encoding_message_container.js │ │ ├── index.js │ │ └── scripts │ │ │ ├── bundle.js │ │ │ └── install.js │ ├── package.json │ ├── python │ │ ├── examples │ │ │ ├── decode_message_container.py │ │ │ └── encode_message_container.py │ │ ├── machinetalk │ │ │ ├── __init__.py │ │ │ └── protobuf │ │ │ │ └── __init__.py │ │ └── setup.py │ ├── scripts │ │ ├── asciidoc.mustache │ │ ├── ios-replace.sh │ │ ├── markdown.mustache │ │ └── protoc-gen-depends │ └── src │ │ ├── README.msgid │ │ └── machinetalk │ │ └── protobuf │ │ ├── canon.proto │ │ ├── config.proto │ │ ├── emcclass.proto │ │ ├── firmware.proto │ │ ├── log.proto │ │ ├── message.proto │ │ ├── motcmds.proto │ │ ├── nanopb.proto │ │ ├── object.proto │ │ ├── preview.proto │ │ ├── rtapi_message.proto │ │ ├── rtapicommand.proto │ │ ├── status.proto │ │ ├── task.proto │ │ ├── test.proto │ │ ├── types.proto │ │ └── value.proto └── zynq-ip │ ├── .gitignore │ ├── btint_axi_1.0 │ ├── component.xml │ ├── src │ │ ├── btint_axi_v1_0.vhd │ │ ├── btint_controller.vhd │ │ ├── btint_controller_tb.vhd │ │ ├── btint_top.vhd │ │ ├── pkt_builder_tx.vhd │ │ ├── pkt_builder_tx_tb.vhd │ │ ├── pkt_receiver_rx.vhd │ │ ├── pkt_receiver_rx_tb.vhd │ │ ├── ram_dualp.vhd │ │ ├── uart_rx.vhd │ │ ├── uart_rx_tb.vhd │ │ ├── uart_test_app.vhd │ │ ├── uart_test_app_control.vhd │ │ ├── uart_tx.vhd │ │ └── uart_tx_tb.vhd │ └── xgui │ │ └── btint_axi_v1_0.tcl │ ├── hm2_axilite │ ├── component.xml │ ├── src │ │ ├── hm2_axilite_gen32_simreg.vhd │ │ ├── hm2_axilite_int.vhd │ │ └── hm2_axilite_int_tb.vhd │ └── xgui │ │ └── hm2_axilite_int_v1_0.tcl │ ├── hm2_io_ts │ ├── component.xml │ ├── src │ │ └── hm2_io_ts.vhd │ └── xgui │ │ └── hm2_io_ts_v1.tcl │ └── hm2_ip_wrap │ ├── .gitignore │ ├── component.xml.in │ ├── src │ ├── firmware_id.vhd │ ├── hostmot2.vhd │ ├── hostmot2_ip_wrap.vhd.in │ └── wordpr.vhd │ └── xgui │ └── HostMot2_ip_wrap_v1_0.tcl ├── Makefile.Quartus ├── README.MD ├── SW └── MK │ ├── dts-overlays │ └── template.dts │ ├── kernel-drivers │ ├── .gitignore │ ├── README.md │ └── hm2reg_uio-module │ │ ├── .kdev4 │ │ └── hm2reg_uio-module.kdev4 │ │ ├── Kbuild │ │ ├── Makefile │ │ ├── hm2reg_uio-module.c │ │ └── hm2reg_uio-module.kdev4 │ ├── packaging │ ├── Makefile.cv │ ├── Makefile.zynq │ └── postinstall.sh │ └── uio_irq_test │ ├── Makefile │ ├── uio_test │ ├── uio_test-1.c │ ├── uio_test.c │ └── uio_test.o ├── build.quartus.sh ├── build.vivado.sh └── docs ├── Beta3-rel ├── mksocfpga_hm2-dir-ok.png └── mksocfpga_hm2-step-pulse.png ├── IRQ-mod_readme.md ├── Qemu-workarounds.md ├── Quartus-Qsys-Ip-search-path_linux-location.md ├── Quartus-Setup-guide.md ├── Quartus-setup-notes └── Altera-15.1-depedencies-and-udev-rules.md ├── README.MD ├── hm2reg-io_orig-timing.png ├── notes-about-quartus.md ├── pics ├── Hostmot2-vhd_inst-pinouts.png ├── Hps-fpga-bridges.png ├── hm2_soc-steprate1.png ├── hm2_soc-steprate2.png ├── hm2reg-io_orig-timing.png └── irq │ ├── HM-Soc-DPLL_wave.png │ ├── HM-Soc-IRQ_wave1.png │ └── HM-Soc-IRQ_wave2.png ├── rtl-views ├── HM2-conn-idrom-addr-print.pdf ├── HM2-conn-print.pdf └── IDROM-print.pdf ├── set-uboot-env.md └── test-configs ├── hm2-soc-stepper-cramps ├── 5i25-soc.ini ├── hm2-soc-stepper-5i25.hal ├── hm2-soc-stepper.var └── tool.tbl ├── hm2_soc-steprate1.png └── hm2_soc-steprate2.png /.gitignore: -------------------------------------------------------------------------------- 1 | *.pyc 2 | -------------------------------------------------------------------------------- /HW/Quartus-Qsys-Ip-search-path_linux-location.md: -------------------------------------------------------------------------------- 1 | Qsys complaining about ip core not found, can be solved by adding a relative(to project folder) path 2 | to the (custom) ip cores: 3 | 4 | The qsys ip search path is now solved 5 | by placing the soc_system.ipx (a .ipx) file in the project folder containing: 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | ---- 14 | 15 | This is about the Quartus gui Global ip library search path: 16 | 17 | Resides in file: 18 | ~/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 19 | 20 | Contents example: 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | Linux Quartus 15.1(Installed in standard location) Relocation Fix for addidn a path to a new global custom ip core: 29 | 30 | (path is relative to quartus project folder) 31 | 32 | Change path to relative path instead: 33 | 34 | 35 | mib@debian9-ws:~$ cat /home/mib/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 36 | 37 | 38 | 39 | 40 | 41 | mib@debian9-ws:~$ cat ~/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 42 | 43 | 44 | 45 | 46 | mib@debian9-ws:~$ 47 | 48 | do: 49 | 50 | cat < ~/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 51 | 52 | 53 | 54 | 55 | EOT 56 | 57 | -------------------------------------------------------------------------------- /HW/QuartusProjects/.gitignore: -------------------------------------------------------------------------------- 1 | # Working with Altera Quartus II (Q2) and do proper versioning is not that easy 2 | # but if you follow some rules it can be accomplished. :) 3 | # This file should be placed into the main directory where the .qpf file is 4 | # found. Generally Q2 throws all entities and so on in the main directory, but 5 | # you can place all stuff also in separate folders. This approach is followed 6 | # here. So when you create a new design create one or more folders where your 7 | # entities will be located and put a .gitignore in there that overrides the 8 | # ignores of this file, e.g. one single rule stating "!*" which allows now all 9 | # type of files. When you add a MegaFunction or another entity to your design, 10 | # simply add it to one of your private folders and Q2 will be happy and manage 11 | # everything quite good. When you want to do versioning of your generated 12 | # SOF/POF files, you can do this by redirecting the generated output to an own 13 | # folder. To do this go to: 14 | # "Assignments" 15 | # -> "Settings 16 | # -> "Compilation Process Settings" 17 | # -> "Save project output files in specified directory" 18 | # Now you can either place a .gitignore in the directory and allow the following 19 | # list of types: 20 | # !*.sof 21 | # !*.pof 22 | # or you create an own submodule in the folder to keep binary files out of your 23 | # design. 24 | 25 | # ignore hdl source files in top level directory 26 | # *.vhd 27 | # *.v 28 | 29 | # ignore Quartus II generated files 30 | *sopc_* 31 | *.jdi 32 | *.ptf.* 33 | *.sof 34 | *.pof 35 | *.cdf 36 | *.qws 37 | *.smsg 38 | *_inst.vhd 39 | *_generation_script* 40 | *.done 41 | *.txt 42 | *.qarlog 43 | *.rpt 44 | *.summary 45 | *.qws 46 | *.cmp 47 | *.eqn 48 | *.html 49 | *.jpg 50 | *.bak 51 | *.qar 52 | *.sopc_builder 53 | *example* 54 | *~ 55 | *.tar.gz 56 | *.pin 57 | *.hex 58 | *.ddb 59 | *.stp 60 | *.rar 61 | *.dpf 62 | *.qdf 63 | *.bz2 64 | *.gz 65 | *.csv 66 | *.dts 67 | *.dtb 68 | *.scr 69 | *.script 70 | *.sopcinfo 71 | # ignore Quartus II generated folders 72 | db/ 73 | incremental_db/ 74 | simulation/ 75 | timing/ 76 | testbench/ 77 | *_sim/ 78 | hps_isw_handoff/ 79 | output_files/ 80 | soc_system/ 81 | software/ 82 | stamp/ 83 | # ignore qsys generated folder 84 | .qsys_edit/ 85 | # ignore build generated files 86 | *.mif 87 | *.qip 88 | -------------------------------------------------------------------------------- /HW/QuartusProjects/Common/I2C_Controller.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2005 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altrea Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL or Verilog source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions:i2c controller 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Joe Yang :| 05/07/10 :| Initial Revision 41 | // V2.0 :| Joe Yang :| 12/12/16 :| Initial Revision 42 | // -------------------------------------------------------------------- 43 | module I2C_Controller ( 44 | input CLOCK, 45 | input [23:0]I2C_DATA, 46 | input GO, 47 | input RESET, 48 | input W_R, 49 | inout I2C_SDAT, 50 | output I2C_SCLK, 51 | output END, 52 | output ACK 53 | ); 54 | 55 | wire SDAO ; 56 | 57 | assign I2C_SDAT = SDAO?1'bz :0 ; 58 | 59 | I2C_WRITE_WDATA wrd( 60 | .RESET_N ( RESET), 61 | .PT_CK ( CLOCK), 62 | .GO ( GO ), 63 | .END_OK ( END ), 64 | .ACK_OK ( ACK ), 65 | .BYTE_NUM ( 2 ), //2byte 66 | .SDAI ( I2C_SDAT ),//IN 67 | .SDAO ( SDAO ),//OUT 68 | .SCLO ( I2C_SCLK ), 69 | .SLAVE_ADDRESS( I2C_DATA[23:16] ), 70 | .REG_DATA ( I2C_DATA[15:0] ) 71 | ); 72 | 73 | 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /HW/QuartusProjects/Common/bidir_io.sv: -------------------------------------------------------------------------------- 1 | module bidir_io 2 | #(parameter IOWidth=36, parameter PortNumWidth=8, parameter Mux_En = 1) 3 | ( 4 | input [PortNumWidth-1:0] portselnum [IOWidth-1:0], 5 | input clk, 6 | input [IOWidth-1:0] out_ena, 7 | input [IOWidth-1:0] od, 8 | input [IOWidth-1:0] out_data, 9 | inout [IOWidth-1:0] gpioport, 10 | output [IOWidth-1:0] data_from_gpio 11 | ); 12 | 13 | reg [IOWidth-1:0] io_data_in; 14 | reg [IOWidth-1:0] outmuxdataout; 15 | 16 | wire [IOWidth-1:0] od_data; 17 | 18 | genvar loop; 19 | generate 20 | for(loop=0;loop 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 15.1.2 Build 193 02/01/2016 SJ Lite Edition 22 | # Date created = 10:42:34 July 26, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "15.1" 27 | DATE = "10:42:34 July 26, 2017" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "DE0_Nano_SoC_Cramps" 32 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************ 2 | # Initial sdc file 3 | # 4 | #************************************************************ 5 | 6 | 7 | # Clock constraints 8 | 9 | create_clock -name "fpga_clk1_50" -period 20.000ns [get_ports {FPGA_CLK1_50}] 10 | 11 | 12 | # Automatically constrain PLL and other generated clocks 13 | derive_pll_clocks -create_base_clocks 14 | 15 | # Automatically calculate clock uncertainty to jitter and other effects. 16 | derive_clock_uncertainty 17 | 18 | 19 | # tsu/th constraints 20 | 21 | # tco constraints 22 | 23 | # tpd constraints 24 | 25 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE0_Nano_SoC_Cramps/generate_hps_qsys_header.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | sopc-create-header-files \ 4 | "$PWD/soc_system.sopcinfo" \ 5 | --single hps_0.h \ 6 | --module hps_0 7 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE0_Nano_SoC_DB25/.gitignore: -------------------------------------------------------------------------------- 1 | *_tmp 2 | *.kate-swp 3 | hostmot2_cfg.vhd 4 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.qpf: -------------------------------------------------------------------------------- 1 | DATE = "Tue Dec 2 09:28:38 2014" 2 | QUARTUS_VERSION = "14.0" 3 | 4 | # Revisions 5 | 6 | PROJECT_REVISION = "DE0_Nano_SoC_DB25" 7 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE0_Nano_SoC_DB25/generate_hps_qsys_header.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | sopc-create-header-files \ 4 | "$PWD/soc_system.sopcinfo" \ 5 | --single hps_0.h \ 6 | --module hps_0 7 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_Commands.md: -------------------------------------------------------------------------------- 1 | DE10_Nano_Commands: 2 | 3 | u-boot: (replace xx:xx:xx:xx:xx:xx with a REAL mac address) 4 | 5 | setenv ethaddr xx:xx:xx:xx:xx:xx 6 | setenv hostname mksocfpga-nano-soc 7 | saveenv 8 | reset 9 | 10 | sudo apt update 11 | 12 | Machinekit: 13 | 14 | sudo apt-get install $(apt-cache depends machinekit | grep Depends | sed "s/.*ends:\ //" | tr '\n' ' ') 15 | sudo apt purge machinekit 16 | (sudo dpkg -i machinekit-rt-preempt_0.1.1-1_armhf.deb machinekit_0.1.1-1_armhf.deb) 17 | (sudo apt-get autoremove) 18 | sudo apt install machinekit-rt-preempt 19 | 20 | Configs: 21 | sudo apt install socfpga-rbf 22 | sudo apt install git ca-certificates 23 | 24 | git clone https://github.com/the-snowwhite/Hm2-soc_FDM.git 25 | for De10_Nano: 26 | 27 | cd Hm2-soc_FDM 28 | git checkout DE10_Nano_FB_Cramps 29 | cd ~/ 30 | 31 | git clone https://github.com/the-snowwhite/Machineface.git 32 | cd Machineface 33 | git checkout work-updated 34 | cd ~/ 35 | git clone https://github.com/the-snowwhite/Cetus.git 36 | cd Cetus 37 | git checkout probework2 38 | cd ~/ 39 | 40 | SPI for tmc2130 stepper drivers: 41 | 42 | git clone --recursive https://github.com/the-snowwhite/SPI.git 43 | sudo apt install python-dev 44 | cd SPI/py-spidev 45 | sudo python setup.py install 46 | cd ~/ 47 | 48 | if /usr/include/features.h:374:25: fatal error: sys/cdefs.h: No such file or directory 49 | -->sudo apt install --reinstall libc6-dev 50 | sudo python setup.py install 51 | cd ~/ 52 | 53 | gksu leafpad /etc/linuxcnc/machinekit.ini 54 | --> REMOTE=1 55 | 56 | cat < start.sh 57 | #!/bin/bash 58 | 59 | ## Enable debug 60 | sudo sh -c 'echo 1 > /proc/sys/fs/suid_dumpable' 61 | export DEBUG=5 62 | 63 | /home/machinekit/SPI/set_tmc2130.sh 8 64 | /usr/bin/mklauncher /home/machinekit/Hm2-soc_FDM 65 | 66 | EOT 67 | 68 | chmod +x start.sh 69 | 70 | ./start.sh 71 | 72 | then run machinekit client :-) -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_FB_Cramps/.gitignore: -------------------------------------------------------------------------------- 1 | *.qip 2 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.qpf: -------------------------------------------------------------------------------- 1 | DATE = "17:14:54 March 04, 2015" 2 | QUARTUS_VERSION = "14.1" 3 | 4 | # Revisions 5 | 6 | PROJECT_REVISION = "DE10_Nano_FB_Cramps" 7 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************ 2 | # THIS IS A WIZARD-GENERATED FILE. 3 | # 4 | # Version 13.0.0 Build 156 04/24/2013 Service Pack 0.dp1 SJ Full Version 5 | # 6 | #************************************************************ 7 | 8 | # Copyright (C) 1991-2013 Altera Corporation 9 | # Your use of Altera Corporation's design tools, logic functions 10 | # and other software and tools, and its AMPP partner logic 11 | # functions, and any output files from any of the foregoing 12 | # (including device programming or simulation files), and any 13 | # associated documentation or information are expressly subject 14 | # to the terms and conditions of the Altera Program License 15 | # Subscription Agreement, Altera MegaCore Function License 16 | # Agreement, or other applicable license agreement, including, 17 | # without limitation, that your use is for the sole purpose of 18 | # programming logic devices manufactured by Altera and sold by 19 | # Altera or its authorized distributors. Please refer to the 20 | # applicable agreement for further details. 21 | 22 | 23 | 24 | # Clock constraints 25 | 26 | create_clock -name "clock_50_0" -period 20.000ns [get_ports {FPGA_CLK1_50}] 27 | create_clock -name "clock_50_1" -period 20.000ns [get_ports {FPGA_CLK2_50}] 28 | create_clock -name "clock_50_2" -period 20.000ns [get_ports {FPGA_CLK3_50}] 29 | 30 | 31 | # Automatically constrain PLL and other generated clocks 32 | derive_pll_clocks -create_base_clocks 33 | 34 | # Automatically calculate clock uncertainty to jitter and other effects. 35 | derive_clock_uncertainty 36 | 37 | 38 | create_clock -name "HDMI_TX_CLK" -period "75.0 MHz" [get_ports {HDMI_TX_CLK}] 39 | 40 | 41 | # tsu/th constraints 42 | 43 | # tco constraints 44 | 45 | # tpd constraints 46 | 47 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system_board_info.xml: -------------------------------------------------------------------------------- 1 | 2 | 13 | 14 | 15 | 16 | altr,socfpga-cyclone5 17 | altr,socfpga 18 | 19 | 20 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25.qpf: -------------------------------------------------------------------------------- 1 | DATE = "17:14:54 March 04, 2015" 2 | QUARTUS_VERSION = "14.1" 3 | 4 | # Revisions 5 | 6 | PROJECT_REVISION = "DE10_Nano_SoC_FB_DB25" 7 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/README.md: -------------------------------------------------------------------------------- 1 | This project is a clone of the DE0_Nano_SoC_DB25 project only with an added framebuffer driving the HDMI output. 2 | 3 | The current screen resolution is: 1024x768x8bpp @60Hz. 4 | 5 | 6 | The frame reader runs on a separate bus (f2h_sdram) as bus master, making it noticably faster than a cpu alone fb. 7 | 8 | This project uses the hm2 config files from the DE0_Nano_SoC_DB25 project folder, so it will run with the same hm2 soc configs. 9 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/generate_hps_qsys_header.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | sopc-create-header-files \ 3 | "./soc_system.sopcinfo" \ 4 | --single hps_0.h \ 5 | --module hps_0 6 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system_board_info.xml: -------------------------------------------------------------------------------- 1 | 2 | 13 | 14 | 15 | 16 | altr,socfpga-cyclone5 17 | altr,socfpga 18 | 19 | 20 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE1_SOC_GHRD/generate_hps_qsys_header.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | sopc-create-header-files \ 4 | "$PWD/soc_system.sopcinfo" \ 5 | --single hps_0.h \ 6 | --module hps_0 7 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE1_SOC_GHRD/soc_system.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE1_SOC_GHRD/soc_system.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.0 Build 154 09/04/2013 SJ Full Version 21 | # Date created = 08:49:17 September 11, 2013 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.1" 26 | DATE = "08:49:17 September 11, 2013" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "soc_system" 31 | -------------------------------------------------------------------------------- /HW/QuartusProjects/DE1_SOC_GHRD/soc_system_timing.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************ 2 | # THIS IS A WIZARD-GENERATED FILE. 3 | # 4 | # Version 13.1.0 Build 162 10/23/2013 SJ Full Version 5 | # 6 | #************************************************************ 7 | 8 | # Copyright (C) 1991-2013 Altera Corporation 9 | # Your use of Altera Corporation's design tools, logic functions 10 | # and other software and tools, and its AMPP partner logic 11 | # functions, and any output files from any of the foregoing 12 | # (including device programming or simulation files), and any 13 | # associated documentation or information are expressly subject 14 | # to the terms and conditions of the Altera Program License 15 | # Subscription Agreement, Altera MegaCore Function License 16 | # Agreement, or other applicable license agreement, including, 17 | # without limitation, that your use is for the sole purpose of 18 | # programming logic devices manufactured by Altera and sold by 19 | # Altera or its authorized distributors. Please refer to the 20 | # applicable agreement for further details. 21 | 22 | 23 | 24 | # Clock constraints 25 | 26 | create_clock -name "clock_50_1" -period 20.000ns [get_ports {CLOCK_50}] 27 | create_clock -name "clock_50_2" -period 20.000ns [get_ports {CLOCK2_50}] 28 | create_clock -name "clock_50_3" -period 20.000ns [get_ports {CLOCK3_50}] 29 | create_clock -name "clock_50_4" -period 20.000ns [get_ports {CLOCK4_50}] 30 | create_clock -name "clock_27_1" -period 37.000ns [get_ports {TD_CLK27}] 31 | 32 | 33 | # Automatically constrain PLL and other generated clocks 34 | derive_pll_clocks -create_base_clocks 35 | 36 | # Automatically calculate clock uncertainty to jitter and other effects. 37 | derive_clock_uncertainty 38 | 39 | # tsu/th constraints 40 | 41 | # tco constraints 42 | 43 | # tpd constraints 44 | -------------------------------------------------------------------------------- /HW/README.BuildSystem.txt: -------------------------------------------------------------------------------- 1 | Build System Install Notes 2 | ========================== 3 | 4 | How to create a Debian based Quartus system to build the FPGA code 5 | Debian Jessie 6 | Quartus 15.1.2 7 | 8 | Install Debian Jessie amd64 via net install on your favorite platform 9 | Full details can be found elsewhere 10 | I used VirtualBox and the netboot mini.iso installer 11 | Install the base system 12 | Username: builder 13 | Password: builder 14 | Install software selections: 15 | SSH server 16 | standard system utilities 17 | *NO* Desktop selected! (unless you want *LOTS* of extra stuff) 18 | 19 | Install additional required Debian packages: 20 | git 21 | make 22 | libsm6 23 | 24 | Obtain the Quartus install files from: 25 | http://dl.altera.com/15.1/?edition=lite&platform=linux&download_manager=direct 26 | 27 | Quartus Prime: 28 | Size: 1.7 GB MD5: CC8BFDE25F57C2F05D1753882BC9607A 29 | QuartusLiteSetup-15.1.0.185-linux.run 30 | 31 | Cyclone V device support: 32 | Size: 1.1 GB MD5: 7F108A307455ACDC3CF6DA21B1FBF211 33 | cyclonev-15.1.0.185.qdz 34 | 35 | Quartus Prime Software v15.1 Update 2 36 | Size: 4.1 GB MD5: EECCEF76A26E98E8022C59C7491FC215 37 | QuartusSetup-15.1.2.193-linux.run 38 | 39 | Connect to the system via ssh with X11 port-forwarding 40 | (the Altera install scripts launch "pop-up" windows) 41 | 42 | Install the Quartus tools: 43 | ./QuartusLiteSetup-15.1.0.185-linux.run 44 | 45 | Add the Quartus tools to your path: 46 | # This assumes the default install location for user "builder". Adjust as 47 | # necessary for your system 48 | export PATH="$PATH:/home/builder/altera_lite/15.1/quartus/bin:/home/builder/altera_lite/15.1/quartus/sopc_builder/bin" 49 | 50 | Enable Talkback: 51 | tb2_install 52 | 53 | Grab the source code: 54 | 55 | git clone https://github.com/the-snowwhite/mksocfpga.git 56 | 57 | Build the bitfile: 58 | 59 | cd mksocfpga/HW/QuartusProjects/DE0_NAN0_SOC_GHRD 60 | make rbf 61 | ...wait... 62 | ...wait... 63 | ...wait... 64 | If all went well, your chip is ready! 65 | FPGA programming file will be: 66 | output_files/soc_system.rbf 67 | 68 | -------------------------------------------------------------------------------- /HW/README.machinetalk-protobuf: -------------------------------------------------------------------------------- 1 | HW/machinetalk-protobuf is brought in as a subtree from 2 | git://github.com/machinekit/machinetalk-protobuf.git 3 | 4 | to update the subtree (eg if a proto file changes): 5 | 6 | git remote add machinetalk-protobuf git://github.com/machinekit/machinetalk-protobuf.git 7 | git fetch machinetalk-protobuf 8 | git subtree merge --prefix=HW/machinetalk-protobuf machinetalk-protobuf/ --squash 9 | 10 | and prepare a PR from the resulting commit. 11 | 12 | -------------------------------------------------------------------------------- /HW/README.md: -------------------------------------------------------------------------------- 1 | Note: Qsys complaints about ip search path not found can be solved via a single file: 2 | the Quartus gui Global ip core library path likewise: 3 | look at: 4 | 5 | [fix Qsys ip search path link:](Quartus-Qsys-Ip-search-path_linux-location.md) 6 | 7 | 8 | --- 9 | 10 | Using the Makefile: 11 | 12 | Start Quartus shell: 13 | 14 | '~/altera/15.1/embedded/embedded_command_shell.sh' 15 | 16 | cd to one of the quartus project folders: 17 | 18 | cd /the-snowwhite_git/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_Cramps 19 | 20 | to start quartus gui with the project in current folder loaded: 21 | 22 | make quartus_edit 23 | 24 | 25 | To script compile all needed output files for Machinekit (via hm2_soc driver): 26 | 27 | make all (same as dts dtb rbf) 28 | 29 | Note: 30 | 31 | 32 | The projects Quartus config is in *.qsf file(be carefull when hand editing). 33 | Beware There are (unclear when needed) differences between linux / and windows \\ Global paths. 34 | 35 | 36 | Note2: 37 | 38 | On my (older) SocKit boards the usb serial uart chip does not power on from the usb cable alone. 39 | Forcing you to power on the SocKit board before dev/ttyUSB0 gets available. And dropping the usb 40 | connection when you power-off-reboot the board. 41 | 42 | This is because the uart chips Reset signal is pulled down too much (0.84V) to be able to come out 43 | of reset without powering up the whole board (caused by the chip connected to R301). 44 | 45 | A simple fix for this is to simply desolder R301. (On pcb-bottomside, near middle about 3 cm abowe switches [H_SW0]) -------------------------------------------------------------------------------- /HW/VivadoProjects/.gitignore: -------------------------------------------------------------------------------- 1 | webtalk* 2 | *_created 3 | *.jou 4 | *.log 5 | all.bif 6 | *.bit 7 | *.bit.bin 8 | firmware_id.mif 9 | .Xil 10 | -------------------------------------------------------------------------------- /HW/VivadoProjects/avnet/ultra96/ultra96v1-mk-2019.1.bsp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/HW/VivadoProjects/avnet/ultra96/ultra96v1-mk-2019.1.bsp -------------------------------------------------------------------------------- /HW/VivadoProjects/avnet/ultra96/ultra96v1_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename 4 | TCL_TEMP_FILE=../../zynqmp_bp.tcl.in 5 | 6 | # The fpga device we are building for 7 | FPGA_DEVICE=xczu3eg-sbva484-1-e 8 | FPGA_DEV_SHORT=xczu3eg 9 | 10 | # Base Project Name 11 | BOARD_NAME=ultra96v1 12 | PRJ_NAME="$BOARD_NAME"_"$FPGA_DEV_SHORT" 13 | 14 | # The board part file url, if the target has one 15 | BOARD_PART="em.avnet.com:ultra96v1:part0:1.2" 16 | 17 | # The physical package pin constraint file 18 | PIN_HW_XDC_FILE=const/ultra96_pinmap.xdc 19 | 20 | # The filename of the top level block diagram 21 | TOP_LEVEL_BD_FILE=scripts/soc_system.tcl 22 | 23 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 24 | # belong in an xdc file above 25 | 26 | # HM2 Pin Filename relative to project folder 27 | PIN_FILE=const/PIN_ULTR_36.vhd 28 | # Pin package name defined in above pin file 29 | PIN_NAME=PIN_ULTR_36 30 | #FWID File name in the const folder 31 | FWID_NAME=FWID_ULTRA96_36 32 | 33 | ############################################################################ 34 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 35 | # block diagram script 36 | ############################################################################ 37 | 38 | # The name of the board to compile into the IP. Matches board name in hal files 39 | BOARD_NAME_HIGH_HEX=52544C55 #ULTR 40 | BOARD_NAME_LOW_HEX=544E5641 #AVNT 41 | -------------------------------------------------------------------------------- /HW/VivadoProjects/avnet/ultra96/ultra96v2-mk-2019.1.bsp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/HW/VivadoProjects/avnet/ultra96/ultra96v2-mk-2019.1.bsp -------------------------------------------------------------------------------- /HW/VivadoProjects/avnet/ultra96/ultra96v2_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename 4 | TCL_TEMP_FILE=../../zynqmp_bp.tcl.in 5 | 6 | # The fpga device we are building for 7 | FPGA_DEVICE=xczu3eg-sbva484-1-e 8 | FPGA_DEV_SHORT=xczu3eg 9 | 10 | # Base Project Name 11 | BOARD_NAME=ultra96v2 12 | PRJ_NAME="$BOARD_NAME"_"$FPGA_DEV_SHORT" 13 | 14 | # The board part file url, if the target has one 15 | BOARD_PART="em.avnet.com:ultra96v2:part0:1.0" 16 | 17 | # The physical package pin constraint file 18 | PIN_HW_XDC_FILE=const/ultra96_pinmap.xdc 19 | 20 | # The filename of the top level block diagram 21 | TOP_LEVEL_BD_FILE=scripts/soc_system-v2.tcl 22 | 23 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 24 | # belong in an xdc file above 25 | 26 | # HM2 Pin Filename relative to project folder 27 | PIN_FILE=const/PIN_ULTR_36.vhd 28 | # Pin package name defined in above pin file 29 | PIN_NAME=PIN_ULTR_36 30 | #FWID File name in the const folder 31 | FWID_NAME=FWID_ULTRA96_36 32 | 33 | ############################################################################ 34 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 35 | # block diagram script 36 | ############################################################################ 37 | 38 | # The name of the board to compile into the IP. Matches board name in hal files 39 | BOARD_NAME_HIGH_HEX=52544C55 #ULTR 40 | BOARD_NAME_LOW_HEX=544E5641 #AVNT 41 | -------------------------------------------------------------------------------- /HW/VivadoProjects/bif/all.bif.in: -------------------------------------------------------------------------------- 1 | all: 2 | 3 | { 4 | %BIT_FILE% 5 | } 6 | -------------------------------------------------------------------------------- /HW/VivadoProjects/make_mpsoc_boot.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | set -e # Exit immediately if a command exits with a non-zero status 3 | 4 | # Builds Boot files for the mpsoc HW using Petalinux. Pass in the board name 5 | # for the project you want to build. Expects Xilinx tools to be installed in 6 | # /opt/Xilinx like in the docker image. 7 | 8 | usage () { 9 | echo "Usage: make_mpsoc_boot.sh boardname" 10 | exit 1 11 | } 12 | 13 | if [ -z "$1" ]; then 14 | usage 15 | fi 16 | 17 | CUR_DIR=`realpath .` 18 | 19 | case $1 in 20 | 21 | *"ultra96"*) 22 | cd /work/HW/VivadoProjects/avnet/ultra96 23 | BOARD_PART="xczu3eg" 24 | rev="2019.1" 25 | ;; 26 | 27 | *"fz3"*) 28 | cd /work/HW/VivadoProjects/myirtech/fz3 29 | BOARD_PART="xczu3eg" 30 | rev="2019.1" 31 | ;; 32 | 33 | *"ultramyir"*) 34 | cd /work/HW/VivadoProjects/myirtech/ultramyir 35 | BOARD_PART="xczu3eg" 36 | rev="2019.1" 37 | ;; 38 | 39 | *"kr260"*) 40 | cd /work/HW/VivadoProjects/xilinx/kr260 41 | BOARD_PART="xck26" 42 | rev="2022.2" 43 | ;; 44 | 45 | *) 46 | echo "cant't find board project folder" 47 | exit 1 48 | ;; 49 | esac 50 | 51 | 52 | 53 | # Delete any old project artifacts folder 54 | PRJ_DIR_CREATED=./"$1"-mk-"$rev" 55 | [ -d "$PRJ_DIR_CREATED" ] && rm -rf "$PRJ_DIR_CREATED" 56 | 57 | petalinux-create -t project -s "$1"-mk-"$rev".bsp 58 | cd "$1"-mk-"$rev" 59 | time petalinux-config --get-hw-description=../"$1"_"$BOARD_PART"_created/"$1"_"$BOARD_PART".sdk --silentconfig 60 | time petalinux-build 61 | petalinux-package --boot --fsbl images/linux/zynqmp_fsbl.elf --u-boot=images/linux/u-boot.elf --pmufw --atf --fpga images/linux/system.bit --force 62 | tar -zxf ./images/linux/rootfs.tar.gz ./lib/modules && tar -zcf ../lib.tar.gz ./lib && rm -r lib 63 | -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/7z010_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename. Leave this here 4 | # to let the config decide if the base template is 5 | # correct for the project 6 | TCL_TEMP_FILE=../../zynq_bp.tcl.in 7 | 8 | # The fpga device we are building for 9 | FPGA_DEVICE=xc7z010clg400-1 10 | FPGA_DEV_SHORT=7z010 11 | 12 | # Base Project Name 13 | PRJ_NAME=microzed_jd2cb_"$FPGA_DEV_SHORT" 14 | 15 | # The board part file url, if the target has one 16 | BOARD_PART="em.avnet.com:microzed_7010:part0:1.2" 17 | 18 | # The physical package pin constraint file 19 | PIN_HW_XDC_FILE=const/microzed_jd2cb_pinmap.xdc 20 | 21 | # The filename of the top level block diagram 22 | TOP_LEVEL_BD_FILE=scripts/mzed_jd2cb_bd.tcl 23 | 24 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 25 | # belong in an xdc file above 26 | 27 | # HM2 Pin Filename relative to project folder 28 | PIN_FILE=const/PIN_MJD2CB_32.vhd 29 | # Pin package name defined in above pin file 30 | PIN_NAME=PIN_MJD2CB_32 31 | #FWID File name in the const folder 32 | FWID_NAME=FWID_MJD2CB_32 33 | 34 | ############################################################################ 35 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 36 | # block diagram script 37 | ############################################################################ 38 | 39 | # The name of the board to compile into the IP. Matches board name in hal files 40 | BOARD_NAME_HIGH_HEX=4243444A #JDCB 41 | BOARD_NAME_LOW_HEX=4332444A #JD2M 42 | -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/7z020_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename. Leave this here 4 | # to let the config decide if the base template is 5 | # correct for the project 6 | TCL_TEMP_FILE=../../zynq_bp.tcl.in 7 | 8 | # The fpga device we are building for 9 | FPGA_DEVICE=xc7z020clg400-1 10 | FPGA_DEV_SHORT=7z020 11 | 12 | # Base Project Name 13 | PRJ_NAME=microzed_jd2cb_"$FPGA_DEV_SHORT" 14 | 15 | # The board part file url, if the target has one 16 | BOARD_PART="em.avnet.com:microzed_7020:part0:1.2" 17 | 18 | # The physical package pin constraint file 19 | PIN_HW_XDC_FILE=const/microzed_jd2cb_pinmap.xdc 20 | 21 | # The filename of the top level block diagram 22 | TOP_LEVEL_BD_FILE=scripts/mzed_jd2cb_bd.tcl 23 | 24 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 25 | # belong in an xdc file above 26 | 27 | # HM2 Pin Filename relative to project folder 28 | PIN_FILE=const/PIN_MJD2CB_32.vhd 29 | # Pin package name defined in above pin file 30 | PIN_NAME=PIN_MJD2CB_32 31 | #FWID File name in the const folder 32 | FWID_NAME=FWID_MJD2CB_32 33 | 34 | ############################################################################ 35 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 36 | # block diagram script 37 | ############################################################################ 38 | 39 | # The name of the board to compile into the IP. Matches board name in hal files 40 | BOARD_NAME_HIGH_HEX=4243444A #JDCB 41 | BOARD_NAME_LOW_HEX=4332444A #JD2M 42 | -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/dts/microzed_jd2cb_ol.dts.in: -------------------------------------------------------------------------------- 1 | /dts-v1/; /plugin/; 2 | 3 | / { 4 | fragment@0 { 5 | target = <&base_fpga_region>; 6 | #address-cells = <1>; 7 | #size-cells = <1>; 8 | __overlay__ { 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | 12 | firmware-name = "zynq/%BIT_FILE%"; 13 | 14 | hm2reg_io_0: hm2-socfpga0@0x43C00000 { 15 | compatible = "generic-uio,ui_pdrv"; 16 | reg = < 0x43C00000 0x00010000 >; 17 | interrupt-parent = <&intc>; 18 | interrupts = <0 29 1>; 19 | }; 20 | 21 | btint_axi_0: btint_axi0@0x43C10000 { 22 | compatible = "generic-uio,ui_pdrv"; 23 | reg = < 0x43C10000 0x00010000 >; 24 | interrupt-parent = <&intc>; 25 | interrupts = <0 30 1>; 26 | }; 27 | 28 | btint_axi_1: btint_axi1@0x43C20000 { 29 | compatible = "generic-uio,ui_pdrv"; 30 | reg = < 0x43C20000 0x00010000 >; 31 | interrupt-parent = <&intc>; 32 | interrupts = <0 31 1>; 33 | }; 34 | }; 35 | }; 36 | }; 37 | -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/ip/hm2_ip_wrap_jd2/src/inp_deb.vhd: -------------------------------------------------------------------------------- 1 | -- Debounces an input signal 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use work.reduction_pkg.all; 5 | 6 | entity inp_deb is 7 | generic ( 8 | NUM_STAGES : integer := 3 9 | ); 10 | port 11 | ( 12 | clk : in std_logic; 13 | input : in std_logic; 14 | output : out std_logic 15 | ); 16 | end entity; 17 | 18 | architecture beh of inp_deb is 19 | signal ff_pack : std_logic_vector(NUM_STAGES - 1 downto 0); 20 | signal filt_j, filt_k, filt_q : std_logic; 21 | begin 22 | process (clk) 23 | begin 24 | if (rising_edge(clk)) then 25 | -- JKFF for the filtered output 26 | if(filt_j = '1' and filt_k = '0') then 27 | filt_q <= '1'; 28 | elsif (filt_j = '0' and filt_k = '1') then 29 | filt_q <= '0'; 30 | elsif(filt_j = '0' and filt_k = '0') then 31 | filt_q <= filt_q; 32 | end if; 33 | 34 | ff_pack(NUM_STAGES - 1 downto 1) <= ff_pack((NUM_STAGES - 2) downto 0); 35 | 36 | -- Load new data into the first stage 37 | ff_pack(0) <= input; 38 | end if; 39 | end process; 40 | 41 | -- Make a big AND gate for the filter 42 | filt_j <= red_and(ff_pack); 43 | -- and a big BAND gate 44 | filt_k <= red_and(not ff_pack); 45 | 46 | -- Outputs 47 | output <= filt_q; 48 | end beh; 49 | -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/ip/hm2_ip_wrap_jd2/src/reduction_pkg.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package reduction_pkg is 5 | function red_and(X : in std_logic_vector) return std_logic; 6 | end reduction_pkg; 7 | 8 | package body reduction_pkg is 9 | function red_and(X : in std_logic_vector) return std_logic is 10 | variable tmp : std_logic := '1'; 11 | begin 12 | for i in X'range loop 13 | tmp := tmp and X(i); 14 | end loop; 15 | return tmp; 16 | end red_and; 17 | end package body; -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/ip/hm2_ip_wrap_jd2/src/sig_delay.vhd: -------------------------------------------------------------------------------- 1 | -- Debounces an input signal 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity sig_delay is 7 | generic ( 8 | CLOCK_RATE : natural := 100000000; -- The frequency of the input clock 9 | DELAY_TIME_INV : natural := 5; -- The frequency of a signal with period 10 | -- delay. 5Hz = 200ms of delay 11 | NUM_TIMER_BITS : natural := 32 12 | ); 13 | port 14 | ( 15 | clk : in std_logic; 16 | input : in std_logic; 17 | output : out std_logic 18 | ); 19 | end entity; 20 | 21 | architecture beh of sig_delay is 22 | type smtype is (idle, dly); 23 | signal current_state, next_state : smtype := idle; 24 | signal reg_out : std_logic := '0'; 25 | signal tmr_cnt : unsigned(NUM_TIMER_BITS - 1 downto 0) := (others => '0'); 26 | signal tmr_per : unsigned(NUM_TIMER_BITS - 1 downto 0) := to_unsigned(CLOCK_RATE / DELAY_TIME_INV, NUM_TIMER_BITS); 27 | begin 28 | output <= reg_out; 29 | 30 | update_reg : process(clk, current_state, input) 31 | begin 32 | if(rising_edge(clk)) then 33 | if(current_state = dly)then 34 | if(tmr_cnt = to_unsigned(0, NUM_TIMER_BITS)) then 35 | reg_out <= input; 36 | end if; 37 | end if; 38 | end if; 39 | end process update_reg; 40 | 41 | update_timer : process (clk, current_state, input, reg_out, tmr_cnt) 42 | begin 43 | if(rising_edge(clk)) then 44 | if(current_state = idle AND input /= reg_out) then 45 | tmr_cnt <= tmr_per; 46 | elsif(current_state = dly) then 47 | if(tmr_cnt >= to_unsigned(0, NUM_TIMER_BITS)) then 48 | tmr_cnt <= tmr_cnt - 1; 49 | end if; 50 | end if; 51 | end if; 52 | end process update_timer; 53 | 54 | update_state : process(clk, next_state) 55 | begin 56 | if(rising_edge(clk)) then 57 | current_state <= next_state; 58 | end if; 59 | end process update_state; 60 | 61 | calc_state : process(current_state, input, reg_out, tmr_cnt) 62 | begin 63 | next_state <= current_state; -- hold by default 64 | if(current_state = idle) then 65 | if(input /= reg_out) then 66 | next_state <= dly; 67 | end if; 68 | else 69 | if(tmr_cnt <= to_unsigned(0, NUM_TIMER_BITS)) then 70 | next_state <= idle; 71 | end if; 72 | end if; 73 | end process calc_state; 74 | end beh; 75 | 76 | -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/ip/jd2_mad_logic/jd2.com_user_jd2_mad_logic_1.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/HW/VivadoProjects/microzed/microzed_jd2cb/ip/jd2_mad_logic/jd2.com_user_jd2_mad_logic_1.zip -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/ip/jd2_mad_logic/src/inp_deb.vhd: -------------------------------------------------------------------------------- 1 | -- Debounces an input signal 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use work.reduction_pkg.all; 5 | 6 | entity inp_deb is 7 | generic ( 8 | NUM_STAGES : integer := 3 9 | ); 10 | port 11 | ( 12 | clk : in std_logic; 13 | input : in std_logic; 14 | output : out std_logic 15 | ); 16 | end entity; 17 | 18 | architecture beh of inp_deb is 19 | signal ff_pack : std_logic_vector(NUM_STAGES - 1 downto 0); 20 | signal filt_j, filt_k, filt_q : std_logic; 21 | begin 22 | process (clk) 23 | begin 24 | if (rising_edge(clk)) then 25 | -- JKFF for the filtered output 26 | if(filt_j = '1' and filt_k = '0') then 27 | filt_q <= '1'; 28 | elsif (filt_j = '0' and filt_k = '1') then 29 | filt_q <= '0'; 30 | elsif(filt_j = '0' and filt_k = '0') then 31 | filt_q <= filt_q; 32 | end if; 33 | 34 | ff_pack(NUM_STAGES - 1 downto 1) <= ff_pack((NUM_STAGES - 2) downto 0); 35 | 36 | -- Load new data into the first stage 37 | ff_pack(0) <= input; 38 | end if; 39 | end process; 40 | 41 | -- Make a big AND gate for the filter 42 | filt_j <= red_and(ff_pack); 43 | -- and a big BAND gate 44 | filt_k <= red_and(not ff_pack); 45 | 46 | -- Outputs 47 | output <= filt_q; 48 | end beh; 49 | -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/ip/jd2_mad_logic/src/reduction_pkg.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package reduction_pkg is 5 | function red_and(X : in std_logic_vector) return std_logic; 6 | end reduction_pkg; 7 | 8 | package body reduction_pkg is 9 | function red_and(X : in std_logic_vector) return std_logic is 10 | variable tmp : std_logic := '1'; 11 | begin 12 | for i in X'range loop 13 | tmp := tmp and X(i); 14 | end loop; 15 | return tmp; 16 | end red_and; 17 | end package body; -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/ip/jd2_mad_logic/src/sig_delay.vhd: -------------------------------------------------------------------------------- 1 | -- Debounces an input signal 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity sig_delay is 7 | generic ( 8 | CLOCK_RATE : natural := 100000000; -- The frequency of the input clock 9 | DELAY_TIME_INV : natural := 5; -- The frequency of a signal with period 10 | -- delay. 5Hz = 200ms of delay 11 | NUM_TIMER_BITS : natural := 32 12 | ); 13 | port 14 | ( 15 | clk : in std_logic; 16 | input : in std_logic; 17 | output : out std_logic 18 | ); 19 | end entity; 20 | 21 | architecture beh of sig_delay is 22 | type smtype is (idle, dly); 23 | signal current_state, next_state : smtype := idle; 24 | signal reg_out : std_logic := '0'; 25 | signal tmr_cnt : unsigned(NUM_TIMER_BITS - 1 downto 0) := (others => '0'); 26 | signal tmr_per : unsigned(NUM_TIMER_BITS - 1 downto 0) := to_unsigned(CLOCK_RATE / DELAY_TIME_INV, NUM_TIMER_BITS); 27 | begin 28 | output <= reg_out; 29 | 30 | update_reg : process(clk, current_state, input) 31 | begin 32 | if(rising_edge(clk)) then 33 | if(current_state = dly)then 34 | if(tmr_cnt = to_unsigned(0, NUM_TIMER_BITS)) then 35 | reg_out <= input; 36 | end if; 37 | end if; 38 | end if; 39 | end process update_reg; 40 | 41 | update_timer : process (clk, current_state, input, reg_out, tmr_cnt) 42 | begin 43 | if(rising_edge(clk)) then 44 | if(current_state = idle AND input /= reg_out) then 45 | tmr_cnt <= tmr_per; 46 | elsif(current_state = dly) then 47 | if(tmr_cnt >= to_unsigned(0, NUM_TIMER_BITS)) then 48 | tmr_cnt <= tmr_cnt - 1; 49 | end if; 50 | end if; 51 | end if; 52 | end process update_timer; 53 | 54 | update_state : process(clk, next_state) 55 | begin 56 | if(rising_edge(clk)) then 57 | current_state <= next_state; 58 | end if; 59 | end process update_state; 60 | 61 | calc_state : process(current_state, input, reg_out, tmr_cnt) 62 | begin 63 | next_state <= current_state; -- hold by default 64 | if(current_state = idle) then 65 | if(input /= reg_out) then 66 | next_state <= dly; 67 | end if; 68 | else 69 | if(tmr_cnt <= to_unsigned(0, NUM_TIMER_BITS)) then 70 | next_state <= idle; 71 | end if; 72 | end if; 73 | end process calc_state; 74 | end beh; 75 | 76 | -------------------------------------------------------------------------------- /HW/VivadoProjects/microzed/microzed_jd2cb/ip/jd2_mad_logic/xgui/jd2_mad_logic_v1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | ipgui::add_param $IPINST -name "WIDTH" 5 | ipgui::add_param $IPINST -name "NUM_DEB_STAGES" 6 | 7 | } 8 | 9 | proc update_PARAM_VALUE.NUM_DEB_STAGES { PARAM_VALUE.NUM_DEB_STAGES } { 10 | # Procedure called to update NUM_DEB_STAGES when any of the dependent parameters in the arguments change 11 | } 12 | 13 | proc validate_PARAM_VALUE.NUM_DEB_STAGES { PARAM_VALUE.NUM_DEB_STAGES } { 14 | # Procedure called to validate NUM_DEB_STAGES 15 | return true 16 | } 17 | 18 | proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { 19 | # Procedure called to update WIDTH when any of the dependent parameters in the arguments change 20 | } 21 | 22 | proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { 23 | # Procedure called to validate WIDTH 24 | return true 25 | } 26 | 27 | 28 | proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } { 29 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 30 | set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH} 31 | } 32 | 33 | proc update_MODELPARAM_VALUE.NUM_DEB_STAGES { MODELPARAM_VALUE.NUM_DEB_STAGES PARAM_VALUE.NUM_DEB_STAGES } { 34 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 35 | set_property value [get_property value ${PARAM_VALUE.NUM_DEB_STAGES}] ${MODELPARAM_VALUE.NUM_DEB_STAGES} 36 | } 37 | 38 | -------------------------------------------------------------------------------- /HW/VivadoProjects/myirtech/fz3/fz3-mk-2019.1.bsp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/HW/VivadoProjects/myirtech/fz3/fz3-mk-2019.1.bsp -------------------------------------------------------------------------------- /HW/VivadoProjects/myirtech/fz3/fz3_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename 4 | TCL_TEMP_FILE=../../zynqmp_bp.tcl.in 5 | 6 | # The fpga device we are building for 7 | FPGA_DEVICE=xczu3eg-sfvc784-1-e 8 | FPGA_DEV_SHORT=xczu3eg 9 | 10 | # Base Project Name 11 | BOARD_NAME=fz3 12 | PRJ_NAME="$BOARD_NAME"_"$FPGA_DEV_SHORT" 13 | 14 | # The board part file url, if the target has one 15 | BOARD_PART="myirtech.com:fz3:part0:1.0" 16 | 17 | # The physical package pin constraint file 18 | PIN_HW_XDC_FILE=const/fz3_pinmap.xdc 19 | 20 | # The filename of the top level block diagram 21 | TOP_LEVEL_BD_FILE=scripts/soc_system.tcl 22 | 23 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 24 | # belong in an xdc file above 25 | 26 | # HM2 Pin Filename relative to project folder 27 | PIN_FILE=const/PIN_FZ3_36.vhd 28 | # Pin package name defined in above pin file 29 | PIN_NAME=PIN_FZ3_36 30 | #FWID File name in the const folder 31 | FWID_NAME=FWID_FZ3_36 32 | 33 | ############################################################################ 34 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 35 | # block diagram script 36 | ############################################################################ 37 | 38 | # The name of the board to compile into the IP. Matches board name in hal files 39 | BOARD_NAME_HIGH_HEX=5F335A46 #FZ3_ 40 | BOARD_NAME_LOW_HEX=5249594D #MYIR 41 | -------------------------------------------------------------------------------- /HW/VivadoProjects/myirtech/ultramyir/ultramyir-mk-2019.1.bsp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/HW/VivadoProjects/myirtech/ultramyir/ultramyir-mk-2019.1.bsp -------------------------------------------------------------------------------- /HW/VivadoProjects/myirtech/ultramyir/ultramyir_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename 4 | TCL_TEMP_FILE=../../zynqmp_bp.tcl.in 5 | 6 | # The fpga device we are building for 7 | FPGA_DEVICE=xczu3eg-sfvc784-1-e 8 | FPGA_DEV_SHORT=xczu3eg 9 | 10 | # Base Project Name 11 | BOARD_NAME=ultramyir 12 | PRJ_NAME="$BOARD_NAME"_"$FPGA_DEV_SHORT" 13 | 14 | # The board part file url, if the target has one 15 | BOARD_PART="myir.com:ultramyir:part0:1.0" 16 | 17 | # The physical package pin constraint file 18 | PIN_HW_XDC_FILE=const/ultramyir_pinmap.xdc 19 | 20 | # The filename of the top level block diagram 21 | TOP_LEVEL_BD_FILE=scripts/soc_system.tcl 22 | 23 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 24 | # belong in an xdc file above 25 | 26 | # HM2 Pin Filename relative to project folder 27 | PIN_FILE=const/PIN_ULTRAMYIR_36.vhd 28 | # Pin package name defined in above pin file 29 | PIN_NAME=PIN_ULTRAMYIR_36 30 | #FWID File name in the const folder 31 | FWID_NAME=FWID_ULTRAMYIR_36 32 | 33 | ############################################################################ 34 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 35 | # block diagram script 36 | ############################################################################ 37 | 38 | # The name of the board to compile into the IP. Matches board name in hal files 39 | BOARD_NAME_HIGH_HEX=52544C55 #ULTR 40 | BOARD_NAME_LOW_HEX=5249594D #MYIR 41 | -------------------------------------------------------------------------------- /HW/VivadoProjects/xilinx/kr260/README.md: -------------------------------------------------------------------------------- 1 | ## Running machinekit-hal on the Kria KR260 board 2 | 3 | First Iteration of the KR260 port runs on the Xilinx Ubuntu Desktop 22.04 LTS from Canonical: 4 | https://ubuntu.com/download/amd-xilinx 5 | 6 | ## Docker based build image for building custom bitfiles: 7 | 8 | docker pull thesnowwhite/bionic-vivado-sdk:2022.2 9 | sudo mkdir /tftpboot 10 | /usr/bin/docker run --rm --privileged --memory 48g --shm-size 1g --device /dev/snd -itv $(pwd):/work -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix --net=host -e TZ=Europe/Copenhagen -v $HOME/.Xauthority:/home/vivado/.Xauthority -v $HOME/.Xresources:/home/vivado/.Xresources -v $HOME/.Xilinx:/home/vivado/.Xilinx -v /tftpboot:/tftpboot --name xilinx-sdk bionic-vivado-sdk:2022.2 /bin/bash 11 | 12 | ## To enable running hostmot2 based machinekit-hal the mksocfpga fpga firmware can be auto loaded 13 | 14 | 15 | wget https://github.com/machinekit/mksocfpga/releases/download/v1/kr260_xck26.bit 16 | wget https://github.com/machinekit/mksocfpga/releases/download/v1/kria_kr260_xck26_ol.dtbo 17 | 18 | sudo mkdir -p /lib/firmware/xilinx/machinekit 19 | sudo mv ./kr260_xck26.bit ./kria_kr260_xck26_ol.dtbo /lib/firmware/xilinx/machinekit 20 | 21 | sudo sh -c 'cat < "/lib/firmware/xilinx/machinekit/shell.json" 22 | { 23 | "shell_type" : "XRT_FLAT", 24 | "num_slots": "1" 25 | } 26 | EOF' 27 | 28 | sudo sh -c 'cat < "/etc/dfx-mgrd/default_firmware" 29 | machinekit 30 | EOF' 31 | 32 | Remember to reboot. 33 | 34 | Then install the following packages from the Machinekit(-hal) cloudsmith repos : 35 | 36 | sudo apt install machinekit-hal \ 37 | libmachinekit-hal \ 38 | modmachinekit-hal-components \ 39 | modmachinekit-hal-drivers 40 | 41 | ## Hal is then invoked with: 42 | 43 | halrun -I 44 | 45 | loadrt hostmot2 46 | newinst hm2_soc_ol hm2-socfpga0 already_programmed=1 -- config="num_pwmgens=3 num_stepgens=6" 47 | 48 | exit 49 | 50 | ## To check what happened in the log: 51 | 52 | cat /var/log/syslog | grep 'rtapi\|msgd' 53 | 54 | 55 | ## The syslog can be cleared with: 56 | 57 | sudo sh -c 'echo "" > /var/log/syslog' 58 | -------------------------------------------------------------------------------- /HW/VivadoProjects/xilinx/kr260/dts/kria_kr260_ol.dts.in: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | 3 | / { 4 | 5 | fragment@0 { 6 | target = <0xffffffff>; 7 | 8 | __overlay__ { 9 | #address-cells = <0x02>; 10 | #size-cells = <0x02>; 11 | firmware-name = "%BIT_FILE%"; 12 | resets = <0xffffffff 0x74 0xffffffff 0x75 0xffffffff 0x76 0xffffffff 0x77>; 13 | hm2reg_io_0: hm2-socfpga0@a0000000 { 14 | clock-names = "fclk0"; 15 | clocks = <0x03 0x47>; 16 | compatible = "generic-uio"; 17 | reg = <0x00 0xa0000000 0x00 0x10000>; 18 | }; 19 | }; 20 | }; 21 | 22 | __fixups__ { 23 | fpga_full = "/fragment@0:target:0"; 24 | zynqmp_reset = "/fragment@0/__overlay__:resets:0\0/fragment@0/__overlay__:resets:8\0/fragment@0/__overlay__:resets:16\0/fragment@0/__overlay__:resets:24"; 25 | }; 26 | }; 27 | -------------------------------------------------------------------------------- /HW/VivadoProjects/xilinx/kr260/kr260_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename 4 | TCL_TEMP_FILE=../../zynqmp_bp.tcl.in 5 | 6 | # The fpga device we are building for 7 | FPGA_DEVICE=xck26-sfvc784-2LV-c 8 | FPGA_DEV_SHORT=xck26 9 | 10 | # Base Project Name 11 | BOARD_NAME=kr260 12 | PRJ_NAME="$BOARD_NAME"_"$FPGA_DEV_SHORT" 13 | 14 | # The board part file url, if the target has one 15 | BOARD_PART="xilinx.com:kr260_som:part0:1.1" 16 | 17 | # The physical package pin constraint file 18 | PIN_HW_XDC_FILE=const/kr260_pinmap.xdc 19 | 20 | # The filename of the top level block diagram 21 | TOP_LEVEL_BD_FILE=scripts/soc_system.tcl 22 | 23 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 24 | # belong in an xdc file above 25 | 26 | # HM2 Pin Filename relative to project folder 27 | PIN_FILE=const/PIN_KR260_36.vhd 28 | # Pin package name defined in above pin file 29 | PIN_NAME=PIN_KR260_36 30 | #FWID File name in the const folder 31 | FWID_NAME=FWID_FZ3_36 32 | 33 | ############################################################################ 34 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 35 | # block diagram script 36 | ############################################################################ 37 | 38 | # The name of the board to compile into the IP. Matches board name in hal files 39 | BOARD_NAME_HIGH_HEX=3632524B #KR26 40 | BOARD_NAME_LOW_HEX=584E4C58 #XLNX 41 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_jd2cb/7z010_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename. Leave this here 4 | # to let the config decide if the base template is 5 | # correct for the project 6 | TCL_TEMP_FILE=../../zynq_bp.tcl.in 7 | 8 | # The fpga device we are building for 9 | FPGA_DEVICE=xc7z010clg400-1 10 | FPGA_DEV_SHORT=7z010 11 | 12 | # Base Project Name 13 | PRJ_NAME=zturn_jd2cb_"$FPGA_DEV_SHORT" 14 | 15 | # The board part file url, if the target has one 16 | BOARD_PART="" 17 | 18 | # The physical package pin constraint file 19 | PIN_HW_XDC_FILE=const/zturn_jd2cb_pinmap.xdc 20 | 21 | # The filename of the top level block diagram 22 | TOP_LEVEL_BD_FILE=scripts/zturn_jd2cb_bd.tcl 23 | 24 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 25 | # belong in an xdc file above 26 | 27 | # HM2 Pin Filename relative to project folder 28 | PIN_FILE=const/PIN_ZJD2CB_36.vhd 29 | # Pin package name defined in above pin file 30 | PIN_NAME=PIN_ZJD2CB_36 31 | #FWID File name in the const folder 32 | FWID_NAME=FWID_ZJD2CB_36 33 | 34 | ############################################################################ 35 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 36 | # block diagram script 37 | ############################################################################ 38 | 39 | # The name of the board to compile into the IP. Matches board name in hal files 40 | BOARD_NAME_HIGH_HEX=4243444A #JDCB 41 | BOARD_NAME_LOW_HEX=4332444A #JD2Z 42 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_jd2cb/7z020_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename. Leave this here 4 | # to let the config decide if the base template is 5 | # correct for the project 6 | TCL_TEMP_FILE=../../zynq_bp.tcl.in 7 | 8 | # The fpga device we are building for 9 | FPGA_DEVICE=xc7z020clg400-1 10 | FPGA_DEV_SHORT=7z020 11 | 12 | # Base Project Name 13 | PRJ_NAME=zturn_jd2cb_"$FPGA_DEV_SHORT" 14 | 15 | # The board part file url, if the target has one 16 | BOARD_PART="" 17 | 18 | # The physical package pin constraint file 19 | PIN_HW_XDC_FILE=const/zturn_jd2cb_pinmap.xdc 20 | 21 | # The filename of the top level block diagram 22 | TOP_LEVEL_BD_FILE=scripts/zturn_jd2cb_bd.tcl 23 | 24 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 25 | # belong in an xdc file above 26 | 27 | # HM2 Pin Filename relative to project folder 28 | PIN_FILE=const/PIN_ZJD2CB_36.vhd 29 | # Pin package name defined in above pin file 30 | PIN_NAME=PIN_ZJD2CB_36 31 | #FWID File name in the const folder 32 | FWID_NAME=FWID_ZJD2CB_36 33 | 34 | ############################################################################ 35 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 36 | # block diagram script 37 | ############################################################################ 38 | 39 | # The name of the board to compile into the IP. Matches board name in hal files 40 | BOARD_NAME_HIGH_HEX=4243444A #JDCB 41 | BOARD_NAME_LOW_HEX=4332444A #JD2Z 42 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_jd2cb/dts/zturn_jd2cb_ol.dts.in: -------------------------------------------------------------------------------- 1 | /dts-v1/; /plugin/; 2 | 3 | / { 4 | fragment@0 { 5 | target = <&base_fpga_region>; 6 | #address-cells = <1>; 7 | #size-cells = <1>; 8 | __overlay__ { 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | 12 | firmware-name = "zynq/%BIT_FILE%"; 13 | 14 | hm2reg_io_0: hm2-socfpga0@0x43C00000 { 15 | compatible = "generic-uio,ui_pdrv"; 16 | reg = < 0x43C00000 0x00010000 >; 17 | interrupt-parent = <&intc>; 18 | interrupts = <0 29 1>; 19 | }; 20 | 21 | btint_axi_0: btint_axi0@0x43C10000 { 22 | compatible = "generic-uio,ui_pdrv"; 23 | reg = < 0x43C10000 0x00010000 >; 24 | interrupt-parent = <&intc>; 25 | interrupts = <0 30 1>; 26 | }; 27 | 28 | btint_axi_1: btint_axi1@0x43C20000 { 29 | compatible = "generic-uio,ui_pdrv"; 30 | reg = < 0x43C20000 0x00010000 >; 31 | interrupt-parent = <&intc>; 32 | interrupts = <0 31 1>; 33 | }; 34 | }; 35 | }; 36 | }; 37 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_jd2cb/ip/jd2_mad_logic/src/inp_deb.vhd: -------------------------------------------------------------------------------- 1 | -- Debounces an input signal 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use work.reduction_pkg.all; 5 | 6 | entity inp_deb is 7 | generic ( 8 | NUM_STAGES : integer := 3 9 | ); 10 | port 11 | ( 12 | clk : in std_logic; 13 | input : in std_logic; 14 | output : out std_logic 15 | ); 16 | end entity; 17 | 18 | architecture beh of inp_deb is 19 | signal ff_pack : std_logic_vector(NUM_STAGES - 1 downto 0); 20 | signal filt_j, filt_k, filt_q : std_logic; 21 | begin 22 | process (clk) 23 | begin 24 | if (rising_edge(clk)) then 25 | -- JKFF for the filtered output 26 | if(filt_j = '1' and filt_k = '0') then 27 | filt_q <= '1'; 28 | elsif (filt_j = '0' and filt_k = '1') then 29 | filt_q <= '0'; 30 | elsif(filt_j = '0' and filt_k = '0') then 31 | filt_q <= filt_q; 32 | end if; 33 | 34 | ff_pack(NUM_STAGES - 1 downto 1) <= ff_pack((NUM_STAGES - 2) downto 0); 35 | 36 | -- Load new data into the first stage 37 | ff_pack(0) <= input; 38 | end if; 39 | end process; 40 | 41 | -- Make a big AND gate for the filter 42 | filt_j <= red_and(ff_pack); 43 | -- and a big BAND gate 44 | filt_k <= red_and(not ff_pack); 45 | 46 | -- Outputs 47 | output <= filt_q; 48 | end beh; 49 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_jd2cb/ip/jd2_mad_logic/src/reduction_pkg.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package reduction_pkg is 5 | function red_and(X : in std_logic_vector) return std_logic; 6 | end reduction_pkg; 7 | 8 | package body reduction_pkg is 9 | function red_and(X : in std_logic_vector) return std_logic is 10 | variable tmp : std_logic := '1'; 11 | begin 12 | for i in X'range loop 13 | tmp := tmp and X(i); 14 | end loop; 15 | return tmp; 16 | end red_and; 17 | end package body; -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_jd2cb/ip/jd2_mad_logic/src/sig_delay.vhd: -------------------------------------------------------------------------------- 1 | -- Debounces an input signal 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity sig_delay is 7 | generic ( 8 | CLOCK_RATE : natural := 100000000; -- The frequency of the input clock 9 | DELAY_TIME_INV : natural := 5; -- The frequency of a signal with period 10 | -- delay. 5Hz = 200ms of delay 11 | NUM_TIMER_BITS : natural := 32 12 | ); 13 | port 14 | ( 15 | clk : in std_logic; 16 | input : in std_logic; 17 | output : out std_logic 18 | ); 19 | end entity; 20 | 21 | architecture beh of sig_delay is 22 | type smtype is (idle, dly); 23 | signal current_state, next_state : smtype := idle; 24 | signal reg_out : std_logic := '0'; 25 | signal tmr_cnt : unsigned(NUM_TIMER_BITS - 1 downto 0) := (others => '0'); 26 | signal tmr_per : unsigned(NUM_TIMER_BITS - 1 downto 0) := to_unsigned(CLOCK_RATE / DELAY_TIME_INV, NUM_TIMER_BITS); 27 | begin 28 | output <= reg_out; 29 | 30 | update_reg : process(clk, current_state, input) 31 | begin 32 | if(rising_edge(clk)) then 33 | if(current_state = dly)then 34 | if(tmr_cnt = to_unsigned(0, NUM_TIMER_BITS)) then 35 | reg_out <= input; 36 | end if; 37 | end if; 38 | end if; 39 | end process update_reg; 40 | 41 | update_timer : process (clk, current_state, input, reg_out, tmr_cnt) 42 | begin 43 | if(rising_edge(clk)) then 44 | if(current_state = idle AND input /= reg_out) then 45 | tmr_cnt <= tmr_per; 46 | elsif(current_state = dly) then 47 | if(tmr_cnt >= to_unsigned(0, NUM_TIMER_BITS)) then 48 | tmr_cnt <= tmr_cnt - 1; 49 | end if; 50 | end if; 51 | end if; 52 | end process update_timer; 53 | 54 | update_state : process(clk, next_state) 55 | begin 56 | if(rising_edge(clk)) then 57 | current_state <= next_state; 58 | end if; 59 | end process update_state; 60 | 61 | calc_state : process(current_state, input, reg_out, tmr_cnt) 62 | begin 63 | next_state <= current_state; -- hold by default 64 | if(current_state = idle) then 65 | if(input /= reg_out) then 66 | next_state <= dly; 67 | end if; 68 | else 69 | if(tmr_cnt <= to_unsigned(0, NUM_TIMER_BITS)) then 70 | next_state <= idle; 71 | end if; 72 | end if; 73 | end process calc_state; 74 | end beh; 75 | 76 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_jd2cb/ip/jd2_mad_logic/xgui/jd2_mad_logic_v1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | ipgui::add_param $IPINST -name "WIDTH" 5 | ipgui::add_param $IPINST -name "NUM_DEB_STAGES" 6 | 7 | } 8 | 9 | proc update_PARAM_VALUE.NUM_DEB_STAGES { PARAM_VALUE.NUM_DEB_STAGES } { 10 | # Procedure called to update NUM_DEB_STAGES when any of the dependent parameters in the arguments change 11 | } 12 | 13 | proc validate_PARAM_VALUE.NUM_DEB_STAGES { PARAM_VALUE.NUM_DEB_STAGES } { 14 | # Procedure called to validate NUM_DEB_STAGES 15 | return true 16 | } 17 | 18 | proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { 19 | # Procedure called to update WIDTH when any of the dependent parameters in the arguments change 20 | } 21 | 22 | proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { 23 | # Procedure called to validate WIDTH 24 | return true 25 | } 26 | 27 | 28 | proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } { 29 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 30 | set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH} 31 | } 32 | 33 | proc update_MODELPARAM_VALUE.NUM_DEB_STAGES { MODELPARAM_VALUE.NUM_DEB_STAGES PARAM_VALUE.NUM_DEB_STAGES } { 34 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 35 | set_property value [get_property value ${PARAM_VALUE.NUM_DEB_STAGES}] ${MODELPARAM_VALUE.NUM_DEB_STAGES} 36 | } 37 | 38 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_ztio/7z010_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename 4 | TCL_TEMP_FILE=../../zynq_bp.tcl.in 5 | 6 | # The fpga device we are building for 7 | FPGA_DEVICE=xc7z010clg400-1 8 | FPGA_DEV_SHORT=7z010 9 | 10 | # Base Project Name 11 | PRJ_NAME=zturn_ztio_"$FPGA_DEV_SHORT" 12 | 13 | # The board part file url, if the target has one 14 | BOARD_PART="" 15 | 16 | # The physical package pin constraint file 17 | PIN_HW_XDC_FILE=const/zturn_ztio_pinmap.xdc 18 | 19 | # The filename of the top level block diagram 20 | TOP_LEVEL_BD_FILE=scripts/zturn_ztio_bd.tcl 21 | 22 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 23 | # belong in an xdc file above 24 | 25 | # HM2 Pin Filename relative to project folder 26 | PIN_FILE=const/PIN_ZTIO_34.vhd 27 | # Pin package name defined in above pin file 28 | PIN_NAME=PIN_ZTIO_34 29 | #FWID File name in the const folder 30 | FWID_NAME=FWID_ZTIO_34 31 | 32 | ############################################################################ 33 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 34 | # block diagram script 35 | ############################################################################ 36 | 37 | # The name of the board to compile into the IP. Matches board name in hal files 38 | BOARD_NAME_HIGH_HEX=4F49545A #ZTIO 39 | BOARD_NAME_LOW_HEX=5249594D #MYIR 40 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_ztio/7z020_config: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # TCL Template Filename 4 | TCL_TEMP_FILE=../../zynq_bp.tcl.in 5 | 6 | # The fpga device we are building for 7 | FPGA_DEVICE=xc7z020clg400-1 8 | FPGA_DEV_SHORT=7z020 9 | 10 | # Base Project Name 11 | PRJ_NAME=zturn_ztio_"$FPGA_DEV_SHORT" 12 | 13 | # The board part file url, if the target has one 14 | BOARD_PART="" 15 | 16 | # The physical package pin constraint file 17 | PIN_HW_XDC_FILE=const/zturn_ztio_pinmap.xdc 18 | 19 | # The filename of the top level block diagram 20 | TOP_LEVEL_BD_FILE=scripts/zturn_ztio_bd.tcl 21 | 22 | ## HostMot2 Pin constraints - these update the IP. Physical pin constraints 23 | # belong in an xdc file above 24 | 25 | # HM2 Pin Filename relative to project folder 26 | PIN_FILE=const/PIN_ZTIO_34.vhd 27 | # Pin package name defined in above pin file 28 | PIN_NAME=PIN_ZTIO_34 29 | #FWID File name in the const folder 30 | FWID_NAME=FWID_ZTIO_34 31 | 32 | ############################################################################ 33 | # HostMot2 Generic Parameters, autofills IP correctly without regenerating 34 | # block diagram script 35 | ############################################################################ 36 | 37 | # The name of the board to compile into the IP. Matches board name in hal files 38 | BOARD_NAME_HIGH_HEX=4F49545A #ZTIO 39 | BOARD_NAME_LOW_HEX=5249594D #MYIR 40 | -------------------------------------------------------------------------------- /HW/VivadoProjects/zturn/zturn_ztio/dts/zturn_ztio_ol.dts.in: -------------------------------------------------------------------------------- 1 | /dts-v1/; /plugin/; 2 | 3 | / { 4 | fragment@0 { 5 | target = <&base_fpga_region>; 6 | #address-cells = <1>; 7 | #size-cells = <1>; 8 | __overlay__ { 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | 12 | firmware-name = "zynq/%BIT_FILE%"; 13 | 14 | hm2reg_io_0: hm2-socfpga0@0x43C00000 { 15 | compatible = "generic-uio,ui_pdrv"; 16 | reg = < 0x43C00000 0x00010000 >; 17 | interrupt-parent = <&intc>; 18 | interrupts = <0 29 1>; 19 | }; 20 | }; 21 | }; 22 | }; 23 | -------------------------------------------------------------------------------- /HW/cv-ip/ADC_LTC2308_FIFO/README.md: -------------------------------------------------------------------------------- 1 | ## Readme for ADC_LTC2308_FIFO ip core modded by Michael Brown marts 2016 for Machinekit usage ## 2 | 3 | 4 | The core now has single channel read as before. 5 | 6 | And a new auto channel select mode, which increases the selected channel on each read (0-7) and then wraps around to ch 0. 7 | 8 | The buffer can contain upto 2048 samples, which each are appended with the adc channel number the data sample is read from. 9 | 10 | the ip core currently presents 2 16 bit read write registers of which: 11 | 12 | reg 0 is used only as control / status register. 13 | 14 | reg 1 is also used for reading the data samples. 15 | 16 | 17 | 18 | WRite: 19 | // write for control 20 | reg measure_fifo_start; 21 | reg [11:0] measure_fifo_num; 22 | reg [2:0] measure_fifo_ch; 23 | reg auto_ch_select; 24 | 25 | addr 0 `define WRITE_REG_START_CH 0 {auto_ch_select, measure_fifo_ch, measure_fifo_start} <= slave_writedata[4:0]; 26 | 27 | addr 1 `define WRITE_REG_MEASURE_NUM 1 {measure_fifo_num} <= slave_writedata[11:0]; 28 | 29 | REad: 30 | reg measure_fifo_done; 31 | wire [11:0] fifo_q; 32 | wire [2:0] fifo_ch_q; 33 | 34 | addr 0 `define READ_REG_MEASURE_DONE 0 slave_read_status slave_readdata <= {measure_fifo_ch, measure_fifo_num, measure_fifo_done}; 35 | 36 | addr 1 `define READ_REG_ADC_VALUE 1 slave_read_data slave_readdata <= {1'b0, fifo_ch_q, fifo_q}; 37 | 38 | 39 | A typical data read cycle would consist of: 40 | 41 | 1. setting the number of measurements by writing reg 1. 42 | 43 | 2. setting bit 1 in reg 1 to 0 (and selected ch in bits 3 - 1, and eventually setting bit 4 for auto ch select mode) 44 | 45 | 3. setting bit 1 in reg 1 to 1 (and selected ch in bits 3 - 1, and eventually setting bit 4 for auto ch select mode) 46 | 47 | Starts the adc read run. 48 | 49 | 4. setting bit 1 in reg 1 to 0 (and selected ch in bits 3 - 1, and eventually setting bit 4 for auto ch select mode) 50 | 51 | Makes the adc ready for next read. 52 | 53 | 54 | NOTE: the measure_fifo_done signal (bit 0 in reg 0), is 1 when the adc data measurement run is finished an data is ready to be read. 55 | 56 | See the adcreg driver and app example software (in mksocfpga/SW/MK/kernel-drivers/ folder) for specifics. 57 | [here: relative link](../../../SW/MK/kernel-drivers/) 58 | -------------------------------------------------------------------------------- /HW/cv-ip/ADC_LTC2308_FIFO/adc1stp1-set-counter.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/HW/cv-ip/ADC_LTC2308_FIFO/adc1stp1-set-counter.jpg -------------------------------------------------------------------------------- /HW/cv-ip/ADC_LTC2308_FIFO/adc_data_fifo.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "15.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "adc_data_fifo.v"] 5 | -------------------------------------------------------------------------------- /HW/cv-ip/ADC_LTC2308_FIFO/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | INTENDED_DEVICE_FAMILY="Cyclone V" 2 | LPM_NUMWORDS=2048 3 | LPM_SHOWAHEAD=ON 4 | LPM_TYPE=dcfifo 5 | LPM_WIDTH=15 6 | LPM_WIDTHU=11 7 | OVERFLOW_CHECKING=ON 8 | RDSYNC_DELAYPIPE=4 9 | READ_ACLR_SYNCH=OFF 10 | UNDERFLOW_CHECKING=ON 11 | USE_EAB=ON 12 | WRITE_ACLR_SYNCH=OFF 13 | WRSYNC_DELAYPIPE=4 14 | DEVICE_FAMILY="Cyclone V" 15 | aclr 16 | data 17 | rdclk 18 | rdreq 19 | wrclk 20 | wrreq 21 | q 22 | rdempty 23 | wrfull 24 | -------------------------------------------------------------------------------- /HW/cv-ip/altsource_probe/hps_reset.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "In-System Sources and Probes" 2 | set_global_assignment -name IP_TOOL_VERSION "15.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hps_reset.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hps_reset_bb.v"] 6 | -------------------------------------------------------------------------------- /HW/cv-ip/cv_ip_pkg.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package cv_ip_pkg is 5 | 6 | component debounce is 7 | generic ( 8 | WIDTH : integer := 32; 9 | POLARITY : string := "HIGH"; 10 | TIMEOUT : integer := 50000; 11 | TIMEOUT_WIDTH : integer := 16 ); 12 | port ( 13 | clk : in std_logic; 14 | reset_n : in std_logic; 15 | data_in : in std_logic_vector(WIDTH-1 downto 0); 16 | data_out : out std_logic_vector(WIDTH-1 downto 0) ); 17 | end component; 18 | 19 | component altera_edge_detector is 20 | generic ( 21 | PULSE_EXT : integer := 0; 22 | EDGE_TYPE : integer := 0; 23 | IGNORE_RST_WHILE_BUSY : integer := 0 ); 24 | port ( 25 | clk : in std_logic; 26 | rst_n : in std_logic; 27 | signal_in : in std_logic; 28 | pulse_out : out std_logic ); 29 | end component; 30 | 31 | component hps_reset is 32 | port ( 33 | probe : in std_logic; 34 | source_clk : in std_logic; 35 | source : out std_logic_vector(2 downto 0) ); 36 | end component; 37 | 38 | component I2C_HDMI_Config is 39 | generic ( 40 | CLK_Freq : integer := 50000000; 41 | I2C_Freq : integer := 20000; 42 | LUT_SIZE : integer := 31 ); 43 | port ( 44 | iCLK : in std_logic; 45 | iRST_N : in std_logic; 46 | I2C_SCLK : out std_logic; 47 | I2C_SDAT : inout std_logic; 48 | HDMI_TX_INT : in std_logic; 49 | READY : out std_logic ); 50 | end component; 51 | 52 | end cv_ip_pkg; 53 | 54 | -------------------------------------------------------------------------------- /HW/cv-ip/edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | module altera_edge_detector #( 2 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 3 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 4 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 5 | ) ( 6 | input clk, 7 | input rst_n, 8 | input signal_in, 9 | output pulse_out 10 | ); 11 | 12 | localparam IDLE = 0, ARM = 1, CAPT = 2; 13 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 14 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 15 | 16 | reg [1:0] state, next_state; 17 | reg pulse_detect; 18 | wire busy_pulsing; 19 | 20 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 21 | assign reset_qual_n = rst_n | busy_pulsing; 22 | 23 | generate 24 | if (PULSE_EXT > 1) begin: pulse_extend 25 | integer i; 26 | reg [PULSE_EXT-1:0] extend_pulse; 27 | always @(posedge clk or negedge reset_qual_n) begin 28 | if (!reset_qual_n) 29 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 30 | else begin 31 | for (i = 1; i < PULSE_EXT; i = i+1) begin 32 | extend_pulse[i] <= extend_pulse[i-1]; 33 | end 34 | extend_pulse[0] <= pulse_detect; 35 | end 36 | end 37 | assign pulse_out = |extend_pulse; 38 | end 39 | else begin: single_pulse 40 | reg pulse_reg; 41 | always @(posedge clk or negedge reset_qual_n) begin 42 | if (!reset_qual_n) 43 | pulse_reg <= 1'b0; 44 | else 45 | pulse_reg <= pulse_detect; 46 | end 47 | assign pulse_out = pulse_reg; 48 | end 49 | endgenerate 50 | 51 | always @(posedge clk) begin 52 | if (!rst_n) 53 | state <= IDLE; 54 | else 55 | state <= next_state; 56 | end 57 | 58 | // edge detect 59 | always @(*) begin 60 | next_state = state; 61 | pulse_detect = 1'b0; 62 | case (state) 63 | IDLE : begin 64 | pulse_detect = 1'b0; 65 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 66 | else next_state = IDLE; 67 | end 68 | ARM : begin 69 | pulse_detect = 1'b0; 70 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 71 | else next_state = ARM; 72 | end 73 | CAPT : begin 74 | pulse_detect = 1'b1; 75 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 76 | else next_state = IDLE; 77 | end 78 | default : begin 79 | pulse_detect = 1'b0; 80 | next_state = IDLE; 81 | end 82 | endcase 83 | end 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /HW/cv-ip/hm2reg_io/hm2reg_io.v: -------------------------------------------------------------------------------- 1 | module hm2reg_io ( 2 | // signals to connect to an Avalon clock source interface 3 | input clk, 4 | input reset_n, 5 | // signals to connect to an Avalon-MM slave interface 6 | input [ADDRESS_WIDTH-1:0] slave_address, 7 | input slave_read, 8 | input slave_write, 9 | output reg [DATA_WIDTH-1:0] slave_readdata, 10 | input [DATA_WIDTH-1:0] slave_writedata, 11 | input slave_chipselect, 12 | // interrupt siganls 13 | output reg slave_irq, 14 | // signals to connect to custom con logic 15 | output reg [DATA_WIDTH-1:0] con_dataout, 16 | input [DATA_WIDTH-1:0] con_datain, 17 | output [ADDRESS_WIDTH-1:0] con_adrout, 18 | output reg con_write_out, 19 | output con_read_out, 20 | output con_chip_sel, 21 | input con_int_in 22 | ); 23 | 24 | parameter ADDRESS_WIDTH = 14; // address size width 25 | parameter DATA_WIDTH = 32; // word size of each input and output register 26 | 27 | parameter IRQ_EN = 1; // 0 = Enable interrupt, 1 = Disable interrupt 28 | 29 | assign con_adrout[ADDRESS_WIDTH-1:0] = slave_address[ADDRESS_WIDTH-1:0]; 30 | assign con_chip_sel = slave_chipselect; 31 | assign con_read_out = slave_read; 32 | 33 | 34 | always @(posedge clk) begin 35 | if (!reset_n) begin 36 | slave_readdata[DATA_WIDTH-1:0] <= 0; 37 | slave_irq <= 0; 38 | con_dataout[DATA_WIDTH-1:0] <= 0; 39 | con_write_out <= 0; 40 | 41 | end 42 | else begin 43 | con_write_out <= slave_write; 44 | if (slave_read) begin 45 | slave_readdata[DATA_WIDTH-1:0] <= con_datain[DATA_WIDTH-1:0]; 46 | end 47 | if (slave_write) begin 48 | con_dataout <= slave_writedata; 49 | end 50 | if (IRQ_EN == 1) begin 51 | if (!con_int_in) 52 | slave_irq <= 1'b1; 53 | else if (slave_read) 54 | slave_irq <= 1'b0; 55 | end 56 | end 57 | end 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /HW/cv-ip/hm2reg_io/machinekiticon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/HW/cv-ip/hm2reg_io/machinekiticon.png -------------------------------------------------------------------------------- /HW/cv-ip/intr_capturer/intr_capturer.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module intr_capturer #( 14 | parameter NUM_INTR = 32 15 | // active high level interrupt is expected for the input of this capturer module 16 | )( 17 | input clk, 18 | input rst_n, 19 | input [NUM_INTR-1:0] interrupt_in, 20 | //input [31:0] wrdata, 21 | input addr, 22 | input read, 23 | output [31:0] rddata 24 | ); 25 | 26 | reg [NUM_INTR-1:0] interrupt_reg; 27 | reg [31:0] readdata_with_waitstate; 28 | wire [31:0] act_readdata; 29 | wire [31:0] readdata_lower_intr; 30 | wire [31:0] readdata_higher_intr; 31 | wire access_lower_32; 32 | wire access_higher_32; 33 | 34 | always @(posedge clk or negedge rst_n) begin 35 | if (!rst_n) interrupt_reg <= 'b0; 36 | else interrupt_reg <= interrupt_in; 37 | end 38 | 39 | generate 40 | if (NUM_INTR>32) begin : two_intr_reg_needed 41 | assign access_higher_32 = read & (addr == 1); 42 | 43 | assign readdata_lower_intr = interrupt_reg[31:0] & {(32){access_lower_32}}; 44 | assign readdata_higher_intr = interrupt_reg[NUM_INTR-1:32] & {(NUM_INTR-32){access_higher_32}}; 45 | end 46 | else begin : only_1_reg 47 | assign readdata_lower_intr = interrupt_reg & {(NUM_INTR){access_lower_32}}; 48 | assign readdata_higher_intr = {32{1'b0}}; 49 | end 50 | endgenerate 51 | 52 | assign access_lower_32 = read & (addr == 0); 53 | assign act_readdata = readdata_lower_intr | readdata_higher_intr; 54 | assign rddata = readdata_with_waitstate; 55 | 56 | always @(posedge clk or negedge rst_n) begin 57 | if (!rst_n) readdata_with_waitstate <= 32'b0; 58 | else readdata_with_waitstate <= act_readdata; 59 | end 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/1366x769-HDMI.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/15-inch-touch-lvds.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/15-inch_touch-lvds.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/B156XTT01.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/HDMI_1024x768.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/HDMI_15-i-lvds-1366x768.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/LP101WX1.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/VESA_1368x768@60.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/de1_soc-fb.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/de1_soc_fb.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /HW/cv-ip/presets/vga1024x768.qprs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /HW/cv-megawizard/lpm-ip/lpm_mux16.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, the Altera Quartus Prime License Agreement, 9 | --the Altera MegaCore Function License Agreement, or other 10 | --applicable license agreement, including, without limitation, 11 | --that your use is for the sole purpose of programming logic 12 | --devices manufactured by Altera and sold by Altera or its 13 | --authorized distributors. Please refer to the applicable 14 | --agreement for further details. 15 | 16 | 17 | component lpm_mux16 18 | PORT 19 | ( 20 | data0 : IN STD_LOGIC ; 21 | data1 : IN STD_LOGIC ; 22 | data10 : IN STD_LOGIC ; 23 | data11 : IN STD_LOGIC ; 24 | data12 : IN STD_LOGIC ; 25 | data13 : IN STD_LOGIC ; 26 | data14 : IN STD_LOGIC ; 27 | data15 : IN STD_LOGIC ; 28 | data2 : IN STD_LOGIC ; 29 | data3 : IN STD_LOGIC ; 30 | data4 : IN STD_LOGIC ; 31 | data5 : IN STD_LOGIC ; 32 | data6 : IN STD_LOGIC ; 33 | data7 : IN STD_LOGIC ; 34 | data8 : IN STD_LOGIC ; 35 | data9 : IN STD_LOGIC ; 36 | sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 37 | result : OUT STD_LOGIC 38 | ); 39 | end component; 40 | -------------------------------------------------------------------------------- /HW/cv-megawizard/lpm-ip/lpm_mux16.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "15.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux16.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux16.cmp"] 6 | -------------------------------------------------------------------------------- /HW/cv-megawizard/lpm-ip/lpm_mux16_inst.vhd: -------------------------------------------------------------------------------- 1 | lpm_mux16_inst : lpm_mux16 PORT MAP ( 2 | data0 => data0_sig, 3 | data1 => data1_sig, 4 | data10 => data10_sig, 5 | data11 => data11_sig, 6 | data12 => data12_sig, 7 | data13 => data13_sig, 8 | data14 => data14_sig, 9 | data15 => data15_sig, 10 | data2 => data2_sig, 11 | data3 => data3_sig, 12 | data4 => data4_sig, 13 | data5 => data5_sig, 14 | data6 => data6_sig, 15 | data7 => data7_sig, 16 | data8 => data8_sig, 17 | data9 => data9_sig, 18 | sel => sel_sig, 19 | result => result_sig 20 | ); 21 | -------------------------------------------------------------------------------- /HW/cv-megawizard/lpm-ip/lpm_shiftreg16.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, the Altera Quartus Prime License Agreement, 9 | --the Altera MegaCore Function License Agreement, or other 10 | --applicable license agreement, including, without limitation, 11 | --that your use is for the sole purpose of programming logic 12 | --devices manufactured by Altera and sold by Altera or its 13 | --authorized distributors. Please refer to the applicable 14 | --agreement for further details. 15 | 16 | 17 | component lpm_shiftreg16 18 | PORT 19 | ( 20 | clock : IN STD_LOGIC ; 21 | enable : IN STD_LOGIC ; 22 | shiftin : IN STD_LOGIC ; 23 | q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) 24 | ); 25 | end component; 26 | -------------------------------------------------------------------------------- /HW/cv-megawizard/lpm-ip/lpm_shiftreg16.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "15.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg16.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg16_inst.vhd"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg16.cmp"] 7 | -------------------------------------------------------------------------------- /HW/cv-megawizard/lpm-ip/lpm_shiftreg16_inst.vhd: -------------------------------------------------------------------------------- 1 | lpm_shiftreg16_inst : lpm_shiftreg16 PORT MAP ( 2 | clock => clock_sig, 3 | enable => enable_sig, 4 | shiftin => shiftin_sig, 5 | q => q_sig 6 | ); 7 | -------------------------------------------------------------------------------- /HW/firmware-tag/.gitignore: -------------------------------------------------------------------------------- 1 | foo.bin 2 | foo.mif 3 | foo.hex 4 | generate.txt 5 | -------------------------------------------------------------------------------- /HW/firmware-tag/DE0_Nano_SoC_Cramps.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "altera socfpga" 12 | fw.num_leds = 0 13 | fw.board_name = "Terasic DE0-Nano" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P0" 17 | c.pins = 24 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P1" 21 | c.pins = 24 22 | 23 | c = fw.connector.add() 24 | c.name = "GPIO0.P2" 25 | c.pins = 24 26 | 27 | return fw 28 | -------------------------------------------------------------------------------- /HW/firmware-tag/DE0_Nano_SoC_DB25.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "altera socfpga" 12 | fw.num_leds = 4 13 | fw.board_name = "Terasic DE0-Nano" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P2" 17 | c.pins = 17 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P3" 21 | c.pins = 17 22 | 23 | c = fw.connector.add() 24 | c.name = "GPIO1.P2" 25 | c.pins = 17 26 | 27 | c = fw.connector.add() 28 | c.name = "GPIO1.P3" 29 | c.pins = 17 30 | 31 | return fw 32 | -------------------------------------------------------------------------------- /HW/firmware-tag/DE10_Nano_FB_Cramps.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "altera socfpga" 12 | fw.num_leds = 0 13 | fw.board_name = "Terasic DE10-Nano" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P0" 17 | c.pins = 24 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P1" 21 | c.pins = 24 22 | 23 | c = fw.connector.add() 24 | c.name = "GPIO0.P2" 25 | c.pins = 24 26 | 27 | return fw 28 | -------------------------------------------------------------------------------- /HW/firmware-tag/DE10_Nano_SoC_FB_DB25.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "altera socfpga" 12 | fw.num_leds = 4 13 | fw.board_name = "Terasic DE10-Nano" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P2" 17 | c.pins = 17 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P3" 21 | c.pins = 17 22 | 23 | c = fw.connector.add() 24 | c.name = "GPIO1.P2" 25 | c.pins = 17 26 | 27 | c = fw.connector.add() 28 | c.name = "GPIO1.P3" 29 | c.pins = 17 30 | 31 | return fw 32 | -------------------------------------------------------------------------------- /HW/firmware-tag/FWID_FZ3_36.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "xczu3eg-sfvc784-1-e" 12 | fw.num_leds = 1 13 | fw.board_name = "FZ3" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P0" 17 | c.pins = 18 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P1" 21 | c.pins = 18 22 | 23 | return fw 24 | 25 | -------------------------------------------------------------------------------- /HW/firmware-tag/FWID_KR260_36.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "xck26-sfvc784-2LV-c" 12 | fw.num_leds = 1 13 | fw.board_name = "KR260" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P0" 17 | c.pins = 18 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P1" 21 | c.pins = 18 22 | 23 | return fw 24 | 25 | -------------------------------------------------------------------------------- /HW/firmware-tag/FWID_MJD2CB_32.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "7z010" 12 | fw.num_leds = 0 13 | fw.board_name = "JDCBM" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P1" 17 | c.pins = 32 18 | 19 | return fw 20 | -------------------------------------------------------------------------------- /HW/firmware-tag/FWID_ULTRA96_36.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "xczu3eg-sbva484-1-e" 12 | fw.num_leds = 1 13 | fw.board_name = "ULTR" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P0" 17 | c.pins = 18 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P1" 21 | c.pins = 18 22 | 23 | return fw 24 | 25 | -------------------------------------------------------------------------------- /HW/firmware-tag/FWID_ULTRAMYIR_36.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "xczu3eg-sfvc784-1-e" 12 | fw.num_leds = 1 13 | fw.board_name = "ULTRAMYIR" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P0" 17 | c.pins = 18 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P1" 21 | c.pins = 18 22 | 23 | return fw 24 | 25 | -------------------------------------------------------------------------------- /HW/firmware-tag/FWID_ZJD2CB_36.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "7z010" 12 | fw.num_leds = 0 13 | fw.board_name = "JDCBZ" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P1" 17 | c.pins = 18 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P2" 21 | c.pins = 18 22 | 23 | return fw 24 | 25 | -------------------------------------------------------------------------------- /HW/firmware-tag/FWID_ZTIO_34.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.firmware_pb2 import Firmware, Connector 2 | from util import get_git_revision_short_hash, get_build_url 3 | 4 | 5 | def gen_fwid(*args,**kwargs): 6 | # construct the descriptor object 7 | fw = Firmware() 8 | fw.build_sha = get_git_revision_short_hash() 9 | fw.comment = get_build_url() 10 | 11 | fw.fpga_part_number = "7z010" 12 | fw.num_leds = 3 13 | fw.board_name = "ZTIO" 14 | 15 | c = fw.connector.add() 16 | c.name = "GPIO0.P1" 17 | c.pins = 17 18 | 19 | c = fw.connector.add() 20 | c.name = "GPIO0.P2" 21 | c.pins = 17 22 | 23 | return fw 24 | 25 | -------------------------------------------------------------------------------- /HW/firmware-tag/Makefile: -------------------------------------------------------------------------------- 1 | # override as needed with 'make TOPDIR=' 2 | TOPDIR := $(realpath ../..) 3 | 4 | all: py-proto example.mif 5 | 6 | 7 | py-proto: $(TOPDIR)/HW/machinetalk-protobuf/build/python/machinetalk/protobuf/firmware_pb2.py 8 | 9 | $(TOPDIR)/HW/machinetalk-protobuf/build/python/machinetalk/protobuf/firmware_pb2.py: 10 | (cd $(TOPDIR)/HW/machinetalk-protobuf; make) 11 | 12 | example.mif: genfwid.py mif.py 13 | python genfwid.py 7I76_7I76_7I76_7I76 14 | 15 | -------------------------------------------------------------------------------- /HW/firmware-tag/genfwid.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import os 3 | import binascii 4 | import struct 5 | import mif 6 | import argparse 7 | import google.protobuf.text_format 8 | 9 | # path to generated protobuf imports 10 | sys.path.insert(0, os.path.abspath(os.path.dirname(os.path.abspath(__file__)) + "../../machinetalk-protobuf/build/python")) 11 | 12 | 13 | maxsize = 2048 14 | cookie = 0xFEEDBABE 15 | width = 32 # of MIF file 16 | format = '.py - eg 7I76_7I76_7I76_7I76.py 25 | fwid = __import__(args.config) 26 | fw = fwid.gen_fwid() 27 | 28 | # serialize it to a blob 29 | buffer = fw.SerializeToString() 30 | 31 | print "%%\nconfig argument: %s" % (args.config) 32 | print "\nsize of encoded message: %d 0x%x" % (fw.ByteSize(),fw.ByteSize()) 33 | print "text format representation:\n---\n", str(fw), "---\n" 34 | print "wire format length=%d %s" % (len(buffer), binascii.hexlify(buffer)) 35 | 36 | # generate the Altera MIF file 37 | # prepend with cookie and length field 38 | blob = struct.pack(format, cookie) + struct.pack(format, fw.ByteSize()) + buffer 39 | 40 | assert len(blob) <= maxsize, ValueError("encoded message size too large: %d (max %d)" % (len(blob), maxsize)) 41 | 42 | print "\nsize of MIF struct including cookie and length field: %d" % (len(blob)) 43 | print "%\n\n" 44 | 45 | mif.create(sys.stdout, width, len(blob), blob, format=format) 46 | -------------------------------------------------------------------------------- /HW/firmware-tag/mif.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # lifted from https://www-asim.lip6.fr/svn/dsx/dsx/trunk/dsx/lib/python/bintools/mif.py 3 | 4 | __all__ = ['create'] 5 | 6 | import struct 7 | 8 | def emit_mif_internal(fd, data, width = 4, format='>L'): 9 | addr = 0 10 | while data: 11 | word = data[:4] 12 | data = data[4:] 13 | if len(word) < 4: 14 | word = word + "\x00"*(4-len(word)) 15 | wval, = struct.unpack(format, word) 16 | print >> fd, ' %04x : %08x;'%( addr, wval ) 17 | addr += 1 18 | return addr 19 | 20 | def create(fd, width, depth, data, format='>L'): 21 | assert width%8 == 0, ValueError("width must be *8") 22 | wdepth = depth / (width / 8) 23 | if wdepth*(width / 8) < depth: 24 | wdepth += 1 25 | print >> fd, "WIDTH=%d;" % width 26 | print >> fd, "DEPTH=%d;" % wdepth 27 | print >> fd 28 | print >> fd, "ADDRESS_RADIX=HEX;" 29 | print >> fd, "DATA_RADIX=HEX;" 30 | print >> fd 31 | print >> fd, "CONTENT BEGIN" 32 | end_addr = emit_mif_internal(fd, data, format=format) 33 | if end_addr < depth/(width/8)-1: 34 | print >> fd, " [%04x .. %04x] : %08x;" % (end_addr, depth/(width/8)-1, 0) 35 | print >> fd, "END;" 36 | 37 | 38 | def _main(): 39 | import sys 40 | create(sys.stdout, 41 | int(sys.argv[2]), 42 | int(sys.argv[3]), 43 | open(sys.argv[1]).read()) 44 | 45 | if __name__ == '__main__': 46 | _main() 47 | 48 | -------------------------------------------------------------------------------- /HW/firmware-tag/util.py: -------------------------------------------------------------------------------- 1 | import subprocess 2 | import os 3 | 4 | def get_git_revision_short_hash(): 5 | try: 6 | sha = subprocess.check_output(['git', 'rev-parse', '--short', 'HEAD']).strip() 7 | except Exception: 8 | sha = "not a git repo" 9 | return sha 10 | 11 | def get_build_url(): 12 | url = os.getenv("BUILD_URL") 13 | if url is None: 14 | url = "$BUILD_URL unset" 15 | return url 16 | 17 | 18 | if __name__ == "__main__": 19 | print "sha:", get_git_revision_short_hash() 20 | print "build_url:", get_build_url() 21 | 22 | -------------------------------------------------------------------------------- /HW/hm2/.gitignore: -------------------------------------------------------------------------------- 1 | *.bak -------------------------------------------------------------------------------- /HW/hm2/config/DE0_Nano_SoC_DB25/hm2_DE0_Nano_SoC_DB25.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE ../../hm2/config/IDROMConst.vhd 2 | set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25_card.vhd 3 | set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_DB25/PIN_7I76_7I85S_GPIO_GPIO.vhd 4 | set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_DB25/PIN_7I76_7I76_7I76_7I76.vhd 5 | set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_DB25/PIN_7I77_7I76_GPIO_GPIO.vhd 6 | set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_DB25/PIN_G540_G540_GPIO_GPIO.vhd 7 | set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_DB25/PIN_A_Volkov.vhd 8 | set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_DB25/PIN_4s6p1q_GPIO_GPIO_GPIO.vhd 9 | 10 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24.sv: -------------------------------------------------------------------------------- 1 | package boardtype; 2 | // DE0-Nano Dev kit and I/O adaptors specific info 3 | // {STRAIGHT=0,DB25=1} BoardAdaptor; 4 | 5 | parameter BoardAdaptor = 0; 6 | parameter ClockHigh = 200000000; // 200 MHz 7 | parameter ClockMed = 100000000; // 100 MHz 8 | parameter ClockLow = 50000000; // 50 MHz 9 | // parameter BoardNameLow = 32'h41524554; // "TERA" 10 | // parameter BoardNameHigh = 32'h4E304544; // "DE0N" 11 | parameter BoardNameLow = 32'h4153454D; // "MESA" 12 | parameter BoardNameHigh = 32'h35324935; // "5I25" 13 | parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) 14 | // FIXME: Figure out Mesanet encoding and put something sensible here 15 | parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd 16 | // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os 17 | // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd 18 | parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) 19 | parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth 20 | parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 21 | parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) 22 | parameter LEDCount = 0; // Number of LEDs 23 | parameter SepClocks = "true"; // Deprecated 24 | parameter OneWS = "true"; // Deprecated 25 | parameter BusWidth = 32; 26 | parameter AddrWidth = 16; 27 | 28 | parameter GPIOWidth = 36; 29 | parameter NumGPIO = 2; 30 | parameter MuxGPIOIOWidth = IOWidth/NumGPIO; 31 | parameter MuxLedWidth = LEDCount/NumGPIO; 32 | parameter ADC = "DE0-Nano-SoC"; 33 | parameter Mux_En = 1; 34 | parameter Capsense = 0; 35 | parameter NumSense = 4; 36 | // Capsense Pins: '{.. etc , Sensor1, Sensor0, charge out} // GPIO 0-71 37 | parameter int Capsense_Pins[NumSense:0] = '{ 40, 39, 38, 37, 36 }; 38 | endpackage //_HeaderIncluded 39 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap.sv: -------------------------------------------------------------------------------- 1 | package boardtype; 2 | // DE0-Nano Dev kit and I/O adaptors specific info 3 | // {STRAIGHT=0,DB25=1} BoardAdaptor; 4 | 5 | parameter BoardAdaptor = 0; 6 | parameter ClockHigh = 200000000; // 200 MHz 7 | parameter ClockMed = 100000000; // 100 MHz 8 | parameter ClockLow = 50000000; // 50 MHz 9 | // parameter BoardNameLow = 32'h41524554; // "TERA" 10 | // parameter BoardNameHigh = 32'h4E304544; // "DE0N" 11 | parameter BoardNameLow = 32'h4153454D; // "MESA" 12 | parameter BoardNameHigh = 32'h35324935; // "5I25" 13 | parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) 14 | // FIXME: Figure out Mesanet encoding and put something sensible here 15 | parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd 16 | // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os 17 | // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd 18 | parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) 19 | parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth 20 | parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 21 | parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) 22 | parameter LEDCount = 0; // Number of LEDs 23 | parameter SepClocks = "true"; // Deprecated 24 | parameter OneWS = "true"; // Deprecated 25 | parameter BusWidth = 32; 26 | parameter AddrWidth = 16; 27 | 28 | parameter GPIOWidth = 36; 29 | parameter NumGPIO = 2; 30 | parameter MuxGPIOIOWidth = IOWidth/NumGPIO; 31 | parameter MuxLedWidth = LEDCount/NumGPIO; 32 | parameter ADC = "DE0-Nano-SoC"; 33 | parameter Mux_En = 1; 34 | parameter Capsense = 1; 35 | parameter NumSense = 4; 36 | // Capsense Pins: '{.. etc , Sensor1, Sensor0, charge out} // GPIO 0-71 37 | parameter int Capsense_Pins[NumSense:0] = '{ 40, 39, 38, 37, 36 }; 38 | endpackage //_HeaderIncluded 39 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc.sv: -------------------------------------------------------------------------------- 1 | package boardtype; 2 | // DE0-Nano Dev kit and I/O adaptors specific info 3 | // {STRAIGHT=0,DB25=1} BoardAdaptor; 4 | 5 | parameter BoardAdaptor = 0; 6 | parameter ClockHigh = 200000000; // 200 MHz 7 | parameter ClockMed = 100000000; // 100 MHz 8 | parameter ClockLow = 50000000; // 50 MHz 9 | // parameter BoardNameLow = 32'h41524554; // "TERA" 10 | // parameter BoardNameHigh = 32'h4E304544; // "DE0N" 11 | parameter BoardNameLow = 32'h4153454D; // "MESA" 12 | parameter BoardNameHigh = 32'h35324935; // "5I25" 13 | parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) 14 | // FIXME: Figure out Mesanet encoding and put something sensible here 15 | parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd 16 | // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os 17 | // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd 18 | parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) 19 | parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth 20 | parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 21 | parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) 22 | parameter LEDCount = 0; // Number of LEDs 23 | parameter SepClocks = "true"; // Deprecated 24 | parameter OneWS = "true"; // Deprecated 25 | parameter BusWidth = 32; 26 | parameter AddrWidth = 16; 27 | 28 | parameter GPIOWidth = 36; 29 | parameter NumGPIO = 2; 30 | parameter MuxGPIOIOWidth = IOWidth/NumGPIO; 31 | parameter MuxLedWidth = LEDCount/NumGPIO; 32 | parameter ADC = "DE0-Nano-SoC"; 33 | parameter Mux_En = 1; 34 | parameter Capsense = 1; 35 | parameter NumSense = 4; 36 | // Capsense Pins: '{.. etc , Sensor1, Sensor0, charge out} // GPIO 0-71 37 | parameter int Capsense_Pins[NumSense:0] = '{ 40, 39, 38, 37, 36 }; 38 | endpackage //_HeaderIncluded 39 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_bspi.sv: -------------------------------------------------------------------------------- 1 | package boardtype; 2 | // DE0-Nano Dev kit and I/O adaptors specific info 3 | // {STRAIGHT=0,DB25=1} BoardAdaptor; 4 | 5 | parameter BoardAdaptor = 0; 6 | parameter ClockHigh = 200000000; // 200 MHz 7 | parameter ClockMed = 100000000; // 100 MHz 8 | parameter ClockLow = 50000000; // 50 MHz 9 | // parameter BoardNameLow = 32'h41524554; // "TERA" 10 | // parameter BoardNameHigh = 32'h4E304544; // "DE0N" 11 | parameter BoardNameLow = 32'h4153454D; // "MESA" 12 | parameter BoardNameHigh = 32'h35324935; // "5I25" 13 | parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) 14 | // FIXME: Figure out Mesanet encoding and put something sensible here 15 | parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd 16 | // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os 17 | // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd 18 | parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) 19 | parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth 20 | parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 21 | parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) 22 | parameter LEDCount = 0; // Number of LEDs 23 | parameter SepClocks = "true"; // Deprecated 24 | parameter OneWS = "true"; // Deprecated 25 | parameter BusWidth = 32; 26 | parameter AddrWidth = 16; 27 | 28 | parameter GPIOWidth = 36; 29 | parameter NumGPIO = 2; 30 | parameter MuxGPIOIOWidth = IOWidth/NumGPIO; 31 | parameter MuxLedWidth = LEDCount/NumGPIO; 32 | parameter ADC = "DE0-Nano-SoC"; 33 | parameter Mux_En = 1; 34 | parameter Capsense = 1; 35 | parameter NumSense = 4; 36 | // Capsense Pins: '{.. etc , Sensor1, Sensor0, charge out} // GPIO 0-71 37 | parameter int Capsense_Pins[NumSense:0] = '{ 40, 39, 38, 37, 36 }; 38 | endpackage //_HeaderIncluded 39 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_dbspi.sv: -------------------------------------------------------------------------------- 1 | package boardtype; 2 | // DE0-Nano Dev kit and I/O adaptors specific info 3 | // {STRAIGHT=0,DB25=1} BoardAdaptor; 4 | 5 | parameter BoardAdaptor = 0; 6 | parameter ClockHigh = 200000000; // 200 MHz 7 | parameter ClockMed = 100000000; // 100 MHz 8 | parameter ClockLow = 50000000; // 50 MHz 9 | // parameter BoardNameLow = 32'h41524554; // "TERA" 10 | // parameter BoardNameHigh = 32'h4E304544; // "DE0N" 11 | parameter BoardNameLow = 32'h4153454D; // "MESA" 12 | parameter BoardNameHigh = 32'h35324935; // "5I25" 13 | parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) 14 | // FIXME: Figure out Mesanet encoding and put something sensible here 15 | parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd 16 | // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os 17 | // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd 18 | parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) 19 | parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth 20 | parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 21 | parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) 22 | parameter LEDCount = 0; // Number of LEDs 23 | parameter SepClocks = "true"; // Deprecated 24 | parameter OneWS = "true"; // Deprecated 25 | parameter BusWidth = 32; 26 | parameter AddrWidth = 16; 27 | 28 | parameter GPIOWidth = 36; 29 | parameter NumGPIO = 2; 30 | parameter MuxGPIOIOWidth = IOWidth/NumGPIO; 31 | parameter MuxLedWidth = LEDCount/NumGPIO; 32 | parameter ADC = "DE0-Nano-SoC"; 33 | parameter Mux_En = 1; 34 | parameter Capsense = 1; 35 | parameter NumSense = 4; 36 | // Capsense Pins: '{.. etc , Sensor1, Sensor0, charge out} // GPIO 0-71 37 | parameter int Capsense_Pins[NumSense:0] = '{ 40, 39, 38, 37, 36 }; 38 | endpackage //_HeaderIncluded 39 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_st_fpga_soc_dc1G.sv: -------------------------------------------------------------------------------- 1 | package boardtype; 2 | // DE0-Nano Dev kit and I/O adaptors specific info 3 | // {STRAIGHT=0,DB25=1} BoardAdaptor; 4 | 5 | parameter BoardAdaptor = 0; 6 | parameter ClockHigh = 200000000; // 200 MHz 7 | parameter ClockMed = 100000000; // 100 MHz 8 | parameter ClockLow = 50000000; // 50 MHz 9 | // parameter BoardNameLow = 32'h41524554; // "TERA" 10 | // parameter BoardNameHigh = 32'h4E304544; // "DE0N" 11 | parameter BoardNameLow = 32'h4153454D; // "MESA" 12 | parameter BoardNameHigh = 32'h35324935; // "5I25" 13 | parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) 14 | // FIXME: Figure out Mesanet encoding and put something sensible here 15 | parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd 16 | // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os 17 | // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd 18 | parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) 19 | parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth 20 | parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 21 | parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) 22 | parameter LEDCount = 0; // Number of LEDs 23 | parameter SepClocks = "true"; // Deprecated 24 | parameter OneWS = "true"; // Deprecated 25 | parameter BusWidth = 32; 26 | parameter AddrWidth = 16; 27 | 28 | parameter GPIOWidth = 36; 29 | parameter NumGPIO = 2; 30 | parameter MuxGPIOIOWidth = IOWidth/NumGPIO; 31 | parameter MuxLedWidth = LEDCount/NumGPIO; 32 | parameter ADC = "DE0-Nano-SoC"; 33 | parameter Mux_En = 0; 34 | parameter Capsense = 0; 35 | parameter NumSense = 4; 36 | // Capsense Pins: '{.. etc , Sensor1, Sensor0, charge out} // GPIO 0-71 37 | parameter int Capsense_Pins[NumSense:0] = '{ 40, 39, 38, 37, 36 }; 38 | endpackage //_HeaderIncluded 39 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_st_fpga_soc_dc1f_ss.sv: -------------------------------------------------------------------------------- 1 | package boardtype; 2 | // DE0-Nano Dev kit and I/O adaptors specific info 3 | // {STRAIGHT=0,DB25=1} BoardAdaptor; 4 | 5 | parameter BoardAdaptor = 0; 6 | parameter ClockHigh = 200000000; // 200 MHz 7 | parameter ClockMed = 100000000; // 100 MHz 8 | parameter ClockLow = 50000000; // 50 MHz 9 | // parameter BoardNameLow = 32'h41524554; // "TERA" 10 | // parameter BoardNameHigh = 32'h4E304544; // "DE0N" 11 | parameter BoardNameLow = 32'h4153454D; // "MESA" 12 | parameter BoardNameHigh = 32'h35324935; // "5I25" 13 | parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) 14 | // FIXME: Figure out Mesanet encoding and put something sensible here 15 | parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd 16 | // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os 17 | // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd 18 | parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) 19 | parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth 20 | parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 21 | parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) 22 | parameter LEDCount = 0; // Number of LEDs 23 | parameter SepClocks = "true"; // Deprecated 24 | parameter OneWS = "true"; // Deprecated 25 | parameter BusWidth = 32; 26 | parameter AddrWidth = 16; 27 | 28 | parameter GPIOWidth = 36; 29 | parameter NumGPIO = 2; 30 | parameter MuxGPIOIOWidth = IOWidth/NumGPIO; 31 | parameter MuxLedWidth = LEDCount/NumGPIO; 32 | parameter ADC = "DE0-Nano-SoC"; 33 | parameter Mux_En = 0; 34 | parameter Capsense = 0; 35 | parameter NumSense = 4; 36 | // Capsense Pins: '{.. etc , Sensor1, Sensor0, charge out} // GPIO 0-71 37 | parameter int Capsense_Pins[NumSense:0] = '{ 40, 39, 38, 37, 36 }; 38 | endpackage //_HeaderIncluded 39 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/hm3_DExx_Nano_xxx_Cramps.in: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE ../../hm2/config/DExx_Nano_xxx_Cramps/hostmot3_cfg.vhd 2 | set_global_assignment -name SYSTEMVERILOG_FILE ../../hm2/config/DExx_Nano_xxx_Cramps/atlas_%CONFIG%.sv 3 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/hm3_pin_config.in: -------------------------------------------------------------------------------- 1 | # I/O Daughterboard adaptor specific: 2 | set_global_assignment -name VHDL_FILE ../../hm2/config/DExx_Nano_xxx_Cramps/PIN_%CONFIG%.vhd -library pin 3 | -------------------------------------------------------------------------------- /HW/hm2/config/DExx_Nano_xxx_Cramps/readme.md: -------------------------------------------------------------------------------- 1 | Shared configs for the DE0_Nano_SoC_Cramps and DE10_Nano_FB_Cramps projects 2 | The DExx ..._Cramps projects are minimalistic as only the hm2 cores in current configs are included. 3 | 4 | A new config is added by creating and then editing a new copy of these 2 files. 5 | 6 | PIN_(your-custom-name).vhd 7 | atlas_(your-custom-name).sv 8 | 9 | If you wish to create a new config including a not yet (in current configs) included core, 10 | post a DExx_.._Cramps new core feature request. (in the GGroup). 11 | -------------------------------------------------------------------------------- /HW/hm2/config/hm2_i25_G540x2_34_config.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name VHDL_FILE ../../hm2/config/i25_x9card.vhd 3 | set_global_assignment -name VHDL_FILE ../../hm2/config/IDROMConst.vhd 4 | set_global_assignment -name VHDL_FILE ../../hm2/config/PIN_G540x2_34.vhd 5 | -------------------------------------------------------------------------------- /HW/hm2/config/hm2_i25_G540x2_34_irq_config.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name VHDL_FILE ../../hm2/config/i25_x9card.vhd 3 | set_global_assignment -name VHDL_FILE ../../hm2/config/IDROMConst.vhd 4 | set_global_assignment -name VHDL_FILE ../../hm2/config/PIN_G540x2_34_irq.vhd 5 | -------------------------------------------------------------------------------- /HW/hm2/drqlogic.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.STD_LOGIC_ARITH.ALL; 5 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 6 | 7 | 8 | entity dmdrqlogic is 9 | generic ( 10 | ndrqs : integer ); 11 | port ( clk : in std_logic; 12 | ibus : in std_logic_vector (31 downto 0); 13 | obus : out std_logic_vector (31 downto 0); 14 | loadmode : in std_logic; 15 | readmode : in std_logic; 16 | drqsources : in std_logic_vector (ndrqs-1 downto 0); 17 | dreqout : out std_logic; 18 | demandmode : out std_logic); 19 | end dmdrqlogic; 20 | 21 | architecture Behavioral of dmdrqlogic is 22 | constant zeromask: std_logic_vector (ndrqs-1 downto 0) := (others => '0'); 23 | signal modereg: std_logic_vector (31 downto 0); 24 | alias mask: std_logic_vector (ndrqs-1 downto 0) is modereg(ndrqs+15 downto 16); -- 16 max 25 | alias enable: std_logic is modereg(0); 26 | signal drq: std_logic; 27 | begin 28 | admdrq: process(clk,drqsources,readmode,mask, modereg) 29 | begin 30 | if rising_edge(clk) then 31 | if loadmode = '1' then 32 | modereg <= ibus; 33 | end if; 34 | end if; 35 | if (mask and drqsources) /= 0 then 36 | drq <= enable; 37 | else 38 | drq <= '0'; 39 | end if; 40 | demandmode <= enable; 41 | obus <= (others => 'Z'); 42 | if readmode = '1' then 43 | obus(31 downto 16) <= modereg(31 downto 16); 44 | obus(0) <= modereg(0); 45 | obus(1) <= drq; 46 | obus(15 downto 2) <= (others => '0'); 47 | end if; 48 | dreqout <= drq; 49 | end process; 50 | end Behavioral; 51 | 52 | -------------------------------------------------------------------------------- /HW/hm2/functions/hm2_functions.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name VHDL_FILE ../../hm2/functions/PinExists.vhd 3 | set_global_assignment -name VHDL_FILE ../../hm2/functions/oneofndecode.vhd 4 | set_global_assignment -name VHDL_FILE ../../hm2/functions/NumberOfModules.vhd 5 | set_global_assignment -name VHDL_FILE ../../hm2/functions/ModuleExists.vhd 6 | set_global_assignment -name VHDL_FILE ../../hm2/functions/MaxPinsPerModule.vhd 7 | set_global_assignment -name VHDL_FILE ../../hm2/functions/MaxOutputPinsPerModule.vhd 8 | set_global_assignment -name VHDL_FILE ../../hm2/functions/MaxIOPinsPerModule.vhd 9 | set_global_assignment -name VHDL_FILE ../../hm2/functions/MaxInputPinsPerModule.vhd 10 | set_global_assignment -name VHDL_FILE ../../hm2/functions/log2.vhd 11 | set_global_assignment -name VHDL_FILE ../../hm2/functions/InputPinsPerModule.vhd 12 | set_global_assignment -name VHDL_FILE ../../hm2/functions/decodedstrobe.vhd 13 | set_global_assignment -name VHDL_FILE ../../hm2/functions/CountPinsInRange.vhd 14 | 15 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | node_modules 3 | 4 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/.npmignore: -------------------------------------------------------------------------------- 1 | * 2 | !js 3 | !build/js/** 4 | !package.json 5 | !README* 6 | !LICENSE* 7 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2014 Michael Haberler 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/dist/README.md: -------------------------------------------------------------------------------- 1 | Distributions 2 | ============= 3 | 4 | machinetalk-protobuf.js is available either only with ProtoBuf.js included. 5 | 6 | ### Full build including ProtoBuf.js 7 | 8 | * **[machinetalk-protobuf.js](https://raw.githubusercontent.com/machinekit/machinetalk-protobuf/master/dist/machinetalk-protobuf.js)** 9 | contains the commented source code. 10 | 11 | * **[machinetalk-protobuf.min.js](https://raw.githubusercontent.com/machinekit/machinetalk-protobuf/master/dist/machinetalk-protobuf.min.js)** 12 | has been compiled with Closure Compiler. 13 | 14 | * **[machinetalk-protobuf.min.js.gz](https://raw.githubusercontent.com/machinekit/machinetalk-protobuf/master/dist/machinetalk-protobuf.min.js.gz)** 15 | has also been gzipped using `-9`. 16 | 17 | * **[machinetalk-protobuf.min.map](https://raw.githubusercontent.com/machinekit/machinetalk-protobuf/master/dist/machinetalk-protobuf.min.map)** 18 | is the source map generated by Closure Compiler. 19 | 20 | When sending pull requests, please note that these files have been automatically generated from the sources located in 21 | [src/](https://github.com/machinekit/machinekit-protobuf/tree/master/src). 22 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/dist/machinetalk-protobuf.min.js.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/HW/machinetalk-protobuf/dist/machinetalk-protobuf.min.js.gz -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/js/examples/decoding_message_container.js: -------------------------------------------------------------------------------- 1 | var machinetalkProtobuf = require('../index.js'); 2 | 3 | var encodedBuffer = new Buffer([0x08, 0xd2, 0x01]); 4 | 5 | // Decode the message. 6 | var decodedMessageContainer = machinetalkProtobuf.message.Container.decode(encodedBuffer); 7 | 8 | // decodedMessageContainer.type === machinetalkProtobuf.message.ContainerType.MT_PING 9 | console.log(decodedMessageContainer); 10 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/js/examples/encoding_message_container.js: -------------------------------------------------------------------------------- 1 | var machinetalkProtobuf = require('../index.js'); 2 | 3 | // Define the message we want to encode. 4 | var messageContainer = { 5 | type: machinetalkProtobuf.message.ContainerType.MT_PING 6 | }; 7 | 8 | // Encode the message. 9 | var encodedMessageContainer = machinetalkProtobuf.message.Container.encode(messageContainer); 10 | 11 | // Strip off excess bytes from the resulting buffer. 12 | var encodedBuffer = encodedMessageContainer.buffer.slice(encodedMessageContainer.offset, encodedMessageContainer.limit); 13 | 14 | // Print the buffer. 15 | console.log(encodedBuffer); -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/js/index.js: -------------------------------------------------------------------------------- 1 | module.exports = require('../build/js/protoexport.js'); 2 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/js/scripts/bundle.js: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env node 2 | var path = require('path'); 3 | var fs = require('fs'); 4 | var mkdirp = require('mkdirp'); 5 | var browserify = require('browserify') 6 | var exec = require('child_process').exec; 7 | var destinationPath = path.join(__dirname, '../../dist'); 8 | var inputFile = path.join(__dirname, '../../build/js/protoexport.js'); 9 | 10 | function makeBundle() { 11 | var bundler = new browserify({standalone: 'machinetalk.protobuf'}); 12 | bundler.add(inputFile); 13 | 14 | bundler.bundle(function (err, src, map) { 15 | if (err) { 16 | console.log('Error:', err); 17 | } 18 | 19 | mkdirp.sync(destinationPath); 20 | fs.writeFileSync(path.join(destinationPath, 'machinetalk-protobuf.js'), src); 21 | 22 | console.log('bundle created'); 23 | }); 24 | } 25 | 26 | function makeMinBundle() { 27 | // As of browserify 5, you must enable debug mode in the constructor to use minifyify 28 | var bundler = new browserify({debug: true, standalone: 'machinetalk.protobuf'}); 29 | bundler.add(inputFile); 30 | bundler.plugin('minifyify', {map: 'machinetalk-protobuf.min.map.json'}); 31 | 32 | bundler.bundle(function (err, src, map) { 33 | if (err) { 34 | console.log('Error:', err); 35 | } 36 | 37 | mkdirp.sync(destinationPath); 38 | fs.writeFileSync(path.join(destinationPath, 'machinetalk-protobuf.min.js'), src); 39 | fs.writeFileSync(path.join(destinationPath, 'machinetalk-protobuf.min.map.json'), map); 40 | 41 | console.log('minified bundle created'); 42 | 43 | makeMinGzBundle(path.join(destinationPath, 'machinetalk-protobuf.min.js')); 44 | }); 45 | } 46 | 47 | function makeMinGzBundle(file) { 48 | var cmd = 'gzip -k -f -9 ' + file; 49 | 50 | exec(cmd, function(err, stdout, stderr) { 51 | if (err) { 52 | console.log('Error:', err); 53 | } 54 | 55 | console.log('Gzipped bundle created'); 56 | }); 57 | } 58 | 59 | makeBundle(); 60 | makeMinBundle(); 61 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/js/scripts/install.js: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env node 2 | var path = require('path'); 3 | var fs = require('fs'); 4 | var mkdirp = require('mkdirp'); 5 | var child_process = require('child_process'); 6 | var sourcePath = path.join(__dirname, '/../../src'); 7 | var destinationPath = path.join(__dirname, '/../../build/js'); 8 | 9 | var namespace = 'machinetalk/protobuf'; 10 | 11 | // Create list of information for protobuf files. 12 | var protos = fs.readdirSync(path.join(sourcePath, namespace)) 13 | .filter(function(filename) { 14 | // Only handle .proto files. 15 | return /\.proto$/.test(filename); 16 | }) 17 | .map(function(filename) { 18 | var name = path.basename(filename, '.proto'); 19 | var fullname = path.join(namespace, name); 20 | return { 21 | filename: filename, 22 | name: name, 23 | fullname: fullname, 24 | protopath: path.join(sourcePath, namespace, filename), 25 | jspath: path.join(destinationPath, namespace, name + '.js') 26 | }; 27 | }); 28 | 29 | // Generate js file for each proto file 30 | protos.forEach(function(protos) { 31 | mkdirp.sync(path.dirname(protos.jspath)); 32 | child_process.execFileSync('pbjs', ['--target', 'commonjs', '--out', protos.jspath, '--path', sourcePath, protos.protopath]); 33 | }); 34 | 35 | 36 | // Generate json file to direct index.js to the generated js files. 37 | var protosjson = protos.map(function(proto) { 38 | return { 39 | name: proto.name, 40 | fullname: proto.fullname 41 | }; 42 | }); 43 | 44 | mkdirp.sync(destinationPath); 45 | var text = ''; 46 | protosjson.forEach(function(proto) { 47 | text += 'module.exports[\'' + proto.name + '\'] = require(\'./' + proto.fullname + '.js\').pb;\n'; 48 | }); 49 | fs.writeFileSync(path.join(destinationPath, 'protoexport.js'), text); 50 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/package.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "machinetalk-protobuf", 3 | "version": "1.0.1", 4 | "description": "Protobuf definitions to communicate with Machinetalk", 5 | "main": "js/index.js", 6 | "scripts": { 7 | "prepublish": "js/scripts/install.js", 8 | "bundle": "js/scripts/bundle.js" 9 | }, 10 | "repository": { 11 | "type": "git", 12 | "url": "git+https://github.com/machinekit/machinetalk-protobuf.git" 13 | }, 14 | "author": "Bob van der Linden ", 15 | "keywords": [ 16 | "machinetalk", 17 | "machinekit", 18 | "protobuf" 19 | ], 20 | "license": "MIT", 21 | "bugs": { 22 | "url": "https://github.com/machinekit/machinetalk-protobuf/issues" 23 | }, 24 | "homepage": "https://github.com/machinekit/machinetalk-protobuf#readme", 25 | "dependencies": { 26 | "mkdirp": "0.5.1", 27 | "protobufjs": "6.8.8" 28 | }, 29 | "devDependencies": { 30 | "browserify": "^13.0.0", 31 | "minifyify": "^7.1.0" 32 | } 33 | } 34 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/python/examples/decode_message_container.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.message_pb2 import Container 2 | from machinetalk.protobuf.types_pb2 import * 3 | 4 | encodedBuffer = ''.join(chr(x) for x in [0x08, 0xd2, 0x01]) 5 | 6 | # create the message container, reuse is more efficient 7 | rx = Container() 8 | 9 | # parse the encoded message 10 | rx.ParseFromString(encodedBuffer) 11 | 12 | # print the decoded message 13 | print(rx) 14 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/python/examples/encode_message_container.py: -------------------------------------------------------------------------------- 1 | from machinetalk.protobuf.message_pb2 import Container 2 | from machinetalk.protobuf.types_pb2 import * 3 | 4 | # create the message container, reuse is more efficient 5 | tx = Container() 6 | 7 | # define the message 8 | tx.Clear() 9 | tx.type = MT_PING 10 | 11 | # encode the message 12 | encodedBuffer = tx.SerializeToString() 13 | 14 | # print the buffer 15 | print(encodedBuffer) 16 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/python/machinetalk/__init__.py: -------------------------------------------------------------------------------- 1 | __import__('pkg_resources').declare_namespace(__name__) -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/python/machinetalk/protobuf/__init__.py: -------------------------------------------------------------------------------- 1 | __import__('pkg_resources').declare_namespace(__name__) -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/scripts/asciidoc.mustache: -------------------------------------------------------------------------------- 1 | = Machinetalk Protobuf Documentation 2 | :toc: 3 | 4 | {{#files}} 5 | 6 | == {{file_name}} 7 | 8 | {{#file_description}}{{file_description}}{{/file_description}} 9 | 10 | {{#file_messages}} 11 | 12 | === {{message_long_name}} 13 | {{message_description}} 14 | 15 | |=========================================== 16 | |*Field* |*Type* |*Label* |*Description* 17 | {{#message_fields}} 18 | |{{field_name}} | <<{{field_long_type}},{{field_long_type}}>> |{{field_label}} |{{#nobr}}{{field_description}}{{/nobr}} 19 | {{/message_fields}} 20 | |=========================================== 21 | {{/file_messages}} 22 | 23 | {{#file_enums}} 24 | 25 | [[{{enum_long_name}}]] 26 | === {{enum_long_name}} 27 | {{enum_description}} 28 | 29 | |===================================== 30 | |*Name* |*Number* |*Description* 31 | {{#enum_values}} 32 | |{{value_name}} |{{value_number}} |{{#nobr}}{{value_description}}{{/nobr}} 33 | {{/enum_values}} 34 | |===================================== 35 | {{/file_enums}} 36 | {{/files}} 37 | 38 | == Scalar Value Types 39 | 40 | |============================================================== 41 | |*.proto Type* |*Notes* |*C++ Type* |*Java Type* |*Python Type* 42 | {{#scalar_value_types}} 43 | |[[{{scalar_value_proto_type}}]] ((({{scalar_value_proto_type}}))) {{scalar_value_proto_type}} |{{scalar_value_notes}} |{{scalar_value_cpp_type}} |{{scalar_value_java_type}} |{{scalar_value_python_type}} 44 | {{/scalar_value_types}} 45 | |============================================================== 46 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/scripts/ios-replace.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # Replace "namespace google" with "namespace google_public" 3 | # in all source/header files. This is to address a 4 | # namespace collision issue when building for recent 5 | # versions of iOS. Apple is using the protobuf library 6 | # internally, and embeds it as a private framework. 7 | ############################################################### 8 | 9 | ( 10 | echo "------------------ Fixup namespace --------------------" 11 | cd $1 12 | sed -i '' -e 's/namespace\ google /namespace\ google_public /g' $(find . -name \*.h -type f) 13 | sed -i '' -e 's/namespace\ google /namespace\ google_public /g' $(find . -name \*.cc -type f) 14 | sed -i '' -e 's/namespace\ google /namespace\ google_public /g' $(find . -name \*.proto -type f) 15 | sed -i '' -e 's/google::protobuf/google_public::protobuf/g' $(find . -name \*.h -type f) 16 | sed -i '' -e 's/google::protobuf/google_public::protobuf/g' $(find . -name \*.cc -type f) 17 | sed -i '' -e 's/google::protobuf/google_public::protobuf/g' $(find . -name \*.proto -type f) 18 | ) 19 | 20 | exit 0 21 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/scripts/markdown.mustache: -------------------------------------------------------------------------------- 1 | # Protocol Documentation 2 | 3 | 4 | ## Table of Contents 5 | {{#files}} 6 | * [{{file_name}}](#{{file_name}}) 7 | {{#file_messages}} 8 | * [{{message_long_name}}](#{{message_full_name}}) 9 | {{/file_messages}} 10 | {{#file_enums}} 11 | * [{{enum_long_name}}](#{{enum_full_name}}) 12 | {{/file_enums}} 13 | {{/files}} 14 | * [Scalar Value Types](#scalar-value-types) 15 | 16 | {{#files}} 17 | 18 |

Top

19 | 20 | ## {{file_name}} 21 | 22 | {{#file_messages}} 23 | 24 | ### {{message_long_name}} 25 | {{message_description}} 26 | 27 | | Field | Type | Label | Description | 28 | | ----- | ---- | ----- | ----------- | 29 | {{#message_fields}} 30 | | {{field_name}} | [{{field_long_type}}](#{{field_full_type}}) | {{field_label}} | {{#nobr}}{{field_description}}{{/nobr}} | 31 | {{/message_fields}} 32 | 33 | {{/file_messages}} 34 | 35 | {{#file_enums}} 36 | 37 | ### {{enum_long_name}} 38 | {{enum_description}} 39 | 40 | | Name | Number | Description | 41 | | ---- | ------ | ----------- | 42 | {{#enum_values}} 43 | | {{value_name}} | {{value_number}} | {{#nobr}}{{value_description}}{{/nobr}} | 44 | {{/enum_values}} 45 | 46 | {{/file_enums}} 47 | {{/files}} 48 | 49 | 50 | ## Scalar Value Types 51 | 52 | | .proto Type | Notes | C++ Type | Java Type | Python Type | 53 | | ----------- | ----- | -------- | --------- | ----------- | 54 | {{#scalar_value_types}} 55 | | {{scalar_value_proto_type}} | {{scalar_value_notes}} | {{scalar_value_cpp_type}} | {{scalar_value_java_type}} | {{scalar_value_python_type}} | 56 | {{/scalar_value_types}} 57 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/src/README.msgid: -------------------------------------------------------------------------------- 1 | about message type id's: 2 | ------------------------ 3 | 4 | nanopb upstream (https://code.google.com/p/nanopb/source/list) as of 5 | commit 62a7e4ff2b34 has introduced a key feature: it is now possible 6 | to associate a msgid option with each message, and have those id's 7 | emitted by the nanopb generator such that a descriptor mapping 8 | descriptors, msgid's, names, and other paramters can be automatically 9 | constructed. 10 | 11 | Thus we can associate an integer ID with each message, which is useful 12 | for runtime type checking of messages. There is no runtime overhead for 13 | this option. 14 | 15 | A typical usage scenario would be with multiframe ringbuffers, when 16 | using different protobuf messages: the multiframe flags field holds 17 | the type id, which is used to determine how to actually process the 18 | frame's content. 19 | 20 | msgid's have to be unique across all messages and all proto files. This must be maintained manually. 21 | 22 | The absolute value of the msgid option is irrelevant as it is only used as a key; uniqueness counts. msgid's need not be sequential. 23 | 24 | It is helpful to use message id' less than say a few thousand because 25 | it will be transported in a limited-size field in the multiframe ring 26 | (a uint32_t), and there should be bits available for other purposes 27 | like specifying the encoding (protobuf, or a deserialized nanopb C 28 | struct). 29 | 30 | Convention for adding msgid's: 31 | ------------------------------ 32 | 33 | Since no proto file is expected to reasonable have more than 100 message definitions, each proto file gets a base message id, recorded in a comment on the top of the file: 34 | 35 | e.g. canon.proto: 36 | // msgid base: 100 37 | 38 | config.proto: 39 | // msgid base: 200 40 | 41 | ans so forth. 42 | 43 | To tag a message with a msgid, proceed like so (using canon.proto as example): 44 | 45 | // make sure nanopb.proto is imported as this defines the option 46 | 47 | import "nanopb.proto"; 48 | // msgid base: 100 49 | 50 | // for each message, add the option like so: 51 | message Emc_Traj_Set_G5x { 52 | 53 | option (nanopb_msgopt).msgid = 101; // assign sequentially for all messages 54 | 55 | required EmcPose origin = 10; 56 | required OriginIndex g5x_index = 20; 57 | } 58 | 59 | 60 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/src/machinetalk/protobuf/emcclass.proto: -------------------------------------------------------------------------------- 1 | import "machinetalk/protobuf/nanopb.proto"; 2 | 3 | // see README.msgid 4 | // msgid base: 300 5 | 6 | package pb; 7 | 8 | // this encoding method of encoding supports NULL values 9 | // using code needs to inspect the has_ property 10 | // to discern whether a value was explicitly set or defaulted 11 | 12 | message PmCartesian { 13 | 14 | option (nanopb_msgopt).msgid = 300; // see README.msgid 15 | 16 | optional double x = 10; 17 | optional double y = 20; 18 | optional double z = 30; 19 | }; 20 | 21 | message EmcPose { 22 | 23 | option (nanopb_msgopt).msgid = 301; 24 | 25 | required PmCartesian tran = 10; 26 | 27 | optional double a = 20; 28 | optional double b = 30; 29 | optional double c = 40; 30 | optional double u = 50; 31 | optional double v = 60; 32 | optional double w = 70; 33 | }; 34 | 35 | // this encoding method requires all fields to be set 36 | // or serialisation fails; NULL values not supported: 37 | 38 | // message PmCartesian { 39 | // required double x = 10; 40 | // required double y = 20; 41 | // required double z = 30; 42 | // }; 43 | 44 | // message EmcPose { 45 | // required PmCartesian tran = 10; 46 | 47 | // required double a = 20; 48 | // required double b = 30; 49 | // required double c = 40; 50 | // required double u = 50; 51 | // required double v = 60; 52 | // required double w = 70; 53 | // }; -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/src/machinetalk/protobuf/firmware.proto: -------------------------------------------------------------------------------- 1 | /** firmware descriptor for hostmot2 2 | The message Firmware encodes the detail which used to be hardcoded in the low-level hostmot2 driver 3 | in the struct hm2_lowlevel_io_struct. 4 | It is placed in the firmware at a well-known location including a length field. 5 | The lowlevel driver decodes this message, and calls hm2_register() accordingly. 6 | */ 7 | 8 | // the nanopb import, plus the nanopb max_size/max_count options are not 9 | // strictly needed but together they result in a fixed-size C struct 10 | // representing the decoded message in nanopb 11 | // see the resulting typedefs _pb_Connector and _pb_Firmware in 12 | // src/machinetalk/generated/firmware.npb.h 13 | // this makes the struct easier to work with in RT (decoding without 14 | // callbacks and malloc()) 15 | 16 | import "machinetalk/protobuf/nanopb.proto"; 17 | 18 | // see README.msgid 19 | // msgid base: 380 20 | 21 | package pb; 22 | 23 | /// describes a connector 24 | message Connector { 25 | /// @exclude 26 | option (nanopb_msgopt).msgid = 380; 27 | 28 | /// will appear in the HAL name 29 | optional string name = 1 [(nanopb).max_size = 20]; 30 | /// number of pins 31 | optional sfixed32 pins = 2; 32 | } 33 | 34 | message Firmware { 35 | /// @exclude 36 | option (nanopb_msgopt).msgid = 385; 37 | /// the machinekit/socfpga build SHA 38 | optional string build_sha = 1 [(nanopb).max_size = 40]; 39 | /// sets hm2_lowlevel_io_struct.fpga_part_number 40 | optional string fpga_part_number = 2 [(nanopb).max_size = 20]; 41 | /// sets hm2_lowlevel_io_struct.num_ioport_connectors, ioport_connector_name, pins_per_connector 42 | repeated Connector connector = 3 [(nanopb).max_count = 16]; 43 | /// sets hm2_lowlevel_io_struct.num_leds 44 | optional sfixed32 num_leds = 4; 45 | /// sets hm2_lowlevel_io_struct.num_leds 46 | optional string board_name = 5 [(nanopb).max_size = 30]; 47 | /// descriptive text, uninterpreted - use for log message if present 48 | optional string comment = 6 [(nanopb).max_size = 80]; 49 | } 50 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/src/machinetalk/protobuf/log.proto: -------------------------------------------------------------------------------- 1 | package pb; 2 | // see README.msgid 3 | // msgid base: 400 4 | 5 | import "machinetalk/protobuf/nanopb.proto"; 6 | import "machinetalk/protobuf/types.proto"; 7 | 8 | message LogMessage { 9 | 10 | option (nanopb_msgopt).msgid = 400; // see README.msgid 11 | 12 | required MsgOrigin origin = 10; 13 | required int32 pid = 20; 14 | required MsgLevel level = 30; 15 | required string tag = 40; // [(nanopb).max_size = 20]; 16 | required string text = 50; // [(nanopb).max_size = 100]; 17 | } 18 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/src/machinetalk/protobuf/rtapi_message.proto: -------------------------------------------------------------------------------- 1 | import "machinetalk/protobuf/nanopb.proto"; 2 | import "machinetalk/protobuf/value.proto"; 3 | 4 | // see README.msgid 5 | // msgid base: 1000 6 | 7 | package pb; 8 | 9 | message RTAPI_Message { 10 | 11 | option (nanopb_msgopt).msgid = 1000; // see README.msgid 12 | 13 | 14 | required int32 msglevel = 10; // [default = RTAPI_MSG_DBG]; 15 | 16 | required string format = 20 [default = "*** uninitialized ***", 17 | (nanopb).max_size = 100]; 18 | 19 | // if this list of scalars is non-empty, 20 | // this implies sprintf(text, ) should be applied 21 | // before display 22 | repeated Value arg = 30 [(nanopb).max_count = 10]; 23 | } 24 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/src/machinetalk/protobuf/rtapicommand.proto: -------------------------------------------------------------------------------- 1 | import "machinetalk/protobuf/nanopb.proto"; 2 | // see README.msgid 3 | // msgid base: 900 4 | 5 | package pb; 6 | 7 | message RTAPICommand { 8 | 9 | option (nanopb_msgopt).msgid = 900; // see README.msgid 10 | 11 | 12 | required int32 instance = 1; 13 | optional string modname = 2; 14 | optional int32 rt_msglevel = 3; 15 | optional int32 user_msglevel = 4; 16 | 17 | // string argv-type vector; used in MT_RTAPI_APP_* and possibly others 18 | repeated string argv = 5; 19 | 20 | optional string threadname = 6; 21 | optional int32 threadperiod = 7; 22 | optional bool use_fp = 8; 23 | optional int32 cpu = 9; 24 | 25 | optional string comp = 10; 26 | optional string func = 11; 27 | optional string instname = 12; 28 | optional int32 flags = 13; 29 | 30 | } 31 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/src/machinetalk/protobuf/test.proto: -------------------------------------------------------------------------------- 1 | // use any of the below for testing and experimentation. 2 | 3 | import "machinetalk/protobuf/emcclass.proto"; 4 | import "machinetalk/protobuf/nanopb.proto"; 5 | 6 | package pb; 7 | 8 | // see README.msgid 9 | // msgid base: 1300 10 | 11 | enum TestOpType { 12 | LINE = 10; 13 | CIRCLE = 20; 14 | }; 15 | 16 | 17 | message Test1 { 18 | 19 | option (nanopb_msgopt).msgid = 1300; // see README.msgid 20 | 21 | // minimum params to encode line or circle 22 | required TestOpType op = 10; 23 | required EmcPose end = 20; 24 | optional PmCartesian center = 30; 25 | optional PmCartesian normal = 40; 26 | optional int32 turn = 50; 27 | } 28 | 29 | 30 | message Test2 { 31 | 32 | option (nanopb_msgopt).msgid = 1301; 33 | 34 | } 35 | 36 | 37 | message Test3 { 38 | 39 | option (nanopb_msgopt).msgid = 1302; 40 | 41 | } 42 | -------------------------------------------------------------------------------- /HW/machinetalk-protobuf/src/machinetalk/protobuf/value.proto: -------------------------------------------------------------------------------- 1 | import "machinetalk/protobuf/nanopb.proto"; 2 | 3 | import "machinetalk/protobuf/emcclass.proto"; 4 | import "machinetalk/protobuf/types.proto"; 5 | 6 | // see README.msgid 7 | // msgid base: 1500 8 | 9 | package pb; 10 | 11 | 12 | // a value for 'passing around'. 13 | 14 | message Value { 15 | option (nanopb_msgopt).msgid = 1500; // see README.msgid 16 | 17 | required ValueType type = 10; 18 | // actual values 19 | 20 | // One of the following must be filled in, 21 | // depending on type. 22 | 23 | // scalars 24 | optional bool halbit = 100; 25 | optional double halfloat = 101; 26 | optional sfixed32 hals32 = 102; 27 | optional fixed32 halu32 = 103; 28 | 29 | optional bytes v_bytes = 120; 30 | optional sfixed32 v_int32 = 130; 31 | optional sfixed64 v_int64 = 140; 32 | optional fixed32 v_uint32 = 150; 33 | optional fixed64 v_uint64 = 160; 34 | optional double v_double = 170; 35 | optional string v_string = 180 [(nanopb).max_size = 41]; 36 | optional bool v_bool = 190; 37 | 38 | // compound types 39 | optional PmCartesian carte = 200; 40 | optional EmcPose pose = 220; 41 | } 42 | -------------------------------------------------------------------------------- /HW/zynq-ip/.gitignore: -------------------------------------------------------------------------------- 1 | /tmp* 2 | /*/tmp* 3 | /*.zip 4 | /*/*.zip 5 | -------------------------------------------------------------------------------- /HW/zynq-ip/btint_axi_1.0/src/pkt_builder_tx_tb.vhd: -------------------------------------------------------------------------------- 1 | -- A simple test bench for the packet building component 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity pkt_builder_tx_tb is 7 | generic ( 8 | BAUD_TIMER_WIDTH : natural := 16 9 | ); 10 | end pkt_builder_tx_tb; 11 | 12 | architecture beh of pkt_builder_tx_tb is 13 | signal clk : std_logic := '0'; 14 | signal rst_n : std_logic := '1'; 15 | signal baudreg : unsigned(BAUD_TIMER_WIDTH - 1 downto 0); 16 | signal uart_busy : std_logic; 17 | signal uart_data : std_logic_vector(7 downto 0) := (others => '0'); 18 | signal uart_load : std_logic := '0'; 19 | signal uart_tx : std_logic; 20 | signal pkt_packet : std_logic_vector(31 downto 0); 21 | signal pkt_we : std_logic := '0'; 22 | signal pkt_busy : std_logic; 23 | 24 | -- Simulation timing 25 | constant clockperiod : TIME := 10 ns; 26 | begin 27 | UUT : entity work.pkt_builder_tx 28 | port map ( 29 | rst_n => rst_n, 30 | clk => clk, 31 | packet => pkt_packet, 32 | we => pkt_we, 33 | busy => pkt_busy, 34 | uart_data => uart_data, 35 | uart_busy => uart_busy, 36 | uart_load => uart_load 37 | ); 38 | 39 | uart_tx_comp : entity work.uart_tx 40 | generic map ( 41 | TIMER_WIDTH => BAUD_TIMER_WIDTH) 42 | port map ( 43 | rst_n => rst_n, 44 | clk => clk, 45 | load => uart_load, 46 | data_in => uart_data, 47 | uart_tx => uart_tx, 48 | busy => uart_busy 49 | ); 50 | 51 | -- Generate the reference clock @ 50% duty cycle 52 | clock_gen : process 53 | begin 54 | wait for (clockperiod / 2); 55 | clk <= '1'; 56 | wait for (clockperiod / 2); 57 | clk <= '0'; 58 | end process clock_gen; 59 | 60 | -- The stimulus 61 | stim : process 62 | begin 63 | rst_n <= '0'; 64 | wait for 15 ns; -- Basic packet 65 | rst_n <= '1'; 66 | pkt_packet <= x"01020304"; 67 | pkt_we <= '1'; 68 | wait until pkt_busy = '1'; 69 | pkt_we <= '0'; 70 | wait until pkt_busy = '0'; -- Flag escaped packet 71 | pkt_packet <= x"01FEFCFD"; 72 | pkt_we <= '1'; 73 | wait until pkt_busy = '1'; 74 | pkt_we <= '0'; 75 | wait until pkt_busy = '0'; -- Checksum gets escaped packet 76 | pkt_packet <= x"01FC0001"; 77 | pkt_we <= '1'; 78 | wait until pkt_busy = '1'; 79 | pkt_we <= '0'; 80 | wait; -- done, wait forever 81 | end process stim; 82 | end beh; 83 | -------------------------------------------------------------------------------- /HW/zynq-ip/btint_axi_1.0/src/ram_dualp.vhd: -------------------------------------------------------------------------------- 1 | -- Dual ram with independent read and write ports 2 | -- used as a ping pong buffer. 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | use ieee.numeric_std.all; 6 | 7 | entity ram_dualp is 8 | generic( 9 | PP_BUF_ADDR_WIDTH : natural := 6 10 | ); 11 | port 12 | ( 13 | clk : in std_logic; 14 | rd_addr : in std_logic_vector(PP_BUF_ADDR_WIDTH - 1 downto 0); 15 | rd_data : out std_logic_vector(7 downto 0); 16 | we : in std_logic; 17 | wr_addr : in std_logic_vector(PP_BUF_ADDR_WIDTH - 1 downto 0); 18 | wr_data : in std_logic_vector(7 downto 0) 19 | ); 20 | end entity; 21 | 22 | architecture beh of ram_dualp is 23 | type mem_type is array ( (2**PP_BUF_ADDR_WIDTH) - 1 downto 0 ) of std_logic_vector(7 downto 0); 24 | signal buf : mem_type; 25 | begin 26 | update_buf : process(clk, wr_addr, we, wr_data) 27 | begin 28 | if(rising_edge(clk)) then 29 | if(we = '1') then 30 | buf(to_integer(unsigned(wr_addr))) <= wr_data; 31 | end if; 32 | rd_data <= buf(to_integer(unsigned(rd_addr))); 33 | end if; 34 | end process update_buf; 35 | end beh; 36 | -------------------------------------------------------------------------------- /HW/zynq-ip/btint_axi_1.0/src/uart_test_app.vhd: -------------------------------------------------------------------------------- 1 | -- Test application that receives data from UART RX 2 | -- increments and resends over UART TX 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | use ieee.numeric_std.all; 6 | 7 | entity uart_test_app is 8 | generic ( 9 | BAUD_TIMER_WIDTH : natural := 16 10 | ); 11 | port ( 12 | clk : in std_logic; 13 | uart_tx : out std_logic; 14 | uart_rx : in std_logic 15 | ); 16 | end uart_test_app; 17 | 18 | architecture arch of uart_test_app is 19 | signal tx_load : std_logic := '0'; 20 | signal rst_n : std_logic := '1'; 21 | signal tx_busy : std_logic; 22 | signal tx_data : std_logic_vector(7 downto 0) := (others => '0'); 23 | signal rx_read : std_logic; 24 | signal rx_data_ready : std_logic; 25 | signal rx_data : std_logic_vector(7 downto 0); 26 | signal rx_overflow_err : std_logic; 27 | signal rx_frame_err : std_logic; 28 | 29 | begin 30 | rxUUT : entity work.uart_rx 31 | generic map ( 32 | TIMER_WIDTH => BAUD_TIMER_WIDTH 33 | ) 34 | port map ( 35 | rst_n => rst_n, 36 | clk => clk, 37 | uart_rx => uart_rx, 38 | data_read => rx_read, 39 | data_ready => rx_data_ready, 40 | data_out => rx_data, 41 | overflow_err => rx_overflow_err, 42 | frame_err => rx_frame_err 43 | ); 44 | 45 | txUUT : entity work.uart_tx 46 | generic map ( 47 | TIMER_WIDTH => BAUD_TIMER_WIDTH 48 | ) 49 | port map ( 50 | rst_n => rst_n, 51 | clk => clk, 52 | load => tx_load, 53 | data_in => tx_data, 54 | uart_tx => uart_tx, 55 | busy => tx_busy 56 | ); 57 | 58 | uartCont : entity work.uart_test_app_control 59 | port map( 60 | mast_rst_n => rst_n, 61 | clk => clk, 62 | rx_data => rx_data, 63 | rx_data_rdy => rx_data_ready, 64 | rx_read_data => rx_read, 65 | rx_overflow_err => rx_overflow_err, 66 | rx_frame_err => rx_frame_err, 67 | tx_data => tx_data, 68 | tx_load_data => tx_load, 69 | tx_busy => tx_busy 70 | ); 71 | end arch; 72 | -------------------------------------------------------------------------------- /HW/zynq-ip/btint_axi_1.0/xgui/btint_axi_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { 11 | # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change 12 | } 13 | 14 | proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { 15 | # Procedure called to validate C_S_AXI_ADDR_WIDTH 16 | return true 17 | } 18 | 19 | proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { 20 | # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change 21 | } 22 | 23 | proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { 24 | # Procedure called to validate C_S_AXI_DATA_WIDTH 25 | return true 26 | } 27 | 28 | 29 | proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } { 30 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 31 | set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH} 32 | } 33 | 34 | proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { 35 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 36 | set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH} 37 | } 38 | 39 | -------------------------------------------------------------------------------- /HW/zynq-ip/hm2_axilite/xgui/hm2_axilite_int_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "C_S_AXI_ADDR_WIDTH" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "C_S_AXI_DATA_WIDTH" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { 13 | # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { 17 | # Procedure called to validate C_S_AXI_ADDR_WIDTH 18 | return true 19 | } 20 | 21 | proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { 22 | # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change 23 | } 24 | 25 | proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { 26 | # Procedure called to validate C_S_AXI_DATA_WIDTH 27 | return true 28 | } 29 | 30 | 31 | proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } { 32 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 33 | set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH} 34 | } 35 | 36 | proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { 37 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 38 | set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH} 39 | } 40 | 41 | -------------------------------------------------------------------------------- /HW/zynq-ip/hm2_io_ts/xgui/hm2_io_ts_v1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | ipgui::add_param $IPINST -name "WIDTH" 5 | 6 | } 7 | 8 | proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { 9 | # Procedure called to update WIDTH when any of the dependent parameters in the arguments change 10 | } 11 | 12 | proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { 13 | # Procedure called to validate WIDTH 14 | return true 15 | } 16 | 17 | 18 | proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } { 19 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 20 | set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH} 21 | } 22 | 23 | -------------------------------------------------------------------------------- /HW/zynq-ip/hm2_ip_wrap/.gitignore: -------------------------------------------------------------------------------- 1 | /component.xml 2 | /src/hostmot2_ip_wrap.vhd 3 | -------------------------------------------------------------------------------- /Makefile.Quartus: -------------------------------------------------------------------------------- 1 | # Build all Quartus projects that have a build.sh script 2 | 3 | BUILD_SCRIPTS := $(wildcard HW/QuartusProjects/*/build.sh) 4 | 5 | .PHONY: all $(BUILD_SCRIPTS) 6 | 7 | all: $(BUILD_SCRIPTS) 8 | 9 | $(BUILD_SCRIPTS): 10 | cd $(dir $@) ; ./$(notdir $@) 11 | 12 | 13 | -------------------------------------------------------------------------------- /SW/MK/dts-overlays/template.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; /plugin/; 2 | 3 | / { 4 | fragment@0 { 5 | target-path = "/soc/base-fpga-region"; 6 | #address-cells = <1>; 7 | #size-cells = <1>; 8 | __overlay__ { 9 | 10 | firmware-name = "%FIRMWARE%"; 11 | 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | ranges = <0x00040000 0xff240000 0x00010000>; 16 | fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>; 17 | 18 | hm2reg_io_0: hm2-socfpga0@0x40000 { 19 | compatible = "generic-uio,ui_pdrv"; 20 | reg = <0x40000 0x10000>; 21 | interrupt-parent = <0x2>; 22 | interrupts = <0 43 1>; 23 | clocks = <&osc1>; 24 | address_width = <14>; 25 | data_width = <32>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | 31 | -------------------------------------------------------------------------------- /SW/MK/kernel-drivers/.gitignore: -------------------------------------------------------------------------------- 1 | *.ko 2 | *.mod.c 3 | 4 | *.o 5 | *.symvers 6 | *.order 7 | *.cmd 8 | *tmp* 9 | *tmp*/* 10 | .tmp** 11 | .tmp*/** 12 | 13 | *.mod 14 | 15 | -------------------------------------------------------------------------------- /SW/MK/kernel-drivers/README.md: -------------------------------------------------------------------------------- 1 | 2 | the hm2adc_uio-module is for now redundant. (not of use). 3 | 4 | hm2reg_uio-module is currently implemented in Machinekit via the hostmot2 hm2_soc driver. 5 | 6 | This documents the inner ADC functionality: 7 | 8 | 9 | HAL hostmot2_ol: Builtin Nano Soc adc ip core. [relative link here](../../../HW/QuartusProjects/Common/adc_ltc2308_fifo.s) 10 | 11 | when running the hm2_soc_ol driver with _adc=1 12 | 13 | adc values show up as: 14 | hm2_5i25.0.nano_soc_adc.ch.0.out 15 | hm2_5i25.0.nano_soc_adc.ch.1.out 16 | hm2_5i25.0.nano_soc_adc.ch.2.out 17 | hm2_5i25.0.nano_soc_adc.ch.3.out 18 | hm2_5i25.0.nano_soc_adc.ch.4.out 19 | hm2_5i25.0.nano_soc_adc.ch.5.out 20 | hm2_5i25.0.nano_soc_adc.ch.6.out 21 | hm2_5i25.0.nano_soc_adc.ch.7.out 22 | in the hal 23 | 24 | mksocmemio: c++ generic Hostmot2 memory read/write utility: 25 | 26 | 27 | manual usage examples: 28 | 29 | 30 | #---------- Single channel select --------------# 31 | 32 | # set measure number (number of samples = 8) 33 | mksocmemio -w 0x204 8 # limit = 2047 ! 34 | 35 | # set sample channel 2 start (ch_nr << 1 | 0x001) 36 | mksocmemio -w 0x204 1 fetch 1 sample 37 | mksocmemio -w 0x200 4 38 | .mksocmemio -w 0x200 5 39 | 40 | # read and print all sampled values to screen 41 | mksocmemio -r 0x204 // 1 sample 42 | 43 | # set sample channel 0 start (ch_nr << 1 | 0x001) 44 | mksocmemio -w 0x204 4 fetch 4 samples 45 | mksocmemio -w 0x200 0 46 | mksocmemio -w 0x200 1 47 | 48 | # read and print all sampled values to screen 49 | mksocmemio -r 0x204 // each suggesive read command to this location shows the next sample 50 | 51 | 52 | #---------- Auto channel select mode ----------------# 53 | #---------- this is the current mode the DExx hal adc ---------------# 54 | # set measure number (number of samples = 8) 55 | .mksocmemio -w 0x204 8 56 | 57 | # set sample channel 2 ready/start/ready and auto update bit(ch_nr << 1 | 0x00(0/1) | 0x010) 58 | mksocmemio -w 0x200 0x0100 59 | mksocmemio -w 0x200 0x0101 // start sampling 60 | 61 | # read and print all sampled values to screen 62 | mksocmemio -r 0x204 // repeat 8 times to read all (8) samples 63 | 64 | -------------------------------------------------------------------------------- /SW/MK/kernel-drivers/hm2reg_uio-module/.kdev4/hm2reg_uio-module.kdev4: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/SW/MK/kernel-drivers/hm2reg_uio-module/.kdev4/hm2reg_uio-module.kdev4 -------------------------------------------------------------------------------- /SW/MK/kernel-drivers/hm2reg_uio-module/Kbuild: -------------------------------------------------------------------------------- 1 | obj-m := hm2reg_uio-module.o 2 | -------------------------------------------------------------------------------- /SW/MK/kernel-drivers/hm2reg_uio-module/Makefile: -------------------------------------------------------------------------------- 1 | KERNEL_SRC_DIR=/home/mib/Development/Projects/arm-linux-gnueabifh-kernel/linux 2 | CURDIR=$(shell pwd) 3 | CROSS_C="/home/mib/Development/Projects/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/bin/arm-linux-gnueabihf-" 4 | ARCH=arm 5 | 6 | OUT_DIR =$(KERNEL_SRC_DIR) 7 | 8 | //NCORES=`nproc` 9 | NCORES=1 10 | 11 | 12 | 13 | #LINUX_VARIABLES = PATH=$(PATH) 14 | LINUX_VARIABLES = ARCH=$(ARCH) 15 | ifneq ("$(KBUILD_BUILD_VERSION)","") 16 | LINUX_VARIABLES += KBUILD_BUILD_VERSION="$(KBUILD_BUILD_VERSION)" 17 | endif 18 | LINUX_VARIABLES += CROSS_COMPILE=$(CROSS_C) 19 | 20 | #ifneq ("$(DEVICETREE_SRC)","") 21 | # LINUX_VARIABLES += CONFIG_DTB_SOURCE=$(DEVICETREE_SRC) 22 | #endif 23 | #LINUX_VARIABLES += INSTALL_MOD_PATH=$(INSTALL_MOD_PATH) 24 | 25 | 26 | ifndef OUT_DIR 27 | $(error OUT_DIR is undefined, bad environment, you point OUT_DIR to the linux kernel build output directory) 28 | endif 29 | 30 | KDIR ?= $(OUT_DIR) 31 | 32 | default: 33 | $(MAKE) -j$(NCORES) $(LINUX_VARIABLES) -C $(KDIR) M=$(CURDIR) 34 | 35 | clean: 36 | $(MAKE) -C $(KDIR) $(LINUX_VARIABLES) M=$(CURDIR) clean 37 | 38 | help: 39 | $(MAKE) -C $(KDIR) $(LINUX_VARIABLES) M=$(CURDIR) help 40 | 41 | modules: 42 | $(MAKE) -j$(NCORES) $(LINUX_VARIABLES) -C $(KDIR) M=$(CURDIR) modules 43 | 44 | modules_install: 45 | $(MAKE) -C $(KDIR) $(LINUX_VARIABLES) M=$(CURDIR) modules_install 46 | 47 | -------------------------------------------------------------------------------- /SW/MK/kernel-drivers/hm2reg_uio-module/hm2reg_uio-module.kdev4: -------------------------------------------------------------------------------- 1 | [Project] 2 | Manager=KDevCustomMakeManager 3 | Name=hm2reg_uio-module 4 | -------------------------------------------------------------------------------- /SW/MK/packaging/Makefile.cv: -------------------------------------------------------------------------------- 1 | # find all .rbf files 2 | # generate a matching dts containing the path name 3 | # convert to dtbo under /lib/firmware/socfpga/dtbo/.dtbo 4 | 5 | # use dtc which came with kernel: 6 | #DTC := /usr/src/linux-headers-$(shell uname -r)/scripts/dtc/dtc 7 | # use the dtc from apt install device-tree-compiler 8 | DTC := dtc 9 | 10 | BASEDIR := /lib/firmware/socfpga 11 | RBF_BASENAMES := $(patsubst %.rbf,%,$(patsubst $(BASEDIR)/%,%, $(wildcard $(BASEDIR)/*.rbf))) 12 | DTBS := $(addprefix $(BASEDIR)/dtbo/, $(addsuffix .dts,$(RBF_BASENAMES))) 13 | DTBO := $(addprefix $(BASEDIR)/dtbo/, $(addsuffix .dtbo,$(RBF_BASENAMES))) 14 | 15 | all: $(DTBO) 16 | 17 | clean: 18 | rm -f $(DTBO) 19 | 20 | 21 | # how to create a dts given an rbf name 22 | $(BASEDIR)/dtbo/%.dts: $(BASEDIR)/%.rbf 23 | sed "s/%FIRMWARE%/socfpga\/"$( $@ 24 | 25 | # dts files depend on the template 26 | $(DTBS): $(BASEDIR)/dtbo/template.dts 27 | 28 | # how to create a dtbo from a dts: 29 | %.dtbo: %.dts 30 | $(DTC) -I dts -O dtb -@ -o $@ $< 31 | -------------------------------------------------------------------------------- /SW/MK/packaging/Makefile.zynq: -------------------------------------------------------------------------------- 1 | # find all $(FWEXT) files in $(BASEDIR) 2 | # generate a matching dts containing the path name 3 | # convert to dtbo under /lib/firmware/zynq/dtbo/.dtbo 4 | 5 | # use dtc which came with kernel: 6 | #DTC := /usr/src/linux-headers-$(shell uname -r)/scripts/dtc/dtc 7 | DTC := dtc 8 | 9 | BASEDIR := /lib/firmware/zynq/dtbo 10 | 11 | 12 | FW_BASENAMES := $(patsubst %.dts,%,$(wildcard $(BASEDIR)/*.dts)) 13 | DTBO := $(addsuffix .dtbo,$(FW_BASENAMES)) 14 | 15 | all: $(DTBO) 16 | 17 | debug: 18 | @echo DTBS=$(DTBS) DTBO=$(DTBO) 19 | 20 | clean: 21 | rm -f $(DTBO) 22 | 23 | 24 | # how to create a dtbo from a dts: 25 | %.dtbo: %.dts 26 | $(DTC) -I dts -O dtb -@ -o $@ $< 27 | -------------------------------------------------------------------------------- /SW/MK/packaging/postinstall.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | cd /lib/firmware/socfpga/dtbo 3 | echo rebuilding device tree overlays in ${PWD} 4 | make all 5 | 6 | -------------------------------------------------------------------------------- /SW/MK/uio_irq_test/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | TARGET = uio_test 3 | 4 | SOCEDS_DEST_ROOT = /home/mib/altera/15.1/embedded 5 | HWLIBS_ROOT = /home/mib/altera/15.1/embedded/ip/altera/hps/altera_hps/hwlib/ 6 | CROSS_COMPILE := /home/mib/Development/Projects/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/bin/arm-linux-gnueabihf- 7 | ALT_DEVICE_FAMILY ?= soc_cv_av 8 | 9 | CFLAGS := -g $(OFLAG) -Wall -Werror -std=c99 $(MULTILIBFLAGS) -I$(HWLIBS_ROOT)/include -I$(HWLIBS_ROOT)/include/$(ALT_DEVICE_FAMILY) -D$(ALT_DEVICE_FAMILY) 10 | ALL_HWLIBS_SRC = $(wildcard $(HWLIBS_ROOT)/src/hwmgr/*.c) $(wildcard $(HWLIBS_ROOT)/src/hwmgr/$(ALT_DEVICE_FAMILY)/*.c $(wildcard $(HWLIBS_ROOT)/src/utils/*.c)) 11 | 12 | LDFLAGS = -g -Wall 13 | CC = $(CROSS_COMPILE)gcc 14 | ARCH= arm 15 | 16 | all: $(TARGET) 17 | 18 | build: $(TARGET) 19 | $(TARGET): $(TARGET).o 20 | $(CC) $(LDFLAGS) $^ -o $@ 21 | %.o : %.c 22 | $(CC) $(CFLAGS) -c $< -o $@ 23 | 24 | .PHONY: clean 25 | clean: 26 | rm -f $(TARGET) *.a *.o *~ 27 | -------------------------------------------------------------------------------- /SW/MK/uio_irq_test/uio_test: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/SW/MK/uio_irq_test/uio_test -------------------------------------------------------------------------------- /SW/MK/uio_irq_test/uio_test-1.c: -------------------------------------------------------------------------------- 1 | #define _XOPEN_SOURCE 500 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | int main() 12 | { 13 | int uiofd; 14 | int configfd; 15 | int err; 16 | int i; 17 | unsigned icount; 18 | unsigned char command_high; 19 | 20 | uiofd = open("/dev/uio0", O_RDONLY); 21 | if (uiofd < 0) { 22 | perror("uio open:"); 23 | return errno; 24 | } 25 | configfd = open("/sys/class/uio/uio0/device/config", O_RDWR); 26 | if (configfd < 0) { 27 | perror("config open:"); 28 | return errno; 29 | } 30 | 31 | /* Read and cache command value */ 32 | err = pread(configfd, &command_high, 1, 5); 33 | if (err != 1) { 34 | perror("command config read:"); 35 | return errno; 36 | } 37 | command_high &= ~0x4; 38 | 39 | for(i = 0;; ++i) { 40 | /* Print out a message, for debugging. */ 41 | if (i == 0) 42 | fprintf(stderr, "Started uio test driver.\n"); 43 | else 44 | fprintf(stderr, "Interrupts: %d\n", icount); 45 | 46 | /****************************************/ 47 | /* Here we got an interrupt from the 48 | device. Do something to it. */ 49 | /****************************************/ 50 | 51 | /* Re-enable interrupts. */ 52 | err = pwrite(configfd, &command_high, 1, 5); 53 | if (err != 1) { 54 | perror("config write:"); 55 | break; 56 | } 57 | 58 | /* Wait for next interrupt. */ 59 | err = read(uiofd, &icount, 4); 60 | if (err != 4) { 61 | perror("uio read:"); 62 | break; 63 | } 64 | 65 | } 66 | return errno; 67 | } 68 | -------------------------------------------------------------------------------- /SW/MK/uio_irq_test/uio_test.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | int main(void) 9 | { 10 | int fd = open("/dev/uio0", O_RDWR); 11 | if (fd < 0) { 12 | perror("open"); 13 | exit(EXIT_FAILURE); 14 | } 15 | 16 | while (1) { /* some condition here */ 17 | uint32_t info = 1; /* unmask */ 18 | 19 | ssize_t nb = write(fd, &info, sizeof(info)); 20 | if (nb < sizeof(info)) { 21 | perror("write"); 22 | close(fd); 23 | exit(EXIT_FAILURE); 24 | } 25 | 26 | /* Wait for interrupt */ 27 | nb = read(fd, &info, sizeof(info)); 28 | if (nb == sizeof(info)) { 29 | /* Do something in response to the interrupt. */ 30 | printf("Interrupt #%u!\n", info); 31 | } 32 | } 33 | 34 | close(fd); 35 | exit(EXIT_SUCCESS); 36 | } -------------------------------------------------------------------------------- /SW/MK/uio_irq_test/uio_test.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/SW/MK/uio_irq_test/uio_test.o -------------------------------------------------------------------------------- /build.quartus.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | set -x 3 | 4 | QSYS_ROOTDIR=/home/builder/altera_lite/15.1/quartus/sopc_builder/bin 5 | ALTERAOCLSDKROOT=/home/builder/altera_lite/15.1/hld 6 | PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/home/builder/altera_lite/15.1/quartus/bin:/home/builder/altera_lite/15.1/quartus/sopc_builder/bin 7 | HOME=/home/builder 8 | 9 | # generate the protobuf python bindings 10 | cd /work/HW/firmware-tag 11 | make TOPDIR=/work py-proto 12 | 13 | # generate Quartus bitfiles 14 | cd /work/ 15 | make -j$(nproc) -f Makefile.Quartus all 16 | 17 | # results are in HW/QuartusProjects/**/output_files/*.rbf 18 | -------------------------------------------------------------------------------- /build.vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | cd /work/HW/VivadoProjects 4 | 5 | configs=`find . -type f -name *_config` 6 | 7 | for cfg in ${configs} 8 | do 9 | echo building ${cfg} 10 | ./make_bitfile.sh ${cfg} 11 | done 12 | -------------------------------------------------------------------------------- /docs/Beta3-rel/mksocfpga_hm2-dir-ok.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/Beta3-rel/mksocfpga_hm2-dir-ok.png -------------------------------------------------------------------------------- /docs/Beta3-rel/mksocfpga_hm2-step-pulse.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/Beta3-rel/mksocfpga_hm2-step-pulse.png -------------------------------------------------------------------------------- /docs/Qemu-workarounds.md: -------------------------------------------------------------------------------- 1 | Stretch: (Qemu 2.5) 2 | Qemu-debootstrap works with the --include= that then also will configure the packages. 3 | 4 | 5 | NOTE: this workaround has beem applied to the stretch rootfs gen script 21 feb 2016. 6 | 7 | 8 | However the debootstrap file contains an -e at the very top, making it grind to a halt midways with following message: 9 | 10 | I: Running command: chroot /mnt/rootfs /debootstrap/debootstrap --second-stage 11 | I: Keyring file not available at /usr/share/keyrings/debian-archive-keyring.gpg; switching to https mirror https://mirrors.kernel.org/debian 12 | 13 | 14 | 15 | Open a separete konsole window and change the -e to: -x or -v (in nano) 16 | 17 | 18 | sudo nano /mnt/rootfs/debootstrap/debootstrap 19 | 20 | ctrl-x --> y 21 | 22 | 23 | then continue the script with: 24 | 25 | sudo chroot /mnt/rootfs /debootstrap/debootstrap --second-stage 26 | 27 | 28 | Afterwards you need to unmount the image completely (option: use "lsblk" command to view the mounts): 29 | 30 | sudo umount -R /mnt/rootfs 31 | sudo losetup -D 32 | 33 | Lastly Remember to comment out at least (with a #) 34 | 35 | #create_image 36 | #build_rootfs_into_image 37 | 38 | At the bottom and save the script before re-running the image build script 39 | 40 | --- 41 | 42 | Jessie 43 | 44 | Default qemu-debootstrap in jessie does not support --include= 45 | 46 | additional apt package install is therefore moved to the intial run script 47 | 48 | 49 | 50 | -------------------------------------------------------------------------------- /docs/Quartus-Qsys-Ip-search-path_linux-location.md: -------------------------------------------------------------------------------- 1 | Update (6-mar-2016) 2 | 3 | Backup and then delete this file: 4 | 5 | /home//.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 6 | 7 | or: 8 | 9 | ~/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 10 | 11 | In the quartus folder place an .ipx file with a relative path to the ip cores folder ie: 12 | 13 | https://github.com/the-snowwhite/mksocfpga/blob/master/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.ipx 14 | 15 | cd 16 | 17 | cat < ./soc_system.ipx 18 | 19 | 20 | 21 | 22 | EOT 23 | 24 | --- 25 | 26 | This is a reference to the Global Quartus IP core search path, not excatly the one qsys uses...! 27 | 28 | /home/mib/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 29 | 30 | Containing: 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | Linux Quartus 15.1(Installed in standard location) Relocation Fix: 39 | 40 | (path is relative to quartus project folder) 41 | 42 | Change path to relative path instead: 43 | 44 | 45 | mib@debian9-ws:~$ cat /home/mib/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 46 | 47 | 48 | 49 | 50 | 51 | mib@debian9-ws:~$ cat ~/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 52 | 53 | 54 | 55 | 56 | mib@debian9-ws:~$ 57 | 58 | do: 59 | 60 | cat < ~/.altera.quartus/ip/15.1/ip_search_path/user_components.ipx 61 | 62 | 63 | 64 | 65 | EOT 66 | 67 | -------------------------------------------------------------------------------- /docs/Quartus-setup-notes/Altera-15.1-depedencies-and-udev-rules.md: -------------------------------------------------------------------------------- 1 | #Install Quartus debian dependencies: 2 | 3 | sudo apt install expat fontconfig libfreetype6 xfonts-base xfonts-tipa libc6 libgtk2.0-0 libcanberra0 libpng3 libpng12.0 libice6 libsm6 util-linux libncurses5 tcl tcllib libx11-6 libxau6 libxdmcp6 libxext6 libxft2 libxrender1 libxt6 libxtst6 4 | 5 | sudo apt install expat:i386 fontconfig:i386 libfreetype6:i386 libc6:i386 libgtk2.0-0:i386 libcanberra0:i386 libpng3:i386 libpng12-0:i386 libice6:i386 libsm6:i386 util-linux:i386 libncurses5:i386 tcl:i386 libx11-6:i386 libxau6:i386 libxdmcp6:i386 libxext6:i386 libxft2:i386 libxrender1:i386 libxt6:i386 libxtst6:i386 6 | sudo apt install libfreetype6:i386 libc6:i386 libgtk2.0-0:i386 libcanberra0:i386 libpng3:i386 libpng12-0:i386 libice6:i386 libsm6:i386 libncurses5:i386 libx11-6:i386 libxau6:i386 libxdmcp6:i386 libxext6:i386 libxft2:i386 libxrender1:i386 libxt6:i386 libxtst6:i386 7 | 8 | sudo apt install expat:i386 fontconfig:i386 libfreetype6:i386 libc6:i386 libgtk2.0-0:i386 libcanberra0:i386 9 | 10 | sudo apt install libncurses5:i386 tcl:i386 libx11-6:i386 libxau6:i386 libxdmcp6:i386 libxext6:i386 libxft2:i386 libxrender1:i386 libxt6:i386 libxtst6:i386 11 | 12 | # not available in debian ? .. seems to work without. 13 | util-linux:i386 14 | 15 | ---- 16 | 17 | #fix detection of node based licenses for * mac hw address 18 | 19 | Add eth0 named lan interface 20 | 21 | replace "xx:xx:xx:xx:xx:xx" with the real mac address of the lan interface to rename. 22 | AFAIK the interface renamed to eth0 does not need to be active or plugged in for the 23 | node locked licening to work. Also you kan install a virtual software only "dummy" 24 | lan interface, and still get the licening to work. 25 | 26 | sudo nano /etc/udev/rules.d/10-network.rules 27 | SUBSYSTEM=="net", ACTION=="add", ATTR{address}=="xx:xx:xx:xx:xx:xx", NAME="eth0" 28 | 29 | mib@debian9-ws:~/$ cat /etc/udev/rules.d/92-usbblaster.rules 30 | 31 | USB-Blaster: 32 | 33 | SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="0666" 34 | SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6002", MODE="0666" 35 | 36 | SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6003", MODE="0666" 37 | 38 | USB-Blaster II 39 | 40 | SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6010", MODE="0666" 41 | SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="0666" 42 | 43 | Activate / enable new settings without reboot: 44 | 45 | sudo udevadm control --reload 46 | -------------------------------------------------------------------------------- /docs/hm2reg-io_orig-timing.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/hm2reg-io_orig-timing.png -------------------------------------------------------------------------------- /docs/notes-about-quartus.md: -------------------------------------------------------------------------------- 1 | look at: 2 | 3 | [HW REadme.md](../HW/README.md) 4 | 5 | -------------------------------------------------------------------------------- /docs/pics/Hostmot2-vhd_inst-pinouts.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/pics/Hostmot2-vhd_inst-pinouts.png -------------------------------------------------------------------------------- /docs/pics/Hps-fpga-bridges.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/pics/Hps-fpga-bridges.png -------------------------------------------------------------------------------- /docs/pics/hm2_soc-steprate1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/pics/hm2_soc-steprate1.png -------------------------------------------------------------------------------- /docs/pics/hm2_soc-steprate2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/pics/hm2_soc-steprate2.png -------------------------------------------------------------------------------- /docs/pics/hm2reg-io_orig-timing.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/pics/hm2reg-io_orig-timing.png -------------------------------------------------------------------------------- /docs/pics/irq/HM-Soc-DPLL_wave.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/pics/irq/HM-Soc-DPLL_wave.png -------------------------------------------------------------------------------- /docs/pics/irq/HM-Soc-IRQ_wave1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/pics/irq/HM-Soc-IRQ_wave1.png -------------------------------------------------------------------------------- /docs/pics/irq/HM-Soc-IRQ_wave2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/pics/irq/HM-Soc-IRQ_wave2.png -------------------------------------------------------------------------------- /docs/rtl-views/HM2-conn-idrom-addr-print.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/rtl-views/HM2-conn-idrom-addr-print.pdf -------------------------------------------------------------------------------- /docs/rtl-views/HM2-conn-print.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/rtl-views/HM2-conn-print.pdf -------------------------------------------------------------------------------- /docs/rtl-views/IDROM-print.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/rtl-views/IDROM-print.pdf -------------------------------------------------------------------------------- /docs/set-uboot-env.md: -------------------------------------------------------------------------------- 1 | 2 | ~~Missing config fpga on u-boot boot fix~~ 3 | 4 | 5 | ~~setenv fpgaimage socfpga.rbf~~ 6 | 7 | ~~setenv fpgadata 0x2000000~~ 8 | 9 | ~~setenv mmcload 'mmc rescan;load mmc 0:1 ${fpgadata} ${fpgaimage};load mmc 0:1 ${loadaddr} ${bootimage};load mmc 0:1 ${fdt_addr} ${fdtimage}'~~ 10 | 11 | ~~setenv fpgaconfig 'load mmc 0:1 ${fpgadata} ${fpgaimage};fpga load 0 ${fpgadata} ${filesize}'~~ 12 | 13 | ~~setenv bootcmd 'run fpgaconfig; run mmcload; run mmcboot'~~ 14 | 15 | --- 16 | 17 | Missing static lan mac address @u-boot fix 18 | 19 | !! permanent until preloader reinstall (replace x's with a real MAC address) 20 | 21 | setenv ethaddr xx:xx:xx:xx:xx:xx 22 | 23 | 24 | Save variables and reboot -> 25 | 26 | saveenv 27 | reset 28 | -------------------------------------------------------------------------------- /docs/test-configs/hm2-soc-stepper-cramps/hm2-soc-stepper.var: -------------------------------------------------------------------------------- 1 | 5161 0.000000 2 | 5162 0.000000 3 | 5163 0.000000 4 | 5164 0.000000 5 | 5165 0.000000 6 | 5166 0.000000 7 | 5167 0.000000 8 | 5168 0.000000 9 | 5169 0.000000 10 | 5181 0.000000 11 | 5182 0.000000 12 | 5183 0.000000 13 | 5184 0.000000 14 | 5185 0.000000 15 | 5186 0.000000 16 | 5187 0.000000 17 | 5188 0.000000 18 | 5189 0.000000 19 | 5210 0.000000 20 | 5211 0.000000 21 | 5212 0.000000 22 | 5213 0.000000 23 | 5214 0.000000 24 | 5215 0.000000 25 | 5216 0.000000 26 | 5217 0.000000 27 | 5218 0.000000 28 | 5219 0.000000 29 | 5220 1.000000 30 | 5221 0.000000 31 | 5222 0.000000 32 | 5223 0.000000 33 | 5224 0.000000 34 | 5225 0.000000 35 | 5226 0.000000 36 | 5227 0.000000 37 | 5228 0.000000 38 | 5229 0.000000 39 | 5230 0.000000 40 | 5241 0.000000 41 | 5242 0.000000 42 | 5243 0.000000 43 | 5244 0.000000 44 | 5245 0.000000 45 | 5246 0.000000 46 | 5247 0.000000 47 | 5248 0.000000 48 | 5249 0.000000 49 | 5250 0.000000 50 | 5261 0.000000 51 | 5262 0.000000 52 | 5263 0.000000 53 | 5264 0.000000 54 | 5265 0.000000 55 | 5266 0.000000 56 | 5267 0.000000 57 | 5268 0.000000 58 | 5269 0.000000 59 | 5270 0.000000 60 | 5281 0.000000 61 | 5282 0.000000 62 | 5283 0.000000 63 | 5284 0.000000 64 | 5285 0.000000 65 | 5286 0.000000 66 | 5287 0.000000 67 | 5288 0.000000 68 | 5289 0.000000 69 | 5290 0.000000 70 | 5301 0.000000 71 | 5302 0.000000 72 | 5303 0.000000 73 | 5304 0.000000 74 | 5305 0.000000 75 | 5306 0.000000 76 | 5307 0.000000 77 | 5308 0.000000 78 | 5309 0.000000 79 | 5310 0.000000 80 | 5321 0.000000 81 | 5322 0.000000 82 | 5323 0.000000 83 | 5324 0.000000 84 | 5325 0.000000 85 | 5326 0.000000 86 | 5327 0.000000 87 | 5328 0.000000 88 | 5329 0.000000 89 | 5330 0.000000 90 | 5341 0.000000 91 | 5342 0.000000 92 | 5343 0.000000 93 | 5344 0.000000 94 | 5345 0.000000 95 | 5346 0.000000 96 | 5347 0.000000 97 | 5348 0.000000 98 | 5349 0.000000 99 | 5350 0.000000 100 | 5361 0.000000 101 | 5362 0.000000 102 | 5363 0.000000 103 | 5364 0.000000 104 | 5365 0.000000 105 | 5366 0.000000 106 | 5367 0.000000 107 | 5368 0.000000 108 | 5369 0.000000 109 | 5370 0.000000 110 | 5381 0.000000 111 | 5382 0.000000 112 | 5383 0.000000 113 | 5384 0.000000 114 | 5385 0.000000 115 | 5386 0.000000 116 | 5387 0.000000 117 | 5388 0.000000 118 | 5389 0.000000 119 | 5390 0.000000 120 | -------------------------------------------------------------------------------- /docs/test-configs/hm2-soc-stepper-cramps/tool.tbl: -------------------------------------------------------------------------------- 1 | T1 P1 D0.125000 Z+0.511000 ;1/8 end mill 2 | T2 P2 D0.062500 Z+0.100000 ;1/16 end mill 3 | T3 P3 D0.201000 Z+1.273000 ;#7 tap drill 4 | T99999 P99999 Z+0.100000 ;big tool number 5 | -------------------------------------------------------------------------------- /docs/test-configs/hm2_soc-steprate1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/test-configs/hm2_soc-steprate1.png -------------------------------------------------------------------------------- /docs/test-configs/hm2_soc-steprate2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/machinekit/mksocfpga/e27a23bb09d4af73c5217a99a2a840577b8b7693/docs/test-configs/hm2_soc-steprate2.png --------------------------------------------------------------------------------