├── Dataset Access link ├── Result and discussion (1).docx ├── Simulation Video Link ├── Simulation video ├── Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approx.pdf ├── Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approx.docx ├── LICENSE ├── References ├── ECG_Digital_Filter_Development_V3.m └── README.md /Dataset Access link: -------------------------------------------------------------------------------- 1 | https://drive.google.com/file/d/1u4TrRZb5FlefYEWwN4pKiS5FsLGIiHpB/view 2 | -------------------------------------------------------------------------------- /Result and discussion (1).docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mahdieslaminet/Capritios_Filter_Design/HEAD/Result and discussion (1).docx -------------------------------------------------------------------------------- /Simulation Video Link: -------------------------------------------------------------------------------- 1 | Simulation Video Link 2 | 3 | https://drive.google.com/file/d/1jkCJwNzZUYs8z4CliZfTObJMEKEQKAXO/view?usp=drive_link 4 | -------------------------------------------------------------------------------- /Simulation video: -------------------------------------------------------------------------------- 1 | Simulation video access link 2 | 3 | https://drive.google.com/file/d/1jkCJwNzZUYs8z4CliZfTObJMEKEQKAXO/view?usp=drive_link 4 | -------------------------------------------------------------------------------- /Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approx.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mahdieslaminet/Capritios_Filter_Design/HEAD/Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approx.pdf -------------------------------------------------------------------------------- /Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approx.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mahdieslaminet/Capritios_Filter_Design/HEAD/Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approx.docx -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 mahdieslaminet 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /References: -------------------------------------------------------------------------------- 1 | References 2 | 3 | 34. G. Keerthiga and S. P. Kumar, “Evaluating FPGA-based denoising 4 | techniques for improved signal quality in electrocardiograms,” 5 | Analog Integrated Circuits and Signal Processing, 2024, doi: 6 | 10.1007/s10470-024-02277-w. 7 | 35. M. Sinnoor and S. K. Janardhan, “An ECG Denoising Method Based 8 | on Hybrid MLTP-EEMD Model,” International Journal of Intelligent 9 | Engineering and Systems, vol. 15, no. 1, pp. 575–583, 2022, doi: 10 | 10.22266/IJIES2022.0228.52. 11 | 36. A. Gon and A. Mukherjee, “Design and FPGA Implementation of an 12 | Efficient Architecture for Noise Removal in ECG Signals Using 13 | Lifting-Based Wavelet Denoising,” in 2023 11th International 14 | Symposium on Electronic Systems Devices and Computing, ESDC 2023, 15 | Institute of Electrical and Electronics Engineers Inc., 2023. doi: 16 | 10.1109/ESDC56251.2023.10149865. 17 | 37. A. S. Deulkar and N. R. Kolhare, “FPGA implementation of audio 18 | and video processing based on Zedboard,” in Proceedings of the 19 | 2020 International Conference on Smart Innovations in Design, 20 | Environment, Management, Planning and Computing, ICSIDEMPC 2020, 21 | 2020, pp. 305–310. doi: 10.1109/ICSIDEMPC49020.2020.9299639. 22 | 38. [1]L. Shang, A. S. Kaviani, and K. Bathala, “Dynamic Power 23 | Consumption in VirtexTM-II FPGA Family,” 2002. 24 | -------------------------------------------------------------------------------- /ECG_Digital_Filter_Development_V3.m: -------------------------------------------------------------------------------- 1 | % ECG IIR digital filter and NLM filter 2 | % Efficient speed, area, and power 3 | % Author: Mehran Shoaei 4 | % Date: 2024.06.21 5 | % DSP Course Dr Eslami SRBIAU University 6 | 7 | % Load ECG signal 8 | ecg_dataset = load('ECGData.mat'); 9 | ecg_signals = ecg_dataset.ECGData.Data; 10 | ecg_signal = ecg_signals(162, :); 11 | ecg_signal = ecg_signal / max(abs(ecg_signal)); % Normalize data 12 | 13 | % Define the coefficients of the IIR digital filter 14 | b = [0.0675, 0.1349, 0.0675]; 15 | a = [1, -1.143, 0.4128]; 16 | 17 | % Perform the IIR filter on the ECG signal 18 | filtered_signal_iir = filter(b, a, ecg_signal); 19 | 20 | % Optimize parameters for the NLM filter 21 | optimized_params = pso_optimization(@nlm_filter, filtered_signal_iir); 22 | 23 | % Use optimized parameters to filter the ECG signal with NLM filter 24 | filtered_signal_nlm = nlm_filter(filtered_signal_iir, optimized_params); 25 | 26 | % Calculate SNR and RMSE for NLM filtered signal 27 | snr_value_final = snr(filtered_signal_nlm, ecg_signal - filtered_signal_nlm); 28 | rmse_value_final = sqrt(mean((ecg_signal - filtered_signal_nlm).^2)); 29 | 30 | % Calculate SNR and RMSE for IIR filtered signal 31 | snr_value_pri = snr(filtered_signal_iir, ecg_signal - filtered_signal_iir); 32 | rmse_value_pri = sqrt(mean((ecg_signal - filtered_signal_iir).^2)); 33 | 34 | % Display results 35 | fprintf('SNR: %f dB\n', snr_value_final); 36 | fprintf('RMSE: %f\n', rmse_value_final); 37 | 38 | % Display the original, IIR filtered, and NLM filtered signals 39 | subplot(3, 2, 1); 40 | plot(ecg_signal); 41 | title('ECG Original Signal'); 42 | xlabel('Time'); 43 | ylabel('Amplitude'); 44 | 45 | subplot(3, 2, 3); 46 | plot(filtered_signal_iir); 47 | title('ECG IIR Filtered Signal'); 48 | xlabel('Time'); 49 | ylabel('Amplitude'); 50 | 51 | subplot(3, 2, 5); 52 | plot(filtered_signal_nlm); 53 | title('ECG NLM Filtered Signal'); 54 | xlabel('Time'); 55 | ylabel('Amplitude'); 56 | 57 | % Display SNR and RMSE values 58 | bar_titles = categorical({'SNR Value Primary','SNR Value New','RSME Value Primary','RMSE Value New'}); 59 | bar_values = [snr_value_pri snr_value_final rmse_value_pri rmse_value_final]; 60 | subplot(3, 2, [2,4,6]); 61 | bar(bar_titles, bar_values, 0.5); 62 | title('Parameters Value - SNR[primary-final],RMSE[primary-final]'); 63 | ylabel('(dB)'); 64 | 65 | % %Display the result of signal 66 | % subplot(2, 3, 5); 67 | % plot(approx_sum_total); 68 | % title('ERCPAA'); 69 | % xlabel('Block'); 70 | % ylabel('Number'); 71 | % 72 | % subplot(2, 3, 6); 73 | % plot(product_total); 74 | % title('BWM'); 75 | % xlabel('Block'); 76 | % ylabel('Number'); 77 | 78 | 79 | % subplot(2, 3, 5); 80 | % bar(rmse_value); 81 | % title('RMSE Value'); 82 | % ylabel('RMSE'); 83 | 84 | % Implementations of ERCPAA and BWM functions 85 | function sum = ercpaa(a, b) 86 | a_bin = dec2bin(a, 8); 87 | b_bin = dec2bin(b, 8); 88 | carry = 0; 89 | sum = zeros(1, 8); 90 | for i = 8:-1:1 91 | ai = str2double(a_bin(i)); 92 | bi = str2double(b_bin(i)); 93 | sum(i) = xor(xor(ai, bi), carry); 94 | carry = or(and(ai, bi), and(carry, xor(ai, bi))); 95 | end 96 | sum = bin2dec(num2str(sum)); 97 | end 98 | 99 | function product = bwmultiplier(a, b) 100 | a_bin = dec2bin(a, 8); 101 | b_bin = dec2bin(b, 8); 102 | n = length(a_bin); 103 | p = zeros(n, n); 104 | for i = 1:n 105 | for j = 1:n 106 | p(i, j) = str2double(a_bin(n-i+1)) * str2double(b_bin(n-j+1)); 107 | end 108 | end 109 | product = 0; 110 | for k = 0:2*n-2 111 | sum = 0; 112 | for i = 0:k 113 | j = k - i; 114 | if i < n && j < n 115 | sum = sum + p(i+1, j+1); 116 | end 117 | end 118 | product = product + sum * 2^k; 119 | end 120 | end 121 | 122 | % Implementation of NLM filter function 123 | function denoised_signal = nlm_filter(signal, params) 124 | search_window = round(params(1)); 125 | similarity_window = round(params(2)); 126 | h = params(3); 127 | N = length(signal); 128 | denoised_signal = zeros(size(signal)); 129 | for i = 1:N 130 | w_start = max(1, i - search_window); 131 | w_end = min(N, i + search_window); 132 | s_start = max(1, i - similarity_window); 133 | s_end = min(N, i + similarity_window); 134 | patch = signal(s_start:s_end); 135 | weights = exp(-(patch - signal(i)).^2 / (h^2)); 136 | weights = weights / sum(weights); 137 | denoised_signal(i) = sum(weights .* signal(s_start:s_end)); 138 | end 139 | end 140 | 141 | % Implementation of PSO optimization function 142 | function optimized_params = pso_optimization(nlm_func, signal) 143 | num_particles = 30; 144 | max_iterations = 100; 145 | param_bounds = [1, 10; 1, 10; 0.1, 1]; 146 | options = optimoptions('particleswarm', 'SwarmSize', num_particles, 'MaxIterations', max_iterations); 147 | optimized_params = particleswarm(@(params) pso_objective(nlm_func, signal, params), 3, param_bounds(:,1), param_bounds(:,2), options); 148 | end 149 | 150 | function error = pso_objective(nlm_func, signal, params) 151 | denoised_signal = nlm_func(signal, params); 152 | error = sqrt(mean((signal - denoised_signal).^2)); 153 | end 154 | 155 | function dfa_result = dfa(signal) 156 | N = length(signal); 157 | n = floor(N/2); 158 | F = zeros(n,1); 159 | for i = 1:n 160 | X = cumsum(signal - mean(signal)); 161 | Y = polyfit(1:N, X, 1); 162 | Y = polyval(Y, 1:N); 163 | F(i) = sqrt(mean((X - Y).^2)); 164 | end 165 | dfa_result = F; 166 | end 167 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Capritious-Filter-Design 2 | 3 | This github repository contains the project code, articles and dataset access link 4 | if you haven't access to drived files, send mail to author 5 | mehran.shoaee@gmail.com 6 | mehran.shoaei@srbiau.ac.ir 7 | 8 | The MATLAB code is available in ECG_Digita_Filter_Development_V3.m matlab code file 9 | this code is a sumulation of porposed filter design in MATLAB development environment 10 | the ECG Dataset that is used in project is available with acces link in google drive 11 | references artile 12 | 13 | 14 | These below persian courses is good for beginner persons who that intrested to understand this 15 | article, simulation and Digital Signal Processing. 16 | 17 | All hints for beginner students 18 | 19 | Dr Mashhadi DSP course 20 | https://maktabkhooneh.org/course/%D9%BE%D8%B1%D8%AF%D8%A7%D8%B2%D8%B4-%D8%B3%DB%8C%DA%AF%D9%86%D8%A7%D9%84%D9%87%D8%A7%DB%8C-%D8%AF%DB%8C%D8%AC%DB%8C%D8%AA%D8%A7%D9%84-mk128/ 21 | 22 | Dr Babaei Signal and System course 23 | https://maktabkhooneh.org/course/%D8%B3%DB%8C%DA%AF%D9%86%D8%A7%D9%84-%D9%88-%D8%B3%D9%8A%D8%B3%D8%AA%D9%85-mk75/ 24 | 25 | 26 | Access link to all project files 27 | 28 | https://www.dropbox.com/scl/fo/mt1g6h3jwbwx92puptq15/ALdZ_4gDh8tkNat1FVmIRVI?rlkey=ln5rqhioth811w7kdaotnv03z&st=5ryrde2s&dl=0 29 | 30 | Capricious Digital Filter Design and Implementation Using 31 | Baugh–Wooley Multiplier and Error Reduced Carry 32 | Prediction Approximate Adder for ECG Noise Removal Application 33 | 34 | Abstract 35 | Capricious digital filter (CDF) plays a significant role of signal processing application field to eradicate noise. 36 | Any prototype filter desired frequency response is attained by developing all pass makeover-based capricious 37 | digital filter (APM-CDF) that sustains full control on cutoff frequency. The benefits of APM-CDF are limited 38 | through its speed,area,andpowerconsume.Inthismanuscript,Baugh–Wooleymultiplier(BWM) with error reduced carry 39 | prediction approximate adder (ERCPAA) is proposed to The implementation of audio and video processing on 40 | FPGA-based systems using the Zedboard platform provides significant advantages in terms of performance and 41 | flexibility. The approach leverages the hardware capabilities of FPGAs to handle parallel processing tasks 42 | efficiently. The design and implementation process involves using high-level synthesis (HLS) tools like Vivado 43 | HLS to convert C/C++ code into RTL, which simplifies the development process and reduces the time required for 44 | optimization. This methodology allows designers to explore various design alternatives and optimize the system for 45 | specific performance metrics, such as latency and resource utilization. For instance, in a comparative analysis of 46 | traditional RTL and HLS-based implementations, the HLS approach demonstrated a reduction in implementation time 47 | from two weeks to one week while also optimizing resource usage, as evidenced by the decrease in Block RAM and DSP48 48 | utilization. 49 | 50 | 51 | Filters are applied to eradicate unwanted noise from the needed input signal’s frequency range. Recently, the 52 | investigators try to design the CDFs for providing feasible realization of digital filters. The CDFs are used 53 | to manage several parameters for giving variable frequency response. The FIR is deemed as the admired CDF filter; 54 | this is applied in many domains. But, FIR filter contains more hardware complex, also it occupies more operating 55 | power. The 2D digital filter reduces the complexity with the help of quadrant symmetric concept. 56 | It diminishes more filter coefficients. The ideal frequency response is accomplished through fractional order 57 | digital discriminate (FOD). 58 | Capricious digital filter is based upon filters operating frequency (OF). The complexity of Capricious digital 59 | filter is decreased with the help of all pass makeover (APM). APM restores every prototype filters delay unit 60 | as well as it maintains operatingfrequency.Byfixedcoefficientprototypefilter,thevariablelowpass, high pass, 61 | band pass, and band stop responses are acquired. APM-CDF is applied to different audio functioning. The aim of 62 | APM-CDF is “to high speed APM-CDF implementation along superior operational frequency”. The fundamental arithmetic 63 | procedures have addition with multiplication. Generally, ternary logic needs low components, it realizes higher 64 | data transmission during interlink wires. Hence, it occupies lower area than binary for distributed functions. 65 | It processes the data effectually with higher speed. These are motivated to design arithmetic and logic circuits 66 | for APM-CDF. 67 | Digital filters are practical DSP structures for signal processing, estimation, and analysis. With the advent of 68 | VLSI-based technology, a number of processes needed for creating digital filters has gradually decreased, which has 69 | encouraged the creation of on-chip VLSI-oriented structure for DSP applications. The fundamental function of digital 70 | filters is multiplication, which necessitates additional hardware under space, speed,delay components, and power 71 | consumption, resulting in ineffective filter design. So, it is essential to decrease the separameters and to decrease 72 | the arithmetic performed under multiplier. 73 | This work designs capricious digital filter depending on all pass makeover. Baugh— Wooley multiplier and ERCPAA is considered 74 | to accelerate filter model with minimal power consume, area. Here, ERCPAA is a faster binary adder that occupies lower 75 | power including area. Also, BWM is utilized to lessen the hardware complex with high speed, lesser area, and lesser 76 | power consume. APM-CDF-ERCPAA-BWM filter is applicable in ECG signal noise removing application for presenting filtered 77 | superior quality signals resulting Baugh–Wooley multiplier acts the same operation by decreasing the number of partial 78 | products derived at each stage, thereby simplifying the architecture with respect to delay, complexity, and power 79 | consumption parameters. The key contributions of this work are summarized below: 80 | In a recent study, Sinnoor and Janardhan (2022) explored FPGA-based denoising techniques to enhance signal quality in 81 | electrocardiograms (ECGs) by using a hybrid model combining Multiscale Local Polynomial Transform (MLPT) and Ensemble 82 | Empirical Mode Decomposition (EEMD). This approach aimed to effectively remove noise such as white Gaussian noise from 83 | ECG signals, leading to improved signal-to-noise ratios (SNR). The hybrid MLPT-EEMD model demonstrated superior 84 | performance, achieving an SNR of 25.93 dB, significantly higher than the traditional Empirical Mode Decomposition (EMD) 85 | and other existing methods. This study underscores the potential of hybrid denoising techniques in delivering high-fidelity 86 | ECG signals for accurate cardiac analysis and diagnosis. 87 | In recent advancements, FPGA-based denoising techniques have been evaluated to enhance the signal quality of 88 | electrocardiograms (ECGs). The study utilized Vivado High-Level Synthesis (HLS) to implement an efficient ECG denoising 89 | method on an FPGA platform. The denoising techniques were assessed based on their ability to reduce noise and improve 90 | signal clarity, using performance metrics such as Mean Squared Error (MSE), Signal-to-Noise Ratio (SNR), and Peak 91 | Signal-to-Noise Ratio (PSNR). The implementation demonstrated significant 92 | 93 | improvements in reducing noise, thereby enhancing the quality of ECG signals, which is critical for accurate diagnosis 94 | and monitoring in medical applications. 95 | The implementation of audio and video processing on FPGA-based systems using the Zedboard platform provides significant 96 | advantages in terms of performance and flexibility. The approach leverages the hardware capabilities of FPGAs to handle 97 | parallel processing tasks efficiently. The design and implementation process involves using high-level synthesis (HLS) 98 | tools like Vivado HLS to convert C/C++ code into RTL, which simplifies the development process and reduces the time 99 | required for optimization. This methodology allows designers to explore various design alternatives and optimize the 100 | system for specific performance metrics, such as latency and resource utilization. For instance, in a 101 | comparative analysis of traditional RTL and HLS-based implementations, the HLS approach demonstrated a reduction in 102 | implementation time from two weeks to one week while also optimizing resource usage, as evidenced by the decrease in 103 | Block RAM and DSP48 utilization. 104 | Large FPDs, which are often called Field Programmable Gate Arrays (FPGAs), consist of a set of logic blocks and a 105 | flexible routing structure to connect them together. Using automated CAD tools, designers may program the logic blocks 106 | and their corresponding interconnect to implement any desired application within a reasonable amount of time. Such 107 | flexibility and fast time to market, however, comes with the expense of additional transistors and metal resources that 108 | are only partially utilized. Therefore, we need to identify utilized logic and routing resources that contribute to a 109 | signal for analyzing the dynamic power consumption. Our analysis and results in this paper can be used in 2 ways: 1) 110 | Better understanding of where power is consumed in FPGAs will help design of future power-efficient FPGAs. 2) Detailed 111 | understanding of power consumption distribution will help expert designers to reduce or control the power characteristics 112 | of their design. 113 | 114 | 115 | Conclusion 116 | In this manuscript, the VLSI designing of APM-CDF utilizing ERCPAA and Baugh–Wooley multiplier (BWM) depending on 117 | arithmetic perspective is proposed. The 118 | proposed APM-CDF-ERCPAA-BWM attains greater functioning frequencies even high filter order owing to its pipelined 119 | design. By introducing variable block sizes, ERCPAA establishes a fair trade-off among delay and area usage. The 120 | simulation outcomes display that the proposed adder utilizes lesser count of modules and lessens the latency over 121 | existing adders. The proposing multiplier design maximized the processing speed with the help of Baugh–Wooley multiplier 122 | (BWM). Such adder with multiplier designing assists their ERCPAA-BWM to raise its speed and operating frequency including 123 | lessening of power with components. It is appropriate in ECG signal noise removing process to offer filtered higher-quality 124 | signals. The experimental performance of proposed APM-CDF- ERCPAA-BWM filter reaches lesser power 23.87%, 21.65%, and 125 | 32.76%, and higher speed 24.76%, 23.77%, 32.86% estimatedtotheexistingAPM-CDFusingDF-4VM-CSA,DF-VMD-CLA,andDF-Radix 2-LCSLA 126 | filters, respectively. The APM-CDF-ERCPAA-BWM filter reaches lesser MSE 21.76%, 24.87% evaluated to the existing APM-CDF 127 | using DF-4VM-CSA, DFVMD-CLA filters, respectively. This research is further extended to develop a new architecture for a 128 | high-speed low power APM-CDF filter with developing efficient reconfigurable designs resulting in low latency and hardware 129 | resources. 130 | --------------------------------------------------------------------------------