├── README.md ├── gettingstarted.pdf └── orpsocv2 ├── bench ├── sysc │ ├── include │ │ ├── DebugUnitSC.h │ │ ├── GdbServerSC.h │ │ ├── JtagDriverSC.h │ │ ├── JtagSC.h │ │ ├── JtagSC_includes.h │ │ ├── MemCache.h │ │ ├── MemoryLoad.h │ │ ├── MpHash.h │ │ ├── Or1200MonitorSC.h │ │ ├── OrpsocAccess.h │ │ ├── OrpsocMain.h │ │ ├── ResetSC.h │ │ ├── RspConnection.h │ │ ├── RspPacket.h │ │ ├── SprCache.h │ │ ├── TapAction.h │ │ ├── TapActionDRScan.h │ │ ├── TapActionIRScan.h │ │ ├── TapActionReset.h │ │ ├── TapStateMachine.h │ │ ├── TraceSC.h │ │ ├── UartSC.h │ │ ├── Utils.h │ │ ├── coff.h │ │ └── elf.h │ └── src │ │ ├── DebugUnitSC.cpp │ │ ├── GdbServerSC.cpp │ │ ├── JtagDriverSC.cpp │ │ ├── JtagSC.cpp │ │ ├── MemCache.cpp │ │ ├── MemoryLoad.cpp │ │ ├── Modules.make │ │ ├── MpHash.cpp │ │ ├── Or1200MonitorSC.cpp │ │ ├── OrpsocAccess.cpp │ │ ├── OrpsocMain.cpp │ │ ├── ResetSC.cpp │ │ ├── RspConnection.cpp │ │ ├── RspPacket.cpp │ │ ├── SprCache.cpp │ │ ├── TapAction.cpp │ │ ├── TapActionDRScan.cpp │ │ ├── TapActionIRScan.cpp │ │ ├── TapActionReset.cpp │ │ ├── TapStateMachine.cpp │ │ ├── TraceSC.cpp │ │ ├── UartSC.cpp │ │ └── Utils.cpp └── verilog │ ├── AT26DFxxx.v │ ├── eth_phy.v │ ├── include │ ├── cfi_flash_BankLib.h │ ├── cfi_flash_CUIcommandData.h │ ├── cfi_flash_TimingData.h │ ├── cfi_flash_UserData.h │ ├── cfi_flash_data.h │ ├── cfi_flash_def.h │ ├── eth_phy_defines.v │ ├── or1200_monitor_defines.v │ ├── orpsoc-testbench-defines.v │ └── timescale.v │ ├── mt48lc16m16a2.v │ ├── or1200_monitor.v │ ├── orpsoc_testbench.v │ ├── smii_phy.v │ ├── uart_decoder.v │ ├── uart_stim.v │ ├── usbhostslave │ ├── HCTxPortArbiter_simlib.v │ ├── RxFifo_simlib.v │ ├── RxfifoBI_simlib.v │ ├── SCTxPortArbiter_simlib.v │ ├── SIEReceiver_simlib.v │ ├── SIETransmitter_simlib.v │ ├── SOFController_simlib.v │ ├── SOFTransmit_simlib.v │ ├── TxFifo_simlib.v │ ├── TxfifoBI_simlib.v │ ├── USBHostControlBI_simlib.v │ ├── USBSlaveControlBI_simlib.v │ ├── USBTxWireArbiter_simlib.v │ ├── directControl_simlib.v │ ├── dpMem_dc_simlib.v │ ├── endpMux_simlib.v │ ├── fifoMux_simlib.v │ ├── fifoRTL_simlib.v │ ├── getPacket_simlib.v │ ├── hostSlaveMuxBI_simlib.v │ ├── hostSlaveMux_simlib.v │ ├── hostcontroller_simlib.v │ ├── lineControlUpdate_simlib.v │ ├── processRxBit_simlib.v │ ├── processRxByte_simlib.v │ ├── processTxByte_simlib.v │ ├── readUSBWireData_simlib.v │ ├── rxStatusMonitor_simlib.v │ ├── sendPacketArbiter_simlib.v │ ├── sendPacketCheckPreamble_simlib.v │ ├── sendPacket_simlib.v │ ├── slaveDirectControl_simlib.v │ ├── slaveGetPacket_simlib.v │ ├── slaveRxStatusMonitor_simlib.v │ ├── slaveSendPacket_simlib.v │ ├── slavecontroller_simlib.v │ ├── speedCtrlMux_simlib.v │ ├── updateCRC16_simlib.v │ ├── updateCRC5_simlib.v │ ├── usbConstants_h.v │ ├── usbHostControl_h.v │ ├── usbHostControl_simlib.v │ ├── usbHostSlave_h.v │ ├── usbSerialInterfaceEngine_h.v │ ├── usbSerialInterfaceEngine_simlib.v │ ├── usbSlaveControl_h.v │ ├── usbSlaveControl_simlib.v │ ├── usb_hostslave_tb.v │ ├── usb_slave_tb.v │ ├── usbhost_simlib.v │ ├── usbhostslave_simlib.v │ ├── usbslave_simlib.v │ ├── wb_master_model.v │ ├── wishBoneBI_simlib.v │ ├── wishBoneBus_h.v │ └── writeUSBWireData_simlib.v │ ├── vpi │ ├── c │ │ ├── Makefile │ │ ├── gdb.c │ │ ├── gdb.h │ │ ├── jp_vpi.c │ │ ├── rsp-rtl_sim.c │ │ ├── rsp-rtl_sim.h │ │ └── rsp-vpi.h │ └── verilog │ │ ├── vpi_debug_defines.v │ │ └── vpi_debug_module.v │ ├── wiredelay.v │ └── x28fxxxp30.v ├── boards ├── README ├── actel │ ├── backend │ │ └── rtl │ │ │ └── verilog │ │ │ └── proasic3.v │ └── ordb1a3pe1500 │ │ ├── Makefile.inc │ │ ├── backend │ │ ├── par │ │ │ ├── README │ │ │ ├── bin │ │ │ │ ├── Makefile │ │ │ │ ├── orsoccpuboard.mkpins │ │ │ │ ├── orsoccpuexpio.mkpinassigns │ │ │ │ └── orsocexpboard.mkpins │ │ │ └── run │ │ │ │ └── Makefile │ │ └── rtl │ │ │ └── verilog │ │ │ ├── README │ │ │ ├── eth_pll.v │ │ │ ├── gbuf.v │ │ │ ├── orpsoc_flashROM.v │ │ │ ├── pll_xtal25_wb20.v │ │ │ ├── pll_xtal25_wb24.v │ │ │ ├── pll_xtal64_wb16.v │ │ │ ├── pll_xtal64_wb20.v │ │ │ ├── pll_xtal64_wb24.v │ │ │ ├── pll_xtal64_wb30.v │ │ │ └── reset_buffer.v │ │ ├── bench │ │ └── verilog │ │ │ ├── include │ │ │ ├── eth_stim.v │ │ │ ├── orpsoc-testbench-defines.v │ │ │ ├── synthesis-defines.v │ │ │ └── timescale.v │ │ │ ├── orpsoc_testbench.v │ │ │ └── spi_slave.v │ │ ├── rtl │ │ └── verilog │ │ │ ├── arbiter │ │ │ ├── README │ │ │ ├── arbiter_bytebus.v │ │ │ ├── arbiter_dbus.v │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ └── clkgen.v │ │ │ ├── flashrom │ │ │ ├── README │ │ │ └── flashrom.v │ │ │ ├── gpio │ │ │ ├── README │ │ │ └── gpio.v │ │ │ ├── include │ │ │ ├── dbg_cpu_defines.v │ │ │ ├── dbg_defines.v │ │ │ ├── dbg_wb_defines.v │ │ │ ├── ethmac_defines.v │ │ │ ├── i2c_master_slave_defines.v │ │ │ ├── or1200_defines.v │ │ │ ├── orpsoc-defines.v │ │ │ ├── orpsoc-params.v │ │ │ ├── sd_defines.v │ │ │ ├── tap_defines.v │ │ │ ├── uart_defines.v │ │ │ ├── usbhostslave_constants_h.v │ │ │ ├── usbhostslave_hostcontrol_h.v │ │ │ ├── usbhostslave_hostslave_h.v │ │ │ ├── usbhostslave_serialinterfaceengine_h.v │ │ │ ├── usbhostslave_slavecontrol_h.v │ │ │ └── usbhostslave_wishbonebus_h.v │ │ │ ├── orpsoc_top │ │ │ └── orpsoc_top.v │ │ │ ├── sdc_controller │ │ │ ├── sd_bd.v │ │ │ ├── sd_clock_divider.v │ │ │ ├── sd_cmd_master.v │ │ │ ├── sd_cmd_serial_host.v │ │ │ ├── sd_controller_wb.v │ │ │ ├── sd_crc_16.v │ │ │ ├── sd_crc_7.v │ │ │ ├── sd_data_master.v │ │ │ ├── sd_data_serial_host.v │ │ │ ├── sd_fifo_rx_filler.v │ │ │ ├── sd_fifo_tx_filler.v │ │ │ ├── sd_rx_fifo.v │ │ │ ├── sd_rx_fifo_tb.v │ │ │ ├── sd_tx_fifo.v │ │ │ └── sdc_controller.v │ │ │ └── versatile_mem_ctrl │ │ │ ├── Makefile │ │ │ ├── README │ │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── Makefile │ │ │ │ ├── burst_length_counter_defines.v │ │ │ │ ├── cke_delay_counter_defines.v │ │ │ │ ├── codec.v │ │ │ │ ├── copyright.v │ │ │ │ ├── ctrl_counter_defines.v │ │ │ │ ├── dcm_pll.v │ │ │ │ ├── ddr_16.fzm │ │ │ │ ├── ddr_16_defines.v │ │ │ │ ├── ddr_ff.v │ │ │ │ ├── delay.v │ │ │ │ ├── egress_fifo.v │ │ │ │ ├── fifo.v │ │ │ │ ├── fifo_adr_counter_defines.v │ │ │ │ ├── fifo_fill.fzm │ │ │ │ ├── fizzim.pl │ │ │ │ ├── fsm_sdr_16.v │ │ │ │ ├── fsm_wb.v │ │ │ │ ├── inc_adr.v │ │ │ │ ├── latency_counter_defines.v │ │ │ │ ├── pre_delay_counter_defines.v │ │ │ │ ├── ref_counter_defines.v │ │ │ │ ├── ref_delay_counter_defines.v │ │ │ │ ├── sdr_16.fzm │ │ │ │ ├── sdr_16_defines.v │ │ │ │ ├── versatile_counter.xls │ │ │ │ ├── versatile_fifo_dual_port_ram_dc_sw.v │ │ │ │ ├── versatile_mem_ctrl_ddr.v │ │ │ │ ├── versatile_mem_ctrl_defines.v │ │ │ │ ├── versatile_mem_ctrl_ip.v │ │ │ │ ├── versatile_mem_ctrl_top.v │ │ │ │ └── versatile_mem_ctrl_wb.v │ │ │ └── versatile_mem_ctrl.v │ │ ├── sim │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── ordb1a3pe1500-or1ksim.cfg │ │ └── run │ │ │ └── Makefile │ │ ├── sw │ │ ├── Makefile.inc │ │ ├── board │ │ │ └── include │ │ │ │ └── board.h │ │ ├── bootrom │ │ │ └── Makefile │ │ ├── drivers │ │ │ └── usbhostslave │ │ │ │ ├── Makefile │ │ │ │ ├── include │ │ │ │ ├── usbhostslave-host.h │ │ │ │ └── usbhostslave-slave.h │ │ │ │ ├── usbhostslave-host.c │ │ │ │ └── usbhostslave-slave.c │ │ └── tests │ │ │ ├── i2c_master_slave │ │ │ └── sim │ │ │ │ ├── Makefile │ │ │ │ └── i2c_master_slave-loopback.c │ │ │ └── usbhostslave │ │ │ └── sim │ │ │ ├── Makefile │ │ │ ├── usbhostslave-hostsimple.c │ │ │ └── usbhostslave-slavesimple.c │ │ └── syn │ │ └── synplify │ │ ├── bin │ │ └── Makefile │ │ └── run │ │ └── Makefile ├── altera │ ├── de0_nano │ │ ├── Makefile.inc │ │ ├── backend │ │ │ └── rtl │ │ │ │ └── verilog │ │ │ │ └── pll.v │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── include │ │ │ │ ├── eth_stim.v │ │ │ │ ├── orpsoc-testbench-defines.v │ │ │ │ ├── synthesis-defines.v │ │ │ │ └── timescale.v │ │ │ │ ├── orpsoc_testbench.v │ │ │ │ └── spi_slave.v │ │ ├── rtl │ │ │ ├── verilog │ │ │ │ ├── adv_debugsys │ │ │ │ │ ├── adbg_crc32.v │ │ │ │ │ ├── adbg_jsp_biu.v │ │ │ │ │ ├── adbg_jsp_module.v │ │ │ │ │ ├── adbg_or1k_biu.v │ │ │ │ │ ├── adbg_or1k_module.v │ │ │ │ │ ├── adbg_or1k_status_reg.v │ │ │ │ │ ├── adbg_wb_biu.v │ │ │ │ │ ├── adbg_wb_module.v │ │ │ │ │ ├── adv_dbg_if.v │ │ │ │ │ ├── bytefifo.v │ │ │ │ │ ├── syncflop.v │ │ │ │ │ └── syncreg.v │ │ │ │ ├── arbiter │ │ │ │ │ ├── README │ │ │ │ │ ├── arbiter_bytebus.v │ │ │ │ │ ├── arbiter_dbus.v │ │ │ │ │ └── arbiter_ibus.v │ │ │ │ ├── clkgen │ │ │ │ │ └── clkgen.v │ │ │ │ ├── flashrom │ │ │ │ │ ├── README │ │ │ │ │ └── flashrom.v │ │ │ │ ├── gpio │ │ │ │ │ ├── README │ │ │ │ │ └── gpio.v │ │ │ │ ├── include │ │ │ │ │ ├── adbg_defines.v │ │ │ │ │ ├── adbg_or1k_defines.v │ │ │ │ │ ├── adbg_wb_defines.v │ │ │ │ │ ├── dbg_cpu_defines.v │ │ │ │ │ ├── dbg_defines.v │ │ │ │ │ ├── dbg_wb_defines.v │ │ │ │ │ ├── ethmac_defines.v │ │ │ │ │ ├── i2c_master_slave_defines.v │ │ │ │ │ ├── or1200_defines.v │ │ │ │ │ ├── orpsoc-defines.v │ │ │ │ │ ├── orpsoc-params.v │ │ │ │ │ ├── sd_defines.v │ │ │ │ │ ├── tap_defines.v │ │ │ │ │ ├── uart_defines.v │ │ │ │ │ ├── usbhostslave_constants_h.v │ │ │ │ │ ├── usbhostslave_hostcontrol_h.v │ │ │ │ │ ├── usbhostslave_hostslave_h.v │ │ │ │ │ ├── usbhostslave_serialinterfaceengine_h.v │ │ │ │ │ ├── usbhostslave_slavecontrol_h.v │ │ │ │ │ ├── usbhostslave_wishbonebus_h.v │ │ │ │ │ └── vga_defines.v │ │ │ │ ├── orpsoc_top │ │ │ │ │ └── orpsoc_top.v │ │ │ │ ├── sdc_controller │ │ │ │ │ ├── sd_bd.v │ │ │ │ │ ├── sd_clock_divider.v │ │ │ │ │ ├── sd_cmd_master.v │ │ │ │ │ ├── sd_cmd_serial_host.v │ │ │ │ │ ├── sd_controller_wb.v │ │ │ │ │ ├── sd_crc_16.v │ │ │ │ │ ├── sd_crc_7.v │ │ │ │ │ ├── sd_data_master.v │ │ │ │ │ ├── sd_data_serial_host.v │ │ │ │ │ ├── sd_fifo_rx_filler.v │ │ │ │ │ ├── sd_fifo_tx_filler.v │ │ │ │ │ ├── sd_rx_fifo.v │ │ │ │ │ ├── sd_rx_fifo_tb.v │ │ │ │ │ ├── sd_tx_fifo.v │ │ │ │ │ └── sdc_controller.v │ │ │ │ ├── versatile_mem_ctrl │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README │ │ │ │ │ ├── rtl │ │ │ │ │ │ └── verilog │ │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ │ ├── async_fifo_mq.v │ │ │ │ │ │ │ ├── burst_length_counter_defines.v │ │ │ │ │ │ │ ├── cke_delay_counter_defines.v │ │ │ │ │ │ │ ├── codec.v │ │ │ │ │ │ │ ├── copyright.v │ │ │ │ │ │ │ ├── ctrl_counter_defines.v │ │ │ │ │ │ │ ├── dcm_pll.v │ │ │ │ │ │ │ ├── ddr_16.fzm │ │ │ │ │ │ │ ├── ddr_16_defines.v │ │ │ │ │ │ │ ├── ddr_ff.v │ │ │ │ │ │ │ ├── delay.v │ │ │ │ │ │ │ ├── dff_sr.v │ │ │ │ │ │ │ ├── egress_fifo.v │ │ │ │ │ │ │ ├── fifo.v │ │ │ │ │ │ │ ├── fifo_adr_counter_defines.v │ │ │ │ │ │ │ ├── fifo_fill.fzm │ │ │ │ │ │ │ ├── fizzim.pl │ │ │ │ │ │ │ ├── fsm_sdr_16.v │ │ │ │ │ │ │ ├── fsm_wb.v │ │ │ │ │ │ │ ├── gray_counter.v │ │ │ │ │ │ │ ├── inc_adr.v │ │ │ │ │ │ │ ├── latency_counter_defines.v │ │ │ │ │ │ │ ├── pre_delay_counter_defines.v │ │ │ │ │ │ │ ├── ref_counter.v │ │ │ │ │ │ │ ├── ref_counter_defines.v │ │ │ │ │ │ │ ├── ref_delay_counter_defines.v │ │ │ │ │ │ │ ├── sdr_16.fzm │ │ │ │ │ │ │ ├── sdr_16_defines.v │ │ │ │ │ │ │ ├── versatile_counter.xls │ │ │ │ │ │ │ ├── versatile_fifo_async_cmp.v │ │ │ │ │ │ │ ├── versatile_fifo_dual_port_ram_dc_sw.v │ │ │ │ │ │ │ ├── versatile_mem_ctrl_ddr.v │ │ │ │ │ │ │ ├── versatile_mem_ctrl_defines.v │ │ │ │ │ │ │ ├── versatile_mem_ctrl_ip.v │ │ │ │ │ │ │ ├── versatile_mem_ctrl_top.v │ │ │ │ │ │ │ └── versatile_mem_ctrl_wb.v │ │ │ │ │ └── versatile_mem_ctrl.v │ │ │ │ ├── vga_lcd │ │ │ │ │ ├── generic_dpram.v │ │ │ │ │ ├── generic_spram.v │ │ │ │ │ ├── timescale.v │ │ │ │ │ ├── vga_clkgen.v │ │ │ │ │ ├── vga_colproc.v │ │ │ │ │ ├── vga_csm_pb.v │ │ │ │ │ ├── vga_cur_cregs.v │ │ │ │ │ ├── vga_curproc.v │ │ │ │ │ ├── vga_enh_top.v │ │ │ │ │ ├── vga_fifo.v │ │ │ │ │ ├── vga_fifo_dc.v │ │ │ │ │ ├── vga_pgen.v │ │ │ │ │ ├── vga_tgen.v │ │ │ │ │ ├── vga_vtim.v │ │ │ │ │ ├── vga_wb_master.v │ │ │ │ │ └── vga_wb_slave.v │ │ │ │ └── wb_sdram_ctrl │ │ │ │ │ ├── arbiter.v │ │ │ │ │ ├── sdram_ctrl.v │ │ │ │ │ ├── wb_port.v │ │ │ │ │ └── wb_sdram_ctrl.v │ │ │ └── vhdl │ │ │ │ └── adv_debugsys │ │ │ │ └── altera_virtual_jtag.vhd │ │ ├── sim │ │ │ ├── bin │ │ │ │ └── Makefile │ │ │ └── run │ │ │ │ └── Makefile │ │ ├── sw │ │ │ ├── Makefile.inc │ │ │ ├── board │ │ │ │ └── include │ │ │ │ │ └── board.h │ │ │ ├── bootrom │ │ │ │ └── Makefile │ │ │ ├── drivers │ │ │ │ └── usbhostslave │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── include │ │ │ │ │ ├── usbhostslave-host.h │ │ │ │ │ └── usbhostslave-slave.h │ │ │ │ │ ├── usbhostslave-host.c │ │ │ │ │ └── usbhostslave-slave.c │ │ │ └── tests │ │ │ │ ├── i2c_master_slave │ │ │ │ └── sim │ │ │ │ │ ├── Makefile │ │ │ │ │ └── i2c_master_slave-loopback.c │ │ │ │ └── usbhostslave │ │ │ │ └── sim │ │ │ │ ├── Makefile │ │ │ │ ├── usbhostslave-hostsimple.c │ │ │ │ └── usbhostslave-slavesimple.c │ │ └── syn │ │ │ └── quartus │ │ │ ├── bin │ │ │ └── Makefile │ │ │ ├── run │ │ │ └── Makefile │ │ │ ├── sdc │ │ │ ├── JTAG_DEBUG.sdc │ │ │ └── common.sdc │ │ │ └── tcl │ │ │ ├── GENERIC_JTAG_TAP_pin_assignments.tcl │ │ │ ├── GPIO0_pin_assignments.tcl │ │ │ ├── UART0_pin_assignments.tcl │ │ │ ├── VERSATILE_SDRAM_pin_assignments.tcl │ │ │ ├── VGA0_pin_assignments.tcl │ │ │ └── common_pin_assignments.tcl │ └── de2_115 │ │ ├── Makefile.inc │ │ ├── README │ │ ├── backend │ │ └── rtl │ │ │ └── verilog │ │ │ └── pll.v │ │ ├── bench │ │ └── verilog │ │ │ ├── include │ │ │ ├── eth_stim.v │ │ │ ├── orpsoc-testbench-defines.v │ │ │ ├── synthesis-defines.v │ │ │ └── timescale.v │ │ │ ├── orpsoc_testbench.v │ │ │ └── spi_slave.v │ │ ├── rtl │ │ ├── verilog │ │ │ ├── adv_debugsys │ │ │ │ ├── adbg_crc32.v │ │ │ │ ├── adbg_jsp_biu.v │ │ │ │ ├── adbg_jsp_module.v │ │ │ │ ├── adbg_or1k_biu.v │ │ │ │ ├── adbg_or1k_module.v │ │ │ │ ├── adbg_or1k_status_reg.v │ │ │ │ ├── adbg_wb_biu.v │ │ │ │ ├── adbg_wb_module.v │ │ │ │ ├── adv_dbg_if.v │ │ │ │ ├── bytefifo.v │ │ │ │ ├── syncflop.v │ │ │ │ └── syncreg.v │ │ │ ├── arbiter │ │ │ │ ├── README │ │ │ │ ├── arbiter_bytebus.v │ │ │ │ ├── arbiter_dbus.v │ │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ │ └── clkgen.v │ │ │ ├── flashrom │ │ │ │ ├── README │ │ │ │ └── flashrom.v │ │ │ ├── gpio │ │ │ │ ├── README │ │ │ │ └── gpio.v │ │ │ ├── include │ │ │ │ ├── adbg_defines.v │ │ │ │ ├── adbg_or1k_defines.v │ │ │ │ ├── adbg_wb_defines.v │ │ │ │ ├── dbg_cpu_defines.v │ │ │ │ ├── dbg_defines.v │ │ │ │ ├── dbg_wb_defines.v │ │ │ │ ├── ethmac_defines.v │ │ │ │ ├── i2c_master_slave_defines.v │ │ │ │ ├── or1200_defines.v │ │ │ │ ├── orpsoc-defines.v │ │ │ │ ├── orpsoc-params.v │ │ │ │ ├── sd_defines.v │ │ │ │ ├── tap_defines.v │ │ │ │ ├── uart_defines.v │ │ │ │ ├── usbhostslave_constants_h.v │ │ │ │ ├── usbhostslave_hostcontrol_h.v │ │ │ │ ├── usbhostslave_hostslave_h.v │ │ │ │ ├── usbhostslave_serialinterfaceengine_h.v │ │ │ │ ├── usbhostslave_slavecontrol_h.v │ │ │ │ └── usbhostslave_wishbonebus_h.v │ │ │ ├── orpsoc_top │ │ │ │ └── orpsoc_top.v │ │ │ ├── sdc_controller │ │ │ │ ├── sd_bd.v │ │ │ │ ├── sd_clock_divider.v │ │ │ │ ├── sd_cmd_master.v │ │ │ │ ├── sd_cmd_serial_host.v │ │ │ │ ├── sd_controller_wb.v │ │ │ │ ├── sd_crc_16.v │ │ │ │ ├── sd_crc_7.v │ │ │ │ ├── sd_data_master.v │ │ │ │ ├── sd_data_serial_host.v │ │ │ │ ├── sd_fifo_rx_filler.v │ │ │ │ ├── sd_fifo_tx_filler.v │ │ │ │ ├── sd_rx_fifo.v │ │ │ │ ├── sd_rx_fifo_tb.v │ │ │ │ ├── sd_tx_fifo.v │ │ │ │ └── sdc_controller.v │ │ │ └── versatile_mem_ctrl │ │ │ │ ├── Makefile │ │ │ │ ├── README │ │ │ │ ├── rtl │ │ │ │ └── verilog │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── async_fifo_mq.v │ │ │ │ │ ├── burst_length_counter_defines.v │ │ │ │ │ ├── cke_delay_counter_defines.v │ │ │ │ │ ├── codec.v │ │ │ │ │ ├── copyright.v │ │ │ │ │ ├── ctrl_counter_defines.v │ │ │ │ │ ├── dcm_pll.v │ │ │ │ │ ├── ddr_16.fzm │ │ │ │ │ ├── ddr_16_defines.v │ │ │ │ │ ├── ddr_ff.v │ │ │ │ │ ├── delay.v │ │ │ │ │ ├── dff_sr.v │ │ │ │ │ ├── egress_fifo.v │ │ │ │ │ ├── fifo.v │ │ │ │ │ ├── fifo_adr_counter_defines.v │ │ │ │ │ ├── fifo_fill.fzm │ │ │ │ │ ├── fizzim.pl │ │ │ │ │ ├── fsm_sdr_16.v │ │ │ │ │ ├── fsm_wb.v │ │ │ │ │ ├── gray_counter.v │ │ │ │ │ ├── inc_adr.v │ │ │ │ │ ├── latency_counter_defines.v │ │ │ │ │ ├── pre_delay_counter_defines.v │ │ │ │ │ ├── ref_counter.v │ │ │ │ │ ├── ref_counter_defines.v │ │ │ │ │ ├── ref_delay_counter_defines.v │ │ │ │ │ ├── sdr_16.fzm │ │ │ │ │ ├── sdr_16_defines.v │ │ │ │ │ ├── versatile_counter.xls │ │ │ │ │ ├── versatile_fifo_async_cmp.v │ │ │ │ │ ├── versatile_fifo_dual_port_ram_dc_sw.v │ │ │ │ │ ├── versatile_mem_ctrl_ddr.v │ │ │ │ │ ├── versatile_mem_ctrl_defines.v │ │ │ │ │ ├── versatile_mem_ctrl_ip.v │ │ │ │ │ ├── versatile_mem_ctrl_top.v │ │ │ │ │ └── versatile_mem_ctrl_wb.v │ │ │ │ └── versatile_mem_ctrl.v │ │ └── vhdl │ │ │ └── adv_debugsys │ │ │ └── altera_virtual_jtag.vhd │ │ ├── sim │ │ ├── bin │ │ │ └── Makefile │ │ └── run │ │ │ └── Makefile │ │ ├── sw │ │ ├── Makefile.inc │ │ ├── board │ │ │ └── include │ │ │ │ └── board.h │ │ ├── bootrom │ │ │ ├── Makefile │ │ │ └── bootrom.v │ │ ├── drivers │ │ │ └── usbhostslave │ │ │ │ ├── Makefile │ │ │ │ ├── include │ │ │ │ ├── usbhostslave-host.h │ │ │ │ └── usbhostslave-slave.h │ │ │ │ ├── usbhostslave-host.c │ │ │ │ └── usbhostslave-slave.c │ │ └── tests │ │ │ ├── i2c_master_slave │ │ │ └── sim │ │ │ │ ├── Makefile │ │ │ │ └── i2c_master_slave-loopback.c │ │ │ └── usbhostslave │ │ │ └── sim │ │ │ ├── Makefile │ │ │ ├── usbhostslave-hostsimple.c │ │ │ └── usbhostslave-slavesimple.c │ │ └── syn │ │ └── quartus │ │ ├── bin │ │ └── Makefile │ │ ├── run │ │ └── Makefile │ │ ├── sdc │ │ ├── JTAG_DEBUG.sdc │ │ └── common.sdc │ │ └── tcl │ │ ├── GENERIC_JTAG_TAP_pin_assignments.tcl │ │ ├── GPIO0_pin_assignments.tcl │ │ ├── UART0_pin_assignments.tcl │ │ ├── VERSATILE_SDRAM_pin_assignments.tcl │ │ └── common_pin_assignments.tcl └── xilinx │ ├── atlys │ ├── Makefile.inc │ ├── README │ ├── backend │ │ ├── bin │ │ │ └── vga_fifo_dc_gen.ngc │ │ └── par │ │ │ ├── bin │ │ │ ├── Makefile │ │ │ ├── atlys.ucf │ │ │ └── atlys.ucf~ │ │ │ └── run │ │ │ ├── Makefile │ │ │ └── _xmsgs │ │ │ ├── bitgen.xmsgs │ │ │ ├── map.xmsgs │ │ │ ├── ngdbuild.xmsgs │ │ │ └── par.xmsgs │ ├── bench │ │ └── verilog │ │ │ ├── ddr2_model.v │ │ │ ├── include │ │ │ ├── ddr2_model_parameters.v │ │ │ ├── ddr2_model_preload.v │ │ │ ├── eth_phy_defines.v │ │ │ ├── eth_stim.v │ │ │ ├── synthesis-defines.v │ │ │ └── timescale.v │ │ │ ├── or1200_monitor.v │ │ │ ├── orpsoc_testbench.v │ │ │ └── orpsoc_testbench.v~ │ ├── rtl │ │ ├── verilog │ │ │ ├── ac97 │ │ │ │ ├── ac97_cra.v │ │ │ │ ├── ac97_dma_if.v │ │ │ │ ├── ac97_dma_req.v │ │ │ │ ├── ac97_fifo_ctrl.v │ │ │ │ ├── ac97_in_fifo.v │ │ │ │ ├── ac97_int.v │ │ │ │ ├── ac97_out_fifo.v │ │ │ │ ├── ac97_prc.v │ │ │ │ ├── ac97_rf.v │ │ │ │ ├── ac97_rst.v │ │ │ │ ├── ac97_sin.v │ │ │ │ ├── ac97_soc.v │ │ │ │ ├── ac97_sout.v │ │ │ │ ├── ac97_top.v │ │ │ │ └── ac97_wb_if.v │ │ │ ├── arbiter │ │ │ │ ├── arbiter_bytebus.v │ │ │ │ ├── arbiter_bytebus.v~ │ │ │ │ ├── arbiter_dbus.v │ │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ │ └── clkgen.v │ │ │ ├── dma │ │ │ │ ├── wb_dma_ch_arb.v │ │ │ │ ├── wb_dma_ch_pri_enc.v │ │ │ │ ├── wb_dma_ch_rf.v │ │ │ │ ├── wb_dma_ch_sel.v │ │ │ │ ├── wb_dma_de.v │ │ │ │ ├── wb_dma_inc30r.v │ │ │ │ ├── wb_dma_pri_enc_sub.v │ │ │ │ ├── wb_dma_rf.v │ │ │ │ ├── wb_dma_top.v │ │ │ │ ├── wb_dma_wb_if.v │ │ │ │ ├── wb_dma_wb_mast.v │ │ │ │ └── wb_dma_wb_slv.v │ │ │ ├── dvi_gen │ │ │ │ ├── DRAM16XN.v │ │ │ │ ├── convert_30to15_fifo.v │ │ │ │ ├── dcmspi.v │ │ │ │ ├── dvi_encoder.v │ │ │ │ ├── dvi_gen_top.v │ │ │ │ ├── encode.v │ │ │ │ ├── serdes_n_to_1.v │ │ │ │ └── synchro.v │ │ │ ├── fdt │ │ │ │ └── fdt.v │ │ │ ├── gfx │ │ │ │ ├── basic_fifo.v │ │ │ │ ├── div_uu.v │ │ │ │ ├── gfx_blender.v │ │ │ │ ├── gfx_clip.v │ │ │ │ ├── gfx_color.v │ │ │ │ ├── gfx_cuvz.v │ │ │ │ ├── gfx_fragment_processor.v │ │ │ │ ├── gfx_interp.v │ │ │ │ ├── gfx_line.v │ │ │ │ ├── gfx_params.v │ │ │ │ ├── gfx_rasterizer.v │ │ │ │ ├── gfx_renderer.v │ │ │ │ ├── gfx_top.v │ │ │ │ ├── gfx_transform.v │ │ │ │ ├── gfx_triangle.v │ │ │ │ ├── gfx_wbm_read.v │ │ │ │ ├── gfx_wbm_read_arbiter.v │ │ │ │ ├── gfx_wbm_write.v │ │ │ │ ├── gfx_wbs.v │ │ │ │ └── timescale.v │ │ │ ├── gpio │ │ │ │ ├── README │ │ │ │ ├── gpio.v │ │ │ │ └── gpio.v~ │ │ │ ├── include │ │ │ │ ├── ac97_defines.v │ │ │ │ ├── dbg_cpu_defines.v │ │ │ │ ├── dbg_defines.v │ │ │ │ ├── dbg_wb_defines.v │ │ │ │ ├── ethmac_defines.v │ │ │ │ ├── i2c_master_slave_defines.v │ │ │ │ ├── or1200_defines.v │ │ │ │ ├── orpsoc-defines.v │ │ │ │ ├── orpsoc-defines.v~ │ │ │ │ ├── orpsoc-params.v │ │ │ │ ├── orpsoc-params.v~ │ │ │ │ ├── tap_defines.v │ │ │ │ ├── uart_defines.v │ │ │ │ ├── vga_defines.v │ │ │ │ ├── wb_dma_defines.v │ │ │ │ └── xilinx_ddr2_params.v │ │ │ ├── ledtest │ │ │ │ ├── .svn │ │ │ │ │ ├── all-wcprops │ │ │ │ │ ├── entries │ │ │ │ │ └── text-base │ │ │ │ │ │ ├── ledmod.v.svn-base │ │ │ │ │ │ ├── ledtest.v.svn-base │ │ │ │ │ │ └── ledtest_wb_slave.v.svn-base │ │ │ │ ├── ledmod.v │ │ │ │ ├── ledmod.v~ │ │ │ │ ├── ledtest.v │ │ │ │ ├── ledtest.v~ │ │ │ │ ├── ledtest_wb_slave.v │ │ │ │ └── ledtest_wb_slave.v~ │ │ │ ├── lfsr │ │ │ │ └── lfsr.v │ │ │ ├── orpsoc_top │ │ │ │ ├── orpsoc_top.v │ │ │ │ └── orpsoc_top.v~ │ │ │ ├── ps2 │ │ │ │ ├── ps2.v │ │ │ │ └── ps2_wishbone.v │ │ │ ├── verilog │ │ │ │ ├── ac97 │ │ │ │ │ ├── ac97_cra.v │ │ │ │ │ ├── ac97_dma_if.v │ │ │ │ │ ├── ac97_dma_req.v │ │ │ │ │ ├── ac97_fifo_ctrl.v │ │ │ │ │ ├── ac97_in_fifo.v │ │ │ │ │ ├── ac97_int.v │ │ │ │ │ ├── ac97_out_fifo.v │ │ │ │ │ ├── ac97_prc.v │ │ │ │ │ ├── ac97_rf.v │ │ │ │ │ ├── ac97_rst.v │ │ │ │ │ ├── ac97_sin.v │ │ │ │ │ ├── ac97_soc.v │ │ │ │ │ ├── ac97_sout.v │ │ │ │ │ ├── ac97_top.v │ │ │ │ │ └── ac97_wb_if.v │ │ │ │ ├── arbiter │ │ │ │ │ ├── arbiter_bytebus.v │ │ │ │ │ ├── arbiter_bytebus.v~ │ │ │ │ │ ├── arbiter_dbus.v │ │ │ │ │ └── arbiter_ibus.v │ │ │ │ ├── clkgen │ │ │ │ │ └── clkgen.v │ │ │ │ ├── dvi_gen │ │ │ │ │ ├── DRAM16XN.v │ │ │ │ │ ├── convert_30to15_fifo.v │ │ │ │ │ ├── dcmspi.v │ │ │ │ │ ├── dvi_encoder.v │ │ │ │ │ ├── dvi_gen_top.v │ │ │ │ │ ├── encode.v │ │ │ │ │ ├── serdes_n_to_1.v │ │ │ │ │ └── synchro.v │ │ │ │ ├── gpio │ │ │ │ │ ├── README │ │ │ │ │ ├── gpio.v │ │ │ │ │ └── gpio.v~ │ │ │ │ └── verilog │ │ │ │ │ ├── ac97 │ │ │ │ │ ├── ac97_cra.v │ │ │ │ │ ├── ac97_dma_if.v │ │ │ │ │ ├── ac97_dma_req.v │ │ │ │ │ ├── ac97_fifo_ctrl.v │ │ │ │ │ ├── ac97_in_fifo.v │ │ │ │ │ ├── ac97_int.v │ │ │ │ │ ├── ac97_out_fifo.v │ │ │ │ │ ├── ac97_prc.v │ │ │ │ │ ├── ac97_rf.v │ │ │ │ │ ├── ac97_rst.v │ │ │ │ │ ├── ac97_sin.v │ │ │ │ │ ├── ac97_soc.v │ │ │ │ │ ├── ac97_sout.v │ │ │ │ │ ├── ac97_top.v │ │ │ │ │ └── ac97_wb_if.v │ │ │ │ │ ├── arbiter │ │ │ │ │ ├── arbiter_bytebus.v │ │ │ │ │ ├── arbiter_bytebus.v~ │ │ │ │ │ ├── arbiter_dbus.v │ │ │ │ │ └── arbiter_ibus.v │ │ │ │ │ ├── clkgen │ │ │ │ │ └── clkgen.v │ │ │ │ │ ├── dvi_gen │ │ │ │ │ ├── DRAM16XN.v │ │ │ │ │ ├── convert_30to15_fifo.v │ │ │ │ │ ├── dcmspi.v │ │ │ │ │ ├── dvi_encoder.v │ │ │ │ │ ├── dvi_gen_top.v │ │ │ │ │ ├── encode.v │ │ │ │ │ ├── serdes_n_to_1.v │ │ │ │ │ └── synchro.v │ │ │ │ │ ├── gpio │ │ │ │ │ ├── README │ │ │ │ │ ├── gpio.v │ │ │ │ │ └── gpio.v~ │ │ │ │ │ └── verilog │ │ │ │ │ ├── ac97 │ │ │ │ │ ├── ac97_cra.v │ │ │ │ │ ├── ac97_dma_if.v │ │ │ │ │ ├── ac97_dma_req.v │ │ │ │ │ ├── ac97_fifo_ctrl.v │ │ │ │ │ ├── ac97_in_fifo.v │ │ │ │ │ ├── ac97_int.v │ │ │ │ │ ├── ac97_out_fifo.v │ │ │ │ │ ├── ac97_prc.v │ │ │ │ │ ├── ac97_rf.v │ │ │ │ │ ├── ac97_rst.v │ │ │ │ │ ├── ac97_sin.v │ │ │ │ │ ├── ac97_soc.v │ │ │ │ │ ├── ac97_sout.v │ │ │ │ │ ├── ac97_top.v │ │ │ │ │ └── ac97_wb_if.v │ │ │ │ │ ├── arbiter │ │ │ │ │ ├── arbiter_bytebus.v │ │ │ │ │ ├── arbiter_bytebus.v~ │ │ │ │ │ ├── arbiter_dbus.v │ │ │ │ │ └── arbiter_ibus.v │ │ │ │ │ ├── clkgen │ │ │ │ │ └── clkgen.v │ │ │ │ │ ├── dvi_gen │ │ │ │ │ ├── DRAM16XN.v │ │ │ │ │ ├── convert_30to15_fifo.v │ │ │ │ │ ├── dcmspi.v │ │ │ │ │ ├── dvi_encoder.v │ │ │ │ │ ├── dvi_gen_top.v │ │ │ │ │ ├── encode.v │ │ │ │ │ ├── serdes_n_to_1.v │ │ │ │ │ └── synchro.v │ │ │ │ │ └── gpio │ │ │ │ │ ├── README │ │ │ │ │ ├── gpio.v │ │ │ │ │ └── gpio.v~ │ │ │ ├── vga_lcd │ │ │ │ ├── generic_dpram.v │ │ │ │ ├── generic_spram.v │ │ │ │ ├── timescale.v │ │ │ │ ├── vga_clkgen.v │ │ │ │ ├── vga_colproc.v │ │ │ │ ├── vga_csm_pb.v │ │ │ │ ├── vga_cur_cregs.v │ │ │ │ ├── vga_curproc.v │ │ │ │ ├── vga_enh_top.v │ │ │ │ ├── vga_fifo.v │ │ │ │ ├── vga_fifo_dc.v │ │ │ │ ├── vga_fifo_dc_gen.v │ │ │ │ ├── vga_pgen.v │ │ │ │ ├── vga_tgen.v │ │ │ │ ├── vga_vtim.v │ │ │ │ ├── vga_wb_master.v │ │ │ │ └── vga_wb_slave.v │ │ │ └── xilinx_ddr2 │ │ │ │ ├── README │ │ │ │ ├── ddr2_mig.v │ │ │ │ ├── infrastructure.v │ │ │ │ ├── iodrp_controller.v │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ ├── mcb_ui_top.v │ │ │ │ ├── memc_wrapper.v │ │ │ │ ├── xilinx_ddr2.v │ │ │ │ └── xilinx_ddr2_if.v │ │ └── verilog_old │ │ │ ├── ac97 │ │ │ ├── ac97_cra.v │ │ │ ├── ac97_dma_if.v │ │ │ ├── ac97_dma_req.v │ │ │ ├── ac97_fifo_ctrl.v │ │ │ ├── ac97_in_fifo.v │ │ │ ├── ac97_int.v │ │ │ ├── ac97_out_fifo.v │ │ │ ├── ac97_prc.v │ │ │ ├── ac97_rf.v │ │ │ ├── ac97_rst.v │ │ │ ├── ac97_sin.v │ │ │ ├── ac97_soc.v │ │ │ ├── ac97_sout.v │ │ │ ├── ac97_top.v │ │ │ └── ac97_wb_if.v │ │ │ ├── arbiter │ │ │ ├── arbiter_bytebus.v │ │ │ ├── arbiter_bytebus.v~ │ │ │ ├── arbiter_dbus.v │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ └── clkgen.v │ │ │ ├── dma │ │ │ ├── wb_dma_ch_arb.v │ │ │ ├── wb_dma_ch_pri_enc.v │ │ │ ├── wb_dma_ch_rf.v │ │ │ ├── wb_dma_ch_sel.v │ │ │ ├── wb_dma_de.v │ │ │ ├── wb_dma_inc30r.v │ │ │ ├── wb_dma_pri_enc_sub.v │ │ │ ├── wb_dma_rf.v │ │ │ ├── wb_dma_top.v │ │ │ ├── wb_dma_wb_if.v │ │ │ ├── wb_dma_wb_mast.v │ │ │ └── wb_dma_wb_slv.v │ │ │ ├── dvi_gen │ │ │ ├── DRAM16XN.v │ │ │ ├── convert_30to15_fifo.v │ │ │ ├── dcmspi.v │ │ │ ├── dvi_encoder.v │ │ │ ├── dvi_gen_top.v │ │ │ ├── encode.v │ │ │ ├── serdes_n_to_1.v │ │ │ └── synchro.v │ │ │ ├── fdt │ │ │ └── fdt.v │ │ │ ├── gpio │ │ │ ├── README │ │ │ ├── gpio.v │ │ │ └── gpio.v~ │ │ │ ├── include │ │ │ ├── ac97_defines.v │ │ │ ├── dbg_cpu_defines.v │ │ │ ├── dbg_defines.v │ │ │ ├── dbg_wb_defines.v │ │ │ ├── ethmac_defines.v │ │ │ ├── i2c_master_slave_defines.v │ │ │ ├── or1200_defines.v │ │ │ ├── orpsoc-defines.v │ │ │ ├── orpsoc-defines.v~ │ │ │ ├── orpsoc-params.v │ │ │ ├── orpsoc-params.v~ │ │ │ ├── tap_defines.v │ │ │ ├── uart_defines.v │ │ │ ├── vga_defines.v │ │ │ ├── wb_dma_defines.v │ │ │ └── xilinx_ddr2_params.v │ │ │ ├── ledtest │ │ │ ├── .svn │ │ │ │ ├── all-wcprops │ │ │ │ ├── entries │ │ │ │ └── text-base │ │ │ │ │ ├── ledmod.v.svn-base │ │ │ │ │ ├── ledtest.v.svn-base │ │ │ │ │ └── ledtest_wb_slave.v.svn-base │ │ │ ├── ledmod.v │ │ │ ├── ledmod.v~ │ │ │ ├── ledtest.v │ │ │ ├── ledtest.v~ │ │ │ ├── ledtest_wb_slave.v │ │ │ └── ledtest_wb_slave.v~ │ │ │ ├── lfsr │ │ │ └── lfsr.v │ │ │ ├── orpsoc_top │ │ │ ├── orpsoc_top.v │ │ │ └── orpsoc_top.v~ │ │ │ ├── ps2 │ │ │ ├── ps2.v │ │ │ └── ps2_wishbone.v │ │ │ ├── vga_lcd │ │ │ ├── generic_dpram.v │ │ │ ├── generic_spram.v │ │ │ ├── timescale.v │ │ │ ├── vga_clkgen.v │ │ │ ├── vga_colproc.v │ │ │ ├── vga_csm_pb.v │ │ │ ├── vga_cur_cregs.v │ │ │ ├── vga_curproc.v │ │ │ ├── vga_enh_top.v │ │ │ ├── vga_fifo.v │ │ │ ├── vga_fifo_dc.v │ │ │ ├── vga_fifo_dc_gen.v │ │ │ ├── vga_pgen.v │ │ │ ├── vga_tgen.v │ │ │ ├── vga_vtim.v │ │ │ ├── vga_wb_master.v │ │ │ └── vga_wb_slave.v │ │ │ └── xilinx_ddr2 │ │ │ ├── README │ │ │ ├── ddr2_mig.v │ │ │ ├── infrastructure.v │ │ │ ├── iodrp_controller.v │ │ │ ├── iodrp_mcb_controller.v │ │ │ ├── mcb_raw_wrapper.v │ │ │ ├── mcb_soft_calibration.v │ │ │ ├── mcb_soft_calibration_top.v │ │ │ ├── mcb_ui_top.v │ │ │ ├── memc_wrapper.v │ │ │ ├── xilinx_ddr2.v │ │ │ └── xilinx_ddr2_if.v │ ├── sim │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── atlys-or1ksim.cfg │ │ └── run │ │ │ └── Makefile │ ├── sw │ │ ├── Makefile.inc │ │ ├── board │ │ │ └── include │ │ │ │ ├── board.h │ │ │ │ └── board.h~ │ │ ├── bootrom │ │ │ ├── Makefile │ │ │ ├── bootrom.v │ │ │ ├── bootrom.v.led │ │ │ ├── led │ │ │ └── led.S~ │ │ └── device_tree │ │ │ ├── atlys.dtb │ │ │ ├── atlys.dts │ │ │ └── device_tree_blob.v │ └── syn │ │ └── xst │ │ ├── bin │ │ └── Makefile │ │ ├── coregen │ │ ├── coregen.cgp │ │ └── xilinx_ddr2_if_cache.xco │ │ └── run │ │ ├── .lso │ │ └── Makefile │ ├── ml501 │ ├── Makefile.inc │ ├── README │ ├── backend │ │ ├── bin │ │ │ └── xilinx_ddr2_if_cache.ngc │ │ └── par │ │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── ml501.ucf │ │ │ └── run │ │ │ └── Makefile │ ├── bench │ │ └── verilog │ │ │ ├── cy7c1354.v │ │ │ ├── ddr2_model.v │ │ │ ├── include │ │ │ ├── ddr2_model_parameters.v │ │ │ ├── ddr2_model_preload.v │ │ │ ├── eth_phy_defines.v │ │ │ ├── eth_stim.v │ │ │ ├── synthesis-defines.v │ │ │ └── timescale.v │ │ │ └── orpsoc_testbench.v │ ├── rtl │ │ └── verilog │ │ │ ├── arbiter │ │ │ ├── arbiter_bytebus.v │ │ │ ├── arbiter_dbus.v │ │ │ └── arbiter_ibus.v │ │ │ ├── clkgen │ │ │ └── clkgen.v │ │ │ ├── gpio │ │ │ ├── README │ │ │ └── gpio.v │ │ │ ├── include │ │ │ ├── dbg_cpu_defines.v │ │ │ ├── dbg_defines.v │ │ │ ├── dbg_wb_defines.v │ │ │ ├── ethmac_defines.v │ │ │ ├── i2c_master_slave_defines.v │ │ │ ├── or1200_defines.v │ │ │ ├── orpsoc-defines.v │ │ │ ├── orpsoc-params.v │ │ │ ├── tap_defines.v │ │ │ ├── uart_defines.v │ │ │ └── xilinx_ddr2_params.v │ │ │ ├── lfsr │ │ │ └── lfsr.v │ │ │ ├── orpsoc_top │ │ │ └── orpsoc_top.v │ │ │ ├── xilinx_ddr2 │ │ │ ├── README │ │ │ ├── ddr2_chipscope.v │ │ │ ├── ddr2_ctrl.v │ │ │ ├── ddr2_idelay_ctrl.v │ │ │ ├── ddr2_infrastructure.v │ │ │ ├── ddr2_mem_if_top.v │ │ │ ├── ddr2_mig.v │ │ │ ├── ddr2_phy_calib.v │ │ │ ├── ddr2_phy_ctl_io.v │ │ │ ├── ddr2_phy_dm_iob.v │ │ │ ├── ddr2_phy_dq_iob.v │ │ │ ├── ddr2_phy_dqs_iob.v │ │ │ ├── ddr2_phy_init.v │ │ │ ├── ddr2_phy_io.v │ │ │ ├── ddr2_phy_top.v │ │ │ ├── ddr2_phy_write.v │ │ │ ├── ddr2_top.v │ │ │ ├── ddr2_usr_addr_fifo.v │ │ │ ├── ddr2_usr_rd.v │ │ │ ├── ddr2_usr_top.v │ │ │ ├── ddr2_usr_wr.v │ │ │ ├── xilinx_ddr2.v │ │ │ ├── xilinx_ddr2_if.v │ │ │ └── xilinx_ddr2_if_cache.v │ │ │ └── xilinx_ssram │ │ │ └── xilinx_ssram.v │ ├── sim │ │ ├── bin │ │ │ ├── Makefile │ │ │ └── ml501-or1ksim.cfg │ │ └── run │ │ │ └── Makefile │ ├── sw │ │ ├── Makefile.inc │ │ ├── board │ │ │ └── include │ │ │ │ └── board.h │ │ ├── bootrom │ │ │ └── Makefile │ │ └── tests │ │ │ └── ethmac │ │ │ └── sim │ │ │ ├── Makefile │ │ │ ├── ethmac-rx.c │ │ │ ├── ethmac-rxtx.c │ │ │ ├── ethmac-rxtxcallresponse.c │ │ │ └── ethmac-tx.c │ └── syn │ │ └── xst │ │ ├── bin │ │ └── Makefile │ │ └── run │ │ └── Makefile │ └── s3adsp1800 │ ├── Makefile.inc │ ├── README │ ├── backend │ ├── bin │ │ └── s3adsp_ddr2_cache.ngc │ └── par │ │ ├── bin │ │ ├── Makefile │ │ └── s3adsp1800.ucf │ │ └── run │ │ └── Makefile │ ├── bench │ └── verilog │ │ ├── ddr2_model.v │ │ ├── include │ │ ├── ddr2_model_parameters.v │ │ ├── ddr2_model_preload.v │ │ ├── eth_phy_defines.v │ │ ├── eth_stim.v │ │ ├── synthesis-defines.v │ │ └── timescale.v │ │ └── orpsoc_testbench.v │ ├── rtl │ └── verilog │ │ ├── arbiter │ │ ├── arbiter_bytebus.v │ │ ├── arbiter_dbus.v │ │ └── arbiter_ibus.v │ │ ├── clkgen │ │ └── clkgen.v │ │ ├── gpio │ │ ├── README │ │ └── gpio.v │ │ ├── include │ │ ├── dbg_cpu_defines.v │ │ ├── dbg_defines.v │ │ ├── dbg_wb_defines.v │ │ ├── ethmac_defines.v │ │ ├── i2c_master_slave_defines.v │ │ ├── or1200_defines.v │ │ ├── orpsoc-defines.v │ │ ├── orpsoc-params.v │ │ ├── s3adsp_ddr2_parameters_0.v │ │ ├── tap_defines.v │ │ └── uart_defines.v │ │ ├── orpsoc_top │ │ └── orpsoc_top.v │ │ └── xilinx_s3adsp_ddr2 │ │ ├── s3adsp_ddr2.v │ │ ├── s3adsp_ddr2_cache.v │ │ ├── s3adsp_ddr2_cal_ctl.v │ │ ├── s3adsp_ddr2_cal_top.v │ │ ├── s3adsp_ddr2_clk_dcm.v │ │ ├── s3adsp_ddr2_controller_0.v │ │ ├── s3adsp_ddr2_controller_iobs_0.v │ │ ├── s3adsp_ddr2_data_path_0.v │ │ ├── s3adsp_ddr2_data_path_iobs_0.v │ │ ├── s3adsp_ddr2_data_read_0.v │ │ ├── s3adsp_ddr2_data_read_controller_0.v │ │ ├── s3adsp_ddr2_data_write_0.v │ │ ├── s3adsp_ddr2_dqs_delay.v │ │ ├── s3adsp_ddr2_fifo_0_wr_en_0.v │ │ ├── s3adsp_ddr2_fifo_1_wr_en_0.v │ │ ├── s3adsp_ddr2_infrastructure.v │ │ ├── s3adsp_ddr2_infrastructure_iobs_0.v │ │ ├── s3adsp_ddr2_infrastructure_top.v │ │ ├── s3adsp_ddr2_iobs_0.v │ │ ├── s3adsp_ddr2_ram8d_0.v │ │ ├── s3adsp_ddr2_rd_gray_cntr.v │ │ ├── s3adsp_ddr2_s3_dm_iob.v │ │ ├── s3adsp_ddr2_s3_dq_iob.v │ │ ├── s3adsp_ddr2_s3_dqs_iob.v │ │ ├── s3adsp_ddr2_tap_dly.v │ │ ├── s3adsp_ddr2_top_0.v │ │ ├── s3adsp_ddr2_wr_gray_cntr.v │ │ ├── xilinx_s3adsp_ddr2.v │ │ └── xilinx_s3adsp_ddr2_if.v │ ├── sim │ ├── bin │ │ └── Makefile │ └── run │ │ └── Makefile │ ├── sw │ ├── Makefile.inc │ ├── board │ │ └── include │ │ │ └── board.h │ ├── bootrom │ │ ├── Makefile │ │ └── bootrom.v │ └── tests │ │ ├── ddr2cache │ │ └── sim │ │ │ ├── Makefile │ │ │ ├── ddr2cache-1.S │ │ │ └── ddr2cache-2.S │ │ └── ethmac │ │ └── sim │ │ ├── Makefile │ │ ├── ethmac-rx.c │ │ ├── ethmac-rxtx.c │ │ ├── ethmac-rxtxcallresponse.c │ │ └── ethmac-tx.c │ └── syn │ └── xst │ ├── bin │ └── Makefile │ └── run │ └── Makefile ├── doc ├── Makefile ├── Makefile.am ├── Makefile.in ├── aclocal.m4 ├── autom4te.cache │ ├── output.0 │ ├── output.1 │ ├── output.2 │ ├── requests │ ├── traces.0 │ ├── traces.1 │ └── traces.2 ├── config.log ├── config.status ├── config.texi ├── configure ├── configure.in ├── fdl-1.2.texi ├── install-sh ├── missing ├── orpsoc.aux ├── orpsoc.cp ├── orpsoc.cps ├── orpsoc.fn ├── orpsoc.info ├── orpsoc.ky ├── orpsoc.log ├── orpsoc.pdf ├── orpsoc.pg ├── orpsoc.texi ├── orpsoc.toc ├── orpsoc.tp ├── orpsoc.vr └── texinfo.tex ├── rtl └── verilog │ ├── arbiter │ ├── README │ ├── arbiter_bytebus.v │ ├── arbiter_dbus.v │ └── arbiter_ibus.v │ ├── cfi_ctrl │ ├── cfi_ctrl.v │ └── cfi_ctrl_engine.v │ ├── clkgen │ ├── README │ └── clkgen.v │ ├── dbg_if │ ├── dbg_cpu.v │ ├── dbg_cpu_registers.v │ ├── dbg_crc32_d1.v │ ├── dbg_if.v │ ├── dbg_register.v │ └── dbg_wb.v │ ├── ethmac │ ├── README │ ├── eth_clockgen.v │ ├── eth_crc.v │ ├── eth_fifo.v │ ├── eth_maccontrol.v │ ├── eth_macstatus.v │ ├── eth_miim.v │ ├── eth_outputcontrol.v │ ├── eth_random.v │ ├── eth_receivecontrol.v │ ├── eth_register.v │ ├── eth_registers.v │ ├── eth_rxaddrcheck.v │ ├── eth_rxcounters.v │ ├── eth_rxethmac.v │ ├── eth_rxstatem.v │ ├── eth_shiftreg.v │ ├── eth_spram_256x32.v │ ├── eth_transmitcontrol.v │ ├── eth_txcounters.v │ ├── eth_txethmac.v │ ├── eth_txstatem.v │ ├── eth_wishbone.v │ ├── ethmac.v │ └── xilinx_dist_ram_16x32.v │ ├── gfx │ ├── basic_fifo.v │ ├── div_uu.v │ ├── gfx_blender.v │ ├── gfx_clip.v │ ├── gfx_color.v │ ├── gfx_cuvz.v │ ├── gfx_fragment_processor.v │ ├── gfx_interp.v │ ├── gfx_line.v │ ├── gfx_params.v │ ├── gfx_rasterizer.v │ ├── gfx_renderer.v │ ├── gfx_top.v │ ├── gfx_transform.v │ ├── gfx_triangle.v │ ├── gfx_wbm_read.v │ ├── gfx_wbm_read_arbiter.v │ ├── gfx_wbm_write.v │ ├── gfx_wbs.v │ └── timescale.v │ ├── i2c_master_slave │ ├── README │ ├── i2c_master_bit_ctrl.v │ ├── i2c_master_byte_ctrl.v │ └── i2c_master_slave.v │ ├── include │ ├── dbg_cpu_defines.v │ ├── dbg_defines.v │ ├── dbg_wb_defines.v │ ├── ethmac_defines.v │ ├── i2c_master_slave_defines.v │ ├── or1200_defines.v │ ├── orpsoc-defines.v │ ├── orpsoc-params.v │ ├── tap_defines.v │ ├── uart_defines.v │ ├── usbhostslave_constants_h.v │ ├── usbhostslave_hostcontrol_h.v │ ├── usbhostslave_hostslave_h.v │ ├── usbhostslave_serialinterfaceengine_h.v │ ├── usbhostslave_slavecontrol_h.v │ └── usbhostslave_wishbonebus_h.v │ ├── intgen │ └── intgen.v │ ├── jtag_tap │ ├── README │ └── jtag_tap.v │ ├── or1200 │ ├── or1200_alu.v │ ├── or1200_amultp2_32x32.v │ ├── or1200_cfgr.v │ ├── or1200_cpu.v │ ├── or1200_ctrl.v │ ├── or1200_dc_fsm.v │ ├── or1200_dc_ram.v │ ├── or1200_dc_tag.v │ ├── or1200_dc_top.v │ ├── or1200_dmmu_tlb.v │ ├── or1200_dmmu_top.v │ ├── or1200_dpram.v │ ├── or1200_dpram_256x32.v │ ├── or1200_dpram_32x32.v │ ├── or1200_du.v │ ├── or1200_except.v │ ├── or1200_fpu.v │ ├── or1200_fpu_addsub.v │ ├── or1200_fpu_arith.v │ ├── or1200_fpu_div.v │ ├── or1200_fpu_fcmp.v │ ├── or1200_fpu_intfloat_conv.v │ ├── or1200_fpu_mul.v │ ├── or1200_fpu_post_norm_addsub.v │ ├── or1200_fpu_post_norm_div.v │ ├── or1200_fpu_post_norm_intfloat_conv.v │ ├── or1200_fpu_post_norm_mul.v │ ├── or1200_fpu_pre_norm_addsub.v │ ├── or1200_fpu_pre_norm_div.v │ ├── or1200_fpu_pre_norm_mul.v │ ├── or1200_freeze.v │ ├── or1200_genpc.v │ ├── or1200_gmultp2_32x32.v │ ├── or1200_ic_fsm.v │ ├── or1200_ic_ram.v │ ├── or1200_ic_tag.v │ ├── or1200_ic_top.v │ ├── or1200_if.v │ ├── or1200_immu_tlb.v │ ├── or1200_immu_top.v │ ├── or1200_iwb_biu.v │ ├── or1200_lsu.v │ ├── or1200_mem2reg.v │ ├── or1200_mult_mac.v │ ├── or1200_operandmuxes.v │ ├── or1200_pic.v │ ├── or1200_pm.v │ ├── or1200_qmem_top.v │ ├── or1200_reg2mem.v │ ├── or1200_rf.v │ ├── or1200_rfram_generic.v │ ├── or1200_sb.v │ ├── or1200_sb_fifo.v │ ├── or1200_spram.v │ ├── or1200_spram_1024x32.v │ ├── or1200_spram_1024x32_bw.v │ ├── or1200_spram_1024x8.v │ ├── or1200_spram_128x32.v │ ├── or1200_spram_2048x32.v │ ├── or1200_spram_2048x32_bw.v │ ├── or1200_spram_2048x8.v │ ├── or1200_spram_256x21.v │ ├── or1200_spram_32_bw.v │ ├── or1200_spram_32x24.v │ ├── or1200_spram_512x20.v │ ├── or1200_spram_64x14.v │ ├── or1200_spram_64x22.v │ ├── or1200_spram_64x24.v │ ├── or1200_sprs.v │ ├── or1200_top.v │ ├── or1200_tpram_32x32.v │ ├── or1200_tt.v │ ├── or1200_wb_biu.v │ ├── or1200_wbmux.v │ └── or1200_xcv_ram32x8d.v │ ├── orpsoc_top │ └── orpsoc_top.v │ ├── ram_wb │ ├── ram_wb.v │ └── ram_wb_b3.v │ ├── rom │ ├── README │ └── rom.v │ ├── simple_spi │ ├── README │ ├── fifo4.v │ └── simple_spi.v │ ├── smii │ ├── README │ ├── smii.v │ ├── smii_if.v │ └── smii_sync.v │ ├── uart16550 │ ├── README │ ├── raminfr.v │ ├── uart16550.v │ ├── uart_debug_if.v │ ├── uart_receiver.v │ ├── uart_regs.v │ ├── uart_rfifo.v │ ├── uart_sync_flops.v │ ├── uart_tfifo.v │ ├── uart_transmitter.v │ └── uart_wb.v │ ├── usbhostslave │ ├── HCTxPortArbiter.v │ ├── README │ ├── RxFifo.v │ ├── RxfifoBI.v │ ├── SCTxPortArbiter.v │ ├── SIEReceiver.v │ ├── SIETransmitter.v │ ├── SOFController.v │ ├── SOFTransmit.v │ ├── TxFifo.v │ ├── TxfifoBI.v │ ├── USBHostControlBI.v │ ├── USBSlaveControlBI.v │ ├── USBTxWireArbiter.v │ ├── directControl.v │ ├── dpMem_dc.v │ ├── endpMux.v │ ├── fifoMux.v │ ├── fifoRTL.v │ ├── getPacket.v │ ├── hostSlaveMux.v │ ├── hostSlaveMuxBI.v │ ├── hostcontroller.v │ ├── lineControlUpdate.v │ ├── processRxBit.v │ ├── processRxByte.v │ ├── processTxByte.v │ ├── readUSBWireData.v │ ├── rxStatusMonitor.v │ ├── sendPacket.v │ ├── sendPacketArbiter.v │ ├── sendPacketCheckPreamble.v │ ├── slaveDirectControl.v │ ├── slaveGetPacket.v │ ├── slaveRxStatusMonitor.v │ ├── slaveSendPacket.v │ ├── slavecontroller.v │ ├── speedCtrlMux.v │ ├── updateCRC16.v │ ├── updateCRC5.v │ ├── usbHostControl.v │ ├── usbSerialInterfaceEngine.v │ ├── usbSlaveControl.v │ ├── usbhost.v │ ├── usbhostslave.v │ ├── usbslave.v │ ├── wishBoneBI.v │ └── writeUSBWireData.v │ ├── wb_ram_b3 │ └── wb_ram_b3.v │ └── wb_switch_b3 │ └── wb_switch_b3.v ├── scripts └── make │ ├── Makefile-board-benchsrc.inc │ ├── Makefile-board-definesparse.inc │ ├── Makefile-board-icarus.inc │ ├── Makefile-board-modelsim.inc │ ├── Makefile-board-paths.inc │ ├── Makefile-board-rtlmodules.inc │ ├── Makefile-board-simclean.inc │ ├── Makefile-board-sw.inc │ ├── Makefile-board-tops.inc │ ├── Makefile-misc.inc │ ├── Makefile-rtltestrules.inc │ ├── Makefile-sim-definesgen.inc │ ├── Makefile-simulators.inc │ └── Makefile-swrules.inc ├── sim ├── bin │ ├── Makefile │ ├── definesgen.inc │ └── refdesign-or1ksim.cfg └── run │ └── Makefile └── sw ├── Makefile.inc ├── README ├── apps ├── cfi_ctrl_programmer │ ├── Makefile │ ├── cfi_ctrl_programmer.c │ └── cfi_ctrl_programmer.ld ├── dhry │ ├── Makefile │ ├── dhry.c │ └── dhry.h ├── spiflash │ ├── Makefile │ ├── README │ ├── spiflash-program.c │ └── spiflash-program.ld └── testfloat │ ├── Makefile │ ├── README │ ├── fail.c │ ├── fail.h │ ├── milieu.h │ ├── or1k-gcc.h │ ├── random.c │ ├── random.h │ ├── slowfloat.c │ ├── slowfloat.h │ ├── softfloat.c │ ├── softfloat.h │ ├── systflags.c │ ├── systflags.h │ ├── systfloat.S │ ├── systfloat.h │ ├── systmodes.c │ ├── systmodes.h │ ├── testCases.c │ ├── testCases.h │ ├── testFunction.c │ ├── testFunction.h │ ├── testLoops.c │ ├── testLoops.h │ ├── testfloat.c │ ├── testsoftfloat.c │ ├── writeHex.c │ └── writeHex.h ├── board └── include │ └── board.h ├── bootrom ├── Makefile ├── bootrom.S └── bootrom.S~ ├── drivers ├── cfi-ctrl │ ├── Makefile │ ├── cfi_ctrl.c │ └── include │ │ └── cfi_ctrl.h ├── ethmac │ ├── Makefile │ ├── ethmac.c │ └── include │ │ ├── eth-phy-mii.h │ │ └── ethmac.h ├── i2c_master_slave │ ├── Makefile │ ├── i2c_master_slave.c │ └── include │ │ └── i2c_master_slave.h ├── or1200 │ ├── Makefile │ ├── cache.S │ ├── crt0.S │ ├── exceptions.c │ ├── include │ │ ├── int.h │ │ ├── or1200-utils.h │ │ └── spr-defs.h │ ├── int.c │ ├── link.ld │ ├── mmu.S │ └── or1200-utils.c ├── simple-spi │ ├── Makefile │ ├── include │ │ └── simple-spi.h │ └── simple-spi.c └── uart │ ├── Makefile │ ├── include │ └── uart.h │ └── uart.c ├── lib ├── Makefile ├── include │ ├── cpu-utils.h │ ├── lib-utils.h │ └── printf.h ├── lib-utils.c └── printf.c ├── tests ├── cfi_ctrl │ ├── board │ │ ├── Makefile │ │ ├── cfi_ctrl-readid.c │ │ └── cfi_ctrl-simple.c │ └── sim │ │ ├── Makefile │ │ ├── cfi_ctrl-readid.c │ │ └── cfi_ctrl-simple.c ├── ethmac │ ├── board │ │ ├── Makefile │ │ └── ethmac-ping.c │ └── sim │ │ ├── Makefile │ │ ├── ethmac-rx.c │ │ ├── ethmac-rxtx.c │ │ ├── ethmac-rxtxcallresponse.c │ │ ├── ethmac-rxtxoverflow.c │ │ └── ethmac-tx.c ├── or1200 │ ├── board │ │ ├── Makefile │ │ ├── or1200-configdetect.c │ │ ├── or1200-div.c │ │ ├── or1200-mmu.c │ │ ├── or1200-mul.c │ │ ├── or1200-rfemmu.S │ │ └── or1200-timerdemo.c │ └── sim │ │ ├── Makefile │ │ ├── or1200-basic.S │ │ ├── or1200-cbasic.c │ │ ├── or1200-cy.S │ │ ├── or1200-dctest.c │ │ ├── or1200-div.c │ │ ├── or1200-except.S │ │ ├── or1200-ext.S │ │ ├── or1200-ffl1.S │ │ ├── or1200-float.c │ │ ├── or1200-fp.S │ │ ├── or1200-intsyscall.S │ │ ├── or1200-linkregtest.S │ │ ├── or1200-mac.S │ │ ├── or1200-maci.S │ │ ├── or1200-mmu.c │ │ ├── or1200-mul.c │ │ ├── or1200-ov.S │ │ ├── or1200-rfe.S │ │ ├── or1200-rfemmu.S │ │ ├── or1200-sf.S │ │ ├── or1200-simple.c │ │ ├── or1200-tick.S │ │ └── or1200-ticksyscall.S ├── sdram │ ├── board │ │ ├── Makefile │ │ └── sdram-rows.c │ └── sim │ │ ├── Makefile │ │ ├── sdram-bankrows.c │ │ ├── sdram-banks.c │ │ ├── sdram-cols.c │ │ ├── sdram-rows.c │ │ └── sdram.h ├── spi │ ├── board │ │ ├── Makefile │ │ └── simplespi-readflash.c │ └── sim │ │ ├── Makefile │ │ ├── spi-interrupt.c │ │ └── spi-simple.c └── uart │ ├── board │ ├── Makefile │ └── uart-echo.c │ └── sim │ ├── Makefile │ ├── uart-interrupt.c │ ├── uart-interruptloopback.c │ └── uart-simple.c └── utils ├── Makefile ├── bin2binsizeword ├── bin2binsizeword.c ├── bin2c ├── bin2c.c ├── bin2flimg ├── bin2flimg.c ├── bin2hex ├── bin2hex.c ├── bin2srec ├── bin2srec.c ├── bin2vlogarray ├── bin2vlogarray.c ├── bin2vmem ├── bin2vmem.c ├── binlog2readable ├── binlog2readable.cpp ├── loader.c └── or32-idecode ├── Makefile ├── ansidecl.h ├── bfd.h ├── dis-asm.h ├── example_input ├── or32-dis.c ├── or32-opc.c ├── or32.h └── symcat.h /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/README.md -------------------------------------------------------------------------------- /gettingstarted.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/gettingstarted.pdf -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/DebugUnitSC.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/DebugUnitSC.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/GdbServerSC.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/GdbServerSC.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/JtagDriverSC.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/JtagDriverSC.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/JtagSC.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/JtagSC.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/JtagSC_includes.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/JtagSC_includes.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/MemCache.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/MemCache.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/MemoryLoad.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/MemoryLoad.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/MpHash.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/MpHash.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/Or1200MonitorSC.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/Or1200MonitorSC.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/OrpsocAccess.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/OrpsocAccess.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/OrpsocMain.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/OrpsocMain.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/ResetSC.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/ResetSC.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/RspConnection.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/RspConnection.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/RspPacket.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/RspPacket.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/SprCache.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/SprCache.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/TapAction.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/TapAction.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/TapActionDRScan.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/TapActionDRScan.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/TapActionIRScan.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/TapActionIRScan.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/TapActionReset.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/TapActionReset.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/TapStateMachine.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/TapStateMachine.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/TraceSC.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/TraceSC.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/UartSC.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/UartSC.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/Utils.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/Utils.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/coff.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/coff.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/include/elf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/include/elf.h -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/DebugUnitSC.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/DebugUnitSC.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/GdbServerSC.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/GdbServerSC.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/JtagDriverSC.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/JtagDriverSC.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/JtagSC.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/JtagSC.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/MemCache.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/MemCache.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/MemoryLoad.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/MemoryLoad.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/Modules.make: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/Modules.make -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/MpHash.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/MpHash.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/OrpsocAccess.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/OrpsocAccess.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/OrpsocMain.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/OrpsocMain.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/ResetSC.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/ResetSC.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/RspConnection.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/RspConnection.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/RspPacket.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/RspPacket.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/SprCache.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/SprCache.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/TapAction.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/TapAction.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/TapActionDRScan.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/TapActionDRScan.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/TapActionIRScan.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/TapActionIRScan.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/TapActionReset.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/TapActionReset.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/TapStateMachine.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/TapStateMachine.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/TraceSC.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/TraceSC.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/UartSC.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/UartSC.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/sysc/src/Utils.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/sysc/src/Utils.cpp -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/AT26DFxxx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/AT26DFxxx.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/eth_phy.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/eth_phy.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/cfi_flash_BankLib.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/cfi_flash_BankLib.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/cfi_flash_CUIcommandData.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/cfi_flash_CUIcommandData.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/cfi_flash_TimingData.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/cfi_flash_TimingData.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/cfi_flash_UserData.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/cfi_flash_UserData.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/cfi_flash_data.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/cfi_flash_data.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/cfi_flash_def.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/cfi_flash_def.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/eth_phy_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/eth_phy_defines.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/or1200_monitor_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/or1200_monitor_defines.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/include/timescale.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/include/timescale.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/mt48lc16m16a2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/mt48lc16m16a2.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/or1200_monitor.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/or1200_monitor.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/orpsoc_testbench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/orpsoc_testbench.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/smii_phy.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/smii_phy.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/uart_decoder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/uart_decoder.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/uart_stim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/uart_stim.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/HCTxPortArbiter_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/HCTxPortArbiter_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/RxFifo_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/RxFifo_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/RxfifoBI_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/RxfifoBI_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/SCTxPortArbiter_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/SCTxPortArbiter_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/SIEReceiver_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/SIEReceiver_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/SIETransmitter_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/SIETransmitter_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/SOFController_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/SOFController_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/SOFTransmit_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/SOFTransmit_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/TxFifo_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/TxFifo_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/TxfifoBI_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/TxfifoBI_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/USBHostControlBI_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/USBHostControlBI_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/USBSlaveControlBI_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/USBSlaveControlBI_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/USBTxWireArbiter_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/USBTxWireArbiter_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/directControl_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/directControl_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/dpMem_dc_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/dpMem_dc_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/endpMux_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/endpMux_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/fifoMux_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/fifoMux_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/fifoRTL_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/fifoRTL_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/getPacket_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/getPacket_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/hostSlaveMuxBI_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/hostSlaveMuxBI_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/hostSlaveMux_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/hostSlaveMux_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/hostcontroller_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/hostcontroller_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/lineControlUpdate_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/lineControlUpdate_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/processRxBit_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/processRxBit_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/processRxByte_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/processRxByte_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/processTxByte_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/processTxByte_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/readUSBWireData_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/readUSBWireData_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/rxStatusMonitor_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/rxStatusMonitor_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/sendPacketArbiter_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/sendPacketArbiter_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/sendPacket_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/sendPacket_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/slaveGetPacket_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/slaveGetPacket_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/slaveSendPacket_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/slaveSendPacket_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/slavecontroller_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/slavecontroller_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/speedCtrlMux_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/speedCtrlMux_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/updateCRC16_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/updateCRC16_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/updateCRC5_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/updateCRC5_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbConstants_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbConstants_h.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbHostControl_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbHostControl_h.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbHostControl_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbHostControl_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbHostSlave_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbHostSlave_h.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbSlaveControl_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbSlaveControl_h.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbSlaveControl_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbSlaveControl_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usb_hostslave_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usb_hostslave_tb.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usb_slave_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usb_slave_tb.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbhost_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbhost_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbhostslave_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbhostslave_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/usbslave_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/usbslave_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/wb_master_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/wb_master_model.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/wishBoneBI_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/wishBoneBI_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/wishBoneBus_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/wishBoneBus_h.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/usbhostslave/writeUSBWireData_simlib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/usbhostslave/writeUSBWireData_simlib.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/c/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/c/Makefile -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/c/gdb.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/c/gdb.c -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/c/gdb.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/c/gdb.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/c/jp_vpi.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/c/jp_vpi.c -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/c/rsp-vpi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/c/rsp-vpi.h -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/wiredelay.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/wiredelay.v -------------------------------------------------------------------------------- /orpsocv2/bench/verilog/x28fxxxp30.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/bench/verilog/x28fxxxp30.v -------------------------------------------------------------------------------- /orpsocv2/boards/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/README -------------------------------------------------------------------------------- /orpsocv2/boards/actel/backend/rtl/verilog/proasic3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/backend/rtl/verilog/proasic3.v -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/backend/par/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/README -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/backend/par/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/README -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/gbuf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/gbuf.v -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/spi_slave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/spi_slave.v -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/README -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio/README -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio/gpio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio/gpio.v -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/backend/rtl/verilog/pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/backend/rtl/verilog/pll.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/bench/verilog/include/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/bench/verilog/spi_slave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/bench/verilog/spi_slave.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/arbiter/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/arbiter/README -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/clkgen/clkgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/clkgen/clkgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/flashrom/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/flashrom/README -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/gpio/README -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/gpio/gpio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/gpio/gpio.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/vga_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/vga_fifo.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/vga_pgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/vga_pgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/vga_tgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/vga_tgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/vga_vtim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/rtl/verilog/vga_lcd/vga_vtim.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/sim/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/sim/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/sw/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/sw/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/sw/board/include/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/sw/board/include/board.h -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/sw/bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/sw/bootrom/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/syn/quartus/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/syn/quartus/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/syn/quartus/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/syn/quartus/sdc/JTAG_DEBUG.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/syn/quartus/sdc/JTAG_DEBUG.sdc -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de0_nano/syn/quartus/sdc/common.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de0_nano/syn/quartus/sdc/common.sdc -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/README -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/backend/rtl/verilog/pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/backend/rtl/verilog/pll.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/bench/verilog/include/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/bench/verilog/spi_slave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/bench/verilog/spi_slave.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/rtl/verilog/arbiter/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/rtl/verilog/arbiter/README -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/rtl/verilog/clkgen/clkgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/rtl/verilog/clkgen/clkgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/rtl/verilog/flashrom/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/rtl/verilog/flashrom/README -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/rtl/verilog/flashrom/flashrom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/rtl/verilog/flashrom/flashrom.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/rtl/verilog/gpio/README -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/rtl/verilog/gpio/gpio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/rtl/verilog/gpio/gpio.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/sim/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/sim/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/sw/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/sw/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/sw/board/include/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/sw/board/include/board.h -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/sw/bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/sw/bootrom/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/sw/bootrom/bootrom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/sw/bootrom/bootrom.v -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/syn/quartus/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/syn/quartus/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/syn/quartus/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/syn/quartus/sdc/JTAG_DEBUG.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/syn/quartus/sdc/JTAG_DEBUG.sdc -------------------------------------------------------------------------------- /orpsocv2/boards/altera/de2_115/syn/quartus/sdc/common.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/altera/de2_115/syn/quartus/sdc/common.sdc -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/backend/bin/vga_fifo_dc_gen.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/backend/bin/vga_fifo_dc_gen.ngc -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/backend/par/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/backend/par/run/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/backend/par/run/_xmsgs/map.xmsgs -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/backend/par/run/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/backend/par/run/_xmsgs/par.xmsgs -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/bench/verilog/ddr2_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/bench/verilog/ddr2_model.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_stim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_stim.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/bench/verilog/include/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/bench/verilog/or1200_monitor.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/bench/verilog/or1200_monitor.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_cra.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_cra.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_dma_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_dma_if.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_dma_req.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_dma_req.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_fifo_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_fifo_ctrl.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_in_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_in_fifo.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_int.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_int.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_out_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_out_fifo.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_prc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_prc.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_rf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_rf.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_rst.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_rst.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_sin.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_sin.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_soc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_soc.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_sout.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_sout.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_top.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_wb_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ac97/ac97_wb_if.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen/clkgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen/clkgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_ch_arb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_ch_arb.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_ch_rf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_ch_rf.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_ch_sel.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_ch_sel.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_de.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_de.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_inc30r.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_inc30r.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_rf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_rf.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_top.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_wb_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_wb_if.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_wb_mast.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_wb_mast.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_wb_slv.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dma/wb_dma_wb_slv.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/DRAM16XN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/DRAM16XN.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/dcmspi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/dcmspi.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/dvi_encoder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/dvi_encoder.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/dvi_gen_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/dvi_gen_top.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/encode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/encode.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/synchro.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/dvi_gen/synchro.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/fdt/fdt.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/fdt/fdt.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/basic_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/basic_fifo.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/div_uu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/div_uu.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_blender.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_blender.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_clip.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_clip.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_color.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_color.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_cuvz.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_cuvz.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_interp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_interp.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_line.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_line.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_params.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_params.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_rasterizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_rasterizer.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_renderer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_renderer.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_top.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_transform.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_transform.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_triangle.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_triangle.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_wbm_read.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_wbm_read.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_wbm_write.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_wbm_write.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_wbs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/gfx_wbs.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gfx/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_defines.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/include/tap_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/tap_defines.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/include/vga_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/vga_defines.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/.svn/entries: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/.svn/entries -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/ledmod.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/ledmod.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/ledmod.v~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/ledmod.v~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/ledtest.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/ledtest.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/ledtest.v~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ledtest/ledtest.v~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr/lfsr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr/lfsr.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ps2/ps2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ps2/ps2.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/ps2/ps2_wishbone.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/ps2/ps2_wishbone.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/verilog/gpio/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/verilog/gpio/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/verilog/gpio/gpio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/verilog/gpio/gpio.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/verilog/gpio/gpio.v~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/verilog/gpio/gpio.v~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_clkgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_clkgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_colproc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_colproc.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_fifo.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_pgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_pgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_tgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_tgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_vtim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/vga_lcd/vga_vtim.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog_old/ac97/ac97_rf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog_old/ac97/ac97_rf.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog_old/fdt/fdt.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog_old/fdt/fdt.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog_old/gpio/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog_old/gpio/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog_old/gpio/gpio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog_old/gpio/gpio.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog_old/gpio/gpio.v~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog_old/gpio/gpio.v~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog_old/lfsr/lfsr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog_old/lfsr/lfsr.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog_old/ps2/ps2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/rtl/verilog_old/ps2/ps2.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/rtl/verilog_old/vga_lcd/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sim/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sim/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sim/bin/atlys-or1ksim.cfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sim/bin/atlys-or1ksim.cfg -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/board/include/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/board/include/board.h -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/board/include/board.h~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/board/include/board.h~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/bootrom/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/bootrom/bootrom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/bootrom/bootrom.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/bootrom/bootrom.v.led: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/bootrom/bootrom.v.led -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/bootrom/led: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/bootrom/led -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/bootrom/led.S~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/bootrom/led.S~ -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/device_tree/atlys.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/device_tree/atlys.dtb -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/sw/device_tree/atlys.dts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/sw/device_tree/atlys.dts -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/syn/xst/coregen/coregen.cgp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/coregen.cgp -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/syn/xst/run/.lso: -------------------------------------------------------------------------------- 1 | blk_mem_gen_v4_3 2 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/atlys/syn/xst/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/backend/par/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/bench/verilog/cy7c1354.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/bench/verilog/cy7c1354.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/bench/verilog/include/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/rtl/verilog/clkgen/clkgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/rtl/verilog/clkgen/clkgen.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/rtl/verilog/gpio/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/rtl/verilog/gpio/gpio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/rtl/verilog/gpio/gpio.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/rtl/verilog/lfsr/lfsr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/rtl/verilog/lfsr/lfsr.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/sim/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/sim/bin/ml501-or1ksim.cfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/sim/bin/ml501-or1ksim.cfg -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/sw/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/sw/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/sw/board/include/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/sw/bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/sw/bootrom/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/ml501/syn/xst/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/backend/par/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/README -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/gpio.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/gpio.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/sim/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/sim/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/sw/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/sw/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/sw/board/include/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/sw/board/include/board.h -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/bootrom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/bootrom.v -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/boards/xilinx/s3adsp1800/syn/xst/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/doc/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/Makefile -------------------------------------------------------------------------------- /orpsocv2/doc/Makefile.am: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/Makefile.am -------------------------------------------------------------------------------- /orpsocv2/doc/Makefile.in: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/Makefile.in -------------------------------------------------------------------------------- /orpsocv2/doc/aclocal.m4: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/aclocal.m4 -------------------------------------------------------------------------------- /orpsocv2/doc/autom4te.cache/output.0: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/autom4te.cache/output.0 -------------------------------------------------------------------------------- /orpsocv2/doc/autom4te.cache/output.1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/autom4te.cache/output.1 -------------------------------------------------------------------------------- /orpsocv2/doc/autom4te.cache/output.2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/autom4te.cache/output.2 -------------------------------------------------------------------------------- /orpsocv2/doc/autom4te.cache/requests: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/autom4te.cache/requests -------------------------------------------------------------------------------- /orpsocv2/doc/autom4te.cache/traces.0: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/autom4te.cache/traces.0 -------------------------------------------------------------------------------- /orpsocv2/doc/autom4te.cache/traces.1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/autom4te.cache/traces.1 -------------------------------------------------------------------------------- /orpsocv2/doc/autom4te.cache/traces.2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/autom4te.cache/traces.2 -------------------------------------------------------------------------------- /orpsocv2/doc/config.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/config.log -------------------------------------------------------------------------------- /orpsocv2/doc/config.status: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/config.status -------------------------------------------------------------------------------- /orpsocv2/doc/config.texi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/config.texi -------------------------------------------------------------------------------- /orpsocv2/doc/configure: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/configure -------------------------------------------------------------------------------- /orpsocv2/doc/configure.in: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/configure.in -------------------------------------------------------------------------------- /orpsocv2/doc/fdl-1.2.texi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/fdl-1.2.texi -------------------------------------------------------------------------------- /orpsocv2/doc/install-sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/install-sh -------------------------------------------------------------------------------- /orpsocv2/doc/missing: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/missing -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.aux: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/orpsoc.aux -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.cp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/orpsoc.cp -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.cps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/orpsoc.cps -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.fn: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/orpsoc.info -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.ky: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/orpsoc.log -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/orpsoc.pdf -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.pg: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.texi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/orpsoc.texi -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.toc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/orpsoc.toc -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.tp: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /orpsocv2/doc/orpsoc.vr: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /orpsocv2/doc/texinfo.tex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/doc/texinfo.tex -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/arbiter/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/arbiter/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/arbiter/arbiter_bytebus.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/arbiter/arbiter_bytebus.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl_engine.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl_engine.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/clkgen/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/clkgen/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/clkgen/clkgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/clkgen/clkgen.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/dbg_if/dbg_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/dbg_if/dbg_if.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/dbg_if/dbg_register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/dbg_if/dbg_register.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/dbg_if/dbg_wb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_clockgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_crc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_crc.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_fifo.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_macstatus.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_miim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_miim.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_random.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_random.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_register.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_registers.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_registers.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_rxaddrcheck.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_rxaddrcheck.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_txcounters.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_txethmac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_txstatem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/eth_wishbone.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/ethmac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/ethmac.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ethmac/xilinx_dist_ram_16x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ethmac/xilinx_dist_ram_16x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/basic_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/basic_fifo.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/div_uu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/div_uu.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_blender.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_blender.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_clip.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_clip.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_color.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_color.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_cuvz.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_cuvz.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_fragment_processor.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_fragment_processor.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_interp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_interp.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_line.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_line.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_params.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_params.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_rasterizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_rasterizer.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_renderer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_renderer.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_top.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_transform.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_transform.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_triangle.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_triangle.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_wbm_read.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_wbm_read.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_wbm_read_arbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_wbm_read_arbiter.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_wbm_write.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_wbm_write.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/gfx_wbs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/gfx/gfx_wbs.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/gfx/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/i2c_master_slave/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/i2c_master_slave/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_bit_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_bit_ctrl.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_slave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_slave.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/dbg_cpu_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/dbg_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/dbg_defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/dbg_wb_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/dbg_wb_defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/ethmac_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/ethmac_defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/i2c_master_slave_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/i2c_master_slave_defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/or1200_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/or1200_defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/orpsoc-defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/orpsoc-defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/orpsoc-params.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/orpsoc-params.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/tap_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/tap_defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/uart_defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/uart_defines.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/usbhostslave_constants_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/usbhostslave_constants_h.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/usbhostslave_hostcontrol_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/usbhostslave_hostcontrol_h.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/usbhostslave_hostslave_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/usbhostslave_hostslave_h.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/usbhostslave_slavecontrol_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/usbhostslave_slavecontrol_h.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/include/usbhostslave_wishbonebus_h.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/include/usbhostslave_wishbonebus_h.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/intgen/intgen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/intgen/intgen.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/jtag_tap/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/jtag_tap/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_alu.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_amultp2_32x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_amultp2_32x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_cfgr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_cfgr.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_cpu.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dc_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dc_top.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dmmu_tlb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dmmu_tlb.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dpram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dpram.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dpram_256x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dpram_256x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_dpram_32x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_dpram_32x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_du.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_du.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_except.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_except.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_addsub.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_addsub.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_arith.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_arith.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_div.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_fcmp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_fcmp.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_mul.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_mul.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_addsub.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_addsub.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_div.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_mul.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_mul.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_addsub.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_addsub.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_div.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_mul.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_mul.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_freeze.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_freeze.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_genpc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_genpc.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_ic_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_if.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_immu_tlb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_immu_tlb.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_immu_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_iwb_biu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_iwb_biu.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_lsu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_lsu.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_mem2reg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_mem2reg.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_pic.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_pic.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_pm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_pm.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_qmem_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_qmem_top.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_rf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_rf.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_sb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_sb.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_sb_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_sb_fifo.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_1024x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_1024x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_1024x32_bw.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_1024x32_bw.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_1024x8.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_1024x8.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_128x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_128x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_2048x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_2048x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_2048x32_bw.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_2048x32_bw.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_2048x8.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_2048x8.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_256x21.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_256x21.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_32_bw.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_32_bw.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_32x24.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_32x24.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_512x20.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_512x20.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_64x14.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_64x14.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_64x22.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_64x22.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_spram_64x24.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_spram_64x24.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_sprs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_sprs.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_top.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_tpram_32x32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_tpram_32x32.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_tt.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_tt.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_wbmux.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/or1200/or1200_xcv_ram32x8d.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/or1200/or1200_xcv_ram32x8d.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ram_wb/ram_wb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ram_wb/ram_wb.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/rom/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/rom/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/rom/rom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/rom/rom.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/simple_spi/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/simple_spi/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/simple_spi/fifo4.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/simple_spi/fifo4.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/simple_spi/simple_spi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/simple_spi/simple_spi.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/smii/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/smii/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/smii/smii.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/smii/smii.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/smii/smii_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/smii/smii_if.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/smii/smii_sync.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/smii/smii_sync.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/raminfr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/raminfr.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart16550.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart16550.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart_debug_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart_debug_if.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart_receiver.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart_receiver.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart_regs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart_regs.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart_rfifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart_tfifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart_transmitter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/uart16550/uart_wb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/uart16550/uart_wb.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/HCTxPortArbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/HCTxPortArbiter.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/README -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/RxFifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/RxFifo.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/RxfifoBI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/RxfifoBI.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/SCTxPortArbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/SCTxPortArbiter.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/SIEReceiver.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/SIEReceiver.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/SIETransmitter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/SIETransmitter.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/SOFController.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/SOFController.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/SOFTransmit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/SOFTransmit.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/TxFifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/TxFifo.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/TxfifoBI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/TxfifoBI.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/USBHostControlBI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/USBHostControlBI.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/USBSlaveControlBI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/USBSlaveControlBI.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/USBTxWireArbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/USBTxWireArbiter.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/directControl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/directControl.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/dpMem_dc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/dpMem_dc.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/endpMux.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/endpMux.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/fifoMux.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/fifoMux.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/fifoRTL.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/fifoRTL.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/getPacket.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/getPacket.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/hostSlaveMux.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/hostSlaveMux.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/hostSlaveMuxBI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/hostSlaveMuxBI.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/hostcontroller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/hostcontroller.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/lineControlUpdate.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/lineControlUpdate.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/processRxBit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/processRxBit.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/processRxByte.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/processRxByte.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/processTxByte.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/processTxByte.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/readUSBWireData.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/readUSBWireData.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/rxStatusMonitor.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/rxStatusMonitor.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/sendPacket.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/sendPacket.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/sendPacketArbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/sendPacketArbiter.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/sendPacketCheckPreamble.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/sendPacketCheckPreamble.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/slaveDirectControl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/slaveDirectControl.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/slaveGetPacket.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/slaveGetPacket.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/slaveRxStatusMonitor.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/slaveRxStatusMonitor.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/slaveSendPacket.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/slaveSendPacket.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/slavecontroller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/slavecontroller.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/speedCtrlMux.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/speedCtrlMux.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/updateCRC16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/updateCRC16.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/updateCRC5.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/updateCRC5.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/usbHostControl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/usbHostControl.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/usbSlaveControl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/usbSlaveControl.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/usbhost.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/usbhost.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/usbhostslave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/usbhostslave.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/usbslave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/usbslave.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/wishBoneBI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/wishBoneBI.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/usbhostslave/writeUSBWireData.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/usbhostslave/writeUSBWireData.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v -------------------------------------------------------------------------------- /orpsocv2/rtl/verilog/wb_switch_b3/wb_switch_b3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/rtl/verilog/wb_switch_b3/wb_switch_b3.v -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-benchsrc.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-benchsrc.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-definesparse.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-definesparse.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-icarus.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-icarus.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-modelsim.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-modelsim.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-paths.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-paths.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-rtlmodules.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-rtlmodules.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-simclean.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-simclean.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-sw.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-sw.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-board-tops.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-board-tops.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-misc.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-misc.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-rtltestrules.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-rtltestrules.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-sim-definesgen.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-sim-definesgen.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-simulators.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-simulators.inc -------------------------------------------------------------------------------- /orpsocv2/scripts/make/Makefile-swrules.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/scripts/make/Makefile-swrules.inc -------------------------------------------------------------------------------- /orpsocv2/sim/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sim/bin/Makefile -------------------------------------------------------------------------------- /orpsocv2/sim/bin/definesgen.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sim/bin/definesgen.inc -------------------------------------------------------------------------------- /orpsocv2/sim/bin/refdesign-or1ksim.cfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sim/bin/refdesign-or1ksim.cfg -------------------------------------------------------------------------------- /orpsocv2/sim/run/Makefile: -------------------------------------------------------------------------------- 1 | include ../bin/Makefile 2 | -------------------------------------------------------------------------------- /orpsocv2/sw/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/Makefile.inc -------------------------------------------------------------------------------- /orpsocv2/sw/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/README -------------------------------------------------------------------------------- /orpsocv2/sw/apps/cfi_ctrl_programmer/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/cfi_ctrl_programmer/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.ld -------------------------------------------------------------------------------- /orpsocv2/sw/apps/dhry/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/dhry/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/apps/dhry/dhry.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/dhry/dhry.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/dhry/dhry.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/dhry/dhry.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/spiflash/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/spiflash/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/apps/spiflash/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/spiflash/README -------------------------------------------------------------------------------- /orpsocv2/sw/apps/spiflash/spiflash-program.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/spiflash/spiflash-program.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/spiflash/spiflash-program.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/spiflash/spiflash-program.ld -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/README -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/fail.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/fail.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/fail.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/fail.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/milieu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/milieu.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/or1k-gcc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/or1k-gcc.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/random.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/random.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/random.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/random.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/slowfloat.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/slowfloat.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/slowfloat.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/slowfloat.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/softfloat.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/softfloat.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/softfloat.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/softfloat.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/systflags.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/systflags.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/systflags.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/systflags.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/systfloat.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/systfloat.S -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/systfloat.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/systfloat.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/systmodes.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/systmodes.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/systmodes.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/systmodes.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/testCases.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/testCases.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/testCases.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/testCases.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/testFunction.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/testFunction.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/testFunction.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/testFunction.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/testLoops.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/testLoops.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/testLoops.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/testLoops.h -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/testfloat.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/testfloat.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/testsoftfloat.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/testsoftfloat.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/writeHex.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/writeHex.c -------------------------------------------------------------------------------- /orpsocv2/sw/apps/testfloat/writeHex.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/apps/testfloat/writeHex.h -------------------------------------------------------------------------------- /orpsocv2/sw/board/include/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/board/include/board.h -------------------------------------------------------------------------------- /orpsocv2/sw/bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/bootrom/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/bootrom/bootrom.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/bootrom/bootrom.S -------------------------------------------------------------------------------- /orpsocv2/sw/bootrom/bootrom.S~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/bootrom/bootrom.S~ -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/cfi-ctrl/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/cfi-ctrl/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/cfi-ctrl/cfi_ctrl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/cfi-ctrl/cfi_ctrl.c -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/cfi-ctrl/include/cfi_ctrl.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/cfi-ctrl/include/cfi_ctrl.h -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/ethmac/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/ethmac/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/ethmac/ethmac.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/ethmac/ethmac.c -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/ethmac/include/eth-phy-mii.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/ethmac/include/eth-phy-mii.h -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/ethmac/include/ethmac.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/ethmac/include/ethmac.h -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/i2c_master_slave/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/i2c_master_slave/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/cache.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/cache.S -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/crt0.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/crt0.S -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/exceptions.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/exceptions.c -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/include/int.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/include/int.h -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/include/or1200-utils.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/include/or1200-utils.h -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/include/spr-defs.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/include/spr-defs.h -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/int.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/int.c -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/link.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/link.ld -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/mmu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/mmu.S -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/or1200/or1200-utils.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/or1200/or1200-utils.c -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/simple-spi/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/simple-spi/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/simple-spi/include/simple-spi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/simple-spi/include/simple-spi.h -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/simple-spi/simple-spi.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/simple-spi/simple-spi.c -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/uart/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/uart/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/uart/include/uart.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/uart/include/uart.h -------------------------------------------------------------------------------- /orpsocv2/sw/drivers/uart/uart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/drivers/uart/uart.c -------------------------------------------------------------------------------- /orpsocv2/sw/lib/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/lib/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/lib/include/cpu-utils.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/lib/include/cpu-utils.h -------------------------------------------------------------------------------- /orpsocv2/sw/lib/include/lib-utils.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/lib/include/lib-utils.h -------------------------------------------------------------------------------- /orpsocv2/sw/lib/include/printf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/lib/include/printf.h -------------------------------------------------------------------------------- /orpsocv2/sw/lib/lib-utils.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/lib/lib-utils.c -------------------------------------------------------------------------------- /orpsocv2/sw/lib/printf.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/lib/printf.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/cfi_ctrl/board/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/cfi_ctrl/board/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-readid.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-readid.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-simple.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-simple.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/cfi_ctrl/sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/cfi_ctrl/sim/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-readid.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-readid.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-simple.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-simple.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/ethmac/board/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/ethmac/board/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/ethmac/board/ethmac-ping.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/ethmac/sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/ethmac/sim/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxoverflow.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxoverflow.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/board/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/board/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/board/or1200-configdetect.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/board/or1200-configdetect.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/board/or1200-div.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/board/or1200-div.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/board/or1200-mmu.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/board/or1200-mmu.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/board/or1200-mul.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/board/or1200-mul.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/board/or1200-rfemmu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/board/or1200-rfemmu.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/board/or1200-timerdemo.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/board/or1200-timerdemo.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-basic.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-basic.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-cy.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-cy.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-dctest.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-div.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-div.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-except.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-except.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-ext.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-ext.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-float.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-float.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-fp.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-fp.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-intsyscall.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-intsyscall.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-mac.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-mac.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-maci.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-maci.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-mmu.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-mul.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-mul.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-ov.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-ov.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-rfe.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-rfe.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-rfemmu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-rfemmu.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-sf.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-sf.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-simple.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-simple.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-tick.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-tick.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S -------------------------------------------------------------------------------- /orpsocv2/sw/tests/sdram/board/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/sdram/board/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/sdram/board/sdram-rows.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/sdram/board/sdram-rows.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/sdram/sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/sdram/sim/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/sdram/sim/sdram-bankrows.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/sdram/sim/sdram-bankrows.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/sdram/sim/sdram-banks.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/sdram/sim/sdram-banks.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/sdram/sim/sdram-cols.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/sdram/sim/sdram-cols.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/sdram/sim/sdram-rows.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/sdram/sim/sdram-rows.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/sdram/sim/sdram.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/sdram/sim/sdram.h -------------------------------------------------------------------------------- /orpsocv2/sw/tests/spi/board/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/spi/board/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/spi/board/simplespi-readflash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/spi/board/simplespi-readflash.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/spi/sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/spi/sim/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/spi/sim/spi-interrupt.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/spi/sim/spi-interrupt.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/spi/sim/spi-simple.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/spi/sim/spi-simple.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/uart/board/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/uart/board/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/uart/board/uart-echo.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/uart/board/uart-echo.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/uart/sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/uart/sim/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/tests/uart/sim/uart-interrupt.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/uart/sim/uart-interrupt.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/uart/sim/uart-interruptloopback.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/uart/sim/uart-interruptloopback.c -------------------------------------------------------------------------------- /orpsocv2/sw/tests/uart/sim/uart-simple.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/tests/uart/sim/uart-simple.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2binsizeword: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2binsizeword -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2binsizeword.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2binsizeword.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2c.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2c.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2flimg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2flimg -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2flimg.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2flimg.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2hex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2hex -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2hex.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2hex.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2srec: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2srec -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2srec.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2srec.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2vlogarray: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2vlogarray -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2vlogarray.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2vlogarray.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2vmem: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2vmem -------------------------------------------------------------------------------- /orpsocv2/sw/utils/bin2vmem.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/bin2vmem.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/binlog2readable: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/binlog2readable -------------------------------------------------------------------------------- /orpsocv2/sw/utils/binlog2readable.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/binlog2readable.cpp -------------------------------------------------------------------------------- /orpsocv2/sw/utils/loader.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/loader.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/Makefile -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/ansidecl.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/ansidecl.h -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/bfd.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/bfd.h -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/dis-asm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/dis-asm.h -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/example_input: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/example_input -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/or32-dis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/or32-dis.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/or32-opc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/or32-opc.c -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/or32.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/or32.h -------------------------------------------------------------------------------- /orpsocv2/sw/utils/or32-idecode/symcat.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/maidenone/ORGFXSoC/HEAD/orpsocv2/sw/utils/or32-idecode/symcat.h --------------------------------------------------------------------------------