├── src ├── Module.supported ├── ixgbe_82598.h ├── ixgbe_osdep2.h ├── ixgbe_x540.h ├── ixgbe_82599.h ├── ixgbe_fcoe.h ├── ixgbe_sriov.h ├── ixgbe_dcb_82598.h ├── ixgbe_dcb_82599.h ├── ixgbe_x550.h ├── ixgbe_dcb.h ├── ixgbe_mbx.h ├── ixgbe_osdep.h ├── ixgbe_common.h ├── ixgbe_sysfs.c ├── ixgbe_phy.h ├── ixgbe_debugfs.c ├── ixgbe_api.h ├── ixgbe_dcb_82598.c ├── Makefile ├── ixgbe_dcb_82599.c └── ixgbe_mbx.c ├── README ├── SUMS ├── pci.updates ├── scripts └── set_irq_affinity ├── ixgbe.7 ├── ixgbe.spec └── COPYING /src/Module.supported: -------------------------------------------------------------------------------- 1 | ixgbe.ko external 2 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/majek/ixgbe/HEAD/README -------------------------------------------------------------------------------- /src/ixgbe_82598.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_82598_H_ 26 | #define _IXGBE_82598_H_ 27 | 28 | u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); 29 | s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw); 30 | s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw); 31 | s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 32 | s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on); 33 | s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); 34 | s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); 35 | s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 36 | u8 *eeprom_data); 37 | u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 38 | s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); 39 | void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw); 40 | void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw); 41 | s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval); 42 | #endif /* _IXGBE_82598_H_ */ 43 | -------------------------------------------------------------------------------- /src/ixgbe_osdep2.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_OSDEP2_H_ 26 | #define _IXGBE_OSDEP2_H_ 27 | 28 | static inline bool ixgbe_removed(void __iomem *addr) 29 | { 30 | return unlikely(!addr); 31 | } 32 | #define IXGBE_REMOVED(a) ixgbe_removed(a) 33 | 34 | static inline void IXGBE_WRITE_REG(struct ixgbe_hw *hw, u32 reg, u32 value) 35 | { 36 | u8 __iomem *reg_addr; 37 | 38 | reg_addr = ACCESS_ONCE(hw->hw_addr); 39 | if (IXGBE_REMOVED(reg_addr)) 40 | return; 41 | #ifdef DBG 42 | switch (reg) { 43 | case IXGBE_EIMS: 44 | case IXGBE_EIMC: 45 | case IXGBE_EIAM: 46 | case IXGBE_EIAC: 47 | case IXGBE_EICR: 48 | case IXGBE_EICS: 49 | printk("%s: Reg - 0x%05X, value - 0x%08X\n", __func__, 50 | reg, value); 51 | default: 52 | break; 53 | } 54 | #endif /* DBG */ 55 | writel(value, reg_addr + reg); 56 | } 57 | 58 | static inline void IXGBE_WRITE_REG64(struct ixgbe_hw *hw, u32 reg, u64 value) 59 | { 60 | u8 __iomem *reg_addr; 61 | 62 | reg_addr = ACCESS_ONCE(hw->hw_addr); 63 | if (IXGBE_REMOVED(reg_addr)) 64 | return; 65 | writeq(value, reg_addr + reg); 66 | } 67 | 68 | #endif /* _IXGBE_OSDEP2_H_ */ 69 | -------------------------------------------------------------------------------- /SUMS: -------------------------------------------------------------------------------- 1 | 09576 6 ixgbe-4.1.1/scripts/set_irq_affinity 2 | 42571 18 ixgbe-4.1.1/COPYING 3 | 50386 39 ixgbe-4.1.1/src/ixgbe_sriov.c 4 | 03933 51 ixgbe-4.1.1/src/kcompat.c 5 | 03057 8 ixgbe-4.1.1/src/ixgbe_phy.h 6 | 10326 14 ixgbe-4.1.1/src/Makefile 7 | 00384 45 ixgbe-4.1.1/src/ixgbe_api.c 8 | 10067 23 ixgbe-4.1.1/src/ixgbe_dcb_nl.c 9 | 03018 4 ixgbe-4.1.1/src/ixgbe_dcb_82598.h 10 | 31928 105 ixgbe-4.1.1/src/ixgbe_ethtool.c 11 | 00999 135 ixgbe-4.1.1/src/kcompat.h 12 | 56780 8 ixgbe-4.1.1/src/ixgbe_common.h 13 | 00516 5 ixgbe-4.1.1/src/ixgbe_x550.h 14 | 02089 2 ixgbe-4.1.1/src/ixgbe_osdep2.h 15 | 25929 7 ixgbe-4.1.1/src/ixgbe_osdep.h 16 | 58442 20 ixgbe-4.1.1/src/ixgbe_mbx.c 17 | 27260 3 ixgbe-4.1.1/src/ixgbe_82599.h 18 | 53143 6 ixgbe-4.1.1/src/ixgbe_dcb.h 19 | 23794 40 ixgbe-4.1.1/src/ixgbe_82598.c 20 | 50167 31 ixgbe-4.1.1/src/ixgbe_param.c 21 | 30951 21 ixgbe-4.1.1/src/ixgbe_dcb.c 22 | 55721 4 ixgbe-4.1.1/src/ixgbe_sriov.h 23 | 62080 76 ixgbe-4.1.1/src/ixgbe_82599.c 24 | 21099 10 ixgbe-4.1.1/src/ixgbe_dcb_82598.c 25 | 44589 294 ixgbe-4.1.1/src/ixgbe_main.c 26 | 10362 36 ixgbe-4.1.1/src/ixgbe.h 27 | 05084 153 ixgbe-4.1.1/src/ixgbe_type.h 28 | 19027 29 ixgbe-4.1.1/src/kcompat_ethtool.c 29 | 14576 27 ixgbe-4.1.1/src/ixgbe_procfs.c 30 | 43555 37 ixgbe-4.1.1/src/ixgbe_lib.c 31 | 44113 10 ixgbe-4.1.1/src/ixgbe_api.h 32 | 38247 5 ixgbe-4.1.1/src/ixgbe_dcb_82599.h 33 | 10210 8 ixgbe-4.1.1/src/ixgbe_sysfs.c 34 | 10046 2 ixgbe-4.1.1/src/ixgbe_82598.h 35 | 14415 7 ixgbe-4.1.1/src/ixgbe_mbx.h 36 | 53172 29 ixgbe-4.1.1/src/ixgbe_x540.c 37 | 23422 3 ixgbe-4.1.1/src/ixgbe_x540.h 38 | 19713 45 ixgbe-4.1.1/src/ixgbe_ptp.c 39 | 54750 3 ixgbe-4.1.1/src/ixgbe_fcoe.h 40 | 50343 29 ixgbe-4.1.1/src/ixgbe_fcoe.c 41 | 12190 1 ixgbe-4.1.1/src/Module.supported 42 | 16759 17 ixgbe-4.1.1/src/ixgbe_dcb_82599.c 43 | 38346 87 ixgbe-4.1.1/src/ixgbe_x550.c 44 | 54301 8 ixgbe-4.1.1/src/ixgbe_debugfs.c 45 | 04371 73 ixgbe-4.1.1/src/ixgbe_phy.c 46 | 33462 134 ixgbe-4.1.1/src/ixgbe_common.c 47 | 56763 8 ixgbe-4.1.1/ixgbe.7 48 | 49681 6 ixgbe-4.1.1/pci.updates 49 | 61223 10 ixgbe-4.1.1/ixgbe.spec 50 | 15674 45 ixgbe-4.1.1/README 51 | -------------------------------------------------------------------------------- /src/ixgbe_x540.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_X540_H_ 26 | #define _IXGBE_X540_H_ 27 | 28 | #include "ixgbe_type.h" 29 | 30 | s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 31 | ixgbe_link_speed *speed, bool *autoneg); 32 | enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw); 33 | s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed, 34 | bool link_up_wait_to_complete); 35 | s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw); 36 | s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw); 37 | u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw); 38 | 39 | s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw); 40 | s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data); 41 | s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words, 42 | u16 *data); 43 | s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data); 44 | s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words, 45 | u16 *data); 46 | s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw); 47 | s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val); 48 | s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw); 49 | s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 50 | 51 | s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask); 52 | void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask); 53 | 54 | s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index); 55 | s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index); 56 | #endif /* _IXGBE_X540_H_ */ 57 | 58 | -------------------------------------------------------------------------------- /src/ixgbe_82599.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_82599_H_ 26 | #define _IXGBE_82599_H_ 27 | 28 | s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 29 | ixgbe_link_speed *speed, bool *autoneg); 30 | enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 31 | void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 32 | void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 33 | void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 34 | void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, 35 | ixgbe_link_speed speed); 36 | s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 37 | ixgbe_link_speed speed, 38 | bool autoneg_wait_to_complete); 39 | s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 40 | bool autoneg_wait_to_complete); 41 | s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed, 42 | bool autoneg_wait_to_complete); 43 | s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 44 | void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 45 | s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 46 | s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); 47 | s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); 48 | s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw); 49 | s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 50 | s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 51 | u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 52 | s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval); 53 | s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val); 54 | s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked); 55 | #endif /* _IXGBE_82599_H_ */ 56 | -------------------------------------------------------------------------------- /src/ixgbe_fcoe.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_FCOE_H_ 26 | #define _IXGBE_FCOE_H_ 27 | 28 | #if IS_ENABLED(CONFIG_FCOE) 29 | 30 | #include 31 | #include 32 | 33 | /* shift bits within STAT fo FCSTAT */ 34 | #define IXGBE_RXDADV_FCSTAT_SHIFT 4 35 | 36 | /* ddp user buffer */ 37 | #define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */ 38 | #define IXGBE_FCPTR_ALIGN 16 39 | #define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t)) 40 | #define IXGBE_FCBUFF_4KB 0x0 41 | #define IXGBE_FCBUFF_8KB 0x1 42 | #define IXGBE_FCBUFF_16KB 0x2 43 | #define IXGBE_FCBUFF_64KB 0x3 44 | #define IXGBE_FCBUFF_MAX 65536 /* 64KB max */ 45 | #define IXGBE_FCBUFF_MIN 4096 /* 4KB min */ 46 | #define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */ 47 | #define IXGBE_FCOE_DDP_MAX_X550 2048 /* 11 bits xid */ 48 | 49 | /* Default user priority to use for FCoE */ 50 | #define IXGBE_FCOE_DEFUP 3 51 | 52 | /* fcerr */ 53 | #define IXGBE_FCERR_BADCRC 0x00100000 54 | #define IXGBE_FCERR_EOFSOF 0x00200000 55 | #define IXGBE_FCERR_NOFIRST 0x00300000 56 | #define IXGBE_FCERR_OOOSEQ 0x00400000 57 | #define IXGBE_FCERR_NODMA 0x00500000 58 | #define IXGBE_FCERR_PKTLOST 0x00600000 59 | 60 | /* FCoE DDP for target mode */ 61 | #define __IXGBE_FCOE_TARGET 1 62 | 63 | struct ixgbe_fcoe_ddp { 64 | int len; 65 | u32 err; 66 | unsigned int sgc; 67 | struct scatterlist *sgl; 68 | dma_addr_t udp; 69 | u64 *udl; 70 | struct dma_pool *pool; 71 | }; 72 | 73 | /* per cpu variables */ 74 | struct ixgbe_fcoe_ddp_pool { 75 | struct dma_pool *pool; 76 | u64 noddp; 77 | u64 noddp_ext_buff; 78 | }; 79 | 80 | struct ixgbe_fcoe { 81 | struct ixgbe_fcoe_ddp_pool __percpu *ddp_pool; 82 | atomic_t refcnt; 83 | spinlock_t lock; 84 | struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX_X550]; 85 | void *extra_ddp_buffer; 86 | dma_addr_t extra_ddp_buffer_dma; 87 | unsigned long mode; 88 | u8 up; 89 | u8 up_set; 90 | }; 91 | #endif /* CONFIG_FCOE */ 92 | 93 | #endif /* _IXGBE_FCOE_H */ 94 | -------------------------------------------------------------------------------- /src/ixgbe_sriov.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | 26 | #ifndef _IXGBE_SRIOV_H_ 27 | #define _IXGBE_SRIOV_H_ 28 | 29 | /* ixgbe driver limit the max number of VFs could be enabled to 30 | * 63 (IXGBE_MAX_VF_FUNCTIONS - 1) 31 | */ 32 | #define IXGBE_MAX_VFS_DRV_LIMIT (IXGBE_MAX_VF_FUNCTIONS - 1) 33 | 34 | void ixgbe_restore_vf_multicasts(struct ixgbe_adapter *adapter); 35 | int ixgbe_set_vf_vlan(struct ixgbe_adapter *adapter, int add, int vid, u32 vf); 36 | void ixgbe_set_vmolr(struct ixgbe_hw *hw, u32 vf, bool aupe); 37 | void ixgbe_msg_task(struct ixgbe_adapter *adapter); 38 | int ixgbe_set_vf_mac(struct ixgbe_adapter *adapter, 39 | int vf, unsigned char *mac_addr); 40 | void ixgbe_disable_tx_rx(struct ixgbe_adapter *adapter); 41 | void ixgbe_ping_all_vfs(struct ixgbe_adapter *adapter); 42 | #ifdef IFLA_VF_MAX 43 | int ixgbe_ndo_set_vf_mac(struct net_device *netdev, int queue, u8 *mac); 44 | int ixgbe_ndo_set_vf_vlan(struct net_device *netdev, int queue, u16 vlan, 45 | u8 qos); 46 | #ifdef HAVE_NDO_SET_VF_MIN_MAX_TX_RATE 47 | int ixgbe_ndo_set_vf_bw(struct net_device *netdev, int vf, int min_tx_rate, 48 | int max_tx_rate); 49 | #else 50 | int ixgbe_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 51 | #endif /* HAVE_NDO_SET_VF_MIN_MAX_TX_RATE */ 52 | #ifdef HAVE_VF_SPOOFCHK_CONFIGURE 53 | int ixgbe_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting); 54 | #endif 55 | int ixgbe_ndo_get_vf_config(struct net_device *netdev, 56 | int vf, struct ifla_vf_info *ivi); 57 | #endif /* IFLA_VF_MAX */ 58 | int ixgbe_disable_sriov(struct ixgbe_adapter *adapter); 59 | #ifdef CONFIG_PCI_IOV 60 | int ixgbe_vf_configuration(struct pci_dev *pdev, unsigned int event_mask); 61 | void ixgbe_enable_sriov(struct ixgbe_adapter *adapter); 62 | #endif 63 | int ixgbe_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 64 | #ifdef IFLA_VF_MAX 65 | void ixgbe_check_vf_rate_limit(struct ixgbe_adapter *adapter); 66 | #endif /* IFLA_VF_MAX */ 67 | void ixgbe_dump_registers(struct ixgbe_adapter *adapter); 68 | 69 | /* 70 | * These are defined in ixgbe_type.h on behalf of the VF driver 71 | * but we need them here unwrapped for the PF driver. 72 | */ 73 | #define IXGBE_DEV_ID_82599_VF 0x10ED 74 | #define IXGBE_DEV_ID_X540_VF 0x1515 75 | #define IXGBE_DEV_ID_X550_VF 0x1565 76 | #endif /* _IXGBE_SRIOV_H_ */ 77 | 78 | -------------------------------------------------------------------------------- /src/ixgbe_dcb_82598.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_DCB_82598_H_ 26 | #define _IXGBE_DCB_82598_H_ 27 | 28 | /* DCB register definitions */ 29 | 30 | #define IXGBE_DPMCS_MTSOS_SHIFT 16 31 | #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 32 | * 1 DFP - Deficit Fixed Priority */ 33 | #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */ 34 | #define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 35 | #define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */ 36 | 37 | #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */ 38 | 39 | #define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 40 | #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */ 41 | 42 | #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 43 | * buffers enable */ 44 | #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 45 | * (RSS) enable */ 46 | 47 | #define IXGBE_TDTQ2TCCR_MCL_SHIFT 12 48 | #define IXGBE_TDTQ2TCCR_BWG_SHIFT 9 49 | #define IXGBE_TDTQ2TCCR_GSP 0x40000000 50 | #define IXGBE_TDTQ2TCCR_LSP 0x80000000 51 | 52 | #define IXGBE_TDPT2TCCR_MCL_SHIFT 12 53 | #define IXGBE_TDPT2TCCR_BWG_SHIFT 9 54 | #define IXGBE_TDPT2TCCR_GSP 0x40000000 55 | #define IXGBE_TDPT2TCCR_LSP 0x80000000 56 | 57 | #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 58 | * 1 DFP - Deficit Fixed Priority */ 59 | #define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */ 60 | #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */ 61 | 62 | #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */ 63 | 64 | #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 65 | #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 66 | #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 67 | #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 68 | 69 | /* DCB driver APIs */ 70 | 71 | /* DCB PFC */ 72 | s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8); 73 | 74 | /* DCB stats */ 75 | s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *); 76 | s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *, 77 | struct ixgbe_hw_stats *, u8); 78 | s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *, 79 | struct ixgbe_hw_stats *, u8); 80 | 81 | /* DCB config arbiters */ 82 | s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, 83 | u8 *, u8 *); 84 | s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, 85 | u8 *, u8 *); 86 | s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *); 87 | 88 | /* DCB initialization */ 89 | s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *); 90 | #endif /* _IXGBE_DCB_82958_H_ */ 91 | -------------------------------------------------------------------------------- /src/ixgbe_dcb_82599.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_DCB_82599_H_ 26 | #define _IXGBE_DCB_82599_H_ 27 | 28 | /* DCB register definitions */ 29 | #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, 30 | * 1 WSP - Weighted Strict Priority 31 | */ 32 | #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, 33 | * 1 WRR - Weighted Round Robin 34 | */ 35 | #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ 36 | #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ 37 | #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must 38 | * clear! 39 | */ 40 | #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ 41 | 42 | /* Receive UP2TC mapping */ 43 | #define IXGBE_RTRUP2TC_UP_SHIFT 3 44 | #define IXGBE_RTRUP2TC_UP_MASK 7 45 | /* Transmit UP2TC mapping */ 46 | #define IXGBE_RTTUP2TC_UP_SHIFT 3 47 | 48 | #define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 49 | #define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ 50 | #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ 51 | #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ 52 | 53 | #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 54 | * buffers enable 55 | */ 56 | #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 57 | * (RSS) enable 58 | */ 59 | 60 | /* RTRPCS Bit Masks */ 61 | #define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 62 | /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 63 | #define IXGBE_RTRPCS_RAC 0x00000004 64 | #define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 65 | 66 | /* RTTDT2C Bit Masks */ 67 | #define IXGBE_RTTDT2C_MCL_SHIFT 12 68 | #define IXGBE_RTTDT2C_BWG_SHIFT 9 69 | #define IXGBE_RTTDT2C_GSP 0x40000000 70 | #define IXGBE_RTTDT2C_LSP 0x80000000 71 | 72 | #define IXGBE_RTTPT2C_MCL_SHIFT 12 73 | #define IXGBE_RTTPT2C_BWG_SHIFT 9 74 | #define IXGBE_RTTPT2C_GSP 0x40000000 75 | #define IXGBE_RTTPT2C_LSP 0x80000000 76 | 77 | /* RTTPCS Bit Masks */ 78 | #define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, 79 | * 1 SP - Strict Priority 80 | */ 81 | #define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ 82 | #define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ 83 | #define IXGBE_RTTPCS_ARBD_SHIFT 22 84 | #define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ 85 | 86 | #define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ 87 | 88 | /* SECTXMINIFG DCB */ 89 | #define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */ 90 | 91 | /* DCB driver APIs */ 92 | 93 | /* DCB PFC */ 94 | s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *); 95 | 96 | /* DCB stats */ 97 | s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *, 98 | struct ixgbe_dcb_config *); 99 | s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *, 100 | struct ixgbe_hw_stats *, u8); 101 | s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *, 102 | struct ixgbe_hw_stats *, u8); 103 | 104 | /* DCB config arbiters */ 105 | s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 106 | u8 *, u8 *); 107 | s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 108 | u8 *, u8 *, u8 *); 109 | s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *, 110 | u8 *, u8 *); 111 | 112 | /* DCB initialization */ 113 | s32 ixgbe_dcb_config_82599(struct ixgbe_hw *, 114 | struct ixgbe_dcb_config *); 115 | 116 | s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, 117 | u8 *, u8 *); 118 | #endif /* _IXGBE_DCB_82959_H_ */ 119 | -------------------------------------------------------------------------------- /src/ixgbe_x550.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_X550_H_ 26 | #define _IXGBE_X550_H_ 27 | 28 | #include "ixgbe_type.h" 29 | 30 | s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw); 31 | s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw); 32 | s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw); 33 | 34 | s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw); 35 | s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw); 36 | s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw); 37 | s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw); 38 | s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size); 39 | s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val); 40 | s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw); 41 | s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 42 | u16 offset, u16 words, u16 *data); 43 | s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 44 | u16 data); 45 | s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 46 | u16 offset, u16 words, u16 *data); 47 | s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 48 | u16 *data); 49 | s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 50 | u16 *data); 51 | s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 52 | u16 data); 53 | s32 ixgbe_set_eee_X550(struct ixgbe_hw *hw, bool enable_eee); 54 | s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee); 55 | void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 56 | unsigned int pool); 57 | void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 58 | bool enable, int vf); 59 | s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 60 | u32 device_type, u32 data); 61 | s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 62 | u32 device_type, u32 *data); 63 | void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw); 64 | void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw); 65 | void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap); 66 | void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf); 67 | enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw); 68 | s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw); 69 | s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 70 | ixgbe_link_speed *speed, bool *autoneg); 71 | void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw); 72 | s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw); 73 | s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw); 74 | s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw); 75 | s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw); 76 | s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw); 77 | s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw); 78 | s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw); 79 | u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw); 80 | void ixgbe_disable_rx_x550(struct ixgbe_hw *hw); 81 | s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed); 82 | s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw); 83 | s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask); 84 | void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask); 85 | s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw); 86 | s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 87 | ixgbe_link_speed speed, 88 | bool autoneg_wait_to_complete); 89 | s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw); 90 | s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 91 | ixgbe_link_speed speed, 92 | bool autoneg_wait_to_complete); 93 | s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 94 | bool *link_up, bool link_up_wait_to_complete); 95 | s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw); 96 | s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw); 97 | s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx); 98 | s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx); 99 | #endif /* _IXGBE_X550_H_ */ 100 | -------------------------------------------------------------------------------- /pci.updates: -------------------------------------------------------------------------------- 1 | # updates for the system pci.ids file 2 | # 3 | # IMPORTANT! Entries in this list must be sorted as they 4 | # would appear in the system pci.ids file. Entries 5 | # are sorted by ven, dev, subven, subdev 6 | # (numerical order). 7 | # 8 | 8086 Intel(R) 9 | 10b6 82598 10GbE PCI-Express Ethernet Controller 10 | 10c6 82598EB 10-Gigabit AF Dual Port Network Connection 11 | 8086 a05f 10-Gigabit XF SR Dual Port Server Adapter 12 | 8086 a15f 10-Gigabit XF SR Dual Port Server Adapter 13 | 10c7 82598EB 10-Gigabit AF Network Connection 14 | 1014 037f 10-Gigabit XF SR Server Adapter 15 | 1014 0380 10-Gigabit XF LR Server Adapter 16 | 8086 a05f 10-Gigabit XF SR Server Adapter 17 | 8086 a15f 10-Gigabit XF SR Server Adapter 18 | 8086 a16f 10-Gigabit XF SR Server Adapter 19 | 10c8 82598EB 10-Gigabit AT Network Connection 20 | 8086 a10c 10-Gigabit AT Server Adapter 21 | 8086 a11c 10-Gigabit AT Server Adapter 22 | 8086 a12c 10-Gigabit AT Server Adapter 23 | 10db 82598EB 10-Gigabit Dual Port Network Connection 24 | 10dd 82598EB 10-Gigabit AT CX4 Network Connection 25 | 10e1 82598EB 10-Gigabit AF Dual Port Network Connection 26 | 8086 a15f 10-Gigabit SR Dual Port Express Module 27 | 10ec 82598EB 10-Gigabit AT CX4 Network Connection 28 | 8086 a01f 10-Gigabit CX4 Dual Port Server Adapter 29 | 8086 a11f 10-Gigabit CX4 Dual Port Server Adapter 30 | 10f1 82598EB 10-Gigabit AF Dual Port Network Connection 31 | 8086 a20f 10-Gigabit AF DA Dual Port Server Adapter 32 | 8086 a21f 10-Gigabit AF DA Dual Port Server Adapter 33 | 10f4 82598EB 10-Gigabit AF Network Connection 34 | 8086 106f 10-Gigabit XF LR Server Adapter 35 | 8086 a06f 10-Gigabit XF LR Server Adapter 36 | 10f7 10-Gigabit BR KX4 Dual Port Network Connection 37 | 108e 7b12 Sun Dual 10GbE PCIe 2.0 FEM 38 | 8086 000d Ethernet Mezzanine Adapter X520-KX4-2 39 | 10f8 82599 10 Gigabit Dual Port Backplane Connection 40 | 1028 1f63 10GbE 2P X520k bNDC 41 | 103c 17d2 Ethernet 10Gb 2-port 560M Adapter 42 | 103c 18d0 HP Ethernet 10Gb 2-port 560FLB Adapter 43 | 8086 000c Ethernet X520 10GbE Dual Port KX4-KR Mezz 44 | 10f9 82599 10 Gigabit CX4 Dual Port Network Connection 45 | 10fb 82599 10 Gigabit Dual Port Network Connection 46 | 1028 06ee Ethernet 10G X520 LOM 47 | 1028 1f72 Ethernet 10G 4P X520/I350 rNDC 48 | 103c 17d0 HP Ethernet 10Gb 2-port 560FLR-SFP+ Adapter 49 | 103c 17d3 HP Ethernet 10Gb 2-port 560SFP+ Adapter 50 | 103c 211b HP Ethernet 10Gb 1-port P560FLR-SFP+ Adapter 51 | 103c 2159 HP Ethernet 10Gb 2-port 562i Adapter 52 | 108e 7b11 Ethernet Server Adapter X520-2 53 | 17aa 1071 ThinkServer X520-2 AnyFabric 54 | 8086 0002 Ethernet Server Adapter X520-DA2 55 | 8086 0003 Ethernet Server Adapter X520-2 56 | 8086 0006 Ethernet Server Adapter X520-1 57 | 8086 0008 Ethernet OCP Server Adapter X520-2 58 | 8086 000a Ethernet Server Adapter X520-1 59 | 8086 000c Ethernet Server Adapter X520-2 60 | 8086 000d Ethernet Server Adapter X520-1OCP 61 | 8086 0470 Ethernet 10GSFP+ DP Embedded CNA X520-2 62 | 8086 7a11 Ethernet Server Adapter X520-2 63 | 8086 7a12 Ethernet Server Adapter X520-2 64 | 10fc 82599 10 Gigabit Dual Port Network Connection 65 | 1507 Ethernet Express Module X520-P2 66 | 108e 7b10 Ethernet Express Module X520-P2 67 | 1508 82598EB Gigabit BX Network Connection 68 | 150b 10-Gigabit AT2 Server Adapter 69 | 8086 a10c 10-Gigabit AT2 Server Adapter 70 | 8086 a11c 10-Gigabit AT2 Server Adapter 71 | 8086 a12c 10-Gigabit AT2 Server Adapter 72 | 1514 Ethernet X520 10GbE Dual Port KX4 Mezz 73 | 8086 000b Ethernet X520 10GbE Dual Port KX4 Mezz 74 | 1517 82599ES 10 Gigabit Network Connection 75 | 1137 006a Cisco UCS CNA M61KR-I Intel Converged Network Adapter 76 | 151c 82599 10 Gigabit TN Network Connection 77 | 108e 7b13 Sun Dual 10GBASE-T LP 78 | 8086 a02c Ethernet Server Adapter X520-T2 79 | 8086 a03c Ethernet Server Adapter X520-T2 80 | 8086 a21c Ethernet Server Adapter X520-T2 81 | 1528 Ethernet Controller X540-AT2 82 | 1028 1f61 Ethernet 10G 4P X540/I350 rNDC 83 | 103c 192d HP Ethernet 10Gb 2-port 561FLR-T Adapter 84 | 103c 211a HP Ethernet 10Gb 2-port 561T Adapter 85 | 108e 7b14 Sun Dual Port 10 GbE PCIe 2.0 ExpressModule, Base-T 86 | 108e 7b15 Sun Dual Port 10 GbE PCIe 2.0 Low Profile Adapter, Base-T 87 | 1137 00bf Ethernet Converged Network Adapter X540-T2 88 | 17aa 1073 ThinkServer X540-T2 AnyFabric 89 | 8086 0001 Ethernet Converged Network Adapter X540-T2 90 | 8086 0002 Ethernet Converged Network Adapter X540-T1 91 | 8086 001a Ethernet Converged Network Adapter X540-T2 92 | 8086 00a2 Ethernet Converged Network Adapter X540-T1 93 | 8086 0471 Ethernet 10GBT DP Embedded CNA X540-T2 94 | 8086 5003 Ethernet 10G 2P X540-t Adapter 95 | 8086 5004 Ethernet 10G 2P X540-t Adapter 96 | 1529 82599 10 Gigabit Dual Port Network Connection with FCoE 97 | 152a 82599 10 Gigabit Dual Port Backplane Connection with FCoE 98 | 154a Ethernet Converged Network Adapter X520-4 99 | 8086 011a Ethernet Converged Network Adapter X520-4 100 | 8086 011b Ethernet Converged Network Adapter X520-4 101 | 8086 011c Ethernet Converged Network Adapter X520-4 102 | 154d Ethernet 10G 2P X520 Adapter 103 | 8086 7b11 Ethernet 10G 2P X520 Adapter 104 | 154f 82599 10 Gigabit Dual Port Network Connection 105 | 1557 82599 10 Gigabit Network Connection 106 | 8086 0001 Ethernet OCP Server Adapter X520-1 107 | 1558 Ethernet Converged Network Adapter X520-Q1 108 | 8086 011a Ethernet Converged Network Adapter X520-Q1 109 | 8086 011b Ethernet Converged Network Adapter X520-Q1 110 | 1560 Ethernet Controller X540 111 | 1563 Ethernet Controller 10G X550T 112 | 8086 0001 Ethernet Converged Network Adapter X550-T2 113 | 8086 0002 Ethernet Converged Network Adapter X550-T1 114 | 8086 001A Ethernet Converged Network Adapter X550-T2 115 | 8086 00A2 Ethernet Converged Network Adapter X550-T1 116 | 15AA Ethernet Connection X552 10 GbE Backplane 117 | 15AB Ethernet Connection X552 10 GbE Backplane 118 | 15AC Ethernet Controller 10G X550EM SFP 119 | 15AD Ethernet Connection X552/X557-AT 10GBASE-T 120 | 15AE Ethernet Controller 1G X550EM Copper 121 | -------------------------------------------------------------------------------- /src/ixgbe_dcb.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_DCB_H_ 26 | #define _IXGBE_DCB_H_ 27 | 28 | #include "ixgbe_type.h" 29 | 30 | /* DCB defines */ 31 | /* DCB credit calculation defines */ 32 | #define IXGBE_DCB_CREDIT_QUANTUM 64 33 | #define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */ 34 | #define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/ 35 | #define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL) 36 | 37 | /* 513 for 32KB TSO packet */ 38 | #define IXGBE_DCB_MIN_TSO_CREDIT \ 39 | ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1) 40 | 41 | /* DCB configuration defines */ 42 | #define IXGBE_DCB_MAX_USER_PRIORITY 8 43 | #define IXGBE_DCB_MAX_BW_GROUP 8 44 | #define IXGBE_DCB_BW_PERCENT 100 45 | 46 | #define IXGBE_DCB_TX_CONFIG 0 47 | #define IXGBE_DCB_RX_CONFIG 1 48 | 49 | /* DCB capability defines */ 50 | #define IXGBE_DCB_PG_SUPPORT 0x00000001 51 | #define IXGBE_DCB_PFC_SUPPORT 0x00000002 52 | #define IXGBE_DCB_BCN_SUPPORT 0x00000004 53 | #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 54 | #define IXGBE_DCB_GSP_SUPPORT 0x00000010 55 | 56 | struct ixgbe_dcb_support { 57 | u32 capabilities; /* DCB capabilities */ 58 | 59 | /* Each bit represents a number of TCs configurable in the hw. 60 | * If 8 traffic classes can be configured, the value is 0x80. */ 61 | u8 traffic_classes; 62 | u8 pfc_traffic_classes; 63 | }; 64 | 65 | enum ixgbe_dcb_tsa { 66 | ixgbe_dcb_tsa_ets = 0, 67 | ixgbe_dcb_tsa_group_strict_cee, 68 | ixgbe_dcb_tsa_strict 69 | }; 70 | 71 | /* Traffic class bandwidth allocation per direction */ 72 | struct ixgbe_dcb_tc_path { 73 | u8 bwg_id; /* Bandwidth Group (BWG) ID */ 74 | u8 bwg_percent; /* % of BWG's bandwidth */ 75 | u8 link_percent; /* % of link bandwidth */ 76 | u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ 77 | u16 data_credits_refill; /* Credit refill amount in 64B granularity */ 78 | u16 data_credits_max; /* Max credits for a configured packet buffer 79 | * in 64B granularity.*/ 80 | enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */ 81 | }; 82 | 83 | enum ixgbe_dcb_pfc { 84 | ixgbe_dcb_pfc_disabled = 0, 85 | ixgbe_dcb_pfc_enabled, 86 | ixgbe_dcb_pfc_enabled_txonly, 87 | ixgbe_dcb_pfc_enabled_rxonly 88 | }; 89 | 90 | /* Traffic class configuration */ 91 | struct ixgbe_dcb_tc_config { 92 | struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */ 93 | enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */ 94 | 95 | u16 desc_credits_max; /* For Tx Descriptor arbitration */ 96 | u8 tc; /* Traffic class (TC) */ 97 | }; 98 | 99 | enum ixgbe_dcb_pba { 100 | /* PBA[0-7] each use 64KB FIFO */ 101 | ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL, 102 | /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ 103 | ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED 104 | }; 105 | 106 | struct ixgbe_dcb_num_tcs { 107 | u8 pg_tcs; 108 | u8 pfc_tcs; 109 | }; 110 | 111 | struct ixgbe_dcb_config { 112 | struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 113 | struct ixgbe_dcb_support support; 114 | struct ixgbe_dcb_num_tcs num_tcs; 115 | u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */ 116 | bool pfc_mode_enable; 117 | bool round_robin_enable; 118 | 119 | enum ixgbe_dcb_pba rx_pba_cfg; 120 | 121 | u32 dcb_cfg_version; /* Not used...OS-specific? */ 122 | u32 link_speed; /* For bandwidth allocation validation purpose */ 123 | bool vt_mode; 124 | }; 125 | 126 | /* DCB driver APIs */ 127 | 128 | /* DCB rule checking */ 129 | s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *); 130 | 131 | /* DCB credits calculation */ 132 | s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int); 133 | s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *, 134 | struct ixgbe_dcb_config *, u32, u8); 135 | 136 | /* DCB PFC */ 137 | s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *); 138 | s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 139 | 140 | /* DCB stats */ 141 | s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *); 142 | s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 143 | s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 144 | 145 | /* DCB config arbiters */ 146 | s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *, 147 | struct ixgbe_dcb_config *); 148 | s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *, 149 | struct ixgbe_dcb_config *); 150 | s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *, 151 | struct ixgbe_dcb_config *); 152 | 153 | /* DCB unpack routines */ 154 | void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *); 155 | void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *); 156 | void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *); 157 | void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *); 158 | void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *); 159 | void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *); 160 | u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8); 161 | 162 | /* DCB initialization */ 163 | s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *); 164 | s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 165 | #endif /* _IXGBE_DCB_H_ */ 166 | -------------------------------------------------------------------------------- /src/ixgbe_mbx.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_MBX_H_ 26 | #define _IXGBE_MBX_H_ 27 | 28 | #include "ixgbe_type.h" 29 | 30 | #define IXGBE_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */ 31 | #define IXGBE_ERR_MBX -100 32 | 33 | #define IXGBE_VFMAILBOX 0x002FC 34 | #define IXGBE_VFMBMEM 0x00200 35 | 36 | /* Define mailbox register bits */ 37 | #define IXGBE_VFMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */ 38 | #define IXGBE_VFMAILBOX_ACK 0x00000002 /* Ack PF message received */ 39 | #define IXGBE_VFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */ 40 | #define IXGBE_VFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */ 41 | #define IXGBE_VFMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */ 42 | #define IXGBE_VFMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */ 43 | #define IXGBE_VFMAILBOX_RSTI 0x00000040 /* PF has reset indication */ 44 | #define IXGBE_VFMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */ 45 | #define IXGBE_VFMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */ 46 | 47 | #define IXGBE_PFMAILBOX_STS 0x00000001 /* Initiate message send to VF */ 48 | #define IXGBE_PFMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */ 49 | #define IXGBE_PFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */ 50 | #define IXGBE_PFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */ 51 | #define IXGBE_PFMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */ 52 | 53 | #define IXGBE_MBVFICR_VFREQ_MASK 0x0000FFFF /* bits for VF messages */ 54 | #define IXGBE_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */ 55 | #define IXGBE_MBVFICR_VFACK_MASK 0xFFFF0000 /* bits for VF acks */ 56 | #define IXGBE_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */ 57 | 58 | /* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the 59 | * PF. The reverse is true if it is IXGBE_PF_*. 60 | * Message ACK's are the value or'd with 0xF0000000 61 | */ 62 | #define IXGBE_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with 63 | * this are the ACK */ 64 | #define IXGBE_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with 65 | * this are the NACK */ 66 | #define IXGBE_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still 67 | * clear to send requests */ 68 | #define IXGBE_VT_MSGINFO_SHIFT 16 69 | /* bits 23:16 are used for extra info for certain messages */ 70 | #define IXGBE_VT_MSGINFO_MASK (0xFF << IXGBE_VT_MSGINFO_SHIFT) 71 | 72 | /* definitions to support mailbox API version negotiation */ 73 | 74 | /* 75 | * each element denotes a version of the API; existing numbers may not 76 | * change; any additions must go at the end 77 | */ 78 | enum ixgbe_pfvf_api_rev { 79 | ixgbe_mbox_api_10, /* API version 1.0, linux/freebsd VF driver */ 80 | ixgbe_mbox_api_20, /* API version 2.0, solaris Phase1 VF driver */ 81 | ixgbe_mbox_api_11, /* API version 1.1, linux/freebsd VF driver */ 82 | /* This value should always be last */ 83 | ixgbe_mbox_api_unknown, /* indicates that API version is not known */ 84 | }; 85 | 86 | /* mailbox API, legacy requests */ 87 | #define IXGBE_VF_RESET 0x01 /* VF requests reset */ 88 | #define IXGBE_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */ 89 | #define IXGBE_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */ 90 | #define IXGBE_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */ 91 | 92 | /* mailbox API, version 1.0 VF requests */ 93 | #define IXGBE_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */ 94 | #define IXGBE_VF_SET_MACVLAN 0x06 /* VF requests PF for unicast filter */ 95 | #define IXGBE_VF_API_NEGOTIATE 0x08 /* negotiate API version */ 96 | 97 | /* mailbox API, version 1.1 VF requests */ 98 | #define IXGBE_VF_GET_QUEUES 0x09 /* get queue configuration */ 99 | 100 | /* GET_QUEUES return data indices within the mailbox */ 101 | #define IXGBE_VF_TX_QUEUES 1 /* number of Tx queues supported */ 102 | #define IXGBE_VF_RX_QUEUES 2 /* number of Rx queues supported */ 103 | #define IXGBE_VF_TRANS_VLAN 3 /* Indication of port vlan */ 104 | #define IXGBE_VF_DEF_QUEUE 4 /* Default queue offset */ 105 | 106 | /* length of permanent address message returned from PF */ 107 | #define IXGBE_VF_PERMADDR_MSG_LEN 4 108 | /* word in permanent address message with the current multicast type */ 109 | #define IXGBE_VF_MC_TYPE_WORD 3 110 | 111 | #define IXGBE_PF_CONTROL_MSG 0x0100 /* PF control message */ 112 | 113 | /* mailbox API, version 2.0 VF requests */ 114 | #define IXGBE_VF_API_NEGOTIATE 0x08 /* negotiate API version */ 115 | #define IXGBE_VF_GET_QUEUES 0x09 /* get queue configuration */ 116 | #define IXGBE_VF_ENABLE_MACADDR 0x0A /* enable MAC address */ 117 | #define IXGBE_VF_DISABLE_MACADDR 0x0B /* disable MAC address */ 118 | #define IXGBE_VF_GET_MACADDRS 0x0C /* get all configured MAC addrs */ 119 | #define IXGBE_VF_SET_MCAST_PROMISC 0x0D /* enable multicast promiscuous */ 120 | #define IXGBE_VF_GET_MTU 0x0E /* get bounds on MTU */ 121 | #define IXGBE_VF_SET_MTU 0x0F /* set a specific MTU */ 122 | 123 | /* mailbox API, version 2.0 PF requests */ 124 | #define IXGBE_PF_TRANSPARENT_VLAN 0x0101 /* enable transparent vlan */ 125 | 126 | #define IXGBE_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */ 127 | #define IXGBE_VF_MBX_INIT_DELAY 500 /* microseconds between retries */ 128 | 129 | s32 ixgbe_read_mbx(struct ixgbe_hw *, u32 *, u16, u16); 130 | s32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16); 131 | s32 ixgbe_read_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16); 132 | s32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16); 133 | s32 ixgbe_check_for_msg(struct ixgbe_hw *, u16); 134 | s32 ixgbe_check_for_ack(struct ixgbe_hw *, u16); 135 | s32 ixgbe_check_for_rst(struct ixgbe_hw *, u16); 136 | void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw); 137 | void ixgbe_init_mbx_params_vf(struct ixgbe_hw *); 138 | void ixgbe_init_mbx_params_pf(struct ixgbe_hw *); 139 | 140 | #endif /* _IXGBE_MBX_H_ */ 141 | -------------------------------------------------------------------------------- /scripts/set_irq_affinity: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # Copyright (c) 2014, Intel Corporation 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are met: 7 | # 8 | # * Redistributions of source code must retain the above copyright notice, 9 | # this list of conditions and the following disclaimer. 10 | # * Redistributions in binary form must reproduce the above copyright 11 | # notice, this list of conditions and the following disclaimer in the 12 | # documentation and/or other materials provided with the distribution. 13 | # * Neither the name of Intel Corporation nor the names of its contributors 14 | # may be used to endorse or promote products derived from this software 15 | # without specific prior written permission. 16 | # 17 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 20 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 21 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 24 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | # 28 | # Affinitize interrupts to cores 29 | # 30 | # typical usage is (as root): 31 | # set_irq_affinity -x local eth1 32 | # 33 | # to get help: 34 | # set_irq_affinity 35 | 36 | usage() 37 | { 38 | echo 39 | echo "Usage: $0 [-x] {all|local|remote|one|custom} [ethX] <[ethY]>" 40 | echo " options: -x Configure XPS as well as smp_affinity" 41 | echo " options: {remote|one} can be followed by a specific node number" 42 | echo " Ex: $0 local eth0" 43 | echo " Ex: $0 remote 1 eth0" 44 | echo " Ex: $0 custom eth0 eth1" 45 | echo " Ex: $0 0-7,16-23 eth0" 46 | echo 47 | exit 1 48 | } 49 | 50 | if [ "$1" == "-x" ]; then 51 | XPS_ENA=1 52 | shift 53 | fi 54 | 55 | num='^[0-9]+$' 56 | # Vars 57 | AFF=$1 58 | shift 59 | 60 | case "$AFF" in 61 | remote) [[ $1 =~ $num ]] && rnode=$1 && shift ;; 62 | one) [[ $1 =~ $num ]] && cnt=$1 && shift ;; 63 | all) ;; 64 | local) ;; 65 | custom) ;; 66 | [0-9]*) ;; 67 | -h|--help) usage ;; 68 | "") usage ;; 69 | *) IFACES=$AFF && AFF=all ;; # Backwards compat mode 70 | esac 71 | 72 | # append the interfaces listed to the string with spaces 73 | while [ "$#" -ne "0" ] ; do 74 | IFACES+=" $1" 75 | shift 76 | done 77 | 78 | # for now the user must specify interfaces 79 | if [ -z "$IFACES" ]; then 80 | usage 81 | exit 1 82 | fi 83 | 84 | # support functions 85 | 86 | set_affinity() 87 | { 88 | VEC=$core 89 | if [ $VEC -ge 32 ] 90 | then 91 | MASK_FILL="" 92 | MASK_ZERO="00000000" 93 | let "IDX = $VEC / 32" 94 | for ((i=1; i<=$IDX;i++)) 95 | do 96 | MASK_FILL="${MASK_FILL},${MASK_ZERO}" 97 | done 98 | 99 | let "VEC -= 32 * $IDX" 100 | MASK_TMP=$((1<<$VEC)) 101 | MASK=$(printf "%X%s" $MASK_TMP $MASK_FILL) 102 | else 103 | MASK_TMP=$((1<<$VEC)) 104 | MASK=$(printf "%X" $MASK_TMP) 105 | fi 106 | 107 | printf "%s" $MASK > /proc/irq/$IRQ/smp_affinity 108 | printf "%s %d %s -> /proc/irq/$IRQ/smp_affinity\n" $IFACE $core $MASK 109 | if ! [ -z "$XPS_ENA" ]; then 110 | printf "%s %d %s -> /sys/class/net/%s/queues/tx-%d/xps_cpus\n" $IFACE $core $MASK $IFACE $((n-1)) 111 | printf "%s" $MASK > /sys/class/net/$IFACE/queues/tx-$((n-1))/xps_cpus 112 | fi 113 | } 114 | 115 | # Allow usage of , or - 116 | # 117 | parse_range () { 118 | RANGE=${@//,/ } 119 | RANGE=${RANGE//-/..} 120 | LIST="" 121 | for r in $RANGE; do 122 | # eval lets us use vars in {#..#} range 123 | [[ $r =~ '..' ]] && r="$(eval echo {$r})" 124 | LIST+=" $r" 125 | done 126 | echo $LIST 127 | } 128 | 129 | # Affinitize interrupts 130 | # 131 | setaff() 132 | { 133 | CORES=$(parse_range $CORES) 134 | ncores=$(echo $CORES | wc -w) 135 | n=1 136 | 137 | # this script only supports interrupt vectors in pairs, 138 | # modification would be required to support a single Tx or Rx queue 139 | # per interrupt vector 140 | 141 | queues="${IFACE}-.*TxRx" 142 | 143 | irqs=$(grep "$queues" /proc/interrupts | cut -f1 -d:) 144 | [ -z "$irqs" ] && irqs=$(grep $IFACE /proc/interrupts | cut -f1 -d:) 145 | [ -z "$irqs" ] && irqs=$(for i in `ls -Ux /sys/class/net/$IFACE/device/msi_irqs` ;\ 146 | do grep "$i:.*TxRx" /proc/interrupts | grep -v fdir | cut -f 1 -d : ;\ 147 | done) 148 | [ -z "$irqs" ] && echo "Error: Could not find interrupts for $IFACE" 149 | 150 | echo "IFACE CORE MASK -> FILE" 151 | echo "=======================" 152 | for IRQ in $irqs; do 153 | [ "$n" -gt "$ncores" ] && n=1 154 | j=1 155 | # much faster than calling cut for each 156 | for i in $CORES; do 157 | [ $((j++)) -ge $n ] && break 158 | done 159 | core=$i 160 | set_affinity 161 | ((n++)) 162 | done 163 | } 164 | 165 | # now the actual useful bits of code 166 | 167 | # these next 2 lines would allow script to auto-determine interfaces 168 | #[ -z "$IFACES" ] && IFACES=$(ls /sys/class/net) 169 | #[ -z "$IFACES" ] && echo "Error: No interfaces up" && exit 1 170 | 171 | # echo IFACES is $IFACES 172 | 173 | CORES=$( 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | 26 | /* glue for the OS independent part of ixgbe 27 | * includes register access macros 28 | */ 29 | 30 | #ifndef _IXGBE_OSDEP_H_ 31 | #define _IXGBE_OSDEP_H_ 32 | 33 | #include 34 | #include 35 | #include 36 | #include 37 | #include 38 | #include "kcompat.h" 39 | 40 | #define IXGBE_CPU_TO_BE16(_x) cpu_to_be16(_x) 41 | #define IXGBE_BE16_TO_CPU(_x) be16_to_cpu(_x) 42 | #define IXGBE_CPU_TO_BE32(_x) cpu_to_be32(_x) 43 | #define IXGBE_BE32_TO_CPU(_x) be32_to_cpu(_x) 44 | 45 | #define msec_delay(_x) msleep(_x) 46 | 47 | #define usec_delay(_x) udelay(_x) 48 | 49 | #define STATIC static 50 | 51 | #define IOMEM __iomem 52 | 53 | #ifdef DBG 54 | #define ASSERT(_x) BUG_ON(!(_x)) 55 | #define DEBUGOUT(S) printk(KERN_DEBUG S) 56 | #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S, ## A) 57 | #define DEBUGOUT2(S, A...) printk(KERN_DEBUG S, ## A) 58 | #define DEBUGOUT3(S, A...) printk(KERN_DEBUG S, ## A) 59 | #define DEBUGOUT4(S, A...) printk(KERN_DEBUG S, ## A) 60 | #define DEBUGOUT5(S, A...) printk(KERN_DEBUG S, ## A) 61 | #define DEBUGOUT6(S, A...) printk(KERN_DEBUG S, ## A) 62 | #else 63 | #define ASSERT(_x) do {} while (0) 64 | #define DEBUGOUT(S) do {} while (0) 65 | #define DEBUGOUT1(S, A...) do {} while (0) 66 | #define DEBUGOUT2(S, A...) do {} while (0) 67 | #define DEBUGOUT3(S, A...) do {} while (0) 68 | #define DEBUGOUT4(S, A...) do {} while (0) 69 | #define DEBUGOUT5(S, A...) do {} while (0) 70 | #define DEBUGOUT6(S, A...) do {} while (0) 71 | #endif 72 | 73 | #define DEBUGFUNC(S) do {} while (0) 74 | 75 | #define IXGBE_SFP_DETECT_RETRIES 2 76 | 77 | struct ixgbe_hw; 78 | struct ixgbe_msg { 79 | u16 msg_enable; 80 | }; 81 | struct net_device *ixgbe_hw_to_netdev(const struct ixgbe_hw *hw); 82 | struct ixgbe_msg *ixgbe_hw_to_msg(const struct ixgbe_hw *hw); 83 | 84 | #define hw_dbg(hw, format, arg...) \ 85 | netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg) 86 | #define hw_err(hw, format, arg...) \ 87 | netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg) 88 | #define e_dev_info(format, arg...) \ 89 | dev_info(pci_dev_to_dev(adapter->pdev), format, ## arg) 90 | #define e_dev_warn(format, arg...) \ 91 | dev_warn(pci_dev_to_dev(adapter->pdev), format, ## arg) 92 | #define e_dev_err(format, arg...) \ 93 | dev_err(pci_dev_to_dev(adapter->pdev), format, ## arg) 94 | #define e_dev_notice(format, arg...) \ 95 | dev_notice(pci_dev_to_dev(adapter->pdev), format, ## arg) 96 | #define e_dbg(msglvl, format, arg...) \ 97 | netif_dbg(adapter, msglvl, adapter->netdev, format, ## arg) 98 | #define e_info(msglvl, format, arg...) \ 99 | netif_info(adapter, msglvl, adapter->netdev, format, ## arg) 100 | #define e_err(msglvl, format, arg...) \ 101 | netif_err(adapter, msglvl, adapter->netdev, format, ## arg) 102 | #define e_warn(msglvl, format, arg...) \ 103 | netif_warn(adapter, msglvl, adapter->netdev, format, ## arg) 104 | #define e_crit(msglvl, format, arg...) \ 105 | netif_crit(adapter, msglvl, adapter->netdev, format, ## arg) 106 | 107 | #define IXGBE_DEAD_READ_RETRIES 10 108 | #define IXGBE_DEAD_READ_REG 0xdeadbeefU 109 | #define IXGBE_FAILED_READ_REG 0xffffffffU 110 | #define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU 111 | #define IXGBE_FAILED_READ_CFG_WORD 0xffffU 112 | #define IXGBE_FAILED_READ_CFG_BYTE 0xffU 113 | 114 | #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \ 115 | IXGBE_WRITE_REG((a), (reg) + ((offset) << 2), (value)) 116 | 117 | #define IXGBE_READ_REG(h, r) ixgbe_read_reg(h, r, false) 118 | #define IXGBE_R32_Q(h, r) ixgbe_read_reg(h, r, true) 119 | 120 | #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \ 121 | IXGBE_READ_REG((a), (reg) + ((offset) << 2))) 122 | 123 | #ifndef writeq 124 | #define writeq(val, addr) do { writel((u32) (val), addr); \ 125 | writel((u32) (val >> 32), (addr + 4)); \ 126 | } while (0); 127 | #endif 128 | 129 | #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) 130 | 131 | u32 ixgbe_read_reg(struct ixgbe_hw *, u32 reg, bool quiet); 132 | extern u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg); 133 | extern void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value); 134 | extern void ewarn(struct ixgbe_hw *hw, const char *str, u32 status); 135 | 136 | #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg_word 137 | #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg_word 138 | #define IXGBE_EEPROM_GRANT_ATTEMPS 100 139 | #define IXGBE_HTONL(_i) htonl(_i) 140 | #define IXGBE_NTOHL(_i) ntohl(_i) 141 | #define IXGBE_NTOHS(_i) ntohs(_i) 142 | #define IXGBE_CPU_TO_LE32(_i) cpu_to_le32(_i) 143 | #define IXGBE_LE32_TO_CPUS(_i) le32_to_cpus(_i) 144 | #define EWARN(H, W, S) ewarn(H, W, S) 145 | 146 | enum { 147 | IXGBE_ERROR_SOFTWARE, 148 | IXGBE_ERROR_POLLING, 149 | IXGBE_ERROR_INVALID_STATE, 150 | IXGBE_ERROR_UNSUPPORTED, 151 | IXGBE_ERROR_ARGUMENT, 152 | IXGBE_ERROR_CAUTION, 153 | }; 154 | 155 | #define ERROR_REPORT(level, format, arg...) do { \ 156 | switch (level) { \ 157 | case IXGBE_ERROR_SOFTWARE: \ 158 | case IXGBE_ERROR_CAUTION: \ 159 | case IXGBE_ERROR_POLLING: \ 160 | netif_warn(ixgbe_hw_to_msg(hw), drv, ixgbe_hw_to_netdev(hw), \ 161 | format, ## arg); \ 162 | break; \ 163 | case IXGBE_ERROR_INVALID_STATE: \ 164 | case IXGBE_ERROR_UNSUPPORTED: \ 165 | case IXGBE_ERROR_ARGUMENT: \ 166 | netif_err(ixgbe_hw_to_msg(hw), hw, ixgbe_hw_to_netdev(hw), \ 167 | format, ## arg); \ 168 | break; \ 169 | default: \ 170 | break; \ 171 | } \ 172 | } while (0) 173 | 174 | #define ERROR_REPORT1 ERROR_REPORT 175 | #define ERROR_REPORT2 ERROR_REPORT 176 | #define ERROR_REPORT3 ERROR_REPORT 177 | 178 | #define UNREFERENCED_XPARAMETER 179 | #define UNREFERENCED_1PARAMETER(_p) do { \ 180 | uninitialized_var(_p); \ 181 | } while (0) 182 | #define UNREFERENCED_2PARAMETER(_p, _q) do { \ 183 | uninitialized_var(_p); \ 184 | uninitialized_var(_q); \ 185 | } while (0) 186 | #define UNREFERENCED_3PARAMETER(_p, _q, _r) do { \ 187 | uninitialized_var(_p); \ 188 | uninitialized_var(_q); \ 189 | uninitialized_var(_r); \ 190 | } while (0) 191 | #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) do { \ 192 | uninitialized_var(_p); \ 193 | uninitialized_var(_q); \ 194 | uninitialized_var(_r); \ 195 | uninitialized_var(_s); \ 196 | } while (0) 197 | 198 | #endif /* _IXGBE_OSDEP_H_ */ 199 | -------------------------------------------------------------------------------- /src/ixgbe_common.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Intel 10 Gigabit PCI Express Linux driver 4 | Copyright (c) 1999 - 2014 Intel Corporation. 5 | 6 | This program is free software; you can redistribute it and/or modify it 7 | under the terms and conditions of the GNU General Public License, 8 | version 2, as published by the Free Software Foundation. 9 | 10 | This program is distributed in the hope it will be useful, but WITHOUT 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | more details. 14 | 15 | The full GNU General Public License is included in this distribution in 16 | the file called "COPYING". 17 | 18 | Contact Information: 19 | Linux NICS 20 | e1000-devel Mailing List 21 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 | 23 | *******************************************************************************/ 24 | 25 | #ifndef _IXGBE_COMMON_H_ 26 | #define _IXGBE_COMMON_H_ 27 | 28 | #include "ixgbe_type.h" 29 | 30 | void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map); 31 | 32 | u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw); 33 | s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw); 34 | s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw); 35 | s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw); 36 | s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw); 37 | s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw); 38 | s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 39 | u32 pba_num_size); 40 | s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr); 41 | s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw); 42 | void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status); 43 | void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw); 44 | s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw); 45 | 46 | s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index); 47 | s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index); 48 | 49 | s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); 50 | s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); 51 | s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 52 | u16 words, u16 *data); 53 | s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); 54 | s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 55 | u16 words, u16 *data); 56 | s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data); 57 | s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 58 | u16 words, u16 *data); 59 | s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 60 | u16 *data); 61 | s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 62 | u16 words, u16 *data); 63 | s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw); 64 | s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 65 | u16 *checksum_val); 66 | s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw); 67 | s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 68 | 69 | s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 70 | u32 enable_addr); 71 | s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index); 72 | s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw); 73 | s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 74 | u32 mc_addr_count, 75 | ixgbe_mc_addr_itr func, bool clear); 76 | s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 77 | u32 addr_count, ixgbe_mc_addr_itr func); 78 | s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw); 79 | s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw); 80 | s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval); 81 | s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw); 82 | s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw); 83 | 84 | s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw); 85 | bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw); 86 | void ixgbe_fc_autoneg(struct ixgbe_hw *hw); 87 | s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw); 88 | 89 | s32 ixgbe_validate_mac_addr(u8 *mac_addr); 90 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask); 91 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask); 92 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 93 | 94 | s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val); 95 | s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked); 96 | 97 | s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index); 98 | s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index); 99 | 100 | s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr); 101 | s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr); 102 | 103 | s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 104 | s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq); 105 | s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 106 | s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 107 | s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw); 108 | s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, 109 | u32 vind, bool vlan_on); 110 | s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 111 | bool vlan_on, bool *vfta_changed); 112 | s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw); 113 | s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan); 114 | 115 | s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, 116 | ixgbe_link_speed *speed, 117 | bool *link_up, bool link_up_wait_to_complete); 118 | 119 | s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 120 | u16 *wwpn_prefix); 121 | 122 | s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs); 123 | void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf); 124 | void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); 125 | s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps); 126 | void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 127 | int strategy); 128 | s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 129 | u8 build, u8 ver); 130 | u8 ixgbe_calculate_checksum(u8 *buffer, u32 length); 131 | s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 132 | u32 length, u32 timeout, bool return_data); 133 | 134 | void ixgbe_clear_tx_pending(struct ixgbe_hw *hw); 135 | 136 | extern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 137 | extern void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 138 | bool ixgbe_mng_present(struct ixgbe_hw *hw); 139 | bool ixgbe_mng_enabled(struct ixgbe_hw *hw); 140 | 141 | #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8 142 | #define IXGBE_EMC_INTERNAL_DATA 0x00 143 | #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20 144 | #define IXGBE_EMC_DIODE1_DATA 0x01 145 | #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19 146 | #define IXGBE_EMC_DIODE2_DATA 0x23 147 | #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A 148 | #define IXGBE_EMC_DIODE3_DATA 0x2A 149 | #define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30 150 | 151 | s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw); 152 | s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw); 153 | void ixgbe_disable_rx_generic(struct ixgbe_hw *hw); 154 | void ixgbe_enable_rx_generic(struct ixgbe_hw *hw); 155 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 156 | ixgbe_link_speed speed, 157 | bool autoneg_wait_to_complete); 158 | void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 159 | ixgbe_link_speed speed); 160 | #endif /* IXGBE_COMMON */ 161 | -------------------------------------------------------------------------------- /ixgbe.7: -------------------------------------------------------------------------------- 1 | .\" LICENSE 2 | .\" 3 | .\" This software program is released under the terms of a license agreement between you ('Licensee') and Intel. Do not use or load this software or any associated materials (collectively, the 'Software') until you have carefully read the full terms and conditions of the LICENSE located in this software package. By loading or using the Software, you agree to the terms of this Agreement. If you do not agree with the terms of this Agreement, do not install or use the Software. 4 | .\" 5 | .\" * Other names and brands may be claimed as the property of others. 6 | .\" 7 | .TH ixgbe 1 "April 1, 2013" 8 | 9 | .SH NAME 10 | ixgbe \-This file describes the Linux* Base Driver for the 10 Gigabit Family of Adapters. 11 | .SH SYNOPSIS 12 | .PD 0.4v 13 | modprobe ixgbe [