├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── images ├── centralized_avsddac.png ├── inside_dac.png ├── inside_pll.png ├── openlane_flow.png ├── physical_design.png ├── post_routing_sim.png ├── post_synth_sim.png ├── pre_synth_sim.png ├── rvmyth_layout.png ├── selected_dac.png ├── selected_pll.png ├── vsdbabysoc_block_diagram.png └── vsdbabysoc_layout.png └── src ├── gds ├── avsddac.gds └── avsdpll.gds ├── gls_model ├── primitives.v └── sky130_fd_sc_hd.v ├── include ├── sandpiper.vh ├── sandpiper_gen.vh ├── sp_default.vh └── sp_verilog.vh ├── layout_conf ├── rvmyth │ ├── config.tcl │ └── pin_order.cfg └── vsdbabysoc │ ├── config.tcl │ ├── macro.cfg │ └── pin_order.cfg ├── lef ├── avsddac.lef └── avsdpll.lef ├── lib ├── avsddac.lib ├── avsdpll.lib └── sky130_fd_sc_hd__tt_025C_1v80.lib ├── module ├── avsddac.v ├── avsdpll.v ├── clk_gate.v ├── pseudo_rand.sv ├── pseudo_rand_gen.sv ├── rvmyth.tlv ├── testbench.rvmyth.post-routing.v ├── testbench.v └── vsdbabysoc.v ├── script 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