├── Module.manifest
├── data
    ├── languages
    │   ├── fuc5_inst.sinc
    │   ├── falcon.opinion
    │   ├── falcon_v4.slaspec
    │   ├── falcon_v5.slaspec
    │   ├── falcon.pspec
    │   ├── sized.sinc
    │   ├── falcon.cspec
    │   ├── falcon.ldefs
    │   ├── macro.sinc
    │   ├── unsized_inst.sinc
    │   ├── base_falcon.slaspec
    │   ├── crypt_inst.sinc
    │   ├── sized_include.sinc
    │   └── envydis.sinc
    ├── testing
    │   ├── simple_flow.asm
    │   ├── Makefile
    │   └── faucon.asm
    └── build.xml
├── images
    └── screenshot1.png
├── .mailmap
├── gradle
    └── wrapper
    │   ├── gradle-wrapper.jar
    │   └── gradle-wrapper.properties
├── extension.properties
├── LICENSE.txt
├── gradlew.bat
├── .github
    └── workflows
    │   └── build.yml
├── .gitignore
├── gradlew
├── src
    └── main
    │   └── java
    │       └── zone
    │           └── mary
    │               └── ghidra
    │                   └── falcon
    │                       └── NvidiaGRBootloaderLoader.java
└── README.md


/Module.manifest:
--------------------------------------------------------------------------------
1 | 


--------------------------------------------------------------------------------
/data/languages/fuc5_inst.sinc:
--------------------------------------------------------------------------------
1 | 


--------------------------------------------------------------------------------
/data/languages/falcon.opinion:
--------------------------------------------------------------------------------
1 | <opinions>
2 | </opinions>
3 | 


--------------------------------------------------------------------------------
/images/screenshot1.png:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/marysaka/ghidra_falcon/HEAD/images/screenshot1.png


--------------------------------------------------------------------------------
/.mailmap:
--------------------------------------------------------------------------------
1 | Mary Guillemard <mary@mary.zone> Mary <mary@mary.zone>
2 | Mary Guillemard <mary@mary.zone> <me@thog.eu>
3 | 


--------------------------------------------------------------------------------
/data/testing/simple_flow.asm:
--------------------------------------------------------------------------------
1 | mov $r2 0x1;
2 | muls $r2 0x2
3 | xor $r3 $r2 0x40;
4 | bra z 0xe;
5 | bra 0x2;
6 | bra 0xe;


--------------------------------------------------------------------------------
/gradle/wrapper/gradle-wrapper.jar:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/marysaka/ghidra_falcon/HEAD/gradle/wrapper/gradle-wrapper.jar


--------------------------------------------------------------------------------
/extension.properties:
--------------------------------------------------------------------------------
1 | name=@extname@
2 | description=Nvidia Falcon ISA extension.
3 | author=marysaka, hthh
4 | createdOn=
5 | version=@extversion@
6 | 


--------------------------------------------------------------------------------
/data/languages/falcon_v4.slaspec:
--------------------------------------------------------------------------------
1 | @define FUC_VERSION "4"
2 | 
3 | @define SUPPORT_FUC3P
4 | @define SUPPORT_FUC4P
5 | @define SUPPORT_FUCOLD
6 | 
7 | @include "base_falcon.slaspec"
8 | 


--------------------------------------------------------------------------------
/data/languages/falcon_v5.slaspec:
--------------------------------------------------------------------------------
 1 | @define FUC_VERSION "5"
 2 | 
 3 | @define SUPPORT_FUC3P
 4 | @define SUPPORT_FUC4P
 5 | @define SUPPORT_FUC5P
 6 | 
 7 | @define CRYPT_EXTENSION
 8 | 
 9 | @include "base_falcon.slaspec"
10 | 


--------------------------------------------------------------------------------
/gradle/wrapper/gradle-wrapper.properties:
--------------------------------------------------------------------------------
1 | distributionBase=GRADLE_USER_HOME
2 | distributionPath=wrapper/dists
3 | distributionUrl=https\://services.gradle.org/distributions/gradle-7.3.3-bin.zip
4 | zipStoreBase=GRADLE_USER_HOME
5 | zipStorePath=wrapper/dists
6 | 


--------------------------------------------------------------------------------
/data/testing/Makefile:
--------------------------------------------------------------------------------
 1 | NAME := faucon
 2 | 
 3 | all: $(NAME)_fw.h
 4 | 
 5 | $(NAME)_fw.bin: $(NAME).asm
 6 | 	envyas -m falcon -V fuc5 -F crypt $? -i -o $@
 7 | 
 8 | $(NAME)_fw.h: $(NAME)_fw.bin
 9 | 	bin2c -o $@ $?
10 | 
11 | print_dis: $(NAME)_fw.bin
12 | 	envydis -i $? -m falcon -V fuc5 -F crypt -n
13 | 
14 | clean:
15 | 	rm -f $(NAME)_fw.h $(NAME)_fw.bin


--------------------------------------------------------------------------------
/data/languages/falcon.pspec:
--------------------------------------------------------------------------------
 1 | <?xml version="1.0" encoding="UTF-8"?>
 2 | 
 3 | <!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/processor_spec.rxg -->
 4 | 
 5 | <processor_spec>
 6 |   <programcounter register="pc"/>
 7 | 
 8 |   <data_space space="dmem"/>
 9 | 
10 |   <volatile outputop="reg_write" inputop="reg_read">
11 |     <range space="register" first="0x58" last="0x5f"/> <!-- imb dmb -->
12 |     <range space="register" first="0x64" last="0xff"/>
13 |   </volatile>
14 | </processor_spec>
15 | 


--------------------------------------------------------------------------------
/LICENSE.txt:
--------------------------------------------------------------------------------
1 | Copyright 2019 marysaka, hthh
2 | 
3 | Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
4 | 
5 | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
6 | 


--------------------------------------------------------------------------------
/data/testing/faucon.asm:
--------------------------------------------------------------------------------
 1 | mov $r13 0x1000;
 2 | mov $sp $r13;
 3 | mov $r13 0xf;
 4 | mov $r13 0xff;
 5 | mov $r13 0xffff;
 6 | mov $r13 0xffffffff;
 7 | 
 8 | mulu $r1 $r13 0x10;
 9 | muls $r1 $r13 0x10;
10 | sext $r1 $r13 0x10;
11 | and $r1 $r13 0x10;
12 | or $r1 $r13 0x10;
13 | xor $r1 $r13 0x10;
14 | xbit $r1 $r13 0x10;
15 | // TODO: ce
16 | iord $r13 I[$r13 + 0x4];
17 | 
18 | mulu $r1 $r13 0x1010;
19 | muls $r1 $r13 0x1010;
20 | and $r1 $r13 0x1010;
21 | or $r1 $r13 0x1010;
22 | xor $r1 $r13 0x1010;
23 | 
24 | mulu $r1 0x10;
25 | muls $r1 0x10;
26 | sext $r1 0x10;
27 | // TODO: sethi
28 | and $r1 0x10;
29 | or $r9 0x10;
30 | xor $r9 0x10;
31 | bset $r9 0x10;
32 | bclr $r9 0x10;
33 | btgl $r9 0x10;
34 | 
35 | mulu $r1 0x1010;
36 | muls $r1 0x1010;
37 | // TODO: sethi
38 | and $r1 0x1010;
39 | or $r9 0x1010;
40 | xor $r9 0x1010;
41 | call 0x77
42 | bra 0x6;
43 | ret;
44 | mov $r10 0x42
45 | ret;


--------------------------------------------------------------------------------
/data/languages/sized.sinc:
--------------------------------------------------------------------------------
 1 | 
 2 | with : op_size=2 ... {
 3 | @define SZ_SUFFIX ""_b32""
 4 | @define SZ_BYTES "4"
 5 | @define SZ_BITS "32"
 6 | 
 7 | @include "sized_include.sinc"
 8 | 
 9 | @undef SZ_SUFFIX
10 | @undef SZ_BYTES
11 | @undef SZ_BITS
12 | }
13 | 
14 | 
15 | @define SZ_SUFFIX ""_b16""
16 | @define SZ_BYTES "2"
17 | @define SZ_BITS "16"
18 | with : op_size=1 ... {
19 | 
20 | @include "sized_include.sinc"
21 | 
22 | } # with
23 | @undef SZ_SUFFIX
24 | @undef SZ_BYTES
25 | @undef SZ_BITS
26 | 
27 | 
28 | @define SZ_SUFFIX ""_b8""
29 | @define SZ_BYTES "1"
30 | @define SZ_BITS "8"
31 | with : op_size=0 ... {
32 | 
33 | @include "sized_include.sinc"
34 | 
35 | }
36 | @undef SZ_SUFFIX
37 | @undef SZ_BYTES
38 | @undef SZ_BITS
39 | 
40 | 
41 | 
42 | # Some entries in the table only run once
43 | @define SZ_SUFFIX ""
44 | @define SZ_BYTES ""
45 | @define SZ_BITS ""
46 | @define ONCE
47 | @include "sized_include.sinc"
48 | @undef ONCE
49 | @undef SZ_SUFFIX
50 | @undef SZ_BYTES
51 | @undef SZ_BITS
52 | 


--------------------------------------------------------------------------------
/data/languages/falcon.cspec:
--------------------------------------------------------------------------------
 1 | <?xml version="1.0" encoding="UTF-8"?>
 2 | 
 3 | <!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/compiler_spec.rxg -->
 4 | 
 5 | <compiler_spec>
 6 |   <data_organization>
 7 |     <absolute_max_alignment value="0" />
 8 |     <machine_alignment value="1" />
 9 |     <default_alignment value="1" />
10 |     <default_pointer_alignment value="4" />
11 |     <pointer_size value="4" />
12 |   </data_organization>
13 | 
14 |   <global>
15 |     <range space="imem"/>
16 |     <range space="dmem"/>
17 |   </global>
18 | 
19 |   <stackpointer register="sp" space="dmem" growth="negative"/>
20 | 
21 |   <returnaddress>
22 |     <varnode space="stack" offset="0" size="4"/>
23 |   </returnaddress>
24 |   <default_proto>
25 |     <!-- FIXME: this needs more research -->
26 |     <prototype name="falcon_prototype" extrapop="4" stackshift="4">
27 |       <input>
28 |         <pentry minsize="1" maxsize="4">
29 |           <register name="r10"/>
30 |         </pentry>
31 |         <pentry minsize="1" maxsize="4">
32 |           <register name="r11"/>
33 |         </pentry>
34 |         <pentry minsize="1" maxsize="4">
35 |           <register name="r12"/>
36 |         </pentry>
37 |         <pentry minsize="1" maxsize="4">
38 |           <register name="r13"/>
39 |         </pentry>
40 |         <pentry minsize="1" maxsize="4">
41 |           <register name="r14"/>
42 |         </pentry>
43 |         <!-- (looks like this is not an argument)
44 |         <pentry minsize="1" maxsize="4">
45 |           <register name="r15"/>
46 |         </pentry>
47 |         -->
48 |         <pentry minsize="1" maxsize="500" align="4">
49 |           <addr offset="4" space="stack"/>
50 |         </pentry>
51 |       </input>
52 |       <output>
53 |         <pentry minsize="1" maxsize="4">
54 |           <register name="r10"/>
55 |         </pentry>
56 |       </output>
57 |       <unaffected>
58 |         <register name="r0"/>
59 |         <register name="r1"/>
60 |         <register name="r2"/>
61 |         <register name="r3"/>
62 |         <register name="r4"/>
63 |         <register name="r5"/>
64 |         <register name="r6"/>
65 |         <register name="r7"/>
66 |         <register name="r8"/>
67 |         <!-- not sure about r9 -->
68 |         <register name="sp"/>
69 |       </unaffected>
70 |       <localrange>
71 |         <range space="stack"/>
72 |       </localrange>
73 |     </prototype>
74 |   </default_proto>
75 | </compiler_spec>
76 | 


--------------------------------------------------------------------------------
/gradlew.bat:
--------------------------------------------------------------------------------
 1 | @if "%DEBUG%" == "" @echo off
 2 | @rem ##########################################################################
 3 | @rem
 4 | @rem  Gradle startup script for Windows
 5 | @rem
 6 | @rem ##########################################################################
 7 | 
 8 | @rem Set local scope for the variables with windows NT shell
 9 | if "%OS%"=="Windows_NT" setlocal
10 | 
11 | set DIRNAME=%~dp0
12 | if "%DIRNAME%" == "" set DIRNAME=.
13 | set APP_BASE_NAME=%~n0
14 | set APP_HOME=%DIRNAME%
15 | 
16 | @rem Add default JVM options here. You can also use JAVA_OPTS and GRADLE_OPTS to pass JVM options to this script.
17 | set DEFAULT_JVM_OPTS="-Xmx64m"
18 | 
19 | @rem Find java.exe
20 | if defined JAVA_HOME goto findJavaFromJavaHome
21 | 
22 | set JAVA_EXE=java.exe
23 | %JAVA_EXE% -version >NUL 2>&1
24 | if "%ERRORLEVEL%" == "0" goto init
25 | 
26 | echo.
27 | echo ERROR: JAVA_HOME is not set and no 'java' command could be found in your PATH.
28 | echo.
29 | echo Please set the JAVA_HOME variable in your environment to match the
30 | echo location of your Java installation.
31 | 
32 | goto fail
33 | 
34 | :findJavaFromJavaHome
35 | set JAVA_HOME=%JAVA_HOME:"=%
36 | set JAVA_EXE=%JAVA_HOME%/bin/java.exe
37 | 
38 | if exist "%JAVA_EXE%" goto init
39 | 
40 | echo.
41 | echo ERROR: JAVA_HOME is set to an invalid directory: %JAVA_HOME%
42 | echo.
43 | echo Please set the JAVA_HOME variable in your environment to match the
44 | echo location of your Java installation.
45 | 
46 | goto fail
47 | 
48 | :init
49 | @rem Get command-line arguments, handling Windows variants
50 | 
51 | if not "%OS%" == "Windows_NT" goto win9xME_args
52 | 
53 | :win9xME_args
54 | @rem Slurp the command line arguments.
55 | set CMD_LINE_ARGS=
56 | set _SKIP=2
57 | 
58 | :win9xME_args_slurp
59 | if "x%~1" == "x" goto execute
60 | 
61 | set CMD_LINE_ARGS=%*
62 | 
63 | :execute
64 | @rem Setup the command line
65 | 
66 | set CLASSPATH=%APP_HOME%\gradle\wrapper\gradle-wrapper.jar
67 | 
68 | @rem Execute Gradle
69 | "%JAVA_EXE%" %DEFAULT_JVM_OPTS% %JAVA_OPTS% %GRADLE_OPTS% "-Dorg.gradle.appname=%APP_BASE_NAME%" -classpath "%CLASSPATH%" org.gradle.wrapper.GradleWrapperMain %CMD_LINE_ARGS%
70 | 
71 | :end
72 | @rem End local scope for the variables with windows NT shell
73 | if "%ERRORLEVEL%"=="0" goto mainEnd
74 | 
75 | :fail
76 | rem Set variable GRADLE_EXIT_CONSOLE if you need the _script_ return code instead of
77 | rem the _cmd.exe /c_ return code!
78 | if  not "" == "%GRADLE_EXIT_CONSOLE%" exit 1
79 | exit /b 1
80 | 
81 | :mainEnd
82 | if "%OS%"=="Windows_NT" endlocal
83 | 
84 | :omega
85 | 


--------------------------------------------------------------------------------
/.github/workflows/build.yml:
--------------------------------------------------------------------------------
 1 | name: CI
 2 | 
 3 | on: [push, pull_request, workflow_dispatch]
 4 | 
 5 | permissions:
 6 |   contents: write
 7 | 
 8 | jobs:
 9 |   build:
10 |     runs-on: ubuntu-latest
11 |     strategy:
12 |       matrix:
13 |         ghidra:
14 |           - "11.1.2"
15 |           - "11.1.1"
16 |           - "11.1"
17 |           - "11.0.3"
18 |           - "11.0.2"
19 |           - "11.0.1"
20 |           - "11.0"
21 |           - "10.4"
22 |           - "10.3.3"
23 |           - "10.3.2"
24 |           - "10.3.1"
25 |           - "10.3"
26 |     steps:
27 |       - uses: actions/checkout@v4
28 | 
29 |       - uses: actions/setup-java@v4
30 |         with:
31 |           distribution: 'temurin'
32 |           java-version: '17'
33 | 
34 |       - uses: gradle/actions/setup-gradle@v3
35 | 
36 |       - uses: antoniovazquezblanco/setup-ghidra@v2.0.5
37 |         with:
38 |           auth_token: ${{ secrets.GITHUB_TOKEN }}
39 |           version: ${{ matrix.ghidra }}
40 | 
41 |       - name: Build extension
42 |         run: ./gradlew -PGHIDRA_INSTALL_DIR=${{ env.GHIDRA_INSTALL_DIR }}
43 | 
44 |       - name: Upload Build Artifact
45 |         uses: actions/upload-artifact@v4
46 |         with:
47 |           name: Falcon for Ghidra ${{ matrix.ghidra }}
48 |           path: dist/ghidra_*.zip
49 |           if-no-files-found: error
50 | 
51 |   release:
52 |     runs-on: "ubuntu-latest"
53 |     needs: build
54 | 
55 |     steps:
56 |     - name: Get current date
57 |       id: date
58 |       run: echo "::set-output name=date::$(date +'%Y-%m-%d')"
59 | 
60 |     - name: Checkout source for nightly release removal
61 |       uses: actions/checkout@v4
62 |       if: github.ref == 'refs/heads/master'
63 | 
64 |     - name: Remove previous nightly release
65 |       if: github.ref == 'refs/heads/master'
66 |       run: |
67 |         git fetch --tags
68 |         gh release delete latest -y || true
69 |         git push --delete origin latest || true
70 | 
71 |     - name: Download binaries
72 |       uses: actions/download-artifact@v4
73 | 
74 |     - name: Release nightly
75 |       if: github.ref == 'refs/heads/master'
76 |       uses: softprops/action-gh-release@v2
77 |       with:
78 |         tag_name: "latest"
79 |         prerelease: true
80 |         name: "Ghidra Falcon Nightly (${{steps.date.outputs.date}})"
81 |         files: Falcon*/*.zip
82 |         fail_on_unmatched_files: true
83 | 
84 |     - name: Release stable
85 |       if: contains(github.ref, 'refs/tags/v')
86 |       uses: softprops/action-gh-release@v2
87 |       with:
88 |         prerelease: false
89 |         name: "Ghidra Falcon ${{github.ref_name}}"
90 |         files: Falcon*/*.zip
91 |         fail_on_unmatched_files: true
92 | 


--------------------------------------------------------------------------------
/data/languages/falcon.ldefs:
--------------------------------------------------------------------------------
 1 | <?xml version="1.0" encoding="UTF-8"?>
 2 | 
 3 | <!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/language_definitions.rxg -->
 4 | 
 5 | <language_definitions>
 6 |   <!-->
 7 |    <language processor="Falcon"
 8 |             endian="little"
 9 |             size="32"
10 |             variant="v0"
11 |             version="1.0"
12 |             slafile="falcon.sla"
13 |             processorspec="falcon_v0.pspec"
14 |             id="falcon:LE:32:v0">
15 |     <description>Nvidia Falcon v0</description>
16 |     <compiler name="default" spec="falcon.cspec" id="default"/>
17 |   </language>
18 |    <language processor="Falcon"
19 |             endian="little"
20 |             size="32"
21 |             variant="v1"
22 |             version="1.0"
23 |             slafile="falcon.sla"
24 |             processorspec="falcon_v1.pspec"
25 |             id="falcon:LE:32:v1">
26 |     <description>Nvidia Falcon v1</description>
27 |     <compiler name="default" spec="falcon.cspec" id="default"/>
28 |   </language>
29 |    <language processor="Falcon"
30 |             endian="little"
31 |             size="32"
32 |             variant="v2"
33 |             version="1.0"
34 |             slafile="falcon.sla"
35 |             processorspec="falcon_v2.pspec"
36 |             id="falcon:LE:32:v2">
37 |     <description>Nvidia Falcon v2</description>
38 |     <compiler name="default" spec="falcon.cspec" id="default"/>
39 |   </language>
40 |    <language processor="Falcon"
41 |             endian="little"
42 |             size="32"
43 |             variant="v3"
44 |             version="1.0"
45 |             slafile="falcon.sla"
46 |             processorspec="falcon_v3.pspec"
47 |             id="falcon:LE:32:v3">
48 |     <description>Nvidia Falcon v3</description>
49 |     <compiler name="default" spec="falcon.cspec" id="default"/>
50 |   </language>
51 |   <!-->
52 |    <language processor="Falcon"
53 |             endian="little"
54 |             size="32"
55 |             variant="v4"
56 |             version="1.0"
57 |             slafile="falcon_v4.sla"
58 |             processorspec="falcon.pspec"
59 |             id="falcon:LE:32:v4">
60 |     <description>Nvidia Falcon v4</description>
61 |     <compiler name="default" spec="falcon.cspec" id="default"/>
62 |   </language>
63 |    <language processor="Falcon"
64 |             endian="little"
65 |             size="32"
66 |             variant="v5"
67 |             version="1.0"
68 |             slafile="falcon_v5.sla"
69 |             processorspec="falcon.pspec"
70 |             id="falcon:LE:32:v5">
71 |     <description>Nvidia Falcon v5</description>
72 |     <compiler name="default" spec="falcon.cspec" id="default"/>
73 |   </language>
74 | </language_definitions>
75 | 


--------------------------------------------------------------------------------
/data/build.xml:
--------------------------------------------------------------------------------
 1 | <?xml version="1.0" encoding="UTF-8"?>
 2 | 
 3 | <!--
 4 |   + Compile sleigh languages within this module.
 5 |   + Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
 6 |   + From command line (requires ant install)
 7 |   +    - cd to data directory containing this file
 8 |   +    - run ant
 9 |   -->
10 |                                      
11 | <project name="privateBuildDeveloper" default="sleighCompile">
12 | 	
13 | 	<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>
14 | 
15 | 	<property name="repo.dir" value="../../../.." />
16 | 	<property name="repo.marker.dir" value="${repo.dir}/.git" />
17 | 	
18 | 	<!--Import optional ant properties.  GhidraDev Eclipse plugin produces this so this file can find the Ghidra installation-->
19 | 	<import file="../.antProperties.xml" optional="true" />
20 | 	
21 | 	<condition property="devmode">
22 | 		<available file="${repo.marker.dir}" type="dir" />
23 | 	</condition>
24 | 
25 | 	<target name="buildSleighClasspathDev" if="devmode">
26 | 		
27 | 		<property name="framework.path" value="${repo.dir}/../ghidra.git/Ghidra/Framework"/>
28 | 		<property name="libs.path" value="${repo.dir}/../ghidra.bin.git/ExternalLibraries/libsForRuntime"/>
29 | 		
30 | 		<path id="sleigh.class.path">
31 | 			<pathelement location="${framework.path}/SoftwareModeling/bin"/>
32 | 			<pathelement location="${framework.path}/Generic/bin"/>
33 | 			<pathelement location="${framework.path}/Utility/bin"/>
34 | 			<fileset dir="${libs.path}">
35 | 				<include name="*.jar"/>
36 | 			</fileset>
37 | 		</path>
38 | 			
39 | 		<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
40 | 			
41 | 	</target>
42 | 	
43 | 	<target name="buildSleighClasspathDist" unless="devmode">
44 | 
45 | 		<!-- If language module is detached from installation, get Ghidra installation directory path from imported properties -->
46 | 		<condition property="framework.path" value="${ghidra.install.dir}/Ghidra/Framework" else="../../../Framework">
47 | 			<available file="${ghidra.install.dir}" type="dir" />
48 | 		</condition>
49 | 		
50 | 		<path id="sleigh.class.path">
51 | 			<fileset dir="${framework.path}/SoftwareModeling/lib">
52 | 				<include name="*.jar"/>
53 | 			</fileset>
54 | 			<fileset dir="${framework.path}/Generic/lib">
55 | 				<include name="*.jar"/>
56 | 			</fileset>
57 | 			<fileset dir="${framework.path}/Utility/lib">
58 | 				<include name="*.jar"/>
59 | 			</fileset>
60 | 		</path>
61 | 		<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
62 | 			
63 | 	</target>	
64 | 		
65 | 	<target name="sleighCompile" depends="buildSleighClasspathDist, buildSleighClasspathDev">
66 | 	    
67 | 		<fail unless="sleigh.compile.exists" />
68 | 		
69 | 		<java classname="${sleigh.compile.class}"
70 | 			classpathref="sleigh.class.path"
71 | 			fork="true"
72 | 			failonerror="true">
73 | 			<jvmarg value="-Xmx2048M"/>
74 | 			<arg value="-a"/>
75 | 			<arg value="./languages"/>
76 | 		</java>
77 | 		
78 |  	</target>
79 | 
80 | </project>
81 | 


--------------------------------------------------------------------------------
/.gitignore:
--------------------------------------------------------------------------------
  1 | ### Eclipse ###
  2 | 
  3 | .metadata
  4 | bin/
  5 | tmp/
  6 | *.tmp
  7 | *.bak
  8 | *.swp
  9 | *~.nib
 10 | local.properties
 11 | .settings/
 12 | .loadpath
 13 | .recommenders
 14 | 
 15 | # External tool builders
 16 | .externalToolBuilders/
 17 | 
 18 | # Locally stored "Eclipse launch configurations"
 19 | *.launch
 20 | 
 21 | # PyDev specific (Python IDE for Eclipse)
 22 | *.pydevproject
 23 | 
 24 | # CDT-specific (C/C++ Development Tooling)
 25 | .cproject
 26 | 
 27 | # CDT- autotools
 28 | .autotools
 29 | 
 30 | # Java annotation processor (APT)
 31 | .factorypath
 32 | 
 33 | # PDT-specific (PHP Development Tools)
 34 | .buildpath
 35 | 
 36 | # sbteclipse plugin
 37 | .target
 38 | 
 39 | # Tern plugin
 40 | .tern-project
 41 | 
 42 | # TeXlipse plugin
 43 | .texlipse
 44 | 
 45 | # STS (Spring Tool Suite)
 46 | .springBeans
 47 | 
 48 | # Code Recommenders
 49 | .recommenders/
 50 | 
 51 | # Annotation Processing
 52 | .apt_generated/
 53 | 
 54 | # Scala IDE specific (Scala & Java development for Eclipse)
 55 | .cache-main
 56 | .scala_dependencies
 57 | .worksheet
 58 | 
 59 | ### Eclipse Patch ###
 60 | # Eclipse Core
 61 | .project
 62 | 
 63 | # JDT-specific (Eclipse Java Development Tools)
 64 | .classpath
 65 | 
 66 | # Annotation Processing
 67 | .apt_generated
 68 | 
 69 | .sts4-cache/
 70 | 
 71 | ### Java ###
 72 | # Compiled class file
 73 | *.class
 74 | 
 75 | # Log file
 76 | *.log
 77 | 
 78 | # BlueJ files
 79 | *.ctxt
 80 | 
 81 | # Mobile Tools for Java (J2ME)
 82 | .mtj.tmp/
 83 | 
 84 | # Package Files #
 85 | *.jar
 86 | *.war
 87 | *.nar
 88 | *.ear
 89 | *.zip
 90 | *.tar.gz
 91 | *.rar
 92 | 
 93 | # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
 94 | hs_err_pid*
 95 | 
 96 | ### Linux ###
 97 | *~
 98 | 
 99 | # temporary files which can be created if a process still has a handle open of a deleted file
100 | .fuse_hidden*
101 | 
102 | # KDE directory preferences
103 | .directory
104 | 
105 | # Linux trash folder which might appear on any partition or disk
106 | .Trash-*
107 | 
108 | # .nfs files are created when an open file is removed but is still being accessed
109 | .nfs*
110 | 
111 | ### OSX ###
112 | # General
113 | .DS_Store
114 | .AppleDouble
115 | .LSOverride
116 | 
117 | # Icon must end with two \r
118 | Icon
119 | 
120 | # Thumbnails
121 | ._*
122 | 
123 | # Files that might appear in the root of a volume
124 | .DocumentRevisions-V100
125 | .fseventsd
126 | .Spotlight-V100
127 | .TemporaryItems
128 | .Trashes
129 | .VolumeIcon.icns
130 | .com.apple.timemachine.donotpresent
131 | 
132 | # Directories potentially created on remote AFP share
133 | .AppleDB
134 | .AppleDesktop
135 | Network Trash Folder
136 | Temporary Items
137 | .apdisk
138 | 
139 | ### Windows ###
140 | # Windows thumbnail cache files
141 | Thumbs.db
142 | ehthumbs.db
143 | ehthumbs_vista.db
144 | 
145 | # Dump file
146 | *.stackdump
147 | 
148 | # Folder config file
149 | [Dd]esktop.ini
150 | 
151 | # Recycle Bin used on file shares
152 | $RECYCLE.BIN/
153 | 
154 | # Windows Installer files
155 | *.cab
156 | *.msi
157 | *.msix
158 | *.msm
159 | *.msp
160 | 
161 | # Windows shortcuts
162 | *.lnk
163 | 
164 | ### Gradle ###
165 | .gradle
166 | build/
167 | 
168 | # Ignore Gradle GUI config
169 | gradle-app.setting
170 | 
171 | # Avoid ignoring Gradle wrapper jar file (.jar files are usually ignored)
172 | !gradle-wrapper.jar
173 | 
174 | # Cache of project
175 | .gradletasknamecache
176 | 
177 | # # Work around https://youtrack.jetbrains.com/issue/IDEA-116898
178 | # gradle/wrapper/gradle-wrapper.properties
179 | 
180 | ### Gradle Patch ###
181 | **/build/
182 | 
183 | # Ghidra stuffs
184 | .antProperties.xml
185 | *.sla
186 | 
187 | data/testing/*_fw.bin
188 | data/testing/*_fw.h


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/data/languages/macro.sinc:
--------------------------------------------------------------------------------
  1 | macro todo_binop(dst, src1, src2) {
  2 |   dst = todo(src1, src2);
  3 | }
  4 | 
  5 | macro store32(addr, value) {
  6 |   *[dmem]:4 (addr) = value;
  7 | }
  8 | macro store16(addr, value) {
  9 |   *[dmem]:2 (addr) = value;
 10 | }
 11 | macro store8(addr, value) {
 12 |   *[dmem]:1 (addr) = value;
 13 | }
 14 | macro load32(dst1, addr) {
 15 |   dst1 = *[dmem]:4 (addr);
 16 | }
 17 | macro load16(dst1, addr) {
 18 |   dst1 = *[dmem]:2 (addr);
 19 | }
 20 | macro load8(dst1, addr) {
 21 |   dst1 = *[dmem]:1 (addr);
 22 | }
 23 | 
 24 | macro xbit(dst1, src1, bit1) {
 25 |   dst1 = (src1 >> bit1) & 1;
 26 | }
 27 | 
 28 | macro op_sext(dst, src1, src2) {
 29 |   local shift_distance = (31 - (src2 & 0x1F));
 30 |   dst = (src1 << shift_distance) s>> shift_distance;
 31 | }
 32 | 
 33 | macro bclr(reg1, bit1) {
 34 |   reg1 = reg1 & ~(1 << bit1);
 35 | }
 36 | 
 37 | macro bset(reg1, bit1) {
 38 |   reg1 = reg1 | (1 << bit1);
 39 | }
 40 | 
 41 | macro btgl(reg1, bit1) {
 42 |   reg1 = reg1 ^ (1 << bit1);
 43 | }
 44 | 
 45 | macro push32(val32) {
 46 |   sp = sp - 4;
 47 |   *[dmem]:4 sp = val32;
 48 | }
 49 | 
 50 | macro pop32(ret32) {
 51 |   sp = sp + 4;
 52 |   ret32 = *[dmem]:4 sp;
 53 | }
 54 | 
 55 | macro ret() {
 56 |   pop32(pc);
 57 |   return [pc];
 58 | }
 59 | 
 60 | macro setResultFlags(result) {
 61 |   $(Z_flag) = (result == 0);
 62 |   $(S_flag) = (result s< 0);
 63 | }
 64 | 
 65 | macro clear(dst) {
 66 |   dst = 0;
 67 | }
 68 | 
 69 | macro mov(dst, src) {
 70 |   dst = src;
 71 | }
 72 | 
 73 | macro and(dst, src1, src2) {
 74 |   dst = src1 & src2;
 75 | 
 76 |   $(C_flag) = 0;
 77 |   $(O_flag) = 0;
 78 |   setResultFlags(dst);
 79 | }
 80 | 
 81 | macro or(dst, src1, src2) {
 82 |   dst = src1 | src2;
 83 | 
 84 |   $(C_flag) = 0;
 85 |   $(O_flag) = 0;
 86 |   setResultFlags(dst);
 87 | }
 88 | 
 89 | macro xor(dst, src1, src2) {
 90 |   dst = src1 ^ src2;
 91 | 
 92 |   $(C_flag) = 0;
 93 |   $(O_flag) = 0;
 94 |   setResultFlags(dst);
 95 | }
 96 | 
 97 | macro shl32(dst, src1, src2) {
 98 |   dst = src1 << (src2 & 0x1F);
 99 | 
100 |   $(O_flag) = 0;
101 |   setResultFlags(dst);
102 | }
103 | 
104 | macro shr32(dst, src1, src2) {
105 |   dst = src1 >> (src2 & 0x1F);
106 | 
107 |   $(O_flag) = 0;
108 |   setResultFlags(dst);
109 | }
110 | 
111 | macro sar32(dst, src1, src2) {
112 |   dst = src1 s>> (src2 & 0x1F);
113 | 
114 |   $(O_flag) = 0;
115 |   setResultFlags(dst);
116 | }
117 | 
118 | macro add(dst, src1, src2) {
119 |   $(C_flag) = carry(src1,src2);
120 |   $(O_flag) = scarry(src1,src2);
121 |   dst = src1 + src2;
122 |   setResultFlags(dst);
123 | }
124 | 
125 | 
126 | macro adc(dst, src1, src2) {
127 |   # TODO: this assumes these flags match x86
128 |   local cf_copy = zext($(C_flag));
129 |   $(C_flag) = carry(src1, src2);
130 |   $(O_flag) = scarry(src1, src2);
131 |   local result = src1 + src2;
132 |   $(C_flag) = $(C_flag) || carry(result, cf_copy);
133 |   $(O_flag) = $(O_flag) ^^ scarry(result, cf_copy);
134 |   dst = result + cf_copy;
135 |   setResultFlags(dst);
136 | }
137 | 
138 | 
139 | macro sub(dst, src1, src2) {
140 |   $(C_flag) = src1 < src2;
141 |   $(O_flag) = sborrow(src1,src2);
142 |   dst = src1 - src2;
143 |   setResultFlags(dst);
144 | }
145 | 
146 | macro cmp(src1, src2) {
147 |   # TODO: check flag correctness
148 |   setResultFlags((src1 - src2));
149 |   $(C_flag) = src1 < src2;
150 |   $(O_flag) = sborrow(src1, src2);
151 | }
152 | 
153 | macro cmpu(src1, src2) {
154 |   # TODO: is this right?
155 |   $(C_flag) = (src1 < src2);
156 |   $(Z_flag) = (src1 == src2);
157 | }
158 | 
159 | macro cmps(src1, src2) {
160 |   $(C_flag) = (src1 s< src2);
161 |   $(Z_flag) = (src1 == src2);
162 | }
163 | 
164 | 
165 | # TODO: check if that set flags on hardware
166 | macro mulu(dst, src1, src2) {
167 |   dst = zext(src1) * zext(src2);
168 | }
169 | 
170 | macro hswap16(dst, src) {
171 |   dst = ((src & 0xFF) << 8) | ((src & 0xFF00) >> 8);
172 |   setResultFlags(dst);
173 |   $(O_flag) = 0;
174 | }
175 | 
176 | macro hswap8(dst, src) {
177 |   # TODO: is this even a thing?
178 |   dst = ((src & 0xF) << 4) | ((src & 0xF0) >> 4);
179 |   setResultFlags(dst);
180 |   $(O_flag) = 0;
181 | }
182 | 
183 | macro not(dst, src) {
184 |   dst = ~src;
185 |   setResultFlags(dst);
186 |   $(O_flag) = 0;
187 | }
188 | 
189 | macro neg(dst, src) {
190 |   dst = -src;
191 |   setResultFlags(dst);
192 |   $(O_flag) = sborrow(0, dst);
193 | }
194 | 
195 | 
196 | 


--------------------------------------------------------------------------------
/data/languages/unsized_inst.sinc:
--------------------------------------------------------------------------------
 1 | define pcodeop exit;
 2 | define pcodeop io_read;
 3 | define pcodeop io_write;
 4 | define pcodeop io_write_sync;
 5 | 
 6 | define pcodeop unkce_io_read;
 7 | 
 8 | define pcodeop vtlb;
 9 | define pcodeop ptlb;
10 | 
11 | define pcodeop cxset;
12 | 
13 | define pcodeop xdst;
14 | define pcodeop xdld;
15 | define pcodeop xcld;
16 | define pcodeop xcwait;
17 | define pcodeop xdwait;
18 | 
19 | 
20 | define pcodeop __clear_flag_ie0;
21 | define pcodeop __clear_flag_ie1;
22 | define pcodeop __clear_flag_ie2;
23 | define pcodeop __clear_flag_is0;
24 | define pcodeop __clear_flag_is1;
25 | define pcodeop __clear_flag_ta;
26 | 
27 | define pcodeop __set_flag_ie0;
28 | define pcodeop __set_flag_ie1;
29 | define pcodeop __set_flag_is0;
30 | define pcodeop __set_flag_is1;
31 | define pcodeop __set_flag_ta;
32 | 
33 | define pcodeop __toggle_flag_ie0;
34 | define pcodeop __toggle_flag_ie1;
35 | define pcodeop __toggle_flag_is0;
36 | define pcodeop __toggle_flag_is1;
37 | define pcodeop __toggle_flag_ta;
38 | 
39 | 
40 | 
41 | 
42 | # TODO: check if that set flags on hardware
43 | macro muls(dst, src1, src2) {
44 |   dst = sext(src1) * sext(src2);
45 | }
46 | 
47 | ### Branch instructions start ###
48 | 
49 | ### Start bra conditional ###
50 | bra_cc: "p0"             is subopcodeL=0x00                              { c:1 = $(P0_flag); export c; }
51 | bra_cc: "p1"             is subopcodeL=0x01                              { c:1 = $(P1_flag); export c; }
52 | bra_cc: "p2"             is subopcodeL=0x02                              { c:1 = $(P2_flag); export c; }
53 | bra_cc: "p3"             is subopcodeL=0x03                              { c:1 = $(P3_flag); export c; }
54 | bra_cc: "p4"             is subopcodeL=0x04                              { c:1 = $(P4_flag); export c; }
55 | bra_cc: "p5"             is subopcodeL=0x05                              { c:1 = $(P5_flag); export c; }
56 | bra_cc: "p6"             is subopcodeL=0x06                              { c:1 = $(P6_flag); export c; }
57 | bra_cc: "p7"             is subopcodeL=0x07                              { c:1 = $(P7_flag); export c; }
58 | bra_cc: "c"              is subopcodeL=0x08                              { c:1 = $(C_flag); export c; }
59 | bra_cc: "o"              is subopcodeL=0x09                              { c:1 = $(O_flag); export c; }
60 | bra_cc: "s"              is subopcodeL=0x0a                              { c:1 = $(S_flag); export c; }
61 | bra_cc: "z"              is subopcodeL=0x0b                              { c:1 = $(Z_flag); export c; }
62 | 
63 | bra_cc: "a"              is subopcodeL=0x0c                              { c:1 = !($(C_flag) || $(Z_flag)); export c; }
64 | bra_cc: "na"             is subopcodeL=0x0d                              { c:1 = $(C_flag) || $(Z_flag); export c; }
65 | bra_cc:                  is subopcodeL=0x0e                              { c:1 = 1; export c; }
66 | bra_cc: "not p0"         is subopcodeL=0x10                              { c:1 = !$(P0_flag); export c; }
67 | bra_cc: "not p1"         is subopcodeL=0x11                              { c:1 = !$(P1_flag); export c; }
68 | bra_cc: "not p2"         is subopcodeL=0x12                              { c:1 = !$(P2_flag); export c; }
69 | bra_cc: "not p3"         is subopcodeL=0x13                              { c:1 = !$(P3_flag); export c; }
70 | bra_cc: "not p4"         is subopcodeL=0x14                              { c:1 = !$(P4_flag); export c; }
71 | bra_cc: "not p5"         is subopcodeL=0x15                              { c:1 = !$(P5_flag); export c; }
72 | bra_cc: "not p6"         is subopcodeL=0x16                              { c:1 = !$(P6_flag); export c; }
73 | bra_cc: "not p7"         is subopcodeL=0x17                              { c:1 = !$(P7_flag); export c; }
74 | bra_cc: "nc"             is subopcodeL=0x18                              { c:1 = !$(C_flag); export c; }
75 | bra_cc: "no"             is subopcodeL=0x19                              { c:1 = !$(O_flag); export c; }
76 | bra_cc: "ns"             is subopcodeL=0x1a                              { c:1 = !$(S_flag); export c; }
77 | bra_cc: "nz"             is subopcodeL=0x1b                              { c:1 = !$(Z_flag); export c; }
78 | bra_cc: "g"              is subopcodeL=0x1c                              { c:1 = !$(Z_flag) && ($(O_flag) == $(S_flag)); export c; }
79 | 
80 | @if defined(SUPPORT_FUC3P)
81 | bra_cc: "le"             is subopcodeL=0x1d                              { c:1 = $(Z_flag) || ($(O_flag) != $(S_flag)); export c; }
82 | bra_cc: "l"              is subopcodeL=0x1e                              { c:1 = ($(O_flag) != $(S_flag)); export c; }
83 | bra_cc: "ge"             is subopcodeL=0x1f                              { c:1 = $(O_flag) == $(S_flag); export c; }
84 | @endif
85 | 
86 | ### End bra conditional ###
87 | 
88 | :bra bra_cc rel8 is raw_opcode=0xf4; subopcodeL < 0x20 & bra_cc; rel8 {
89 |   if (bra_cc) goto rel8;
90 | }
91 | 
92 | :bra bra_cc rel16 is raw_opcode=0xf5; subopcodeL < 0x20 & bra_cc; rel16 {
93 |   if (bra_cc) goto rel16;
94 | }
95 | 
96 | 
97 | ### Branch instructions end ###
98 | 
99 | 


--------------------------------------------------------------------------------
/gradlew:
--------------------------------------------------------------------------------
  1 | #!/usr/bin/env sh
  2 | 
  3 | ##############################################################################
  4 | ##
  5 | ##  Gradle start up script for UN*X
  6 | ##
  7 | ##############################################################################
  8 | 
  9 | # Attempt to set APP_HOME
 10 | # Resolve links: $0 may be a link
 11 | PRG="$0"
 12 | # Need this for relative symlinks.
 13 | while [ -h "$PRG" ] ; do
 14 |     ls=`ls -ld "$PRG"`
 15 |     link=`expr "$ls" : '.*-> \(.*\)$'`
 16 |     if expr "$link" : '/.*' > /dev/null; then
 17 |         PRG="$link"
 18 |     else
 19 |         PRG=`dirname "$PRG"`"/$link"
 20 |     fi
 21 | done
 22 | SAVED="`pwd`"
 23 | cd "`dirname \"$PRG\"`/" >/dev/null
 24 | APP_HOME="`pwd -P`"
 25 | cd "$SAVED" >/dev/null
 26 | 
 27 | APP_NAME="Gradle"
 28 | APP_BASE_NAME=`basename "$0"`
 29 | 
 30 | # Add default JVM options here. You can also use JAVA_OPTS and GRADLE_OPTS to pass JVM options to this script.
 31 | DEFAULT_JVM_OPTS='"-Xmx64m"'
 32 | 
 33 | # Use the maximum available, or set MAX_FD != -1 to use that value.
 34 | MAX_FD="maximum"
 35 | 
 36 | warn () {
 37 |     echo "$*"
 38 | }
 39 | 
 40 | die () {
 41 |     echo
 42 |     echo "$*"
 43 |     echo
 44 |     exit 1
 45 | }
 46 | 
 47 | # OS specific support (must be 'true' or 'false').
 48 | cygwin=false
 49 | msys=false
 50 | darwin=false
 51 | nonstop=false
 52 | case "`uname`" in
 53 |   CYGWIN* )
 54 |     cygwin=true
 55 |     ;;
 56 |   Darwin* )
 57 |     darwin=true
 58 |     ;;
 59 |   MINGW* )
 60 |     msys=true
 61 |     ;;
 62 |   NONSTOP* )
 63 |     nonstop=true
 64 |     ;;
 65 | esac
 66 | 
 67 | CLASSPATH=$APP_HOME/gradle/wrapper/gradle-wrapper.jar
 68 | 
 69 | # Determine the Java command to use to start the JVM.
 70 | if [ -n "$JAVA_HOME" ] ; then
 71 |     if [ -x "$JAVA_HOME/jre/sh/java" ] ; then
 72 |         # IBM's JDK on AIX uses strange locations for the executables
 73 |         JAVACMD="$JAVA_HOME/jre/sh/java"
 74 |     else
 75 |         JAVACMD="$JAVA_HOME/bin/java"
 76 |     fi
 77 |     if [ ! -x "$JAVACMD" ] ; then
 78 |         die "ERROR: JAVA_HOME is set to an invalid directory: $JAVA_HOME
 79 | 
 80 | Please set the JAVA_HOME variable in your environment to match the
 81 | location of your Java installation."
 82 |     fi
 83 | else
 84 |     JAVACMD="java"
 85 |     which java >/dev/null 2>&1 || die "ERROR: JAVA_HOME is not set and no 'java' command could be found in your PATH.
 86 | 
 87 | Please set the JAVA_HOME variable in your environment to match the
 88 | location of your Java installation."
 89 | fi
 90 | 
 91 | # Increase the maximum file descriptors if we can.
 92 | if [ "$cygwin" = "false" -a "$darwin" = "false" -a "$nonstop" = "false" ] ; then
 93 |     MAX_FD_LIMIT=`ulimit -H -n`
 94 |     if [ $? -eq 0 ] ; then
 95 |         if [ "$MAX_FD" = "maximum" -o "$MAX_FD" = "max" ] ; then
 96 |             MAX_FD="$MAX_FD_LIMIT"
 97 |         fi
 98 |         ulimit -n $MAX_FD
 99 |         if [ $? -ne 0 ] ; then
100 |             warn "Could not set maximum file descriptor limit: $MAX_FD"
101 |         fi
102 |     else
103 |         warn "Could not query maximum file descriptor limit: $MAX_FD_LIMIT"
104 |     fi
105 | fi
106 | 
107 | # For Darwin, add options to specify how the application appears in the dock
108 | if $darwin; then
109 |     GRADLE_OPTS="$GRADLE_OPTS \"-Xdock:name=$APP_NAME\" \"-Xdock:icon=$APP_HOME/media/gradle.icns\""
110 | fi
111 | 
112 | # For Cygwin, switch paths to Windows format before running java
113 | if $cygwin ; then
114 |     APP_HOME=`cygpath --path --mixed "$APP_HOME"`
115 |     CLASSPATH=`cygpath --path --mixed "$CLASSPATH"`
116 |     JAVACMD=`cygpath --unix "$JAVACMD"`
117 | 
118 |     # We build the pattern for arguments to be converted via cygpath
119 |     ROOTDIRSRAW=`find -L / -maxdepth 1 -mindepth 1 -type d 2>/dev/null`
120 |     SEP=""
121 |     for dir in $ROOTDIRSRAW ; do
122 |         ROOTDIRS="$ROOTDIRS$SEP$dir"
123 |         SEP="|"
124 |     done
125 |     OURCYGPATTERN="(^($ROOTDIRS))"
126 |     # Add a user-defined pattern to the cygpath arguments
127 |     if [ "$GRADLE_CYGPATTERN" != "" ] ; then
128 |         OURCYGPATTERN="$OURCYGPATTERN|($GRADLE_CYGPATTERN)"
129 |     fi
130 |     # Now convert the arguments - kludge to limit ourselves to /bin/sh
131 |     i=0
132 |     for arg in "$@" ; do
133 |         CHECK=`echo "$arg"|egrep -c "$OURCYGPATTERN" -`
134 |         CHECK2=`echo "$arg"|egrep -c "^-"`                                 ### Determine if an option
135 | 
136 |         if [ $CHECK -ne 0 ] && [ $CHECK2 -eq 0 ] ; then                    ### Added a condition
137 |             eval `echo args$i`=`cygpath --path --ignore --mixed "$arg"`
138 |         else
139 |             eval `echo args$i`="\"$arg\""
140 |         fi
141 |         i=$((i+1))
142 |     done
143 |     case $i in
144 |         (0) set -- ;;
145 |         (1) set -- "$args0" ;;
146 |         (2) set -- "$args0" "$args1" ;;
147 |         (3) set -- "$args0" "$args1" "$args2" ;;
148 |         (4) set -- "$args0" "$args1" "$args2" "$args3" ;;
149 |         (5) set -- "$args0" "$args1" "$args2" "$args3" "$args4" ;;
150 |         (6) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" ;;
151 |         (7) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" ;;
152 |         (8) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" "$args7" ;;
153 |         (9) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" "$args7" "$args8" ;;
154 |     esac
155 | fi
156 | 
157 | # Escape application args
158 | save () {
159 |     for i do printf %s\\n "$i" | sed "s/'/'\\\\''/g;1s/^/'/;\$s/\$/' \\\\/" ; done
160 |     echo " "
161 | }
162 | APP_ARGS=$(save "$@")
163 | 
164 | # Collect all arguments for the java command, following the shell quoting and substitution rules
165 | eval set -- $DEFAULT_JVM_OPTS $JAVA_OPTS $GRADLE_OPTS "\"-Dorg.gradle.appname=$APP_BASE_NAME\"" -classpath "\"$CLASSPATH\"" org.gradle.wrapper.GradleWrapperMain "$APP_ARGS"
166 | 
167 | # by default we should be in the correct project dir, but when run from Finder on Mac, the cwd is wrong
168 | if [ "$(uname)" = "Darwin" ] && [ "$HOME" = "$PWD" ]; then
169 |   cd "$(dirname "$0")"
170 | fi
171 | 
172 | exec "$JAVACMD" "$@"
173 | 


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/src/main/java/zone/mary/ghidra/falcon/NvidiaGRBootloaderLoader.java:
--------------------------------------------------------------------------------
  1 | package zone.mary.ghidra.falcon;
  2 | 
  3 | import java.io.IOException;
  4 | import java.util.*;
  5 | 
  6 | import ghidra.app.util.Option;
  7 | import ghidra.app.util.bin.BinaryReader;
  8 | import ghidra.app.util.bin.ByteProvider;
  9 | import ghidra.app.util.importer.MessageLog;
 10 | import ghidra.app.util.opinion.AbstractProgramLoader;
 11 | import ghidra.app.util.opinion.Loaded;
 12 | import ghidra.app.util.opinion.LoadException;
 13 | import ghidra.app.util.opinion.LoadSpec;
 14 | import ghidra.app.util.opinion.LoaderTier;
 15 | import ghidra.framework.model.DomainFolder;
 16 | import ghidra.framework.model.DomainObject;
 17 | import ghidra.framework.model.Project;
 18 | import ghidra.framework.store.LockException;
 19 | import ghidra.program.flatapi.FlatProgramAPI;
 20 | import ghidra.program.model.address.Address;
 21 | import ghidra.program.model.address.AddressOutOfBoundsException;
 22 | import ghidra.program.model.address.AddressOverflowException;
 23 | import ghidra.program.model.lang.CompilerSpec;
 24 | import ghidra.program.model.lang.CompilerSpecID;
 25 | import ghidra.program.model.lang.Language;
 26 | import ghidra.program.model.lang.LanguageCompilerSpecPair;
 27 | import ghidra.program.model.lang.LanguageID;
 28 | import ghidra.program.model.listing.Program;
 29 | import ghidra.program.model.mem.MemoryBlock;
 30 | import ghidra.util.Msg;
 31 | import ghidra.util.exception.CancelledException;
 32 | import ghidra.util.task.TaskMonitor;
 33 | 
 34 | public class NvidiaGRBootloaderLoader extends AbstractProgramLoader {
 35 | 	private static final LanguageID FALCON4_LANGUAGE_ID = new LanguageID("falcon:LE:32:v4");
 36 | 	private static final LanguageID FALCON5_LANGUAGE_ID = new LanguageID("falcon:LE:32:v5");
 37 | 
 38 | 	@Override
 39 | 	public String getName() {
 40 | 		return "NVIDIA GR BootLoader";
 41 | 	}
 42 | 
 43 | 	@Override
 44 | 	public Collection<LoadSpec> findSupportedLoadSpecs(ByteProvider provider) throws IOException {
 45 | 		List<LoadSpec> loadSpecs = new ArrayList<>();
 46 | 
 47 | 		BinaryReader reader = new BinaryReader(provider, true);
 48 | 
 49 | 		long startOffset = reader.readUnsignedInt(0x0);
 50 | 		long size = reader.readUnsignedInt(0x4);
 51 | 
 52 | 		if (provider.length() - 0x10 < size) {
 53 | 			return loadSpecs;
 54 | 		}
 55 | 
 56 | 		int checksum = 0;
 57 | 
 58 | 		for (int i = 0; i < size / 4; i++) {
 59 | 			checksum = (checksum + reader.readInt(startOffset + 0x10 + i * 4));
 60 | 		}
 61 | 
 62 | 		// TODO: Use the checksum to match against commonly known bootloaders
 63 | 
 64 | 		loadSpecs.add(new LoadSpec(this, 0,
 65 | 				new LanguageCompilerSpecPair(FALCON4_LANGUAGE_ID, new CompilerSpecID("default")), true));
 66 | 		loadSpecs.add(new LoadSpec(this, 0,
 67 | 				new LanguageCompilerSpecPair(FALCON5_LANGUAGE_ID, new CompilerSpecID("default")), true));
 68 | 
 69 | 		return loadSpecs;
 70 | 	}
 71 | 
 72 | 	@Override
 73 | 	public List<Option> getDefaultOptions(ByteProvider provider, LoadSpec loadSpec, DomainObject domainObject,
 74 | 			boolean isLoadIntoProgram) {
 75 | 		List<Option> list = new ArrayList<Option>();
 76 | 
 77 | 		// TODO: Options?
 78 | 
 79 | 		return list;
 80 | 	}
 81 | 
 82 | 	@Override
 83 | 	public String validateOptions(ByteProvider provider, LoadSpec loadSpec, List<Option> options, Program program) {
 84 | 		return null;
 85 | 	}
 86 | 
 87 | 	@Override
 88 | 	public LoaderTier getTier() {
 89 | 		return LoaderTier.SPECIALIZED_TARGET_LOADER;
 90 | 	}
 91 | 
 92 | 	@Override
 93 | 	public int getTierPriority() {
 94 | 		return Integer.MAX_VALUE;
 95 | 	}
 96 | 
 97 | 	@Override
 98 | 	protected List<Loaded<Program>> loadProgram(ByteProvider provider, String programName,
 99 | 			Project project, String projectFolderPath, LoadSpec loadSpec, List<Option> options,
100 | 			MessageLog log, Object consumer, TaskMonitor monitor)
101 | 			throws IOException, LoadException, CancelledException {
102 | 
103 | 		LanguageCompilerSpecPair pair = loadSpec.getLanguageCompilerSpec();
104 | 		Language importerLanguage = getLanguageService().getLanguage(pair.languageID);
105 | 		CompilerSpec importerCompilerSpec = importerLanguage.getCompilerSpecByID(pair.compilerSpecID);
106 | 
107 | 		Address baseAddr = importerLanguage.getAddressFactory().getDefaultAddressSpace().getAddress(0);
108 | 		Program prog = createProgram(provider, programName, baseAddr, getName(), importerLanguage, importerCompilerSpec,
109 | 				consumer);
110 | 		boolean success = false;
111 | 
112 | 		List<Loaded<Program>> loadedList = List.of(new Loaded<>(prog, programName, projectFolderPath));
113 | 
114 | 		try {
115 | 			loadInto(provider, loadSpec, options, log, prog, monitor);
116 | 			success = true;
117 | 
118 | 			return loadedList;
119 | 		} finally {
120 | 			if (!success) {
121 | 				prog.release(consumer);
122 | 			}
123 | 		}
124 | 	}
125 | 
126 | 	@Override
127 | 	protected void loadProgramInto(ByteProvider provider, LoadSpec loadSpec,
128 | 			List<Option> options, MessageLog log, Program program, TaskMonitor monitor) throws IOException, LoadException, CancelledException {
129 | 		BinaryReader reader = new BinaryReader(provider, true);
130 | 
131 | 		FlatProgramAPI api = new FlatProgramAPI(program);
132 | 
133 | 		long startOffset = reader.readUnsignedInt(0x0);
134 | 		long size = reader.readUnsignedInt(0x4);
135 | 		long instructionMemoryOffset = reader.readUnsignedInt(0x8);
136 | 		long entrypointOffset = reader.readUnsignedInt(0xC);
137 | 
138 | 		Address instructionMemoryAddress = api.toAddr(instructionMemoryOffset);
139 | 		Address entrypointAddress = api.toAddr(entrypointOffset);
140 | 
141 | 		try {
142 | 			program.setImageBase(instructionMemoryAddress, true);
143 | 		} catch (AddressOverflowException | LockException | IllegalStateException | AddressOutOfBoundsException e) {
144 | 			throw new LoadException("Failed to set image base");
145 | 		}
146 | 
147 | 		byte[] data = provider.readBytes(startOffset + 0x10, size);
148 | 
149 | 		try {
150 | 			MemoryBlock block = api.createMemoryBlock("bootloader", instructionMemoryAddress, data, false);
151 | 			block.setPermissions(true, false, true);
152 | 		} catch (Exception e) {
153 | 			throw new LoadException("Failed to load image");
154 | 		}
155 | 
156 | 		api.addEntryPoint(entrypointAddress);
157 | 		api.disassemble(entrypointAddress);
158 | 		api.createFunction(entrypointAddress, "_bootloader_entrypoint");
159 | 	}
160 | }
161 | 


--------------------------------------------------------------------------------
/data/languages/base_falcon.slaspec:
--------------------------------------------------------------------------------
  1 | # Base specification for the Nvidia Falcon
  2 | 
  3 | define endian=little;
  4 | define alignment=1;
  5 | 
  6 | define space imem       type=ram_space      size=4 default;
  7 | define space dmem       type=ram_space      size=4;
  8 | define space register   type=register_space size=4;
  9 | 
 10 | # general-purpose registers
 11 | define register offset=0 size=4 [
 12 |   # the full words (32 bits) of the GPRs
 13 |   r0  r1  r2  r3
 14 |   r4  r5  r6  r7
 15 |   r8  r9  r10 r11
 16 |   r12 r13 r14 r15
 17 | ];
 18 | define register offset=0 size=2 [
 19 |   # the lower halfwords (16 bits) of the GPRs
 20 |   r0h  _ r1h  _ r2h  _ r3h  _
 21 |   r4h  _ r5h  _ r6h  _ r7h  _
 22 |   r8h  _ r9h  _ r10h _ r11h _
 23 |   r12h _ r13h _ r14h _ r15h _
 24 | ];
 25 | define register offset=0 size=1 [
 26 |   # the lower bytes (8 bits) of the GPRs
 27 |   r0b  _ _ _ r1b  _ _ _ r2b  _ _ _ r3b  _ _ _
 28 |   r4b  _ _ _ r5b  _ _ _ r6b  _ _ _ r7b  _ _ _
 29 |   r8b  _ _ _ r9b  _ _ _ r10b _ _ _ r11b _ _ _
 30 |   r12b _ _ _ r13b _ _ _ r14b _ _ _ r15b _ _ _
 31 | ];
 32 | 
 33 | # special-purpose registers
 34 | define register offset=0x40 size=4 [
 35 |   iv0  iv1  iv2  ev
 36 |   sp   pc   imb  dmb
 37 |   csw  ccr  sec  ctx
 38 |   exci sec1 imb1 dmb1
 39 | ];
 40 | 
 41 | @if defined(CRYPT_EXTENSION)
 42 | # crypto registers
 43 | define register offset=0x200 size=4 [  # XXX: dirty hack; crypto regs are 133 bits in size
 44 |   c0 c1 c2 c3 c4 c5 c6 c7
 45 | ];
 46 | @endif
 47 | 
 48 | # Flag bits from the CSW register.
 49 | # TODO: Use bitrange when supported.
 50 | #define bitrange p0=csw[0,1]
 51 | #                p1=csw[1,1]
 52 | #                p2=csw[2,1]
 53 | #                p3=csw[3,1]
 54 | #                p4=csw[4,1]
 55 | #                p5=csw[5,1]
 56 | #                p6=csw[6,1]
 57 | #                p7=csw[7,1]
 58 | #                cf=csw[8,1]
 59 | #                of=csw[9,1]
 60 | #                sf=csw[10,1]
 61 | #                zf=csw[11,1]
 62 | #                ie0=csw[16,1]
 63 | #                ie1=csw[17,1]
 64 | #                ie2=csw[18,1]
 65 | #                is0=csw[20,1]
 66 | #                is1=csw[21,1]
 67 | #                is2=csw[22,1]
 68 | #                ea=csw[24,1];
 69 | 
 70 | # unpacked flags
 71 | define register offset=0x100 size=1 [
 72 |   CF # bit 8
 73 |   OF # bit 9
 74 |   SF # bit 10
 75 |   ZF # bit 11
 76 | ];
 77 | 
 78 | # TODO: define flags?
 79 | 
 80 | @define P0_flag "csw[0, 1]"
 81 | @define P1_flag "csw[1, 1]"
 82 | @define P2_flag "csw[2, 1]"
 83 | @define P3_flag "csw[3, 1]"
 84 | @define P4_flag "csw[4, 1]"
 85 | @define P5_flag "csw[5, 1]"
 86 | @define P6_flag "csw[6, 1]"
 87 | @define P7_flag "csw[7, 1]"
 88 | @define C_flag "CF"
 89 | @define O_flag "OF"
 90 | @define S_flag "SF"
 91 | @define Z_flag "ZF"
 92 | 
 93 | macro unpackflags(tmp) {
 94 |   CF = (tmp & 0x100) != 0;
 95 |   OF = (tmp & 0x200) != 0;
 96 |   SF = (tmp & 0x400) != 0;
 97 |   ZF = (tmp & 0x800) != 0;
 98 | }
 99 | 
100 | macro packflags(tmp) {
101 |   tmp = (tmp & 0xFFFFF0FF)
102 |     | (0x100 * zext(CF & 1))
103 |     | (0x200 * zext(OF & 1))
104 |     | (0x400 * zext(SF & 1))
105 |     | (0x800 * zext(ZF & 1));
106 | }
107 | 
108 | 
109 | # 8 bits format & size of opcode
110 | define token opcode_len_format (8)
111 |   # raw opcode for unsized instructions
112 |   raw_opcode=(0, 7)
113 |   raw_opcode_lo=(0, 3)
114 |   raw_opcode_hi=(4, 7)
115 |   op_size=(6, 7)
116 |   op_format=(0, 5)
117 |   o1_format=(0, 3)
118 |   reg0=(0, 3)
119 | ;
120 | 
121 | define token opcode_byte1 (8)
122 |   reg2=(0, 3)
123 |   sreg2=(0, 3)
124 |   reg1=(4, 7)
125 |   sreg1=(4, 7)
126 |   subopcode2=(0, 3)
127 |   subopcodeb1_0_2=(0, 2)
128 |   subopcodeb1_0_5=(0, 5)
129 |   subopcodeb1_0_7=(0, 7)
130 |   subopcodeL=(0, 6)
131 |   pred1=(0, 2)
132 | ;
133 | 
134 | define token opcode_byte2 (8)
135 |   subopcode3=(0, 3)
136 |   reg3=(4, 7)
137 | 
138 |   bitf8_0=(0,4)
139 |   bitf8_1=(5,7)
140 | 
141 |   subopcode_crypti=(0,4)
142 | ;
143 | 
144 | define token opcode_byte4 (8)
145 |   subopcode5=(0, 3)
146 | 
147 |   crypt_extra=(0, 1)
148 |   #subopcode_crypt=(2, 7)
149 | ;
150 | 
151 | @if defined(CRYPT_EXTENSION)
152 | # The crypto pair represents the last two bytes of a crypto command instruction.
153 | # It encodes data which are meant to be transferred to the SCP via an artificial
154 | # signal. This signal includes a crypto opcode, register notations and immediates,
155 | # depending on the specific command to be invoked.
156 | define token crypt_pair (16)
157 |   creg1=(0, 2)
158 |   creg2=(4, 6)
159 | 
160 |   cimm=(4, 9)
161 | 
162 |   subopcode_crypt=(10,14)
163 | ;
164 | @endif
165 | 
166 | define token immediate8 (8)
167 |   imm8=(0, 7)
168 |   imm8s=(0, 7) signed
169 |   fimm8=(0, 7)
170 |   fimm8s=(0, 7) signed
171 | ;
172 | 
173 | define token opcode_immediate16 (16)
174 |   imm16=(0, 15)
175 |   imm16s=(0, 15) signed
176 |   fimm16=(0, 15)
177 |   fimm16s=(0, 15) signed
178 | 
179 |   bitf16_0=(0,4)
180 |   bitf16_1=(5,9)
181 | ;
182 | 
183 | define token opcode_immediate24 (24)
184 |   fimm24s=(0, 23) signed
185 |   fimm24=(0, 23)
186 | ;
187 | 
188 | define token opcode_immediate32 (32)
189 |   fimm32=(0, 31)
190 | ;
191 | 
192 | # TODO: define opcode48 (seems used for bra on fuc5)
193 | 
194 | attach variables [ reg0 reg1 reg2 reg3 ]
195 | [
196 |   r0  r1  r2  r3
197 |   r4  r5  r6  r7
198 |   r8  r9  r10 r11
199 |   r12 r13 r14 r15
200 | ];
201 | 
202 | attach variables [ sreg1 sreg2 ]
203 | [
204 |   iv0  iv1  iv2  ev
205 |   sp   pc   imb  dmb
206 |   csw  ccr  sec  ctx
207 |   exci sec1 imb1 dmb1
208 | ];
209 | 
210 | @if defined(CRYPT_EXTENSION)
211 | attach variables [ creg1 creg2 ]
212 | [
213 |   c0 c1 c2 c3 c4 c5 c6 c7
214 | ];
215 | @endif
216 | 
217 | rel8: target is imm8s [ target = inst_start + imm8s; ] {
218 |   export *[imem]:4 target;
219 | }
220 | 
221 | rel16: target is imm16s [ target = inst_start + imm16s; ] {
222 |   export *[imem]:4 target;
223 | }
224 | 
225 | addr8: imm8 is imm8 {
226 |   export *[imem]:4 imm8;
227 | }
228 | 
229 | addr16: imm16 is imm16 {
230 |   export *[imem]:4 imm16;
231 | }
232 | 
233 | fimm24st: target is fimm24s [ target = 0 + fimm24s; ] {
234 |   export *[imem]:4 target;
235 | }
236 | 
237 | define pcodeop todo;
238 | define pcodeop todo_flags;
239 | 
240 | @include "macro.sinc"
241 | @include "unsized_inst.sinc"
242 | 
243 | @if defined(SUPPORT_FUC5P)
244 | @include "fuc5_inst.sinc"
245 | @endif
246 | 
247 | @if defined(CRYPT_EXTENSION)
248 | @include "crypt_inst.sinc"
249 | @endif
250 | 
251 | @include "envydis.sinc"
252 | 
253 | @include "sized.sinc"
254 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
  1 | # Nvidia Falcon plugin for Ghidra
  2 | 
  3 | This is pretty immature, so you'll probably need to do some development to use it, but it's likely good enough to save a bit of time over an `envydis` dead-listing.
  4 | 
  5 | ![Screenshot](/images/screenshot1.png)
  6 | 
  7 | ## Setup instructions
  8 | 
  9 | - Ensure you have the ``JAVA_HOME`` environment variable set to the path of your JDK 11 installation.
 10 | - Set the ``GHIDRA_INSTALL_DIR`` environment variable to your Ghidra install directory.
 11 | - Run ``./gradlew``.
 12 | - You'll find the output zip file inside ``/dist``.
 13 | - Copy the output zip to ``<Ghidra install directory>/Extensions/Ghidra``
 14 | - Start Ghidra and use the "Install Extensions" dialog to finish the installation. (``File -> Install Extensions...``)
 15 | 
 16 | ## Development
 17 | 
 18 | This is just how I do it:
 19 | 
 20 | Open up the [envytools Falcon ISA documentation](https://envytools.readthedocs.io/en/latest/hw/falcon/isa.html) to compare the semantic information with the reference pseudocode. Open Ghidra's `doc/languages/index.html` for a reference for how the Sleigh language works.
 21 | 
 22 | Load your test binary in Ghidra.
 23 | 
 24 | Use [envydis](https://github.com/envytools/envytools) on the binary you're looking at so you can quickly check the disassembly for errors if anything seems off.
 25 | 
 26 | In Ghidra enable PCode display by clicking the "Edit the Listing fields" icon at the top of the Listing view, right clicking "PCode" and clicking "Enable Field" (you may wish to toggle this on-and-off during reversing as it is quite verbose).
 27 | 
 28 | In Ghidra open the script manager ("Window" -> "Script Manager") and add key-bindings for `DebugSleighInstructionParse.java` and `ReloadSleighLangauge.java`.
 29 | 
 30 | `DebugSleighInstructionParse.java` will log detailed debug information about the instruciton parse for the byte under the cursor. I usually use it to find the `{line# 756} ld_b32 <reg2>, D[<reg1>]` so I know what line to go to to fix the PCode output.
 31 | 
 32 | `ReloadSleighLangauge.java` will reload most changes to the slaspec, including new instructions and new semantic definitions. However, if you add new registers or new `define pcodeop ...` statements, you will need to restart Ghidra to get correct output.
 33 | 
 34 | ### Adding instructions to the decompiler
 35 | 
 36 | At the moment any particularly poorly implemented instruction should show up as a call to the `todo` pcodeop in the decompiler output - this is a hint that the instruction should be implemented for correct decompilation. Get the line number using `DebugSleighInstructionParse.java` on the corresponding instruction, and add the implementation to the slaspec/sinc file.
 37 | 
 38 | See Ghidra's `doc/languages/index.html` for more information about how to describe instructions.
 39 | 
 40 | Run `ReloadSleighLangauge.java`, or, if you've added a new pcodeop for the instruction, close and re-open Ghidra to see the new output.
 41 | 
 42 | 
 43 | ### Adding instructions to the disassembler
 44 | 
 45 | If you hit undecodable instruction bytes, find the correct decoding in your `envydis` output, then search through the `envydis.sinc` file for the envydis source comment that matches. For example:
 46 | 
 47 | ```
 48 | #	{ 0x0004003c, 0x000f003f, OP3B, N("shl"), T(sz), REG3, REG1, REG2 },
 49 | ```
 50 | 
 51 | Try to find an implemented instruction using the same encoding/operands, for example:
 52 | 
 53 | ```
 54 | #	{ 0x0002003c, 0x000f003f, OP3B, N("sub"), T(sz), REG3, REG1, REG2 },
 55 | :sub_b32 reg3, reg1, reg2 is op_format=0x3c & op_size=2; reg2 & reg1; subopcode3=0x2 & reg3 {
 56 |   sub(reg3, reg1, reg2);
 57 | }
 58 | ```
 59 | 
 60 | Copy-paste and change the opcode/subopcode, mnemonic, and implementation:
 61 | 
 62 | ```
 63 | :shl_b32 reg3, reg1, reg2 is op_format=0x3c & op_size=2; reg2 & reg1; subopcode3=0x4 & reg3 {
 64 |   todo();
 65 | }
 66 | ```
 67 | 
 68 | Reload (with your `ReloadSleighLangauge.java` hotkey), disassemble the bytes (by pressing `D`), and check the output is correct. If it fails to disassemble, double check your code, or use `DebugSleighInstructionParse.java` to see where it goes wrong.
 69 | 
 70 | If you hit errors reloading, you can view the log by clicking the "Show Console" icon at the bottom Ghidra project window (the one with the file listing, not the CodeBrowser/disassembly window). The errors are only helpful some of the time, so I usually check my changes by hand first to see if I can spot what I did wrong.
 71 | 
 72 | ### Syntax highlighting
 73 | 
 74 | If you like syntax highlighting, Sleigh often looks okay highlighted as a bash script. I got tired of this and wrote a very basic sublime-syntax, which can be found at: https://github.com/hthh/sleigh-sublime-syntax
 75 | 
 76 | ## To-Do
 77 | 
 78 | Finish adding instructions and figure out how to do thorough automated testing.
 79 | 
 80 | It should be practical to generate a huge test file covering every instruction encoding with different operand values, and automatically compare the Ghidra and envydis output to finish the instruction decoding.
 81 | 
 82 | No idea how best to test the decompilation/pcode.
 83 | 
 84 | Known issues/todo-list:
 85 | 
 86 | * add other falcon variants
 87 | * fix mpop/mpush (and variants) to read/write all values
 88 | * rename "ram" to "iram" and document adding a "dram" section for globals
 89 | * try making "io" a real address space? might make naming easier
 90 | * see if there's a way to make crypto stuff decompile as `csecret(c1, 0x2)` instead of `csecret(1, 2)`
 91 | * global stores can be reordered to come after pcodeop calls that implicitly read from them (probably a ghidra bug?)
 92 | * can we bundle types? I'm loading an enum with io address constants (e.g. `FALCON_MAILBOX1 = 0x1100`) to make reversing easier. ("io" address space and default names might be the right approach?)
 93 | * finish adding packflags and unpackflags anywhere the flags register is used directly. make "xbit" on condition flags just move the one register.
 94 | * make the flags register actually show up when not just used for condition codes. writes to flags such as  "interrupt enable" don't show up in the decompiler.
 95 | * update readme screenshot sometime - that function is looking a ton better already (https://imgur.com/KGQJebQ), but I want to try to get things stable first to avoid making the repo huge with png files
 96 | 
 97 | ## Resources
 98 | 
 99 | * https://envytools.readthedocs.io/en/latest/hw/falcon/index.html - thorough hardware documentation
100 | * https://switchbrew.org/wiki/TSEC - crypt functionality
101 | * http://0x04.net/~mwk/Falcon.html - calling convention
102 | 


--------------------------------------------------------------------------------
/data/languages/crypt_inst.sinc:
--------------------------------------------------------------------------------
  1 | ###############################################################
  2 | ##
  3 | ## Definitions of the SCP opcodes from the crypto extension.
  4 | ##
  5 | ###############################################################
  6 | 
  7 | # Pseudocode operations for all crypto commands.
  8 | define pcodeop Do_Nothing;
  9 | define pcodeop Move_Data;
 10 | define pcodeop Read_Stream;
 11 | define pcodeop Write_Stream;
 12 | define pcodeop Generate_Random;
 13 | define pcodeop Record_Seq0;
 14 | define pcodeop Execute_Seq0;
 15 | define pcodeop Record_Seq1;
 16 | define pcodeop Execute_Seq1;
 17 | define pcodeop Modify_Acl;
 18 | define pcodeop Xor_Data;
 19 | define pcodeop Add_Data;
 20 | define pcodeop And_Data;
 21 | define pcodeop Reverse_Data;
 22 | define pcodeop GF_Multiply;
 23 | define pcodeop Load_Secret;
 24 | define pcodeop Set_Keyreg;
 25 | define pcodeop Expand_Key;
 26 | define pcodeop Reverse_Expand_Key;
 27 | define pcodeop Encrypt;
 28 | define pcodeop Decrypt;
 29 | define pcodeop Compare_Sig;
 30 | define pcodeop Encrypt_Sig;
 31 | define pcodeop Forget_Sig;
 32 | 
 33 | # Does nothing.
 34 | :cnop is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x0 {
 35 |   Do_Nothing();
 36 | }
 37 | 
 38 | # Moves a block into another crypto register.
 39 | :cmov creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x1 & creg1 & creg2 {
 40 |   Move_Data(creg1 :4, creg2 :4);
 41 | }
 42 | 
 43 | # Reads a block from the crypto stream.
 44 | :cxsin creg1 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x2 & creg1 {
 45 |   Read_Stream(creg1 :4);
 46 | }
 47 | 
 48 | # Writes a block to the crypto stream.
 49 | :cxsout creg1 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x3 & creg1 {
 50 |   Write_Stream(creg1 :4);
 51 | }
 52 | 
 53 | # Fills a crypto register with random data from the RNG controller.
 54 | :crnd creg1 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x4 & creg1 {
 55 |   Generate_Random(creg1 :4);
 56 | }
 57 | 
 58 | # Records a crypto script to be stored in slot 0 of the SEQ block of the SCP.
 59 | :cs0begin cimm is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x5 & cimm {
 60 |   Record_Seq0(cimm :5);
 61 | }
 62 | 
 63 | # Executes the crypto script stored in slot 0 of the SEQ block of the SCP.
 64 | :cs0exec cimm is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x6 & cimm {
 65 |   Execute_Seq0(cimm :5);
 66 | }
 67 | 
 68 | # Records a crypto script to be stored in slot 1 of the SEQ block of the SCP.
 69 | :cs1begin cimm is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x7 & cimm {
 70 |   Record_Seq1(cimm :5);
 71 | }
 72 | 
 73 | # Executes the crypto script stored in slot 1 of the SEQ block of the SCP.
 74 | :cs1exec cimm is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x8 & cimm {
 75 |   Execute_Seq1(cimm :5);
 76 | }
 77 | 
 78 | # Modifies the ACL value of a crypto register under special circumstances.
 79 | :cchmod creg1, cimm is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0xA & creg1 & cimm {
 80 |   Modify_Acl(creg1 :4, cimm :5);
 81 | }
 82 | 
 83 | # XORs a block with another block and stores the result.
 84 | :cxor creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0xB & creg1 & creg2 {
 85 |   Xor_Data(creg1 :4, creg2 :4);
 86 | }
 87 | 
 88 | # Adds an immediate to a block, modulo 2^64.
 89 | :cadd creg1, cimm is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0xC & creg1 & cimm {
 90 |   Add_Data(creg1 :4, cimm :5);
 91 | }
 92 | 
 93 | # ANDs a block with another block and stores the result.
 94 | :cand creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0xD & creg1 & creg2 {
 95 |   And_Data(creg1 :4, creg2 :4);
 96 | }
 97 | 
 98 | # Swaps the endianness of a block.
 99 | :crev creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0xE & creg1 & creg2 {
100 |   Reverse_Data(creg1 :4, creg2 :4);
101 | }
102 | 
103 | # Performs a Galois field multiplication on the whole block: res=block << 1; if (block & 0x800....) res ^= 0x87;
104 | :cgfmul creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0xF & creg1 & creg2 {
105 |   GF_Multiply(creg1 :4, creg2 :4);
106 | }
107 | 
108 | # Loads a selected hardware secret into a crypto register.
109 | :csecret creg1, cimm is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x10 & creg1 & cimm {
110 |   Load_Secret(creg1 :4, cimm :5);
111 | }
112 | 
113 | # Binds a register as the key register whose contents should be used for enc/dec operations.
114 | :ckeyreg creg1 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x11 & creg1 {
115 |   Set_Keyreg(creg1 :4);
116 | }
117 | 
118 | # Walks through the AES key schedule to generate the last round key.
119 | :ckexp creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x12 & creg1 & creg2 {
120 |   Expand_Key(creg1 :4, creg2 :4);
121 | }
122 | 
123 | # Walks through the AES key schedule in reverse to get the original key.
124 | :ckrexp creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x13 & creg1 & creg2 {
125 |   Reverse_Expand_Key(creg1 :4, creg2 :4);
126 | }
127 | 
128 | # Encrypts a block using the active key register and stores the ciphertext.
129 | :cenc creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x14 & creg1 & creg2 {
130 |   Encrypt(creg1 :4, creg2 :4);
131 | }
132 | 
133 | # Decrypts a block using the active key register and stores the plaintext.
134 | :cdec creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x15 & creg1 & creg2 {
135 |   Decrypt(creg1 :4, creg2 :4);
136 | }
137 | 
138 | # Compares two signatures and sets the auth signature for HS if they match.
139 | :csigcmp creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x16 & creg1 & creg2 {
140 |   Compare_Sig(creg1 :4, creg2 :4);
141 | }
142 | 
143 | # Encrypts the auth signature of the running code and sets ACL 0x13.
144 | :csigenc creg1, creg2 is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x17 & creg1 & creg2 {
145 |   Encrypt_Sig(creg1 :4, creg2 :4);
146 | }
147 | 
148 | # Clears the auth signature of the running HS code.
149 | :csigclr is raw_opcode=0xF5; subopcodeb1_0_7=0x3C; subopcode_crypt=0x18 {
150 |   Forget_Sig();
151 | }
152 | 
153 | #	/* The indirect crypt opcodes.
154 | #	 *
155 | #	 * For one-reg opcodes, the crypt register to use is selected by
156 | #	 * bits 8-10 of the operand. For two-reg opcodes, destination is in
157 | #	 * bits 8-10, source in 0-2. For reg, imm opcodes, reg is in
158 | #	 * bits 8-10, immediate in 0-5. For imm-only opcodes, immediate is in
159 | #	 * bits 0-5.
160 | #	 *
161 | #	 * Or, in other words, the insn is converted into f5/3c op as follows:
162 | #	 *
163 | #	 *  bits 0-3: bits 8-11 of reg operand
164 | #	 *  bits 4-9: bits 0-5 of reg operand
165 | #	 *  bits 10-14: bits 0-4 of immediate byte
166 | #	 *  bit 15: always set.
167 | #	 */
168 | #	{ 0x00010cf2, 0x001f0fff, OP3B, N("cimov"), REG1, .fmask = F_CRYPT },
169 | :cimov reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x01 {
170 |   todo(reg1 :4);
171 | }
172 | 
173 | #	{ 0x00020cf2, 0x001f0fff, OP3B, N("cixsin"), REG1, .fmask = F_CRYPT },
174 | :cixsin reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x02 {
175 |   todo(reg1 :4);
176 | }
177 | 
178 | #	{ 0x00030cf2, 0x001f0fff, OP3B, N("cixsout"), REG1, .fmask = F_CRYPT },
179 | :cixsout reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x03 {
180 |   todo(reg1 :4);
181 | }
182 | 
183 | #	{ 0x00050cf2, 0x001f0fff, OP3B, N("cis0begin"), REG1, .fmask = F_CRYPT },
184 | :cis0begin reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x05 {
185 |   todo(reg1 :4);
186 | }
187 | 
188 | #	{ 0x00060cf2, 0x001f0fff, OP3B, N("cis0exec"), REG1, .fmask = F_CRYPT },
189 | :cis0exec reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x06 {
190 |   todo(reg1 :4);
191 | }
192 | 
193 | #	{ 0x00070cf2, 0x001f0fff, OP3B, N("cis1begin"), REG1, .fmask = F_CRYPT },
194 | :cis1begin reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x07 {
195 |   todo(reg1 :4);
196 | }
197 | 
198 | #	{ 0x00080cf2, 0x001f0fff, OP3B, N("cis1exec"), REG1, .fmask = F_CRYPT },
199 | :cis1exec reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x08 {
200 |   todo(reg1 :4);
201 | }
202 | 
203 | #	{ 0x000b0cf2, 0x001f0fff, OP3B, N("cixor"), REG1, .fmask = F_CRYPT },
204 | :cixor reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x0b {
205 |   todo(reg1 :4);
206 | }
207 | 
208 | #	{ 0x000c0cf2, 0x001f0fff, OP3B, N("ciadd"), REG1, .fmask = F_CRYPT },
209 | :ciadd reg1 is raw_opcode=0xf2; subopcode2=0xC & reg1; subopcode_crypti=0x0c {
210 |   todo(reg1 :4);
211 | }
212 | 
213 | #	{ 0x000d0cf2, 0x001f0fff, OP3B, N("ciand"), REG1, .fmask = F_CRYPT },
214 | :ciand reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x0d {
215 |   todo(reg1 :4);
216 | }
217 | 
218 | #	{ 0x000e0cf2, 0x001f0fff, OP3B, N("cirev"), REG1, .fmask = F_CRYPT },
219 | :cirev reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x0e {
220 |   todo(reg1 :4);
221 | }
222 | 
223 | #	{ 0x000f0cf2, 0x001f0fff, OP3B, N("ciprecmac"), REG1, .fmask = F_CRYPT },
224 | :ciprecmac reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x0f {
225 |   todo(reg1 :4);
226 | }
227 | 
228 | #	{ 0x00100cf2, 0x001f0fff, OP3B, N("cisecret"), REG1, .fmask = F_CRYPT },
229 | :cisecret reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x10 {
230 |   todo(reg1 :4);
231 | }
232 | 
233 | #	{ 0x00110cf2, 0x001f0fff, OP3B, N("cikeyreg"), REG1, .fmask = F_CRYPT },
234 | :cikeyreg reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x11 {
235 |   todo(reg1 :4);
236 | }
237 | 
238 | #	{ 0x00120cf2, 0x001f0fff, OP3B, N("cikexp"), REG1, .fmask = F_CRYPT },
239 | :cikexp reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x12 {
240 |   todo(reg1 :4);
241 | }
242 | 
243 | #	{ 0x00130cf2, 0x001f0fff, OP3B, N("cikrexp"), REG1, .fmask = F_CRYPT },
244 | :cikrexp reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x13 {
245 |   todo(reg1 :4);
246 | }
247 | 
248 | #	{ 0x00140cf2, 0x001f0fff, OP3B, N("cienc"), REG1, .fmask = F_CRYPT },
249 | :cienc reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x14 {
250 |   todo(reg1 :4);
251 | }
252 | 
253 | #	{ 0x00150cf2, 0x001f0fff, OP3B, N("cidec"), REG1, .fmask = F_CRYPT },
254 | :cidec reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x15 {
255 |   todo(reg1 :4);
256 | }
257 | 
258 | #	{ 0x00170cf2, 0x001f0fff, OP3B, N("cisigenc"), REG1, .fmask = F_CRYPT },
259 | :cisigenc reg1 is raw_opcode=0xf2; subopcode2=0xc & reg1; subopcode_crypti=0x17 {
260 |   todo(reg1 :4);
261 | }
262 | 


--------------------------------------------------------------------------------
/data/languages/sized_include.sinc:
--------------------------------------------------------------------------------
  1 | # WARNING: This is a multiply-included header, see "sized.sinc".
  2 | 
  3 | # Constructors in "@ifdef ONCE" are defined only once.
  4 | # Constructors in "@ifndef ONCE" are defined three times, for b32, b16 and b8 variants,
  5 | # these run in a "with" block that validates the "op_size" field.
  6 | 
  7 | @ifndef ONCE
  8 | #static struct insn tabsi[] = {
  9 | #	{ 0x00000000, 0x0000003f, OP3B, N("st"), T(sz), T(datari), REG2, .fmask = F_FUCOLD },
 10 | @if defined(SUPPORT_FUCOLD)
 11 | :st^$(SZ_SUFFIX) "D"^[reg1 + offset], reg2 is op_format=0x00; reg2 & reg1; imm8 [ offset=imm8 * $(SZ_BYTES); ] {
 12 | @if SZ_BITS == "32"
 13 |   store32
 14 | @elif SZ_BITS == "16"
 15 |   store16
 16 | @elif SZ_BITS == "8"
 17 |   store8
 18 | @endif
 19 |     (reg1 + offset, reg2);
 20 | }
 21 | @endif
 22 | #	{ 0x00000000, 0x00000030, OP3B, OOPS, T(sz), REG1, REG2, IMM8, .fmask = F_FUCOLD },
 23 | #
 24 | 
 25 | 
 26 | @endif # !ONCE
 27 | @ifdef ONCE
 28 | @if defined(SUPPORT_FUC5P)
 29 | #	{ 0x00000000, 0x000000f0, OP2B, N("mov"), REG0, FIMM8S, .fmask = F_FUC5P },
 30 | :mov reg0, fimm8s is raw_opcode_hi=0x00 & reg0; fimm8s {
 31 |   reg0 = fimm8s;
 32 | }
 33 | 
 34 | #	{ 0x00000040, 0x000000f0, OP3B, N("mov"), REG0, FIMM16S, .fmask = F_FUC5P },
 35 | :mov reg0, fimm16s is raw_opcode_hi=0x4 & reg0; fimm16s {
 36 |   reg0 = fimm16s;
 37 | }
 38 | 
 39 | #	{ 0x00000080, 0x000000f0, OP4B, N("mov"), REG0, FIMM24S, .fmask = F_FUC5P },
 40 | :mov reg0, fimm24s is raw_opcode_hi=0x8 & reg0; fimm24s {
 41 |   reg0 = fimm24s;
 42 | }
 43 | @endif
 44 | 
 45 | @endif # ONCE
 46 | @ifndef ONCE
 47 | #
 48 | #	{ 0x00000010, 0x0000003f, OP3B, N("add"), T(sz), REG2, REG1, IMM8 },
 49 | :add^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x10; reg2 & reg1; imm8 {
 50 |   add(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
 51 | }
 52 | 
 53 | #	{ 0x00000011, 0x0000003f, OP3B, N("adc"), T(sz), REG2, REG1, IMM8 },
 54 | :adc^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x11; reg2 & reg1; imm8 {
 55 |   adc(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
 56 | }
 57 | 
 58 | #	{ 0x00000012, 0x0000003f, OP3B, N("sub"), T(sz), REG2, REG1, IMM8 },
 59 | :sub^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x12; reg2 & reg1; imm8 {
 60 |   sub(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
 61 | }
 62 | 
 63 | #	{ 0x00000013, 0x0000003f, OP3B, N("sbb"), T(sz), REG2, REG1, IMM8 },
 64 | :sbb^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x13; reg2 & reg1; imm8 {
 65 |   todo_binop(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8 :1);
 66 |   #sbb(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
 67 | }
 68 | 
 69 | #	{ 0x00000014, 0x0000003f, OP3B, N("shl"), T(sz), REG2, REG1, IMM8 },
 70 | :shl^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x14; reg2 & reg1; imm8 {
 71 |   # TODO: fix mask
 72 |   shl32(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
 73 | }
 74 | 
 75 | #	{ 0x00000015, 0x0000003f, OP3B, N("shr"), T(sz), REG2, REG1, IMM8 },
 76 | :shr^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x15; reg2 & reg1; imm8 {
 77 |   # TODO: fix mask
 78 |   shr32(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
 79 | }
 80 | 
 81 | #	{ 0x00000017, 0x0000003f, OP3B, N("sar"), T(sz), REG2, REG1, IMM8 },
 82 | :sar^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x17; reg2 & reg1; imm8 {
 83 |   # TODO: fix mask
 84 |   sar32(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
 85 | }
 86 | 
 87 | #	{ 0x00000018, 0x0000003f, OP3B, N("ld"), T(sz), REG2, T(datari) },
 88 | :ld^$(SZ_SUFFIX) reg2, "D"^[reg1 + offset] is op_format=0x18; reg2 & reg1; imm8 [ offset=imm8 * $(SZ_BYTES); ] {
 89 | @if SZ_BITS == "32"
 90 |   load32
 91 | @elif SZ_BITS == "16"
 92 |   load16
 93 | @elif SZ_BITS == "8"
 94 |   load8
 95 | @endif
 96 |     (reg2:$(SZ_BYTES), reg1 + offset);
 97 | }
 98 | 
 99 | #	{ 0x0000001c, 0x0000003f, OP3B, N("shlc"), T(sz), REG2, REG1, IMM8 },
100 | :shlc^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x1c; reg2 & reg1; imm8 {
101 |   todo_binop(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8 :1);
102 | }
103 | 
104 | #	{ 0x0000001d, 0x0000003f, OP3B, N("shrc"), T(sz), REG2, REG1, IMM8 },
105 | :shrc^$(SZ_SUFFIX) reg2, reg1, imm8 is op_format=0x1d; reg2 & reg1; imm8 {
106 |   todo_binop(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8 :1);
107 | }
108 | 
109 | #	{ 0x00000010, 0x00000030, OP3B, OOPS, T(sz), REG2, REG1 },
110 | #
111 | @if defined(SUPPORT_FUCOLD)
112 | #	{ 0x00000020, 0x0000003f, OP4B, N("add"), T(sz), REG2, REG1, IMM16, .fmask = F_FUCOLD },
113 | :add^$(SZ_SUFFIX) reg2, reg1, imm16 is op_format=0x20; reg2 & reg1; imm16 {
114 |   add(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16);
115 | }
116 | 
117 | #	{ 0x00000021, 0x0000003f, OP4B, N("adc"), T(sz), REG2, REG1, IMM16, .fmask = F_FUCOLD },
118 | :adc^$(SZ_SUFFIX) reg2, reg1, imm16 is op_format=0x21; reg2 & reg1; imm16 {
119 |   adc(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16);
120 | }
121 | 
122 | #	{ 0x00000022, 0x0000003f, OP4B, N("sub"), T(sz), REG2, REG1, IMM16, .fmask = F_FUCOLD },
123 | :sub^$(SZ_SUFFIX) reg2, reg1, imm16 is op_format=0x22; reg2 & reg1; imm16 {
124 |   sub(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16);
125 | }
126 | 
127 | #	{ 0x00000023, 0x0000003f, OP4B, N("sbb"), T(sz), REG2, REG1, IMM16, .fmask = F_FUCOLD },
128 | :sbb^$(SZ_SUFFIX) reg2, reg1, imm16 is op_format=0x23; reg2 & reg1; imm16 {
129 |   todo_binop(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16 :4);
130 | }
131 | 
132 | #	{ 0x00000020, 0x00000030, OP4B, OOPS, T(sz), REG2, REG1, IMM16, .fmask = F_FUCOLD },
133 | @endif
134 | #
135 | @if defined(SUPPORT_FUC5P)
136 | #	{ 0x00000020, 0x0000003f, OP2B, N("st"), T(sz), DATAR, REG2, .fmask = F_FUC5P },
137 | :st^$(SZ_SUFFIX) "D"^[reg1], reg2 is op_format=0x20; reg2 & reg1 {
138 | @if SZ_BITS == "32"
139 |   store32
140 | @elif SZ_BITS == "16"
141 |   store16
142 | @elif SZ_BITS == "8"
143 |   store8
144 | @endif
145 |     (reg1, reg2);
146 | }
147 | 
148 | #	{ 0x00000021, 0x0000003f, OP2B, N("st"), T(sz), T(dataspr), REG1, .fmask = F_FUC5P },
149 | #	{ 0x00000024, 0x0000003f, OP2B, N("cmpu"), T(sz), REG1, REG2, .fmask = F_FUC5P },
150 | :cmpu^$(SZ_SUFFIX) reg1, reg2 is op_format=0x24; reg2 & reg1 {
151 |   cmpu(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
152 | }
153 | 
154 | #	{ 0x00000025, 0x0000003f, OP2B, N("cmps"), T(sz), REG1, REG2, .fmask = F_FUC5P },
155 | :cmps^$(SZ_SUFFIX) reg1, reg2 is op_format=0x25; reg2 & reg1 {
156 |   cmps(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
157 | }
158 | 
159 | #	{ 0x00000026, 0x0000003f, OP2B, N("cmp"), T(sz), REG1, REG2, .fmask = F_FUC5P },
160 | :cmp^$(SZ_SUFFIX) reg1, reg2 is op_format=0x26; reg2 & reg1 {
161 |   cmp(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
162 | }
163 | 
164 | #	{ 0x00000020, 0x00000030, OP2B, OOPS, T(sz), REG1, REG2, .fmask = F_FUC5P },
165 | @endif
166 | #
167 | #
168 | #	{ 0x00000130, 0x00000f3f, T(ol0), N("st"), T(sz), T(datasp), REG1 },
169 | :st^$(SZ_SUFFIX) "D"^[sp + offset], reg1 is op_format=0x30; subopcode2=0x1 & reg1 & sp ; imm8 [ offset=imm8 * $(SZ_BYTES); ] {
170 | @if SZ_BITS == "32"
171 |   store32
172 | @elif SZ_BITS == "16"
173 |   store16
174 | @elif SZ_BITS == "8"
175 |   store8
176 | @endif
177 |     (sp + offset, reg1);
178 | }
179 | 
180 | #	{ 0x00000430, 0x00000f3e, T(ol0), N("cmpu"), T(sz), REG1, T(i) },
181 | :cmpu^$(SZ_SUFFIX) reg1, imm8 is op_format=0x30; subopcode2=0x4 & reg1 ; imm8 {
182 |   cmpu(reg1:$(SZ_BYTES), imm8);
183 | }
184 | :cmpu^$(SZ_SUFFIX) reg1, imm16 is op_format=0x31; subopcode2=0x4 & reg1 ; imm16 {
185 |   cmpu(reg1:$(SZ_BYTES), imm16);
186 | }
187 | 
188 | #	{ 0x00000530, 0x00000f3e, T(ol0), N("cmps"), T(sz), REG1, T(is) },
189 | :cmps^$(SZ_SUFFIX) reg1, imm8s is op_format=0x30; subopcode2=0x5 & reg1 ; imm8s {
190 |   cmps(reg1:$(SZ_BYTES), imm8s);
191 | }
192 | :cmps^$(SZ_SUFFIX) reg1, imm16s is op_format=0x31; subopcode2=0x5 & reg1 ; imm16s {
193 |   cmps(reg1:$(SZ_BYTES), imm16s);
194 | }
195 | 
196 | #	{ 0x00000630, 0x00000f3e, T(ol0), N("cmp"), T(sz), REG1, T(is), .fmask = F_FUC3P },
197 | :cmp^$(SZ_SUFFIX) reg1, imm8s is op_format=0x30; subopcode2=0x6 & reg1 ; imm8s {
198 |   cmp(reg1:$(SZ_BYTES), imm8s);
199 | }
200 | :cmp^$(SZ_SUFFIX) reg1, imm16s is op_format=0x31; subopcode2=0x6 & reg1 ; imm16s {
201 |   cmp(reg1:$(SZ_BYTES), imm16s);
202 | }
203 | 
204 | #	{ 0x00000030, 0x0000003e, T(ol0), OOPS, T(sz), REG1, T(i) },
205 | #
206 | @if defined(SUPPORT_FUC5P)
207 | #	{ 0x00000032, 0x0000003f, OP2B, N("mov"), T(sz), REG2, REG1, .fmask = F_FUC5P },
208 | :mov^$(SZ_SUFFIX) reg2, reg1 is op_format=0x32; reg2 & reg1 {
209 |   mov(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES));
210 | }
211 | 
212 | #
213 | #	/* XXX not verified yet */
214 | #	{ 0x00000033, 0x00000f3f, OP4B, N("bra"), T(sz), REG1, IMM8, N("e"), SFBTARG, .fmask = F_FUC5P },
215 | :bra^$(SZ_SUFFIX) reg1, imm8, "e", rel8 is op_format=0x33; subopcode2=0x0 & reg1; imm8; rel8 {
216 |   if ((reg1:$(SZ_BYTES)) == imm8) goto rel8;
217 | }
218 | 
219 | #	{ 0x00000433, 0x00000f3f, OP4B, N("bra"), T(sz), REG1, IMM8, N("ne"), SFBTARG, .fmask = F_FUC5P },
220 | :bra^$(SZ_SUFFIX) reg1, imm8, "ne", rel8 is op_format=0x33; subopcode2=0x4 & reg1; imm8; rel8 {
221 |   if ((reg1:$(SZ_BYTES)) != imm8) goto rel8;
222 | }
223 | 
224 | #	{ 0x00000933, 0x00000f3f, OP5B, N("bra"), T(sz), REG1, IMM8, N("e"), LFBTARG, .fmask = F_FUC5P },
225 | :bra^$(SZ_SUFFIX) reg1, imm8, "e", rel16 is op_format=0x33; subopcode2=0x9 & reg1; imm8; rel16 {
226 |  if ((reg1:$(SZ_BYTES)) == imm8) goto rel16;
227 | }
228 | 
229 | #	{ 0x00000a33, 0x00000f3f, OP5B, N("bra"), T(sz), REG1, IMM16, N("e"), SFFBTARG, .fmask = F_FUC5P },
230 | :bra^$(SZ_SUFFIX) reg1, imm16, "e", rel8 is op_format=0x33; subopcode2=0xA & reg1; imm16; rel8 {
231 |   if ((reg1:$(SZ_BYTES)) == imm16) goto rel8;
232 | }
233 | 
234 | #	{ 0x00000b33, 0x00000f3f, OP6B, N("bra"), T(sz), REG1, IMM16, N("e"), LFFBTARG, .fmask = F_FUC5P },
235 | :bra^$(SZ_SUFFIX) reg1, imm16, "e", rel16 is op_format=0x33; subopcode2=0xB & reg1; imm16; rel16 {
236 |   if ((reg1:$(SZ_BYTES)) == imm16) goto rel16;
237 | }
238 | 
239 | #	{ 0x00000d33, 0x00000f3f, OP5B, N("bra"), T(sz), REG1, IMM8, N("ne"), LFBTARG, .fmask = F_FUC5P },
240 | :bra^$(SZ_SUFFIX) reg1, imm8, "ne", rel16 is op_format=0x33; subopcode2=0xD & reg1; imm8; rel16 {
241 |  if ((reg1:$(SZ_BYTES)) != imm8) goto rel16;
242 | }
243 | 
244 | #	{ 0x00000e33, 0x00000f3f, OP5B, N("bra"), T(sz), REG1, IMM16, N("ne"), SFFBTARG, .fmask = F_FUC5P },
245 | :bra^$(SZ_SUFFIX) reg1, imm16, "ne", rel8 is op_format=0x33; subopcode2=0xE & reg1; imm16; rel8 {
246 |   if ((reg1:$(SZ_BYTES)) != imm16) goto rel8;
247 | }
248 | 
249 | #	{ 0x00000f33, 0x00000f3f, OP6B, N("bra"), T(sz), REG1, IMM16, N("ne"), LFFBTARG, .fmask = F_FUC5P },
250 | :bra^$(SZ_SUFFIX) reg1, imm16, "ne", rel16 is op_format=0x33; subopcode2=0xf & reg1; imm16; rel16 {
251 |   if ((reg1:$(SZ_BYTES)) != imm16) goto rel16;
252 | }
253 | @endif
254 | #
255 | #	{ 0x00000034, 0x00000f3f, OP3B, N("ld"), T(sz), REG1, T(datasp) },
256 | :ld^$(SZ_SUFFIX) reg1, "D"^[sp + offset] is op_format=0x34; subopcode2=0x0 & reg1 & sp ; imm8 [ offset=imm8 * $(SZ_BYTES); ] {
257 | @if SZ_BITS == "32"
258 |   load32
259 | @elif SZ_BITS == "16"
260 |   load16
261 | @elif SZ_BITS == "8"
262 |   load8
263 | @endif
264 |     (reg1:$(SZ_BYTES), sp + offset);
265 | }
266 | 
267 | #	{ 0x00000034, 0x0000003f, OP3B, OOPS, T(sz), REG1, IMM8 },
268 | #
269 | 
270 | @if defined(SUPPORT_FUC5P)
271 | #	{ 0x00000035, 0x0000003f, OP3B, N("st"), T(sz), T(datari), REG2, .fmask = F_FUC5P },
272 | :st^$(SZ_SUFFIX) "D"^[reg1 + offset], reg2 is op_format=0x35; reg2 & reg1; imm8 [ offset=imm8 * $(SZ_BYTES); ] {
273 | @if SZ_BITS == "32"
274 |   store32
275 | @elif SZ_BITS == "16"
276 |   store16
277 | @elif SZ_BITS == "8"
278 |   store8
279 | @endif
280 |     (reg1 + offset, reg2);
281 | }
282 | @endif
283 | 
284 | #
285 | #	{ 0x00000036, 0x00000f3e, T(ol0), N("add"), T(sz), REG1, T(i) },
286 | :add^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0x0 & reg1; imm8 {
287 |   add(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
288 | }
289 | :add^$(SZ_SUFFIX) reg1, imm16 is op_format=0x37; subopcode2=0x0 & reg1; imm16 {
290 |   add(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16);
291 | }
292 | 
293 | #	{ 0x00000136, 0x00000f3e, T(ol0), N("adc"), T(sz), REG1, T(i) },
294 | :adc^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0x1 & reg1; imm8 {
295 |   adc(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
296 | }
297 | 
298 | #	{ 0x00000236, 0x00000f3e, T(ol0), N("sub"), T(sz), REG1, T(i) },
299 | :sub^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0x2 & reg1; imm8 {
300 |   sub(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
301 | }
302 | :sub^$(SZ_SUFFIX) reg1, imm16 is op_format=0x37; subopcode2=0x2 & reg1; imm16 {
303 |   sub(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16);
304 | }
305 | 
306 | #	{ 0x00000336, 0x00000f3e, T(ol0), N("sbb"), T(sz), REG1, T(i) },
307 | :sbb^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0x3 & reg1; imm8 {
308 |   todo_binop(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8 :1);
309 | }
310 | 
311 | #	{ 0x00000436, 0x00000f3f, T(ol0), N("shl"), T(sz), REG1, T(i) },
312 | :shl^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0x4 & reg1; imm8 {
313 |   # TODO: fix mask
314 |   shl32(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
315 | }
316 | 
317 | #	{ 0x00000536, 0x00000f3f, T(ol0), N("shr"), T(sz), REG1, T(i) },
318 | :shr^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0x5 & reg1; imm8 {
319 |   # TODO: fix mask
320 |   shr32(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
321 | }
322 | 
323 | #	{ 0x00000736, 0x00000f3f, T(ol0), N("sar"), T(sz), REG1, T(i) },
324 | :sar^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0x7 & reg1; imm8 {
325 |   # TODO: fix mask
326 |   sar32(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8);
327 | }
328 | 
329 | #	{ 0x00000c36, 0x00000f3f, T(ol0), N("shlc"), T(sz), REG1, T(i) },
330 | :shlc^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0xc & reg1; imm8 {
331 |   todo_binop(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8 :1);
332 | }
333 | 
334 | #	{ 0x00000d36, 0x00000f3f, T(ol0), N("shrc"), T(sz), REG1, T(i) },
335 | :shrc^$(SZ_SUFFIX) reg1, imm8 is op_format=0x36; subopcode2=0xd & reg1; imm8 {
336 |   todo_binop(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), imm8 :1);
337 | }
338 | 
339 | #	{ 0x00000036, 0x0000003e, T(ol0), OOPS, T(sz), REG1, T(i) },
340 | #
341 | @if defined(SUPPORT_FUCOLD)
342 | #	{ 0x00000038, 0x000f003f, OP3B, N("st"), T(sz), DATAR, REG2, .fmask = F_FUCOLD },
343 | :st^$(SZ_SUFFIX) "D"^[reg1], reg2 is op_format=0x38; reg2 & reg1; subopcode3=0x0 {
344 | @if SZ_BITS == "32"
345 |   store32
346 | @elif SZ_BITS == "16"
347 |   store16
348 | @elif SZ_BITS == "8"
349 |   store8
350 | @endif
351 |     (reg1, reg2);
352 | }
353 | 
354 | 
355 | #	{ 0x00010038, 0x000f003f, OP3B, N("st"), T(sz), T(dataspr), REG1, .fmask = F_FUCOLD },
356 | #	{ 0x00040038, 0x000f003f, OP3B, N("cmpu"), T(sz), REG1, REG2, .fmask = F_FUCOLD },
357 | :cmpu^$(SZ_SUFFIX) reg1, reg2 is op_format=0x38; reg2 & reg1; subopcode3=0x4 {
358 |   cmpu(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
359 | }
360 | 
361 | #	{ 0x00050038, 0x000f003f, OP3B, N("cmps"), T(sz), REG1, REG2, .fmask = F_FUCOLD },
362 | :cmps^$(SZ_SUFFIX) reg1, reg2 is op_format=0x38; reg2 & reg1; subopcode3=0x5 {
363 |   cmps(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
364 | }
365 | 
366 | #	{ 0x00060038, 0x000f003f, OP3B, N("cmp"), T(sz), REG1, REG2, .fmask = F_FUC3P | F_FUCOLD },
367 | :cmp^$(SZ_SUFFIX) reg1, reg2 is op_format=0x38; reg2 & reg1; subopcode3=0x6 {
368 |   cmp(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
369 | }
370 | 
371 | #	{ 0x00000038, 0x0000003f, OP3B, OOPS, T(sz), REG1, REG2, .fmask = F_FUCOLD },
372 | @endif
373 | #
374 | 
375 | @if defined(SUPPORT_FUC5P)
376 | #	{ 0x0000000038, 0x0f0000003f, OP5B, N("add"), T(sz), REG2, REG1, IMM16, .fmask = F_FUC5P },
377 | :add^$(SZ_SUFFIX) reg2, reg1, imm16 is op_format=0x38; reg2 & reg1; imm16 ; subopcode5=0x0 {
378 |   add(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16);
379 | }
380 | 
381 | #	{ 0x0100000038, 0x0f0000003f, OP5B, N("adc"), T(sz), REG2, REG1, IMM16, .fmask = F_FUC5P },
382 | :adc^$(SZ_SUFFIX) reg2, reg1, imm16 is op_format=0x38; reg2 & reg1; imm16 ; subopcode5=0x1 {
383 |   adc(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16);
384 | }
385 | 
386 | #	{ 0x0200000038, 0x0f0000003f, OP5B, N("sub"), T(sz), REG2, REG1, IMM16, .fmask = F_FUC5P },
387 | :sub^$(SZ_SUFFIX) reg2, reg1, imm16 is op_format=0x38; reg2 & reg1; imm16 ; subopcode5=0x2 {
388 |   sub(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16);
389 | }
390 | 
391 | #	{ 0x0300000038, 0x0f0000003f, OP5B, N("sbb"), T(sz), REG2, REG1, IMM16, .fmask = F_FUC5P },
392 | :sbb^$(SZ_SUFFIX) reg2, reg1, imm16 is op_format=0x38; reg2 & reg1; imm16 ; subopcode5=0x3 {
393 |   todo_binop(reg2:$(SZ_BYTES), reg1:$(SZ_BYTES), imm16 :4);
394 | }
395 | 
396 | #	{ 0x00000038, 0x0000003f, OP5B, OOPS, T(sz), REG2, REG1, IMM16, .fmask = F_FUC5P },
397 | @endif
398 | #
399 | #	{ 0x00000039, 0x000f003f, OP3B, N("not"), T(sz), REG2, REG1 },
400 | :not^$(SZ_SUFFIX) reg1, reg2 is op_format=0x39; reg2 & reg1; subopcode3=0x0 {
401 |   not(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
402 | }
403 | 
404 | #	{ 0x00010039, 0x000f003f, OP3B, N("neg"), T(sz), REG2, REG1 },
405 | :neg^$(SZ_SUFFIX) reg1, reg2 is op_format=0x39; reg2 & reg1; subopcode3=0x1 {
406 |   neg(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
407 | }
408 | 
409 | #	{ 0x00020039, 0x000f003f, OP3B, N("movf"), T(sz), REG2, REG1, .fmask = F_FUC0 },
410 | 
411 | @if defined(SUPPORT_FUCOLD)
412 | #	{ 0x00020039, 0x000f003f, OP3B, N("mov"), T(sz), REG2, REG1, .fmask = F_FUC3P | F_FUCOLD },
413 | :mov^$(SZ_SUFFIX) reg1, reg2 is op_format=0x39; reg2 & reg1; subopcode3=0x2 {
414 |   mov(reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
415 | }
416 | @endif
417 | 
418 | #	{ 0x00030039, 0x000f003f, OP3B, N("hswap"), T(sz), REG2, REG1 },
419 | #	{ 0x00000039, 0x0000003f, OP3B, OOPS, T(sz), REG2, REG1 },
420 | #
421 | #	{ 0x0000003a, 0x000f003f, OP3B, N("ld"), T(sz), REG1, T(dataspr) },
422 | #	{ 0x0000003a, 0x0000003f, OP3B, OOPS, T(sz), REG1, REG2 },
423 | #
424 | #	{ 0x0000003b, 0x000f003f, OP3B, N("add"), T(sz), REG1, REG2 },
425 | :add^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0x0 {
426 |   add(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
427 | }
428 | 
429 | #	{ 0x0001003b, 0x000f003f, OP3B, N("adc"), T(sz), REG1, REG2 },
430 | :adc^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0x1 {
431 |   adc(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
432 | }
433 | 
434 | #	{ 0x0002003b, 0x000f003f, OP3B, N("sub"), T(sz), REG1, REG2 },
435 | :sub^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0x2 {
436 |   sub(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
437 | }
438 | 
439 | #	{ 0x0003003b, 0x000f003f, OP3B, N("sbb"), T(sz), REG1, REG2 },
440 | :sbb^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0x3 {
441 |   todo_binop(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
442 | }
443 | 
444 | #	{ 0x0004003b, 0x000f003f, OP3B, N("shl"), T(sz), REG1, REG2 },
445 | :shl^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0x4 {
446 |   # TODO: fix mask
447 |   shl32(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
448 | }
449 | 
450 | #	{ 0x0005003b, 0x000f003f, OP3B, N("shr"), T(sz), REG1, REG2 },
451 | :shr^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0x5 {
452 |   # TODO: fix mask
453 |   shr32(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
454 | }
455 | 
456 | #	{ 0x0007003b, 0x000f003f, OP3B, N("sar"), T(sz), REG1, REG2 },
457 | :sar^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0x7 {
458 |   # TODO: fix mask
459 |   sar32(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
460 | }
461 | 
462 | 
463 | #	{ 0x000c003b, 0x000f003f, OP3B, N("shlc"), T(sz), REG1, REG2 },
464 | :shlc^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0xc {
465 |   todo_binop(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
466 | }
467 | 
468 | #	{ 0x000d003b, 0x000f003f, OP3B, N("shrc"), T(sz), REG1, REG2 },
469 | :shrc^$(SZ_SUFFIX) reg1, reg2 is op_format=0x3b; reg2 & reg1; subopcode3=0xd {
470 |   todo_binop(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
471 | }
472 | 
473 | #	{ 0x0000003b, 0x0000003f, OP3B, OOPS, T(sz), REG1, REG2 },
474 | #
475 | #	{ 0x0000003c, 0x000f003f, OP3B, N("add"), T(sz), REG3, REG1, REG2 },
476 | :add^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0x0 & reg3 {
477 |   add(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
478 | }
479 | 
480 | #	{ 0x0001003c, 0x000f003f, OP3B, N("adc"), T(sz), REG3, REG1, REG2 },
481 | :adc^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0x1 & reg3 {
482 |   adc(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
483 | }
484 | 
485 | #	{ 0x0002003c, 0x000f003f, OP3B, N("sub"), T(sz), REG3, REG1, REG2 },
486 | :sub^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0x2 & reg3 {
487 |   sub(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
488 | }
489 | 
490 | #	{ 0x0003003c, 0x000f003f, OP3B, N("sbb"), T(sz), REG3, REG1, REG2 },
491 | :sbb^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0x3 & reg3 {
492 |   todo_binop(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
493 | }
494 | 
495 | #	{ 0x0004003c, 0x000f003f, OP3B, N("shl"), T(sz), REG3, REG1, REG2 },
496 | :shl^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0x4 & reg3 {
497 |   shl32(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
498 | }
499 | 
500 | #	{ 0x0005003c, 0x000f003f, OP3B, N("shr"), T(sz), REG3, REG1, REG2 },
501 | :shr^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0x5 & reg3 {
502 |   # TODO: fix mask
503 |   shr32(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
504 | }
505 | 
506 | #	{ 0x0007003c, 0x000f003f, OP3B, N("sar"), T(sz), REG3, REG1, REG2 },
507 | :sar^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0x7 & reg3 {
508 |   # TODO: fix mask
509 |   sar32(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
510 | }
511 | 
512 | #	{ 0x0008003c, 0x000f003f, OP3B, N("ld"), T(sz), REG3, T(datarr) },
513 | :ld^$(SZ_SUFFIX) reg3, "D"^[reg1 + reg2*$(SZ_BYTES)] is op_format=0x3c; reg1 & reg2 ; subopcode3=0x8 & reg3 {
514 | @if SZ_BITS == "32"
515 |   load32
516 | @elif SZ_BITS == "16"
517 |   load16
518 | @elif SZ_BITS == "8"
519 |   load8
520 | @endif
521 |     (reg3:$(SZ_BYTES), reg1 + reg2*$(SZ_BYTES));
522 | }
523 | 
524 | @if defined(SUPPORT_FUC5P)
525 | #	{ 0x0009003c, 0x000f003f, OP3B, N("st"), T(sz), T(datarralt), REG2, .fmask = F_FUC5P },
526 | :st^$(SZ_SUFFIX) "D"^[reg1 + reg3*$(SZ_BYTES)], reg2 is op_format=0x3c; reg1 & reg2 ; subopcode3=0x9 & reg3 {
527 | @if SZ_BITS == "32"
528 |   store32
529 | @elif SZ_BITS == "16"
530 |   store16
531 | @elif SZ_BITS == "8"
532 |   store8
533 | @endif
534 |     (reg1 + reg3*$(SZ_BYTES), reg2);
535 | }
536 | @endif
537 | 
538 | #	{ 0x000c003c, 0x000f003f, OP3B, N("shlc"), T(sz), REG3, REG1, REG2 },
539 | :shlc^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0xc & reg3 {
540 |   todo_binop(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
541 | }
542 | 
543 | #	{ 0x000d003c, 0x000f003f, OP3B, N("shrc"), T(sz), REG3, REG1, REG2 },
544 | :shrc^$(SZ_SUFFIX) reg3, reg1, reg2 is op_format=0x3c; reg2 & reg1; subopcode3=0xd & reg3 {
545 |   todo_binop(reg3:$(SZ_BYTES), reg1:$(SZ_BYTES), reg2:$(SZ_BYTES));
546 | }
547 | 
548 | #	{ 0x0000003c, 0x0000003f, OP3B, OOPS, T(sz), REG3, REG1, REG2 },
549 | #	
550 | #	{ 0x0000003d, 0x00000f3f, OP2B, N("not"), T(sz), REG1 },
551 | :not^$(SZ_SUFFIX) reg1 is op_format=0x3d; subopcode2=0x0 & reg1 {
552 |   not(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES));
553 | }
554 | 
555 | #	{ 0x0000013d, 0x00000f3f, OP2B, N("neg"), T(sz), REG1 },
556 | :neg^$(SZ_SUFFIX) reg1 is op_format=0x3d; subopcode2=0x1 & reg1 {
557 |   neg(reg1:$(SZ_BYTES), reg1:$(SZ_BYTES));
558 | }
559 | 
560 | #	{ 0x0000023d, 0x00000f3f, OP2B, N("movf"), T(sz), REG1, .fmask = F_FUC0 },
561 | #	{ 0x0000023d, 0x00000f3f, OP2B, N("mov"), T(sz), REG1, .fmask = F_FUC3P },
562 | 
563 | @endif # !ONCE
564 | @ifdef ONCE
565 | 
566 | #	{ 0x0000033d, 0x00000f3f, OP2B, N("hswap"), T(sz), REG1 },
567 | :hswap_b32 reg1 is op_format=0x3D & op_size=2; subopcode2=0x3 & reg1  {
568 |   local tmp = (reg1 & 0xFFFF0000) >> 16;
569 |   tmp = tmp | ((reg1 & 0xFFFF) << 16);
570 |   reg1 = tmp;
571 | 
572 |   setResultFlags(reg1);
573 |   $(O_flag) = 0;
574 | }
575 | :hswap_b16 reg1 is op_format=0x3D & op_size=1; subopcode2=0x3 & reg1  {
576 |   local tmp = reg1 & 0xFFFF0000;
577 |   tmp = tmp | ((reg1 & 0xFF) << 8);
578 |   tmp = tmp | ((reg1 & 0xFF00) >> 8);
579 |   reg1 = tmp;
580 |   setResultFlags(reg1:2);
581 |   $(O_flag) = 0;
582 | 
583 |   # TODO: probably should replace with this, but 32-bit endian swap
584 |   # (hswap_b16, hswap_b32, hswap_b16) looks better with the above.
585 |   #hswap16(reg1:2, reg1:2);
586 | }
587 | :hswap_b8 reg1 is op_format=0x3D & op_size=0; subopcode2=0x3 & reg1  {
588 |   hswap8(reg1:1, reg1:1);
589 | }
590 | 
591 | @endif
592 | @ifndef ONCE
593 | 
594 | # { 0x0000043d, 0x00000f3f, OP2B, N("clear"), T(sz), REG1 },
595 | :clear^$(SZ_SUFFIX) reg1 is op_format=0x3D ; subopcode2=0x4 & reg1  {
596 |   clear(reg1 :$(SZ_BYTES));
597 | }
598 | 
599 | #	{ 0x0000053d, 0x00000f3f, OP2B, N("setf"), T(sz), REG1, .fmask = F_FUC3P },
600 | :setf^$(SZ_SUFFIX) reg1 is op_format=0x3D ; subopcode2=0x5 & reg1  {
601 |   setResultFlags(reg1 :$(SZ_BYTES));
602 |   $(O_flag) = 0;
603 | }
604 | 
605 | #	{ 0x0000003d, 0x0000003f, OP2B, OOPS, T(sz), REG1 },
606 | #
607 | 
608 | @endif # !ONCE
609 | @ifdef ONCE
610 | #	{ 0x0000003e, 0x000000ff, OP4B, N("lbra"), LLBTARG, .fmask = F_FUC4P },
611 | :lbra fimm24st is raw_opcode = 0x3E; fimm24st { # signed?
612 |   goto fimm24st;
613 | } 
614 | 
615 | #	{ 0x0000007e, 0x000000ff, OP4B, N("lcall"), LLCTARG, .fmask = F_FUC4P },
616 | :lcall fimm24st is raw_opcode = 0x7E; fimm24st {
617 |   push32(&:4 inst_next);
618 |   call fimm24st;
619 | } 
620 | 
621 | #	{ 0x000000be, 0x000000ff, OP4B, OOPS, FIMM24, .fmask = F_FUC4P },
622 | #
623 | 
624 | @endif
625 | @ifndef ONCE
626 | 
627 | @if defined(SUPPORT_FUC5P)
628 | #	{ 0x0000003f, 0x0000003f, OP2B, N("ld"), T(sz), REG2, DATAR, .fmask = F_FUC5P },
629 | :ld^$(SZ_SUFFIX) reg2, "D"^[reg1] is op_format=0x3F; reg2 & reg1  {
630 | @if SZ_BITS == "32"
631 |   load32
632 | @elif SZ_BITS == "16"
633 |   load16
634 | @elif SZ_BITS == "8"
635 |   load8
636 | @endif
637 |     (reg2:$(SZ_BYTES), reg1);
638 | }
639 | @endif
640 | 
641 | #
642 | #	{ 0, 0, OOPS, T(sz) },
643 | #};
644 | @endif # !ONCE
645 | 


--------------------------------------------------------------------------------
/data/languages/envydis.sinc:
--------------------------------------------------------------------------------
  1 | # envydis comments:
  2 | # Copyright (C) 2013 Marcin Kościelnicki
  3 | # Copyright (C) 2013 Ben Skeggs
  4 | # Copyright (C) 2013 Martin Peres
  5 | # Copyright (C) 2013 Maarten Lankhorst
  6 | # Copyright (C) 2013 Roy Spliet
  7 | # Copyright (C) 2013 Christoph Bumiller
  8 | # Copyright (C) 2013 Marcin Ślusarz
  9 | # Copyright (C) 2013 Emil Velikov
 10 | # Copyright (C) 2013 Francisco Jerez
 11 | # 
 12 | # Permission is hereby granted, free of charge, to any person obtaining a copy of
 13 | # this software and associated documentation files (the "Software"), to deal in
 14 | # the Software without restriction, including without limitation the rights to
 15 | # use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 16 | # the Software, and to permit persons to whom the Software is furnished to do so, 
 17 | # subject to the following conditions:
 18 | # 
 19 | # The above copyright notice and this permission notice shall be included in all 
 20 | # copies or substantial portions of the Software.
 21 | # 
 22 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
 23 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 24 | # FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 25 | # COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 26 | # IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 27 | # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 28 | ##define F_FUC0	1
 29 | ##define F_FUC3P	2
 30 | ##define F_FUC4P	4
 31 | ##define F_CRYPT	8
 32 | ##define F_FUC5P	0x10
 33 | ##define F_FUCOLD	0x20
 34 | ##define F_FUC6P	0x40
 35 | #
 36 | #/*
 37 | # * Code target fields
 38 | # */
 39 | #
 40 | #static struct rbitfield pcrel16off = { { 16, 16 }, RBF_SIGNED, .pcrel = 1, .wrapok = 1 };
 41 | #static struct rbitfield pcrel8off = { { 16, 8 }, RBF_SIGNED, .pcrel = 1 };
 42 | #static struct rbitfield fpcrel16off = { { 24, 16 }, RBF_SIGNED, .pcrel = 1, .wrapok = 1 };
 43 | #static struct rbitfield fpcrel8off = { { 24, 8 }, RBF_SIGNED, .pcrel = 1 };
 44 | #static struct rbitfield ffpcrel16off = { { 32, 16 }, RBF_SIGNED, .pcrel = 1, .wrapok = 1 };
 45 | #static struct rbitfield ffpcrel8off = { { 32, 8 }, RBF_SIGNED, .pcrel = 1 };
 46 | ##define SBTARG atombtarg, &pcrel8off
 47 | ##define LBTARG atombtarg, &pcrel16off
 48 | ##define SFBTARG atombtarg, &fpcrel8off
 49 | ##define LFBTARG atombtarg, &fpcrel16off
 50 | ##define SFFBTARG atombtarg, &ffpcrel8off
 51 | ##define LFFBTARG atombtarg, &ffpcrel16off
 52 | ##define LABTARG atombtarg, &imm16woff
 53 | ##define SABTARG atombtarg, &imm8off
 54 | ##define LCTARG atomctarg, &imm16woff
 55 | ##define SCTARG atomctarg, &imm8off
 56 | ##define FCTARG atomctarg, &fimm16off
 57 | ##define LLBTARG atombtarg, &fimm24off
 58 | ##define LLCTARG atomctarg, &fimm24off
 59 | #
 60 | #/*
 61 | # * Register fields
 62 | # */
 63 | #
 64 | #static struct sreg sreg_sr[] = {
 65 | #	{ 0, "iv0" },
 66 | #	{ 1, "iv1" },
 67 | #	{ 3, "tv" },
 68 | #	{ 4, "sp" },
 69 | #	{ 5, "pc" },
 70 | #	{ 6, "xcbase" },
 71 | #	{ 7, "xdbase" },
 72 | #	{ 8, "csw" },
 73 | #	{ 9, "cx", .fmask = F_CRYPT },
 74 | #	{ 0xa, "cauth", .fmask = F_CRYPT },
 75 | #	{ 0xb, "xtargets" },
 76 | #	{ 0xc, "tstatus", .fmask = F_FUC3P },
 77 | #	{ -1 },
 78 | #};
 79 | #static struct bitfield reg0_bf = { 0, 4 };
 80 | #static struct bitfield reg1_bf = { 12, 4 };
 81 | #static struct bitfield reg2_bf = { 8, 4 };
 82 | #static struct bitfield reg3_bf = { 20, 4 };
 83 | #static struct bitfield pred1_bf = { 8, 3 };
 84 | #static struct bitfield pred2_bf = { 16, 3 };
 85 | #static struct bitfield creg1_bf = { 16, 3 };
 86 | #static struct bitfield creg2_bf = { 20, 3 };
 87 | #static struct reg reg0_r = { &reg0_bf, "r" };
 88 | #static struct reg reg1_r = { &reg1_bf, "r" };
 89 | #static struct reg reg2_r = { &reg2_bf, "r" };
 90 | #static struct reg reg3_r = { &reg3_bf, "r" };
 91 | #static struct reg pred1_r = { &pred1_bf, "p", .cool = 1 };
 92 | #static struct reg pred2_r = { &pred2_bf, "p", .cool = 1 };
 93 | #static struct reg creg1_r = { &creg1_bf, "c" };
 94 | #static struct reg creg2_r = { &creg2_bf, "c" };
 95 | #static struct reg sreg1_r = { &reg1_bf, "s", .specials = sreg_sr, .always_special = 1 };
 96 | #static struct reg sreg2_r = { &reg2_bf, "s", .specials = sreg_sr, .always_special = 1 };
 97 | #static struct reg sp_r = { 0, "sp", .cool = 1 };
 98 | #static struct reg csw_r = { 0, "csw", .cool = 1 };
 99 | ##define REG0 atomreg, &reg0_r
100 | ##define REG1 atomreg, &reg1_r
101 | ##define REG2 atomreg, &reg2_r
102 | ##define REG3 atomreg, &reg3_r
103 | ##define PRED1 atomreg, &pred1_r
104 | ##define PRED2 atomreg, &pred2_r
105 | ##define CREG1 atomreg, &creg1_r
106 | ##define CREG2 atomreg, &creg2_r
107 | ##define SREG1 atomreg, &sreg1_r
108 | ##define SREG2 atomreg, &sreg2_r
109 | ##define SP atomreg, &sp_r
110 | ##define csw atomreg, &csw_r
111 | #
112 | #/*
113 | # * Immediate fields
114 | # */
115 | #
116 | #static struct rbitfield imm16off = { 16, 16 };
117 | #static struct rbitfield imm8off = { 16, 8 };
118 | #static struct rbitfield imm16soff = { { 16, 16 }, RBF_SIGNED };
119 | #static struct rbitfield imm8soff = { { 16, 8 }, RBF_SIGNED };
120 | #static struct rbitfield imm16woff = { { 16, 16 }, .wrapok = 1 };
121 | #static struct rbitfield imm16hoff = { { 16, 16 }, RBF_UNSIGNED, 16 };
122 | #static struct rbitfield imm8hoff = { { 16, 8 }, RBF_UNSIGNED, 16 };
123 | #static struct rbitfield fimm8soff = { { 8, 8 }, RBF_SIGNED };
124 | #static struct rbitfield fimm16soff = { { 8, 16 }, RBF_SIGNED };
125 | #static struct rbitfield fimm24soff = { { 8, 24 }, RBF_SIGNED };
126 | #static struct rbitfield fimm16off = { 8, 16 };
127 | #static struct rbitfield fimm24off = { 8, 24 };
128 | #static struct rbitfield fimm32off = { 8, 32 };
129 | #static struct bitfield strapoff = { 8, 2 };
130 | #static struct bitfield cimm2off = { 20, 6 };
131 | ##define IMM16 atomrimm, &imm16off
132 | ##define IMM8 atomrimm, &imm8off
133 | ##define IMM16S atomrimm, &imm16soff
134 | ##define IMM8S atomrimm, &imm8soff
135 | ##define IMM16W atomrimm, &imm16woff
136 | ##define IMM16H atomrimm, &imm16hoff
137 | ##define IMM8H atomrimm, &imm8hoff
138 | ##define FIMM8S atomrimm, &fimm8soff
139 | ##define FIMM16S atomrimm, &fimm16soff
140 | ##define FIMM24S atomrimm, &fimm24soff
141 | ##define FIMM24 atomrimm, &fimm24off
142 | ##define FIMM32 atomrimm, &fimm32off
143 | ##define STRAP atomimm, &strapoff
144 | ##define CIMM2 atomimm, &cimm2off
145 | #
146 | #static struct bitfield bitf8bf[] = { { 16, 5 }, { 21, 3 } };
147 | #static struct bitfield bitf16bf[] = { { 16, 5 }, { 21, 5 }, };
148 | ##define BITF8 atombf, bitf8bf
149 | ##define BITF16 atombf, bitf16bf
150 | #
151 | #/*
152 | # * Memory fields
153 | # */
154 | #
155 | #static struct rbitfield off8_bf = { { 16, 8 }, RBF_UNSIGNED, 0 };
156 | #static struct rbitfield off16_bf = { { 16, 8 }, RBF_UNSIGNED, 1 };
157 | #static struct rbitfield off32_bf = { { 16, 8 }, RBF_UNSIGNED, 2 };
158 | #static struct mem datar_m = { "D", 0, &reg1_r };
159 | #static struct mem datari8_m = { "D", 0, &reg1_r, &off8_bf };
160 | #static struct mem datari16_m = { "D", 0, &reg1_r, &off16_bf };
161 | #static struct mem datari32_m = { "D", 0, &reg1_r, &off32_bf };
162 | #static struct mem datarr8_m = { "D", 0, &reg1_r, 0, &reg2_r, 0 };
163 | #static struct mem datarr16_m = { "D", 0, &reg1_r, 0, &reg2_r, 1 };
164 | #static struct mem datarr32_m = { "D", 0, &reg1_r, 0, &reg2_r, 2 };
165 | #static struct mem datarralt8_m = { "D", 0, &reg1_r, 0, &reg3_r, 0 };
166 | #static struct mem datarralt16_m = { "D", 0, &reg1_r, 0, &reg3_r, 1 };
167 | #static struct mem datarralt32_m = { "D", 0, &reg1_r, 0, &reg3_r, 2 };
168 | #static struct mem datasp8_m = { "D", 0, &sp_r, &off8_bf };
169 | #static struct mem datasp16_m = { "D", 0, &sp_r, &off16_bf };
170 | #static struct mem datasp32_m = { "D", 0, &sp_r, &off32_bf };
171 | #static struct mem dataspr8_m = { "D", 0, &sp_r, 0, &reg2_r, 0 };
172 | #static struct mem dataspr16_m = { "D", 0, &sp_r, 0, &reg2_r, 1 };
173 | #static struct mem dataspr32_m = { "D", 0, &sp_r, 0, &reg2_r, 2 };
174 | ##define DATAR atommem, &datar_m
175 | ##define DATARI8 atommem, &datari8_m
176 | ##define DATARI16 atommem, &datari16_m
177 | ##define DATARI32 atommem, &datari32_m
178 | ##define DATARR8 atommem, &datarr8_m
179 | ##define DATARR16 atommem, &datarr16_m
180 | ##define DATARR32 atommem, &datarr32_m
181 | ##define DATARRALT8 atommem, &datarralt8_m
182 | ##define DATARRALT16 atommem, &datarralt16_m
183 | ##define DATARRALT32 atommem, &datarralt32_m
184 | ##define DATA8SP atommem, &datasp8_m
185 | ##define DATA16SP atommem, &datasp16_m
186 | ##define DATA32SP atommem, &datasp32_m
187 | ##define DATA8SPR atommem, &dataspr8_m
188 | ##define DATA16SPR atommem, &dataspr16_m
189 | ##define DATA32SPR atommem, &dataspr32_m
190 | #
191 | #/*
192 | # * IO space
193 | # */
194 | #
195 | #static struct mem ior_m = { "I", 0, &reg1_r };
196 | #static struct mem iorr_m = { "I", 0, &reg1_r, 0, &reg2_r, 2 };
197 | #static struct mem iori_m = { "I", 0, &reg1_r, &off32_bf };
198 | ##define IOR atommem, &ior_m
199 | ##define IORR atommem, &iorr_m
200 | ##define IORI atommem, &iori_m
201 | #
202 | #static struct insn tabp[] = {
203 | #	{ 0x00000000, 0x00001800, PRED1 },
204 | #	{ 0x00000800, 0x00001f00, N("b") },
205 | #	{ 0x00000800, 0x00001f00, N("c") },
206 | #	{ 0x00000900, 0x00001f00, N("o") },
207 | #	{ 0x00000a00, 0x00001f00, N("s") },
208 | #	{ 0x00000b00, 0x00001f00, N("e") },
209 | #	{ 0x00000b00, 0x00001f00, N("z") },
210 | #	{ 0x00000c00, 0x00001f00, N("a") },
211 | #	{ 0x00000d00, 0x00001f00, N("be") },
212 | #	{ 0x00000d00, 0x00001f00, N("na") },
213 | #	{ 0x00000e00, 0x00001f00, ENDMARK },
214 | #	{ 0x00001000, 0x00001800, N("not"), PRED1 },
215 | #	{ 0x00001800, 0x00001f00, N("ae") },
216 | #	{ 0x00001800, 0x00001f00, N("nb") },
217 | #	{ 0x00001800, 0x00001f00, N("nc") },
218 | #	{ 0x00001900, 0x00001f00, N("no") },
219 | #	{ 0x00001a00, 0x00001f00, N("ns") },
220 | #	{ 0x00001b00, 0x00001f00, N("ne") },
221 | #	{ 0x00001b00, 0x00001f00, N("nz") },
222 | #	{ 0x00001c00, 0x00001f00, N("g"), .fmask = F_FUC3P },
223 | #	{ 0x00001d00, 0x00001f00, N("le"), .fmask = F_FUC3P },
224 | #	{ 0x00001e00, 0x00001f00, N("l"), .fmask = F_FUC3P },
225 | #	{ 0x00001f00, 0x00001f00, N("ge"), .fmask = F_FUC3P },
226 | #	{ 0, 0, OOPS },
227 | #};
228 | #
229 | #static struct insn tabfl[] = {
230 | #	{ 0x00000000, 0x00180000, PRED2 },
231 | #	{ 0x00080000, 0x001f0000, N("c") },
232 | #	{ 0x00090000, 0x001f0000, N("o") },
233 | #	{ 0x000a0000, 0x001f0000, N("s") },
234 | #	{ 0x000b0000, 0x001f0000, N("z") },
235 | #	{ 0x00100000, 0x001f0000, N("ie0") },
236 | #	{ 0x00110000, 0x001f0000, N("ie1") },
237 | #	{ 0x00120000, 0x001f0000, N("ie2"), .fmask = F_FUC4P },
238 | #	{ 0x00140000, 0x001f0000, N("is0") },
239 | #	{ 0x00150000, 0x001f0000, N("is1") },
240 | #	{ 0x00160000, 0x001f0000, N("is2"), .fmask = F_FUC4P },
241 | #	{ 0x00180000, 0x001f0000, N("ta") },
242 | #	{ 0x00000000, 0x00000000, OOPS },
243 | #};
244 | #
245 | #F(i, 0, IMM8, IMM16);
246 | #F(is, 0, IMM8S, IMM16S);
247 | #F(ih, 0, IMM8H, IMM16H);
248 | #F(bt, 0, SBTARG, LBTARG);
249 | #F(abt, 0, SABTARG, LABTARG);
250 | #F(ct, 0, SCTARG, LCTARG);
251 | #F(ol0, 0, OP3B, OP4B);
252 | #
253 | 
254 | 
255 | 
256 | #	{ 0, 0, OOPS },
257 | #};
258 | #
259 | #static struct insn tabsz[] = {
260 | #	{ 0x00000000, 0x000000c0, N("b8") },
261 | #	{ 0x00000040, 0x000000c0, N("b16") },
262 | #	{ 0x00000080, 0x000000c0, N("b32") },
263 | #	{ 0, 0, OOPS },
264 | #};
265 | #
266 | #static struct insn tabdatari[] = {
267 | #	{ 0x00000000, 0x000000c0, DATARI8 },
268 | #	{ 0x00000040, 0x000000c0, DATARI16 },
269 | #	{ 0x00000080, 0x000000c0, DATARI32 },
270 | #	{ 0, 0, OOPS },
271 | #};
272 | #
273 | #static struct insn tabdatasp[] = {
274 | #	{ 0x00000000, 0x000000c0, DATA8SP },
275 | #	{ 0x00000040, 0x000000c0, DATA16SP },
276 | #	{ 0x00000080, 0x000000c0, DATA32SP },
277 | #	{ 0, 0, OOPS },
278 | #};
279 | #
280 | #static struct insn tabdatarr[] = {
281 | #	{ 0x00000000, 0x000000c0, DATARR8 },
282 | #	{ 0x00000040, 0x000000c0, DATARR16 },
283 | #	{ 0x00000080, 0x000000c0, DATARR32 },
284 | #	{ 0, 0, OOPS },
285 | #};
286 | #
287 | #static struct insn tabdatarralt[] = {
288 | #	{ 0x00000000, 0x000000c0, DATARRALT8 },
289 | #	{ 0x00000040, 0x000000c0, DATARRALT16 },
290 | #	{ 0x00000080, 0x000000c0, DATARRALT32 },
291 | #	{ 0, 0, OOPS },
292 | #};
293 | #
294 | #static struct insn tabdataspr[] = {
295 | #	{ 0x00000000, 0x000000c0, DATA8SPR },
296 | #	{ 0x00000040, 0x000000c0, DATA16SPR },
297 | #	{ 0x00000080, 0x000000c0, DATA32SPR },
298 | #	{ 0, 0, OOPS },
299 | #};
300 | #
301 | 
302 | #static struct insn tabsi[] = {
303 | # // moved to sized_include.sinc
304 | #}
305 | #
306 | #static struct insn tabm[] = {
307 | #	{ 0x00000000, 0x000000c0, T(si) },
308 | #	{ 0x00000040, 0x000000c0, T(si) },
309 | #	{ 0x00000080, 0x000000c0, T(si) },
310 | #
311 | #	{ 0x000000c0, 0x000000ff, OP3B, N("mulu"), REG2, REG1, IMM8 },
312 | :mulu reg2, reg1, imm8 is raw_opcode=0xc0; reg2 & reg1; imm8 {
313 |   mulu(reg2, reg1, imm8:1);
314 | }
315 | 
316 | #	{ 0x000000c1, 0x000000ff, OP3B, N("muls"), REG2, REG1, IMM8S },
317 | :muls reg2, reg1, imm8s is raw_opcode=0xc1; reg2 & reg1; imm8s {
318 |   muls(reg2, reg1, imm8s:1);
319 | }
320 | 
321 | #	{ 0x000000c2, 0x000000ff, OP3B, N("sext"), REG2, REG1, IMM8 },
322 | :sext reg2, reg1, imm8 is raw_opcode=0xc2; reg2 & reg1; imm8 {
323 |   op_sext(reg2, reg1, imm8);
324 | }
325 | 
326 | #	{ 0x000000c3, 0x000000ff, OP3B, N("extrs"), REG2, REG1, BITF8, .fmask = F_FUC3P },
327 | :extrs reg2, reg1, bitf8_0^":"^suffix is raw_opcode=0xc3; reg2 & reg1; bitf8_0 & bitf8_1 [ suffix=bitf8_0 + bitf8_1; ] {
328 |   # TODO: macro this a lot
329 |   reg2 = (((reg1 >> bitf8_0) & ((1 << (bitf8_1+1)) - 1)) << (32 - (bitf8_1+1))) s>> (32 - (bitf8_1+1));
330 | }
331 | 
332 | #	{ 0x000000c4, 0x000000ff, OP3B, N("and"), REG2, REG1, IMM8 },
333 | :and reg2, reg1, imm8 is raw_opcode=0xc4; reg2 & reg1; imm8 { and(reg2, reg1, imm8); }
334 | 
335 | #	{ 0x000000c5, 0x000000ff, OP3B, N("or"), REG2, REG1, IMM8 },
336 | :or  reg2, reg1, imm8 is raw_opcode=0xc5; reg2 & reg1; imm8 { or(reg2, reg1, imm8); }
337 | 
338 | #	{ 0x000000c6, 0x000000ff, OP3B, N("xor"), REG2, REG1, IMM8 },
339 | :xor reg2, reg1, imm8 is raw_opcode=0xc6; reg2 & reg1; imm8 { xor(reg2, reg1, imm8); }
340 | 
341 | #	{ 0x000000c7, 0x000000ff, OP3B, N("extr"), REG2, REG1, BITF8, .fmask = F_FUC3P },
342 | :extr reg2, reg1, bitf8_0^":"^suffix is raw_opcode=0xc7; reg2 & reg1; bitf8_0 & bitf8_1 [ suffix=bitf8_0 + bitf8_1; ] {
343 |   reg2 = (reg1 >> bitf8_0) & ((1 << bitf8_1) - 1);
344 | }
345 | 
346 | #	{ 0x000000c8, 0x000000ff, OP3B, N("xbit"), REG2, REG1, IMM8 },
347 | :xbit reg2, reg1, imm8 is raw_opcode=0xc8; reg2 & reg1; imm8 {
348 |   xbit(reg2, reg1, imm8);
349 | }
350 | 
351 | #	{ 0x000000cb, 0x000000ff, OP3B, N("ins"), REG2, REG1, BITF8, .fmask = F_FUC3P },
352 | :ins reg2, reg1, bitf8_0^":"^suffix is raw_opcode=0xcb; reg2 & reg1; bitf8_0 & bitf8_1 [ suffix=bitf8_0 + bitf8_1; ] {
353 |   reg2 = todo(reg1, bitf8_0 :4, suffix :4);
354 | }
355 | 
356 | #	{ 0x000000cc, 0x000000ff, OP3B, N("div"), REG2, REG1, IMM8, .fmask = F_FUC3P },
357 | :mod reg2, reg1, imm8 is raw_opcode=0xcc; reg2 & reg1; imm8 {
358 |   reg2 = reg1 / imm8;
359 | }
360 | 
361 | #	{ 0x000000cd, 0x000000ff, OP3B, N("mod"), REG2, REG1, IMM8, .fmask = F_FUC3P },
362 | :mod reg2, reg1, imm8 is raw_opcode=0xcd; reg2 & reg1; imm8 {
363 |   reg2 = reg1 % imm8;
364 | }
365 | 
366 | #	{ 0x000000ce, 0x000000ff, OP3B, U("ce"), REG2, IORI },
367 | :unkce reg2, "I"^[reg1 + offset] is raw_opcode=0xce; reg2 & reg1; imm8 [ offset=imm8 * 4; ] {
368 |   reg2 = unkce_io_read(reg1 + offset);
369 | }
370 | 
371 | #	{ 0x000000cf, 0x000000ff, OP3B, N("iord"), REG2, IORI },
372 | :iord reg2, [reg1 + offset] is raw_opcode=0xcf; reg2 & reg1; imm8 [ offset=imm8 * 4; ] {
373 |   reg2 = io_read(reg1 + offset);
374 | }
375 | 
376 | #	{ 0x000000c0, 0x000000f0, OP3B, OOPS, REG2, REG1, IMM8 },
377 | #
378 | #	{ 0x000000d0, 0x000000ff, OP3B, N("iowr"), IORI, REG2, .fmask = F_FUCOLD },
379 | #	{ 0x000000d1, 0x000000ff, OP3B, N("iowrs"), IORI, REG2, .fmask = F_FUC3P | F_FUCOLD },
380 | #	{ 0x000000d0, 0x000000f0, OP3B, OOPS, REG1, REG2, IMM8, .fmask = F_FUCOLD },
381 | #
382 | @if defined(SUPPORT_FUC5P)
383 | #	{ 0x000000d0, 0x000000f0, OP5B, N("mov"), REG0, FIMM32, .fmask = F_FUC5P },
384 | :mov reg0, fimm32 is raw_opcode_hi=0xd & reg0; fimm32 {
385 |  reg0 = fimm32;
386 | }
387 | @endif
388 | 
389 | #
390 | #	{ 0x000000e0, 0x000000ff, OP4B, N("mulu"), REG2, REG1, IMM16 },
391 | :mulu reg2, reg1, imm16 is raw_opcode=0xe0; reg2 & reg1; imm16 {
392 |   mulu(reg2, reg1, imm16:2);
393 | }
394 | 
395 | 
396 | #	{ 0x000000e1, 0x000000ff, OP4B, N("muls"), REG2, REG1, IMM16S },
397 | :muls reg2, reg1, imm16s is raw_opcode=0xe1; reg2 & reg1; imm16s {
398 |   muls(reg2, reg1, imm16s:2);
399 | }
400 | 
401 | 
402 | #	{ 0x000000e3, 0x000000ff, OP4B, N("extrs"), REG2, REG1, BITF16, .fmask = F_FUC3P },
403 | :extrs reg2, reg1, bitf16_0^":"^suffix is raw_opcode=0xe3; reg2 & reg1; bitf16_0 & bitf16_1 [ suffix=bitf16_0 + bitf16_1; ] {
404 |   reg2 = todo(reg1, bitf16_0 :4, suffix :4);
405 | }
406 | 
407 | #	{ 0x000000e4, 0x000000ff, OP4B, N("and"), REG2, REG1, IMM16 },
408 | :and reg2, reg1, imm16 is raw_opcode=0xe4; reg2 & reg1; imm16 { and(reg2, reg1, imm16); }
409 | 
410 | #	{ 0x000000e5, 0x000000ff, OP4B, N("or"), REG2, REG1, IMM16 },
411 | :or  reg2, reg1, imm16 is raw_opcode=0xe5; reg2 & reg1; imm16 { or(reg2, reg1, imm16); }
412 | 
413 | #	{ 0x000000e6, 0x000000ff, OP4B, N("xor"), REG2, REG1, IMM16 },
414 | :xor reg2, reg1, imm16 is raw_opcode=0xe6; reg2 & reg1; imm16 { xor(reg2, reg1, imm16); }
415 | 
416 | #	{ 0x000000e7, 0x000000ff, OP4B, N("extr"), REG2, REG1, BITF16, .fmask = F_FUC3P },
417 | :extr reg2, reg1, bitf16_0^":"^suffix is raw_opcode=0xe7; reg2 & reg1; bitf16_0 & bitf16_1 [ suffix=bitf16_0 + bitf16_1; ] {
418 |   reg2 = (reg1 >> bitf16_0) & ((1 << (bitf16_1 + 1)) - 1);
419 | }
420 | 
421 | 
422 | #	{ 0x000000eb, 0x000000ff, OP4B, N("ins"), REG2, REG1, BITF16, .fmask = F_FUC3P },
423 | :ins reg2, reg1, bitf16_0^":"^suffix is raw_opcode=0xeb; reg2 & reg1; bitf16_0 & bitf16_1 [ suffix=bitf16_0 + bitf16_1; ] {
424 |   reg2 = todo(reg1, bitf16_0 :4, suffix :4);
425 | }
426 | 
427 | #	{ 0x000000ec, 0x000000ff, OP4B, N("div"), REG2, REG1, IMM16, .fmask = F_FUC3P },
428 | :div reg2, reg1, imm16 is raw_opcode=0xec; reg2 & reg1; imm16 { reg2 = reg1 / imm16; }
429 | 
430 | #	{ 0x000000ed, 0x000000ff, OP4B, N("mod"), REG2, REG1, IMM16, .fmask = F_FUC3P },
431 | :mod reg2, reg1, imm16 is raw_opcode=0xed; reg2 & reg1; imm16 { reg2 = reg1 % imm16; }
432 | 
433 | #	{ 0x000000e0, 0x000000f0, OP4B, OOPS, REG2, REG1, IMM16 },
434 | #
435 | #	{ 0x000000f0, 0x00000ffe, T(ol0), N("mulu"), REG1, T(i) },
436 | :mulu reg1, imm8 is raw_opcode=0xf0; subopcode2=0x0 & reg1; imm8  {
437 |   mulu(reg1, reg1, imm8:1);
438 | }
439 | :mulu reg1, imm16 is raw_opcode=0xf1; subopcode2=0x0 & reg1; imm16  {
440 |   mulu(reg1, reg1, imm16:2);
441 | }
442 | 
443 | 
444 | #	{ 0x000001f0, 0x00000ffe, T(ol0), N("muls"), REG1, T(is) },
445 | :muls reg1, imm8s is raw_opcode=0xf0; subopcode2=0x1 & reg1; imm8s {
446 |   muls(reg1, reg1, imm8s:1);
447 | }
448 | :muls reg1, imm16s is raw_opcode=0xf1; subopcode2=0x1 & reg1; imm16s {
449 |   muls(reg1, reg1, imm16s:2);
450 | }
451 | 
452 | #	{ 0x000002f0, 0x00000fff, T(ol0), N("sext"), REG1, T(i) },
453 | :sext reg1, imm8 is raw_opcode=0xf0; subopcode2=0x2 & reg1; imm8 {
454 |   todo();
455 | }
456 | 
457 | #	{ 0x000003f0, 0x00000ffe, T(ol0), N("sethi"), REG1, T(ih) },
458 | :sethi reg1, immvalue is raw_opcode=0xf0; subopcode2=0x3 & reg1; imm8 [ immvalue=imm8 << 16; ] {
459 |   reg1 = (reg1 & 0xFFFF) | immvalue;
460 | }
461 | :sethi reg1, immvalue is raw_opcode=0xf1; subopcode2=0x3 & reg1; imm16 [ immvalue=imm16 << 16; ] {
462 |   reg1 = (reg1 & 0xFFFF) | immvalue;
463 | }
464 | 
465 | #	{ 0x000004f0, 0x00000ffe, T(ol0), N("and"), REG1, T(i) },
466 | :and reg1, imm8 is raw_opcode=0xf0; subopcode2=0x4 & reg1; imm8 { and(reg1, reg1, imm8); }
467 | :and reg1, imm16 is raw_opcode=0xf1; subopcode2=0x4 & reg1; imm16 { and(reg1, reg1, imm16); }
468 | 
469 | #	{ 0x000005f0, 0x00000ffe, T(ol0), N("or"), REG1, T(i) },
470 | :or  reg1, imm8 is raw_opcode=0xf0; subopcode2=0x5 & reg1; imm8 { or(reg1, reg1, imm8); }
471 | :or  reg1, imm16 is raw_opcode=0xf1; subopcode2=0x5 & reg1; imm16 { or(reg1, reg1, imm16); }
472 | 
473 | #	{ 0x000006f0, 0x00000ffe, T(ol0), N("xor"), REG1, T(i) },
474 | :xor reg1, imm8 is raw_opcode=0xf0; subopcode2=0x6 & reg1; imm8 { xor(reg1, reg1, imm8); }
475 | :xor reg1, imm16 is raw_opcode=0xf1; subopcode2=0x6 & reg1; imm16 { xor(reg1, reg1, imm16); }
476 | 
477 | #	{ 0x000007f0, 0x00000ffe, T(ol0), N("mov"), REG1, T(is), .fmask = F_FUCOLD },
478 | @if defined(SUPPORT_FUCOLD)
479 | :mov reg1, imm8s is raw_opcode=0xf0; subopcode2=0x7 & reg1; imm8s {
480 |   mov(reg1, imm8s);
481 | }
482 | :mov reg1, imm16s is raw_opcode=0xf1; subopcode2=0x7 & reg1; imm16s {
483 |   mov(reg1, imm16s);
484 | }
485 | @endif
486 | 
487 | # shadowed by previous (?)
488 | #	{ 0x000007f1, 0x00000fff, T(ol0), N("movw"), REG1, IMM16W, .fmask = F_FUCOLD },
489 | 
490 | 
491 | #	{ 0x000009f0, 0x00000fff, T(ol0), N("bset"), REG1, T(i) },
492 | :bset reg1, imm8 is raw_opcode=0xf0; subopcode2=0x9 & reg1; imm8 {
493 |   bset(reg1, imm8);
494 | }
495 | 
496 | #	{ 0x00000af0, 0x00000fff, T(ol0), N("bclr"), REG1, T(i) },
497 | :bclr reg1, imm8 is raw_opcode=0xf0; subopcode2=0xa & reg1; imm8 {
498 |   bclr(reg1, imm8);
499 | }
500 | 
501 | #	{ 0x00000bf0, 0x00000fff, T(ol0), N("btgl"), REG1, T(i) },
502 | :btgl reg1, imm8 is raw_opcode=0xf0; subopcode2=0xb & reg1; imm8 {
503 |   btgl(reg1, imm8);
504 | }
505 | 
506 | #	{ 0x00000cf0, 0x00000fff, T(ol0), N("xbit"), REG1, csw, T(fl) },
507 | :xbit reg1, csw, imm8 is raw_opcode=0xf0; subopcode2=0xC & reg1 & csw; imm8 {
508 |   # TODO: display flag name
509 |   packflags(csw);
510 |   xbit(reg1, csw, imm8);
511 |   unpackflags(csw);
512 | }
513 | 
514 | #	{ 0x000000f0, 0x000000fe, T(ol0), OOPS, REG1, T(i) },
515 | #
516 | #	{ 0x000008f2, 0x00000fff, OP3B, N("setp"), T(fl), REG1 },
517 | :setp imm8, reg1 is raw_opcode=0xf2; subopcode2=0x8 & reg1; imm8 {
518 |   csw = csw & ~(1 << imm8);
519 |   csw = csw | ((reg1 & 1) << imm8);
520 | }
521 | 
522 | #	{ 0x00000cf2, 0x00000fff, OP3B, OOPS, REG1, .fmask = F_CRYPT },
523 | #	{ 0x000000f2, 0x000000ff, OP3B, OOPS, REG1, IMM8 },
524 | #
525 | @if defined(SUPPORT_FUC5P)
526 | #	{ 0x000000f3, 0x000000ff, OP3B, N("call"), FCTARG, .fmask = F_FUC5P },
527 | :call addr16 is raw_opcode=0xf3; addr16 {
528 |   push32(&:4 inst_next);
529 |   call addr16;
530 | }
531 | @endif
532 | 
533 | #
534 | #	{ 0x000000f4, 0x000020fe, T(ol0), N("bra"), T(p), T(bt) },
535 | #	{ 0x000020f4, 0x00003ffe, T(ol0), N("bra"), T(abt), ENDMARK },
536 | :bra addr16 is raw_opcode=0xf5; subopcodeb1_0_7=0x20; addr16 {
537 |   goto addr16;
538 | }
539 | 
540 | #	{ 0x000021f4, 0x00003fff, T(ol0), N("call"), T(ct) },
541 | :call addr8 is raw_opcode=0xf4; subopcodeb1_0_7=0x21; addr8 {
542 |   push32(&:4 inst_next);
543 |   call addr8;
544 | }
545 | 
546 | #	{ 0x000021f5, 0x00003fff, T(ol0), N("call"), T(ct), .fmask = F_FUCOLD },
547 | @if defined(SUPPORT_FUCOLD)
548 | :call addr16 is raw_opcode=0xf5; subopcodeb1_0_7=0x21; addr16 {
549 |   push32(&:4 inst_next);
550 |   call addr16;
551 | }
552 | @endif
553 | 
554 | #	{ 0x000028f4, 0x00003fff, T(ol0), N("sleep"), T(fl) }, /* sleeps while given flag is true */
555 | :sleep imm8 is raw_opcode=0xf4 ; subopcodeb1_0_7=0x28 ; imm8 {
556 |   # TODO: display flag name
557 |   todo(imm8 :1);
558 | }
559 | 
560 | #	{ 0x000030f4, 0x00003ffe, T(ol0), N("add"), SP, T(is) },
561 | :add sp, imm8s is raw_opcode=0xf4 ; subopcodeb1_0_7=0x30 ; imm8s & sp {
562 |   add(sp, sp, imm8s);
563 | }
564 | :add sp, imm16s is raw_opcode=0xf5 ; subopcodeb1_0_7=0x30 ; imm16s & sp {
565 |   add(sp, sp, imm16s);
566 | }
567 | 
568 | #	{ 0x000031f4, 0x00003fff, T(ol0), N("bset"), csw, T(fl) },
569 | :bset csw, "ie0" is raw_opcode=0xf4 ; subopcodeb1_0_7=0x31 & csw ; imm8=0x10 {
570 |   __set_flag_ie0();
571 |   csw[0x10, 1] = 1;
572 | }
573 | :bset csw, "ie1" is raw_opcode=0xf4 ; subopcodeb1_0_7=0x31 & csw ; imm8=0x11 {
574 |   __set_flag_ie1();
575 |   csw[0x11, 1] = 1;
576 | }
577 | :bset csw, imm8 is raw_opcode=0xf4 ; subopcodeb1_0_7=0x31 & csw ; imm8 {
578 |   # TODO: display flag name
579 |   packflags(csw);
580 |   bset(csw, imm8);
581 |   unpackflags(csw);
582 | }
583 | 
584 | #	{ 0x000032f4, 0x00003fff, T(ol0), N("bclr"), csw, T(fl) },
585 | :bclr csw, "ie0" is raw_opcode=0xf4 ; subopcodeb1_0_7=0x32 & csw ; imm8=0x10 {
586 |   __clear_flag_ie0();
587 |   csw[0x10, 1] = 0;
588 | }
589 | :bclr csw, "ie1" is raw_opcode=0xf4 ; subopcodeb1_0_7=0x32 & csw ; imm8=0x11 {
590 |   __clear_flag_ie1();
591 |   csw[0x11, 1] = 0;
592 | }
593 | :bclr csw, "ie2" is raw_opcode=0xf4 ; subopcodeb1_0_7=0x32 & csw ; imm8=0x12 {
594 |   __clear_flag_ie2();
595 |   csw[0x12, 1] = 0;
596 | }
597 | 
598 | :bclr csw, imm8 is raw_opcode=0xf4 ; subopcodeb1_0_7=0x32 & csw ; imm8 {
599 |   # TODO: display flag name
600 |   packflags(csw);
601 |   bclr(csw, imm8);
602 |   unpackflags(csw);
603 | }
604 | 
605 | #	{ 0x000033f4, 0x00003fff, T(ol0), N("btgl"), csw, T(fl) },
606 | :btgl csw, imm8 is raw_opcode=0xf4 ; subopcodeb1_0_7=0x33 & csw ; imm8 {
607 |   # TODO: display flag name
608 |   packflags(csw);
609 |   btgl(csw, imm8);
610 |   unpackflags(csw);
611 | }
612 | 
613 | #	{ 0x00003cf4, 0x00003fff, T(ol0), N("cxset"), IMM8, .fmask = F_CRYPT },
614 | :cxset imm8 is raw_opcode=0xf4 ; subopcodeb1_0_7=0x3c ; imm8 {
615 |   cxset(imm8 :1);
616 | }
617 | 
618 | #	{ 0x00003cf5, 0x00003fff, T(ol0), T(cocmd), .fmask = F_CRYPT },
619 | #	{ 0x000000f4, 0x000000fe, T(ol0), OOPS, T(i) },
620 | #
621 | @if defined(SUPPORT_FUC5P)
622 | #	{ 0x000000f6, 0x000000ff, OP3B, N("iowr"), IORI, REG2, .fmask = F_FUC5P },
623 | :iowr [reg1^"+"^offset], reg2 is raw_opcode=0xf6; reg2 & reg1; imm8 [ offset=imm8 * 4; ] {
624 |   io_write(reg1 + offset, reg2);
625 | }
626 | 
627 | #	{ 0x000000f7, 0x000000ff, OP3B, N("iowrs"), IORI, REG2, .fmask = F_FUC5P },
628 | :iowrs [reg1^"+"^offset], reg2 is raw_opcode=0xf7; reg2 & reg1; imm8 [ offset=imm8 * 4; ] {
629 |   io_write_sync(reg1+offset, reg2);
630 | }
631 | @endif
632 | 
633 | #
634 | #	{ 0x000000f8, 0x00000fff, OP2B, N("ret"), ENDMARK },
635 | :ret is raw_opcode=0xf8; subopcode2=0x0 {
636 |   ret();
637 | }
638 | 
639 | #	{ 0x000001f8, 0x00000fff, OP2B, N("iret"), ENDMARK },
640 | :iret is raw_opcode=0xf8; subopcode2=0x1 {
641 |   todo();
642 |   goto inst_start;
643 | }
644 | 
645 | #	{ 0x000002f8, 0x00000fff, OP2B, N("exit"), ENDMARK },
646 | :exit is raw_opcode=0xf8; subopcode2=0x2 {
647 |   exit();
648 | #<spin>
649 |   goto inst_start;
650 | }
651 | 
652 | #	{ 0x000003f8, 0x00000fff, OP2B, N("xdwait") },
653 | :xdwait is raw_opcode=0xf8; subopcode2=0x3 {
654 |   xdwait();
655 | }
656 | 
657 | #	{ 0x000006f8, 0x00000fff, OP2B, U("f8/6") },
658 | :unk_f8_6 is raw_opcode=0xf8; subopcode2=0x6 {
659 |   todo();
660 | }
661 | 
662 | #	{ 0x000007f8, 0x00000fff, OP2B, N("xcwait") },
663 | :xcwait is raw_opcode=0xf8; subopcode2=0x7 {
664 |   xcwait();
665 | }
666 | 
667 | #	{ 0x000008f8, 0x00000cff, OP2B, N("trap"), STRAP },
668 | #	{ 0x000000f8, 0x000000ff, OP2B, OOPS },
669 | #
670 | #	{ 0x000000f9, 0x00000fff, OP2B, N("push"), REG1 },
671 | :push reg1 is raw_opcode=0xf9; subopcode2=0x0 & reg1 {
672 |   push32(reg1);
673 | }
674 | 
675 | #	{ 0x000001f9, 0x00000fff, OP2B, N("add"), SP, REG1 },
676 | @if defined(SUPPORT_FUC5P)
677 | #	/* Display these in a better way, perhaps? */
678 | #	{ 0x000002f9, 0x00000fff, OP2B, N("mpush"), REG1, .fmask = F_FUC5P },
679 | :mpush reg1 is raw_opcode=0xf9; subopcode2=0x2 & reg1 {
680 |   # TODO: I'm guessing if reg1 == 3 it pushes r0, r1, r2, and r3, etc.
681 |   # need to verify and implement somehow.
682 |   sp = sp - &reg1; # TODO: remove this horrible hack
683 |   push32(reg1);
684 | }
685 | @endif
686 | 
687 | #	{ 0x000004f9, 0x00000fff, OP2B, N("bra"), REG1 },
688 | :bra reg1 is raw_opcode=0xf9; subopcode2=0x4 & reg1 {
689 |   goto [reg1];
690 | }
691 | 
692 | #	{ 0x000005f9, 0x00000fff, OP2B, N("call"), REG1 },
693 | :call reg1 is raw_opcode=0xf9; subopcode2=0x5 & reg1 {
694 |   push32(&:4 inst_next);
695 |   call [reg1];
696 | }
697 | 
698 | #	{ 0x000008f9, 0x00000fff, OP2B, N("itlb"), REG1, .fmask = F_FUC3P },
699 | :itlb reg1 is raw_opcode=0xf9; subopcode2=0x8 & reg1 {
700 |   todo(reg1);
701 | }
702 | 
703 | #	{ 0x000009f9, 0x00000fff, OP2B, N("bset"), csw, REG1 },
704 | :bset csw, reg1 is raw_opcode=0xf9; subopcode2=0x9 & reg1 & csw {
705 |   packflags(csw);
706 |   bset(csw, (reg1 & 0x1F));
707 |   unpackflags(csw);
708 | }
709 | 
710 | #	{ 0x00000af9, 0x00000fff, OP2B, N("bclr"), csw, REG1 },
711 | :bclr csw, reg1 is raw_opcode=0xf9; subopcode2=0xa & reg1 & csw {
712 |   packflags(csw);
713 |   bclr(csw, (reg1 & 0x1F));
714 |   unpackflags(csw);
715 | }
716 | 
717 | #	{ 0x00000bf9, 0x00000fff, OP2B, N("btgl"), csw, REG1 },
718 | :btgl csw, reg1 is raw_opcode=0xf9; subopcode2=0xb & reg1 & csw {
719 |   packflags(csw);
720 |   btgl(csw, (reg1 & 0x1F));
721 |   unpackflags(csw);
722 | }
723 | 
724 | #	{ 0x000000f9, 0x000000ff, OP2B, OOPS, REG1 },
725 | #
726 | #	{ 0x000000fa, 0x000f00ff, OP3B, N("iowr"), IOR, REG2 },
727 | :iowr "I"^[reg1], reg2 is raw_opcode=0xfa; reg2 & reg1; subopcode3=0 {
728 |   io_write(reg1, reg2);
729 | }
730 | 
731 | #	{ 0x000100fa, 0x000f00ff, OP3B, N("iowrs"), IOR, REG2, .fmask = F_FUC3P },
732 | :iowrs "I"^[reg1], reg2 is raw_opcode=0xfa; reg2 & reg1; subopcode3=1 {
733 |   io_write_sync(reg1, reg2);
734 | }
735 | 
736 | #	{ 0x000400fa, 0x000f00ff, OP3B, N("xcld"), REG1, REG2 },
737 | :xcld reg1, reg2 is raw_opcode=0xFA; reg2 & reg1; subopcode3=0x4 {
738 |   xcld(reg1, reg2);
739 | }
740 | 
741 | #	{ 0x000500fa, 0x000f00ff, OP3B, N("xdld"), REG1, REG2 },
742 | :xdld reg1, reg2 is raw_opcode=0xFA; reg2 & reg1; subopcode3=0x5 {
743 |   xdld(reg1, reg2);
744 | }
745 | 
746 | #	{ 0x000600fa, 0x000f00ff, OP3B, N("xdst"), REG1, REG2 },
747 | :xdst reg1, reg2 is raw_opcode=0xFA; reg2 & reg1; subopcode3=0x6 {
748 |   xdst(reg1, reg2);
749 | }
750 | 
751 | #	{ 0x000800fa, 0x000f00ff, OP3B, N("setp"), REG2, REG1 },
752 | :setp reg2, reg1 is raw_opcode=0xFA; reg2 & reg1; subopcode3=0x8 {
753 |   packflags(csw);
754 |   local shift = reg1 & 0x1F;
755 |   csw = (csw & ~(1 << shift)) | ((reg2 & 1) << shift);
756 |   unpackflags(csw);
757 | }
758 | 
759 | #	{ 0x000000fa, 0x000000ff, OP3B, OOPS, REG1, REG2 },
760 | #
761 | #	/* Display these in a better way, perhaps? */
762 | @if defined(SUPPORT_FUC5P)
763 | #	{ 0x000000fb, 0x000007ff, OP2B, N("mpop"), REG1, .fmask = F_FUC5P },
764 | :mpop reg1 is raw_opcode=0xFB; subopcodeb1_0_2=0 & reg1 {
765 |   # TODO: I'm guessing if reg1 == 3 it pops r0, r1, r2, and r3, etc.
766 |   # need to verify and implement somehow.
767 |   pop32(reg1);
768 |   sp = sp + &reg1; # TODO: remove this horrible hack
769 | }
770 | 
771 | #	{ 0x000001fb, 0x000007ff, OP2B, N("mpopret"), REG1, ENDMARK, .fmask = F_FUC5P },
772 | :mpopret reg1 is raw_opcode=0xFB; subopcodeb1_0_2=1 & reg1 {
773 |   # TODO: see mpop
774 |   pop32(reg1);
775 |   sp = sp + &reg1; # TODO: remove this horrible hack
776 |   ret();
777 | }
778 | 
779 | #	{ 0x000002fb, 0x000007ff, OP4B, N("mpopadd"), REG1, IMM16S, .fmask = F_FUC5P },
780 | #	{ 0x000003fb, 0x000007ff, OP4B, N("mpopaddret"), REG1, IMM16S, ENDMARK, .fmask = F_FUC5P },
781 | :mpopaddret reg1, imm16s is raw_opcode=0xFB; subopcodeb1_0_2=3 & reg1 ; imm16s {
782 |   # TODO: see mpop
783 |   pop32(reg1);
784 |   sp = sp + &reg1; # TODO: remove this horrible hack
785 |   sp = sp + imm16s;
786 |   ret();
787 | }
788 | 
789 | #	{ 0x000004fb, 0x000007ff, OP3B, N("mpopadd"), REG1, IMM8S, .fmask = F_FUC5P },
790 | :mpopaddret reg1, imm8s is raw_opcode=0xFB; subopcodeb1_0_2=4 & reg1 ; imm8s {
791 |   # TODO: see mpop
792 |   pop32(reg1);
793 |   sp = sp + &reg1; # TODO: remove this horrible hack
794 |   sp = sp + imm8s;
795 | }
796 | 
797 | #	{ 0x000005fb, 0x000007ff, OP3B, N("mpopaddret"), REG1, IMM8S, ENDMARK, .fmask = F_FUC5P },
798 | :mpopaddret reg1, imm8s is raw_opcode=0xFB; subopcodeb1_0_2=5 & reg1 ; imm8s {
799 |   # TODO: see mpop
800 |   pop32(reg1);
801 |   sp = sp + &reg1; # TODO: remove this horrible hack
802 |   sp = sp + imm8s;
803 |   ret();
804 | }
805 | @endif
806 | 
807 | #
808 | #	{ 0x000000fc, 0x00000fff, OP2B, N("pop"), REG1 },
809 | :pop reg1 is raw_opcode=0xfc; subopcode2=0x0 & reg1 {
810 |   pop32(reg1);
811 | }
812 | 
813 | #	{ 0x000000fc, 0x000000ff, OP2B, OOPS, REG1 },
814 | #
815 | #	{ 0x000000fd, 0x000f00ff, OP3B, N("mulu"), REG1, REG2 },
816 | :mulu reg1, reg2 is raw_opcode=0xFD; reg2 & reg1; subopcode3=0x0 {
817 |   reg1 = todo(reg1, reg2);
818 | }
819 | 
820 | #	{ 0x000100fd, 0x000f00ff, OP3B, N("muls"), REG1, REG2 },
821 | :muls reg1, reg2 is raw_opcode=0xFD; reg2 & reg1; subopcode3=0x1 {
822 |   reg1 = sext(reg1 :2) * sext(reg2 :2);
823 | }
824 | 
825 | #	{ 0x000200fd, 0x000f00ff, OP3B, N("sext"), REG1, REG2 },
826 | #	{ 0x000400fd, 0x000f00ff, OP3B, N("and"), REG1, REG2 },
827 | :and reg1, reg2 is raw_opcode=0xFD; reg2 & reg1; subopcode3=0x4 {
828 |   and(reg1, reg1, reg2);
829 | }
830 | 
831 | #	{ 0x000500fd, 0x000f00ff, OP3B, N("or"), REG1, REG2 },
832 | :or reg1, reg2 is raw_opcode=0xFD; reg2 & reg1; subopcode3=0x5 {
833 |   or(reg1, reg1, reg2);
834 | }
835 | 
836 | #	{ 0x000600fd, 0x000f00ff, OP3B, N("xor"), REG1, REG2 },
837 | :xor reg1, reg2 is raw_opcode=0xFD; reg2 & reg1; subopcode3=0x6 {
838 |   xor(reg1, reg1, reg2);
839 | }
840 | 
841 | #	{ 0x000900fd, 0x000f00ff, OP3B, N("bset"), REG1, REG2 },
842 | :bset reg1, reg2 is raw_opcode=0xFD; reg2 & reg1; subopcode3=0x9 {
843 |   bset(reg1, (reg2 & 0x1F));
844 | }
845 | 
846 | #	{ 0x000a00fd, 0x000f00ff, OP3B, N("bclr"), REG1, REG2 },
847 | :bclr reg1, reg2 is raw_opcode=0xFD; reg2 & reg1; subopcode3=0xa {
848 |   bclr(reg1, (reg2 & 0x1F));
849 | }
850 | 
851 | #	{ 0x000b00fd, 0x000f00ff, OP3B, N("btgl"), REG1, REG2 },
852 | :btgl reg1, reg2 is raw_opcode=0xFD; reg2 & reg1; subopcode3=0xd {
853 |   btgl(reg1, (reg2 & 0x1F));
854 | }
855 | #	{ 0x000000fd, 0x000000ff, OP3B, OOPS, REG1, REG2 },
856 | #
857 | #	{ 0x000000fe, 0x000f00ff, OP3B, N("mov"), SREG2, REG1 },
858 | :mov sreg2, reg1 is raw_opcode=0xfe; reg1 & sreg2; subopcode3=0x0 {
859 |   sreg2 = reg1;
860 |   # TODO: unpack csw
861 | }
862 | 
863 | #	{ 0x000100fe, 0x000f00ff, OP3B, N("mov"), REG2, SREG1 },
864 | :mov reg2, sreg1 is raw_opcode=0xfe; sreg1 & reg2; subopcode3=0x1 {
865 |   # TODO: pack csw
866 |   reg2 = sreg1;
867 | }
868 | 
869 | #	{ 0x000200fe, 0x000f00ff, OP3B, N("ptlb"), REG2, REG1, .fmask = F_FUC3P },
870 | :vtlb reg2, reg1 is raw_opcode=0xfe; reg2 & reg1; subopcode3=0x2 {
871 |   reg2 = ptlb(reg1);
872 | }
873 | 
874 | #	{ 0x000300fe, 0x000f00ff, OP3B, N("vtlb"), REG2, REG1, .fmask = F_FUC3P },
875 | :vtlb reg2, reg1 is raw_opcode=0xfe; reg2 & reg1; subopcode3=0x3 {
876 |   reg2 = vtlb(reg1);
877 | }
878 | 
879 | #	{ 0x000c00fe, 0x000f00ff, OP3B, N("xbit"), REG2, csw, REG1 },
880 | :xbit reg2, csw, reg1 is raw_opcode=0xfe; reg2 & reg1 & csw; subopcode3=0xc {
881 |   packflags(csw);
882 |   xbit(reg2, csw, reg1);
883 |   unpackflags(csw);
884 | }
885 | 
886 | #	{ 0x000000fe, 0x000000ff, OP3B, OOPS, REG2, REG1 },
887 | #
888 | #	{ 0x000000ff, 0x000f00ff, OP3B, N("mulu"), REG3, REG1, REG2 },
889 | :mulu reg3, reg1, reg2 is raw_opcode=0xff; reg2 & reg1; subopcode3=0x0 & reg3 {
890 |   reg3 = zext(reg1 :2) * zext(reg2 :2);
891 | }
892 | 
893 | #	{ 0x000100ff, 0x000f00ff, OP3B, N("muls"), REG3, REG1, REG2 },
894 | :muls reg3, reg1, reg2 is raw_opcode=0xff; reg2 & reg1; subopcode3=0x1 & reg3 {
895 |   reg3 = sext(reg1 :2) * sext(reg2 :2);
896 |   #reg3 = todo(reg1, reg2);
897 | }
898 | 
899 | #	{ 0x000200ff, 0x000f00ff, OP3B, N("sext"), REG3, REG1, REG2 },
900 | #	{ 0x000300ff, 0x000f00ff, OP3B, N("extrs"), REG3, REG1, REG2, .fmask = F_FUC3P },
901 | #	{ 0x000400ff, 0x000f00ff, OP3B, N("and"), REG3, REG1, REG2 },
902 | :and reg3, reg1, reg2 is raw_opcode=0xff; reg2 & reg1; subopcode3=0x4 & reg3 {
903 |   and(reg3, reg1, reg2);
904 | }
905 | 
906 | #	{ 0x000500ff, 0x000f00ff, OP3B, N("or"), REG3, REG1, REG2 },
907 | :or reg3, reg1, reg2 is raw_opcode=0xff; reg2 & reg1; subopcode3=0x5 & reg3 {
908 |   or(reg3, reg1, reg2);
909 | }
910 | 
911 | #	{ 0x000600ff, 0x000f00ff, OP3B, N("xor"), REG3, REG1, REG2 },
912 | :xor reg3, reg1, reg2 is raw_opcode=0xff; reg2 & reg1; subopcode3=0x6 & reg3 {
913 |   xor(reg3, reg1, reg2);
914 | }
915 | 
916 | #	{ 0x000700ff, 0x000f00ff, OP3B, N("extr"), REG3, REG1, REG2, .fmask = F_FUC3P },
917 | #	{ 0x000800ff, 0x000f00ff, OP3B, N("xbit"), REG3, REG1, REG2 },
918 | :xbit reg3, reg1, reg2 is raw_opcode=0xff; reg2 & reg1; subopcode3=0x8 & reg3 {
919 |   xbit(reg3, reg1, reg2);
920 | }
921 | 
922 | #	{ 0x000c00ff, 0x000f00ff, OP3B, N("div"), REG3, REG1, REG2, .fmask = F_FUC3P },
923 | :div reg3, reg1, reg2 is raw_opcode=0xff; reg2 & reg1; subopcode3=0xc & reg3 {
924 |   reg3 = reg1 / reg2;
925 | }
926 | 
927 | #	{ 0x000d00ff, 0x000f00ff, OP3B, N("mod"), REG3, REG1, REG2, .fmask = F_FUC3P },
928 | :mod reg3, reg1, reg2 is raw_opcode=0xff; reg2 & reg1; subopcode3=0xd & reg3 {
929 |   reg3 = reg1 % reg2;
930 | }
931 | 
932 | #	{ 0x000e00ff, 0x000f00ff, OP3B, U("ff/e"), REG3, IORR },
933 | #	{ 0x000f00ff, 0x000f00ff, OP3B, N("iord"), REG3, IORR },
934 | 
935 | :iord reg3, "I"^[reg1 + reg2*4] is raw_opcode=0xff; reg2 & reg1; subopcode3=0xF & reg3 {
936 |   reg3 = io_read(reg1 + reg2*4);
937 | }
938 | 
939 | 
940 | 
941 | #	{ 0x000000ff, 0x000000ff, OP3B, OOPS, REG3, REG1, REG2 },
942 | #
943 | #	{ 0, 0, OOPS },
944 | #};
945 | 


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