├── .gitignore ├── LICENSE ├── README.md ├── apio_template ├── apio.ini ├── install_apio.bat ├── install_apio.sh ├── pins.pcf └── top.v ├── board ├── TinyFPGA-BX-Schematic.pdf ├── TinyFPGA-BX-cache.lib ├── TinyFPGA-BX-rescue.lib ├── TinyFPGA-BX.kicad_pcb ├── TinyFPGA-BX.net ├── TinyFPGA-BX.pro ├── TinyFPGA-BX.sch ├── TinyFPGA-BX.xml ├── tinyfpga.lib └── tinyfpga.pretty │ ├── BGA-60_9x10_8.0x9.0mm_Pitch0.8mm.wrl │ ├── BGA_285_18x18_100x100mm_Pitch05mm.wrl │ ├── CDFN3225-4LD-PL-1.kicad_mod │ ├── CM81.kicad_mod │ ├── DFN-4_2x2_2.5x3.2mm_Pitch0.8mm.wrl │ ├── DFN-8-1EP_4x4mm_Pitch0.8mm.wrl │ ├── DM3D-SF.wrl │ ├── FBGA-24_5x5_6.0x8.0mm_Pitch1.0mm.wrl │ ├── Lattice-32QFN.kicad_mod │ ├── Lattice-QFN-32_5x5mm_Pitch0.5mm.kicad_mod │ ├── PTS_810_SMT_Switch.kicad_mod │ ├── SC-70-5.wrl │ ├── SC-70-C5.kicad_mod │ ├── SOT-23-5.wrl │ ├── Thin-DFN4.kicad_mod │ ├── UCBGA-81_9x9_4x4mm_Pitch0.4mm.wrl │ ├── USB-Micro.wrl │ ├── WLCSP-20_5x4_2.015x1.615mm_Pitch0.4mm.wrl │ ├── WLCSP-6_3x2_1.16x0.86mm_Pitch0.4mm.wrl │ └── Y97M01810FP.wrl ├── bootloader_alt ├── Makefile ├── TinyFPGA_B.asc ├── TinyFPGA_B.bin ├── TinyFPGA_B.blif ├── TinyFPGA_B.v ├── bootloader_alt │ ├── bootloader_alt_sbt.project │ └── bootloader_alt_syn.prj └── pins.pcf ├── dft ├── Makefile ├── TinyFPGA_B.v └── pins.pcf ├── examples └── picosoc │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── custom_ops.S │ ├── firmware.bin │ ├── firmware.c │ ├── firmware.elf │ ├── hardware.pcf │ ├── hardware.v │ ├── picorv32.v │ ├── picosoc.v │ ├── riscv_flash.ld │ ├── sections.lds │ ├── simpleuart.v │ ├── spiflash.v │ ├── spimemio.v │ └── start.S ├── icecube2_template ├── constraints │ ├── clk.sdc │ └── pins.pcf ├── template_lse.prj ├── template_sbt.project ├── template_syn.prd ├── template_syn.prj └── verilog │ └── TinyFPGA_B.v └── icestorm_template ├── Makefile ├── README.md ├── pins.pcf └── top.v /.gitignore: -------------------------------------------------------------------------------- 1 | *_Implmnt/ 2 | stdout.log 3 | synlog.tcl 4 | *~ 5 | *.swp 6 | *bak 7 | gerbers/ 8 | build/ 9 | *.pyc 10 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mattvenn/TinyFPGA-BX/9a5c9cb9fc09344bf0535946a51b30e60cf99c4c/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # TinyFPGA BX 2 | The TinyFPGA BX board is a tiny FPGA board with low cost per logic element and convenient USB bitstream programming capability. It measures just 18mm x 36mm and is a perfect fit for breadboards. The heart of the BX board is a iCE40LP8K-CM81 FPGA from Lattice. 3 | 4 | ## Getting Started on the BX 5 | The [TinyFPGA BX User Guide](https://tinyfpga.com/bx/guide.html) will help you get up and running with the BX. 6 | 7 | For full details on the ICE40 series of FPGAs you can read the [ICE40 Family Handbook](http://www.latticesemi.com/~/media/LatticeSemi/Documents/Handbooks/iCE40FamilyHandbook.pdf). 8 | 9 | ## Specifications 10 | - Height: 1.4 inches, width: 0.7 inches 11 | - Programming interface: USB 2.0 full-speed (12 mbit/sec) 12 | - ICE40LP8K FPGA 13 | - 7,680 four-input look-up-tables 14 | - 128 KBit block RAM 15 | - Phase Locked Loop 16 | - 41 user IO pins 17 | - 8 MBit of SPI Flash 18 | - Onboard 3.3 V (300 mA) and 1.2 V (150 mA) LDO regulators 19 | - Low-Power 16 MHz MEMs Oscillator 20 | - 1.3 mA power when active 21 | - 50 ppm stability. 22 | 23 | ## Project Directory Structure 24 | ### board 25 | This contains a [KiCad](http://kicad-pcb.org/) project with the schematic and layout of the B-series boards. The board is designed with 4/4mil track size/spacing and 0.2mm hole size. BOM list for the BX board is available here as well. 26 | 27 | ### icecube2_template 28 | This is a template iCEcube2 project for developing your own designs to program onto the board. It takes care of pin and clock constraints. Just edit the TinyFPGA_BX.v file to add your designs module(s). 29 | 30 | ### icestorm_template 31 | This is a template IceStorm project for developing your own designs to program onto the board. It takes care of pin and clock constraints. Just edit the TinyFPGA_BX.v file to add your designs module(s). Use `make` to build your project. 32 | 33 | ## Project Log 34 | For more information on the development and production of the B-Series please read and follow the [TinyFPGA B-Series Project Page](https://hackaday.io/project/26848-tinyfpga-b-series) at hackaday.io. 35 | 36 | ## License 37 | The TinyFPGA BX project is an open source project licensed under CERN Open Hardware Licence v1.2. Please see the included LICENSE file for details. If you do wish to distribute boards derived from this open source hardware project then you must also release the source files for the boards under CERN Open Hardware Licence v1.2. You are free to do this, but please improve upon the original design and provide a tangible benefit for users of the board. 38 | 39 | ## Building your own TinyFPGA BX Board 40 | It is possible to build the TinyFPGA BX boards by hand in a home lab. However, it uses tiny 0402 surface mount capacitors and resistors and the iCE40 FPGAs used are in a 81 ball BGA package with 0.4mm pitch between the balls. It is a challenging undertaking and will most likely result in some bad assembled boards along with the good. I have used the following with success to hand assemble the prototype boards: 41 | + Parts for the [TinyFPGA BX](https://octopart.com/bom-tool/ALrZVouf) 42 | + [Lead-Free Solder Paste](https://www.amazon.com/gp/product/B00HKK6XHC) 43 | + [Stainless Steel Solder Paste Squeegee](http://dirtypcbs.com/store/details/14/solder-paste-squeegee) 44 | + [TinyFPGA BX Solder Paste Stencil](https://www.oshstencils.com) 45 | + You'll need to generate the gerber files and upload the solder paste layer. If you plan on using solder paste for the FPGA chip, you will want the stainless steel stencil, I do not believe the polymide will work with the fine pitch BGA package. I have found that fine-pitch BGA packages are easier to assemble with only flux and no paste for prototypes. 46 | + [TinyFPGA BX PCBs](https://oshpark.com/shared_projects/uMrRTfyL) 47 | + OSH Park does a very nice job with these boards on their 4-layer process. 48 | + [Precision Tweezers](https://www.amazon.com/Precision-Anti-static-Marrywindix-Electronics-Jewelry-making/dp/B00DVIEJ14) for placing parts on the board 49 | + Some sort of magnifying tool for placing parts ([magnifying glasses](https://www.amazon.com/dp/B01H8808H6), [magnifying lamp](https://www.amazon.com/Brightech-LightView-SuperBright-Magnifier-Adjustable/dp/B00UW2IRJ2), microscope) 50 | + [Reflow Oven](http://www.whizoo.com/) 51 | + This is the kit I use to reflow my prototypes. You may also be able to use a good hot-plate or hot-air tool. 52 | + [Lattice FPGA Programmer](https://www.ebay.com/sch/i.html?_productid=533163279) 53 | + You will need this to load the bootloader onto the SPI Flash. Once the bootloader is installed you can use the Python-based programmer application to program the board over USB. 54 | 55 | ## Buy TinyFPGA BX Boards 56 | If you don't want to go through the hassle of ordering parts, tools, and supplies and assembling the boards yourself you can order professionally assembled and tested boards from [Crowd Supply](https://www.crowdsupply.com/tinyfpga/tinyfpga-bx). These boards are not hobbyist-made, they are fabricated and assembled in a professional PCB fab that manufactures and assembles many other consumer, industrial and military electronics. They go through an automated testing and programming process to ensure the board is healthy and ready to program over USB. When the Crowd Supply campaign ends and all the backers orders are shipped the boards will become available on Tindie and the TinyFPGA Store. 57 | -------------------------------------------------------------------------------- /apio_template/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = TinyFPGA-BX 3 | 4 | -------------------------------------------------------------------------------- /apio_template/install_apio.bat: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | @pause 5 | 6 | -------------------------------------------------------------------------------- /apio_template/install_apio.sh: -------------------------------------------------------------------------------- 1 | pip install apio==0.4.0b3 tinyprog 2 | apio install system scons icestorm drivers 3 | apio drivers --serial-enable 4 | 5 | -------------------------------------------------------------------------------- /apio_template/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io --warn-no-port PIN_1 A2 42 | set_io --warn-no-port PIN_2 A1 43 | set_io --warn-no-port PIN_3 B1 44 | set_io --warn-no-port PIN_4 C2 45 | set_io --warn-no-port PIN_5 C1 46 | set_io --warn-no-port PIN_6 D2 47 | set_io --warn-no-port PIN_7 D1 48 | set_io --warn-no-port PIN_8 E2 49 | set_io --warn-no-port PIN_9 E1 50 | set_io --warn-no-port PIN_10 G2 51 | set_io --warn-no-port PIN_11 H1 52 | set_io --warn-no-port PIN_12 J1 53 | set_io --warn-no-port PIN_13 H2 54 | 55 | # Right side of board 56 | set_io --warn-no-port PIN_14 H9 57 | set_io --warn-no-port PIN_15 D9 58 | set_io --warn-no-port PIN_16 D8 59 | set_io --warn-no-port PIN_17 C9 60 | set_io --warn-no-port PIN_18 A9 61 | set_io --warn-no-port PIN_19 B8 62 | set_io --warn-no-port PIN_20 A8 63 | set_io --warn-no-port PIN_21 B7 64 | set_io --warn-no-port PIN_22 A7 65 | set_io --warn-no-port PIN_23 B6 66 | set_io --warn-no-port PIN_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io --warn-no-port SPI_SS F7 70 | set_io --warn-no-port SPI_SCK G7 71 | set_io --warn-no-port SPI_IO0 G6 72 | set_io --warn-no-port SPI_IO1 H7 73 | set_io --warn-no-port SPI_IO2 H4 74 | set_io --warn-no-port SPI_IO3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io --warn-no-port PIN_25 G1 78 | set_io --warn-no-port PIN_26 J3 79 | set_io --warn-no-port PIN_27 J4 80 | set_io --warn-no-port PIN_28 G9 81 | set_io --warn-no-port PIN_29 J9 82 | set_io --warn-no-port PIN_30 E8 83 | set_io --warn-no-port PIN_31 J2 84 | 85 | # LED 86 | set_io --warn-no-port LED B3 87 | 88 | # USB 89 | set_io --warn-no-port USBP B4 90 | set_io --warn-no-port USBN A4 91 | set_io --warn-no-port USBPU A3 92 | 93 | # 16MHz clock 94 | set_io --warn-no-port CLK B2 # input 95 | -------------------------------------------------------------------------------- /apio_template/top.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module top ( 3 | input CLK, // 16MHz clock 4 | output LED, // User/boot LED next to power LED 5 | output USBPU // USB pull-up resistor 6 | ); 7 | // drive USB pull-up resistor to '0' to disable USB 8 | assign USBPU = 0; 9 | 10 | //////// 11 | // make a simple blink circuit 12 | //////// 13 | 14 | // keep track of time and location in blink_pattern 15 | reg [25:0] blink_counter; 16 | 17 | // pattern that will be flashed over the LED over time 18 | wire [31:0] blink_pattern = 32'b101010001110111011100010101; 19 | 20 | // increment the blink_counter every clock 21 | always @(posedge CLK) begin 22 | blink_counter <= blink_counter + 1; 23 | end 24 | 25 | // light up the LED according to the pattern 26 | assign LED = blink_pattern[blink_counter[25:21]]; 27 | endmodule 28 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX-Schematic.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mattvenn/TinyFPGA-BX/9a5c9cb9fc09344bf0535946a51b30e60cf99c4c/board/TinyFPGA-BX-Schematic.pdf -------------------------------------------------------------------------------- /board/TinyFPGA-BX-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # +1V2 5 | # 6 | DEF +1V2 #PWR 0 0 Y Y 1 F P 7 | F0 "#PWR" 0 -150 50 H I C CNN 8 | F1 "+1V2" 0 140 50 H V C CNN 9 | F2 "" 0 0 50 H I C CNN 10 | F3 "" 0 0 50 H I C CNN 11 | DRAW 12 | P 2 0 1 0 -30 50 0 100 N 13 | P 2 0 1 0 0 0 0 100 N 14 | P 2 0 1 0 0 100 30 50 N 15 | X +1V2 1 0 0 0 U 50 50 1 1 W N 16 | ENDDRAW 17 | ENDDEF 18 | # 19 | # +3V3 20 | # 21 | DEF +3V3 #PWR 0 0 Y Y 1 F P 22 | F0 "#PWR" 0 -150 50 H I C CNN 23 | F1 "+3V3" 0 140 50 H V C CNN 24 | F2 "" 0 0 50 H I C CNN 25 | F3 "" 0 0 50 H I C CNN 26 | ALIAS +3.3V 27 | DRAW 28 | P 2 0 1 0 -30 50 0 100 N 29 | P 2 0 1 0 0 0 0 100 N 30 | P 2 0 1 0 0 100 30 50 N 31 | X +3V3 1 0 0 0 U 50 50 1 1 W N 32 | ENDDRAW 33 | ENDDEF 34 | # 35 | # +5V 36 | # 37 | DEF +5V #PWR 0 0 Y Y 1 F P 38 | F0 "#PWR" 0 -150 50 H I C CNN 39 | F1 "+5V" 0 140 50 H V C CNN 40 | F2 "" 0 0 50 H I C CNN 41 | F3 "" 0 0 50 H I C CNN 42 | DRAW 43 | P 2 0 1 0 -30 50 0 100 N 44 | P 2 0 1 0 0 0 0 100 N 45 | P 2 0 1 0 0 100 30 50 N 46 | X +5V 1 0 0 0 U 50 50 1 1 W N 47 | ENDDRAW 48 | ENDDEF 49 | # 50 | # AT25SF041-SSHD-B 51 | # 52 | DEF AT25SF041-SSHD-B U 0 40 Y Y 1 L N 53 | F0 "U" 150 250 60 H V R CNN 54 | F1 "AT25SF041-SSHD-B" 150 150 60 H V R CNN 55 | F2 "" 0 0 60 H I C CNN 56 | F3 "" 0 0 60 H I C CNN 57 | DRAW 58 | S 200 400 1200 -700 1 1 12 N 59 | X !CS 1 1400 -300 200 L 50 50 1 1 B 60 | X SO 2 1400 -200 200 L 50 50 1 1 B 61 | X !WP 3 0 -100 200 R 50 50 1 1 B 62 | X GND 4 700 -900 200 U 50 50 1 1 B 63 | X SI 5 1400 -100 200 L 50 50 1 1 B 64 | X SCK 6 1400 0 200 L 50 50 1 1 B 65 | X !HOLD 7 0 -200 200 R 50 50 1 1 B 66 | X VCC 8 700 600 200 D 50 50 1 1 B 67 | ENDDRAW 68 | ENDDEF 69 | # 70 | # C 71 | # 72 | DEF C C 0 10 N Y 1 F N 73 | F0 "C" 25 100 50 H V L CNN 74 | F1 "C" 25 -100 50 H V L CNN 75 | F2 "" 38 -150 50 H I C CNN 76 | F3 "" 0 0 50 H I C CNN 77 | $FPLIST 78 | C_* 79 | $ENDFPLIST 80 | DRAW 81 | P 2 0 1 20 -80 -30 80 -30 N 82 | P 2 0 1 20 -80 30 80 30 N 83 | X ~ 1 0 150 110 D 50 50 1 1 P 84 | X ~ 2 0 -150 110 U 50 50 1 1 P 85 | ENDDRAW 86 | ENDDEF 87 | # 88 | # C_Small 89 | # 90 | DEF C_Small C 0 10 N N 1 F N 91 | F0 "C" 10 70 50 H V L CNN 92 | F1 "C_Small" 10 -80 50 H V L CNN 93 | F2 "" 0 0 50 H I C CNN 94 | F3 "" 0 0 50 H I C CNN 95 | $FPLIST 96 | C_* 97 | $ENDFPLIST 98 | DRAW 99 | P 2 0 1 13 -60 -20 60 -20 N 100 | P 2 0 1 12 -60 20 60 20 N 101 | X ~ 1 0 100 80 D 50 50 1 1 P 102 | X ~ 2 0 -100 80 U 50 50 1 1 P 103 | ENDDRAW 104 | ENDDEF 105 | # 106 | # Conn_01x14 107 | # 108 | DEF Conn_01x14 J 0 40 Y N 1 F N 109 | F0 "J" 0 700 50 H V C CNN 110 | F1 "Conn_01x14" 0 -800 50 H V C CNN 111 | F2 "" 0 0 50 H I C CNN 112 | F3 "" 0 0 50 H I C CNN 113 | $FPLIST 114 | Connector*:*_??x*mm* 115 | Connector*:*1x??x*mm* 116 | Pin?Header?Straight?1X* 117 | Pin?Header?Angled?1X* 118 | Socket?Strip?Straight?1X* 119 | Socket?Strip?Angled?1X* 120 | $ENDFPLIST 121 | DRAW 122 | S -50 -695 0 -705 1 1 6 N 123 | S -50 -595 0 -605 1 1 6 N 124 | S -50 -495 0 -505 1 1 6 N 125 | S -50 -395 0 -405 1 1 6 N 126 | S -50 -295 0 -305 1 1 6 N 127 | S -50 -195 0 -205 1 1 6 N 128 | S -50 -95 0 -105 1 1 6 N 129 | S -50 5 0 -5 1 1 6 N 130 | S -50 105 0 95 1 1 6 N 131 | S -50 205 0 195 1 1 6 N 132 | S -50 305 0 295 1 1 6 N 133 | S -50 405 0 395 1 1 6 N 134 | S -50 505 0 495 1 1 6 N 135 | S -50 605 0 595 1 1 6 N 136 | S -50 650 50 -750 1 1 10 f 137 | X Pin_1 1 -200 600 150 R 50 50 1 1 P 138 | X Pin_2 2 -200 500 150 R 50 50 1 1 P 139 | X Pin_3 3 -200 400 150 R 50 50 1 1 P 140 | X Pin_4 4 -200 300 150 R 50 50 1 1 P 141 | X Pin_5 5 -200 200 150 R 50 50 1 1 P 142 | X Pin_6 6 -200 100 150 R 50 50 1 1 P 143 | X Pin_7 7 -200 0 150 R 50 50 1 1 P 144 | X Pin_8 8 -200 -100 150 R 50 50 1 1 P 145 | X Pin_9 9 -200 -200 150 R 50 50 1 1 P 146 | X Pin_10 10 -200 -300 150 R 50 50 1 1 P 147 | X Pin_11 11 -200 -400 150 R 50 50 1 1 P 148 | X Pin_12 12 -200 -500 150 R 50 50 1 1 P 149 | X Pin_13 13 -200 -600 150 R 50 50 1 1 P 150 | X Pin_14 14 -200 -700 150 R 50 50 1 1 P 151 | ENDDRAW 152 | ENDDEF 153 | # 154 | # Conn_02x03_Odd_Even 155 | # 156 | DEF Conn_02x03_Odd_Even J 0 40 Y N 1 F N 157 | F0 "J" 50 200 50 H V C CNN 158 | F1 "Conn_02x03_Odd_Even" 50 -200 50 H V C CNN 159 | F2 "" 0 0 50 H I C CNN 160 | F3 "" 0 0 50 H I C CNN 161 | $FPLIST 162 | Connector*:*2x??x*mm* 163 | Connector*:*2x???Pitch* 164 | Pin_Header_Straight_2X* 165 | Pin_Header_Angled_2X* 166 | Socket_Strip_Straight_2X* 167 | Socket_Strip_Angled_2X* 168 | $ENDFPLIST 169 | DRAW 170 | S -50 -95 0 -105 1 1 6 N 171 | S -50 5 0 -5 1 1 6 N 172 | S -50 105 0 95 1 1 6 N 173 | S -50 150 150 -150 1 1 10 f 174 | S 150 -95 100 -105 1 1 6 N 175 | S 150 5 100 -5 1 1 6 N 176 | S 150 105 100 95 1 1 6 N 177 | X Pin_1 1 -200 100 150 R 50 50 1 1 P 178 | X Pin_2 2 300 100 150 L 50 50 1 1 P 179 | X Pin_3 3 -200 0 150 R 50 50 1 1 P 180 | X Pin_4 4 300 0 150 L 50 50 1 1 P 181 | X Pin_5 5 -200 -100 150 R 50 50 1 1 P 182 | X Pin_6 6 300 -100 150 L 50 50 1 1 P 183 | ENDDRAW 184 | ENDDEF 185 | # 186 | # Conn_02x08_Odd_Even 187 | # 188 | DEF Conn_02x08_Odd_Even J 0 40 Y N 1 F N 189 | F0 "J" 50 400 50 H V C CNN 190 | F1 "Conn_02x08_Odd_Even" 50 -500 50 H V C CNN 191 | F2 "" 0 0 50 H I C CNN 192 | F3 "" 0 0 50 H I C CNN 193 | $FPLIST 194 | Connector*:*2x??x*mm* 195 | Connector*:*2x???Pitch* 196 | Pin_Header_Straight_2X* 197 | Pin_Header_Angled_2X* 198 | Socket_Strip_Straight_2X* 199 | Socket_Strip_Angled_2X* 200 | $ENDFPLIST 201 | DRAW 202 | S -50 -395 0 -405 1 1 6 N 203 | S -50 -295 0 -305 1 1 6 N 204 | S -50 -195 0 -205 1 1 6 N 205 | S -50 -95 0 -105 1 1 6 N 206 | S -50 5 0 -5 1 1 6 N 207 | S -50 105 0 95 1 1 6 N 208 | S -50 205 0 195 1 1 6 N 209 | S -50 305 0 295 1 1 6 N 210 | S -50 350 150 -450 1 1 10 f 211 | S 150 -395 100 -405 1 1 6 N 212 | S 150 -295 100 -305 1 1 6 N 213 | S 150 -195 100 -205 1 1 6 N 214 | S 150 -95 100 -105 1 1 6 N 215 | S 150 5 100 -5 1 1 6 N 216 | S 150 105 100 95 1 1 6 N 217 | S 150 205 100 195 1 1 6 N 218 | S 150 305 100 295 1 1 6 N 219 | X Pin_1 1 -200 300 150 R 50 50 1 1 P 220 | X Pin_2 2 300 300 150 L 50 50 1 1 P 221 | X Pin_3 3 -200 200 150 R 50 50 1 1 P 222 | X Pin_4 4 300 200 150 L 50 50 1 1 P 223 | X Pin_5 5 -200 100 150 R 50 50 1 1 P 224 | X Pin_6 6 300 100 150 L 50 50 1 1 P 225 | X Pin_7 7 -200 0 150 R 50 50 1 1 P 226 | X Pin_8 8 300 0 150 L 50 50 1 1 P 227 | X Pin_9 9 -200 -100 150 R 50 50 1 1 P 228 | X Pin_10 10 300 -100 150 L 50 50 1 1 P 229 | X Pin_11 11 -200 -200 150 R 50 50 1 1 P 230 | X Pin_12 12 300 -200 150 L 50 50 1 1 P 231 | X Pin_13 13 -200 -300 150 R 50 50 1 1 P 232 | X Pin_14 14 300 -300 150 L 50 50 1 1 P 233 | X Pin_15 15 -200 -400 150 R 50 50 1 1 P 234 | X Pin_16 16 300 -400 150 L 50 50 1 1 P 235 | ENDDRAW 236 | ENDDEF 237 | # 238 | # DSC6001CI2A-016.0000T 239 | # 240 | DEF DSC6001CI2A-016.0000T U 0 40 Y Y 1 L N 241 | F0 "U" 150 250 60 H V R CNN 242 | F1 "DSC6001CI2A-016.0000T" 150 150 60 H V R CNN 243 | F2 "" 0 0 60 H I C CNN 244 | F3 "" 0 0 60 H I C CNN 245 | DRAW 246 | S 200 400 1000 -400 1 1 12 N 247 | X OE 1 0 0 200 R 50 50 1 1 B 248 | X GND 2 600 -600 200 U 50 50 1 1 B 249 | X OUT 3 1200 0 200 L 50 50 1 1 B 250 | X VDD 4 600 600 200 D 50 50 1 1 B 251 | ENDDRAW 252 | ENDDEF 253 | # 254 | # Ferrite_Bead_Small 255 | # 256 | DEF Ferrite_Bead_Small L 0 0 N Y 1 F N 257 | F0 "L" 75 50 50 H V L CNN 258 | F1 "Ferrite_Bead_Small" 75 -50 50 H V L CNN 259 | F2 "" -70 0 50 V I C CNN 260 | F3 "" 0 0 50 H I C CNN 261 | $FPLIST 262 | Inductor_* 263 | L_* 264 | *Ferrite* 265 | $ENDFPLIST 266 | DRAW 267 | P 2 0 1 0 0 -50 0 -31 N 268 | P 2 0 1 0 0 35 0 51 N 269 | P 5 0 1 0 -72 11 -44 59 72 -8 44 -56 -72 11 N 270 | X ~ 1 0 100 50 D 50 50 1 1 P 271 | X ~ 2 0 -100 50 U 50 50 1 1 P 272 | ENDDRAW 273 | ENDDEF 274 | # 275 | # GND 276 | # 277 | DEF GND #PWR 0 0 Y Y 1 F P 278 | F0 "#PWR" 0 -250 50 H I C CNN 279 | F1 "GND" 0 -150 50 H V C CNN 280 | F2 "" 0 0 50 H I C CNN 281 | F3 "" 0 0 50 H I C CNN 282 | DRAW 283 | P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N 284 | X GND 1 0 0 0 D 50 50 1 1 W N 285 | ENDDRAW 286 | ENDDEF 287 | # 288 | # LED_Small 289 | # 290 | DEF LED_Small D 0 10 N N 1 F N 291 | F0 "D" -50 125 50 H V L CNN 292 | F1 "LED_Small" -175 -100 50 H V L CNN 293 | F2 "" 0 0 50 V I C CNN 294 | F3 "" 0 0 50 V I C CNN 295 | $FPLIST 296 | LED-* 297 | LED_* 298 | $ENDFPLIST 299 | DRAW 300 | P 2 0 1 0 -30 -40 -30 40 N 301 | P 2 0 1 0 40 0 -30 0 N 302 | P 4 0 1 0 30 -40 -30 0 30 40 30 -40 N 303 | P 5 0 1 0 0 30 -20 50 -10 50 -20 50 -20 40 N 304 | P 5 0 1 0 20 50 0 70 10 70 0 70 0 60 N 305 | X K 1 -100 0 70 R 50 50 1 1 P 306 | X A 2 100 0 70 L 50 50 1 1 P 307 | ENDDRAW 308 | ENDDEF 309 | # 310 | # MIC5365-1.2YC5-TR 311 | # 312 | DEF MIC5365-1.2YC5-TR U 0 40 Y Y 1 L N 313 | F0 "U" 200 250 60 H V L CNN 314 | F1 "MIC5365-1.2YC5-TR" 200 150 60 H V L CNN 315 | F2 "" 0 0 60 H I C CNN 316 | F3 "" 0 0 60 H I C CNN 317 | DRAW 318 | S 200 100 1000 -500 1 1 12 N 319 | X VIN 1 0 0 200 R 50 50 1 1 B 320 | X GND 2 600 -700 200 U 50 50 1 1 B 321 | X EN 3 0 -100 200 R 50 50 1 1 B 322 | X NC 4 1200 0 200 L 50 50 1 1 B 323 | X VOUT 5 1200 -100 200 L 50 50 1 1 B 324 | ENDDRAW 325 | ENDDEF 326 | # 327 | # MIC5504-3.3YM5-TR 328 | # 329 | DEF MIC5504-3.3YM5-TR U 0 40 Y Y 1 L N 330 | F0 "U" 200 250 60 H V L CNN 331 | F1 "MIC5504-3.3YM5-TR" 200 150 60 H V L CNN 332 | F2 "" 0 0 60 H I C CNN 333 | F3 "" 0 0 60 H I C CNN 334 | DRAW 335 | S 200 100 1000 -500 1 1 12 N 336 | X VIN 1 0 0 200 R 50 50 1 1 B 337 | X GND 2 600 -700 200 U 50 50 1 1 B 338 | X EN 3 0 -100 200 R 50 50 1 1 B 339 | X NC 4 1200 0 200 L 50 50 1 1 B 340 | X VOUT 5 1200 -100 200 L 50 50 1 1 B 341 | ENDDRAW 342 | ENDDEF 343 | # 344 | # R 345 | # 346 | DEF R R 0 0 N Y 1 F N 347 | F0 "R" 80 0 50 V V C CNN 348 | F1 "R" 0 0 50 V V C CNN 349 | F2 "" -70 0 50 V I C CNN 350 | F3 "" 0 0 50 H I C CNN 351 | $FPLIST 352 | R_* 353 | R_* 354 | $ENDFPLIST 355 | DRAW 356 | S -40 -100 40 100 0 1 10 N 357 | X ~ 1 0 150 50 D 50 50 1 1 P 358 | X ~ 2 0 -150 50 U 50 50 1 1 P 359 | ENDDRAW 360 | ENDDEF 361 | # 362 | # R_Small 363 | # 364 | DEF R_Small R 0 10 N N 1 F N 365 | F0 "R" 30 20 50 H V L CNN 366 | F1 "R_Small" 30 -40 50 H V L CNN 367 | F2 "" 0 0 50 H I C CNN 368 | F3 "" 0 0 50 H I C CNN 369 | $FPLIST 370 | R_* 371 | $ENDFPLIST 372 | DRAW 373 | S -30 70 30 -70 0 1 8 N 374 | X ~ 1 0 100 30 D 50 50 1 1 P 375 | X ~ 2 0 -100 30 U 50 50 1 1 P 376 | ENDDRAW 377 | ENDDEF 378 | # 379 | # SW_Push 380 | # 381 | DEF SW_Push SW 0 40 N N 1 F N 382 | F0 "SW" 50 100 50 H V L CNN 383 | F1 "SW_Push" 0 -60 50 H V C CNN 384 | F2 "" 0 200 50 H I C CNN 385 | F3 "" 0 200 50 H I C CNN 386 | DRAW 387 | C -80 0 20 0 1 0 N 388 | C 80 0 20 0 1 0 N 389 | P 2 0 1 0 0 50 0 120 N 390 | P 2 0 1 0 100 50 -100 50 N 391 | X 1 1 -200 0 100 R 50 50 0 1 P 392 | X 2 2 200 0 100 L 50 50 0 1 P 393 | ENDDRAW 394 | ENDDEF 395 | # 396 | # TEST 397 | # 398 | DEF TEST TP 0 40 N N 1 F N 399 | F0 "TP" 0 300 50 H V C BNN 400 | F1 "TEST" 0 250 50 H V C CNN 401 | F2 "" 0 0 50 H I C CNN 402 | F3 "" 0 0 50 H I C CNN 403 | DRAW 404 | P 6 0 1 0 0 200 -50 150 0 100 50 150 0 200 0 200 N 405 | X ~ 1 0 0 100 U 50 50 1 1 P 406 | ENDDRAW 407 | ENDDEF 408 | # 409 | # USB_OTG 410 | # 411 | DEF USB_OTG J 0 40 Y Y 1 F N 412 | F0 "J" -200 450 50 H V L CNN 413 | F1 "USB_OTG" -200 350 50 H V L CNN 414 | F2 "" 150 -50 50 H I C CNN 415 | F3 "" 150 -50 50 H I C CNN 416 | $FPLIST 417 | USB* 418 | $ENDFPLIST 419 | DRAW 420 | C -150 85 25 0 1 10 F 421 | C -25 135 15 0 1 10 F 422 | S -200 -300 200 300 0 1 10 f 423 | S -5 -300 5 -270 0 1 0 N 424 | S 10 50 -20 20 0 1 10 F 425 | S 200 -205 170 -195 0 1 0 N 426 | S 200 -105 170 -95 0 1 0 N 427 | S 200 -5 170 5 0 1 0 N 428 | S 200 195 170 205 0 1 0 N 429 | P 2 0 1 10 -75 85 25 85 N 430 | P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N 431 | P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N 432 | P 4 0 1 10 25 110 25 60 75 85 25 110 F 433 | P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F 434 | P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N 435 | X VBUS 1 300 200 100 L 50 50 1 1 W 436 | X D- 2 300 -100 100 L 50 50 1 1 P 437 | X D+ 3 300 0 100 L 50 50 1 1 P 438 | X ID 4 300 -200 100 L 50 50 1 1 P 439 | X GND 5 0 -400 100 U 50 50 1 1 W 440 | X Shield 6 -100 -400 100 U 50 50 1 1 P 441 | ENDDRAW 442 | ENDDEF 443 | # 444 | # iCE40-LP8K-CM81 445 | # 446 | DEF iCE40-LP8K-CM81 U 0 40 Y Y 8 L N 447 | F0 "U" 200 250 60 H V L CNN 448 | F1 "iCE40-LP8K-CM81" 200 150 60 H V L CNN 449 | F2 "" 0 0 60 H I C CNN 450 | F3 "" 0 0 60 H I C CNN 451 | DRAW 452 | S 200 100 1000 -1000 1 1 12 N 453 | X IOB_103_CBSEL0 G5 0 -300 200 R 50 50 1 1 B 454 | X IOB_104_CBSEL1 H5 0 -600 200 R 50 50 1 1 B 455 | X CDONE E6 0 -200 200 R 50 50 1 1 B 456 | X IOB_105_SDO G6 0 -400 200 R 50 50 1 1 B 457 | X CRESET_B H6 0 -700 200 R 50 50 1 1 B 458 | X VPP_FAST C7 0 0 200 R 50 50 1 1 B 459 | X IOB_107_SCK G7 0 -500 200 R 50 50 1 1 B 460 | X IOB_106_SDI H7 0 -800 200 R 50 50 1 1 B 461 | X VPP_2V5 C8 0 -100 200 R 50 50 1 1 B 462 | X VCC_SPI H8 0 -900 200 R 50 50 1 1 B 463 | S 200 100 500 -400 2 1 12 N 464 | X GND F4 0 0 200 R 50 50 2 1 B 465 | X GND F5 0 -100 200 R 50 50 2 1 B 466 | X GND F6 0 -200 200 R 50 50 2 1 B 467 | X GND F9 0 -300 200 R 50 50 2 1 B 468 | S 200 100 900 -800 3 1 12 N 469 | X IOB_54 H1 0 -200 200 R 50 50 3 1 B 470 | X IOB_55 J1 0 -400 200 R 50 50 3 1 B 471 | X IOB_56 J2 0 -500 200 R 50 50 3 1 B 472 | X IOB_57 J3 0 -600 200 R 50 50 3 1 B 473 | X IOB_81_GBIN5 G4 0 -100 200 R 50 50 3 1 B 474 | X IOB_82_GBIN4 H4 0 -300 200 R 50 50 3 1 B 475 | X IOB_70 J4 0 -700 200 R 50 50 3 1 B 476 | X IOB_108_SS F7 0 0 200 R 50 50 3 1 B 477 | S 200 100 1000 -1800 4 1 12 N 478 | X IOL_3A B1 0 0 200 R 50 50 4 1 B 479 | X IOL_3B C1 0 -200 200 R 50 50 4 1 B 480 | X IOL_10A D1 0 -500 200 R 50 50 4 1 B 481 | X IOL_10B E1 0 -800 200 R 50 50 4 1 B 482 | X IOL_22A F1 0 -1200 200 R 50 50 4 1 B 483 | X IOL_24B G1 0 -1400 200 R 50 50 4 1 B 484 | X IOL_2B B2 0 -100 200 R 50 50 4 1 B 485 | X IOL_2A C2 0 -300 200 R 50 50 4 1 B 486 | X IOL_7A D2 0 -600 200 R 50 50 4 1 B 487 | X IOL_13A E2 0 -900 200 R 50 50 4 1 B 488 | X IOL_26A G2 0 -1500 200 R 50 50 4 1 B 489 | X IOL_26B H2 0 -1700 200 R 50 50 4 1 B 490 | X IOL_7B C3 0 -400 200 R 50 50 4 1 B 491 | X IOL_13B_GBIN7 D3 0 -700 200 R 50 50 4 1 B 492 | X IOL_14A_GBIN6 E3 0 -1000 200 R 50 50 4 1 B 493 | X IOL_22B F3 0 -1300 200 R 50 50 4 1 B 494 | X IOL_24A G3 0 -1600 200 R 50 50 4 1 B 495 | X IOL_14B E4 0 -1100 200 R 50 50 4 1 B 496 | S 200 100 1000 -1500 5 1 12 N 497 | X IOR_115 D6 0 -300 200 R 50 50 5 1 B 498 | X IOR_117 D7 0 -400 200 R 50 50 5 1 B 499 | X IOR_118 E7 0 -700 200 R 50 50 5 1 B 500 | X IOR_141_GBIN2 D8 0 -500 200 R 50 50 5 1 B 501 | X IOR_140_GBIN3 E8 0 -800 200 R 50 50 5 1 B 502 | X IOR_113 F8 0 -900 200 R 50 50 5 1 B 503 | X IOR_114 G8 0 -1000 200 R 50 50 5 1 B 504 | X IOR_109 J8 0 -1300 200 R 50 50 5 1 B 505 | X IOR_116 A9 0 0 200 R 50 50 5 1 B 506 | X IOR_120 B9 0 -100 200 R 50 50 5 1 B 507 | X IOR_148 C9 0 -200 200 R 50 50 5 1 B 508 | X IOR_119 D9 0 -600 200 R 50 50 5 1 B 509 | X IOR_112 G9 0 -1100 200 R 50 50 5 1 B 510 | X IOR_111 H9 0 -1200 200 R 50 50 5 1 B 511 | X IOR_110 J9 0 -1400 200 R 50 50 5 1 B 512 | S 200 100 1000 -1700 6 1 12 N 513 | X IOT_224 A1 0 0 200 R 50 50 6 1 B 514 | X IOT_221 A2 0 -100 200 R 50 50 6 1 B 515 | X IOT_217 A3 0 -200 200 R 50 50 6 1 B 516 | X IOT_218 B3 0 -700 200 R 50 50 6 1 B 517 | X IOT_208 A4 0 -300 200 R 50 50 6 1 B 518 | X IOT_211 B4 0 -800 200 R 50 50 6 1 B 519 | X IOT_198_GBIN0 C4 0 -1300 200 R 50 50 6 1 B 520 | X IOT_188 B5 0 -900 200 R 50 50 6 1 B 521 | X IOT_197_GBIN1 C5 0 -1400 200 R 50 50 6 1 B 522 | X IOT_212 D5 0 -1500 200 R 50 50 6 1 B 523 | X IOT_214 E5 0 -1600 200 R 50 50 6 1 B 524 | X IOT_185 A6 0 -400 200 R 50 50 6 1 B 525 | X IOT_183 B6 0 -1000 200 R 50 50 6 1 B 526 | X IOT_177 A7 0 -500 200 R 50 50 6 1 B 527 | X IOT_180 B7 0 -1100 200 R 50 50 6 1 B 528 | X IOT_174 A8 0 -600 200 R 50 50 6 1 B 529 | X IOT_170 B8 0 -1200 200 R 50 50 6 1 B 530 | S 200 100 700 -200 7 1 12 N 531 | X GNDPLL0 J6 0 0 200 R 50 50 7 1 B 532 | X VCCPLL0 J7 0 -100 200 R 50 50 7 1 B 533 | S 200 100 700 -700 8 1 12 N 534 | X VCC F2 0 -400 200 R 50 50 8 1 B 535 | X VCCIO_3 H3 0 -500 200 R 50 50 8 1 B 536 | X VCC D4 0 -200 200 R 50 50 8 1 B 537 | X VCCIO_0 A5 0 0 200 R 50 50 8 1 B 538 | X VCCIO_2 J5 0 -600 200 R 50 50 8 1 B 539 | X VCCIO_1 C6 0 -100 200 R 50 50 8 1 B 540 | X VCC E9 0 -300 200 R 50 50 8 1 B 541 | ENDDRAW 542 | ENDDEF 543 | # 544 | #End Library 545 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX-rescue.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | #End Library 5 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX.pro: -------------------------------------------------------------------------------- 1 | update=3/30/2018 3:46:56 PM 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [cvpcb] 9 | version=1 10 | NetIExt=net 11 | [eeschema] 12 | version=1 13 | LibDir= 14 | [eeschema/libraries] 15 | LibName1=power 16 | LibName2=device 17 | LibName3=switches 18 | LibName4=relays 19 | LibName5=motors 20 | LibName6=transistors 21 | LibName7=conn 22 | LibName8=linear 23 | LibName9=regul 24 | LibName10=74xx 25 | LibName11=cmos4000 26 | LibName12=adc-dac 27 | LibName13=memory 28 | LibName14=xilinx 29 | LibName15=microcontrollers 30 | LibName16=dsp 31 | LibName17=microchip 32 | LibName18=analog_switches 33 | LibName19=motorola 34 | LibName20=texas 35 | LibName21=intel 36 | LibName22=audio 37 | LibName23=interface 38 | LibName24=digital-audio 39 | LibName25=philips 40 | LibName26=display 41 | LibName27=cypress 42 | LibName28=siliconi 43 | LibName29=opto 44 | LibName30=atmel 45 | LibName31=contrib 46 | LibName32=valves 47 | [pcbnew] 48 | version=1 49 | PageLayoutDescrFile= 50 | LastNetListRead=TinyFPGA-BX.net 51 | PadDrill=0 52 | PadDrillOvalY=0 53 | PadSizeH=0.09999999999999999 54 | PadSizeV=0.09999999999999999 55 | PcbTextSizeV=1.5 56 | PcbTextSizeH=1.5 57 | PcbTextThickness=0.3 58 | ModuleTextSizeV=1 59 | ModuleTextSizeH=1 60 | ModuleTextSizeThickness=0.15 61 | SolderMaskClearance=0.075 62 | SolderMaskMinWidth=0 63 | DrawSegmentWidth=0.2 64 | BoardOutlineThickness=0.15 65 | ModuleOutlineThickness=0.15 66 | [schematic_editor] 67 | version=1 68 | PageLayoutDescrFile= 69 | PlotDirectoryName= 70 | SubpartIdSeparator=0 71 | SubpartFirstId=65 72 | NetFmtName= 73 | SpiceForceRefPrefix=0 74 | SpiceUseNetNumbers=0 75 | LabSize=60 76 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | C:/Users/lvale/Documents/TinyFPGA/TinyFPGA-ICE/TinyFPGA-ICE.sch 5 | 5/24/2017 7:27:29 AM 6 | Eeschema 4.0.6 7 | 8 | 9 | 10 | <company/> 11 | <rev/> 12 | <date/> 13 | <source>TinyFPGA-ICE.sch</source> 14 | <comment number="1" value=""/> 15 | <comment number="2" value=""/> 16 | <comment number="3" value=""/> 17 | <comment number="4" value=""/> 18 | </title_block> 19 | </sheet> 20 | </design> 21 | <components> 22 | <comp ref="U1"> 23 | <value>iCE40-LP8K-CM81</value> 24 | <footprint>tinyfpga:CM81</footprint> 25 | <libsource lib="tinyfpga" part="iCE40-LP8K-CM81"/> 26 | <sheetpath names="/" tstamps="/"/> 27 | <tstamp>591007FD</tstamp> 28 | </comp> 29 | <comp ref="J1"> 30 | <value>CONN_01X14</value> 31 | <footprint>Pin_Headers:Pin_Header_Straight_1x14_Pitch2.54mm</footprint> 32 | <libsource lib="conn" part="CONN_01X14"/> 33 | <sheetpath names="/" tstamps="/"/> 34 | <tstamp>591076F8</tstamp> 35 | </comp> 36 | <comp ref="J2"> 37 | <value>CONN_01X14</value> 38 | <footprint>Pin_Headers:Pin_Header_Straight_1x14_Pitch2.54mm</footprint> 39 | <libsource lib="conn" part="CONN_01X14"/> 40 | <sheetpath names="/" tstamps="/"/> 41 | <tstamp>5910778F</tstamp> 42 | </comp> 43 | <comp ref="J3"> 44 | <value>USB_OTG</value> 45 | <footprint>Connectors:USB_Micro-B</footprint> 46 | <libsource lib="conn" part="USB_OTG"/> 47 | <sheetpath names="/" tstamps="/"/> 48 | <tstamp>5918C75D</tstamp> 49 | </comp> 50 | <comp ref="SW1"> 51 | <value>SW_Push</value> 52 | <footprint>tinyfpga:PTS_810_SMT_Switch</footprint> 53 | <libsource lib="switches" part="SW_Push"/> 54 | <sheetpath names="/" tstamps="/"/> 55 | <tstamp>5918CB81</tstamp> 56 | </comp> 57 | <comp ref="U4"> 58 | <value>MIC5365-1.2YC5-TR</value> 59 | <footprint>tinyfpga:SC-70-C5</footprint> 60 | <libsource lib="tinyfpga" part="MIC5365-1.2YC5-TR"/> 61 | <sheetpath names="/" tstamps="/"/> 62 | <tstamp>591A9EDF</tstamp> 63 | </comp> 64 | <comp ref="U2"> 65 | <value>MIC5504-3.3YM5-TR</value> 66 | <footprint>tinyfpga:SC-70-C5</footprint> 67 | <libsource lib="tinyfpga" part="MIC5504-3.3YM5-TR"/> 68 | <sheetpath names="/" tstamps="/"/> 69 | <tstamp>591A9F5A</tstamp> 70 | </comp> 71 | <comp ref="U3"> 72 | <value>DSC6001CI2A-016.0000T</value> 73 | <footprint>tinyfpga:CDFN3225-4LD-PL-1</footprint> 74 | <libsource lib="tinyfpga" part="DSC6001CI2A-016.0000T"/> 75 | <sheetpath names="/" tstamps="/"/> 76 | <tstamp>591A9FD7</tstamp> 77 | </comp> 78 | <comp ref="U5"> 79 | <value>AT25SF041-SSHD-B</value> 80 | <footprint>Housings_SOIC:SOIC-8-1EP_3.9x4.9mm_Pitch1.27mm</footprint> 81 | <libsource lib="tinyfpga" part="AT25SF041-SSHD-B"/> 82 | <sheetpath names="/" tstamps="/"/> 83 | <tstamp>591BDF5F</tstamp> 84 | </comp> 85 | <comp ref="C2"> 86 | <value>1uF</value> 87 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 88 | <libsource lib="device" part="C"/> 89 | <sheetpath names="/" tstamps="/"/> 90 | <tstamp>591BF1F2</tstamp> 91 | </comp> 92 | <comp ref="C3"> 93 | <value>1uF</value> 94 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 95 | <libsource lib="device" part="C"/> 96 | <sheetpath names="/" tstamps="/"/> 97 | <tstamp>591BF26D</tstamp> 98 | </comp> 99 | <comp ref="C1"> 100 | <value>1uF</value> 101 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 102 | <libsource lib="device" part="C"/> 103 | <sheetpath names="/" tstamps="/"/> 104 | <tstamp>591C09B3</tstamp> 105 | </comp> 106 | <comp ref="C4"> 107 | <value>1uF</value> 108 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 109 | <libsource lib="device" part="C"/> 110 | <sheetpath names="/" tstamps="/"/> 111 | <tstamp>591C0A32</tstamp> 112 | </comp> 113 | <comp ref="L1"> 114 | <value>Bead</value> 115 | <footprint>Inductors_SMD:L_0603</footprint> 116 | <libsource lib="device" part="Ferrite_Bead_Small"/> 117 | <sheetpath names="/" tstamps="/"/> 118 | <tstamp>591C2A75</tstamp> 119 | </comp> 120 | <comp ref="R2"> 121 | <value>68</value> 122 | <footprint>Resistors_SMD:R_0402_NoSilk</footprint> 123 | <libsource lib="device" part="R"/> 124 | <sheetpath names="/" tstamps="/"/> 125 | <tstamp>591D2293</tstamp> 126 | </comp> 127 | <comp ref="R3"> 128 | <value>68</value> 129 | <footprint>Resistors_SMD:R_0402_NoSilk</footprint> 130 | <libsource lib="device" part="R"/> 131 | <sheetpath names="/" tstamps="/"/> 132 | <tstamp>591D2392</tstamp> 133 | </comp> 134 | <comp ref="R1"> 135 | <value>1.5k</value> 136 | <footprint>Resistors_SMD:R_0402_NoSilk</footprint> 137 | <libsource lib="device" part="R"/> 138 | <sheetpath names="/" tstamps="/"/> 139 | <tstamp>591D2427</tstamp> 140 | </comp> 141 | <comp ref="C5"> 142 | <value>100nF</value> 143 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 144 | <libsource lib="device" part="C"/> 145 | <sheetpath names="/" tstamps="/"/> 146 | <tstamp>591E10BF</tstamp> 147 | </comp> 148 | <comp ref="C8"> 149 | <value>100nF</value> 150 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 151 | <libsource lib="device" part="C"/> 152 | <sheetpath names="/" tstamps="/"/> 153 | <tstamp>591E1ADB</tstamp> 154 | </comp> 155 | <comp ref="C7"> 156 | <value>100nF</value> 157 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 158 | <libsource lib="device" part="C"/> 159 | <sheetpath names="/" tstamps="/"/> 160 | <tstamp>591E2ADF</tstamp> 161 | </comp> 162 | <comp ref="C6"> 163 | <value>10uF</value> 164 | <footprint>Capacitors_SMD:C_0603</footprint> 165 | <libsource lib="device" part="C"/> 166 | <sheetpath names="/" tstamps="/"/> 167 | <tstamp>591E2B9D</tstamp> 168 | </comp> 169 | <comp ref="R4"> 170 | <value>100</value> 171 | <footprint>Resistors_SMD:R_0402_NoSilk</footprint> 172 | <libsource lib="device" part="R"/> 173 | <sheetpath names="/" tstamps="/"/> 174 | <tstamp>591E2BF1</tstamp> 175 | </comp> 176 | <comp ref="C9"> 177 | <value>100nF</value> 178 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 179 | <libsource lib="device" part="C_Small"/> 180 | <sheetpath names="/" tstamps="/"/> 181 | <tstamp>591E9D9B</tstamp> 182 | </comp> 183 | <comp ref="C10"> 184 | <value>100nF</value> 185 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 186 | <libsource lib="device" part="C_Small"/> 187 | <sheetpath names="/" tstamps="/"/> 188 | <tstamp>591E9E78</tstamp> 189 | </comp> 190 | <comp ref="C11"> 191 | <value>100nF</value> 192 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 193 | <libsource lib="device" part="C_Small"/> 194 | <sheetpath names="/" tstamps="/"/> 195 | <tstamp>591E9EF1</tstamp> 196 | </comp> 197 | <comp ref="C12"> 198 | <value>10nF</value> 199 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 200 | <libsource lib="device" part="C_Small"/> 201 | <sheetpath names="/" tstamps="/"/> 202 | <tstamp>591E9FF1</tstamp> 203 | </comp> 204 | <comp ref="C13"> 205 | <value>10nF</value> 206 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 207 | <libsource lib="device" part="C_Small"/> 208 | <sheetpath names="/" tstamps="/"/> 209 | <tstamp>591EA15E</tstamp> 210 | </comp> 211 | <comp ref="C14"> 212 | <value>10nF</value> 213 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 214 | <libsource lib="device" part="C_Small"/> 215 | <sheetpath names="/" tstamps="/"/> 216 | <tstamp>591EA1D8</tstamp> 217 | </comp> 218 | <comp ref="C15"> 219 | <value>10nF</value> 220 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 221 | <libsource lib="device" part="C_Small"/> 222 | <sheetpath names="/" tstamps="/"/> 223 | <tstamp>591EA257</tstamp> 224 | </comp> 225 | <comp ref="R5"> 226 | <value>10k</value> 227 | <footprint>Resistors_SMD:R_0402_NoSilk</footprint> 228 | <libsource lib="device" part="R"/> 229 | <sheetpath names="/" tstamps="/"/> 230 | <tstamp>591EBB96</tstamp> 231 | </comp> 232 | <comp ref="C16"> 233 | <value>100nF</value> 234 | <footprint>Capacitors_SMD:C_0402_NoSilk</footprint> 235 | <libsource lib="device" part="C_Small"/> 236 | <sheetpath names="/" tstamps="/"/> 237 | <tstamp>591EA04F</tstamp> 238 | </comp> 239 | <comp ref="R6"> 240 | <value>R</value> 241 | <footprint>Resistors_SMD:R_0402</footprint> 242 | <libsource lib="device" part="R"/> 243 | <sheetpath names="/" tstamps="/"/> 244 | <tstamp>592015DC</tstamp> 245 | </comp> 246 | <comp ref="C17"> 247 | <value>10uF</value> 248 | <footprint>Capacitors_SMD:C_0603</footprint> 249 | <libsource lib="device" part="C"/> 250 | <sheetpath names="/" tstamps="/"/> 251 | <tstamp>592061E2</tstamp> 252 | </comp> 253 | <comp ref="R7"> 254 | <value>10k</value> 255 | <footprint>Resistors_SMD:R_0402_NoSilk</footprint> 256 | <libsource lib="device" part="R"/> 257 | <sheetpath names="/" tstamps="/"/> 258 | <tstamp>5922D14B</tstamp> 259 | </comp> 260 | <comp ref="TP1"> 261 | <value>TEST</value> 262 | <footprint>Measurement_Points:Measurement_Point_Round-SMD-Pad_Small</footprint> 263 | <libsource lib="device" part="TEST"/> 264 | <sheetpath names="/" tstamps="/"/> 265 | <tstamp>5922E3E0</tstamp> 266 | </comp> 267 | <comp ref="TP2"> 268 | <value>TEST</value> 269 | <footprint>Measurement_Points:Measurement_Point_Round-SMD-Pad_Small</footprint> 270 | <libsource lib="device" part="TEST"/> 271 | <sheetpath names="/" tstamps="/"/> 272 | <tstamp>5923D3AB</tstamp> 273 | </comp> 274 | </components> 275 | <libparts> 276 | <libpart lib="tinyfpga" part="AT25SF041-SSHD-B"> 277 | <fields> 278 | <field name="Reference">U</field> 279 | <field name="Value">AT25SF041-SSHD-B</field> 280 | </fields> 281 | <pins> 282 | <pin num="1" name="!CS" type="BiDi"/> 283 | <pin num="2" name="SO" type="BiDi"/> 284 | <pin num="3" name="!WP" type="BiDi"/> 285 | <pin num="4" name="GND" type="BiDi"/> 286 | <pin num="5" name="SI" type="BiDi"/> 287 | <pin num="6" name="SCK" type="BiDi"/> 288 | <pin num="7" name="!HOLD" type="BiDi"/> 289 | <pin num="8" name="VCC" type="BiDi"/> 290 | </pins> 291 | </libpart> 292 | <libpart lib="device" part="C"> 293 | <description>Unpolarized capacitor</description> 294 | <footprints> 295 | <fp>C_*</fp> 296 | </footprints> 297 | <fields> 298 | <field name="Reference">C</field> 299 | <field name="Value">C</field> 300 | </fields> 301 | <pins> 302 | <pin num="1" name="~" type="passive"/> 303 | <pin num="2" name="~" type="passive"/> 304 | </pins> 305 | </libpart> 306 | <libpart lib="conn" part="CONN_01X14"> 307 | <description>Connector, single row, 01x14, pin header</description> 308 | <footprints> 309 | <fp>Pin_Header_Straight_1X*</fp> 310 | <fp>Pin_Header_Angled_1X*</fp> 311 | <fp>Socket_Strip_Straight_1X*</fp> 312 | <fp>Socket_Strip_Angled_1X*</fp> 313 | </footprints> 314 | <fields> 315 | <field name="Reference">J</field> 316 | <field name="Value">CONN_01X14</field> 317 | </fields> 318 | <pins> 319 | <pin num="1" name="P1" type="passive"/> 320 | <pin num="2" name="P2" type="passive"/> 321 | <pin num="3" name="P3" type="passive"/> 322 | <pin num="4" name="P4" type="passive"/> 323 | <pin num="5" name="P5" type="passive"/> 324 | <pin num="6" name="P6" type="passive"/> 325 | <pin num="7" name="P7" type="passive"/> 326 | <pin num="8" name="P8" type="passive"/> 327 | <pin num="9" name="P9" type="passive"/> 328 | <pin num="10" name="P10" type="passive"/> 329 | <pin num="11" name="P11" type="passive"/> 330 | <pin num="12" name="P12" type="passive"/> 331 | <pin num="13" name="P13" type="passive"/> 332 | <pin num="14" name="P14" type="passive"/> 333 | </pins> 334 | </libpart> 335 | <libpart lib="device" part="C_Small"> 336 | <description>Unpolarized capacitor</description> 337 | <footprints> 338 | <fp>C_*</fp> 339 | </footprints> 340 | <fields> 341 | <field name="Reference">C</field> 342 | <field name="Value">C_Small</field> 343 | </fields> 344 | <pins> 345 | <pin num="1" name="~" type="passive"/> 346 | <pin num="2" name="~" type="passive"/> 347 | </pins> 348 | </libpart> 349 | <libpart lib="tinyfpga" part="DSC6001CI2A-016.0000T"> 350 | <fields> 351 | <field name="Reference">U</field> 352 | <field name="Value">DSC6001CI2A-016.0000T</field> 353 | </fields> 354 | <pins> 355 | <pin num="1" name="OE" type="BiDi"/> 356 | <pin num="2" name="GND" type="BiDi"/> 357 | <pin num="3" name="OUT" type="BiDi"/> 358 | <pin num="4" name="VDD" type="BiDi"/> 359 | </pins> 360 | </libpart> 361 | <libpart lib="device" part="Ferrite_Bead_Small"> 362 | <description>Ferrite bead, small symbol</description> 363 | <footprints> 364 | <fp>Inductor_*</fp> 365 | <fp>L_*</fp> 366 | <fp>*Ferrite*</fp> 367 | </footprints> 368 | <fields> 369 | <field name="Reference">L</field> 370 | <field name="Value">Ferrite_Bead_Small</field> 371 | </fields> 372 | <pins> 373 | <pin num="1" name="~" type="passive"/> 374 | <pin num="2" name="~" type="passive"/> 375 | </pins> 376 | </libpart> 377 | <libpart lib="tinyfpga" part="MIC5365-1.2YC5-TR"> 378 | <fields> 379 | <field name="Reference">U</field> 380 | <field name="Value">MIC5365-1.2YC5-TR</field> 381 | </fields> 382 | <pins> 383 | <pin num="1" name="VIN" type="BiDi"/> 384 | <pin num="2" name="GND" type="BiDi"/> 385 | <pin num="3" name="EN" type="BiDi"/> 386 | <pin num="4" name="NC" type="BiDi"/> 387 | <pin num="5" name="VOUT" type="BiDi"/> 388 | </pins> 389 | </libpart> 390 | <libpart lib="tinyfpga" part="MIC5504-3.3YM5-TR"> 391 | <fields> 392 | <field name="Reference">U</field> 393 | <field name="Value">MIC5504-3.3YM5-TR</field> 394 | </fields> 395 | <pins> 396 | <pin num="1" name="VIN" type="BiDi"/> 397 | <pin num="2" name="GND" type="BiDi"/> 398 | <pin num="3" name="EN" type="BiDi"/> 399 | <pin num="4" name="NC" type="BiDi"/> 400 | <pin num="5" name="VOUT" type="BiDi"/> 401 | </pins> 402 | </libpart> 403 | <libpart lib="device" part="R"> 404 | <description>Resistor</description> 405 | <footprints> 406 | <fp>R_*</fp> 407 | <fp>R_*</fp> 408 | </footprints> 409 | <fields> 410 | <field name="Reference">R</field> 411 | <field name="Value">R</field> 412 | </fields> 413 | <pins> 414 | <pin num="1" name="~" type="passive"/> 415 | <pin num="2" name="~" type="passive"/> 416 | </pins> 417 | </libpart> 418 | <libpart lib="switches" part="SW_Push"> 419 | <description>Push button switch, generic, two pins</description> 420 | <fields> 421 | <field name="Reference">SW</field> 422 | <field name="Value">SW_Push</field> 423 | </fields> 424 | <pins> 425 | <pin num="1" name="1" type="passive"/> 426 | <pin num="2" name="2" type="passive"/> 427 | </pins> 428 | </libpart> 429 | <libpart lib="device" part="TEST"> 430 | <description>Testpoint, connection for test equipment</description> 431 | <fields> 432 | <field name="Reference">TP</field> 433 | <field name="Value">TEST</field> 434 | </fields> 435 | <pins> 436 | <pin num="1" name="~" type="passive"/> 437 | </pins> 438 | </libpart> 439 | <libpart lib="conn" part="USB_OTG"> 440 | <description>USB mini/micro connector</description> 441 | <footprints> 442 | <fp>USB*</fp> 443 | </footprints> 444 | <fields> 445 | <field name="Reference">J</field> 446 | <field name="Value">USB_OTG</field> 447 | </fields> 448 | <pins> 449 | <pin num="1" name="VBUS" type="power_in"/> 450 | <pin num="2" name="D-" type="passive"/> 451 | <pin num="3" name="D+" type="passive"/> 452 | <pin num="4" name="ID" type="passive"/> 453 | <pin num="5" name="GND" type="power_in"/> 454 | <pin num="6" name="Shield" type="passive"/> 455 | </pins> 456 | </libpart> 457 | <libpart lib="tinyfpga" part="iCE40-LP8K-CM81"> 458 | <fields> 459 | <field name="Reference">U</field> 460 | <field name="Value">iCE40-LP8K-CM81</field> 461 | </fields> 462 | <pins> 463 | <pin num="A1" name="IOT_224" type="BiDi"/> 464 | <pin num="A2" name="IOT_221" type="BiDi"/> 465 | <pin num="A3" name="IOT_217" type="BiDi"/> 466 | <pin num="A4" name="IOT_208" type="BiDi"/> 467 | <pin num="A5" name="VCCIO_0" type="BiDi"/> 468 | <pin num="A6" name="IOT_185" type="BiDi"/> 469 | <pin num="A7" name="IOT_177" type="BiDi"/> 470 | <pin num="A8" name="IOT_174" type="BiDi"/> 471 | <pin num="A9" name="IOR_116" type="BiDi"/> 472 | <pin num="B1" name="IOL_3A" type="BiDi"/> 473 | <pin num="B2" name="IOL_2B" type="BiDi"/> 474 | <pin num="B3" name="IOT_218" type="BiDi"/> 475 | <pin num="B4" name="IOT_211" type="BiDi"/> 476 | <pin num="B5" name="IOT_188" type="BiDi"/> 477 | <pin num="B6" name="IOT_183" type="BiDi"/> 478 | <pin num="B7" name="IOT_180" type="BiDi"/> 479 | <pin num="B8" name="IOT_170" type="BiDi"/> 480 | <pin num="B9" name="IOR_120" type="BiDi"/> 481 | <pin num="C1" name="IOL_3B" type="BiDi"/> 482 | <pin num="C2" name="IOL_2A" type="BiDi"/> 483 | <pin num="C3" name="IOL_7B" type="BiDi"/> 484 | <pin num="C4" name="IOT_198_GBIN0" type="BiDi"/> 485 | <pin num="C5" name="IOT_197_GBIN1" type="BiDi"/> 486 | <pin num="C6" name="VCCIO_1" type="BiDi"/> 487 | <pin num="C7" name="VPP_FAST" type="BiDi"/> 488 | <pin num="C8" name="VPP_2V5" type="BiDi"/> 489 | <pin num="C9" name="IOR_148" type="BiDi"/> 490 | <pin num="D1" name="IOL_10A" type="BiDi"/> 491 | <pin num="D2" name="IOL_7A" type="BiDi"/> 492 | <pin num="D3" name="IOL_13B_GBIN7" type="BiDi"/> 493 | <pin num="D4" name="VCC" type="BiDi"/> 494 | <pin num="D5" name="IOT_212" type="BiDi"/> 495 | <pin num="D6" name="IOR_115" type="BiDi"/> 496 | <pin num="D7" name="IOR_117" type="BiDi"/> 497 | <pin num="D8" name="IOR_141_GBIN2" type="BiDi"/> 498 | <pin num="D9" name="IOR_119" type="BiDi"/> 499 | <pin num="E1" name="IOL_10B" type="BiDi"/> 500 | <pin num="E2" name="IOL_13A" type="BiDi"/> 501 | <pin num="E3" name="IOL_14A_GBIN6" type="BiDi"/> 502 | <pin num="E4" name="IOL_14B" type="BiDi"/> 503 | <pin num="E5" name="IOT_214" type="BiDi"/> 504 | <pin num="E6" name="CDONE" type="BiDi"/> 505 | <pin num="E7" name="IOR_118" type="BiDi"/> 506 | <pin num="E8" name="IOR_140_GBIN3" type="BiDi"/> 507 | <pin num="E9" name="VCC" type="BiDi"/> 508 | <pin num="F1" name="IOL_22A" type="BiDi"/> 509 | <pin num="F2" name="VCC" type="BiDi"/> 510 | <pin num="F3" name="IOL_22B" type="BiDi"/> 511 | <pin num="F4" name="GND" type="BiDi"/> 512 | <pin num="F5" name="GND" type="BiDi"/> 513 | <pin num="F6" name="GND" type="BiDi"/> 514 | <pin num="F7" name="IOB_108_SS" type="BiDi"/> 515 | <pin num="F8" name="IOR_113" type="BiDi"/> 516 | <pin num="F9" name="GND" type="BiDi"/> 517 | <pin num="G1" name="IOL_24B" type="BiDi"/> 518 | <pin num="G2" name="IOL_26A" type="BiDi"/> 519 | <pin num="G3" name="IOL_24A" type="BiDi"/> 520 | <pin num="G4" name="IOB_81_GBIN5" type="BiDi"/> 521 | <pin num="G5" name="IOB_103_CBSEL0" type="BiDi"/> 522 | <pin num="G6" name="IOB_105_SDO" type="BiDi"/> 523 | <pin num="G7" name="IOB_107_SCK" type="BiDi"/> 524 | <pin num="G8" name="IOR_114" type="BiDi"/> 525 | <pin num="G9" name="IOR_112" type="BiDi"/> 526 | <pin num="H1" name="IOB_54" type="BiDi"/> 527 | <pin num="H2" name="IOL_26B" type="BiDi"/> 528 | <pin num="H3" name="VCCIO_3" type="BiDi"/> 529 | <pin num="H4" name="IOB_82_GBIN4" type="BiDi"/> 530 | <pin num="H5" name="IOB_104_CBSEL1" type="BiDi"/> 531 | <pin num="H6" name="CRESET_B" type="BiDi"/> 532 | <pin num="H7" name="IOB_106_SDI" type="BiDi"/> 533 | <pin num="H8" name="VCC_SPI" type="BiDi"/> 534 | <pin num="H9" name="IOR_111" type="BiDi"/> 535 | <pin num="J1" name="IOB_55" type="BiDi"/> 536 | <pin num="J2" name="IOB_56" type="BiDi"/> 537 | <pin num="J3" name="IOB_57" type="BiDi"/> 538 | <pin num="J4" name="IOB_70" type="BiDi"/> 539 | <pin num="J5" name="VCCIO_2" type="BiDi"/> 540 | <pin num="J6" name="GNDPLL0" type="BiDi"/> 541 | <pin num="J7" name="VCCPLL0" type="BiDi"/> 542 | <pin num="J8" name="IOR_109" type="BiDi"/> 543 | <pin num="J9" name="IOR_110" type="BiDi"/> 544 | </pins> 545 | </libpart> 546 | </libparts> 547 | <libraries> 548 | <library logical="conn"> 549 | <uri>C:\Program Files\KiCad\share\kicad\library\conn.lib</uri> 550 | </library> 551 | <library logical="device"> 552 | <uri>C:\Program Files\KiCad\share\kicad\library\device.lib</uri> 553 | </library> 554 | <library logical="switches"> 555 | <uri>C:\Program Files\KiCad\share\kicad\library\switches.lib</uri> 556 | </library> 557 | <library logical="tinyfpga"> 558 | <uri>C:\Users\lvale\Documents\TinyFPGA\tinyfpga.lib</uri> 559 | </library> 560 | </libraries> 561 | <nets> 562 | <net code="1" name="SDI"> 563 | <node ref="J2" pin="13"/> 564 | <node ref="U1" pin="H7"/> 565 | <node ref="U5" pin="5"/> 566 | <node ref="U1" pin="J8"/> 567 | </net> 568 | <net code="2" name="SS"> 569 | <node ref="U1" pin="G9"/> 570 | <node ref="U1" pin="F7"/> 571 | <node ref="J2" pin="11"/> 572 | <node ref="U5" pin="1"/> 573 | <node ref="U1" pin="F8"/> 574 | <node ref="R5" pin="2"/> 575 | </net> 576 | <net code="3" name="SDO"> 577 | <node ref="U1" pin="H4"/> 578 | <node ref="U1" pin="G6"/> 579 | <node ref="J2" pin="14"/> 580 | <node ref="U1" pin="G5"/> 581 | <node ref="U1" pin="J3"/> 582 | <node ref="U5" pin="2"/> 583 | </net> 584 | <net code="4" name="SCK"> 585 | <node ref="U1" pin="G8"/> 586 | <node ref="U5" pin="6"/> 587 | <node ref="U1" pin="G7"/> 588 | <node ref="U1" pin="H9"/> 589 | <node ref="J2" pin="12"/> 590 | </net> 591 | <net code="5" name="+3V3"> 592 | <node ref="C15" pin="1"/> 593 | <node ref="C14" pin="1"/> 594 | <node ref="U1" pin="B7"/> 595 | <node ref="U1" pin="B6"/> 596 | <node ref="U1" pin="B8"/> 597 | <node ref="C16" pin="1"/> 598 | <node ref="U1" pin="J2"/> 599 | <node ref="U1" pin="B9"/> 600 | <node ref="R5" pin="1"/> 601 | <node ref="R6" pin="1"/> 602 | <node ref="U1" pin="C6"/> 603 | <node ref="U1" pin="J5"/> 604 | <node ref="U1" pin="A5"/> 605 | <node ref="U1" pin="H3"/> 606 | <node ref="U1" pin="H8"/> 607 | <node ref="U1" pin="C8"/> 608 | <node ref="C2" pin="1"/> 609 | <node ref="C8" pin="1"/> 610 | <node ref="C4" pin="1"/> 611 | <node ref="U4" pin="3"/> 612 | <node ref="J2" pin="2"/> 613 | <node ref="C5" pin="1"/> 614 | <node ref="U1" pin="J9"/> 615 | <node ref="C9" pin="1"/> 616 | <node ref="C10" pin="1"/> 617 | <node ref="R1" pin="2"/> 618 | <node ref="U3" pin="4"/> 619 | <node ref="U3" pin="1"/> 620 | <node ref="U5" pin="8"/> 621 | <node ref="U2" pin="5"/> 622 | <node ref="U2" pin="4"/> 623 | <node ref="U4" pin="1"/> 624 | </net> 625 | <net code="6" name="+1V2"> 626 | <node ref="C11" pin="1"/> 627 | <node ref="U1" pin="D4"/> 628 | <node ref="U4" pin="5"/> 629 | <node ref="C12" pin="1"/> 630 | <node ref="J2" pin="3"/> 631 | <node ref="C13" pin="1"/> 632 | <node ref="R4" pin="2"/> 633 | <node ref="U1" pin="F1"/> 634 | <node ref="U1" pin="F2"/> 635 | <node ref="U1" pin="D2"/> 636 | <node ref="U1" pin="E2"/> 637 | <node ref="U1" pin="D3"/> 638 | <node ref="C3" pin="1"/> 639 | <node ref="U1" pin="E9"/> 640 | </net> 641 | <net code="7" name="Net-(C6-Pad1)"> 642 | <node ref="C7" pin="1"/> 643 | <node ref="U1" pin="J6"/> 644 | <node ref="C6" pin="1"/> 645 | </net> 646 | <net code="8" name="Net-(C6-Pad2)"> 647 | <node ref="U1" pin="J7"/> 648 | <node ref="R4" pin="1"/> 649 | <node ref="C6" pin="2"/> 650 | <node ref="C7" pin="2"/> 651 | </net> 652 | <net code="9" name="Net-(J3-Pad1)"> 653 | <node ref="L1" pin="2"/> 654 | <node ref="J3" pin="1"/> 655 | </net> 656 | <net code="10" name="Net-(J3-Pad2)"> 657 | <node ref="J3" pin="2"/> 658 | <node ref="R3" pin="2"/> 659 | </net> 660 | <net code="11" name="Net-(J3-Pad3)"> 661 | <node ref="R1" pin="1"/> 662 | <node ref="R2" pin="2"/> 663 | <node ref="J3" pin="3"/> 664 | </net> 665 | <net code="12" name="CLK"> 666 | <node ref="U1" pin="B4"/> 667 | <node ref="U1" pin="C4"/> 668 | <node ref="U1" pin="B5"/> 669 | <node ref="U1" pin="C5"/> 670 | <node ref="U3" pin="3"/> 671 | <node ref="J1" pin="4"/> 672 | </net> 673 | <net code="13" name="USB_P"> 674 | <node ref="U1" pin="A3"/> 675 | <node ref="J1" pin="2"/> 676 | <node ref="R2" pin="1"/> 677 | </net> 678 | <net code="14" name="USB_N"> 679 | <node ref="U1" pin="A4"/> 680 | <node ref="J1" pin="3"/> 681 | <node ref="R3" pin="1"/> 682 | </net> 683 | <net code="15" name="174"> 684 | <node ref="J2" pin="6"/> 685 | <node ref="U1" pin="A8"/> 686 | </net> 687 | <net code="16" name="116"> 688 | <node ref="U1" pin="A9"/> 689 | <node ref="J2" pin="7"/> 690 | </net> 691 | <net code="17" name="141_GBIN2"> 692 | <node ref="U1" pin="E8"/> 693 | <node ref="U1" pin="D7"/> 694 | <node ref="U1" pin="E7"/> 695 | <node ref="J2" pin="8"/> 696 | <node ref="U1" pin="D8"/> 697 | </net> 698 | <net code="18" name="148"> 699 | <node ref="J2" pin="9"/> 700 | <node ref="U1" pin="C9"/> 701 | </net> 702 | <net code="19" name="119"> 703 | <node ref="U1" pin="D9"/> 704 | <node ref="J2" pin="10"/> 705 | </net> 706 | <net code="20" name="177"> 707 | <node ref="U1" pin="A7"/> 708 | <node ref="J2" pin="5"/> 709 | </net> 710 | <net code="21" name="+5V"> 711 | <node ref="C1" pin="1"/> 712 | <node ref="J2" pin="1"/> 713 | <node ref="C17" pin="1"/> 714 | <node ref="U2" pin="3"/> 715 | <node ref="U2" pin="1"/> 716 | <node ref="L1" pin="1"/> 717 | </net> 718 | <net code="22" name="185"> 719 | <node ref="U1" pin="A6"/> 720 | <node ref="J2" pin="4"/> 721 | </net> 722 | <net code="23" name="Net-(R7-Pad1)"> 723 | <node ref="U5" pin="3"/> 724 | <node ref="R7" pin="1"/> 725 | <node ref="TP1" pin="1"/> 726 | </net> 727 | <net code="24" name="3A"> 728 | <node ref="J1" pin="8"/> 729 | <node ref="U1" pin="B1"/> 730 | </net> 731 | <net code="25" name="3B"> 732 | <node ref="U1" pin="C1"/> 733 | <node ref="J1" pin="9"/> 734 | </net> 735 | <net code="26" name="10A"> 736 | <node ref="J1" pin="10"/> 737 | <node ref="U1" pin="D1"/> 738 | </net> 739 | <net code="27" name="24B"> 740 | <node ref="J1" pin="12"/> 741 | <node ref="U1" pin="G1"/> 742 | </net> 743 | <net code="28" name="54"> 744 | <node ref="J1" pin="13"/> 745 | <node ref="U1" pin="H1"/> 746 | </net> 747 | <net code="29" name="55"> 748 | <node ref="J1" pin="14"/> 749 | <node ref="U1" pin="J1"/> 750 | </net> 751 | <net code="30" name="224"> 752 | <node ref="U1" pin="A1"/> 753 | <node ref="J1" pin="7"/> 754 | </net> 755 | <net code="31" name="2B"> 756 | <node ref="U1" pin="B2"/> 757 | <node ref="J1" pin="5"/> 758 | <node ref="U1" pin="C2"/> 759 | <node ref="U1" pin="C3"/> 760 | <node ref="U1" pin="B3"/> 761 | </net> 762 | <net code="32" name="221"> 763 | <node ref="U1" pin="A2"/> 764 | <node ref="J1" pin="6"/> 765 | </net> 766 | <net code="33" name="CRESET_B"> 767 | <node ref="SW1" pin="2"/> 768 | <node ref="U1" pin="H5"/> 769 | <node ref="R6" pin="2"/> 770 | <node ref="U1" pin="J4"/> 771 | <node ref="TP2" pin="1"/> 772 | <node ref="U1" pin="H6"/> 773 | </net> 774 | <net code="34" name="VPP_FAST"> 775 | <node ref="U1" pin="C7"/> 776 | </net> 777 | <net code="35" name="CDONE"> 778 | <node ref="U1" pin="E6"/> 779 | </net> 780 | <net code="36" name="115"> 781 | <node ref="U1" pin="D6"/> 782 | </net> 783 | <net code="37" name="10B"> 784 | <node ref="J1" pin="11"/> 785 | <node ref="U1" pin="E1"/> 786 | </net> 787 | <net code="38" name="Net-(U1-PadE3)"> 788 | <node ref="U1" pin="E3"/> 789 | </net> 790 | <net code="39" name="Net-(U1-PadF3)"> 791 | <node ref="U1" pin="F3"/> 792 | </net> 793 | <net code="40" name="GND"> 794 | <node ref="C1" pin="2"/> 795 | <node ref="C5" pin="2"/> 796 | <node ref="C9" pin="2"/> 797 | <node ref="C10" pin="2"/> 798 | <node ref="U1" pin="E4"/> 799 | <node ref="C11" pin="2"/> 800 | <node ref="J1" pin="1"/> 801 | <node ref="C2" pin="2"/> 802 | <node ref="C8" pin="2"/> 803 | <node ref="C3" pin="2"/> 804 | <node ref="R7" pin="2"/> 805 | <node ref="C17" pin="2"/> 806 | <node ref="C13" pin="2"/> 807 | <node ref="C16" pin="2"/> 808 | <node ref="C15" pin="2"/> 809 | <node ref="C14" pin="2"/> 810 | <node ref="C4" pin="2"/> 811 | <node ref="J3" pin="5"/> 812 | <node ref="U3" pin="2"/> 813 | <node ref="U5" pin="4"/> 814 | <node ref="U4" pin="2"/> 815 | <node ref="U1" pin="F4"/> 816 | <node ref="SW1" pin="1"/> 817 | <node ref="J3" pin="6"/> 818 | <node ref="U1" pin="F5"/> 819 | <node ref="U1" pin="F6"/> 820 | <node ref="U1" pin="F9"/> 821 | <node ref="U2" pin="2"/> 822 | <node ref="U1" pin="E5"/> 823 | <node ref="C12" pin="2"/> 824 | </net> 825 | <net code="41" name="Net-(U5-Pad7)"> 826 | <node ref="U5" pin="7"/> 827 | </net> 828 | <net code="42" name="Net-(J3-Pad4)"> 829 | <node ref="J3" pin="4"/> 830 | </net> 831 | <net code="43" name="Net-(U4-Pad4)"> 832 | <node ref="U4" pin="4"/> 833 | </net> 834 | <net code="44" name="81_GBIN5"> 835 | <node ref="U1" pin="G4"/> 836 | </net> 837 | <net code="45" name="26A"> 838 | <node ref="U1" pin="G2"/> 839 | </net> 840 | <net code="46" name="24A"> 841 | <node ref="U1" pin="G3"/> 842 | </net> 843 | <net code="47" name="26B"> 844 | <node ref="U1" pin="H2"/> 845 | </net> 846 | <net code="48" name="212"> 847 | <node ref="U1" pin="D5"/> 848 | </net> 849 | </nets> 850 | </export> 851 | -------------------------------------------------------------------------------- /board/tinyfpga.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | DEF MachXO2-1200-QFN32 U 0 40 Y Y 1 L N 3 | F0 "U" 150 250 60 H V R CNN 4 | F1 "MachXO2-1200-QFN32" 150 150 60 H V R CNN 5 | DRAW 6 | X VCCIO3 6 2000 1100 200 D 50 50 1 1 B 7 | X VCCIO2 7 1900 1100 200 D 50 50 1 1 B 8 | X VCCIO2 15 1800 1100 200 D 50 50 1 1 B 9 | X VCC 18 1700 1100 200 D 50 50 1 1 B 10 | X VCCIO1 19 1600 1100 200 D 50 50 1 1 B 11 | X VCCIO0 24 1500 1100 200 D 50 50 1 1 B 12 | X VCCIO0 31 1400 1100 200 D 50 50 1 1 B 13 | X VCC 2 1300 1100 200 D 50 50 1 1 B 14 | X PR5D 20 3200 -1000 200 L 50 50 1 1 B 15 | X PR5C 21 3200 -900 200 L 50 50 1 1 B 16 | X PT17D/DONE 23 3200 -800 200 L 50 50 1 1 B 17 | X PT15D/PROGRAMN 25 3200 -700 200 L 50 50 1 1 B 18 | X PT15C/JTAGENB 26 3200 -600 200 L 50 50 1 1 B 19 | X PT12D/SDA 27 3200 -500 200 L 50 50 1 1 B 20 | X PT12C/SCL 28 3200 -400 200 L 50 50 1 1 B 21 | X PT11D/TMS 29 3200 -300 200 L 50 50 1 1 B 22 | X PT11C/TCK 30 3200 -200 200 L 50 50 1 1 B 23 | X PT10D/TDI 32 3200 -100 200 L 50 50 1 1 B 24 | X PT10C/TDO 1 3200 0 200 L 50 50 1 1 B 25 | X GND 3 1500 -2100 200 U 50 50 1 1 B 26 | X GND 22 1600 -2100 200 U 50 50 1 1 B 27 | X GND 33 1700 -2100 200 U 50 50 1 1 B 28 | X PL9A 4 0 0 200 R 50 50 1 1 B 29 | X PL9B 5 0 -100 200 R 50 50 1 1 B 30 | X PB4C/CS 8 0 -200 200 R 50 50 1 1 B 31 | X PB6C/SCLK 9 0 -300 200 R 50 50 1 1 B 32 | X PB6D/MISO 10 0 -400 200 R 50 50 1 1 B 33 | X PB9A 11 0 -500 200 R 50 50 1 1 B 34 | X PB9B 12 0 -600 200 R 50 50 1 1 B 35 | X PB11A 13 0 -700 200 R 50 50 1 1 B 36 | X PB11B 14 0 -800 200 R 50 50 1 1 B 37 | X PB20C/SN 16 0 -900 200 R 50 50 1 1 B 38 | X PB20D/MOSI 17 0 -1000 200 R 50 50 1 1 B 39 | S 200 900 3000 -1900 1 1 12 N 40 | ENDDRAW 41 | ENDDEF 42 | DEF iCE40-LP8K-CM81 U 0 40 Y Y 8 L N 43 | F0 "U" 200 250 60 H V L CNN 44 | F1 "iCE40-LP8K-CM81" 200 150 60 H V L CNN 45 | DRAW 46 | X VPP_FAST C7 0 0 200 R 50 50 1 1 B 47 | X VPP_2V5 C8 0 -100 200 R 50 50 1 1 B 48 | X CDONE E6 0 -200 200 R 50 50 1 1 B 49 | X IOB_103_CBSEL0 G5 0 -300 200 R 50 50 1 1 B 50 | X IOB_105_SDO G6 0 -400 200 R 50 50 1 1 B 51 | X IOB_107_SCK G7 0 -500 200 R 50 50 1 1 B 52 | X IOB_104_CBSEL1 H5 0 -600 200 R 50 50 1 1 B 53 | X CRESET_B H6 0 -700 200 R 50 50 1 1 B 54 | X IOB_106_SDI H7 0 -800 200 R 50 50 1 1 B 55 | X VCC_SPI H8 0 -900 200 R 50 50 1 1 B 56 | S 200 100 1000 -1000 1 1 12 N 57 | X GND F4 0 0 200 R 50 50 2 1 B 58 | X GND F5 0 -100 200 R 50 50 2 1 B 59 | X GND F6 0 -200 200 R 50 50 2 1 B 60 | X GND F9 0 -300 200 R 50 50 2 1 B 61 | S 200 100 500 -400 2 1 12 N 62 | X IOB_108_SS F7 0 0 200 R 50 50 3 1 B 63 | X IOB_81_GBIN5 G4 0 -100 200 R 50 50 3 1 B 64 | X IOB_54 H1 0 -200 200 R 50 50 3 1 B 65 | X IOB_82_GBIN4 H4 0 -300 200 R 50 50 3 1 B 66 | X IOB_55 J1 0 -400 200 R 50 50 3 1 B 67 | X IOB_56 J2 0 -500 200 R 50 50 3 1 B 68 | X IOB_57 J3 0 -600 200 R 50 50 3 1 B 69 | X IOB_70 J4 0 -700 200 R 50 50 3 1 B 70 | S 200 100 900 -800 3 1 12 N 71 | X IOL_3A B1 0 0 200 R 50 50 4 1 B 72 | X IOL_2B B2 0 -100 200 R 50 50 4 1 B 73 | X IOL_3B C1 0 -200 200 R 50 50 4 1 B 74 | X IOL_2A C2 0 -300 200 R 50 50 4 1 B 75 | X IOL_7B C3 0 -400 200 R 50 50 4 1 B 76 | X IOL_10A D1 0 -500 200 R 50 50 4 1 B 77 | X IOL_7A D2 0 -600 200 R 50 50 4 1 B 78 | X IOL_13B_GBIN7 D3 0 -700 200 R 50 50 4 1 B 79 | X IOL_10B E1 0 -800 200 R 50 50 4 1 B 80 | X IOL_13A E2 0 -900 200 R 50 50 4 1 B 81 | X IOL_14A_GBIN6 E3 0 -1000 200 R 50 50 4 1 B 82 | X IOL_14B E4 0 -1100 200 R 50 50 4 1 B 83 | X IOL_22A F1 0 -1200 200 R 50 50 4 1 B 84 | X IOL_22B F3 0 -1300 200 R 50 50 4 1 B 85 | X IOL_24B G1 0 -1400 200 R 50 50 4 1 B 86 | X IOL_26A G2 0 -1500 200 R 50 50 4 1 B 87 | X IOL_24A G3 0 -1600 200 R 50 50 4 1 B 88 | X IOL_26B H2 0 -1700 200 R 50 50 4 1 B 89 | S 200 100 1000 -1800 4 1 12 N 90 | X IOR_116 A9 0 0 200 R 50 50 5 1 B 91 | X IOR_120 B9 0 -100 200 R 50 50 5 1 B 92 | X IOR_148 C9 0 -200 200 R 50 50 5 1 B 93 | X IOR_115 D6 0 -300 200 R 50 50 5 1 B 94 | X IOR_117 D7 0 -400 200 R 50 50 5 1 B 95 | X IOR_141_GBIN2 D8 0 -500 200 R 50 50 5 1 B 96 | X IOR_119 D9 0 -600 200 R 50 50 5 1 B 97 | X IOR_118 E7 0 -700 200 R 50 50 5 1 B 98 | X IOR_140_GBIN3 E8 0 -800 200 R 50 50 5 1 B 99 | X IOR_113 F8 0 -900 200 R 50 50 5 1 B 100 | X IOR_114 G8 0 -1000 200 R 50 50 5 1 B 101 | X IOR_112 G9 0 -1100 200 R 50 50 5 1 B 102 | X IOR_111 H9 0 -1200 200 R 50 50 5 1 B 103 | X IOR_109 J8 0 -1300 200 R 50 50 5 1 B 104 | X IOR_110 J9 0 -1400 200 R 50 50 5 1 B 105 | S 200 100 1000 -1500 5 1 12 N 106 | X IOT_224 A1 0 0 200 R 50 50 6 1 B 107 | X IOT_221 A2 0 -100 200 R 50 50 6 1 B 108 | X IOT_217 A3 0 -200 200 R 50 50 6 1 B 109 | X IOT_208 A4 0 -300 200 R 50 50 6 1 B 110 | X IOT_185 A6 0 -400 200 R 50 50 6 1 B 111 | X IOT_177 A7 0 -500 200 R 50 50 6 1 B 112 | X IOT_174 A8 0 -600 200 R 50 50 6 1 B 113 | X IOT_218 B3 0 -700 200 R 50 50 6 1 B 114 | X IOT_211 B4 0 -800 200 R 50 50 6 1 B 115 | X IOT_188 B5 0 -900 200 R 50 50 6 1 B 116 | X IOT_183 B6 0 -1000 200 R 50 50 6 1 B 117 | X IOT_180 B7 0 -1100 200 R 50 50 6 1 B 118 | X IOT_170 B8 0 -1200 200 R 50 50 6 1 B 119 | X IOT_198_GBIN0 C4 0 -1300 200 R 50 50 6 1 B 120 | X IOT_197_GBIN1 C5 0 -1400 200 R 50 50 6 1 B 121 | X IOT_212 D5 0 -1500 200 R 50 50 6 1 B 122 | X IOT_214 E5 0 -1600 200 R 50 50 6 1 B 123 | S 200 100 1000 -1700 6 1 12 N 124 | X GNDPLL0 J6 0 0 200 R 50 50 7 1 B 125 | X VCCPLL0 J7 0 -100 200 R 50 50 7 1 B 126 | S 200 100 700 -200 7 1 12 N 127 | X VCCIO_0 A5 0 0 200 R 50 50 8 1 B 128 | X VCCIO_1 C6 0 -100 200 R 50 50 8 1 B 129 | X VCC D4 0 -200 200 R 50 50 8 1 B 130 | X VCC E9 0 -300 200 R 50 50 8 1 B 131 | X VCC F2 0 -400 200 R 50 50 8 1 B 132 | X VCCIO_3 H3 0 -500 200 R 50 50 8 1 B 133 | X VCCIO_2 J5 0 -600 200 R 50 50 8 1 B 134 | S 200 100 700 -700 8 1 12 N 135 | ENDDRAW 136 | ENDDEF 137 | DEF MIC5365-1.2YC5-TR U 0 40 Y Y 1 L N 138 | F0 "U" 200 250 60 H V L CNN 139 | F1 "MIC5365-1.2YC5-TR" 200 150 60 H V L CNN 140 | DRAW 141 | X GND 2 600 -700 200 U 50 50 1 1 B 142 | X VOUT 5 1200 -100 200 L 50 50 1 1 B 143 | X NC 4 1200 0 200 L 50 50 1 1 B 144 | X VIN 1 0 0 200 R 50 50 1 1 B 145 | X EN 3 0 -100 200 R 50 50 1 1 B 146 | S 200 100 1000 -500 1 1 12 N 147 | ENDDRAW 148 | ENDDEF 149 | DEF MIC5504-3.3YM5-TR U 0 40 Y Y 1 L N 150 | F0 "U" 200 250 60 H V L CNN 151 | F1 "MIC5504-3.3YM5-TR" 200 150 60 H V L CNN 152 | DRAW 153 | X GND 2 600 -700 200 U 50 50 1 1 B 154 | X VOUT 5 1200 -100 200 L 50 50 1 1 B 155 | X NC 4 1200 0 200 L 50 50 1 1 B 156 | X VIN 1 0 0 200 R 50 50 1 1 B 157 | X EN 3 0 -100 200 R 50 50 1 1 B 158 | S 200 100 1000 -500 1 1 12 N 159 | ENDDRAW 160 | ENDDEF 161 | DEF DSC6001CI2A-016.0000T U 0 40 Y Y 1 L N 162 | F0 "U" 150 250 60 H V R CNN 163 | F1 "DSC6001CI2A-016.0000T" 150 150 60 H V R CNN 164 | DRAW 165 | X VDD 4 600 600 200 D 50 50 1 1 B 166 | X GND 2 600 -600 200 U 50 50 1 1 B 167 | X OUT 3 1200 0 200 L 50 50 1 1 B 168 | X OE 1 0 0 200 R 50 50 1 1 B 169 | S 200 400 1000 -400 1 1 12 N 170 | ENDDRAW 171 | ENDDEF 172 | DEF AT25SF041-SSHD-B U 0 40 Y Y 1 L N 173 | F0 "U" 150 250 60 H V R CNN 174 | F1 "AT25SF041-SSHD-B" 150 150 60 H V R CNN 175 | DRAW 176 | X VCC 8 700 600 200 D 50 50 1 1 B 177 | X !CS 1 1400 -300 200 L 50 50 1 1 B 178 | X SO 2 1400 -200 200 L 50 50 1 1 B 179 | X SI 5 1400 -100 200 L 50 50 1 1 B 180 | X SCK 6 1400 0 200 L 50 50 1 1 B 181 | X GND 4 700 -900 200 U 50 50 1 1 B 182 | X !WP 3 0 -100 200 R 50 50 1 1 B 183 | X !HOLD 7 0 -200 200 R 50 50 1 1 B 184 | S 200 400 1200 -700 1 1 12 N 185 | ENDDRAW 186 | ENDDEF 187 | -------------------------------------------------------------------------------- /board/tinyfpga.pretty/CDFN3225-4LD-PL-1.kicad_mod: -------------------------------------------------------------------------------- 1 | (module CDFN3225-4LD-PL-1 (layer F.Cu) (tedit 591AA274) 2 | (fp_text reference REF** (at 0 3.05) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value CDFN3225-4LD-PL-1 (at 0 -2.85) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_circle (center -2.361386 1.541754) (end -2.161386 1.391754) (layer F.Fab) (width 0.15)) 9 | (fp_line (start 1.438614 1.041754) (end -1.761386 1.041754) (layer F.Fab) (width 0.15)) 10 | (fp_line (start 1.438614 -1.458246) (end 1.438614 1.041754) (layer F.Fab) (width 0.15)) 11 | (fp_line (start -1.761386 -1.458246) (end 1.438614 -1.458246) (layer F.Fab) (width 0.15)) 12 | (fp_line (start -1.761386 1.041754) (end -1.761386 -1.458246) (layer F.Fab) (width 0.15)) 13 | (pad 1 smd rect (at -1.211386 0.741754 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask)) 14 | (pad 4 smd rect (at -1.211386 -1.158246 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at 0.888614 -1.158246 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask)) 16 | (pad 2 smd rect (at 0.888614 0.741754 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask)) 17 | ) 18 | -------------------------------------------------------------------------------- /board/tinyfpga.pretty/CM81.kicad_mod: -------------------------------------------------------------------------------- 1 | (module CM81 (layer F.Cu) (tedit 5902DC62) 2 | (clearance 0.102) 3 | (fp_text reference REF** (at 1.6 6.4) (layer F.SilkS) 4 | (effects (font (size 1 1) (thickness 0.15))) 5 | ) 6 | (fp_text value CM81 (at 1.6 0.8) (layer F.Fab) 7 | (effects (font (size 1 1) (thickness 0.15))) 8 | ) 9 | (fp_line (start -0.4 2.4) (end -0.4 5.6) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -0.4 5.6) (end 3.6 5.6) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 3.6 5.6) (end 3.6 1.6) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 3.6 1.6) (end 0.4 1.6) (layer F.SilkS) (width 0.15)) 13 | (pad A1 smd circle (at 0 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 14 | (pad A2 smd circle (at 0.4 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 15 | (pad A3 smd circle (at 0.8 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 16 | (pad A4 smd circle (at 1.2 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 17 | (pad A5 smd circle (at 1.6 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 18 | (pad A6 smd circle (at 2 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 19 | (pad A7 smd circle (at 2.4 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 20 | (pad A8 smd circle (at 2.8 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 21 | (pad A9 smd circle (at 3.2 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 22 | (pad B1 smd circle (at 0 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 23 | (pad B2 smd circle (at 0.4 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 24 | (pad B3 smd circle (at 0.8 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 25 | (pad B4 smd circle (at 1.2 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 26 | (pad B5 smd circle (at 1.6 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 27 | (pad B6 smd circle (at 2 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 28 | (pad B7 smd circle (at 2.4 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 29 | (pad B8 smd circle (at 2.8 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 30 | (pad B9 smd circle (at 3.2 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 31 | (pad C1 smd circle (at 0 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 32 | (pad C2 smd circle (at 0.4 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 33 | (pad C3 smd circle (at 0.8 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 34 | (pad C4 smd circle (at 1.2 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 35 | (pad C5 smd circle (at 1.6 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 36 | (pad C6 smd circle (at 2 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 37 | (pad C7 smd circle (at 2.4 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 38 | (pad C8 smd circle (at 2.8 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 39 | (pad C9 smd circle (at 3.2 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 40 | (pad D1 smd circle (at 0 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 41 | (pad D2 smd circle (at 0.4 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 42 | (pad D3 smd circle (at 0.8 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 43 | (pad D4 smd circle (at 1.2 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 44 | (pad D5 smd circle (at 1.6 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 45 | (pad D6 smd circle (at 2 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 46 | (pad D7 smd circle (at 2.4 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 47 | (pad D8 smd circle (at 2.8 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 48 | (pad D9 smd circle (at 3.2 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 49 | (pad E1 smd circle (at 0 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 50 | (pad E2 smd circle (at 0.4 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 51 | (pad E3 smd circle (at 0.8 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 52 | (pad E4 smd circle (at 1.2 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 53 | (pad E5 smd circle (at 1.6 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 54 | (pad E6 smd circle (at 2 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 55 | (pad E7 smd circle (at 2.4 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 56 | (pad E8 smd circle (at 2.8 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 57 | (pad E9 smd circle (at 3.2 3.6) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 58 | (pad F1 smd circle (at 0 4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 59 | (pad F2 smd circle (at 0.4 4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask)) 60 | (pad F3 smd circle (at 0.8 4) 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StepUp wrl exported 3 | 4 | # Copyright (C) 2017, kicad StepUp 5 | # 6 | # This program is free software: you can redistribute it and/or modify 7 | # it under the terms of the GNU General Public License as published by 8 | # the Free Software Foundation, either version 3 of the License, or 9 | # any later version. 10 | # 11 | # This program is distributed in the hope that it will be useful, 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | # GNU General Public License for more details. 15 | # 16 | # You should have received a copy of the GNU General Public License 17 | # along with this program. If not, see http://www.gnu.org/licenses/. 18 | # 19 | # As a special exception, if you create a design which uses this symbol, 20 | # and embed this symbol or unaltered portions of this symbol into the design, 21 | # this symbol does not by itself cause the resulting design to be covered by 22 | # the GNU General Public License. 23 | # This exception does not however invalidate any other reasons why the design 24 | # itself might be covered by the GNU General Public License. 25 | # If you modify this symbol, you may extend this exception to your version of the symbol, 26 | # but you are not obligated to do so. 27 | # If you do not wish to do so, delete this exception statement from your version 28 | # Risk disclaimer 29 | # *USE 3D CAD DATA AT YOUR OWN RISK* 30 | # *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* 31 | # 32 | Shape { 33 | appearance Appearance {material DEF PIN-01 Material { 34 | ambientIntensity 0.271 35 | diffuseColor 0.824 0.82 0.781 36 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8 | (fp_line (start -2.5 -1.5) (end -1.5 -2.5) (layer F.Fab) (width 0.15)) 9 | (fp_line (start -2.5 2.5) (end -2.5 -1.5) (layer F.Fab) (width 0.15)) 10 | (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.Fab) (width 0.15)) 11 | (fp_line (start 2.5 -2.5) (end 2.5 2.5) (layer F.Fab) (width 0.15)) 12 | (fp_line (start -1.5 -2.5) (end 2.5 -2.5) (layer F.Fab) (width 0.15)) 13 | (fp_line (start -1.25 0) (end 1.25 0) (layer F.Mask) (width 0.3)) 14 | (fp_line (start -1.35 1.35) (end -1.35 -1.35) (layer F.Mask) (width 0.15)) 15 | (fp_line (start 1.35 1.35) (end -1.35 1.35) (layer F.Mask) (width 0.15)) 16 | (fp_line (start 1.35 -1.35) (end 1.35 1.35) (layer F.Mask) (width 0.15)) 17 | (fp_line (start -1.35 -1.35) (end 1.35 -1.35) (layer F.Mask) (width 0.15)) 18 | (fp_line (start 0 -1.25) (end 0 1.25) (layer F.Mask) (width 0.3)) 19 | (pad 32 smd oval (at -1.75 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 20 | (solder_mask_margin 0.07)) 21 | (pad 31 smd oval (at -1.25 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 22 | (solder_mask_margin 0.07)) 23 | (pad 30 smd oval (at -0.75 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 24 | (solder_mask_margin 0.07)) 25 | (pad 29 smd oval (at -0.25 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 26 | (solder_mask_margin 0.07)) 27 | (pad 28 smd oval (at 0.25 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 28 | (solder_mask_margin 0.07)) 29 | (pad 27 smd oval (at 0.75 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 30 | (solder_mask_margin 0.07)) 31 | (pad 26 smd oval (at 1.25 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 32 | (solder_mask_margin 0.07)) 33 | (pad 25 smd oval (at 1.75 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 34 | (solder_mask_margin 0.07)) 35 | (pad 24 smd oval (at 2.5 -1.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 36 | (solder_mask_margin 0.07)) 37 | (pad 23 smd oval (at 2.5 -1.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 38 | (solder_mask_margin 0.07)) 39 | (pad 22 smd oval (at 2.5 -0.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 40 | (solder_mask_margin 0.07)) 41 | (pad 21 smd oval (at 2.5 -0.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 42 | (solder_mask_margin 0.07)) 43 | (pad 20 smd oval (at 2.5 0.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 44 | (solder_mask_margin 0.07)) 45 | (pad 19 smd oval (at 2.5 0.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 46 | (solder_mask_margin 0.07)) 47 | (pad 18 smd oval (at 2.5 1.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 48 | (solder_mask_margin 0.07)) 49 | (pad 17 smd oval (at 2.5 1.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 50 | (solder_mask_margin 0.07)) 51 | (pad 16 smd oval (at 1.75 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 52 | (solder_mask_margin 0.07)) 53 | (pad 15 smd oval (at 1.25 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 54 | (solder_mask_margin 0.07)) 55 | (pad 14 smd oval (at 0.75 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 56 | (solder_mask_margin 0.07)) 57 | (pad 13 smd oval (at 0.25 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 58 | (solder_mask_margin 0.07)) 59 | (pad 12 smd oval (at -0.25 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 60 | (solder_mask_margin 0.07)) 61 | (pad 11 smd oval (at -0.75 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 62 | (solder_mask_margin 0.07)) 63 | (pad 10 smd oval (at -1.25 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 64 | (solder_mask_margin 0.07)) 65 | (pad 9 smd oval (at -1.75 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 66 | (solder_mask_margin 0.07)) 67 | (pad 8 smd oval (at -2.5 1.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 68 | (solder_mask_margin 0.07)) 69 | (pad 7 smd oval (at -2.5 1.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 70 | (solder_mask_margin 0.07)) 71 | (pad 6 smd oval (at -2.5 0.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 72 | (solder_mask_margin 0.07)) 73 | (pad 5 smd oval (at -2.5 0.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 74 | (solder_mask_margin 0.07)) 75 | (pad 4 smd oval (at -2.5 -0.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 76 | (solder_mask_margin 0.07)) 77 | (pad 3 smd oval (at -2.5 -0.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 78 | (solder_mask_margin 0.07)) 79 | (pad 2 smd oval (at -2.5 -1.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 80 | (solder_mask_margin 0.07)) 81 | (pad 1 smd oval (at -2.5 -1.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask) 82 | (solder_mask_margin 0.07)) 83 | (pad 33 smd rect (at -0.7 -0.7) (size 1.17 1.17) (layers F.Cu F.Paste F.Mask)) 84 | (pad 33 smd rect (at 0.7 0.7) (size 1.17 1.17) (layers F.Cu F.Paste F.Mask)) 85 | (pad 33 smd rect (at 0.7 -0.7) (size 1.17 1.17) (layers F.Cu F.Paste F.Mask)) 86 | (pad 33 smd rect (at -0.7 0.7) (size 1.17 1.17) (layers F.Cu F.Paste F.Mask)) 87 | ) 88 | -------------------------------------------------------------------------------- /board/tinyfpga.pretty/Lattice-QFN-32_5x5mm_Pitch0.5mm.kicad_mod: -------------------------------------------------------------------------------- 1 | (module Lattice-QFN-32_5x5mm_Pitch0.5mm locked (layer F.Cu) (tedit 59043BB9) 2 | (descr "UH Package; 32-Lead Plastic QFN (5mm x 5mm); (see Linear Technology QFN_32_05-08-1693.pdf)") 3 | (tags "QFN 0.5") 4 | (attr smd) 5 | (fp_text reference U2 (at 0 -3.75) (layer F.SilkS) hide 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_text value MachXO2-1200-QFN32 (at 0 3.75) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -1.5 -2.5) (end 2.5 -2.5) (layer F.Fab) (width 0.15)) 12 | (fp_line (start 2.5 -2.5) (end 2.5 2.5) (layer F.Fab) (width 0.15)) 13 | (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.Fab) (width 0.15)) 14 | (fp_line (start -2.5 2.5) (end -2.5 -1.5) (layer F.Fab) (width 0.15)) 15 | (fp_line (start -2.5 -1.5) (end -1.5 -2.5) (layer F.Fab) (width 0.15)) 16 | (fp_line (start -3 -3) (end -3 3) (layer F.CrtYd) (width 0.05)) 17 | (fp_line (start 3 -3) (end 3 3) (layer F.CrtYd) (width 0.05)) 18 | (fp_line (start -3 -3) (end 3 -3) (layer F.CrtYd) (width 0.05)) 19 | (fp_line (start -3 3) (end 3 3) (layer F.CrtYd) (width 0.05)) 20 | (fp_line (start 2.625 -2.625) (end 2.625 -2.1) (layer F.SilkS) (width 0.15)) 21 | (fp_line (start -2.625 2.625) (end -2.625 2.1) (layer F.SilkS) (width 0.15)) 22 | (fp_line (start 2.625 2.625) (end 2.625 2.1) (layer F.SilkS) (width 0.15)) 23 | (fp_line (start -2.625 -2.625) (end -2.1 -2.625) (layer F.SilkS) (width 0.15)) 24 | (fp_line (start -2.625 2.625) (end -2.1 2.625) (layer F.SilkS) (width 0.15)) 25 | (fp_line (start 2.625 2.625) (end 2.1 2.625) (layer F.SilkS) (width 0.15)) 26 | (fp_line (start 2.625 -2.625) (end 2.1 -2.625) (layer F.SilkS) (width 0.15)) 27 | (pad 1 smd rect (at -2.4 -1.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 28 | (pad 2 smd rect (at -2.4 -1.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 29 | (pad 3 smd rect (at -2.4 -0.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 30 | (pad 4 smd rect (at -2.4 -0.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 31 | (pad 5 smd rect (at -2.4 0.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 32 | (pad 6 smd rect (at -2.4 0.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 33 | (pad 7 smd rect (at -2.4 1.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 34 | (pad 8 smd rect (at -2.4 1.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 35 | (pad 9 smd rect (at -1.75 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 36 | (pad 10 smd rect (at -1.25 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 37 | (pad 11 smd rect (at -0.75 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 38 | (pad 12 smd rect (at -0.25 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 39 | (pad 13 smd rect (at 0.25 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 40 | (pad 14 smd rect (at 0.75 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 41 | (pad 15 smd rect (at 1.25 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 42 | (pad 16 smd rect (at 1.75 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 43 | (pad 17 smd rect (at 2.4 1.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 44 | (pad 18 smd rect (at 2.4 1.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 45 | (pad 19 smd rect (at 2.4 0.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 46 | (pad 20 smd rect (at 2.4 0.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 47 | (pad 21 smd rect (at 2.4 -0.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 48 | (pad 22 smd rect (at 2.4 -0.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 49 | (pad 23 smd rect (at 2.4 -1.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 50 | (pad 24 smd rect (at 2.4 -1.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 51 | (pad 25 smd rect (at 1.75 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 52 | (pad 26 smd rect (at 1.25 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 53 | (pad 27 smd rect (at 0.75 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 54 | (pad 28 smd rect (at 0.25 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 55 | (pad 29 smd rect (at -0.25 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 56 | (pad 30 smd rect (at -0.75 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 57 | (pad 31 smd rect (at -1.25 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 58 | (pad 32 smd rect (at -1.75 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)) 59 | (pad 33 smd rect (at 0.8625 0.8625) (size 1.725 1.725) (layers F.Cu F.Paste F.Mask) 60 | (solder_paste_margin_ratio -0.2)) 61 | (pad 33 smd rect (at 0.8625 -0.8625) (size 1.725 1.725) (layers F.Cu F.Paste F.Mask) 62 | (solder_paste_margin_ratio -0.2)) 63 | (pad 33 smd rect (at -0.8625 0.8625) (size 1.725 1.725) (layers F.Cu F.Paste F.Mask) 64 | (solder_paste_margin_ratio -0.2)) 65 | (pad 33 smd rect (at -0.8625 -0.8625) (size 1.725 1.725) (layers F.Cu F.Paste F.Mask) 66 | (solder_paste_margin_ratio -0.2)) 67 | (model Housings_DFN_QFN.3dshapes/QFN-32-1EP_5x5mm_Pitch0.5mm.wrl 68 | (at (xyz 0 0 0)) 69 | (scale (xyz 1 1 1)) 70 | (rotate (xyz 0 0 0)) 71 | ) 72 | ) 73 | -------------------------------------------------------------------------------- /board/tinyfpga.pretty/PTS_810_SMT_Switch.kicad_mod: -------------------------------------------------------------------------------- 1 | (module PTS_810_SMT_Switch (layer F.Cu) (tedit 591A91F4) 2 | (fp_text reference REF** (at 0 3.2) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value "PTS 810 SMT Switch" (at 0 -3) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start 2.1 -1.6) (end -2.1 -1.6) (layer F.Fab) (width 0.15)) 9 | (fp_line (start 2.1 1.6) (end 2.1 -1.6) (layer F.Fab) (width 0.15)) 10 | (fp_line (start -2.1 1.6) (end 2.1 1.6) (layer F.Fab) (width 0.15)) 11 | (fp_line (start -2.1 1.2) (end -2.1 1.6) (layer F.Fab) (width 0.15)) 12 | (fp_line (start -2.1 -1.6) (end -2.1 1.2) (layer F.Fab) (width 0.15)) 13 | (pad 1 smd rect (at -2.075 -1.075) (size 1.05 0.65) (layers F.Cu F.Paste F.Mask)) 14 | (pad 1 smd rect (at 2.075 -1.075) (size 1.05 0.65) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at 2.075 1.075) (size 1.05 0.65) (layers F.Cu F.Paste F.Mask)) 16 | (pad 2 smd rect (at -2.075 1.075) (size 1.05 0.65) (layers F.Cu F.Paste F.Mask)) 17 | ) 18 | -------------------------------------------------------------------------------- /board/tinyfpga.pretty/SC-70-C5.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SC-70-C5 (layer F.Cu) (tedit 591AA024) 2 | (fp_text reference REF** (at 0 2.85) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value SC-70-C5 (at 0 -2.85) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_circle (center 1.4 -1) (end 1.6 -0.925) (layer F.Fab) (width 0.15)) 9 | (fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15)) 10 | (fp_line (start -1 -0.625) (end -1 0.625) (layer F.Fab) (width 0.15)) 11 | (fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15)) 12 | (fp_line (start 1 -0.625) (end -1 -0.625) (layer F.Fab) (width 0.15)) 13 | (pad 2 smd rect (at 0 -1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at -0.65 -1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask)) 15 | (pad 1 smd rect (at 0.65 -1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd rect (at -0.65 1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd rect (at 0.65 1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask)) 18 | ) 19 | -------------------------------------------------------------------------------- /board/tinyfpga.pretty/Thin-DFN4.kicad_mod: -------------------------------------------------------------------------------- 1 | (module Thin-DFN4 (layer F.Cu) (tedit 5A13CB11) 2 | (attr smd) 3 | (fp_text reference U5 (at 0 -0.3) (layer F.Fab) 4 | (effects (font (size 0.127 0.127) (thickness 0.03175))) 5 | ) 6 | (fp_text value MIC5504-2.5YM5-TR (at 0 0.7) (layer F.Fab) 7 | (effects (font (size 0.127 0.127) (thickness 0.03175))) 8 | ) 9 | (fp_circle (center -0.3 0.3) (end -0.2 0.3) (layer F.Fab) (width 0.05)) 10 | (fp_line (start -0.5 -0.5) (end -0.5 0.5) (layer F.Fab) (width 0.05)) 11 | (fp_line (start 0.5 -0.5) (end -0.5 -0.5) (layer F.Fab) (width 0.05)) 12 | (fp_line (start 0.5 0.5) (end 0.5 -0.5) (layer F.Fab) (width 0.05)) 13 | (fp_line (start -0.5 0.5) (end 0.5 0.5) (layer F.Fab) (width 0.05)) 14 | (pad 2 smd trapezoid (at 0 0 45) (size 0.48 0.48) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd trapezoid (at 0.325 0.54) (size 0.25 0.22) (layers F.Cu F.Paste F.Mask)) 16 | (pad 1 smd trapezoid (at -0.325 0.54) (size 0.25 0.22) (layers F.Cu F.Paste F.Mask)) 17 | (pad 3 smd trapezoid (at 0.325 -0.54) (size 0.25 0.22) (layers F.Cu F.Paste F.Mask)) 18 | (pad 4 smd trapezoid (at -0.325 -0.54) (size 0.25 0.22) (layers F.Cu F.Paste F.Mask)) 19 | (pad 3 smd trapezoid (at 0.325 -0.43 180) (size 0.25 0.22) (rect_delta 0.2199 0 ) (layers F.Cu F.Paste F.Mask) 20 | (solder_mask_margin 0.025)) 21 | (pad 4 smd trapezoid (at -0.325 -0.43) (size 0.25 0.22) (rect_delta 0.2199 0 ) (layers F.Cu F.Paste F.Mask) 22 | (solder_mask_margin 0.025)) 23 | (pad 2 smd trapezoid (at 0.325 0.43 180) (size 0.25 0.22) (rect_delta 0.2199 0 ) (layers F.Cu F.Paste F.Mask) 24 | (solder_mask_margin 0.025)) 25 | (pad 1 smd trapezoid (at -0.325 0.43) (size 0.25 0.22) (rect_delta 0.2199 0 ) (layers F.Cu F.Paste F.Mask) 26 | (solder_mask_margin 0.025)) 27 | ) 28 | -------------------------------------------------------------------------------- /bootloader_alt/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile 2 | # 3 | # The following license is from the icestorm project and specifically applies to this file only: 4 | # 5 | # Permission to use, copy, modify, and/or distribute this software for any 6 | # purpose with or without fee is hereby granted, provided that the above 7 | # copyright notice and this permission notice appear in all copies. 8 | # 9 | # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 | # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 | # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 | # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 | # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 | # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 | # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 | 17 | PROJ = TinyFPGA_B 18 | 19 | PIN_DEF = pins.pcf 20 | DEVICE = lp8k 21 | 22 | all: $(PROJ).rpt $(PROJ).bin 23 | 24 | %.blif: %.v 25 | yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $< 26 | 27 | %.asc: $(PIN_DEF) %.blif 28 | arachne-pnr -d 8k -P cm81 -o $@ -p $^ 29 | 30 | %.bin: %.asc 31 | icepack $< $@ 32 | 33 | %.rpt: %.asc 34 | icetime -d $(DEVICE) -mtr $@ $< 35 | 36 | %_tb: %_tb.v %.v 37 | iverilog -o $@ $^ 38 | 39 | %_tb.vcd: %_tb 40 | vvp -N $< +vcd=$@ 41 | 42 | %_syn.v: %.blif 43 | yosys -p 'read_blif -wideports $^; write_verilog $@' 44 | 45 | %_syntb: %_tb.v %_syn.v 46 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 47 | 48 | %_syntb.vcd: %_syntb 49 | vvp -N $< +vcd=$@ 50 | 51 | prog: $(PROJ).bin 52 | iceprog $< 53 | 54 | sudo-prog: $(PROJ).bin 55 | @echo 'Executing prog as root!!!' 56 | sudo iceprog $< 57 | 58 | clean: 59 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin 60 | 61 | .SECONDARY: 62 | .PHONY: all prog clean 63 | -------------------------------------------------------------------------------- /bootloader_alt/TinyFPGA_B.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mattvenn/TinyFPGA-BX/9a5c9cb9fc09344bf0535946a51b30e60cf99c4c/bootloader_alt/TinyFPGA_B.bin -------------------------------------------------------------------------------- /bootloader_alt/TinyFPGA_B.blif: -------------------------------------------------------------------------------- 1 | # Generated by Yosys 0.7+336 (git sha1 adf1754, clang 3.8.0-2ubuntu4 -fPIC -Os) 2 | 3 | .model TinyFPGA_B 4 | .inputs 5 | .outputs pin_pu pin_led 6 | .names $false 7 | .names $true 8 | 1 9 | .names $undef 10 | .names $false pin_led 11 | 1 1 12 | .names $false pin_pu 13 | 1 1 14 | .end 15 | -------------------------------------------------------------------------------- /bootloader_alt/TinyFPGA_B.v: -------------------------------------------------------------------------------- 1 | module TinyFPGA_B ( 2 | output pin_pu, 3 | output pin_led 4 | ); 5 | assign pin_pu = 1'b0; 6 | assign pin_led = 1'b0; 7 | endmodule 8 | -------------------------------------------------------------------------------- /bootloader_alt/bootloader_alt/bootloader_alt_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.01.27914 - Build Date: Jan 12 2017 19:10:45 4 | ProjectName=bootloader_alt 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../TinyFPGA_B.v 8 | ProjectCFiles= 9 | CurImplementation=bootloader_alt_Implmnt 10 | Implementations=bootloader_alt_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [bootloader_alt_Implmnt] 15 | DeviceFamily=iCE40 16 | Device=LP8K 17 | DevicePackage=CM81 18 | DevicePower= 19 | NetlistFile=bootloader_alt_Implmnt/bootloader_alt.edf 20 | AdditionalEDIFFile= 21 | IPEDIFFile= 22 | DesignLib=bootloader_alt_Implmnt/sbt/netlist/oadb-TinyFPGA_B 23 | DesignView=_rt 24 | DesignCell=TinyFPGA_B 25 | SynthesisSDCFile=bootloader_alt_Implmnt/bootloader_alt.scf 26 | UserPinConstraintFile= 27 | UserSDCFile= 28 | PhysicalConstraintFile=../pins.pcf 29 | BackendImplPathName= 30 | Devicevoltage=1.2 31 | DevicevoltagePerformance=+/-5%(datasheet default) 32 | DeviceTemperature=25 33 | TimingAnalysisBasedOn=Typical 34 | OperationRange=Commercial 35 | TypicalCustomTemperature=25 36 | WorstCustomTemperature=85 37 | BestCustomTemperature=0 38 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 39 | derValue=0.85 40 | TimingPathNumberStick=0 41 | 42 | [lse options] 43 | CarryChain=True 44 | CarryChainLength=0 45 | CommandLineOptions= 46 | EBRUtilization=100.00 47 | FSMEncodingStyle=Auto 48 | FixGatedClocks=True 49 | I/OInsertion=True 50 | IntermediateFileDump=False 51 | LoopLimit=1950 52 | MaximalFanout=10000 53 | MemoryInitialValueFileSearchPath= 54 | NumberOfCriticalPaths=3 55 | OptimizationGoal=Area 56 | PropagateConstants=True 57 | RAMStyle=Auto 58 | ROMStyle=Auto 59 | RWCheckOnRam=False 60 | RemoveDuplicateRegisters=True 61 | ResolvedMixedDrivers=False 62 | ResourceSharing=True 63 | TargetFrequency= 64 | TopLevelUnit= 65 | UseIORegister=Auto 66 | VHDL2008=False 67 | VerilogIncludeSearchPath= 68 | 69 | [tool options] 70 | PlacerEffortLevel=std 71 | PlacerAutoLutCascade=yes 72 | PlacerAutoRamCascade=yes 73 | PlacerPowerDriven=no 74 | PlacerAreaDriven=no 75 | RouteWithTimingDriven=yes 76 | RouteWithPinPermutation=yes 77 | BitmapSPIFlashMode=yes 78 | BitmapRAM4KInit=yes 79 | BitmapInitRamBank=1111 80 | BitmapOscillatorFR=low 81 | BitmapEnableWarmBoot=yes 82 | BitmapDisableHeader=no 83 | BitmapSetSecurity=no 84 | BitmapSetNoUsedIONoPullup=no 85 | FloorPlannerShowFanInNets=yes 86 | FloorPlannerShowFanOutNets=yes 87 | HookTo3rdPartyTextEditor= 88 | 89 | -------------------------------------------------------------------------------- /bootloader_alt/bootloader_alt/bootloader_alt_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-B-Series\bootloader_alt\bootloader_alt\bootloader_alt_syn.prj 3 | #project files 4 | add_file -verilog -lib work "../TinyFPGA_B.v" 5 | 6 | #implementation: "bootloader_alt_Implmnt" 7 | impl -add bootloader_alt_Implmnt -type fpga 8 | 9 | #implementation attributes 10 | set_option -vlog_std v2001 11 | set_option -project_relative_includes 1 12 | 13 | #device options 14 | set_option -technology SBTiCE40 15 | set_option -part iCE40LP8K 16 | set_option -package CM81 17 | set_option -speed_grade 18 | set_option -part_companion "" 19 | 20 | #compilation/mapping options 21 | 22 | # mapper_options 23 | set_option -frequency auto 24 | set_option -write_verilog 0 25 | set_option -write_vhdl 0 26 | 27 | # Silicon Blue iCE40 28 | set_option -maxfan 10000 29 | set_option -disable_io_insertion 0 30 | set_option -pipe 1 31 | set_option -retiming 0 32 | set_option -update_models_cp 0 33 | set_option -fixgatedclocks 2 34 | set_option -fixgeneratedclocks 0 35 | 36 | # NFilter 37 | set_option -popfeed 0 38 | set_option -constprop 0 39 | set_option -createhierarchy 0 40 | 41 | # sequential_optimization_options 42 | set_option -symbolic_fsm_compiler 1 43 | 44 | # Compiler Options 45 | set_option -compiler_compatible 0 46 | set_option -resource_sharing 1 47 | 48 | #automatic place and route (vendor) options 49 | set_option -write_apr_constraint 1 50 | 51 | #set result format/file last 52 | project -result_format "edif" 53 | project -result_file ./bootloader_alt_Implmnt/bootloader_alt.edf 54 | project -log_file "./bootloader_alt_Implmnt/bootloader_alt.srr" 55 | impl -active "bootloader_alt_Implmnt" 56 | project -run synthesis -clean 57 | -------------------------------------------------------------------------------- /bootloader_alt/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Family & Device: iCE40LP8K 3 | # Package: CM81 4 | ############################################################################### 5 | 6 | #set_io pin_1 A2 7 | #set_io pin_2 A1 8 | #set_io pin_3 B1 9 | #set_io pin_4 C2 10 | #set_io pin_5 C1 11 | #set_io pin_6 D2 12 | #set_io pin_7 D1 13 | #set_io pin_8 E2 14 | #set_io pin_9 E1 15 | #set_io pin_10 G2 16 | #set_io pin_11 H1 17 | #set_io pin_12 J1 18 | #set_io pin_13 H2 19 | #set_io pin_14 H9 20 | #set_io pin_15 D9 21 | #set_io pin_16 D8 22 | #set_io pin_17 C9 23 | #set_io pin_18 A9 24 | #set_io pin_19 B8 25 | #set_io pin_20 A8 26 | #set_io pin_21 B7 27 | #set_io pin_22 A7 28 | #set_io pin_23 B6 29 | #set_io pin_24 A6 30 | #set_io pin_25 G1 31 | #set_io pin_26 J3 32 | #set_io pin_27 J4 33 | #set_io pin_28 H4 34 | #set_io pin_29_miso H7 35 | #set_io pin_30_cs F7 36 | #set_io pin_31_mosi G6 37 | #set_io pin_32_sck G7 38 | #set_io pin_33 J8 39 | #set_io pin_34 G9 40 | #set_io pin_35 J9 41 | #set_io pin_36 E8 42 | #set_io pin_37 J2 43 | set_io pin_led B3 44 | #set_io pin_usbp B4 45 | #set_io pin_usbn A4 46 | set_io pin_pu A3 47 | #set_io pin_clk B2 48 | 49 | -------------------------------------------------------------------------------- /dft/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile 2 | # 3 | # The following license is from the icestorm project and specifically applies to this file only: 4 | # 5 | # Permission to use, copy, modify, and/or distribute this software for any 6 | # purpose with or without fee is hereby granted, provided that the above 7 | # copyright notice and this permission notice appear in all copies. 8 | # 9 | # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 | # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 | # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 | # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 | # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 | # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 | # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 | 17 | PROJ = TinyFPGA_B 18 | 19 | PIN_DEF = pins.pcf 20 | DEVICE = lp8k 21 | 22 | all: $(PROJ).rpt $(PROJ).bin 23 | 24 | %.blif: %.v 25 | yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $< 26 | 27 | %.asc: $(PIN_DEF) %.blif 28 | arachne-pnr -d 8k -P cm81 -o $@ -p $^ 29 | 30 | %.bin: %.asc 31 | icepack $< $@ 32 | 33 | %.rpt: %.asc 34 | icetime -d $(DEVICE) -mtr $@ $< 35 | 36 | %_tb: %_tb.v %.v 37 | iverilog -o $@ $^ 38 | 39 | %_tb.vcd: %_tb 40 | vvp -N $< +vcd=$@ 41 | 42 | %_syn.v: %.blif 43 | yosys -p 'read_blif -wideports $^; write_verilog $@' 44 | 45 | %_syntb: %_tb.v %_syn.v 46 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 47 | 48 | %_syntb.vcd: %_syntb 49 | vvp -N $< +vcd=$@ 50 | 51 | prog: $(PROJ).bin 52 | iceprog $< 53 | 54 | sudo-prog: $(PROJ).bin 55 | @echo 'Executing prog as root!!!' 56 | sudo iceprog $< 57 | 58 | clean: 59 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin 60 | 61 | .SECONDARY: 62 | .PHONY: all prog clean 63 | -------------------------------------------------------------------------------- /dft/TinyFPGA_B.v: -------------------------------------------------------------------------------- 1 | module TinyFPGA_B ( 2 | input pin_clk, 3 | 4 | input pin_usbp, 5 | input pin_usbn, 6 | input pin_pu, 7 | 8 | input pin_led, 9 | 10 | output pin_1, 11 | output pin_2, 12 | output pin_3, 13 | output pin_4, 14 | output pin_5, 15 | output pin_6, 16 | output pin_7, 17 | output pin_8, 18 | output pin_9, 19 | output pin_10, 20 | output pin_11, 21 | output pin_12, 22 | input pin_13, 23 | output pin_14, 24 | output pin_15, 25 | output pin_16, 26 | output pin_17, 27 | output pin_18, 28 | output pin_19, 29 | output pin_20, 30 | input pin_21, 31 | input pin_22, 32 | input pin_23, 33 | input pin_24, 34 | input pin_25, 35 | input pin_26, 36 | input pin_27, 37 | input pin_28, 38 | input pin_29_miso, 39 | output pin_30_cs, 40 | input pin_31_mosi, 41 | output pin_32_sck, 42 | input pin_33, 43 | input pin_34, 44 | input pin_35, 45 | input pin_36, 46 | input pin_37 47 | ); 48 | // there are some decoupling caps just for the PLL on the board, 49 | // let's pipe the clock through the PLL so we can test both the 50 | // clock and PLL at once 51 | wire clk_48mhz; 52 | reg [19:0] clock_divider; 53 | reg slow_clock; 54 | 55 | SB_PLL40_CORE pll_inst ( 56 | .REFERENCECLK(pin_clk), 57 | .PLLOUTCORE(clk_48mhz), 58 | .PLLOUTGLOBAL(), 59 | .EXTFEEDBACK(), 60 | .DYNAMICDELAY(), 61 | .RESETB(1'b1), 62 | .BYPASS(1'b0), 63 | .LATCHINPUTVALUE(), 64 | .LOCK(), 65 | .SDI(), 66 | .SDO(), 67 | .SCLK() 68 | ); 69 | // Fin=16, Fout=48 70 | defparam pll_inst.DIVR = 4'b0000; 71 | defparam pll_inst.DIVF = 7'b0101111; 72 | defparam pll_inst.DIVQ = 3'b100; 73 | defparam pll_inst.FILTER_RANGE = 3'b001; 74 | defparam pll_inst.FEEDBACK_PATH = "SIMPLE"; 75 | defparam pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; 76 | defparam pll_inst.FDA_FEEDBACK = 4'b0000; 77 | defparam pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; 78 | defparam pll_inst.FDA_RELATIVE = 4'b0000; 79 | defparam pll_inst.SHIFTREG_DIV_MODE = 2'b00; 80 | defparam pll_inst.PLLOUT_SELECT = "GENCLK"; 81 | defparam pll_inst.ENABLE_ICEGATE = 1'b0; 82 | // divide the clock down to ensure two things: 83 | // 1. clock is connected to FPGA 84 | // 2. output clock is measurable by test-jig 85 | assign pin_32_sck = slow_clock; 86 | always @(posedge clk_48mhz) begin 87 | if (clock_divider < 1000000) begin 88 | clock_divider <= clock_divider + 1; 89 | end else begin 90 | slow_clock <= ~slow_clock; 91 | clock_divider <= 0; 92 | end 93 | end 94 | 95 | 96 | // pulling an input pin low will drive the corresponding 97 | // output pin low as well. this is a simple way for the 98 | // test jig to test all the IOs for opens and shorts 99 | assign pin_1 = pin_21;// ? 1'bz : 0; 100 | assign pin_2 = pin_22;// ? 1'bz : 0; 101 | assign pin_3 = pin_23;// ? 1'bz : 0; 102 | assign pin_4 = pin_24;// ? 1'bz : 0; 103 | assign pin_5 = pin_25;// ? 1'bz : 0; 104 | assign pin_6 = pin_26;// ? 1'bz : 0; 105 | assign pin_7 = pin_27;// ? 1'bz : 0; 106 | assign pin_8 = pin_28;// ? 1'bz : 0; 107 | assign pin_9 = pin_29_miso;// ? 1'bz : 0; 108 | assign pin_10 = pin_13;// ? 1'bz : 0; 109 | assign pin_11 = pin_31_mosi;// ? 1'bz : 0; 110 | assign pin_12 = pin_pu;// ? 1'bz : 0; 111 | assign pin_30_cs = pin_33;// ? 1'bz : 0; 112 | assign pin_14 = pin_34;// ? 1'bz : 0; 113 | assign pin_15 = pin_35;// ? 1'bz : 0; 114 | assign pin_16 = pin_36;// ? 1'bz : 0; 115 | assign pin_17 = pin_37;// ? 1'bz : 0; 116 | assign pin_18 = pin_led;// ? 1'bz : 0; 117 | assign pin_19 = pin_usbp;// ? 1'bz : 0; 118 | assign pin_20 = pin_usbn;// ? 1'bz : 0; 119 | 120 | 121 | endmodule 122 | -------------------------------------------------------------------------------- /dft/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Family & Device: iCE40LP8K 3 | # Package: CM81 4 | ############################################################################### 5 | 6 | set_io pin_1 A2 7 | set_io pin_2 A1 8 | set_io pin_3 B1 9 | set_io pin_4 C2 10 | set_io pin_5 C1 11 | set_io pin_6 D2 12 | set_io pin_7 D1 13 | set_io pin_8 E2 14 | set_io pin_9 E1 15 | set_io pin_10 G2 16 | set_io pin_11 H1 17 | set_io pin_12 J1 18 | set_io pin_13 H2 19 | set_io pin_14 H9 20 | set_io pin_15 D9 21 | set_io pin_16 D8 22 | set_io pin_17 C9 23 | set_io pin_18 A9 24 | set_io pin_19 B8 25 | set_io pin_20 A8 26 | set_io pin_21 B7 27 | set_io pin_22 A7 28 | set_io pin_23 B6 29 | set_io pin_24 A6 30 | set_io pin_25 G1 31 | set_io pin_26 J3 32 | set_io pin_27 J4 33 | set_io pin_28 H4 34 | set_io pin_29_miso H7 35 | set_io pin_30_cs F7 36 | set_io pin_31_mosi H5 37 | set_io pin_32_sck G7 38 | set_io pin_33 J8 39 | set_io pin_34 G9 40 | set_io pin_35 J9 41 | set_io pin_36 E8 42 | set_io pin_37 J2 43 | set_io pin_led B3 44 | set_io pin_usbp B4 45 | set_io pin_usbn A4 46 | set_io pin_pu A3 47 | set_io pin_clk B2 48 | 49 | -------------------------------------------------------------------------------- /examples/picosoc/.gitignore: -------------------------------------------------------------------------------- 1 | /spiflash_tb.vcd 2 | /spiflash_tb.vvp 3 | /firmware.elf 4 | /firmware.hex 5 | /firmware.bin 6 | /hardware.asc 7 | /hardware.bin 8 | /hardware.blif 9 | /hardware.log 10 | /hardware.rpt 11 | /hardware_syn.v 12 | /hardware_syn_tb.vvp 13 | /hardware_tb.vvp 14 | /testbench.vcd 15 | /cmos.log 16 | -------------------------------------------------------------------------------- /examples/picosoc/Makefile: -------------------------------------------------------------------------------- 1 | 2 | upload: hardware.bin firmware.bin 3 | tinyprog -p hardware.bin -u firmware.bin 4 | 5 | 6 | hardware.blif: hardware.v spimemio.v simpleuart.v picosoc.v picorv32.v 7 | yosys -ql hardware.log -p 'synth_ice40 -top hardware -blif hardware.blif' $^ 8 | 9 | hardware.asc: hardware.pcf hardware.blif 10 | arachne-pnr -d 8k -P cm81 -o hardware.asc -p hardware.pcf hardware.blif 11 | 12 | hardware.bin: hardware.asc 13 | icetime -d hx8k -c 12 -mtr hardware.rpt hardware.asc 14 | icepack hardware.asc hardware.bin 15 | 16 | 17 | firmware.elf: sections.lds start.S firmware.c 18 | riscv32-unknown-elf-gcc -march=rv32imc -nostartfiles -Wl,-Bstatic,-T,sections.lds,--strip-debug,-Map=firmware.map,--cref -ffreestanding -nostdlib -o firmware.elf start.S firmware.c 19 | 20 | firmware.bin: firmware.elf 21 | riscv32-unknown-elf-objcopy -O binary firmware.elf /dev/stdout > firmware.bin 22 | 23 | 24 | clean: 25 | rm -f firmware.elf firmware.hex firmware.bin firmware.o firmware.map \ 26 | hardware.blif hardware.log hardware.asc hardware.rpt hardware.bin 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /examples/picosoc/README.md: -------------------------------------------------------------------------------- 1 | # Video Notes 2 | 3 | Git repository https://github.com/mattvenn/TinyFPGA-BX/tree/master/examples/picosoc 4 | 5 | The README.md contains information on: 6 | 7 | * Information about installing the toolchains 8 | * Electrical wiring for the demos 9 | * Precompiled firmware binaries: 10 | * master - starting point 11 | * ws2812 - includes ws2812 driver and serial driver 12 | 13 | # PicoSOC TinyFPGA example 14 | 15 | PicoSOC is an SOC - system on chip. It includes everything you need to 16 | run a RiscV CPU on the TinyFPGA. 17 | 18 | The RiscV CPU is PicoRV32, made by Clifford Wolf. The original repo is here: 19 | 20 | https://github.com/cliffordwolf/picorv32 21 | 22 | The SOC example that uses the PicoRV32 was originally made for the Lattice 8k evaluation 23 | board. This example has been modified to work with the TinyFPGA by Luke from TinyFPGA. 24 | 25 | # FPGA Toolchain 26 | 27 | You can synthesise the demo with the [icestorm](http://www.clifford.at/icestorm/) toolchain. 28 | A very convient way to install the toolchain is to use [APIO](https://github.com/FPGAwars/apio) 29 | And then set your path to include the installed tools and copy the chipdb and yosys files: 30 | 31 | export PATH=$PATH:~/.apio/packages/toolchain-icestorm/bin/ 32 | sudo cp -r ~/.apio/packages/toolchain-icestorm/share/icebox/ /usr/local/share/ 33 | sudo cp -r ~/.apio/packages/toolchain-icestorm/share/yosys /usr/local/share/ 34 | 35 | 36 | You will also need tinyprog: 37 | 38 | pip install tinyprog 39 | 40 | For more info on the TinyFPGA tools and setup see the TinyFPGA page: https://tinyfpga.com/bx/guide.html 41 | 42 | At this point you should be able to run make upload to synthesise the hardware and program to the TinyFPGA. 43 | I have precompiled the firmware.c and added the firmware.bin and hex files to the repo so you don't need GCC. 44 | 45 | If you just want to see the demos in the video, you can switch to the ws2812 branch 46 | 47 | git checkout ws2812 48 | 49 | Which should allow you to program the precompiled firmware or run the simulation without installing GCC. 50 | 51 | # GCC for firmware compilation 52 | 53 | As this is a RiscV CPU running on the FPGA, we really need the RiscV GCC tools to get the most out of it! 54 | Fetching the repos and compiling took about 3 hours on my 4 year old T400 Lenovo laptop. Full instructions 55 | here: https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain 56 | 57 | What I did was: 58 | 59 | sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \ 60 | libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \ 61 | gperf libtool patchutils bc zlib1g-dev git libexpat1-dev 62 | 63 | git clone git@github.com:cliffordwolf/picorv32.git 64 | cd picorv32/ 65 | time make -j2 build-riscv32i-tools 66 | export PATH=$PATH:/opt/riscv32i/bin/ 67 | 68 | Then make firmware.bin should work and you can then write your own c program or edit my demos. 69 | 70 | # Wiring for the demo 71 | 72 | * Serial TX is pin 1 73 | * Serial RX is pin 2 74 | * WS2812 data is pin 3 75 | -------------------------------------------------------------------------------- /examples/picosoc/custom_ops.S: -------------------------------------------------------------------------------- 1 | // This is free and unencumbered software released into the public domain. 2 | // 3 | // Anyone is free to copy, modify, publish, use, compile, sell, or 4 | // distribute this software, either in source code form or as a compiled 5 | // binary, for any purpose, commercial or non-commercial, and by any 6 | // means. 7 | 8 | #define regnum_q0 0 9 | #define regnum_q1 1 10 | #define regnum_q2 2 11 | #define regnum_q3 3 12 | 13 | #define regnum_x0 0 14 | #define regnum_x1 1 15 | #define regnum_x2 2 16 | #define regnum_x3 3 17 | #define regnum_x4 4 18 | #define regnum_x5 5 19 | #define regnum_x6 6 20 | #define regnum_x7 7 21 | #define regnum_x8 8 22 | #define regnum_x9 9 23 | #define regnum_x10 10 24 | #define regnum_x11 11 25 | #define regnum_x12 12 26 | #define regnum_x13 13 27 | #define regnum_x14 14 28 | #define regnum_x15 15 29 | #define regnum_x16 16 30 | #define regnum_x17 17 31 | #define regnum_x18 18 32 | #define regnum_x19 19 33 | #define regnum_x20 20 34 | #define regnum_x21 21 35 | #define regnum_x22 22 36 | #define regnum_x23 23 37 | #define regnum_x24 24 38 | #define regnum_x25 25 39 | #define regnum_x26 26 40 | #define regnum_x27 27 41 | #define regnum_x28 28 42 | #define regnum_x29 29 43 | #define regnum_x30 30 44 | #define regnum_x31 31 45 | 46 | #define regnum_zero 0 47 | #define regnum_ra 1 48 | #define regnum_sp 2 49 | #define regnum_gp 3 50 | #define regnum_tp 4 51 | #define regnum_t0 5 52 | #define regnum_t1 6 53 | #define regnum_t2 7 54 | #define regnum_s0 8 55 | #define regnum_s1 9 56 | #define regnum_a0 10 57 | #define regnum_a1 11 58 | #define regnum_a2 12 59 | #define regnum_a3 13 60 | #define regnum_a4 14 61 | #define regnum_a5 15 62 | #define regnum_a6 16 63 | #define regnum_a7 17 64 | #define regnum_s2 18 65 | #define regnum_s3 19 66 | #define regnum_s4 20 67 | #define regnum_s5 21 68 | #define regnum_s6 22 69 | #define regnum_s7 23 70 | #define regnum_s8 24 71 | #define regnum_s9 25 72 | #define regnum_s10 26 73 | #define regnum_s11 27 74 | #define regnum_t3 28 75 | #define regnum_t4 29 76 | #define regnum_t5 30 77 | #define regnum_t6 31 78 | 79 | // x8 is s0 and also fp 80 | #define regnum_fp 8 81 | 82 | #define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \ 83 | .word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0)) 84 | 85 | #define picorv32_getq_insn(_rd, _qs) \ 86 | r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011) 87 | 88 | #define picorv32_setq_insn(_qd, _rs) \ 89 | r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011) 90 | 91 | #define picorv32_retirq_insn() \ 92 | r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011) 93 | 94 | #define picorv32_maskirq_insn(_rd, _rs) \ 95 | r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011) 96 | 97 | #define picorv32_waitirq_insn(_rd) \ 98 | r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011) 99 | 100 | #define picorv32_timer_insn(_rd, _rs) \ 101 | r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011) 102 | -------------------------------------------------------------------------------- /examples/picosoc/firmware.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mattvenn/TinyFPGA-BX/9a5c9cb9fc09344bf0535946a51b30e60cf99c4c/examples/picosoc/firmware.bin -------------------------------------------------------------------------------- /examples/picosoc/firmware.c: -------------------------------------------------------------------------------- 1 | #include <stdint.h> 2 | #include <stdbool.h> 3 | 4 | // a pointer to this is a null pointer, but the compiler does not 5 | // know that because "sram" is a linker symbol from sections.lds. 6 | extern uint32_t sram; 7 | 8 | #define reg_spictrl (*(volatile uint32_t*)0x02000000) 9 | #define reg_uart_clkdiv (*(volatile uint32_t*)0x02000004) 10 | #define reg_uart_data (*(volatile uint32_t*)0x02000008) 11 | #define reg_leds (*(volatile uint32_t*)0x03000000) 12 | 13 | extern uint32_t _sidata, _sdata, _edata, _sbss, _ebss,_heap_start; 14 | 15 | uint32_t set_irq_mask(uint32_t mask); asm ( 16 | ".global set_irq_mask\n" 17 | "set_irq_mask:\n" 18 | ".word 0x0605650b\n" 19 | "ret\n" 20 | ); 21 | 22 | 23 | 24 | 25 | void main() { 26 | set_irq_mask(0xff); 27 | 28 | // switch to dual IO mode 29 | reg_spictrl = (reg_spictrl & ~0x007F0000) | 0x00400000; 30 | 31 | // blink the user LED 32 | uint32_t led_timer = 0; 33 | 34 | while (1) { 35 | reg_leds = led_timer >> 16; 36 | led_timer = led_timer + 1; 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /examples/picosoc/firmware.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mattvenn/TinyFPGA-BX/9a5c9cb9fc09344bf0535946a51b30e60cf99c4c/examples/picosoc/firmware.elf -------------------------------------------------------------------------------- /examples/picosoc/hardware.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the <project name> project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io --warn-no-port pin_1 A2 42 | set_io --warn-no-port pin_2 A1 43 | set_io --warn-no-port pin_3 B1 44 | set_io --warn-no-port pin_4 C2 45 | set_io --warn-no-port pin_5 C1 46 | set_io --warn-no-port pin_6 D2 47 | set_io --warn-no-port pin_7 D1 48 | set_io --warn-no-port pin_8 E2 49 | set_io --warn-no-port pin_9 E1 50 | set_io --warn-no-port pin_10 G2 51 | set_io --warn-no-port pin_11 H1 52 | set_io --warn-no-port pin_12 J1 53 | set_io --warn-no-port pin_13 H2 54 | 55 | # Right side of board 56 | set_io --warn-no-port pin_14 H9 57 | set_io --warn-no-port pin_15 D9 58 | set_io --warn-no-port pin_16 D8 59 | set_io --warn-no-port pin_17 C9 60 | set_io --warn-no-port pin_18 A9 61 | set_io --warn-no-port pin_19 B8 62 | set_io --warn-no-port pin_20 A8 63 | set_io --warn-no-port pin_21 B7 64 | set_io --warn-no-port pin_22 A7 65 | set_io --warn-no-port pin_23 B6 66 | set_io --warn-no-port pin_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io flash_csb F7 70 | set_io flash_clk G7 71 | set_io flash_io0 G6 72 | set_io flash_io1 H7 73 | set_io flash_io2 H4 74 | set_io flash_io3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io --warn-no-port pin_25 G1 78 | set_io --warn-no-port pin_26 J3 79 | set_io --warn-no-port pin_27 J4 80 | set_io --warn-no-port pin_28 G9 81 | set_io --warn-no-port pin_29 J9 82 | set_io --warn-no-port pin_30 E8 83 | set_io --warn-no-port pin_31 J2 84 | 85 | # LED 86 | set_io --warn-no-port user_led B3 87 | 88 | # USB 89 | set_io pin_pu A3 90 | set_io pin_usbp B4 91 | set_io pin_usbn A4 92 | 93 | # 16MHz clock 94 | set_io clk_16mhz B2 95 | -------------------------------------------------------------------------------- /examples/picosoc/hardware.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module hardware ( 21 | input clk_16mhz, 22 | 23 | // onboard USB interface 24 | output pin_pu, 25 | output pin_usbp, 26 | output pin_usbn, 27 | 28 | // hardware UART 29 | output pin_1, 30 | input pin_2, 31 | 32 | // onboard LED 33 | output user_led, 34 | 35 | // onboard SPI flash interface 36 | output flash_csb, 37 | output flash_clk, 38 | inout flash_io0, 39 | inout flash_io1, 40 | inout flash_io2, 41 | inout flash_io3 42 | ); 43 | assign pin_pu = 1'b1; 44 | assign pin_usbp = 1'b0; 45 | assign pin_usbn = 1'b0; 46 | 47 | wire clk = clk_16mhz; 48 | 49 | 50 | /////////////////////////////////// 51 | // Power-on Reset 52 | /////////////////////////////////// 53 | reg [5:0] reset_cnt = 0; 54 | wire resetn = &reset_cnt; 55 | 56 | always @(posedge clk) begin 57 | reset_cnt <= reset_cnt + !resetn; 58 | end 59 | 60 | 61 | /////////////////////////////////// 62 | // SPI Flash Interface 63 | /////////////////////////////////// 64 | wire flash_io0_oe, flash_io0_do, flash_io0_di; 65 | wire flash_io1_oe, flash_io1_do, flash_io1_di; 66 | wire flash_io2_oe, flash_io2_do, flash_io2_di; 67 | wire flash_io3_oe, flash_io3_do, flash_io3_di; 68 | 69 | SB_IO #( 70 | .PIN_TYPE(6'b 1010_01), 71 | .PULLUP(1'b 0) 72 | ) flash_io_buf [3:0] ( 73 | .PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}), 74 | .OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}), 75 | .D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}), 76 | .D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}) 77 | ); 78 | 79 | 80 | 81 | /////////////////////////////////// 82 | // Peripheral Bus 83 | /////////////////////////////////// 84 | wire iomem_valid; 85 | reg iomem_ready; 86 | wire [3:0] iomem_wstrb; 87 | wire [31:0] iomem_addr; 88 | wire [31:0] iomem_wdata; 89 | reg [31:0] iomem_rdata; 90 | 91 | reg [31:0] gpio; 92 | assign user_led = gpio[0]; 93 | 94 | always @(posedge clk) begin 95 | if (!resetn) begin 96 | gpio <= 0; 97 | end else begin 98 | iomem_ready <= 0; 99 | 100 | /////////////////////////// 101 | // GPIO Peripheral 102 | /////////////////////////// 103 | if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin 104 | iomem_ready <= 1; 105 | iomem_rdata <= gpio; 106 | if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0]; 107 | if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8]; 108 | if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16]; 109 | if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24]; 110 | end 111 | 112 | 113 | /////////////////////////// 114 | // Template Peripheral 115 | /////////////////////////// 116 | if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h04) begin 117 | iomem_ready <= 1; 118 | iomem_rdata <= 32'h0; 119 | end 120 | end 121 | end 122 | 123 | picosoc #( 124 | .PROGADDR_RESET(32'h0005_0000), // beginning of user space in SPI flash 125 | .PROGADDR_IRQ(32'h0005_0010), 126 | .MEM_WORDS(2048) // use 2KBytes of block RAM by default 127 | ) soc ( 128 | .clk (clk ), 129 | .resetn (resetn ), 130 | 131 | .ser_tx (pin_1 ), 132 | .ser_rx (pin_2 ), 133 | 134 | .flash_csb (flash_csb ), 135 | .flash_clk (flash_clk ), 136 | 137 | .flash_io0_oe (flash_io0_oe), 138 | .flash_io1_oe (flash_io1_oe), 139 | .flash_io2_oe (flash_io2_oe), 140 | .flash_io3_oe (flash_io3_oe), 141 | 142 | .flash_io0_do (flash_io0_do), 143 | .flash_io1_do (flash_io1_do), 144 | .flash_io2_do (flash_io2_do), 145 | .flash_io3_do (flash_io3_do), 146 | 147 | .flash_io0_di (flash_io0_di), 148 | .flash_io1_di (flash_io1_di), 149 | .flash_io2_di (flash_io2_di), 150 | .flash_io3_di (flash_io3_di), 151 | 152 | .irq_5 (1'b0 ), 153 | .irq_6 (1'b0 ), 154 | .irq_7 (1'b0 ), 155 | 156 | .iomem_valid (iomem_valid ), 157 | .iomem_ready (iomem_ready ), 158 | .iomem_wstrb (iomem_wstrb ), 159 | .iomem_addr (iomem_addr ), 160 | .iomem_wdata (iomem_wdata ), 161 | .iomem_rdata (iomem_rdata ) 162 | ); 163 | endmodule 164 | -------------------------------------------------------------------------------- /examples/picosoc/picosoc.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | `ifdef PICORV32_V 21 | `error "picosoc.v must be read before picorv32.v!" 22 | `endif 23 | 24 | `define PICORV32_REGS picosoc_regs 25 | 26 | module picosoc ( 27 | input clk, 28 | input resetn, 29 | 30 | output iomem_valid, 31 | input iomem_ready, 32 | output [ 3:0] iomem_wstrb, 33 | output [31:0] iomem_addr, 34 | output [31:0] iomem_wdata, 35 | input [31:0] iomem_rdata, 36 | 37 | input irq_5, 38 | input irq_6, 39 | input irq_7, 40 | 41 | output ser_tx, 42 | input ser_rx, 43 | 44 | output flash_csb, 45 | output flash_clk, 46 | 47 | output flash_io0_oe, 48 | output flash_io1_oe, 49 | output flash_io2_oe, 50 | output flash_io3_oe, 51 | 52 | output flash_io0_do, 53 | output flash_io1_do, 54 | output flash_io2_do, 55 | output flash_io3_do, 56 | 57 | input flash_io0_di, 58 | input flash_io1_di, 59 | input flash_io2_di, 60 | input flash_io3_di 61 | ); 62 | parameter integer MEM_WORDS = 256; 63 | parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory 64 | parameter [31:0] PROGADDR_RESET = 32'h 0005_0000; // 1 MB into flash 65 | parameter [31:0] PROGADDR_IRQ = 32'h 0005_0010; // 1 MB into flash 66 | 67 | reg [31:0] irq; 68 | wire irq_stall = 0; 69 | wire irq_uart = 0; 70 | 71 | always @* begin 72 | irq = 0; 73 | irq[3] = irq_stall; 74 | irq[4] = irq_uart; 75 | irq[5] = irq_5; 76 | irq[6] = irq_6; 77 | irq[7] = irq_7; 78 | end 79 | 80 | wire mem_valid; 81 | wire mem_instr; 82 | wire mem_ready; 83 | wire [31:0] mem_addr; 84 | wire [31:0] mem_wdata; 85 | wire [3:0] mem_wstrb; 86 | wire [31:0] mem_rdata; 87 | 88 | wire spimem_ready; 89 | wire [31:0] spimem_rdata; 90 | 91 | reg ram_ready; 92 | wire [31:0] ram_rdata; 93 | 94 | assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); 95 | assign iomem_wstrb = mem_wstrb; 96 | assign iomem_addr = mem_addr; 97 | assign iomem_wdata = mem_wdata; 98 | 99 | wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000); 100 | wire [31:0] spimemio_cfgreg_do; 101 | 102 | wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004); 103 | wire [31:0] simpleuart_reg_div_do; 104 | 105 | wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008); 106 | wire [31:0] simpleuart_reg_dat_do; 107 | wire simpleuart_reg_dat_wait; 108 | 109 | assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel || 110 | simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait); 111 | 112 | assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata : 113 | spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do : 114 | simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000; 115 | 116 | picorv32 #( 117 | .STACKADDR(STACKADDR), 118 | .PROGADDR_RESET(PROGADDR_RESET), 119 | .PROGADDR_IRQ(PROGADDR_IRQ), 120 | .BARREL_SHIFTER(1), 121 | .COMPRESSED_ISA(1), 122 | .ENABLE_MUL(1), 123 | .ENABLE_DIV(1), 124 | .ENABLE_IRQ(1), 125 | .ENABLE_IRQ_QREGS(1) 126 | ) cpu ( 127 | .clk (clk ), 128 | .resetn (resetn ), 129 | .mem_valid (mem_valid ), 130 | .mem_instr (mem_instr ), 131 | .mem_ready (mem_ready ), 132 | .mem_addr (mem_addr ), 133 | .mem_wdata (mem_wdata ), 134 | .mem_wstrb (mem_wstrb ), 135 | .mem_rdata (mem_rdata ), 136 | .irq (irq ) 137 | ); 138 | 139 | spimemio spimemio ( 140 | .clk (clk), 141 | .resetn (resetn), 142 | .valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000), 143 | .ready (spimem_ready), 144 | .addr (mem_addr[23:0]), 145 | .rdata (spimem_rdata), 146 | 147 | .flash_csb (flash_csb ), 148 | .flash_clk (flash_clk ), 149 | 150 | .flash_io0_oe (flash_io0_oe), 151 | .flash_io1_oe (flash_io1_oe), 152 | .flash_io2_oe (flash_io2_oe), 153 | .flash_io3_oe (flash_io3_oe), 154 | 155 | .flash_io0_do (flash_io0_do), 156 | .flash_io1_do (flash_io1_do), 157 | .flash_io2_do (flash_io2_do), 158 | .flash_io3_do (flash_io3_do), 159 | 160 | .flash_io0_di (flash_io0_di), 161 | .flash_io1_di (flash_io1_di), 162 | .flash_io2_di (flash_io2_di), 163 | .flash_io3_di (flash_io3_di), 164 | 165 | .cfgreg_we(spimemio_cfgreg_sel ? mem_wstrb : 4'b 0000), 166 | .cfgreg_di(mem_wdata), 167 | .cfgreg_do(spimemio_cfgreg_do) 168 | ); 169 | 170 | simpleuart simpleuart ( 171 | .clk (clk ), 172 | .resetn (resetn ), 173 | 174 | .ser_tx (ser_tx ), 175 | .ser_rx (ser_rx ), 176 | 177 | .reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000), 178 | .reg_div_di (mem_wdata), 179 | .reg_div_do (simpleuart_reg_div_do), 180 | 181 | .reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0), 182 | .reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb), 183 | .reg_dat_di (mem_wdata), 184 | .reg_dat_do (simpleuart_reg_dat_do), 185 | .reg_dat_wait(simpleuart_reg_dat_wait) 186 | ); 187 | 188 | always @(posedge clk) 189 | ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS; 190 | 191 | picosoc_mem #(.WORDS(MEM_WORDS)) memory ( 192 | .clk(clk), 193 | .wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0), 194 | .addr(mem_addr[23:2]), 195 | .wdata(mem_wdata), 196 | .rdata(ram_rdata) 197 | ); 198 | endmodule 199 | 200 | // Implementation note: 201 | // Replace the following two modules with wrappers for your SRAM cells. 202 | 203 | module picosoc_regs ( 204 | input clk, wen, 205 | input [5:0] waddr, 206 | input [5:0] raddr1, 207 | input [5:0] raddr2, 208 | input [31:0] wdata, 209 | output [31:0] rdata1, 210 | output [31:0] rdata2 211 | ); 212 | reg [31:0] regs [0:31]; 213 | 214 | always @(posedge clk) 215 | if (wen) regs[waddr[4:0]] <= wdata; 216 | 217 | assign rdata1 = regs[raddr1[4:0]]; 218 | assign rdata2 = regs[raddr2[4:0]]; 219 | endmodule 220 | 221 | module picosoc_mem #( 222 | parameter integer WORDS = 256 223 | ) ( 224 | input clk, 225 | input [3:0] wen, 226 | input [21:0] addr, 227 | input [31:0] wdata, 228 | output reg [31:0] rdata 229 | ); 230 | reg [31:0] mem [0:WORDS-1]; 231 | 232 | always @(posedge clk) begin 233 | rdata <= mem[addr]; 234 | if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0]; 235 | if (wen[1]) mem[addr][15: 8] <= wdata[15: 8]; 236 | if (wen[2]) mem[addr][23:16] <= wdata[23:16]; 237 | if (wen[3]) mem[addr][31:24] <= wdata[31:24]; 238 | end 239 | endmodule 240 | 241 | -------------------------------------------------------------------------------- /examples/picosoc/riscv_flash.ld: -------------------------------------------------------------------------------- 1 | /* Default linker script, for normal executables */ 2 | /* Copyright (C) 2014-2017 Free Software Foundation, Inc. 3 | Copying and distribution of this script, with or without modification, 4 | are permitted in any medium without royalty provided the copyright 5 | notice and this notice are preserved. */ 6 | OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", 7 | "elf32-littleriscv") 8 | OUTPUT_ARCH(riscv) 9 | /*ENTRY(_start)*/ 10 | SECTIONS 11 | { 12 | /* Stuff in .text.sram is located in SRAM */ 13 | . = 0x00000000; 14 | .text.sram : { 15 | *(.text.sram) 16 | } 17 | text_sram_end = .; 18 | 19 | /* In "flashpmem" mode everything above 1MB in the flash is */ 20 | /* mapped directly into the processor address space */ 21 | . = 0x00050000; 22 | .text : 23 | { 24 | *(.text) 25 | *(.text.unlikely .text.*_unlikely .text.unlikely.*) 26 | *(.text.exit .text.exit.*) 27 | *(.text.startup .text.startup.*) 28 | *(.text.hot .text.hot.*) 29 | *(.stub .text.* .gnu.linkonce.t.*) 30 | /* .gnu.warning sections are handled specially by elf32.em. */ 31 | *(.gnu.warning) 32 | } 33 | .init : 34 | { 35 | KEEP (*(SORT_NONE(.init))) 36 | } 37 | .plt : { *(.plt) } 38 | .iplt : { *(.iplt) } 39 | .fini : 40 | { 41 | KEEP (*(SORT_NONE(.fini))) 42 | } 43 | PROVIDE (__etext = .); 44 | PROVIDE (_etext = .); 45 | PROVIDE (etext = .); 46 | .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } 47 | .rodata1 : { *(.rodata1) } 48 | .sdata2 : 49 | { 50 | *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) 51 | } 52 | .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } 53 | .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } 54 | .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } 55 | .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table 56 | .gcc_except_table.*) } 57 | .gnu_extab : ONLY_IF_RO { *(.gnu_extab*) } 58 | /* These sections are generated by the Sun/Oracle C++ compiler. */ 59 | .exception_ranges : ONLY_IF_RO { *(.exception_ranges 60 | .exception_ranges*) } 61 | /* Adjust the address for the data segment. We want to adjust up to 62 | the same address within the page on the next page up. */ 63 | . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); 64 | /* Exception handling */ 65 | .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } 66 | .gnu_extab : ONLY_IF_RW { *(.gnu_extab) } 67 | .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } 68 | .exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } 69 | /* Thread Local Storage sections */ 70 | .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } 71 | .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } 72 | .preinit_array : 73 | { 74 | PROVIDE_HIDDEN (__preinit_array_start = .); 75 | KEEP (*(.preinit_array)) 76 | PROVIDE_HIDDEN (__preinit_array_end = .); 77 | } 78 | .init_array : 79 | { 80 | PROVIDE_HIDDEN (__init_array_start = .); 81 | KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) 82 | KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) 83 | PROVIDE_HIDDEN (__init_array_end = .); 84 | } 85 | .fini_array : 86 | { 87 | PROVIDE_HIDDEN (__fini_array_start = .); 88 | KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) 89 | KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) 90 | PROVIDE_HIDDEN (__fini_array_end = .); 91 | } 92 | .ctors : 93 | { 94 | /* gcc uses crtbegin.o to find the start of 95 | the constructors, so we make sure it is 96 | first. Because this is a wildcard, it 97 | doesn't matter if the user does not 98 | actually link against crtbegin.o; the 99 | linker won't look for a file to match a 100 | wildcard. The wildcard also means that it 101 | doesn't matter which directory crtbegin.o 102 | is in. */ 103 | KEEP (*crtbegin.o(.ctors)) 104 | KEEP (*crtbegin?.o(.ctors)) 105 | /* We don't want to include the .ctor section from 106 | the crtend.o file until after the sorted ctors. 107 | The .ctor section from the crtend file contains the 108 | end of ctors marker and it must be last */ 109 | KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) 110 | KEEP (*(SORT(.ctors.*))) 111 | KEEP (*(.ctors)) 112 | } 113 | .dtors : 114 | { 115 | KEEP (*crtbegin.o(.dtors)) 116 | KEEP (*crtbegin?.o(.dtors)) 117 | KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) 118 | KEEP (*(SORT(.dtors.*))) 119 | KEEP (*(.dtors)) 120 | } 121 | .jcr : { KEEP (*(.jcr)) } 122 | .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) } 123 | .dynamic : { *(.dynamic) } 124 | . = DATA_SEGMENT_RELRO_END (0, .); 125 | 126 | /* everything below is goind to be in SRAM */ 127 | . = text_sram_end; 128 | 129 | .data : 130 | { 131 | *(.data .data.* .gnu.linkonce.d.*) 132 | SORT(CONSTRUCTORS) 133 | } 134 | .data1 : { *(.data1) } 135 | .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } 136 | /* We want the small data sections together, so single-instruction offsets 137 | can access them all, and initialized data all before uninitialized, so 138 | we can shorten the on-disk segment size. */ 139 | .sdata : 140 | { 141 | __global_pointer$ = . + 0x800; 142 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) 143 | *(.sdata .sdata.* .gnu.linkonce.s.*) 144 | } 145 | _edata = .; PROVIDE (edata = .); 146 | . = .; 147 | __bss_start = .; 148 | .sbss : 149 | { 150 | *(.dynsbss) 151 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 152 | *(.scommon) 153 | } 154 | .bss : 155 | { 156 | *(.dynbss) 157 | *(.bss .bss.* .gnu.linkonce.b.*) 158 | *(COMMON) 159 | /* Align here to ensure that the .bss section occupies space up to 160 | _end. Align after .bss to ensure correct alignment even if the 161 | .bss section disappears because there are no input sections. 162 | FIXME: Why do we need it? When there is no .bss section, we don't 163 | pad the .data section. */ 164 | . = ALIGN(. != 0 ? 32 / 8 : 1); 165 | } 166 | . = ALIGN(32 / 8); 167 | . = SEGMENT_START("ldata-segment", .); 168 | . = ALIGN(32 / 8); 169 | _end = .; PROVIDE (end = .); 170 | . = DATA_SEGMENT_END (.); 171 | /* Stabs debugging sections. */ 172 | .stab 0 : { *(.stab) } 173 | .stabstr 0 : { *(.stabstr) } 174 | .stab.excl 0 : { *(.stab.excl) } 175 | .stab.exclstr 0 : { *(.stab.exclstr) } 176 | .stab.index 0 : { *(.stab.index) } 177 | .stab.indexstr 0 : { *(.stab.indexstr) } 178 | .comment 0 : { *(.comment) } 179 | /* DWARF debug sections. 180 | Symbols in the DWARF debugging sections are relative to the beginning 181 | of the section so we begin them at 0. */ 182 | /* DWARF 1 */ 183 | .debug 0 : { *(.debug) } 184 | .line 0 : { *(.line) } 185 | /* GNU DWARF 1 extensions */ 186 | .debug_srcinfo 0 : { *(.debug_srcinfo) } 187 | .debug_sfnames 0 : { *(.debug_sfnames) } 188 | /* DWARF 1.1 and DWARF 2 */ 189 | .debug_aranges 0 : { *(.debug_aranges) } 190 | .debug_pubnames 0 : { *(.debug_pubnames) } 191 | /* DWARF 2 */ 192 | .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } 193 | .debug_abbrev 0 : { *(.debug_abbrev) } 194 | .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } 195 | .debug_frame 0 : { *(.debug_frame) } 196 | .debug_str 0 : { *(.debug_str) } 197 | .debug_loc 0 : { *(.debug_loc) } 198 | .debug_macinfo 0 : { *(.debug_macinfo) } 199 | /* SGI/MIPS DWARF 2 extensions */ 200 | .debug_weaknames 0 : { *(.debug_weaknames) } 201 | .debug_funcnames 0 : { *(.debug_funcnames) } 202 | .debug_typenames 0 : { *(.debug_typenames) } 203 | .debug_varnames 0 : { *(.debug_varnames) } 204 | /* DWARF 3 */ 205 | .debug_pubtypes 0 : { *(.debug_pubtypes) } 206 | .debug_ranges 0 : { *(.debug_ranges) } 207 | /* DWARF Extension. */ 208 | .debug_macro 0 : { *(.debug_macro) } 209 | .debug_addr 0 : { *(.debug_addr) } 210 | .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } 211 | /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } 212 | } 213 | 214 | -------------------------------------------------------------------------------- /examples/picosoc/sections.lds: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | FLASH (rx) : ORIGIN = 0x00050000, LENGTH = 0x100000 /* entire flash, 1 MiB */ 4 | RAM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x002000 /* 8 KB */ 5 | } 6 | 7 | SECTIONS { 8 | /* The program code and other data goes into FLASH */ 9 | .text : 10 | { 11 | . = ALIGN(4); 12 | *(.text) /* .text sections (code) */ 13 | *(.text*) /* .text* sections (code) */ 14 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 15 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 16 | *(.srodata) /* .rodata sections (constants, strings, etc.) */ 17 | *(.srodata*) /* .rodata* sections (constants, strings, etc.) */ 18 | *(.eh_frame) 19 | *(.eh_frame*) 20 | . = ALIGN(4); 21 | _etext = .; /* define a global symbol at end of code */ 22 | _sidata = _etext; /* This is used by the startup in order to initialize the .data secion */ 23 | } >FLASH 24 | 25 | 26 | /* This is the initialized data section 27 | The program executes knowing that the data is in the RAM 28 | but the loader puts the initial values in the FLASH (inidata). 29 | It is one task of the startup to copy the initial values from FLASH to RAM. */ 30 | .data : AT ( _sidata ) 31 | { 32 | . = ALIGN(4); 33 | _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ 34 | _ram_start = .; /* create a global symbol at ram start for garbage collector */ 35 | *(.data) /* .data sections */ 36 | *(.data*) /* .data* sections */ 37 | *(.sdata) /* .sdata sections */ 38 | *(.sdata*) /* .sdata* sections */ 39 | *(.init_array) /* .sdata sections */ 40 | *(.init_array*) /* .sdata* sections */ 41 | . = ALIGN(4); 42 | _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ 43 | } >RAM 44 | 45 | /* Uninitialized data section */ 46 | .bss : 47 | { 48 | . = ALIGN(4); 49 | _sbss = .; /* define a global symbol at bss start; used by startup code */ 50 | *(.bss) 51 | *(.bss*) 52 | *(.sbss) 53 | *(.sbss*) 54 | *(COMMON) 55 | 56 | . = ALIGN(4); 57 | _ebss = .; /* define a global symbol at bss end; used by startup code */ 58 | } >RAM 59 | 60 | /* this is to define the start of the heap, and make sure we have a minimum size */ 61 | .heap : 62 | { 63 | . = ALIGN(4); 64 | _heap_start = .; /* define a global symbol at heap start */ 65 | } >RAM 66 | } 67 | -------------------------------------------------------------------------------- /examples/picosoc/simpleuart.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module simpleuart ( 21 | input clk, 22 | input resetn, 23 | 24 | output ser_tx, 25 | input ser_rx, 26 | 27 | input [3:0] reg_div_we, 28 | input [31:0] reg_div_di, 29 | output [31:0] reg_div_do, 30 | 31 | input reg_dat_we, 32 | input reg_dat_re, 33 | input [31:0] reg_dat_di, 34 | output [31:0] reg_dat_do, 35 | output reg_dat_wait 36 | ); 37 | reg [31:0] cfg_divider; 38 | 39 | reg [3:0] recv_state; 40 | reg [31:0] recv_divcnt; 41 | reg [7:0] recv_pattern; 42 | reg [7:0] recv_buf_data; 43 | reg recv_buf_valid; 44 | 45 | reg [9:0] send_pattern; 46 | reg [3:0] send_bitcnt; 47 | reg [31:0] send_divcnt; 48 | reg send_dummy; 49 | 50 | assign reg_div_do = cfg_divider; 51 | 52 | assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy); 53 | assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0; 54 | 55 | always @(posedge clk) begin 56 | if (!resetn) begin 57 | cfg_divider <= 1; 58 | end else begin 59 | if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0]; 60 | if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8]; 61 | if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16]; 62 | if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24]; 63 | end 64 | end 65 | 66 | always @(posedge clk) begin 67 | if (!resetn) begin 68 | recv_state <= 0; 69 | recv_divcnt <= 0; 70 | recv_pattern <= 0; 71 | recv_buf_data <= 0; 72 | recv_buf_valid <= 0; 73 | end else begin 74 | recv_divcnt <= recv_divcnt + 1; 75 | if (reg_dat_re) 76 | recv_buf_valid <= 0; 77 | case (recv_state) 78 | 0: begin 79 | if (!ser_rx) 80 | recv_state <= 1; 81 | recv_divcnt <= 0; 82 | end 83 | 1: begin 84 | if (2*recv_divcnt > cfg_divider) begin 85 | recv_state <= 2; 86 | recv_divcnt <= 0; 87 | end 88 | end 89 | 10: begin 90 | if (recv_divcnt > cfg_divider) begin 91 | recv_buf_data <= recv_pattern; 92 | recv_buf_valid <= 1; 93 | recv_state <= 0; 94 | end 95 | end 96 | default: begin 97 | if (recv_divcnt > cfg_divider) begin 98 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 99 | recv_state <= recv_state + 1; 100 | recv_divcnt <= 0; 101 | end 102 | end 103 | endcase 104 | end 105 | end 106 | 107 | assign ser_tx = send_pattern[0]; 108 | 109 | always @(posedge clk) begin 110 | if (reg_div_we) 111 | send_dummy <= 1; 112 | send_divcnt <= send_divcnt + 1; 113 | if (!resetn) begin 114 | send_pattern <= ~0; 115 | send_bitcnt <= 0; 116 | send_divcnt <= 0; 117 | send_dummy <= 1; 118 | end else begin 119 | if (send_dummy && !send_bitcnt) begin 120 | send_pattern <= ~0; 121 | send_bitcnt <= 15; 122 | send_divcnt <= 0; 123 | send_dummy <= 0; 124 | end else 125 | if (reg_dat_we && !send_bitcnt) begin 126 | send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0}; 127 | send_bitcnt <= 10; 128 | send_divcnt <= 0; 129 | end else 130 | if (send_divcnt > cfg_divider && send_bitcnt) begin 131 | send_pattern <= {1'b1, send_pattern[9:1]}; 132 | send_bitcnt <= send_bitcnt - 1; 133 | send_divcnt <= 0; 134 | end 135 | end 136 | end 137 | endmodule 138 | -------------------------------------------------------------------------------- /examples/picosoc/spiflash.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | `timescale 1 ns / 1 ps 21 | 22 | // 23 | // Simple SPI flash simulation model 24 | // 25 | // This model samples io input signals 1ns before the SPI clock edge and 26 | // updates output signals 1ns after the SPI clock edge. 27 | // 28 | // Supported commands: 29 | // AB, B9, FF, 03, BB, EB, ED 30 | // 31 | // Well written SPI flash data sheets: 32 | // Cypress S25FL064L http://www.cypress.com/file/316661/download 33 | // Cypress S25FL128L http://www.cypress.com/file/316171/download 34 | // 35 | 36 | module spiflash ( 37 | input csb, 38 | input clk, 39 | inout io0, // MOSI 40 | inout io1, // MISO 41 | inout io2, 42 | inout io3 43 | ); 44 | localparam verbose = 0; 45 | localparam integer latency = 8; 46 | 47 | reg [7:0] buffer; 48 | integer bitcount = 0; 49 | integer bytecount = 0; 50 | integer dummycount = 0; 51 | 52 | reg [7:0] spi_cmd; 53 | reg [7:0] xip_cmd = 0; 54 | reg [23:0] spi_addr; 55 | 56 | reg [7:0] spi_in; 57 | reg [7:0] spi_out; 58 | reg spi_io_vld; 59 | 60 | reg powered_up = 0; 61 | 62 | localparam [3:0] mode_spi = 1; 63 | localparam [3:0] mode_dspi_rd = 2; 64 | localparam [3:0] mode_dspi_wr = 3; 65 | localparam [3:0] mode_qspi_rd = 4; 66 | localparam [3:0] mode_qspi_wr = 5; 67 | localparam [3:0] mode_qspi_ddr_rd = 6; 68 | localparam [3:0] mode_qspi_ddr_wr = 7; 69 | 70 | reg [3:0] mode = 0; 71 | reg [3:0] next_mode = 0; 72 | 73 | reg io0_oe = 0; 74 | reg io1_oe = 0; 75 | reg io2_oe = 0; 76 | reg io3_oe = 0; 77 | 78 | reg io0_dout = 0; 79 | reg io1_dout = 0; 80 | reg io2_dout = 0; 81 | reg io3_dout = 0; 82 | 83 | assign #1 io0 = io0_oe ? io0_dout : 1'bz; 84 | assign #1 io1 = io1_oe ? io1_dout : 1'bz; 85 | assign #1 io2 = io2_oe ? io2_dout : 1'bz; 86 | assign #1 io3 = io3_oe ? io3_dout : 1'bz; 87 | 88 | wire io0_delayed; 89 | wire io1_delayed; 90 | wire io2_delayed; 91 | wire io3_delayed; 92 | 93 | assign #1 io0_delayed = io0; 94 | assign #1 io1_delayed = io1; 95 | assign #1 io2_delayed = io2; 96 | assign #1 io3_delayed = io3; 97 | 98 | // 16 MB (128Mb) Flash 99 | reg [7:0] memory [0:16*1024*1024-1]; 100 | 101 | initial begin 102 | $readmemh("firmware.hex", memory); 103 | end 104 | 105 | task spi_action; 106 | begin 107 | spi_in = buffer; 108 | 109 | if (bytecount == 1) begin 110 | spi_cmd = buffer; 111 | 112 | if (spi_cmd == 8'h ab) 113 | powered_up = 1; 114 | 115 | if (spi_cmd == 8'h b9) 116 | powered_up = 0; 117 | 118 | if (spi_cmd == 8'h ff) 119 | xip_cmd = 0; 120 | end 121 | 122 | if (powered_up && spi_cmd == 'h 03) begin 123 | if (bytecount == 2) 124 | spi_addr[23:16] = buffer; 125 | 126 | if (bytecount == 3) 127 | spi_addr[15:8] = buffer; 128 | 129 | if (bytecount == 4) 130 | spi_addr[7:0] = buffer; 131 | 132 | if (bytecount >= 4) begin 133 | buffer = memory[spi_addr]; 134 | spi_addr = spi_addr + 1; 135 | end 136 | end 137 | 138 | if (powered_up && spi_cmd == 'h bb) begin 139 | if (bytecount == 1) 140 | mode = mode_dspi_rd; 141 | 142 | if (bytecount == 2) 143 | spi_addr[23:16] = buffer; 144 | 145 | if (bytecount == 3) 146 | spi_addr[15:8] = buffer; 147 | 148 | if (bytecount == 4) 149 | spi_addr[7:0] = buffer; 150 | 151 | if (bytecount == 5) begin 152 | xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00; 153 | mode = mode_dspi_wr; 154 | dummycount = latency; 155 | end 156 | 157 | if (bytecount >= 5) begin 158 | buffer = memory[spi_addr]; 159 | spi_addr = spi_addr + 1; 160 | end 161 | end 162 | 163 | if (powered_up && spi_cmd == 'h eb) begin 164 | if (bytecount == 1) 165 | mode = mode_qspi_rd; 166 | 167 | if (bytecount == 2) 168 | spi_addr[23:16] = buffer; 169 | 170 | if (bytecount == 3) 171 | spi_addr[15:8] = buffer; 172 | 173 | if (bytecount == 4) 174 | spi_addr[7:0] = buffer; 175 | 176 | if (bytecount == 5) begin 177 | xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00; 178 | mode = mode_qspi_wr; 179 | dummycount = latency; 180 | end 181 | 182 | if (bytecount >= 5) begin 183 | buffer = memory[spi_addr]; 184 | spi_addr = spi_addr + 1; 185 | end 186 | end 187 | 188 | if (powered_up && spi_cmd == 'h ed) begin 189 | if (bytecount == 1) 190 | next_mode = mode_qspi_ddr_rd; 191 | 192 | if (bytecount == 2) 193 | spi_addr[23:16] = buffer; 194 | 195 | if (bytecount == 3) 196 | spi_addr[15:8] = buffer; 197 | 198 | if (bytecount == 4) 199 | spi_addr[7:0] = buffer; 200 | 201 | if (bytecount == 5) begin 202 | xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00; 203 | mode = mode_qspi_ddr_wr; 204 | dummycount = latency; 205 | end 206 | 207 | if (bytecount >= 5) begin 208 | buffer = memory[spi_addr]; 209 | spi_addr = spi_addr + 1; 210 | end 211 | end 212 | 213 | spi_out = buffer; 214 | spi_io_vld = 1; 215 | 216 | if (verbose) begin 217 | if (bytecount == 1) 218 | $write("<SPI-START>"); 219 | $write("<SPI:%02x:%02x>", spi_in, spi_out); 220 | end 221 | 222 | end 223 | endtask 224 | 225 | task ddr_rd_edge; 226 | begin 227 | buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed}; 228 | bitcount = bitcount + 4; 229 | if (bitcount == 8) begin 230 | bitcount = 0; 231 | bytecount = bytecount + 1; 232 | spi_action; 233 | end 234 | end 235 | endtask 236 | 237 | task ddr_wr_edge; 238 | begin 239 | io0_oe = 1; 240 | io1_oe = 1; 241 | io2_oe = 1; 242 | io3_oe = 1; 243 | 244 | io0_dout = buffer[4]; 245 | io1_dout = buffer[5]; 246 | io2_dout = buffer[6]; 247 | io3_dout = buffer[7]; 248 | 249 | buffer = {buffer, 4'h 0}; 250 | bitcount = bitcount + 4; 251 | if (bitcount == 8) begin 252 | bitcount = 0; 253 | bytecount = bytecount + 1; 254 | spi_action; 255 | end 256 | end 257 | endtask 258 | 259 | always @(csb) begin 260 | if (csb) begin 261 | if (verbose) begin 262 | $display(""); 263 | $fflush; 264 | end 265 | buffer = 0; 266 | bitcount = 0; 267 | bytecount = 0; 268 | mode = mode_spi; 269 | io0_oe = 0; 270 | io1_oe = 0; 271 | io2_oe = 0; 272 | io3_oe = 0; 273 | end else 274 | if (xip_cmd) begin 275 | buffer = xip_cmd; 276 | bitcount = 0; 277 | bytecount = 1; 278 | spi_action; 279 | end 280 | end 281 | 282 | always @(csb, clk) begin 283 | spi_io_vld = 0; 284 | if (!csb && !clk) begin 285 | if (dummycount > 0) begin 286 | io0_oe = 0; 287 | io1_oe = 0; 288 | io2_oe = 0; 289 | io3_oe = 0; 290 | end else 291 | case (mode) 292 | mode_spi: begin 293 | io0_oe = 0; 294 | io1_oe = 1; 295 | io2_oe = 0; 296 | io3_oe = 0; 297 | io1_dout = buffer[7]; 298 | end 299 | mode_dspi_rd: begin 300 | io0_oe = 0; 301 | io1_oe = 0; 302 | io2_oe = 0; 303 | io3_oe = 0; 304 | end 305 | mode_dspi_wr: begin 306 | io0_oe = 1; 307 | io1_oe = 1; 308 | io2_oe = 0; 309 | io3_oe = 0; 310 | io0_dout = buffer[6]; 311 | io1_dout = buffer[7]; 312 | end 313 | mode_qspi_rd: begin 314 | io0_oe = 0; 315 | io1_oe = 0; 316 | io2_oe = 0; 317 | io3_oe = 0; 318 | end 319 | mode_qspi_wr: begin 320 | io0_oe = 1; 321 | io1_oe = 1; 322 | io2_oe = 1; 323 | io3_oe = 1; 324 | io0_dout = buffer[4]; 325 | io1_dout = buffer[5]; 326 | io2_dout = buffer[6]; 327 | io3_dout = buffer[7]; 328 | end 329 | mode_qspi_ddr_rd: begin 330 | ddr_rd_edge; 331 | end 332 | mode_qspi_ddr_wr: begin 333 | ddr_wr_edge; 334 | end 335 | endcase 336 | if (next_mode) begin 337 | case (next_mode) 338 | mode_qspi_ddr_rd: begin 339 | io0_oe = 0; 340 | io1_oe = 0; 341 | io2_oe = 0; 342 | io3_oe = 0; 343 | end 344 | mode_qspi_ddr_wr: begin 345 | io0_oe = 1; 346 | io1_oe = 1; 347 | io2_oe = 1; 348 | io3_oe = 1; 349 | io0_dout = buffer[4]; 350 | io1_dout = buffer[5]; 351 | io2_dout = buffer[6]; 352 | io3_dout = buffer[7]; 353 | end 354 | endcase 355 | mode = next_mode; 356 | next_mode = 0; 357 | end 358 | end 359 | end 360 | 361 | always @(posedge clk) begin 362 | if (!csb) begin 363 | if (dummycount > 0) begin 364 | dummycount = dummycount - 1; 365 | end else 366 | case (mode) 367 | mode_spi: begin 368 | buffer = {buffer, io0}; 369 | bitcount = bitcount + 1; 370 | if (bitcount == 8) begin 371 | bitcount = 0; 372 | bytecount = bytecount + 1; 373 | spi_action; 374 | end 375 | end 376 | mode_dspi_rd, mode_dspi_wr: begin 377 | buffer = {buffer, io1, io0}; 378 | bitcount = bitcount + 2; 379 | if (bitcount == 8) begin 380 | bitcount = 0; 381 | bytecount = bytecount + 1; 382 | spi_action; 383 | end 384 | end 385 | mode_qspi_rd, mode_qspi_wr: begin 386 | buffer = {buffer, io3, io2, io1, io0}; 387 | bitcount = bitcount + 4; 388 | if (bitcount == 8) begin 389 | bitcount = 0; 390 | bytecount = bytecount + 1; 391 | spi_action; 392 | end 393 | end 394 | mode_qspi_ddr_rd: begin 395 | ddr_rd_edge; 396 | end 397 | mode_qspi_ddr_wr: begin 398 | ddr_wr_edge; 399 | end 400 | endcase 401 | end 402 | end 403 | endmodule 404 | -------------------------------------------------------------------------------- /examples/picosoc/spimemio.v: -------------------------------------------------------------------------------- 1 | /* 2 | * PicoSoC - A simple example SoC using PicoRV32 3 | * 4 | * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module spimemio ( 21 | input clk, resetn, 22 | 23 | input valid, 24 | output ready, 25 | input [23:0] addr, 26 | output reg [31:0] rdata, 27 | 28 | output flash_csb, 29 | output flash_clk, 30 | 31 | output flash_io0_oe, 32 | output flash_io1_oe, 33 | output flash_io2_oe, 34 | output flash_io3_oe, 35 | 36 | output flash_io0_do, 37 | output flash_io1_do, 38 | output flash_io2_do, 39 | output flash_io3_do, 40 | 41 | input flash_io0_di, 42 | input flash_io1_di, 43 | input flash_io2_di, 44 | input flash_io3_di, 45 | 46 | input [3:0] cfgreg_we, 47 | input [31:0] cfgreg_di, 48 | output [31:0] cfgreg_do 49 | ); 50 | reg xfer_resetn; 51 | reg din_valid; 52 | wire din_ready; 53 | reg [7:0] din_data; 54 | reg [3:0] din_tag; 55 | reg din_cont; 56 | reg din_qspi; 57 | reg din_ddr; 58 | reg din_rd; 59 | 60 | wire dout_valid; 61 | wire [7:0] dout_data; 62 | wire [3:0] dout_tag; 63 | 64 | reg [23:0] buffer; 65 | 66 | reg [23:0] rd_addr; 67 | reg rd_valid; 68 | reg rd_wait; 69 | reg rd_inc; 70 | 71 | assign ready = valid && (addr == rd_addr) && rd_valid; 72 | wire jump = valid && !ready && (addr != rd_addr+4) && rd_valid; 73 | 74 | reg softreset; 75 | 76 | reg config_en; // cfgreg[31] 77 | reg config_ddr; // cfgreg[22] 78 | reg config_qspi; // cfgreg[21] 79 | reg config_cont; // cfgreg[20] 80 | reg [3:0] config_dummy; // cfgreg[19:16] 81 | reg [3:0] config_oe; // cfgreg[11:8] 82 | reg config_csb; // cfgreg[5] 83 | reg config_clk; // cfgref[4] 84 | reg [3:0] config_do; // cfgreg[3:0] 85 | 86 | assign cfgreg_do[31] = config_en; 87 | assign cfgreg_do[30:23] = 0; 88 | assign cfgreg_do[22] = config_ddr; 89 | assign cfgreg_do[21] = config_qspi; 90 | assign cfgreg_do[20] = config_cont; 91 | assign cfgreg_do[19:16] = config_dummy; 92 | assign cfgreg_do[15:12] = 0; 93 | assign cfgreg_do[11:8] = {flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}; 94 | assign cfgreg_do[7:6] = 0; 95 | assign cfgreg_do[5] = flash_csb; 96 | assign cfgreg_do[4] = flash_clk; 97 | assign cfgreg_do[3:0] = {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}; 98 | 99 | always @(posedge clk) begin 100 | softreset <= !config_en || cfgreg_we; 101 | if (!resetn) begin 102 | softreset <= 1; 103 | config_en <= 1; 104 | config_csb <= 0; 105 | config_clk <= 0; 106 | config_oe <= 0; 107 | config_do <= 0; 108 | config_ddr <= 0; 109 | config_qspi <= 0; 110 | config_cont <= 0; 111 | config_dummy <= 8; 112 | end else begin 113 | if (cfgreg_we[0]) begin 114 | config_csb <= cfgreg_di[5]; 115 | config_clk <= cfgreg_di[4]; 116 | config_do <= cfgreg_di[3:0]; 117 | end 118 | if (cfgreg_we[1]) begin 119 | config_oe <= cfgreg_di[11:8]; 120 | end 121 | if (cfgreg_we[2]) begin 122 | config_ddr <= cfgreg_di[22]; 123 | config_qspi <= cfgreg_di[21]; 124 | config_cont <= cfgreg_di[20]; 125 | config_dummy <= cfgreg_di[19:16]; 126 | end 127 | if (cfgreg_we[3]) begin 128 | config_en <= cfgreg_di[31]; 129 | end 130 | end 131 | end 132 | 133 | wire xfer_csb; 134 | wire xfer_clk; 135 | 136 | wire xfer_io0_oe; 137 | wire xfer_io1_oe; 138 | wire xfer_io2_oe; 139 | wire xfer_io3_oe; 140 | 141 | wire xfer_io0_do; 142 | wire xfer_io1_do; 143 | wire xfer_io2_do; 144 | wire xfer_io3_do; 145 | 146 | reg xfer_io0_90; 147 | reg xfer_io1_90; 148 | reg xfer_io2_90; 149 | reg xfer_io3_90; 150 | 151 | always @(negedge clk) begin 152 | xfer_io0_90 <= xfer_io0_do; 153 | xfer_io1_90 <= xfer_io1_do; 154 | xfer_io2_90 <= xfer_io2_do; 155 | xfer_io3_90 <= xfer_io3_do; 156 | end 157 | 158 | assign flash_csb = config_en ? xfer_csb : config_csb; 159 | assign flash_clk = config_en ? xfer_clk : config_clk; 160 | 161 | assign flash_io0_oe = config_en ? xfer_io0_oe : config_oe[0]; 162 | assign flash_io1_oe = config_en ? xfer_io1_oe : config_oe[1]; 163 | assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2]; 164 | assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3]; 165 | 166 | assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0]; 167 | assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1]; 168 | assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2]; 169 | assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3]; 170 | 171 | wire xfer_dspi = din_ddr && !din_qspi; 172 | wire xfer_ddr = din_ddr && din_qspi; 173 | 174 | spimemio_xfer xfer ( 175 | .clk (clk ), 176 | .resetn (xfer_resetn ), 177 | .din_valid (din_valid ), 178 | .din_ready (din_ready ), 179 | .din_data (din_data ), 180 | .din_tag (din_tag ), 181 | .din_cont (din_cont ), 182 | .din_dspi (xfer_dspi ), 183 | .din_qspi (din_qspi ), 184 | .din_ddr (xfer_ddr ), 185 | .din_rd (din_rd ), 186 | .dout_valid (dout_valid ), 187 | .dout_data (dout_data ), 188 | .dout_tag (dout_tag ), 189 | .flash_csb (xfer_csb ), 190 | .flash_clk (xfer_clk ), 191 | .flash_io0_oe (xfer_io0_oe ), 192 | .flash_io1_oe (xfer_io1_oe ), 193 | .flash_io2_oe (xfer_io2_oe ), 194 | .flash_io3_oe (xfer_io3_oe ), 195 | .flash_io0_do (xfer_io0_do ), 196 | .flash_io1_do (xfer_io1_do ), 197 | .flash_io2_do (xfer_io2_do ), 198 | .flash_io3_do (xfer_io3_do ), 199 | .flash_io0_di (flash_io0_di), 200 | .flash_io1_di (flash_io1_di), 201 | .flash_io2_di (flash_io2_di), 202 | .flash_io3_di (flash_io3_di) 203 | ); 204 | 205 | reg [3:0] state; 206 | 207 | always @(posedge clk) begin 208 | xfer_resetn <= 1; 209 | din_valid <= 0; 210 | 211 | if (!resetn || softreset) begin 212 | state <= 0; 213 | xfer_resetn <= 0; 214 | rd_valid <= 0; 215 | din_tag <= 0; 216 | din_cont <= 0; 217 | din_qspi <= 0; 218 | din_ddr <= 0; 219 | din_rd <= 0; 220 | end else begin 221 | if (dout_valid && dout_tag == 1) buffer[ 7: 0] <= dout_data; 222 | if (dout_valid && dout_tag == 2) buffer[15: 8] <= dout_data; 223 | if (dout_valid && dout_tag == 3) buffer[23:16] <= dout_data; 224 | if (dout_valid && dout_tag == 4) begin 225 | rdata <= {dout_data, buffer}; 226 | rd_addr <= rd_inc ? rd_addr + 4 : addr; 227 | rd_valid <= 1; 228 | rd_wait <= rd_inc; 229 | rd_inc <= 1; 230 | end 231 | 232 | if (valid) 233 | rd_wait <= 0; 234 | 235 | case (state) 236 | 0: begin 237 | din_valid <= 1; 238 | din_data <= 8'h ff; 239 | din_tag <= 0; 240 | if (din_ready) begin 241 | din_valid <= 0; 242 | state <= 1; 243 | end 244 | end 245 | 1: begin 246 | if (dout_valid) begin 247 | xfer_resetn <= 0; 248 | state <= 2; 249 | end 250 | end 251 | 2: begin 252 | din_valid <= 1; 253 | din_data <= 8'h ab; 254 | din_tag <= 0; 255 | if (din_ready) begin 256 | din_valid <= 0; 257 | state <= 3; 258 | end 259 | end 260 | 3: begin 261 | if (dout_valid) begin 262 | xfer_resetn <= 0; 263 | state <= 4; 264 | end 265 | end 266 | 4: begin 267 | rd_inc <= 0; 268 | din_valid <= 1; 269 | din_tag <= 0; 270 | case ({config_ddr, config_qspi}) 271 | 2'b11: din_data <= 8'h ED; 272 | 2'b01: din_data <= 8'h EB; 273 | 2'b10: din_data <= 8'h BB; 274 | 2'b00: din_data <= 8'h 03; 275 | endcase 276 | if (din_ready) begin 277 | din_valid <= 0; 278 | state <= 5; 279 | end 280 | end 281 | 5: begin 282 | if (valid && !ready) begin 283 | din_valid <= 1; 284 | din_tag <= 0; 285 | din_data <= addr[23:16]; 286 | din_qspi <= config_qspi; 287 | din_ddr <= config_ddr; 288 | if (din_ready) begin 289 | din_valid <= 0; 290 | state <= 6; 291 | end 292 | end 293 | end 294 | 6: begin 295 | din_valid <= 1; 296 | din_tag <= 0; 297 | din_data <= addr[15:8]; 298 | if (din_ready) begin 299 | din_valid <= 0; 300 | state <= 7; 301 | end 302 | end 303 | 7: begin 304 | din_valid <= 1; 305 | din_tag <= 0; 306 | din_data <= addr[7:0]; 307 | if (din_ready) begin 308 | din_valid <= 0; 309 | din_data <= 0; 310 | state <= config_qspi || config_ddr ? 8 : 9; 311 | end 312 | end 313 | 8: begin 314 | din_valid <= 1; 315 | din_tag <= 0; 316 | din_data <= config_cont ? 8'h A5 : 8'h FF; 317 | if (din_ready) begin 318 | din_rd <= 1; 319 | din_data <= config_dummy; 320 | din_valid <= 0; 321 | state <= 9; 322 | end 323 | end 324 | 9: begin 325 | din_valid <= 1; 326 | din_tag <= 1; 327 | if (din_ready) begin 328 | din_valid <= 0; 329 | state <= 10; 330 | end 331 | end 332 | 10: begin 333 | din_valid <= 1; 334 | din_data <= 8'h 00; 335 | din_tag <= 2; 336 | if (din_ready) begin 337 | din_valid <= 0; 338 | state <= 11; 339 | end 340 | end 341 | 11: begin 342 | din_valid <= 1; 343 | din_tag <= 3; 344 | if (din_ready) begin 345 | din_valid <= 0; 346 | state <= 12; 347 | end 348 | end 349 | 12: begin 350 | if (!rd_wait || valid) begin 351 | din_valid <= 1; 352 | din_tag <= 4; 353 | if (din_ready) begin 354 | din_valid <= 0; 355 | state <= 9; 356 | end 357 | end 358 | end 359 | endcase 360 | 361 | if (jump) begin 362 | rd_inc <= 0; 363 | rd_valid <= 0; 364 | xfer_resetn <= 0; 365 | if (config_cont) begin 366 | state <= 5; 367 | end else begin 368 | state <= 4; 369 | din_qspi <= 0; 370 | din_ddr <= 0; 371 | end 372 | din_rd <= 0; 373 | end 374 | end 375 | end 376 | endmodule 377 | 378 | module spimemio_xfer ( 379 | input clk, resetn, 380 | 381 | input din_valid, 382 | output din_ready, 383 | input [7:0] din_data, 384 | input [3:0] din_tag, 385 | input din_cont, 386 | input din_dspi, 387 | input din_qspi, 388 | input din_ddr, 389 | input din_rd, 390 | 391 | output dout_valid, 392 | output [7:0] dout_data, 393 | output [3:0] dout_tag, 394 | 395 | output reg flash_csb, 396 | output reg flash_clk, 397 | 398 | output reg flash_io0_oe, 399 | output reg flash_io1_oe, 400 | output reg flash_io2_oe, 401 | output reg flash_io3_oe, 402 | 403 | output reg flash_io0_do, 404 | output reg flash_io1_do, 405 | output reg flash_io2_do, 406 | output reg flash_io3_do, 407 | 408 | input flash_io0_di, 409 | input flash_io1_di, 410 | input flash_io2_di, 411 | input flash_io3_di 412 | ); 413 | reg [7:0] obuffer; 414 | reg [7:0] ibuffer; 415 | 416 | reg [3:0] count; 417 | reg [3:0] dummy_count; 418 | 419 | reg xfer_cont; 420 | reg xfer_dspi; 421 | reg xfer_qspi; 422 | reg xfer_ddr; 423 | reg xfer_ddr_q; 424 | reg xfer_rd; 425 | reg [3:0] xfer_tag; 426 | reg [3:0] xfer_tag_q; 427 | 428 | reg [7:0] next_obuffer; 429 | reg [7:0] next_ibuffer; 430 | reg [3:0] next_count; 431 | 432 | reg fetch; 433 | reg next_fetch; 434 | reg last_fetch; 435 | 436 | always @(posedge clk) begin 437 | xfer_ddr_q <= xfer_ddr; 438 | xfer_tag_q <= xfer_tag; 439 | end 440 | 441 | assign din_ready = din_valid && resetn && next_fetch; 442 | 443 | assign dout_valid = (xfer_ddr_q ? fetch && !last_fetch : next_fetch && !fetch) && resetn; 444 | assign dout_data = ibuffer; 445 | assign dout_tag = xfer_tag_q; 446 | 447 | always @* begin 448 | flash_io0_oe = 0; 449 | flash_io1_oe = 0; 450 | flash_io2_oe = 0; 451 | flash_io3_oe = 0; 452 | 453 | flash_io0_do = 0; 454 | flash_io1_do = 0; 455 | flash_io2_do = 0; 456 | flash_io3_do = 0; 457 | 458 | next_obuffer = obuffer; 459 | next_ibuffer = ibuffer; 460 | next_count = count; 461 | next_fetch = 0; 462 | 463 | if (dummy_count == 0) begin 464 | casez ({xfer_ddr, xfer_qspi, xfer_dspi}) 465 | 3'b 000: begin 466 | flash_io0_oe = 1; 467 | flash_io0_do = obuffer[7]; 468 | 469 | if (flash_clk) begin 470 | next_obuffer = {obuffer[6:0], 1'b 0}; 471 | next_count = count - |count; 472 | end else begin 473 | next_ibuffer = {ibuffer[6:0], flash_io1_di}; 474 | end 475 | 476 | next_fetch = (next_count == 0); 477 | end 478 | 3'b 01?: begin 479 | flash_io0_oe = !xfer_rd; 480 | flash_io1_oe = !xfer_rd; 481 | flash_io2_oe = !xfer_rd; 482 | flash_io3_oe = !xfer_rd; 483 | 484 | flash_io0_do = obuffer[4]; 485 | flash_io1_do = obuffer[5]; 486 | flash_io2_do = obuffer[6]; 487 | flash_io3_do = obuffer[7]; 488 | 489 | if (flash_clk) begin 490 | next_obuffer = {obuffer[3:0], 4'b 0000}; 491 | next_count = count - {|count, 2'b00}; 492 | end else begin 493 | next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}; 494 | end 495 | 496 | next_fetch = (next_count == 0); 497 | end 498 | 3'b 11?: begin 499 | flash_io0_oe = !xfer_rd; 500 | flash_io1_oe = !xfer_rd; 501 | flash_io2_oe = !xfer_rd; 502 | flash_io3_oe = !xfer_rd; 503 | 504 | flash_io0_do = obuffer[4]; 505 | flash_io1_do = obuffer[5]; 506 | flash_io2_do = obuffer[6]; 507 | flash_io3_do = obuffer[7]; 508 | 509 | next_obuffer = {obuffer[3:0], 4'b 0000}; 510 | next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}; 511 | next_count = count - {|count, 2'b00}; 512 | 513 | next_fetch = (next_count == 0); 514 | end 515 | 3'b ??1: begin 516 | flash_io0_oe = !xfer_rd; 517 | flash_io1_oe = !xfer_rd; 518 | 519 | flash_io0_do = obuffer[6]; 520 | flash_io1_do = obuffer[7]; 521 | 522 | if (flash_clk) begin 523 | next_obuffer = {obuffer[5:0], 2'b 00}; 524 | next_count = count - {|count, 1'b0}; 525 | end else begin 526 | next_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di}; 527 | end 528 | 529 | next_fetch = (next_count == 0); 530 | end 531 | endcase 532 | end 533 | end 534 | 535 | always @(posedge clk) begin 536 | if (!resetn) begin 537 | fetch <= 1; 538 | last_fetch <= 1; 539 | flash_csb <= 1; 540 | flash_clk <= 0; 541 | count <= 0; 542 | dummy_count <= 0; 543 | xfer_tag <= 0; 544 | xfer_cont <= 0; 545 | xfer_dspi <= 0; 546 | xfer_qspi <= 0; 547 | xfer_ddr <= 0; 548 | xfer_rd <= 0; 549 | end else begin 550 | fetch <= next_fetch; 551 | last_fetch <= xfer_ddr ? fetch : 1; 552 | if (dummy_count) begin 553 | flash_clk <= !flash_clk && !flash_csb; 554 | dummy_count <= dummy_count - flash_clk; 555 | end else 556 | if (count) begin 557 | flash_clk <= !flash_clk && !flash_csb; 558 | obuffer <= next_obuffer; 559 | ibuffer <= next_ibuffer; 560 | count <= next_count; 561 | end 562 | if (din_valid && din_ready) begin 563 | flash_csb <= 0; 564 | flash_clk <= 0; 565 | 566 | count <= 8; 567 | dummy_count <= din_rd ? din_data : 0; 568 | obuffer <= din_data; 569 | 570 | xfer_tag <= din_tag; 571 | xfer_cont <= din_cont; 572 | xfer_dspi <= din_dspi; 573 | xfer_qspi <= din_qspi; 574 | xfer_ddr <= din_ddr; 575 | xfer_rd <= din_rd; 576 | end 577 | end 578 | end 579 | endmodule 580 | -------------------------------------------------------------------------------- /examples/picosoc/start.S: -------------------------------------------------------------------------------- 1 | // This is free and unencumbered software released into the public domain. 2 | // 3 | // Anyone is free to copy, modify, publish, use, compile, sell, or 4 | // distribute this software, either in source code form or as a compiled 5 | // binary, for any purpose, commercial or non-commercial, and by any 6 | // means. 7 | 8 | 9 | #include "custom_ops.S" 10 | .section .data 11 | 12 | .balign 4 13 | irq_handler_addr: 14 | .word 0x0000000000000000 15 | soft_q2: 16 | .word 0x0000000000000000 17 | soft_q3: 18 | .word 0x0000000000000000 19 | soft_q0: 20 | .word 0 21 | soft_q1: 22 | .word 0 23 | 24 | 25 | 26 | 27 | 28 | .section .text 29 | 30 | reset_vec: 31 | // no more than 8 bytes here ! 32 | j start 33 | 34 | .global debug 35 | 36 | .balign 16 37 | irq_vec: 38 | 39 | /* save registers */ 40 | //picorv32_setq_insn(q2, x1) 41 | //picorv32_setq_insn(q3, x2) 42 | sw x1, 4(zero) 43 | sw x2, 8(zero) 44 | 45 | 46 | picorv32_getq_insn(x1, q0) 47 | sw x1, 12(zero) 48 | picorv32_getq_insn(x1, q1) 49 | sw x1, 16(zero) 50 | 51 | 52 | 53 | 54 | 55 | // x2 is the stack pointer 56 | lui x2, %hi(4096 - 4*32) 57 | addi x2, x2, %lo(4096 - 4*32) 58 | 59 | picorv32_getq_insn(x1, q0) 60 | sw x1, 0*4(x2) 61 | 62 | 63 | //picorv32_getq_insn(x1, q2) 64 | lw x1, 4(zero) 65 | sw x1, 1*4(x2) 66 | 67 | //picorv32_getq_insn(x1, q3) 68 | lw x1, 8(zero) 69 | sw x1, 2*4(x2) 70 | 71 | sw x3, 3*4(x2) 72 | sw x4, 4*4(x2) 73 | sw x5, 5*4(x2) 74 | sw x6, 6*4(x2) 75 | sw x7, 7*4(x2) 76 | sw x8, 8*4(x2) 77 | sw x9, 9*4(x2) 78 | sw x10, 10*4(x2) 79 | sw x11, 11*4(x2) 80 | sw x12, 12*4(x2) 81 | sw x13, 13*4(x2) 82 | sw x14, 14*4(x2) 83 | sw x15, 15*4(x2) 84 | sw x16, 16*4(x2) 85 | sw x17, 17*4(x2) 86 | sw x18, 18*4(x2) 87 | sw x19, 19*4(x2) 88 | sw x20, 20*4(x2) 89 | sw x21, 21*4(x2) 90 | sw x22, 22*4(x2) 91 | sw x23, 23*4(x2) 92 | sw x24, 24*4(x2) 93 | sw x25, 25*4(x2) 94 | sw x26, 26*4(x2) 95 | sw x27, 27*4(x2) 96 | sw x28, 28*4(x2) 97 | sw x29, 29*4(x2) 98 | sw x30, 30*4(x2) 99 | sw x31, 31*4(x2) 100 | 101 | /* call interrupt handler C function */ 102 | 103 | // arg0 = interrupt type bitmask 104 | picorv32_getq_insn(a0, q1) 105 | 106 | // arg1 = pointer to stored registers 107 | mv a1, x2 108 | 109 | // load irq handler address to x1 (ra) 110 | lw x1, 0(zero) 111 | 112 | // call to C function 113 | beq x0, x1, 1f 114 | jalr x1, x1, 0 115 | 1: 116 | 117 | /* restore registers */ 118 | 119 | lw x1, 0*4(x2) 120 | picorv32_setq_insn(q0, x1) 121 | 122 | 123 | lw x1, 1*4(x2) 124 | picorv32_setq_insn(q1, x1) 125 | 126 | lw x1, 2*4(x2) 127 | //picorv32_setq_insn(q2, x1) 128 | sw x1, 4(zero) 129 | 130 | 131 | lw x3, 3*4(x2) 132 | lw x4, 4*4(x2) 133 | lw x5, 5*4(x2) 134 | lw x6, 6*4(x2) 135 | lw x7, 7*4(x2) 136 | lw x8, 8*4(x2) 137 | lw x9, 9*4(x2) 138 | lw x10, 10*4(x2) 139 | lw x11, 11*4(x2) 140 | lw x12, 12*4(x2) 141 | lw x13, 13*4(x2) 142 | lw x14, 14*4(x2) 143 | lw x15, 15*4(x2) 144 | lw x16, 16*4(x2) 145 | lw x17, 17*4(x2) 146 | lw x18, 18*4(x2) 147 | lw x19, 19*4(x2) 148 | lw x20, 20*4(x2) 149 | lw x21, 21*4(x2) 150 | lw x22, 22*4(x2) 151 | lw x23, 23*4(x2) 152 | lw x24, 24*4(x2) 153 | lw x25, 25*4(x2) 154 | lw x26, 26*4(x2) 155 | lw x27, 27*4(x2) 156 | lw x28, 28*4(x2) 157 | lw x29, 29*4(x2) 158 | lw x30, 30*4(x2) 159 | lw x31, 31*4(x2) 160 | 161 | picorv32_getq_insn(x1, q1) 162 | //picorv32_getq_insn(x2, q2) 163 | lw x2, 4(zero) 164 | 165 | //mv a0, x2 166 | //call debug 167 | nop 168 | nop 169 | nop 170 | picorv32_retirq_insn() 171 | 172 | 173 | 174 | /* Main program 175 | **********************************/ 176 | 177 | start: 178 | /* zero-initialize all registers */ 179 | 180 | addi x1, zero, 0 181 | //addi x2, zero, 0 182 | addi x3, zero, 0 183 | addi x4, zero, 0 184 | addi x5, zero, 0 185 | addi x6, zero, 0 186 | addi x7, zero, 0 187 | addi x8, zero, 0 188 | addi x9, zero, 0 189 | addi x10, zero, 0 190 | addi x11, zero, 0 191 | addi x12, zero, 0 192 | addi x13, zero, 0 193 | addi x14, zero, 0 194 | addi x15, zero, 0 195 | addi x16, zero, 0 196 | addi x17, zero, 0 197 | addi x18, zero, 0 198 | addi x19, zero, 0 199 | addi x20, zero, 0 200 | addi x21, zero, 0 201 | addi x22, zero, 0 202 | addi x23, zero, 0 203 | addi x24, zero, 0 204 | addi x25, zero, 0 205 | addi x26, zero, 0 206 | addi x27, zero, 0 207 | addi x28, zero, 0 208 | addi x29, zero, 0 209 | addi x30, zero, 0 210 | addi x31, zero, 0 211 | 212 | # copy data section 213 | la a0, _sidata # load _sidata to a0 214 | la a1, _sdata # load _sdata to a1 215 | la a2, _edata # load _edata to a2 216 | bge a1, a2, end_init_data # if _edata > _sdata jump to end 217 | 218 | loop_init_data: 219 | lw a3, 0(a0) # load data at a0 to a3 220 | sw a3, 0(a1) # store data in a3 to a1 (_sdata) 221 | addi a0, a0, 4 # add 4 to a0 222 | addi a1, a1, 4 # add 4 to a1 223 | blt a1, a2, loop_init_data # if a1 < a2 finish 224 | 225 | end_init_data: 226 | 227 | # zero-init bss section 228 | la a0, _sbss 229 | la a1, _ebss 230 | bge a0, a1, end_init_bss 231 | 232 | loop_init_bss: 233 | sw zero, 0(a0) 234 | addi a0, a0, 4 235 | blt a0, a1, loop_init_bss 236 | 237 | end_init_bss: 238 | call main 239 | 240 | loop: 241 | j loop 242 | 243 | 244 | 245 | 246 | -------------------------------------------------------------------------------- /icecube2_template/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | 3 | # iCEcube SDC 4 | 5 | # Version: 2017.01.27914 6 | 7 | # File Generated: Jul 9 2017 15:15:35 8 | 9 | # ############################################################################## 10 | 11 | ####---- CreateClock list ----1 12 | create_clock -period 62.50 -name {pin3_clk_16mhz} [get_ports {pin3_clk_16mhz}] 13 | 14 | -------------------------------------------------------------------------------- /icecube2_template/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | 3 | # iCEcube PCF 4 | 5 | # Version: 2017.01.27914 6 | 7 | # File Generated: Jun 24 2017 13:04:57 8 | 9 | # Family & Device: iCE40LP8K 10 | 11 | # Package: CM81 12 | 13 | # ############################################################################## 14 | 15 | ###IOSet List 24 16 | set_io pin13 J1 17 | set_io pin15_sdi H7 18 | set_io pin1_usb_dp A3 19 | set_io pin20 E8 20 | set_io pin2_usb_dn A4 21 | set_io pin4 B2 22 | set_io pin10 E1 23 | set_io pin18 D9 24 | set_io pin7 B1 25 | set_io pin11 G1 26 | set_io pin19 C9 27 | set_io pin22 A8 28 | set_io pin6 A1 29 | set_io pin12 H1 30 | set_io pin16_sck G7 31 | set_io pin21 A9 32 | set_io pin5 A2 33 | set_io pin9 D1 34 | set_io pin14_sdo G6 35 | set_io pin24 A6 36 | set_io pin8 C1 37 | set_io pin17_ss F7 38 | set_io pin23 A7 39 | set_io pin3_clk_16mhz B4 40 | 41 | -------------------------------------------------------------------------------- /icecube2_template/template_lse.prj: -------------------------------------------------------------------------------- 1 | #-- Lattice, Inc. 2 | #-- Project file C:\lscc\iCEcube2.2017.01\sbt_backend\Projects\template\template_lse.prj 3 | 4 | #device 5 | -a SBTiCE40 6 | -d iCE40LP8K 7 | -t CM81 8 | #constraint file 9 | -sdc "constraints/clk.sdc" 10 | 11 | #options 12 | -optimization_goal Area 13 | -twr_paths 3 14 | -bram_utilization 100.00 15 | -ramstyle Auto 16 | -romstyle Auto 17 | -use_carry_chain 1 18 | -carry_chain_length 0 19 | -resource_sharing 1 20 | -propagate_constants 1 21 | -remove_duplicate_regs 1 22 | -max_fanout 10000 23 | -fsm_encoding_style Auto 24 | -use_io_insertion 1 25 | -use_io_reg auto 26 | -resolve_mixed_drivers 0 27 | -RWCheckOnRam 0 28 | -fix_gated_clocks 1 29 | -loop_limit 1950 30 | 31 | -ver "verilog/TinyFPGA_B.v" 32 | -p "C:/lscc/iCEcube2.2017.01/sbt_backend/Projects/template" 33 | 34 | #set result format/file last 35 | -output_edif template_Implmnt/template.edf 36 | 37 | #set log file 38 | -logfile "template_Implmnt/template_lse.log" 39 | -------------------------------------------------------------------------------- /icecube2_template/template_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.01.27914 - Build Date: Jan 12 2017 19:10:45 4 | ProjectName=template 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=verilog/TinyFPGA_B.v=work 8 | ProjectCFiles= 9 | CurImplementation=template_Implmnt 10 | Implementations=template_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [template_Implmnt] 42 | DeviceFamily=iCE40 43 | Device=LP8K 44 | DevicePackage=CM81 45 | DevicePower= 46 | NetlistFile=template_Implmnt/template.edf 47 | AdditionalEDIFFile= 48 | IPEDIFFile= 49 | DesignLib=template_Implmnt/sbt/netlist/oadb-TinyFPGA_B 50 | DesignView=_rt 51 | DesignCell=TinyFPGA_B 52 | SynthesisSDCFile=template_Implmnt/template.scf 53 | UserPinConstraintFile= 54 | UserSDCFile=constraints/clk.sdc 55 | PhysicalConstraintFile=constraints/pins.pcf 56 | BackendImplPathName= 57 | Devicevoltage=1.14 58 | DevicevoltagePerformance=+/-5%(datasheet default) 59 | DeviceTemperature=85 60 | TimingAnalysisBasedOn=Worst 61 | OperationRange=Commercial 62 | TypicalCustomTemperature=25 63 | WorstCustomTemperature=85 64 | BestCustomTemperature=0 65 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 66 | derValue=1.03369 67 | TimingPathNumberStick=0 68 | 69 | [tool options] 70 | PlacerEffortLevel=std 71 | PlacerAutoLutCascade=yes 72 | PlacerAutoRamCascade=yes 73 | PlacerPowerDriven=no 74 | PlacerAreaDriven=no 75 | RouteWithTimingDriven=yes 76 | RouteWithPinPermutation=yes 77 | BitmapSPIFlashMode=yes 78 | BitmapRAM4KInit=yes 79 | BitmapInitRamBank=1111 80 | BitmapOscillatorFR=low 81 | BitmapEnableWarmBoot=yes 82 | BitmapDisableHeader=no 83 | BitmapSetSecurity=no 84 | BitmapSetNoUsedIONoPullup=no 85 | FloorPlannerShowFanInNets=yes 86 | FloorPlannerShowFanOutNets=yes 87 | HookTo3rdPartyTextEditor=no 88 | 89 | -------------------------------------------------------------------------------- /icecube2_template/template_syn.prd: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version L-2016.09L+ice40 3 | #-- Project file C:\lscc\iCEcube2.2017.01\sbt_backend\Projects\template\template_syn.prd 4 | #-- Written on Thu Jun 29 00:07:23 2017 5 | 6 | # 7 | ### Watch Implementation type ### 8 | # 9 | watch_impl -all 10 | # 11 | ### Watch Implementation properties ### 12 | # 13 | watch_prop -clear 14 | -------------------------------------------------------------------------------- /icecube2_template/template_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version L-2016.09L+ice40 3 | #-- Project file C:\lscc\iCEcube2.2017.01\sbt_backend\Projects\template\template_syn.prj 4 | #-- Written on Sun Jun 04 23:11:47 2017 5 | 6 | 7 | #project files 8 | 9 | add_file -verilog -lib work "verilog/TinyFPGA_B.v" 10 | #implementation: "template_Implmnt" 11 | impl -add template_Implmnt -type fpga 12 | 13 | # 14 | #implementation attributes 15 | 16 | set_option -vlog_std v2001 17 | set_option -project_relative_includes 1 18 | 19 | #device options 20 | set_option -technology SBTiCE40 21 | set_option -part iCE40LP8K 22 | set_option -package CM81 23 | set_option -speed_grade 24 | set_option -part_companion "" 25 | 26 | #compilation/mapping options 27 | 28 | # hdl_compiler_options 29 | set_option -distributed_compile 0 30 | 31 | # mapper_without_write_options 32 | set_option -frequency auto 33 | set_option -srs_instrumentation 1 34 | 35 | # mapper_options 36 | set_option -write_verilog 0 37 | set_option -write_vhdl 0 38 | 39 | # Lattice iCE40 40 | set_option -maxfan 10000 41 | set_option -rw_check_on_ram 0 42 | set_option -disable_io_insertion 0 43 | set_option -pipe 1 44 | set_option -retiming 0 45 | set_option -update_models_cp 0 46 | set_option -fix_gated_and_generated_clocks 1 47 | set_option -run_prop_extract 1 48 | 49 | # NFilter 50 | set_option -no_sequential_opt 0 51 | 52 | # sequential_optimization_options 53 | set_option -symbolic_fsm_compiler 1 54 | 55 | # Compiler Options 56 | set_option -compiler_compatible 0 57 | set_option -resource_sharing 1 58 | 59 | # Compiler Options 60 | set_option -auto_infer_blackbox 0 61 | 62 | #automatic place and route (vendor) options 63 | set_option -write_apr_constraint 1 64 | 65 | #set result format/file last 66 | project -result_file "template_Implmnt/template.edf" 67 | impl -active template_Implmnt 68 | project -run synthesis -clean 69 | -------------------------------------------------------------------------------- /icecube2_template/verilog/TinyFPGA_B.v: -------------------------------------------------------------------------------- 1 | module TinyFPGA_B ( 2 | inout pin1_usb_dp, 3 | inout pin2_usb_dn, 4 | input pin3_clk_16mhz, 5 | inout pin4, 6 | inout pin5, 7 | inout pin6, 8 | inout pin7, 9 | inout pin8, 10 | inout pin9, 11 | inout pin10, 12 | inout pin11, 13 | inout pin12, 14 | inout pin13, 15 | inout pin14_sdo, 16 | inout pin15_sdi, 17 | inout pin16_sck, 18 | inout pin17_ss, 19 | inout pin18, 20 | inout pin19, 21 | inout pin20, 22 | inout pin21, 23 | inout pin22, 24 | inout pin23, 25 | inout pin24 26 | ); 27 | 28 | // left side of board 29 | assign pin1_usb_dp = 1'bz; 30 | assign pin2_usb_dn = 1'bz; 31 | assign pin4 = 1'bz; 32 | assign pin5 = 1'bz; 33 | assign pin6 = 1'bz; 34 | assign pin7 = 1'bz; 35 | assign pin8 = 1'bz; 36 | assign pin9 = 1'bz; 37 | assign pin10 = 1'bz; 38 | assign pin11 = 1'bz; 39 | assign pin12 = 1'bz; 40 | assign pin13 = 1'bz; 41 | 42 | // right side of board 43 | assign pin14_sdo = 1'bz; 44 | assign pin15_sdi = 1'bz; 45 | assign pin16_sck = 1'bz; 46 | assign pin17_ss = 1'bz; 47 | assign pin18 = 1'bz; 48 | assign pin19 = 1'bz; 49 | assign pin20 = 1'bz; 50 | assign pin21 = 1'bz; 51 | assign pin22 = 1'bz; 52 | assign pin23 = 1'bz; 53 | assign pin24 = 1'bz; 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /icestorm_template/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile 2 | # 3 | # The following license is from the icestorm project and specifically applies to this file only: 4 | # 5 | # Permission to use, copy, modify, and/or distribute this software for any 6 | # purpose with or without fee is hereby granted, provided that the above 7 | # copyright notice and this permission notice appear in all copies. 8 | # 9 | # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 | # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 | # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 | # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 | # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 | # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 | # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 | 17 | PROJ = top 18 | 19 | PIN_DEF = pins.pcf 20 | DEVICE = lp8k 21 | 22 | all: $(PROJ).rpt $(PROJ).bin 23 | 24 | %.blif: %.v 25 | yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $< 26 | 27 | %.asc: $(PIN_DEF) %.blif 28 | arachne-pnr -d 8k -P cm81 -o $@ -p $^ 29 | 30 | %.bin: %.asc 31 | icepack $< $@ 32 | 33 | %.rpt: %.asc 34 | icetime -d $(DEVICE) -mtr $@ $< 35 | 36 | %_tb: %_tb.v %.v 37 | iverilog -o $@ $^ 38 | 39 | %_tb.vcd: %_tb 40 | vvp -N $< +vcd=$@ 41 | 42 | %_syn.v: %.blif 43 | yosys -p 'read_blif -wideports $^; write_verilog $@' 44 | 45 | %_syntb: %_tb.v %_syn.v 46 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 47 | 48 | %_syntb.vcd: %_syntb 49 | vvp -N $< +vcd=$@ 50 | 51 | prog: $(PROJ).bin 52 | tinyprog -p $< 53 | 54 | sudo-prog: $(PROJ).bin 55 | @echo 'Executing prog as root!!!' 56 | sudo tinyprog -p $< 57 | 58 | clean: 59 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin 60 | 61 | .SECONDARY: 62 | .PHONY: all prog clean 63 | -------------------------------------------------------------------------------- /icestorm_template/README.md: -------------------------------------------------------------------------------- 1 | Install [icestorm](http://www.clifford.at/icestorm/) for your computer once: 2 | 3 | ```sh 4 | sudo apt-get install build-essential clang bison flex libreadline-dev \ 5 | gawk tcl-dev libffi-dev git mercurial graphviz \ 6 | xdot pkg-config python python3 libftdi-dev 7 | 8 | mkdir icestorm-build 9 | cd icestorm-build 10 | 11 | git clone https://github.com/cliffordwolf/icestorm.git icestorm 12 | cd icestorm 13 | make -j$(nproc) 14 | sudo make install 15 | cd .. 16 | 17 | 18 | git clone https://github.com/cseed/arachne-pnr.git arachne-pnr 19 | cd arachne-pnr 20 | make -j$(nproc) 21 | sudo make install 22 | cd .. 23 | 24 | git clone https://github.com/cliffordwolf/yosys.git yosys 25 | cd yosys 26 | make -j$(nproc) 27 | sudo make install 28 | cd .. 29 | 30 | pip install --user tinyprog 31 | ``` 32 | 33 | Copy the icestorm_template directory to a new project directory with a name of your choosing: 34 | 35 | ```shell 36 | cp icestorm_template ~/my_tinyfpga_project 37 | ``` 38 | 39 | Build the project: 40 | ```shell 41 | cd ~/my_tinyfpga_project 42 | make 43 | ``` 44 | 45 | Program the TinyFPGA B-series board with the bitstream: 46 | ```shell 47 | make prog 48 | ``` 49 | 50 | 51 | -------------------------------------------------------------------------------- /icestorm_template/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # TinyFPGA BX constraint file (.pcf) 4 | # 5 | ############################################################################### 6 | # 7 | # Copyright (c) 2018, Luke Valenty 8 | # All rights reserved. 9 | # 10 | # Redistribution and use in source and binary forms, with or without 11 | # modification, are permitted provided that the following conditions are met: 12 | # 13 | # 1. Redistributions of source code must retain the above copyright notice, this 14 | # list of conditions and the following disclaimer. 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23 | # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 | # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 | # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # The views and conclusions contained in the software and documentation are those 31 | # of the authors and should not be interpreted as representing official policies, 32 | # either expressed or implied, of the <project name> project. 33 | # 34 | ############################################################################### 35 | 36 | #### 37 | # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/ 38 | #### 39 | 40 | # Left side of board 41 | set_io --warn-no-port PIN_1 A2 42 | set_io --warn-no-port PIN_2 A1 43 | set_io --warn-no-port PIN_3 B1 44 | set_io --warn-no-port PIN_4 C2 45 | set_io --warn-no-port PIN_5 C1 46 | set_io --warn-no-port PIN_6 D2 47 | set_io --warn-no-port PIN_7 D1 48 | set_io --warn-no-port PIN_8 E2 49 | set_io --warn-no-port PIN_9 E1 50 | set_io --warn-no-port PIN_10 G2 51 | set_io --warn-no-port PIN_11 H1 52 | set_io --warn-no-port PIN_12 J1 53 | set_io --warn-no-port PIN_13 H2 54 | 55 | # Right side of board 56 | set_io --warn-no-port PIN_14 H9 57 | set_io --warn-no-port PIN_15 D9 58 | set_io --warn-no-port PIN_16 D8 59 | set_io --warn-no-port PIN_17 C9 60 | set_io --warn-no-port PIN_18 A9 61 | set_io --warn-no-port PIN_19 B8 62 | set_io --warn-no-port PIN_20 A8 63 | set_io --warn-no-port PIN_21 B7 64 | set_io --warn-no-port PIN_22 A7 65 | set_io --warn-no-port PIN_23 B6 66 | set_io --warn-no-port PIN_24 A6 67 | 68 | # SPI flash interface on bottom of board 69 | set_io --warn-no-port SPI_SS F7 70 | set_io --warn-no-port SPI_SCK G7 71 | set_io --warn-no-port SPI_IO0 G6 72 | set_io --warn-no-port SPI_IO1 H7 73 | set_io --warn-no-port SPI_IO2 H4 74 | set_io --warn-no-port SPI_IO3 J8 75 | 76 | # General purpose pins on bottom of board 77 | set_io --warn-no-port PIN_25 G1 78 | set_io --warn-no-port PIN_26 J3 79 | set_io --warn-no-port PIN_27 J4 80 | set_io --warn-no-port PIN_28 G9 81 | set_io --warn-no-port PIN_29 J9 82 | set_io --warn-no-port PIN_30 E8 83 | set_io --warn-no-port PIN_31 J2 84 | 85 | # LED 86 | set_io --warn-no-port LED B3 87 | 88 | # USB 89 | set_io --warn-no-port USBP B4 90 | set_io --warn-no-port USBN A4 91 | set_io --warn-no-port USBPU A3 92 | 93 | # 16MHz clock 94 | set_io --warn-no-port CLK B2 # input 95 | -------------------------------------------------------------------------------- /icestorm_template/top.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module top ( 3 | input CLK, // 16MHz clock 4 | output LED, // User/boot LED next to power LED 5 | output USBPU // USB pull-up resistor 6 | ); 7 | // drive USB pull-up resistor to '0' to disable USB 8 | assign USBPU = 0; 9 | 10 | //////// 11 | // make a simple blink circuit 12 | //////// 13 | 14 | // keep track of time and location in blink_pattern 15 | reg [25:0] blink_counter; 16 | 17 | // pattern that will be flashed over the LED over time 18 | wire [31:0] blink_pattern = 32'b101010001110111011100010101; 19 | 20 | // increment the blink_counter every clock 21 | always @(posedge CLK) begin 22 | blink_counter <= blink_counter + 1; 23 | end 24 | 25 | // light up the LED according to the pattern 26 | assign LED = blink_pattern[blink_counter[25:21]]; 27 | endmodule 28 | --------------------------------------------------------------------------------