└── README.md /README.md: -------------------------------------------------------------------------------- 1 | # Awesome open source ASIC resources 2 | 3 | [Terminology](https://zerotoasiccourse.com/terminology/) 4 | 5 | ## Digital focussed tools 6 | 7 | * [OpenLane](https://openlane-docs.readthedocs.io/en/rtd-develop/) - end to end ASIC flow 8 | * [OpenROAD](https://github.com/The-OpenROAD-Project) - provides many of the tools in OpenLane 9 | * [Silicon Compiler](https://www.siliconcompiler.com/) - end to end ASIC flow 10 | * [Coriolis 2](http://coriolis.lip6.fr/) - end to end ASIC flow 11 | * [OSS Cad Suite](https://github.com/YosysHQ/oss-cad-suite-build) - lots of open source tools useful for digital design 12 | * [OSFPGA](https://github.com/os-fpga) - end to end FPGA flow with open source tools such as Yosys, VTR and VPR 13 | * [VHDL support - with GHDL](https://docs.google.com/document/d/1RAQWjmxpJndlEJdLWXK8irIqWuYTstqu7pU3tOIFccc/edit) 14 | * [Awesome list of verification tools](https://github.com/troyguo/awesome-dv) 15 | * [Awesome list of HDL tools / libraries / cores ...](https://hdl.github.io/awesome/) 16 | * [SemiWiki's list of open EDA tools](https://semiwiki.com/wikis/industry-wikis/eda-open-source-tools-wiki/) 17 | * [Andreas' list of awesome hardware tools](https://github.com/aolofsson/awesome-hardware-tools) 18 | 19 | ## High level synthesis (HLS) 20 | 21 | * [Amaranth](https://github.com/amaranth-lang) 22 | * [XLS](https://google.github.io/xls/) 23 | * [Spinal](https://github.com/SpinalHDL/SpinalHDL) 24 | 25 | ## Analogue focussed tools 26 | 27 | * [Magic](http://opencircuitdesign.com/magic/) - old school, layout drawing tool; still a requirement in the modern flows. [Cheatsheet](https://github.com/hpretl/iic-osic/blob/main/magic-cheatsheet/magic_cheatsheet.pdf). 28 | * [Klayout](https://www.klayout.de/) - modern style layout drawing tool. 29 | * [Xschem](https://xschem.sourceforge.io/stefan/index.html) - old school, schematic capture 30 | * [Mosaic](https://nyancad.github.io/Mosaic/) - schematic capture (experimental) 31 | * [Ngspice](http://ngspice.sourceforge.net/) - simulation 32 | * [Xyce](https://xyce.sandia.gov/) - simulation 33 | * [gdsfactory](https://gdsfactory.github.io/gdsfactory/) - EDA tool to Layout and simulate Integrated Circuits. 34 | 35 | ## Generators 36 | 37 | * [OpenRAM](https://openram.soe.ucsc.edu/) - SRAM generator 38 | * [DFFRAM](https://github.com/Cloud-V/DFFRAM) - Memory Compiler using FF/Latch cells 39 | * [OpenFASoC](https://github.com/idea-fasoc/OpenFASOC) - Analogue IP generator (LDO, temperature sense etc) 40 | * [MOSAIC_BAG2](https://gitlab.com/mosaic_group/mosaic_BAG/virtuoso_template) - Analogue IP generator framework (w/minimum working example) 41 | * [RgGen](https://github.com/rggen/rggen) - CSR generator (SystemVerilog/Verilog/VHDL RTL, UVM reg model etc) 42 | 43 | ## PDK 44 | 45 | * [Sky130](https://skywater-pdk.readthedocs.io/en/main/) 46 | * Watch this space! 47 | 48 | ## Community 49 | 50 | * [Skywater PDK Slack](https://join.slack.com/t/skywater-pdk/shared_invite/zt-ggcxts4x-4V5AwC950Zv9YgbZ4g~sMQ) 51 | * [Twitter list](https://twitter.com/i/lists/1510948904736628736) 52 | 53 | ## Videos 54 | 55 | * Zero to ASIC course videos, interviews, news [https://www.youtube.com/zerotoasic](https://www.youtube.com/zerotoasic) 56 | * Asianometry - the promise of open source EDA tools [https://www.youtube.com/watch?v=OmEbzRp_NGg](https://www.youtube.com/watch?v=OmEbzRp_NGg) 57 | 58 | ## How to get started with the Google sponsored shuttle 59 | 60 | * [Quickstart guide](https://caravel-user-project.readthedocs.io/en/latest/quickstart.html) 61 | * Then [join the community slack](https://join.slack.com/t/skywater-pdk/shared_invite/zt-ggcxts4x-4V5AwC950Zv9YgbZ4g~sMQ) #shuttle & #caravel channels. 62 | * Check the [FAQ](https://docs.google.com/document/d/1Y7LuP_0dJ_vmD8G_Twc6qc97fj7aW5pRV5nAjN2oOUk/edit#heading=h.dabsoa4nkp71) 63 | * See the projects submitted here: [https://platform.efabless.com/projects/public](https://platform.efabless.com/projects/public) 64 | 65 | ## Conferences 66 | 67 | * [The open source digital design conference](https://orconf.org/) 68 | * OpenTapeout [https://www.youtube.com/playlist?list=PLyynFETmdQDQdLCIu_HJBFNY17AAFp5W7](https://www.youtube.com/playlist?list=PLyynFETmdQDQdLCIu_HJBFNY17AAFp5W7) 69 | * FOSSi events: [https://www.fossi-foundation.org/events](https://www.fossi-foundation.org/events) 70 | * Free silicon conference: [https://wiki.f-si.org/index.php/FSiC2022](https://wiki.f-si.org/index.php/FSiC2022) 71 | 72 | ## Courses 73 | 74 | * [Zero To ASIC course](https://zerotoasiccourse.com/) 75 | * [VSD VLSI courses on Udemy](https://www.udemy.com/course/vlsi-academy-custom-layout/) 76 | 77 | ## Articles 78 | 79 | * [https://www.theregister.com/2020/07/03/open_chip_hardware/](https://www.theregister.com/2020/07/03/open_chip_hardware/) 80 | * [http://olofkindgren.blogspot.com/2019/12/2019-year-of-risc-v-and-open-source.html](http://olofkindgren.blogspot.com/2019/12/2019-year-of-risc-v-and-open-source.html) 81 | * [https://zerotoasiccourse.com/post/](https://zerotoasiccourse.com/post/) 82 | 83 | ## Mailing lists / newsletters 84 | 85 | * El correo libre: [https://medium.com/librecores/el-correo-libre-issue-46-11028b1d0e63#ead0](https://medium.com/librecores/el-correo-libre-issue-46-11028b1d0e63#ead0) 86 | * [https://zerotoasiccourse.com/newsletter/](https://zerotoasiccourse.com/newsletter/) 87 | 88 | ## Interest groups 89 | 90 | * [FOSSi](https://www.fossi-foundation.org/) - FOSSi Foundation is a non-profit foundation with the mission to promote and assist free and open digital hardware designs and their related ecosystems. 91 | * [Chips Alliance](https://chipsalliance.org/) - CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development 92 | * [WOSET](https://woset-workshop.github.io/) - The WOSET workshop aims to galvanize the open-source EDA movement. 93 | 94 | ## Companies 95 | 96 | * [ChipFlow](https://www.chipflow.io/) - Helping product companies to make their own chips with open source tools 97 | * [Efabless](https://efabless.com/) - simplifying chip creation 98 | * [LibreSilicon](https://libresilicon.com/) - open source manufacturing process standard 99 | * [LowRISC](https://lowrisc.org/open-silicon/) - open source silicon designs and tools 100 | * [Skywater Technology](https://www.skywatertechnology.com/) - foundry that first published open source PDK 101 | * [OpenHW Group](https://www.openhwgroup.org/) - open-source cores, verification, software and standards 102 | * [YosysHQ](https://www.yosyshq.com/) - open source EDA & Formal Verification 103 | * [ZeroASIC](https://www.zeroasic.com/) - makers of silicon compiler ASIC tool flow 104 | 105 | ## Work in progress 106 | 107 | * [Luna PnR](https://github.com/asicsforthemasses) 108 | --------------------------------------------------------------------------------