├── .gitignore ├── settings.gradle ├── src ├── test │ ├── resources │ │ └── testData │ │ │ ├── test3.v │ │ │ └── test.v │ └── java │ │ └── com │ │ └── verilogplugin │ │ ├── VerilogParsingTest.java │ │ └── VerilogCodeInsightTest.java ├── main │ ├── resources │ │ ├── psi.png │ │ └── setting.png │ └── java │ │ └── com │ │ └── verilogplugin │ │ ├── icons │ │ └── jar-gray.png │ │ └── lang │ │ ├── core │ │ ├── psi │ │ │ ├── VerilogNamedElement.java │ │ │ ├── VerilogElementType.java │ │ │ ├── VerilogTokenType.java │ │ │ ├── VerilogFile.java │ │ │ └── VerilogElementFactory.java │ │ ├── VerilogLanguage.java │ │ ├── lexer │ │ │ └── VerilogLexerAdapter.java │ │ ├── VerilogAdapter.java │ │ ├── VerilogIcons.java │ │ ├── VerilogFileTypeFactory.java │ │ └── VerilogFileType.java │ │ ├── codestyle │ │ └── VerilogCodeStyleSettings.java │ │ ├── highlight │ │ └── VerilogSyntaxHighlighterFactory.java │ │ └── commenter │ │ └── VerilogCommenter.java └── gen │ └── com │ └── verilogplugin │ └── lang │ └── core │ └── psi │ ├── VerilogCaseType.java │ ├── VerilogOptSigned.java │ ├── VerilogTopRecover.java │ ├── VerilogOptionalComma.java │ ├── VerilogParamInteger.java │ ├── VerilogParamSigned.java │ ├── VerilogWireTypeToken.java │ ├── VerilogWireTypeTokenListRest.java │ ├── VerilogId.java │ ├── VerilogAssert_.java │ ├── VerilogSingleArg.java │ ├── VerilogAlwaysEvent.java │ ├── VerilogArgList.java │ ├── VerilogAttr.java │ ├── VerilogOptLabel.java │ ├── VerilogParamRange.java │ ├── VerilogDefattr.java │ ├── VerilogRange.java │ ├── VerilogAssignExpr.java │ ├── VerilogAttrListRest.java │ ├── VerilogGenStmtBlock.java │ ├── VerilogLvalueConcatList.java │ ├── VerilogNonOptRange.java │ ├── VerilogOptAttrList.java │ ├── VerilogRangeOrInteger.java │ ├── VerilogAlwaysCond.java │ ├── VerilogAttrOpt.java │ ├── VerilogCaseSelect.java │ ├── VerilogOptGenElse.java │ ├── VerilogTokPrimWrapper.java │ ├── VerilogAssignStmt.java │ ├── VerilogGenStmtOrNull.java │ ├── VerilogModuleArgOptAssignment.java │ ├── VerilogWireType.java │ ├── VerilogDefparamDecl.java │ ├── VerilogOptionalElse.java │ ├── VerilogOptSynopsysAttr.java │ ├── VerilogTaskFuncBody.java │ ├── VerilogBehavioralStmtOpt.java │ ├── VerilogCellParameterListOpt.java │ ├── VerilogExpr.java │ ├── VerilogCellPort.java │ ├── VerilogWireName.java │ ├── VerilogCellParameter.java │ ├── VerilogArgList2.java │ ├── VerilogCaseBody.java │ ├── VerilogCellList.java │ ├── VerilogConcatList.java │ ├── VerilogFuncDecl.java │ ├── VerilogPrimList.java │ ├── VerilogSingleParamDecl.java │ ├── VerilogTaskDecl.java │ ├── VerilogAttrAssign.java │ ├── VerilogCaseExprList.java │ ├── VerilogLvalue.java │ ├── VerilogSingleCell.java │ ├── VerilogTaskFuncDecl.java │ ├── VerilogAttrList.java │ ├── VerilogModuleArgs.java │ ├── VerilogOptArgList.java │ ├── VerilogSimpleBehavioralStmt.java │ ├── VerilogCellPortList.java │ ├── VerilogGenCaseBody.java │ ├── VerilogGenCaseItem.java │ ├── VerilogModuleGenBody.java │ ├── VerilogSinglePrim.java │ ├── VerilogWireNameAndOptAssign.java │ ├── VerilogAlwaysEvents.java │ ├── VerilogCaseItem.java │ ├── VerilogHierarchicalId.java │ ├── VerilogAssignExprList.java │ ├── VerilogModuleBody.java │ ├── VerilogParamDeclList.java │ ├── VerilogModuleBodyRest.java │ ├── VerilogWireNameList.java │ ├── VerilogCellParameterList.java │ ├── VerilogBehavioralStmtList.java │ ├── VerilogDefparamDeclList.java │ ├── VerilogWireTypeTokenList.java │ ├── VerilogAlwaysStmt.java │ ├── VerilogSingleDefparamDecl.java │ ├── VerilogParamDecl.java │ ├── VerilogLocalparamDecl.java │ ├── VerilogWireDecl.java │ ├── VerilogRvalue.java │ ├── VerilogModuleArg.java │ ├── VerilogCellStmt.java │ ├── VerilogModule.java │ ├── VerilogGenStmt.java │ ├── VerilogBasicExpr.java │ ├── VerilogModuleBodyStmt.java │ ├── impl │ ├── VerilogCaseTypeImpl.java │ ├── VerilogOptSignedImpl.java │ ├── VerilogTopRecoverImpl.java │ ├── VerilogParamSignedImpl.java │ ├── VerilogParamIntegerImpl.java │ ├── VerilogOptionalCommaImpl.java │ ├── VerilogWireTypeTokenImpl.java │ ├── VerilogWireTypeTokenListRestImpl.java │ ├── VerilogIdImpl.java │ ├── VerilogAssignExprImpl.java │ ├── VerilogAssert_Impl.java │ ├── VerilogOptLabelImpl.java │ ├── VerilogRangeImpl.java │ ├── VerilogArgListImpl.java │ ├── VerilogSingleArgImpl.java │ ├── VerilogAlwaysEventImpl.java │ ├── VerilogParamRangeImpl.java │ ├── VerilogAttrImpl.java │ ├── VerilogDefattrImpl.java │ ├── VerilogOptAttrListImpl.java │ ├── VerilogAlwaysCondImpl.java │ ├── VerilogAttrListRestImpl.java │ ├── VerilogCaseSelectImpl.java │ ├── VerilogGenStmtBlockImpl.java │ ├── VerilogRangeOrIntegerImpl.java │ ├── VerilogTokPrimWrapperImpl.java │ ├── VerilogOptGenElseImpl.java │ ├── VerilogAssignStmtImpl.java │ ├── VerilogLvalueConcatListImpl.java │ ├── VerilogWireTypeImpl.java │ ├── VerilogAttrOptImpl.java │ ├── VerilogGenStmtOrNullImpl.java │ ├── VerilogNonOptRangeImpl.java │ ├── VerilogOptionalElseImpl.java │ ├── VerilogDefparamDeclImpl.java │ ├── VerilogOptSynopsysAttrImpl.java │ ├── VerilogBehavioralStmtOptImpl.java │ ├── VerilogModuleArgOptAssignmentImpl.java │ ├── VerilogTaskFuncBodyImpl.java │ ├── VerilogCellParameterListOptImpl.java │ ├── VerilogCellPortImpl.java │ ├── VerilogExprImpl.java │ ├── VerilogWireNameImpl.java │ ├── VerilogCaseBodyImpl.java │ ├── VerilogArgList2Impl.java │ ├── VerilogCellParameterImpl.java │ ├── VerilogCellListImpl.java │ ├── VerilogConcatListImpl.java │ ├── VerilogFuncDeclImpl.java │ ├── VerilogLvalueImpl.java │ ├── VerilogPrimListImpl.java │ ├── VerilogTaskDeclImpl.java │ ├── VerilogAttrAssignImpl.java │ ├── VerilogAttrListImpl.java │ ├── VerilogCaseExprListImpl.java │ ├── VerilogOptArgListImpl.java │ ├── VerilogSingleCellImpl.java │ ├── VerilogSingleParamDeclImpl.java │ ├── VerilogTaskFuncDeclImpl.java │ ├── VerilogModuleArgsImpl.java │ ├── VerilogCellPortListImpl.java │ ├── VerilogSinglePrimImpl.java │ ├── VerilogGenCaseBodyImpl.java │ ├── VerilogModuleGenBodyImpl.java │ ├── VerilogHierarchicalIdImpl.java │ ├── VerilogAlwaysEventsImpl.java │ ├── VerilogCaseItemImpl.java │ ├── VerilogGenCaseItemImpl.java │ ├── VerilogSimpleBehavioralStmtImpl.java │ ├── VerilogWireNameAndOptAssignImpl.java │ ├── VerilogAssignExprListImpl.java │ ├── VerilogModuleBodyImpl.java │ ├── VerilogModuleBodyRestImpl.java │ ├── VerilogParamDeclListImpl.java │ ├── VerilogWireNameListImpl.java │ ├── VerilogCellParameterListImpl.java │ ├── VerilogBehavioralStmtListImpl.java │ ├── VerilogDefparamDeclListImpl.java │ ├── VerilogWireTypeTokenListImpl.java │ ├── VerilogAlwaysStmtImpl.java │ ├── VerilogSingleDefparamDeclImpl.java │ ├── VerilogParamDeclImpl.java │ ├── VerilogLocalparamDeclImpl.java │ ├── VerilogWireDeclImpl.java │ ├── VerilogModuleArgImpl.java │ ├── VerilogRvalueImpl.java │ ├── VerilogCellStmtImpl.java │ ├── VerilogModuleImpl.java │ ├── VerilogGenStmtImpl.java │ └── VerilogBasicExprImpl.java │ └── VerilogBehavioralStmt.java ├── .github ├── template-cleanup │ ├── settings.gradle.kts │ ├── CHANGELOG.md │ ├── gradle.properties │ └── README.md ├── readme │ ├── draft-release.png │ ├── settings-secrets.png │ └── use-this-template.png └── workflows │ └── release.yml ├── gradle.properties ├── gradle └── wrapper │ ├── gradle-wrapper.jar │ └── gradle-wrapper.properties ├── detekt-config.yml ├── CODE_OF_CONDUCT.md └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | .gradle 2 | .idea 3 | build -------------------------------------------------------------------------------- /settings.gradle: -------------------------------------------------------------------------------- 1 | rootProject.name = 'verilogplugin' 2 | 3 | -------------------------------------------------------------------------------- /src/test/resources/testData/test3.v: -------------------------------------------------------------------------------- 1 | module a; 2 | endmodule 3 | -------------------------------------------------------------------------------- /.github/template-cleanup/settings.gradle.kts: -------------------------------------------------------------------------------- 1 | rootProject.name = "%NAME%" 2 | -------------------------------------------------------------------------------- /src/test/resources/testData/test.v: -------------------------------------------------------------------------------- 1 | // this is a test 2 | module abc; 3 | endmodule 4 | -------------------------------------------------------------------------------- /gradle.properties: -------------------------------------------------------------------------------- 1 | org.gradle.java.home=/Library/Java/JavaVirtualMachines/jdk1.8.0_251.jdk/Contents/Home -------------------------------------------------------------------------------- /src/main/resources/psi.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/max6cn/verilogplugin/HEAD/src/main/resources/psi.png -------------------------------------------------------------------------------- /src/main/resources/setting.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/max6cn/verilogplugin/HEAD/src/main/resources/setting.png -------------------------------------------------------------------------------- /.github/readme/draft-release.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/max6cn/verilogplugin/HEAD/.github/readme/draft-release.png -------------------------------------------------------------------------------- /gradle/wrapper/gradle-wrapper.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/max6cn/verilogplugin/HEAD/gradle/wrapper/gradle-wrapper.jar -------------------------------------------------------------------------------- /.github/readme/settings-secrets.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/max6cn/verilogplugin/HEAD/.github/readme/settings-secrets.png -------------------------------------------------------------------------------- /.github/readme/use-this-template.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/max6cn/verilogplugin/HEAD/.github/readme/use-this-template.png -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/icons/jar-gray.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/max6cn/verilogplugin/HEAD/src/main/java/com/verilogplugin/icons/jar-gray.png -------------------------------------------------------------------------------- /gradle/wrapper/gradle-wrapper.properties: -------------------------------------------------------------------------------- 1 | distributionBase=GRADLE_USER_HOME 2 | distributionPath=wrapper/dists 3 | distributionUrl=https\://services.gradle.org/distributions/gradle-6.7-all.zip 4 | zipStoreBase=GRADLE_USER_HOME 5 | zipStorePath=wrapper/dists 6 | -------------------------------------------------------------------------------- /detekt-config.yml: -------------------------------------------------------------------------------- 1 | # Default detekt configuration: 2 | # https://github.com/detekt/detekt/blob/master/detekt-core/src/main/resources/default-detekt-config.yml 3 | 4 | formatting: 5 | Indentation: 6 | continuationIndentSize: 8 7 | ParameterListWrapping: 8 | indentSize: 8 9 | -------------------------------------------------------------------------------- /CODE_OF_CONDUCT.md: -------------------------------------------------------------------------------- 1 | ## Code of Conduct 2 | 3 | This project and the corresponding community is governed by the [JetBrains Open Source and Community Code of Conduct](https://confluence.jetbrains.com/display/ALL/JetBrains+Open+Source+and+Community+Code+of+Conduct). Please make sure you read it. 4 | 5 | -------------------------------------------------------------------------------- /.github/template-cleanup/CHANGELOG.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | # %NAME% Changelog 4 | 5 | ## [Unreleased] 6 | ### Added 7 | - Initial scaffold created from [IntelliJ Platform Plugin Template](https://github.com/JetBrains/intellij-platform-plugin-template) 8 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCaseType.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCaseType extends PsiElement { 9 | 10 | } 11 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogOptSigned.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogOptSigned extends PsiElement { 9 | 10 | } 11 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogTopRecover.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogTopRecover extends PsiElement { 9 | 10 | } 11 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogOptionalComma.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogOptionalComma extends PsiElement { 9 | 10 | } 11 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogParamInteger.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogParamInteger extends PsiElement { 9 | 10 | } 11 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogParamSigned.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogParamSigned extends PsiElement { 9 | 10 | } 11 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogWireTypeToken.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogWireTypeToken extends PsiElement { 9 | 10 | } 11 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogWireTypeTokenListRest.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogWireTypeTokenListRest extends PsiElement { 9 | 10 | } 11 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogId.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogId extends PsiElement { 9 | 10 | @NotNull 11 | PsiElement getIdentifier(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAssert_.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAssert_ extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogSingleArg.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogSingleArg extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAlwaysEvent.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAlwaysEvent extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogArgList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogArgList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogArgList2 getArgList2(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAttr.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAttr extends PsiElement { 9 | 10 | @NotNull 11 | List getAttrOptList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogOptLabel.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogOptLabel extends PsiElement { 9 | 10 | @Nullable 11 | PsiElement getIdentifier(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogParamRange.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogParamRange extends PsiElement { 9 | 10 | @NotNull 11 | VerilogRange getRange(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogDefattr.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogDefattr extends PsiElement { 9 | 10 | @NotNull 11 | VerilogOptAttrList getOptAttrList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogRange.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogRange extends PsiElement { 9 | 10 | @Nullable 11 | VerilogNonOptRange getNonOptRange(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAssignExpr.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAssignExpr extends VerilogExpr { 9 | 10 | @NotNull 11 | List getExprList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAttrListRest.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAttrListRest extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAttrList getAttrList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogGenStmtBlock.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogGenStmtBlock extends PsiElement { 9 | 10 | @NotNull 11 | VerilogGenStmt getGenStmt(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogLvalueConcatList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogLvalueConcatList extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogNonOptRange.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogNonOptRange extends PsiElement { 9 | 10 | @NotNull 11 | List getExprList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogOptAttrList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogOptAttrList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAttrList getAttrList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogRangeOrInteger.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogRangeOrInteger extends PsiElement { 9 | 10 | @Nullable 11 | VerilogRange getRange(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAlwaysCond.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAlwaysCond extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAlwaysEvents getAlwaysEvents(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAttrOpt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAttrOpt extends PsiElement { 9 | 10 | @NotNull 11 | List getOptAttrListList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCaseSelect.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCaseSelect extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCaseExprList getCaseExprList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogOptGenElse.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogOptGenElse extends PsiElement { 9 | 10 | @Nullable 11 | VerilogGenStmtOrNull getGenStmtOrNull(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogTokPrimWrapper.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogTokPrimWrapper extends PsiElement { 9 | 10 | @Nullable 11 | PsiElement getTokPrimitive(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAssignStmt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAssignStmt extends PsiElement { 9 | 10 | @NotNull 11 | VerilogAssignExprList getAssignExprList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogGenStmtOrNull.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogGenStmtOrNull extends PsiElement { 9 | 10 | @Nullable 11 | VerilogGenStmtBlock getGenStmtBlock(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogModuleArgOptAssignment.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogModuleArgOptAssignment extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogWireType.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogWireType extends PsiElement { 9 | 10 | @NotNull 11 | VerilogWireTypeTokenList getWireTypeTokenList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogDefparamDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogDefparamDecl extends PsiElement { 9 | 10 | @NotNull 11 | VerilogDefparamDeclList getDefparamDeclList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogOptionalElse.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogOptionalElse extends PsiElement { 9 | 10 | @Nullable 11 | VerilogBehavioralStmt getBehavioralStmt(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogOptSynopsysAttr.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogOptSynopsysAttr extends PsiElement { 9 | 10 | @Nullable 11 | VerilogOptSynopsysAttr getOptSynopsysAttr(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogTaskFuncBody.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogTaskFuncBody extends PsiElement { 9 | 10 | @NotNull 11 | List getBehavioralStmtList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogBehavioralStmtOpt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogBehavioralStmtOpt extends PsiElement { 9 | 10 | @Nullable 11 | VerilogBehavioralStmt getBehavioralStmt(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCellParameterListOpt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCellParameterListOpt extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCellParameterList getCellParameterList(); 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogExpr.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogExpr extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAttr getAttr(); 12 | 13 | @NotNull 14 | List getExprList(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCellPort.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCellPort extends PsiElement { 9 | 10 | @Nullable 11 | VerilogExpr getExpr(); 12 | 13 | @Nullable 14 | PsiElement getIdentifier(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogWireName.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogWireName extends PsiElement { 9 | 10 | @NotNull 11 | VerilogRange getRange(); 12 | 13 | @NotNull 14 | PsiElement getIdentifier(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCellParameter.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCellParameter extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | @Nullable 14 | PsiElement getIdentifier(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogArgList2.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogArgList2 extends PsiElement { 9 | 10 | @Nullable 11 | VerilogArgList getArgList(); 12 | 13 | @NotNull 14 | VerilogSingleArg getSingleArg(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCaseBody.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCaseBody extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCaseBody getCaseBody(); 12 | 13 | @Nullable 14 | VerilogCaseItem getCaseItem(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCellList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCellList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCellList getCellList(); 12 | 13 | @NotNull 14 | VerilogSingleCell getSingleCell(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogConcatList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogConcatList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogConcatList getConcatList(); 12 | 13 | @NotNull 14 | VerilogExpr getExpr(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogFuncDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogFuncDecl extends PsiElement { 9 | 10 | @NotNull 11 | VerilogTaskFuncBody getTaskFuncBody(); 12 | 13 | @NotNull 14 | PsiElement getIdentifier(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogPrimList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogPrimList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogPrimList getPrimList(); 12 | 13 | @NotNull 14 | VerilogSinglePrim getSinglePrim(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogSingleParamDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogSingleParamDecl extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | @NotNull 14 | PsiElement getIdentifier(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogTaskDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogTaskDecl extends PsiElement { 9 | 10 | @NotNull 11 | VerilogTaskFuncBody getTaskFuncBody(); 12 | 13 | @NotNull 14 | PsiElement getIdentifier(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAttrAssign.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAttrAssign extends PsiElement { 9 | 10 | @Nullable 11 | VerilogExpr getExpr(); 12 | 13 | @NotNull 14 | VerilogHierarchicalId getHierarchicalId(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCaseExprList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCaseExprList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCaseExprList getCaseExprList(); 12 | 13 | @Nullable 14 | VerilogExpr getExpr(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogLvalue.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogLvalue extends PsiElement { 9 | 10 | @Nullable 11 | VerilogLvalueConcatList getLvalueConcatList(); 12 | 13 | @Nullable 14 | VerilogRvalue getRvalue(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogSingleCell.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogSingleCell extends PsiElement { 9 | 10 | @NotNull 11 | VerilogCellPortList getCellPortList(); 12 | 13 | @NotNull 14 | PsiElement getIdentifier(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogTaskFuncDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogTaskFuncDecl extends PsiElement { 9 | 10 | @Nullable 11 | VerilogFuncDecl getFuncDecl(); 12 | 13 | @Nullable 14 | VerilogTaskDecl getTaskDecl(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAttrList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAttrList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAttrAssign getAttrAssign(); 12 | 13 | @Nullable 14 | VerilogAttrListRest getAttrListRest(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogModuleArgs.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogModuleArgs extends PsiElement { 9 | 10 | @NotNull 11 | VerilogModuleArg getModuleArg(); 12 | 13 | @Nullable 14 | VerilogModuleArgs getModuleArgs(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogOptArgList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogOptArgList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogArgList getArgList(); 12 | 13 | @Nullable 14 | VerilogOptionalComma getOptionalComma(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogSimpleBehavioralStmt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogSimpleBehavioralStmt extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | @NotNull 14 | VerilogLvalue getLvalue(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCellPortList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCellPortList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCellPort getCellPort(); 12 | 13 | @Nullable 14 | VerilogCellPortList getCellPortList(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogGenCaseBody.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogGenCaseBody extends PsiElement { 9 | 10 | @Nullable 11 | VerilogGenCaseBody getGenCaseBody(); 12 | 13 | @Nullable 14 | VerilogGenCaseItem getGenCaseItem(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogGenCaseItem.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogGenCaseItem extends PsiElement { 9 | 10 | @NotNull 11 | VerilogCaseSelect getCaseSelect(); 12 | 13 | @NotNull 14 | VerilogGenStmtOrNull getGenStmtOrNull(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogModuleGenBody.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogModuleGenBody extends PsiElement { 9 | 10 | @Nullable 11 | VerilogGenStmt getGenStmt(); 12 | 13 | @Nullable 14 | VerilogModuleGenBody getModuleGenBody(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogSinglePrim.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogSinglePrim extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCellPortList getCellPortList(); 12 | 13 | @Nullable 14 | VerilogSingleCell getSingleCell(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogWireNameAndOptAssign.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogWireNameAndOptAssign extends PsiElement { 9 | 10 | @Nullable 11 | VerilogExpr getExpr(); 12 | 13 | @NotNull 14 | VerilogWireName getWireName(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAlwaysEvents.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAlwaysEvents extends PsiElement { 9 | 10 | @NotNull 11 | VerilogAlwaysEvent getAlwaysEvent(); 12 | 13 | @Nullable 14 | VerilogAlwaysEvents getAlwaysEvents(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCaseItem.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCaseItem extends PsiElement { 9 | 10 | @NotNull 11 | VerilogBehavioralStmtOpt getBehavioralStmtOpt(); 12 | 13 | @NotNull 14 | VerilogCaseSelect getCaseSelect(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogHierarchicalId.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogHierarchicalId extends PsiElement { 9 | 10 | @Nullable 11 | VerilogHierarchicalId getHierarchicalId(); 12 | 13 | @NotNull 14 | PsiElement getIdentifier(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAssignExprList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAssignExprList extends PsiElement { 9 | 10 | @NotNull 11 | VerilogAssignExpr getAssignExpr(); 12 | 13 | @Nullable 14 | VerilogAssignExprList getAssignExprList(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogModuleBody.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogModuleBody extends PsiElement { 9 | 10 | @NotNull 11 | VerilogModuleBodyRest getModuleBodyRest(); 12 | 13 | @NotNull 14 | VerilogModuleBodyStmt getModuleBodyStmt(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogParamDeclList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogParamDeclList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogParamDeclList getParamDeclList(); 12 | 13 | @NotNull 14 | VerilogSingleParamDecl getSingleParamDecl(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogModuleBodyRest.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogModuleBodyRest extends PsiElement { 9 | 10 | @Nullable 11 | VerilogModuleBodyRest getModuleBodyRest(); 12 | 13 | @Nullable 14 | VerilogModuleBodyStmt getModuleBodyStmt(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogWireNameList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogWireNameList extends PsiElement { 9 | 10 | @NotNull 11 | VerilogWireNameAndOptAssign getWireNameAndOptAssign(); 12 | 13 | @Nullable 14 | VerilogWireNameList getWireNameList(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCellParameterList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCellParameterList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCellParameter getCellParameter(); 12 | 13 | @Nullable 14 | VerilogCellParameterList getCellParameterList(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogBehavioralStmtList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogBehavioralStmtList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogBehavioralStmt getBehavioralStmt(); 12 | 13 | @Nullable 14 | VerilogBehavioralStmtList getBehavioralStmtList(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogDefparamDeclList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogDefparamDeclList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogDefparamDeclList getDefparamDeclList(); 12 | 13 | @NotNull 14 | VerilogSingleDefparamDecl getSingleDefparamDecl(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogWireTypeTokenList.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogWireTypeTokenList extends PsiElement { 9 | 10 | @Nullable 11 | VerilogWireTypeToken getWireTypeToken(); 12 | 13 | @Nullable 14 | VerilogWireTypeTokenListRest getWireTypeTokenListRest(); 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogAlwaysStmt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogAlwaysStmt extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAlwaysCond getAlwaysCond(); 12 | 13 | @Nullable 14 | VerilogAttrOpt getAttrOpt(); 15 | 16 | @NotNull 17 | VerilogBehavioralStmt getBehavioralStmt(); 18 | 19 | } 20 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogSingleDefparamDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogSingleDefparamDecl extends PsiElement { 9 | 10 | @NotNull 11 | VerilogExpr getExpr(); 12 | 13 | @NotNull 14 | VerilogHierarchicalId getHierarchicalId(); 15 | 16 | @NotNull 17 | VerilogRange getRange(); 18 | 19 | } 20 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogParamDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogParamDecl extends PsiElement { 9 | 10 | @NotNull 11 | VerilogParamDeclList getParamDeclList(); 12 | 13 | @NotNull 14 | VerilogParamInteger getParamInteger(); 15 | 16 | @NotNull 17 | VerilogParamRange getParamRange(); 18 | 19 | @NotNull 20 | VerilogParamSigned getParamSigned(); 21 | 22 | } 23 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogLocalparamDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogLocalparamDecl extends PsiElement { 9 | 10 | @NotNull 11 | VerilogParamDeclList getParamDeclList(); 12 | 13 | @NotNull 14 | VerilogParamInteger getParamInteger(); 15 | 16 | @NotNull 17 | VerilogParamRange getParamRange(); 18 | 19 | @NotNull 20 | VerilogParamSigned getParamSigned(); 21 | 22 | } 23 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogWireDecl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogWireDecl extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAttrOpt getAttrOpt(); 12 | 13 | @Nullable 14 | VerilogRange getRange(); 15 | 16 | @Nullable 17 | VerilogWireNameList getWireNameList(); 18 | 19 | @Nullable 20 | VerilogWireType getWireType(); 21 | 22 | @Nullable 23 | PsiElement getIdentifier(); 24 | 25 | } 26 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogRvalue.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogRvalue extends PsiElement { 9 | 10 | @Nullable 11 | VerilogExpr getExpr(); 12 | 13 | @NotNull 14 | VerilogHierarchicalId getHierarchicalId(); 15 | 16 | @NotNull 17 | List getNonOptRangeList(); 18 | 19 | @Nullable 20 | VerilogRange getRange(); 21 | 22 | @Nullable 23 | VerilogRvalue getRvalue(); 24 | 25 | } 26 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogModuleArg.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogModuleArg extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAttr getAttr(); 12 | 13 | @Nullable 14 | VerilogModuleArgOptAssignment getModuleArgOptAssignment(); 15 | 16 | @Nullable 17 | VerilogRange getRange(); 18 | 19 | @Nullable 20 | VerilogWireType getWireType(); 21 | 22 | @NotNull 23 | PsiElement getIdentifier(); 24 | 25 | } 26 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogCellStmt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogCellStmt extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAttrOpt getAttrOpt(); 12 | 13 | @Nullable 14 | VerilogCellList getCellList(); 15 | 16 | @Nullable 17 | VerilogCellParameterListOpt getCellParameterListOpt(); 18 | 19 | @Nullable 20 | VerilogPrimList getPrimList(); 21 | 22 | @Nullable 23 | VerilogTokPrimWrapper getTokPrimWrapper(); 24 | 25 | @Nullable 26 | PsiElement getIdentifier(); 27 | 28 | } 29 | -------------------------------------------------------------------------------- /.github/template-cleanup/gradle.properties: -------------------------------------------------------------------------------- 1 | # IntelliJ Platform Artifacts Repositories 2 | # -> https://www.jetbrains.org/intellij/sdk/docs/reference_guide/intellij_artifacts.html 3 | 4 | pluginGroup = %GROUP% 5 | pluginName_ = %NAME% 6 | pluginVersion = 0.0.1 7 | pluginSinceBuild = 193 8 | pluginUntilBuild = 202.* 9 | 10 | platformType = IC 11 | platformVersion = 2019.3 12 | platformDownloadSources = true 13 | # Plugin Dependencies -> https://www.jetbrains.org/intellij/sdk/docs/basics/plugin_structure/plugin_dependencies.html 14 | # Example: platformPlugins = com.intellij.java,com.jetbrains.php:203.4449.22 15 | platformPlugins = 16 | 17 | # Opt-out flag for bundling Kotlin standard library. 18 | # See https://kotlinlang.org/docs/reference/using-gradle.html#dependency-on-the-standard-library for details. 19 | kotlin.stdlib.default.dependency = false 20 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogModule.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogModule extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAttrOpt getAttrOpt(); 12 | 13 | @NotNull 14 | List getModuleArgsList(); 15 | 16 | @Nullable 17 | VerilogModuleBody getModuleBody(); 18 | 19 | @NotNull 20 | List getParamIntegerList(); 21 | 22 | @NotNull 23 | List getParamRangeList(); 24 | 25 | @NotNull 26 | List getParamSignedList(); 27 | 28 | @NotNull 29 | List getSingleParamDeclList(); 30 | 31 | @Nullable 32 | PsiElement getIdentifier(); 33 | 34 | } 35 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/psi/VerilogNamedElement.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core.psi; 17 | 18 | import com.intellij.psi.PsiNameIdentifierOwner; 19 | 20 | public interface VerilogNamedElement extends PsiNameIdentifierOwner { 21 | 22 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogGenStmt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogGenStmt extends PsiElement { 9 | 10 | @Nullable 11 | VerilogCaseType getCaseType(); 12 | 13 | @Nullable 14 | VerilogExpr getExpr(); 15 | 16 | @Nullable 17 | VerilogGenCaseBody getGenCaseBody(); 18 | 19 | @Nullable 20 | VerilogGenStmtBlock getGenStmtBlock(); 21 | 22 | @Nullable 23 | VerilogModuleBodyStmt getModuleBodyStmt(); 24 | 25 | @Nullable 26 | VerilogModuleGenBody getModuleGenBody(); 27 | 28 | @Nullable 29 | VerilogOptGenElse getOptGenElse(); 30 | 31 | @NotNull 32 | List getOptLabelList(); 33 | 34 | @NotNull 35 | List getSimpleBehavioralStmtList(); 36 | 37 | } 38 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogBasicExpr.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogBasicExpr extends VerilogExpr { 9 | 10 | @Nullable 11 | VerilogArgList getArgList(); 12 | 13 | @NotNull 14 | List getAttrList(); 15 | 16 | @Nullable 17 | VerilogCaseItem getCaseItem(); 18 | 19 | @Nullable 20 | VerilogConcatList getConcatList(); 21 | 22 | @Nullable 23 | VerilogExpr getExpr(); 24 | 25 | @Nullable 26 | VerilogGenCaseItem getGenCaseItem(); 27 | 28 | @Nullable 29 | VerilogHierarchicalId getHierarchicalId(); 30 | 31 | @Nullable 32 | VerilogOptSynopsysAttr getOptSynopsysAttr(); 33 | 34 | @Nullable 35 | VerilogOptionalComma getOptionalComma(); 36 | 37 | @Nullable 38 | VerilogRvalue getRvalue(); 39 | 40 | } 41 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/VerilogLanguage.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core; 17 | 18 | import com.intellij.lang.Language; 19 | 20 | public class VerilogLanguage extends Language { 21 | public static final VerilogLanguage INSTANCE = new VerilogLanguage(); 22 | 23 | private VerilogLanguage() { 24 | super("Verilog"); 25 | } 26 | } -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/lexer/VerilogLexerAdapter.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core.lexer; 17 | 18 | import com.intellij.lexer.FlexAdapter; 19 | 20 | import java.io.Reader; 21 | 22 | public class VerilogLexerAdapter extends FlexAdapter { 23 | public VerilogLexerAdapter() { 24 | super(new _VerilogLexer((Reader) null)); 25 | } 26 | 27 | } 28 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/VerilogAdapter.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core; 17 | 18 | import com.intellij.lexer.FlexAdapter; 19 | import com.verilogplugin.lang.core.lexer._VerilogLexer; 20 | 21 | import java.io.Reader; 22 | 23 | public class VerilogAdapter extends FlexAdapter { 24 | public VerilogAdapter() { 25 | super(new _VerilogLexer((Reader) null)); 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogModuleBodyStmt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogModuleBodyStmt extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAlwaysStmt getAlwaysStmt(); 12 | 13 | @Nullable 14 | VerilogAssert_ getAssert_(); 15 | 16 | @Nullable 17 | VerilogAssignStmt getAssignStmt(); 18 | 19 | @Nullable 20 | VerilogCellStmt getCellStmt(); 21 | 22 | @Nullable 23 | VerilogDefattr getDefattr(); 24 | 25 | @Nullable 26 | VerilogDefparamDecl getDefparamDecl(); 27 | 28 | @Nullable 29 | VerilogLocalparamDecl getLocalparamDecl(); 30 | 31 | @Nullable 32 | VerilogModuleGenBody getModuleGenBody(); 33 | 34 | @Nullable 35 | VerilogParamDecl getParamDecl(); 36 | 37 | @Nullable 38 | VerilogTaskFuncDecl getTaskFuncDecl(); 39 | 40 | @Nullable 41 | VerilogWireDecl getWireDecl(); 42 | 43 | } 44 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCaseTypeImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCaseTypeImpl extends ASTWrapperPsiElement implements VerilogCaseType { 15 | 16 | public VerilogCaseTypeImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCaseType(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogOptSignedImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogOptSignedImpl extends ASTWrapperPsiElement implements VerilogOptSigned { 15 | 16 | public VerilogOptSignedImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitOptSigned(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogTopRecoverImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogTopRecoverImpl extends ASTWrapperPsiElement implements VerilogTopRecover { 15 | 16 | public VerilogTopRecoverImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitTopRecover(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/VerilogIcons.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core; 17 | 18 | import com.intellij.openapi.util.IconLoader; 19 | 20 | import javax.swing.*; 21 | 22 | public class VerilogIcons { 23 | // private static Icon load(String path) { 24 | // return IconLoader.getIcon(path, VerilogIcons.class); 25 | // } 26 | 27 | public static final Icon FILE = IconLoader.getIcon("/com/verilogplugin/icons/jar-gray.png"); 28 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogParamSignedImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogParamSignedImpl extends ASTWrapperPsiElement implements VerilogParamSigned { 15 | 16 | public VerilogParamSignedImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitParamSigned(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/codestyle/VerilogCodeStyleSettings.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.codestyle; 17 | 18 | import com.intellij.psi.codeStyle.CodeStyleSettings; 19 | import com.intellij.psi.codeStyle.CustomCodeStyleSettings; 20 | 21 | public class VerilogCodeStyleSettings extends CustomCodeStyleSettings { 22 | public VerilogCodeStyleSettings(CodeStyleSettings settings) { 23 | super("VerilogCodeStyleSettings", settings); 24 | } 25 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogParamIntegerImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogParamIntegerImpl extends ASTWrapperPsiElement implements VerilogParamInteger { 15 | 16 | public VerilogParamIntegerImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitParamInteger(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogOptionalCommaImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogOptionalCommaImpl extends ASTWrapperPsiElement implements VerilogOptionalComma { 15 | 16 | public VerilogOptionalCommaImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitOptionalComma(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogWireTypeTokenImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogWireTypeTokenImpl extends ASTWrapperPsiElement implements VerilogWireTypeToken { 15 | 16 | public VerilogWireTypeTokenImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitWireTypeToken(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogWireTypeTokenListRestImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogWireTypeTokenListRestImpl extends ASTWrapperPsiElement implements VerilogWireTypeTokenListRest { 15 | 16 | public VerilogWireTypeTokenListRestImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitWireTypeTokenListRest(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/psi/VerilogElementType.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core.psi; 17 | 18 | import com.intellij.psi.tree.IElementType; 19 | import com.verilogplugin.lang.core.VerilogLanguage; 20 | import org.jetbrains.annotations.NonNls; 21 | import org.jetbrains.annotations.NotNull; 22 | 23 | public class VerilogElementType extends IElementType { 24 | public VerilogElementType(@NotNull @NonNls String debugName) { 25 | super(debugName, VerilogLanguage.INSTANCE); 26 | } 27 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogIdImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogIdImpl extends ASTWrapperPsiElement implements VerilogId { 15 | 16 | public VerilogIdImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitId(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public PsiElement getIdentifier() { 32 | return findNotNullChildByType(IDENTIFIER); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAssignExprImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.verilogplugin.lang.core.psi.*; 12 | 13 | public class VerilogAssignExprImpl extends VerilogExprImpl implements VerilogAssignExpr { 14 | 15 | public VerilogAssignExprImpl(@NotNull ASTNode node) { 16 | super(node); 17 | } 18 | 19 | public void accept(@NotNull VerilogVisitor visitor) { 20 | visitor.visitAssignExpr(this); 21 | } 22 | 23 | public void accept(@NotNull PsiElementVisitor visitor) { 24 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 25 | else super.accept(visitor); 26 | } 27 | 28 | @Override 29 | @NotNull 30 | public List getExprList() { 31 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogExpr.class); 32 | } 33 | 34 | } 35 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/VerilogFileTypeFactory.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core; 17 | 18 | import com.intellij.openapi.fileTypes.FileTypeConsumer; 19 | import com.intellij.openapi.fileTypes.FileTypeFactory; 20 | import org.jetbrains.annotations.NotNull; 21 | 22 | public class VerilogFileTypeFactory extends FileTypeFactory { 23 | @Override 24 | public void createFileTypes(@NotNull FileTypeConsumer fileTypeConsumer) { 25 | fileTypeConsumer.consume(VerilogFileType.INSTANCE, VerilogFileType.INSTANCE.getDefaultExtension()); 26 | } 27 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAssert_Impl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAssert_Impl extends ASTWrapperPsiElement implements VerilogAssert_ { 15 | 16 | public VerilogAssert_Impl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAssert_(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogOptLabelImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogOptLabelImpl extends ASTWrapperPsiElement implements VerilogOptLabel { 15 | 16 | public VerilogOptLabelImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitOptLabel(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public PsiElement getIdentifier() { 32 | return findChildByType(IDENTIFIER); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogRangeImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogRangeImpl extends ASTWrapperPsiElement implements VerilogRange { 15 | 16 | public VerilogRangeImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitRange(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogNonOptRange getNonOptRange() { 32 | return findChildByClass(VerilogNonOptRange.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogArgListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogArgListImpl extends ASTWrapperPsiElement implements VerilogArgList { 15 | 16 | public VerilogArgListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitArgList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogArgList2 getArgList2() { 32 | return findChildByClass(VerilogArgList2.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogSingleArgImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogSingleArgImpl extends ASTWrapperPsiElement implements VerilogSingleArg { 15 | 16 | public VerilogSingleArgImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitSingleArg(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAlwaysEventImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAlwaysEventImpl extends ASTWrapperPsiElement implements VerilogAlwaysEvent { 15 | 16 | public VerilogAlwaysEventImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAlwaysEvent(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogParamRangeImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogParamRangeImpl extends ASTWrapperPsiElement implements VerilogParamRange { 15 | 16 | public VerilogParamRangeImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitParamRange(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogRange getRange() { 32 | return findNotNullChildByClass(VerilogRange.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAttrImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAttrImpl extends ASTWrapperPsiElement implements VerilogAttr { 15 | 16 | public VerilogAttrImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAttr(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public List getAttrOptList() { 32 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogAttrOpt.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogDefattrImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogDefattrImpl extends ASTWrapperPsiElement implements VerilogDefattr { 15 | 16 | public VerilogDefattrImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitDefattr(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogOptAttrList getOptAttrList() { 32 | return findNotNullChildByClass(VerilogOptAttrList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogOptAttrListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogOptAttrListImpl extends ASTWrapperPsiElement implements VerilogOptAttrList { 15 | 16 | public VerilogOptAttrListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitOptAttrList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAttrList getAttrList() { 32 | return findChildByClass(VerilogAttrList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAlwaysCondImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAlwaysCondImpl extends ASTWrapperPsiElement implements VerilogAlwaysCond { 15 | 16 | public VerilogAlwaysCondImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAlwaysCond(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAlwaysEvents getAlwaysEvents() { 32 | return findChildByClass(VerilogAlwaysEvents.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAttrListRestImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAttrListRestImpl extends ASTWrapperPsiElement implements VerilogAttrListRest { 15 | 16 | public VerilogAttrListRestImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAttrListRest(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAttrList getAttrList() { 32 | return findChildByClass(VerilogAttrList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCaseSelectImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCaseSelectImpl extends ASTWrapperPsiElement implements VerilogCaseSelect { 15 | 16 | public VerilogCaseSelectImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCaseSelect(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCaseExprList getCaseExprList() { 32 | return findChildByClass(VerilogCaseExprList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogGenStmtBlockImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogGenStmtBlockImpl extends ASTWrapperPsiElement implements VerilogGenStmtBlock { 15 | 16 | public VerilogGenStmtBlockImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitGenStmtBlock(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogGenStmt getGenStmt() { 32 | return findNotNullChildByClass(VerilogGenStmt.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogRangeOrIntegerImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogRangeOrIntegerImpl extends ASTWrapperPsiElement implements VerilogRangeOrInteger { 15 | 16 | public VerilogRangeOrIntegerImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitRangeOrInteger(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogRange getRange() { 32 | return findChildByClass(VerilogRange.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogTokPrimWrapperImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogTokPrimWrapperImpl extends ASTWrapperPsiElement implements VerilogTokPrimWrapper { 15 | 16 | public VerilogTokPrimWrapperImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitTokPrimWrapper(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public PsiElement getTokPrimitive() { 32 | return findChildByType(TOK_PRIMITIVE); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogOptGenElseImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogOptGenElseImpl extends ASTWrapperPsiElement implements VerilogOptGenElse { 15 | 16 | public VerilogOptGenElseImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitOptGenElse(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogGenStmtOrNull getGenStmtOrNull() { 32 | return findChildByClass(VerilogGenStmtOrNull.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAssignStmtImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAssignStmtImpl extends ASTWrapperPsiElement implements VerilogAssignStmt { 15 | 16 | public VerilogAssignStmtImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAssignStmt(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogAssignExprList getAssignExprList() { 32 | return findNotNullChildByClass(VerilogAssignExprList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogLvalueConcatListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogLvalueConcatListImpl extends ASTWrapperPsiElement implements VerilogLvalueConcatList { 15 | 16 | public VerilogLvalueConcatListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitLvalueConcatList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogWireTypeImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogWireTypeImpl extends ASTWrapperPsiElement implements VerilogWireType { 15 | 16 | public VerilogWireTypeImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitWireType(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogWireTypeTokenList getWireTypeTokenList() { 32 | return findNotNullChildByClass(VerilogWireTypeTokenList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAttrOptImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAttrOptImpl extends ASTWrapperPsiElement implements VerilogAttrOpt { 15 | 16 | public VerilogAttrOptImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAttrOpt(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public List getOptAttrListList() { 32 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogOptAttrList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogGenStmtOrNullImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogGenStmtOrNullImpl extends ASTWrapperPsiElement implements VerilogGenStmtOrNull { 15 | 16 | public VerilogGenStmtOrNullImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitGenStmtOrNull(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogGenStmtBlock getGenStmtBlock() { 32 | return findChildByClass(VerilogGenStmtBlock.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogNonOptRangeImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogNonOptRangeImpl extends ASTWrapperPsiElement implements VerilogNonOptRange { 15 | 16 | public VerilogNonOptRangeImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitNonOptRange(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public List getExprList() { 32 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogExpr.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogOptionalElseImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogOptionalElseImpl extends ASTWrapperPsiElement implements VerilogOptionalElse { 15 | 16 | public VerilogOptionalElseImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitOptionalElse(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogBehavioralStmt getBehavioralStmt() { 32 | return findChildByClass(VerilogBehavioralStmt.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/psi/VerilogTokenType.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core.psi; 17 | 18 | import com.intellij.psi.tree.IElementType; 19 | import com.verilogplugin.lang.core.VerilogLanguage; 20 | import org.jetbrains.annotations.NonNls; 21 | import org.jetbrains.annotations.NotNull; 22 | 23 | public class VerilogTokenType extends IElementType { 24 | public VerilogTokenType(@NotNull @NonNls String debugName) { 25 | super(debugName, VerilogLanguage.INSTANCE); 26 | } 27 | 28 | @Override 29 | public String toString() { 30 | return "VerilogTokenType." + super.toString(); 31 | } 32 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogDefparamDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogDefparamDeclImpl extends ASTWrapperPsiElement implements VerilogDefparamDecl { 15 | 16 | public VerilogDefparamDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitDefparamDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogDefparamDeclList getDefparamDeclList() { 32 | return findNotNullChildByClass(VerilogDefparamDeclList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogOptSynopsysAttrImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogOptSynopsysAttrImpl extends ASTWrapperPsiElement implements VerilogOptSynopsysAttr { 15 | 16 | public VerilogOptSynopsysAttrImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitOptSynopsysAttr(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogOptSynopsysAttr getOptSynopsysAttr() { 32 | return findChildByClass(VerilogOptSynopsysAttr.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogBehavioralStmtOptImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogBehavioralStmtOptImpl extends ASTWrapperPsiElement implements VerilogBehavioralStmtOpt { 15 | 16 | public VerilogBehavioralStmtOptImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitBehavioralStmtOpt(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogBehavioralStmt getBehavioralStmt() { 32 | return findChildByClass(VerilogBehavioralStmt.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogModuleArgOptAssignmentImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogModuleArgOptAssignmentImpl extends ASTWrapperPsiElement implements VerilogModuleArgOptAssignment { 15 | 16 | public VerilogModuleArgOptAssignmentImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitModuleArgOptAssignment(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogTaskFuncBodyImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogTaskFuncBodyImpl extends ASTWrapperPsiElement implements VerilogTaskFuncBody { 15 | 16 | public VerilogTaskFuncBodyImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitTaskFuncBody(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public List getBehavioralStmtList() { 32 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogBehavioralStmt.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/VerilogBehavioralStmt.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.psi.PsiElement; 7 | 8 | public interface VerilogBehavioralStmt extends PsiElement { 9 | 10 | @Nullable 11 | VerilogAssert_ getAssert_(); 12 | 13 | @Nullable 14 | VerilogAttr getAttr(); 15 | 16 | @Nullable 17 | VerilogBehavioralStmt getBehavioralStmt(); 18 | 19 | @Nullable 20 | VerilogBehavioralStmtList getBehavioralStmtList(); 21 | 22 | @Nullable 23 | VerilogCaseBody getCaseBody(); 24 | 25 | @Nullable 26 | VerilogCaseType getCaseType(); 27 | 28 | @Nullable 29 | VerilogDefattr getDefattr(); 30 | 31 | @Nullable 32 | VerilogExpr getExpr(); 33 | 34 | @Nullable 35 | VerilogHierarchicalId getHierarchicalId(); 36 | 37 | @Nullable 38 | VerilogOptArgList getOptArgList(); 39 | 40 | @NotNull 41 | List getOptLabelList(); 42 | 43 | @Nullable 44 | VerilogOptSynopsysAttr getOptSynopsysAttr(); 45 | 46 | @Nullable 47 | VerilogOptionalElse getOptionalElse(); 48 | 49 | @Nullable 50 | VerilogSimpleBehavioralStmt getSimpleBehavioralStmt(); 51 | 52 | @Nullable 53 | VerilogWireDecl getWireDecl(); 54 | 55 | } 56 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCellParameterListOptImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCellParameterListOptImpl extends ASTWrapperPsiElement implements VerilogCellParameterListOpt { 15 | 16 | public VerilogCellParameterListOptImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCellParameterListOpt(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCellParameterList getCellParameterList() { 32 | return findChildByClass(VerilogCellParameterList.class); 33 | } 34 | 35 | } 36 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/highlight/VerilogSyntaxHighlighterFactory.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.highlight; 17 | 18 | import com.intellij.openapi.fileTypes.SyntaxHighlighter; 19 | import com.intellij.openapi.fileTypes.SyntaxHighlighterFactory; 20 | import com.intellij.openapi.project.Project; 21 | import com.intellij.openapi.vfs.VirtualFile; 22 | import org.jetbrains.annotations.NotNull; 23 | 24 | public class VerilogSyntaxHighlighterFactory extends SyntaxHighlighterFactory { 25 | @NotNull 26 | @Override 27 | public SyntaxHighlighter getSyntaxHighlighter(Project project, VirtualFile virtualFile) { 28 | return new VerilogSyntaxHighlighter(); 29 | } 30 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCellPortImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCellPortImpl extends ASTWrapperPsiElement implements VerilogCellPort { 15 | 16 | public VerilogCellPortImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCellPort(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogExpr getExpr() { 32 | return findChildByClass(VerilogExpr.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public PsiElement getIdentifier() { 38 | return findChildByType(IDENTIFIER); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogExprImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogExprImpl extends ASTWrapperPsiElement implements VerilogExpr { 15 | 16 | public VerilogExprImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitExpr(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAttr getAttr() { 32 | return findChildByClass(VerilogAttr.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public List getExprList() { 38 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogExpr.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogWireNameImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogWireNameImpl extends ASTWrapperPsiElement implements VerilogWireName { 15 | 16 | public VerilogWireNameImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitWireName(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogRange getRange() { 32 | return findNotNullChildByClass(VerilogRange.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public PsiElement getIdentifier() { 38 | return findNotNullChildByType(IDENTIFIER); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCaseBodyImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCaseBodyImpl extends ASTWrapperPsiElement implements VerilogCaseBody { 15 | 16 | public VerilogCaseBodyImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCaseBody(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCaseBody getCaseBody() { 32 | return findChildByClass(VerilogCaseBody.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogCaseItem getCaseItem() { 38 | return findChildByClass(VerilogCaseItem.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogArgList2Impl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogArgList2Impl extends ASTWrapperPsiElement implements VerilogArgList2 { 15 | 16 | public VerilogArgList2Impl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitArgList2(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogArgList getArgList() { 32 | return findChildByClass(VerilogArgList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogSingleArg getSingleArg() { 38 | return findNotNullChildByClass(VerilogSingleArg.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCellParameterImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCellParameterImpl extends ASTWrapperPsiElement implements VerilogCellParameter { 15 | 16 | public VerilogCellParameterImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCellParameter(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public PsiElement getIdentifier() { 38 | return findChildByType(IDENTIFIER); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCellListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCellListImpl extends ASTWrapperPsiElement implements VerilogCellList { 15 | 16 | public VerilogCellListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCellList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCellList getCellList() { 32 | return findChildByClass(VerilogCellList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogSingleCell getSingleCell() { 38 | return findNotNullChildByClass(VerilogSingleCell.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogConcatListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogConcatListImpl extends ASTWrapperPsiElement implements VerilogConcatList { 15 | 16 | public VerilogConcatListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitConcatList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogConcatList getConcatList() { 32 | return findChildByClass(VerilogConcatList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogExpr getExpr() { 38 | return findNotNullChildByClass(VerilogExpr.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogFuncDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogFuncDeclImpl extends ASTWrapperPsiElement implements VerilogFuncDecl { 15 | 16 | public VerilogFuncDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitFuncDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogTaskFuncBody getTaskFuncBody() { 32 | return findNotNullChildByClass(VerilogTaskFuncBody.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public PsiElement getIdentifier() { 38 | return findNotNullChildByType(IDENTIFIER); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogLvalueImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogLvalueImpl extends ASTWrapperPsiElement implements VerilogLvalue { 15 | 16 | public VerilogLvalueImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitLvalue(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogLvalueConcatList getLvalueConcatList() { 32 | return findChildByClass(VerilogLvalueConcatList.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogRvalue getRvalue() { 38 | return findChildByClass(VerilogRvalue.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogPrimListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogPrimListImpl extends ASTWrapperPsiElement implements VerilogPrimList { 15 | 16 | public VerilogPrimListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitPrimList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogPrimList getPrimList() { 32 | return findChildByClass(VerilogPrimList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogSinglePrim getSinglePrim() { 38 | return findNotNullChildByClass(VerilogSinglePrim.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogTaskDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogTaskDeclImpl extends ASTWrapperPsiElement implements VerilogTaskDecl { 15 | 16 | public VerilogTaskDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitTaskDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogTaskFuncBody getTaskFuncBody() { 32 | return findNotNullChildByClass(VerilogTaskFuncBody.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public PsiElement getIdentifier() { 38 | return findNotNullChildByType(IDENTIFIER); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAttrAssignImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAttrAssignImpl extends ASTWrapperPsiElement implements VerilogAttrAssign { 15 | 16 | public VerilogAttrAssignImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAttrAssign(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogExpr getExpr() { 32 | return findChildByClass(VerilogExpr.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogHierarchicalId getHierarchicalId() { 38 | return findNotNullChildByClass(VerilogHierarchicalId.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAttrListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAttrListImpl extends ASTWrapperPsiElement implements VerilogAttrList { 15 | 16 | public VerilogAttrListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAttrList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAttrAssign getAttrAssign() { 32 | return findChildByClass(VerilogAttrAssign.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogAttrListRest getAttrListRest() { 38 | return findChildByClass(VerilogAttrListRest.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCaseExprListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCaseExprListImpl extends ASTWrapperPsiElement implements VerilogCaseExprList { 15 | 16 | public VerilogCaseExprListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCaseExprList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCaseExprList getCaseExprList() { 32 | return findChildByClass(VerilogCaseExprList.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogExpr getExpr() { 38 | return findChildByClass(VerilogExpr.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogOptArgListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogOptArgListImpl extends ASTWrapperPsiElement implements VerilogOptArgList { 15 | 16 | public VerilogOptArgListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitOptArgList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogArgList getArgList() { 32 | return findChildByClass(VerilogArgList.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogOptionalComma getOptionalComma() { 38 | return findChildByClass(VerilogOptionalComma.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogSingleCellImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogSingleCellImpl extends ASTWrapperPsiElement implements VerilogSingleCell { 15 | 16 | public VerilogSingleCellImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitSingleCell(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogCellPortList getCellPortList() { 32 | return findNotNullChildByClass(VerilogCellPortList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public PsiElement getIdentifier() { 38 | return findNotNullChildByType(IDENTIFIER); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogSingleParamDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogSingleParamDeclImpl extends ASTWrapperPsiElement implements VerilogSingleParamDecl { 15 | 16 | public VerilogSingleParamDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitSingleParamDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public PsiElement getIdentifier() { 38 | return findNotNullChildByType(IDENTIFIER); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogTaskFuncDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogTaskFuncDeclImpl extends ASTWrapperPsiElement implements VerilogTaskFuncDecl { 15 | 16 | public VerilogTaskFuncDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitTaskFuncDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogFuncDecl getFuncDecl() { 32 | return findChildByClass(VerilogFuncDecl.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogTaskDecl getTaskDecl() { 38 | return findChildByClass(VerilogTaskDecl.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogModuleArgsImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogModuleArgsImpl extends ASTWrapperPsiElement implements VerilogModuleArgs { 15 | 16 | public VerilogModuleArgsImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitModuleArgs(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogModuleArg getModuleArg() { 32 | return findNotNullChildByClass(VerilogModuleArg.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogModuleArgs getModuleArgs() { 38 | return findChildByClass(VerilogModuleArgs.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCellPortListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCellPortListImpl extends ASTWrapperPsiElement implements VerilogCellPortList { 15 | 16 | public VerilogCellPortListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCellPortList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCellPort getCellPort() { 32 | return findChildByClass(VerilogCellPort.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogCellPortList getCellPortList() { 38 | return findChildByClass(VerilogCellPortList.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogSinglePrimImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogSinglePrimImpl extends ASTWrapperPsiElement implements VerilogSinglePrim { 15 | 16 | public VerilogSinglePrimImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitSinglePrim(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCellPortList getCellPortList() { 32 | return findChildByClass(VerilogCellPortList.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogSingleCell getSingleCell() { 38 | return findChildByClass(VerilogSingleCell.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogGenCaseBodyImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogGenCaseBodyImpl extends ASTWrapperPsiElement implements VerilogGenCaseBody { 15 | 16 | public VerilogGenCaseBodyImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitGenCaseBody(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogGenCaseBody getGenCaseBody() { 32 | return findChildByClass(VerilogGenCaseBody.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogGenCaseItem getGenCaseItem() { 38 | return findChildByClass(VerilogGenCaseItem.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogModuleGenBodyImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogModuleGenBodyImpl extends ASTWrapperPsiElement implements VerilogModuleGenBody { 15 | 16 | public VerilogModuleGenBodyImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitModuleGenBody(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogGenStmt getGenStmt() { 32 | return findChildByClass(VerilogGenStmt.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogModuleGenBody getModuleGenBody() { 38 | return findChildByClass(VerilogModuleGenBody.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## Notice 2 | 3 | Due to a FS crash most progress has been lost, this project has been paused until further notice 4 | 5 | ### Verilogplugin 6 | 7 | Verilog Plugin for Intellij IDEA 8 | 9 | #### Status 10 | * working on lexer and basic syntax highlighter 11 | * parser 12 | 13 | ![](https://raw.githubusercontent.com/max6cn/verilogplugin/master/resources/setting.png) 14 | ![](https://raw.githubusercontent.com/max6cn/verilogplugin/master/resources/psi.png) 15 | #### Features(Planed) 16 | 17 | * Lexer 18 | * Syntax Highlighting 19 | * Parser 20 | * Anotator 21 | * External Tool 22 | * Color settings 23 | * Refrences and resolve 24 | * Code completion 25 | Reference completion 26 | contributor-based completion 27 | * Find Usages 28 | * Rename Refactoring 29 | * Safe Delete Refactoring 30 | * Code Formatter 31 | * Code Style Setting 32 | * Rearranger 33 | * Code Inspections and Intentions 34 | * Structure View 35 | * Surround With 36 | * Goto and Goto Symbol 37 | * Indexing 38 | * Stub Trees 39 | * Documentation 40 | * Minor Features 41 | code folding 42 | Coment Code 43 | Join Lines 44 | Smart Enter 45 | Naming suggestions 46 | Sematic highlight usage 47 | View |Parameter Info 48 | To Do View 49 | View |Conext info 50 | Spellchecking 51 | 52 | #### 3rd Party Tool Support 53 | * Synthesis Tools Support(include FPGA) 54 | * Simulation tools Support 55 | * Linter 56 | * Waveform Viewer(?) 57 | * Blockdiagram viewer(?) 58 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogHierarchicalIdImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogHierarchicalIdImpl extends ASTWrapperPsiElement implements VerilogHierarchicalId { 15 | 16 | public VerilogHierarchicalIdImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitHierarchicalId(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogHierarchicalId getHierarchicalId() { 32 | return findChildByClass(VerilogHierarchicalId.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public PsiElement getIdentifier() { 38 | return findNotNullChildByType(IDENTIFIER); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAlwaysEventsImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAlwaysEventsImpl extends ASTWrapperPsiElement implements VerilogAlwaysEvents { 15 | 16 | public VerilogAlwaysEventsImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAlwaysEvents(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogAlwaysEvent getAlwaysEvent() { 32 | return findNotNullChildByClass(VerilogAlwaysEvent.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogAlwaysEvents getAlwaysEvents() { 38 | return findChildByClass(VerilogAlwaysEvents.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCaseItemImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCaseItemImpl extends ASTWrapperPsiElement implements VerilogCaseItem { 15 | 16 | public VerilogCaseItemImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCaseItem(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogBehavioralStmtOpt getBehavioralStmtOpt() { 32 | return findNotNullChildByClass(VerilogBehavioralStmtOpt.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogCaseSelect getCaseSelect() { 38 | return findNotNullChildByClass(VerilogCaseSelect.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogGenCaseItemImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogGenCaseItemImpl extends ASTWrapperPsiElement implements VerilogGenCaseItem { 15 | 16 | public VerilogGenCaseItemImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitGenCaseItem(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogCaseSelect getCaseSelect() { 32 | return findNotNullChildByClass(VerilogCaseSelect.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogGenStmtOrNull getGenStmtOrNull() { 38 | return findNotNullChildByClass(VerilogGenStmtOrNull.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogSimpleBehavioralStmtImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogSimpleBehavioralStmtImpl extends ASTWrapperPsiElement implements VerilogSimpleBehavioralStmt { 15 | 16 | public VerilogSimpleBehavioralStmtImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitSimpleBehavioralStmt(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogLvalue getLvalue() { 38 | return findNotNullChildByClass(VerilogLvalue.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogWireNameAndOptAssignImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogWireNameAndOptAssignImpl extends ASTWrapperPsiElement implements VerilogWireNameAndOptAssign { 15 | 16 | public VerilogWireNameAndOptAssignImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitWireNameAndOptAssign(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogExpr getExpr() { 32 | return findChildByClass(VerilogExpr.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogWireName getWireName() { 38 | return findNotNullChildByClass(VerilogWireName.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAssignExprListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAssignExprListImpl extends ASTWrapperPsiElement implements VerilogAssignExprList { 15 | 16 | public VerilogAssignExprListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAssignExprList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogAssignExpr getAssignExpr() { 32 | return findNotNullChildByClass(VerilogAssignExpr.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogAssignExprList getAssignExprList() { 38 | return findChildByClass(VerilogAssignExprList.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogModuleBodyImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogModuleBodyImpl extends ASTWrapperPsiElement implements VerilogModuleBody { 15 | 16 | public VerilogModuleBodyImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitModuleBody(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogModuleBodyRest getModuleBodyRest() { 32 | return findNotNullChildByClass(VerilogModuleBodyRest.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogModuleBodyStmt getModuleBodyStmt() { 38 | return findNotNullChildByClass(VerilogModuleBodyStmt.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogModuleBodyRestImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogModuleBodyRestImpl extends ASTWrapperPsiElement implements VerilogModuleBodyRest { 15 | 16 | public VerilogModuleBodyRestImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitModuleBodyRest(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogModuleBodyRest getModuleBodyRest() { 32 | return findChildByClass(VerilogModuleBodyRest.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogModuleBodyStmt getModuleBodyStmt() { 38 | return findChildByClass(VerilogModuleBodyStmt.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogParamDeclListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogParamDeclListImpl extends ASTWrapperPsiElement implements VerilogParamDeclList { 15 | 16 | public VerilogParamDeclListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitParamDeclList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogParamDeclList getParamDeclList() { 32 | return findChildByClass(VerilogParamDeclList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogSingleParamDecl getSingleParamDecl() { 38 | return findNotNullChildByClass(VerilogSingleParamDecl.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogWireNameListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogWireNameListImpl extends ASTWrapperPsiElement implements VerilogWireNameList { 15 | 16 | public VerilogWireNameListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitWireNameList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogWireNameAndOptAssign getWireNameAndOptAssign() { 32 | return findNotNullChildByClass(VerilogWireNameAndOptAssign.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogWireNameList getWireNameList() { 38 | return findChildByClass(VerilogWireNameList.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCellParameterListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCellParameterListImpl extends ASTWrapperPsiElement implements VerilogCellParameterList { 15 | 16 | public VerilogCellParameterListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCellParameterList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCellParameter getCellParameter() { 32 | return findChildByClass(VerilogCellParameter.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogCellParameterList getCellParameterList() { 38 | return findChildByClass(VerilogCellParameterList.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogBehavioralStmtListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogBehavioralStmtListImpl extends ASTWrapperPsiElement implements VerilogBehavioralStmtList { 15 | 16 | public VerilogBehavioralStmtListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitBehavioralStmtList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogBehavioralStmt getBehavioralStmt() { 32 | return findChildByClass(VerilogBehavioralStmt.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogBehavioralStmtList getBehavioralStmtList() { 38 | return findChildByClass(VerilogBehavioralStmtList.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogDefparamDeclListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogDefparamDeclListImpl extends ASTWrapperPsiElement implements VerilogDefparamDeclList { 15 | 16 | public VerilogDefparamDeclListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitDefparamDeclList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogDefparamDeclList getDefparamDeclList() { 32 | return findChildByClass(VerilogDefparamDeclList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogSingleDefparamDecl getSingleDefparamDecl() { 38 | return findNotNullChildByClass(VerilogSingleDefparamDecl.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogWireTypeTokenListImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogWireTypeTokenListImpl extends ASTWrapperPsiElement implements VerilogWireTypeTokenList { 15 | 16 | public VerilogWireTypeTokenListImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitWireTypeTokenList(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogWireTypeToken getWireTypeToken() { 32 | return findChildByClass(VerilogWireTypeToken.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogWireTypeTokenListRest getWireTypeTokenListRest() { 38 | return findChildByClass(VerilogWireTypeTokenListRest.class); 39 | } 40 | 41 | } 42 | -------------------------------------------------------------------------------- /src/test/java/com/verilogplugin/VerilogParsingTest.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin; 17 | 18 | import com.intellij.testFramework.ParsingTestCase; 19 | import com.verilogplugin.lang.core.VerilogParserDefinition; 20 | 21 | public class VerilogParsingTest extends ParsingTestCase { 22 | public VerilogParsingTest() { 23 | super("", "v", new VerilogParserDefinition()); 24 | } 25 | 26 | public void testParsingTestData() { 27 | doTest(true); 28 | } 29 | 30 | @Override 31 | protected String getTestDataPath() { 32 | return VerilogParsingTest.class.getResource("testData/test.v").getPath(); 33 | } 34 | 35 | @Override 36 | protected boolean skipSpaces() { 37 | return false; 38 | } 39 | 40 | @Override 41 | protected boolean includeRanges() { 42 | return true; 43 | } 44 | } 45 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/commenter/VerilogCommenter.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.commenter; 17 | 18 | import com.intellij.lang.Commenter; 19 | import org.jetbrains.annotations.Nullable; 20 | 21 | public class VerilogCommenter implements Commenter { 22 | @Nullable 23 | @Override 24 | public String getLineCommentPrefix() { 25 | return "//"; 26 | } 27 | 28 | @Nullable 29 | @Override 30 | public String getBlockCommentPrefix() { 31 | return "/*"; 32 | } 33 | 34 | @Nullable 35 | @Override 36 | public String getBlockCommentSuffix() { 37 | return "*/"; 38 | } 39 | 40 | @Nullable 41 | @Override 42 | public String getCommentedBlockCommentPrefix() { 43 | return "/**"; 44 | } 45 | 46 | @Nullable 47 | @Override 48 | public String getCommentedBlockCommentSuffix() { 49 | return "**/"; 50 | } 51 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogAlwaysStmtImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogAlwaysStmtImpl extends ASTWrapperPsiElement implements VerilogAlwaysStmt { 15 | 16 | public VerilogAlwaysStmtImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitAlwaysStmt(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAlwaysCond getAlwaysCond() { 32 | return findChildByClass(VerilogAlwaysCond.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogAttrOpt getAttrOpt() { 38 | return findChildByClass(VerilogAttrOpt.class); 39 | } 40 | 41 | @Override 42 | @NotNull 43 | public VerilogBehavioralStmt getBehavioralStmt() { 44 | return findNotNullChildByClass(VerilogBehavioralStmt.class); 45 | } 46 | 47 | } 48 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogSingleDefparamDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogSingleDefparamDeclImpl extends ASTWrapperPsiElement implements VerilogSingleDefparamDecl { 15 | 16 | public VerilogSingleDefparamDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitSingleDefparamDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogExpr getExpr() { 32 | return findNotNullChildByClass(VerilogExpr.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogHierarchicalId getHierarchicalId() { 38 | return findNotNullChildByClass(VerilogHierarchicalId.class); 39 | } 40 | 41 | @Override 42 | @NotNull 43 | public VerilogRange getRange() { 44 | return findNotNullChildByClass(VerilogRange.class); 45 | } 46 | 47 | } 48 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/psi/VerilogFile.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core.psi; 17 | 18 | import com.intellij.extapi.psi.PsiFileBase; 19 | import com.intellij.openapi.fileTypes.FileType; 20 | import com.intellij.psi.FileViewProvider; 21 | import com.verilogplugin.lang.core.VerilogFileType; 22 | import com.verilogplugin.lang.core.VerilogLanguage; 23 | import org.jetbrains.annotations.NotNull; 24 | 25 | import javax.swing.*; 26 | 27 | public class VerilogFile extends PsiFileBase { 28 | public VerilogFile(@NotNull FileViewProvider viewProvider) { 29 | super(viewProvider, VerilogLanguage.INSTANCE); 30 | } 31 | 32 | @NotNull 33 | @Override 34 | public FileType getFileType() { 35 | return VerilogFileType.INSTANCE; 36 | } 37 | 38 | @Override 39 | public String toString() { 40 | return "Verilog File"; 41 | } 42 | 43 | @Override 44 | public Icon getIcon(int flags) { 45 | return super.getIcon(flags); 46 | } 47 | } -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/VerilogFileType.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core; 17 | 18 | import com.intellij.openapi.fileTypes.LanguageFileType; 19 | import org.jetbrains.annotations.NotNull; 20 | import org.jetbrains.annotations.Nullable; 21 | 22 | import javax.swing.*; 23 | 24 | public class VerilogFileType extends LanguageFileType { 25 | public static final VerilogFileType INSTANCE = new VerilogFileType(); 26 | 27 | private VerilogFileType() { 28 | super(VerilogLanguage.INSTANCE); 29 | } 30 | 31 | @NotNull 32 | @Override 33 | public String getName() { 34 | return "Verilog file"; 35 | } 36 | 37 | @NotNull 38 | @Override 39 | public String getDescription() { 40 | return "Verilog HDL file"; 41 | } 42 | 43 | @NotNull 44 | @Override 45 | public String getDefaultExtension() { 46 | return "v"; 47 | } 48 | 49 | @Nullable 50 | @Override 51 | public Icon getIcon() { 52 | return VerilogIcons.FILE; 53 | } 54 | } -------------------------------------------------------------------------------- /src/test/java/com/verilogplugin/VerilogCodeInsightTest.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin; 17 | 18 | import com.intellij.codeInsight.generation.actions.CommentByLineCommentAction; 19 | import com.intellij.testFramework.fixtures.LightCodeInsightFixtureTestCase; 20 | import com.verilogplugin.lang.core.VerilogFileType; 21 | 22 | public class VerilogCodeInsightTest extends LightCodeInsightFixtureTestCase { 23 | @Override 24 | protected String getTestDataPath() { 25 | return VerilogCodeInsightTest.class.getResource("testData/test.v").getPath(); 26 | } 27 | 28 | public void testCommenter() { 29 | myFixture.configureByText(VerilogFileType.INSTANCE, "a+b"); 30 | CommentByLineCommentAction commentAction = new CommentByLineCommentAction(); 31 | commentAction.actionPerformedImpl(getProject(), myFixture.getEditor()); 32 | myFixture.checkResult("//a+b"); 33 | commentAction.actionPerformedImpl(getProject(), myFixture.getEditor()); 34 | myFixture.checkResult("a+b"); 35 | } 36 | 37 | 38 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogParamDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogParamDeclImpl extends ASTWrapperPsiElement implements VerilogParamDecl { 15 | 16 | public VerilogParamDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitParamDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogParamDeclList getParamDeclList() { 32 | return findNotNullChildByClass(VerilogParamDeclList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogParamInteger getParamInteger() { 38 | return findNotNullChildByClass(VerilogParamInteger.class); 39 | } 40 | 41 | @Override 42 | @NotNull 43 | public VerilogParamRange getParamRange() { 44 | return findNotNullChildByClass(VerilogParamRange.class); 45 | } 46 | 47 | @Override 48 | @NotNull 49 | public VerilogParamSigned getParamSigned() { 50 | return findNotNullChildByClass(VerilogParamSigned.class); 51 | } 52 | 53 | } 54 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogLocalparamDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogLocalparamDeclImpl extends ASTWrapperPsiElement implements VerilogLocalparamDecl { 15 | 16 | public VerilogLocalparamDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitLocalparamDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @NotNull 31 | public VerilogParamDeclList getParamDeclList() { 32 | return findNotNullChildByClass(VerilogParamDeclList.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogParamInteger getParamInteger() { 38 | return findNotNullChildByClass(VerilogParamInteger.class); 39 | } 40 | 41 | @Override 42 | @NotNull 43 | public VerilogParamRange getParamRange() { 44 | return findNotNullChildByClass(VerilogParamRange.class); 45 | } 46 | 47 | @Override 48 | @NotNull 49 | public VerilogParamSigned getParamSigned() { 50 | return findNotNullChildByClass(VerilogParamSigned.class); 51 | } 52 | 53 | } 54 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogWireDeclImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogWireDeclImpl extends ASTWrapperPsiElement implements VerilogWireDecl { 15 | 16 | public VerilogWireDeclImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitWireDecl(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAttrOpt getAttrOpt() { 32 | return findChildByClass(VerilogAttrOpt.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogRange getRange() { 38 | return findChildByClass(VerilogRange.class); 39 | } 40 | 41 | @Override 42 | @Nullable 43 | public VerilogWireNameList getWireNameList() { 44 | return findChildByClass(VerilogWireNameList.class); 45 | } 46 | 47 | @Override 48 | @Nullable 49 | public VerilogWireType getWireType() { 50 | return findChildByClass(VerilogWireType.class); 51 | } 52 | 53 | @Override 54 | @Nullable 55 | public PsiElement getIdentifier() { 56 | return findChildByType(IDENTIFIER); 57 | } 58 | 59 | } 60 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogModuleArgImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogModuleArgImpl extends ASTWrapperPsiElement implements VerilogModuleArg { 15 | 16 | public VerilogModuleArgImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitModuleArg(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAttr getAttr() { 32 | return findChildByClass(VerilogAttr.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogModuleArgOptAssignment getModuleArgOptAssignment() { 38 | return findChildByClass(VerilogModuleArgOptAssignment.class); 39 | } 40 | 41 | @Override 42 | @Nullable 43 | public VerilogRange getRange() { 44 | return findChildByClass(VerilogRange.class); 45 | } 46 | 47 | @Override 48 | @Nullable 49 | public VerilogWireType getWireType() { 50 | return findChildByClass(VerilogWireType.class); 51 | } 52 | 53 | @Override 54 | @NotNull 55 | public PsiElement getIdentifier() { 56 | return findNotNullChildByType(IDENTIFIER); 57 | } 58 | 59 | } 60 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogRvalueImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogRvalueImpl extends ASTWrapperPsiElement implements VerilogRvalue { 15 | 16 | public VerilogRvalueImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitRvalue(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogExpr getExpr() { 32 | return findChildByClass(VerilogExpr.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public VerilogHierarchicalId getHierarchicalId() { 38 | return findNotNullChildByClass(VerilogHierarchicalId.class); 39 | } 40 | 41 | @Override 42 | @NotNull 43 | public List getNonOptRangeList() { 44 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogNonOptRange.class); 45 | } 46 | 47 | @Override 48 | @Nullable 49 | public VerilogRange getRange() { 50 | return findChildByClass(VerilogRange.class); 51 | } 52 | 53 | @Override 54 | @Nullable 55 | public VerilogRvalue getRvalue() { 56 | return findChildByClass(VerilogRvalue.class); 57 | } 58 | 59 | } 60 | -------------------------------------------------------------------------------- /src/main/java/com/verilogplugin/lang/core/psi/VerilogElementFactory.java: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2014 @max6cn 3 | * All rights reserved. This program and the accompanying materials 4 | * are made available under the terms of the GNU Lesser General Public License 5 | * (LGPL) version 2.1 which accompanies this distribution, and is available at 6 | * http://www.gnu.org/licenses/lgpl-2.1.html 7 | * This library is distributed in the hope that it will be useful, 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 10 | * Lesser General Public License for more details. 11 | * 12 | * Contributors: 13 | * @max6cn 14 | */ 15 | 16 | package com.verilogplugin.lang.core.psi; 17 | 18 | import com.intellij.openapi.project.Project; 19 | import com.intellij.psi.PsiElement; 20 | import com.intellij.psi.PsiFileFactory; 21 | import com.verilogplugin.lang.core.VerilogFileType; 22 | 23 | public class VerilogElementFactory { 24 | // public static VerilogProperty createProperty(Project project, String name, String value) { 25 | // final VerilogFile file = createFile(project, name + " = " + value); 26 | // return (VerilogProperty) file.getFirstChild(); 27 | // } 28 | // 29 | // public static VerilogProperty createProperty(Project project, String name) { 30 | // final VerilogFile file = createFile(project, name); 31 | // return (VerilogProperty) file.getFirstChild(); 32 | // } 33 | 34 | public static PsiElement createCRLF(Project project) { 35 | final VerilogFile file = createFile(project, "\n"); 36 | return file.getFirstChild(); 37 | } 38 | 39 | public static VerilogFile createFile(Project project, String text) { 40 | String name = "dummy.v"; 41 | return (VerilogFile) PsiFileFactory.getInstance(project). 42 | createFileFromText(name, VerilogFileType.INSTANCE, text); 43 | } 44 | } -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogCellStmtImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogCellStmtImpl extends ASTWrapperPsiElement implements VerilogCellStmt { 15 | 16 | public VerilogCellStmtImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitCellStmt(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAttrOpt getAttrOpt() { 32 | return findChildByClass(VerilogAttrOpt.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogCellList getCellList() { 38 | return findChildByClass(VerilogCellList.class); 39 | } 40 | 41 | @Override 42 | @Nullable 43 | public VerilogCellParameterListOpt getCellParameterListOpt() { 44 | return findChildByClass(VerilogCellParameterListOpt.class); 45 | } 46 | 47 | @Override 48 | @Nullable 49 | public VerilogPrimList getPrimList() { 50 | return findChildByClass(VerilogPrimList.class); 51 | } 52 | 53 | @Override 54 | @Nullable 55 | public VerilogTokPrimWrapper getTokPrimWrapper() { 56 | return findChildByClass(VerilogTokPrimWrapper.class); 57 | } 58 | 59 | @Override 60 | @Nullable 61 | public PsiElement getIdentifier() { 62 | return findChildByType(IDENTIFIER); 63 | } 64 | 65 | } 66 | -------------------------------------------------------------------------------- /.github/workflows/release.yml: -------------------------------------------------------------------------------- 1 | # GitHub Actions Workflow created for handling the release process based on the draft release prepared 2 | # with the Build workflow. Running the publishPlugin task requires the PUBLISH_TOKEN secret provided. 3 | 4 | name: Release 5 | on: 6 | release: 7 | types: [prereleased, released] 8 | 9 | jobs: 10 | 11 | # Prepare and publish the plugin to the Marketplace repository 12 | release: 13 | name: Publish Plugin 14 | runs-on: ubuntu-latest 15 | steps: 16 | 17 | # Setup Java 1.8 environment for the next steps 18 | - name: Setup Java 19 | uses: actions/setup-java@v1 20 | with: 21 | java-version: 1.8 22 | 23 | # Check out current repository 24 | - name: Fetch Sources 25 | uses: actions/checkout@v2 26 | with: 27 | ref: ${{ github.event.release.tag_name }} 28 | 29 | # Publish the plugin to the Marketplace 30 | - name: Publish Plugin 31 | env: 32 | PUBLISH_TOKEN: ${{ secrets.PUBLISH_TOKEN }} 33 | run: ./gradlew publishPlugin 34 | 35 | # Patch changelog, commit and push to the current repository 36 | changelog: 37 | name: Update Changelog 38 | needs: release 39 | runs-on: ubuntu-latest 40 | steps: 41 | 42 | # Setup Java 1.8 environment for the next steps 43 | - name: Setup Java 44 | uses: actions/setup-java@v1 45 | with: 46 | java-version: 1.8 47 | 48 | # Check out current repository 49 | - name: Fetch Sources 50 | uses: actions/checkout@v2 51 | with: 52 | ref: ${{ github.event.release.tag_name }} 53 | 54 | # Update Unreleased section with the current version 55 | - name: Patch Changelog 56 | run: ./gradlew patchChangelog 57 | 58 | # Commit patched Changelog 59 | - name: Commit files 60 | run: | 61 | git config --local user.email "action@github.com" 62 | git config --local user.name "GitHub Action" 63 | git commit -m "Update changelog" -a 64 | 65 | # Push changes 66 | - name: Push changes 67 | uses: ad-m/github-push-action@master 68 | with: 69 | branch: main 70 | github_token: ${{ secrets.GITHUB_TOKEN }} 71 | -------------------------------------------------------------------------------- /.github/template-cleanup/README.md: -------------------------------------------------------------------------------- 1 | # %NAME% 2 | 3 | ![Build](https://github.com/%REPOSITORY%/workflows/Build/badge.svg) 4 | [![Version](https://img.shields.io/jetbrains/plugin/v/PLUGIN_ID.svg)](https://plugins.jetbrains.com/plugin/PLUGIN_ID) 5 | [![Downloads](https://img.shields.io/jetbrains/plugin/d/PLUGIN_ID.svg)](https://plugins.jetbrains.com/plugin/PLUGIN_ID) 6 | 7 | ## Template ToDo list 8 | - [x] Create a new [IntelliJ Platform Plugin Template][template] project. 9 | - [ ] Verify the [pluginGroup](/gradle.properties), [plugin ID](/src/main/resources/META-INF/plugin.xml) and [sources package](/src/main/kotlin). 10 | - [ ] Review the [Legal Agreements](https://plugins.jetbrains.com/docs/marketplace/legal-agreements.html). 11 | - [ ] [Publish a plugin manually](https://www.jetbrains.org/intellij/sdk/docs/basics/getting_started/publishing_plugin.html) for the first time. 12 | - [ ] Set the Plugin ID in the above README badges. 13 | - [ ] Set the [Deployment Token](https://plugins.jetbrains.com/docs/marketplace/plugin-upload.html). 14 | - [ ] Click the Watch button on the top of the [IntelliJ Platform Plugin Template][template] to be notified about releases containing new features and fixes. 15 | 16 | 17 | This Fancy IntelliJ Platform Plugin is going to be your implementation of the brilliant ideas that you have. 18 | 19 | This specific section is a source for the [plugin.xml](/src/main/resources/META-INF/plugin.xml) file which will be extracted by the [Gradle](/build.gradle.kts) during the build process. 20 | 21 | To keep everything working, do not remove `` sections. 22 | 23 | 24 | ## Installation 25 | 26 | - Using IDE built-in plugin system: 27 | 28 | Preferences > Plugins > Marketplace > Search for "%NAME%" > 29 | Install Plugin 30 | 31 | - Manually: 32 | 33 | Download the [latest release](https://github.com/%REPOSITORY%/releases/latest) and install it manually using 34 | Preferences > Plugins > ⚙️ > Install plugin from disk... 35 | 36 | 37 | --- 38 | Plugin based on the [IntelliJ Platform Plugin Template][template]. 39 | 40 | [template]: https://github.com/JetBrains/intellij-platform-plugin-template 41 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogModuleImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogModuleImpl extends ASTWrapperPsiElement implements VerilogModule { 15 | 16 | public VerilogModuleImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitModule(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogAttrOpt getAttrOpt() { 32 | return findChildByClass(VerilogAttrOpt.class); 33 | } 34 | 35 | @Override 36 | @NotNull 37 | public List getModuleArgsList() { 38 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogModuleArgs.class); 39 | } 40 | 41 | @Override 42 | @Nullable 43 | public VerilogModuleBody getModuleBody() { 44 | return findChildByClass(VerilogModuleBody.class); 45 | } 46 | 47 | @Override 48 | @NotNull 49 | public List getParamIntegerList() { 50 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogParamInteger.class); 51 | } 52 | 53 | @Override 54 | @NotNull 55 | public List getParamRangeList() { 56 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogParamRange.class); 57 | } 58 | 59 | @Override 60 | @NotNull 61 | public List getParamSignedList() { 62 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogParamSigned.class); 63 | } 64 | 65 | @Override 66 | @NotNull 67 | public List getSingleParamDeclList() { 68 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogSingleParamDecl.class); 69 | } 70 | 71 | @Override 72 | @Nullable 73 | public PsiElement getIdentifier() { 74 | return findChildByType(IDENTIFIER); 75 | } 76 | 77 | } 78 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogGenStmtImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.intellij.extapi.psi.ASTWrapperPsiElement; 12 | import com.verilogplugin.lang.core.psi.*; 13 | 14 | public class VerilogGenStmtImpl extends ASTWrapperPsiElement implements VerilogGenStmt { 15 | 16 | public VerilogGenStmtImpl(@NotNull ASTNode node) { 17 | super(node); 18 | } 19 | 20 | public void accept(@NotNull VerilogVisitor visitor) { 21 | visitor.visitGenStmt(this); 22 | } 23 | 24 | public void accept(@NotNull PsiElementVisitor visitor) { 25 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 26 | else super.accept(visitor); 27 | } 28 | 29 | @Override 30 | @Nullable 31 | public VerilogCaseType getCaseType() { 32 | return findChildByClass(VerilogCaseType.class); 33 | } 34 | 35 | @Override 36 | @Nullable 37 | public VerilogExpr getExpr() { 38 | return findChildByClass(VerilogExpr.class); 39 | } 40 | 41 | @Override 42 | @Nullable 43 | public VerilogGenCaseBody getGenCaseBody() { 44 | return findChildByClass(VerilogGenCaseBody.class); 45 | } 46 | 47 | @Override 48 | @Nullable 49 | public VerilogGenStmtBlock getGenStmtBlock() { 50 | return findChildByClass(VerilogGenStmtBlock.class); 51 | } 52 | 53 | @Override 54 | @Nullable 55 | public VerilogModuleBodyStmt getModuleBodyStmt() { 56 | return findChildByClass(VerilogModuleBodyStmt.class); 57 | } 58 | 59 | @Override 60 | @Nullable 61 | public VerilogModuleGenBody getModuleGenBody() { 62 | return findChildByClass(VerilogModuleGenBody.class); 63 | } 64 | 65 | @Override 66 | @Nullable 67 | public VerilogOptGenElse getOptGenElse() { 68 | return findChildByClass(VerilogOptGenElse.class); 69 | } 70 | 71 | @Override 72 | @NotNull 73 | public List getOptLabelList() { 74 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogOptLabel.class); 75 | } 76 | 77 | @Override 78 | @NotNull 79 | public List getSimpleBehavioralStmtList() { 80 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogSimpleBehavioralStmt.class); 81 | } 82 | 83 | } 84 | -------------------------------------------------------------------------------- /src/gen/com/verilogplugin/lang/core/psi/impl/VerilogBasicExprImpl.java: -------------------------------------------------------------------------------- 1 | // This is a generated file. Not intended for manual editing. 2 | package com.verilogplugin.lang.core.psi.impl; 3 | 4 | import java.util.List; 5 | import org.jetbrains.annotations.*; 6 | import com.intellij.lang.ASTNode; 7 | import com.intellij.psi.PsiElement; 8 | import com.intellij.psi.PsiElementVisitor; 9 | import com.intellij.psi.util.PsiTreeUtil; 10 | import static com.verilogplugin.lang.core.psi.VerilogTokenTypes.*; 11 | import com.verilogplugin.lang.core.psi.*; 12 | 13 | public class VerilogBasicExprImpl extends VerilogExprImpl implements VerilogBasicExpr { 14 | 15 | public VerilogBasicExprImpl(@NotNull ASTNode node) { 16 | super(node); 17 | } 18 | 19 | public void accept(@NotNull VerilogVisitor visitor) { 20 | visitor.visitBasicExpr(this); 21 | } 22 | 23 | public void accept(@NotNull PsiElementVisitor visitor) { 24 | if (visitor instanceof VerilogVisitor) accept((VerilogVisitor)visitor); 25 | else super.accept(visitor); 26 | } 27 | 28 | @Override 29 | @Nullable 30 | public VerilogArgList getArgList() { 31 | return findChildByClass(VerilogArgList.class); 32 | } 33 | 34 | @Override 35 | @NotNull 36 | public List getAttrList() { 37 | return PsiTreeUtil.getChildrenOfTypeAsList(this, VerilogAttr.class); 38 | } 39 | 40 | @Override 41 | @Nullable 42 | public VerilogCaseItem getCaseItem() { 43 | return findChildByClass(VerilogCaseItem.class); 44 | } 45 | 46 | @Override 47 | @Nullable 48 | public VerilogConcatList getConcatList() { 49 | return findChildByClass(VerilogConcatList.class); 50 | } 51 | 52 | @Override 53 | @Nullable 54 | public VerilogExpr getExpr() { 55 | return findChildByClass(VerilogExpr.class); 56 | } 57 | 58 | @Override 59 | @Nullable 60 | public VerilogGenCaseItem getGenCaseItem() { 61 | return findChildByClass(VerilogGenCaseItem.class); 62 | } 63 | 64 | @Override 65 | @Nullable 66 | public VerilogHierarchicalId getHierarchicalId() { 67 | return findChildByClass(VerilogHierarchicalId.class); 68 | } 69 | 70 | @Override 71 | @Nullable 72 | public VerilogOptSynopsysAttr getOptSynopsysAttr() { 73 | return findChildByClass(VerilogOptSynopsysAttr.class); 74 | } 75 | 76 | @Override 77 | @Nullable 78 | public VerilogOptionalComma getOptionalComma() { 79 | return findChildByClass(VerilogOptionalComma.class); 80 | } 81 | 82 | @Override 83 | @Nullable 84 | public VerilogRvalue getRvalue() { 85 | return findChildByClass(VerilogRvalue.class); 86 | } 87 | 88 | } 89 | --------------------------------------------------------------------------------