├── LICENSE ├── README.md ├── usb_ctrl.v └── usb_top.v /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. By contrast, the GNU General Public 13 | License is intended to guarantee your freedom to share and change free 14 | software--to make sure the software is free for all its users. This 15 | General Public License applies to most of the Free Software 16 | Foundation's software and to any other program whose authors commit to 17 | using it. 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If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # USB_Ctrl 2 | 使用Verilog对USB芯片的控制时序示例 3 | 4 | 环境 5 | = 6 | FPGA：Altera Cyclone IV E EP4CE30F23C8
7 | Software：Quartus II 13.0
8 | USB IC: CY7C68013A
9 | 本代码针对 所使用的开发板上的USB芯片 调试，不保证一定可以移植到别的平台上正常使用，仅供参考
10 | USB的传输方式选择了异步传输 11 | 12 | 文件 13 | = 14 | * `usb_ctrl.v` : CY7C68013A USB芯片的驱动程序，使用verilog语言 15 | * `usb_top.v` : 对`usb_ctrl.v`的示例使用程序（example） 16 | 17 | `usb_top.v` 18 | == 19 | 参数定义 20 | -- 21 | * `LOOP_WORK` : 当该参数设为1时，发送的数据将会是从USB芯片接受到的数据，形成一个loopback，write_data输入端口无效 22 | * `AUTO_WORK` : 当该参数设为1时，驱动将会自动完成读取USB数据到向USB写入数据的过程，此参数主要用于测试使用 23 | * `AUTO_RNUM` : 当`AUTO_WORK`为1时，该值有效，该值表示每次读取数据过程的数目，同时rd_wr_num输入端口无效 24 | * `AUTO_WNUM` : 当`AUTO_WORK`为1时，该值有效，该值表示每次写入数据过程的数目，同时rd_wr_num输入端口无效 25 | * `TS_NUM` : 每次读取过程或者写入数据过程中需要等待的时间长度，时间最好控制在50ns以上 26 | 27 | 状态机跳转条件 28 | ------ 29 | * `IDLE` ：空闲状态，如果不在测试状态（`AUTO_WORK = 0`），会根据rd_wr_en, usb_n_ept_to或usb_n_ful_sx进行状态跳转至`RD_PRE`,`WR`;否则会根据usb_n_ept_to或usb_n_ful_sx进行状态跳转至`RD_PRE`,`WR`，优先进入`RD_PRE` 30 | 31 | * `RD_PRE` ：读取准备状态，拉低usb_sloe, usb_slrd，然后跳转至`RD` 32 | 33 | * `RD` ：读取状态，如果fifo读取已空，会跳转至`RD_BURST`；如果不在测试状态，会根据rd_wr_en，cnt_data进行状态跳转至`RD_OVER`,`RD_BURST`;否则会根据cnt_data进行状态跳转至`RD_BURST`，该过程usb_sloe,usb_slrd,ts_cnt会进行相关操作 34 | 35 | * `RD_BURST`：读取结束状态，如果不在测试状态，状态回到`IDLE`状态，否则根据usb_n_ful_sx跳转到`WR`或`IDLE`状态 36 | 37 | * `RD_OVER` ：再次读取状态，该状态在测试状态下不会使用。仅当非测试状态并且在`RD`状态下读取完rd_wr_num的数据后rd_wr_en依旧使能读状态时会进入该状态；如果fifo读取已空，会跳转至`RD_BURST`，会根据rd_wr_en，cnt_data进行状态跳转至`RD_OVER`,`RD_BURST` 38 | 39 | * `WR` ：写入状态，如果fifo写入已满，会跳转至`WR_BURST`；如果不在测试状态，会根据rd_wr_en，cnt_data进行状态跳转至`WR_OVER`,`WR_BURST`;否则会根据cnt_data进行状态跳转至`WR_BURST`，该过程usb_sloe,usb_slrd,ts_cnt会进行相关操作 40 | 41 | * `WR_BURST`：写入结束状态，状态跳转至`IDLE`状态 42 | 43 | * `WR_OVER` ：再次写入状态，该状态在测试状态下不会使用。仅当非测试状态并且在`WR`状态下读取完rd_wr_num的数据后rd_wr_en依旧使能写状态时会进入该状态；如果fifo写入已满，会跳转至`WR_BURST`，会根据rd_wr_en，cnt_data进行状态跳转至`WR_OVER`,`WR_BURST` 44 | 45 | 内部寄存器状态 46 | -- 47 | 主要是wr_req(控制inout端口的usb_data的输入输出方向),cnt_data（记录读取或写入数据的数目）,ts_cnt（每次读取或者写入过程前的setup time计数器）在各种状态下的输出操作。 48 | 49 | 外部信号 50 | -- 51 | 主要有tra_data（传输数据）,usb_slcs（usb片选信号，低有效），usb_sloe（usb输出有效信号，低有效）,usb_slrd（usb读取信号，低有效），usb_slwr（usb写入信号，低有效），usb_addr（usb的fifo地址），read_data（读取的数据），output_valid（输出数据的有效指示信号），write_ready（写入数据的准备信号）。 52 | -------------------------------------------------------------------------------- /usb_ctrl.v: -------------------------------------------------------------------------------- 1 | /* 2 | @author : WoodFan 3 | @date : 2019/04/08 4 | @name : usb_ctrl 5 | @function 6 | ** usb driver of ctrol 7 | */ 8 | module usb_ctrl 9 | #( 10 | parameter LOOP_WORK = 1 , //loopback 11 | parameter AUTO_WORK = 1 , //automatic receive data then transmit data 12 | parameter AUTO_RNUM = 8 , 13 | parameter AUTO_WNUM = 8 , 14 | parameter TS_NUM = 4 // setup time loop number 15 | ) 16 | ( 17 | /* FPGA main interface */ 18 | input clk , 19 | input rst_n , 20 | /* USB FIFO Indication*/ 21 | input usb_n_ept_to, /*FIFO2 empty*/ 22 | input usb_n_ept_fr, /*FIFO4 empty*/ 23 | input usb_n_ful_sx, /*FIFO6 full */ 24 | inout [15:0] usb_data , 25 | /* device ctrl */ 26 | input [10:0] rd_wr_num , /* the number of read or write data */ 27 | input [ 1:0] rd_wr_en , /* 10 -> read or 01 -> write */ 28 | output usb_is_busy , 29 | output reg [15:0]read_data , 30 | input [15:0] write_data , 31 | output reg output_valid, 32 | output reg write_ready , 33 | /* USB Ctrl Signal*/ 34 | output reg usb_slcs , /* chipselect */ 35 | output reg usb_sloe , /* data output enable */ 36 | output reg usb_slrd , /* read indicate */ 37 | output reg usb_slwr , /* write req */ 38 | output reg [ 1:0]usb_addr 39 | ); 40 | 41 | //FSM State 42 | localparam IDLE = 4'd0 , 43 | RD_PRE=4'd1 , 44 | RD = 4'd2 , 45 | RD_BURST = 4'd3, 46 | RD_OVER = 4'd5 , 47 | WR = 4'd7 , 48 | WR_BURST = 4'd9, 49 | WR_OVER = 4'd11 50 | ; 51 | //read_date 52 | wire [15:0] rec_data ; 53 | //FSM register 54 | reg [ 3:0] state ; 55 | reg [ 3:0] state_nxt; 56 | //indication whether to write or read 57 | reg wr_req ; 58 | //the counter of setup time 59 | reg [ 7:0] ts_cnt ; 60 | 61 | reg [15:0] tra_data ; 62 | // the counter of write data or read data 63 | reg [10:0] cnt_data ; 64 | 65 | 66 | /* only LOOP_WORK set to 1, the receive data will be sent to PC again */ 67 | assign usb_data = wr_req ? ((LOOP_WORK == 1) ? rec_data : tra_data) : 16'hzzzz; 68 | assign rec_data = read_data; 69 | //when state != IDLe and need to read but fifo is emptyed or need to write but fifo is full, is_busy will be high 70 | assign usb_is_busy = (state == IDLE) ? 1'b0 : ((rd_wr_en == 2'b10 && !usb_n_ept_to) ? 1'b0 : ((rd_wr_en == 2'b01 && !usb_n_ful_sx) ? 1'b0: 1'b1)); 71 | 72 | always @ (posedge clk or negedge rst_n) 73 | begin 74 | if (!rst_n) 75 | begin 76 | state <= IDLE; 77 | end 78 | else 79 | begin 80 | state <= state_nxt; 81 | end 82 | end 83 | 84 | /* 85 | FSM 86 | AUTOWORK == 1 // Test Mode 87 | IDLE RD RD_BURST WR WR_BURST 88 | FIFO2 not empty -> the number of read data meet AUTO_RNUM -> FIFO6 not full -> the number of write data meet AUTO_RNUM -> IDLE 89 | 90 | AUTOWORK == 1 -> RD_OVER(RD) -----| 91 | IDLE RD | RD_BURST | 92 | FIFO2 not empty -> the number of read data meet rd_wr_num -> IDLE <------ 93 | and FIFO6 not -> WR_OVER(WR) ------| 94 | full and WR | WR_BURST | 95 | case(rd_wr_en) -> the number of write data meet rd_wr_num -> IDLE <------ 96 | */ 97 | always @ (*) 98 | begin 99 | state_nxt = state; 100 | case (state) 101 | IDLE: 102 | begin 103 | if (AUTO_WORK == 0) 104 | case (rd_wr_en) 105 | 2'b10: state_nxt = usb_n_ept_to ? RD_PRE : IDLE; 106 | 2'b01: state_nxt = usb_n_ful_sx ? WR : IDLE; 107 | default: state_nxt = IDLE; 108 | endcase 109 | else 110 | state_nxt = usb_n_ept_to ? RD : (usb_n_ful_sx ? WR : IDLE); 111 | end 112 | 113 | RD_PRE: 114 | begin 115 | state_nxt = RD; 116 | end 117 | 118 | RD: 119 | begin 120 | if (!usb_n_ept_to) 121 | state_nxt = RD_BURST; 122 | else if (AUTO_WORK == 0) 123 | if (rd_wr_en == 2'b10 && cnt_data >= rd_wr_num) 124 | state_nxt = RD_OVER; 125 | else if (cnt_data >= rd_wr_num) 126 | state_nxt = RD_BURST; 127 | else 128 | state_nxt = RD; 129 | else 130 | if (cnt_data >= AUTO_RNUM) 131 | state_nxt = RD_BURST; 132 | else 133 | state_nxt = RD; 134 | end 135 | 136 | RD_BURST: 137 | begin 138 | if (AUTO_WORK == 0) 139 | state_nxt = IDLE; 140 | else 141 | state_nxt = usb_n_ful_sx ? WR : IDLE; 142 | end 143 | 144 | RD_OVER: 145 | begin 146 | if (!usb_n_ept_to) 147 | state_nxt = RD_BURST; 148 | else if (rd_wr_en == 2'b10 && cnt_data >= rd_wr_num) 149 | state_nxt = RD_OVER; 150 | else if (cnt_data >= rd_wr_num) 151 | state_nxt = RD_BURST; 152 | end 153 | 154 | WR: 155 | begin 156 | if (!usb_n_ful_sx) 157 | state_nxt = WR_BURST; 158 | else if (AUTO_WORK == 0) 159 | if (rd_wr_en == 2'b01 && cnt_data >= rd_wr_num - 11'd1) 160 | state_nxt = WR_OVER; 161 | else if (cnt_data >= rd_wr_num - 11'd1) 162 | state_nxt = WR_BURST; 163 | else 164 | state_nxt = WR; 165 | else 166 | if (cnt_data >= AUTO_RNUM - 1) 167 | state_nxt = WR_BURST; 168 | else 169 | state_nxt = WR; 170 | end 171 | 172 | WR_BURST: state_nxt = IDLE ; 173 | 174 | WR_OVER: 175 | begin 176 | if (!usb_n_ful_sx) 177 | state_nxt = WR_BURST; 178 | else if (rd_wr_en == 2'b01 && cnt_data >= rd_wr_num - 11'd1) 179 | state_nxt = WR_OVER; 180 | else if (cnt_data >= rd_wr_num - 11'd1) 181 | state_nxt = WR_BURST; 182 | end 183 | default:state_nxt = state; 184 | endcase 185 | end 186 | 187 | 188 | // internal signal 189 | always @ (posedge clk or negedge rst_n) 190 | begin 191 | if (!rst_n) 192 | begin 193 | wr_req <= 'd0; 194 | cnt_data <= 'd0; 195 | ts_cnt <= 'd0; 196 | end 197 | else 198 | case (state) 199 | IDLE: 200 | begin 201 | cnt_data <= 'd0; 202 | wr_req <= 'd0; 203 | if (state_nxt == RD) 204 | begin 205 | ts_cnt<= 'd0; 206 | wr_req<= 'd0; 207 | end 208 | else if (state_nxt == WR) 209 | begin 210 | wr_req<= 1'b1; 211 | end 212 | end 213 | 214 | RD_PRE: ; 215 | /* 216 | RD_OVER -> cnt_data need to be reset 217 | */ 218 | RD, WR: 219 | begin 220 | if (state_nxt == RD_OVER || state_nxt == WR_OVER) 221 | begin 222 | cnt_data <= 'd0; 223 | ts_cnt <= 'd0; 224 | end 225 | else if (ts_cnt >= TS_NUM - 1) 226 | begin 227 | cnt_data <= cnt_data + 11'd1; 228 | ts_cnt <= 'd0; 229 | end 230 | else 231 | begin 232 | ts_cnt <= ts_cnt + 8'd1; 233 | end 234 | end 235 | 236 | RD_BURST, WR_BURST: 237 | begin 238 | cnt_data <= 'd0 ; 239 | ts_cnt <= 'd0; 240 | end 241 | /*WR_OVER and RD_OVER is only exist when AUTO_WOOK == 0*/ 242 | RD_OVER, WR_OVER: 243 | begin 244 | if ((state_nxt == RD_OVER || state_nxt == WR_OVER) && cnt_data > rd_wr_num - 1) 245 | cnt_data <= 'd0; 246 | else if (ts_cnt >= TS_NUM - 1) 247 | begin 248 | cnt_data <= cnt_data + 11'd1; 249 | ts_cnt <= 'd0; 250 | end 251 | else 252 | begin 253 | ts_cnt <= ts_cnt + 8'd1; 254 | end 255 | end 256 | default:; 257 | endcase 258 | end 259 | 260 | //external signal 261 | always @ (posedge clk or negedge rst_n) 262 | begin 263 | if (!rst_n) 264 | begin 265 | tra_data<= 'd0; 266 | usb_slcs<= 'd0; 267 | usb_sloe<= 1'b1; 268 | usb_slrd<= 1'b1; 269 | usb_slwr<= 1'b1; 270 | usb_addr<= 'd0; 271 | read_data<= 'd0; 272 | output_valid<='d0; 273 | write_ready<='d0; 274 | end 275 | else 276 | case (state) 277 | IDLE: 278 | begin 279 | usb_slcs<= 'd0; 280 | output_valid<='d0; 281 | write_ready<='d0; 282 | usb_sloe<= 1'b1; 283 | usb_slrd<= 1'b1; 284 | usb_slwr<= 1'b1; 285 | if (state_nxt == RD) 286 | begin 287 | usb_addr <= 2'b0; 288 | usb_sloe <= 1'b1; 289 | usb_slrd <= 1'b1; 290 | end 291 | else if (state_nxt == WR) 292 | begin 293 | usb_addr <= 2'b10; 294 | usb_slwr <= 1'b1; 295 | end 296 | end 297 | 298 | RD_PRE: 299 | begin 300 | usb_sloe <= 1'b0; 301 | usb_slrd <= 1'b0; 302 | end 303 | 304 | /* 305 | RD_OVER -> cnt_data need to be reset 306 | */ 307 | RD, RD_OVER: 308 | begin 309 | if (ts_cnt >= TS_NUM - 1) 310 | begin 311 | usb_sloe <= 1'b0; 312 | usb_slrd <= 1'b0; 313 | read_data <= usb_data; 314 | output_valid<= 1'b1; 315 | end 316 | else 317 | begin 318 | usb_sloe <= 1'b1; 319 | usb_slrd <= 1'b1; 320 | 321 | output_valid<= 1'b0; 322 | end 323 | end 324 | /*WR_OVER and RD_OVER is only exist when AUTO_WOOK == 0*/ 325 | RD_BURST, WR_BURST: 326 | begin 327 | output_valid<= 1'b0; 328 | read_data<= usb_data; 329 | usb_sloe <= 1'b1; 330 | usb_slrd <= 1'b1; 331 | if (state_nxt == WR) 332 | usb_addr <= 2'b10; 333 | 334 | tra_data <= write_data; 335 | write_ready <= 1'b0; 336 | usb_slwr <= 1'b1; 337 | end 338 | 339 | /* cas time == TS_NUM clk*/ 340 | WR, WR_OVER: 341 | begin 342 | if (ts_cnt >= TS_NUM - 1 ) 343 | begin 344 | usb_slwr <= 1'b0; 345 | write_ready <= 1'b1; 346 | tra_data <= read_data; 347 | read_data<= read_data + 16'd1; 348 | end 349 | else 350 | begin 351 | usb_slwr <= 1'b1; 352 | end 353 | end 354 | default:usb_slcs <= 1'b1; 355 | endcase 356 | end 357 | 358 | endmodule 359 | -------------------------------------------------------------------------------- /usb_top.v: -------------------------------------------------------------------------------- 1 | module usb_top( 2 | input clk_in , 3 | input rst_n , 4 | input usb_n_ept_to , /*FIFO2 empty*/ 5 | input usb_n_ept_fr , /*FIFO4 empty*/ 6 | input usb_n_ful_sx , /*FIFO6 full */ 7 | inout [15:0] usb_data , 8 | 9 | output usb_slcs , /* chipselect */ 10 | output usb_sloe , /* data output enable */ 11 | output usb_slrd , /* read indicate */ 12 | output usb_slwr , /* write req */ 13 | output [ 1:0]usb_addr 14 | ); 15 | reg [10:0]rd_wr_num ; 16 | reg [1:0] rd_wr_en ; 17 | wire usb_is_busy; 18 | wire [15:0]read_data; 19 | reg [15:0]write_data; 20 | wire output_valid; 21 | wire write_ready; 22 | 23 | pll pll_inst( 24 | .inclk0(clk_in), 25 | .c0(clk) 26 | ); 27 | 28 | always @ (posedge clk or negedge rst_n) 29 | begin 30 | if (!rst_n) 31 | begin 32 | rd_wr_num <= 'd0; 33 | rd_wr_en <= 'd0; 34 | write_data<= 'd0; 35 | end 36 | else 37 | begin 38 | rd_wr_num <= 11'd4; 39 | 40 | if (!usb_is_busy) 41 | rd_wr_en <= 2'b10; 42 | 43 | // if (!usb_is_busy) 44 | // rd_wr_en <= 2'b01; 45 | // write_data <= write_data + 16'd1; 46 | end 47 | end 48 | 49 | usb_ctrl 50 | #( 51 | .LOOP_WORK (0) , 52 | .AUTO_WORK (0) , 53 | .TS_NUM (4) 54 | ) 55 | usb_inst 56 | ( 57 | /* FPGA main interface */ 58 | .clk (clk), 59 | .rst_n (rst_n), 60 | /* USB FIFO Indication*/ 61 | .usb_n_ept_to (usb_n_ept_to), /*FIFO2 empty*/ 62 | .usb_n_ept_fr (usb_n_ept_fr), /*FIFO4 empty*/ 63 | .usb_n_ful_sx (usb_n_ful_sx), /*FIFO6 full */ 64 | .usb_data (usb_data) , 65 | /* device ctrl */ 66 | .rd_wr_num (rd_wr_num ) , /* the number of read or write data */ 67 | .rd_wr_en (rd_wr_en ) , /* 10 -> read or 01 -> write */ 68 | .usb_is_busy (usb_is_busy ) , 69 | .read_data (read_data ) , 70 | .write_data (write_data ) , 71 | .output_valid (output_valid ) , 72 | .write_ready (write_ready ) , 73 | /* USB Ctrl Signal*/ 74 | .usb_slcs (usb_slcs), /* chipselect */ 75 | .usb_sloe (usb_sloe), /* data output enable */ 76 | .usb_slrd (usb_slrd), /* read indicate */ 77 | .usb_slwr (usb_slwr), /* write req */ 78 | .usb_addr (usb_addr) 79 | ); 80 | 81 | endmodule 82 | --------------------------------------------------------------------------------