├── README.md
├── convolution_data
    ├── conv_activation_fixed
    ├── conv_weight
    ├── image_84_84_x10
    └── max_pooling_activation_fixed
├── design_1.v
├── design_1_wrapper.v
├── diagram.png
├── main.c
├── result.png
├── start_end.v
├── test_bench
    └── simulation.v
├── top.xdc
├── top
    └── design_1_wrapper.v
└── vector_add.v


/README.md:
--------------------------------------------------------------------------------
 1 | # CNN_Accelerator(FPGA Design)
 2 | 
 3 | 　The goals of the project are to design CNN(Convolution Neural Network) accelerator using a Xilinx FPGA board and to compare performance with CPU.<br><br>
 4 | 
 5 | # Experimental Env.
 6 | * ```Zynq-7000 SoC``` <br>
 7 | * ```Xilinx Vivado 2018.2```<br><br>
 8 | 
 9 | # Design diagram
10 | <img src = "diagram.png" ><br><br>
11 | 
12 | # File hierarchy
13 | 
14 | 1. Design Source
15 |     * top(design_1_warpper.v)
16 |         * p_1: vector_add(vector_add.v)
17 |         * sf_1: start_end(start_end.v)
18 |         * design_1_i : design_1(design_1.bd)
19 |     
20 | 2. Constraints
21 |     * constrs_1
22 |         * top.xdc
23 |    
24 | 3. Simulation Sources
25 |     * sim_1
26 |         * test_bench(design_1_wrapper.v)
27 |         * top <br><br>
28 | 
29 | # Run
30 |        
31 | 　By following the design diagram and file hierarchy, you can simulate test_bench module. Execute and compare the result to typical C code(go to "Lanch SDK" menu). Then, Copy and paste the "main.c" in the C language editor window. You can see the execution time for the CNN in both FPGA and CPU.<br><br>
32 | 
33 | # Result
34 | 
35 | CPU Elapsed time: 11ms<br>
36 | FPGA Elapsed time: 0.847ms<br>
37 | 
38 | <img src = "result.png"><br>
39 | 


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1399 | 0x00,
1400 | 0x00,
1401 | 0x04,
1402 | 0x04,
1403 | 0x0c,
1404 | 0x0e,
1405 | 0x0e,
1406 | 0x0f,
1407 | 0x0e,
1408 | 0x0e,
1409 | 0x0e,
1410 | 0x0e,
1411 | 0x0e,
1412 | 0x0e,
1413 | 0x0e,
1414 | 0x12,
1415 | 0x0c,
1416 | 0x11,
1417 | 0x0d,
1418 | 0x04,
1419 | 0x00,
1420 | 0x00,
1421 | 0x00,
1422 | 0x00,
1423 | 0x00,
1424 | 0x00,
1425 | 0x00,
1426 | 0x00,
1427 | 0x00,
1428 | 0x00,
1429 | 0x00,
1430 | 0x00,
1431 | 0x00,
1432 | 0x00,
1433 | 0x00,
1434 | 0x00,
1435 | 0x00,
1436 | 0x00,
1437 | 0x00,
1438 | 0x00,
1439 | 0x00,
1440 | 0x00,
1441 | 0x00,
1442 | 0x07,
1443 | 0x07,
1444 | 0x0d,
1445 | 0x0c,
1446 | 0x0d,
1447 | 0x0e,
1448 | 0x0e,
1449 | 0x0f,
1450 | 0x0e,
1451 | 0x12,
1452 | 0x12,
1453 | 0x10,
1454 | 0x16,
1455 | 0x11,
1456 | 0x07,
1457 | 0x00,
1458 | 0x00,
1459 | 0x00,
1460 | 0x00,
1461 | 0x00,
1462 | 0x00,
1463 | 0x00,
1464 | 0x00,
1465 | 0x00,
1466 | 0x00,
1467 | 0x00,
1468 | 0x00,
1469 | 0x00,
1470 | 0x00,
1471 | 0x00,
1472 | 0x00,
1473 | 0x00,
1474 | 0x00,
1475 | 0x00,
1476 | 0x00,
1477 | 0x00,
1478 | 0x00,
1479 | 0x00,
1480 | 0x00,
1481 | 0x00,
1482 | 0x00,
1483 | 0x0a,
1484 | 0x0a,
1485 | 0x11,
1486 | 0x0e,
1487 | 0x0e,
1488 | 0x0e,
1489 | 0x0e,
1490 | 0x0c,
1491 | 0x07,
1492 | 0x07,
1493 | 0x07,
1494 | 0x02,
1495 | 0x00,
1496 | 0x00,
1497 | 0x00,
1498 | 0x00,
1499 | 0x00,
1500 | 0x00,
1501 | 0x00,
1502 | 0x00,
1503 | 0x00,
1504 | 0x00,
1505 | 0x00,
1506 | 0x00,
1507 | 0x00,
1508 | 0x00,
1509 | 0x00,
1510 | 0x00,
1511 | 0x00,
1512 | 0x00,
1513 | 0x00,
1514 | 0x00,
1515 | 0x00,
1516 | 0x00,
1517 | 0x00,
1518 | 0x00,
1519 | 0x00,
1520 | 0x00,
1521 | 0x00,
1522 | 0x00,
1523 | 0x00,
1524 | 0x08,
1525 | 0x0c,
1526 | 0x13,
1527 | 0x17,
1528 | 0x17,
1529 | 0x17,
1530 | 0x17,
1531 | 0x15,
1532 | 0x10,
1533 | 0x0b,
1534 | 0x0b,
1535 | 0x07,
1536 | 0x01,
1537 | 0x00,
1538 | 0x00,
1539 | 0x00,
1540 | 0x00,
1541 | 0x00,
1542 | 0x00,
1543 | 0x00,
1544 | 0x00,
1545 | 0x00,
1546 | 0x00,
1547 | 0x00,
1548 | 0x00,
1549 | 0x00,
1550 | 0x00,
1551 | 0x00,
1552 | 0x00,
1553 | 0x00,
1554 | 0x00,
1555 | 0x00,
1556 | 0x00,
1557 | 0x00,
1558 | 0x00,
1559 | 0x00,
1560 | 0x00,
1561 | 0x00,
1562 | 0x00,
1563 | 0x00,
1564 | 0x00,
1565 | 0x00,
1566 | 0x00,
1567 | 0x00,
1568 | 0x00,
1569 | 0x00,
1570 | 0x00,
1571 | 0x00,
1572 | 0x00,
1573 | 0x00,
1574 | 0x00,
1575 | 0x00,
1576 | 0x00,
1577 | 0x00,
1578 | 0x00,
1579 | 0x00,
1580 | 0x00,
1581 | 0x00,
1582 | 0x00,
1583 | 0x00,
1584 | 0x00,
1585 | 0x00,
1586 | 0x00,
1587 | 0x00,
1588 | 0x00,
1589 | 0x00,
1590 | 0x00,
1591 | 0x00,
1592 | 0x00,
1593 | 0x00,
1594 | 0x00,
1595 | 0x00,
1596 | 0x00,
1597 | 0x00,
1598 | 0x00,
1599 | 0x00,
1600 | 0x00,
1601 | 0x00,
1602 | 0x00,
1603 | 0x00,
1604 | 0x00,
1605 | 0x00,
1606 | 0x00,
1607 | 0x00,
1608 | 0x00,
1609 | 0x00,
1610 | 0x00,
1611 | 0x00,
1612 | 0x00,
1613 | 0x00,
1614 | 0x00,
1615 | 0x00,
1616 | 0x00,
1617 | 0x00,
1618 | 0x00,
1619 | 0x00,
1620 | 0x00,
1621 | 0x00,
1622 | 0x00,
1623 | 0x00,
1624 | 0x00,
1625 | 0x00,
1626 | 0x00,
1627 | 0x00,
1628 | 0x00,
1629 | 0x00,
1630 | 0x00,
1631 | 0x00,
1632 | 0x00,
1633 | 0x00,
1634 | 0x00,
1635 | 0x00,
1636 | 0x00,
1637 | 0x00,
1638 | 0x00,
1639 | 0x00,
1640 | 0x00,
1641 | 0x00,
1642 | 0x00,
1643 | 0x00,
1644 | 0x00,
1645 | 0x00,
1646 | 0x00,
1647 | 0x00,
1648 | 0x00,
1649 | 0x00,
1650 | 0x00,
1651 | 0x00,
1652 | 0x00,
1653 | 0x00,
1654 | 0x00,
1655 | 0x00,
1656 | 0x00,
1657 | 0x00,
1658 | 0x00,
1659 | 0x00,
1660 | 0x00,
1661 | 0x00,
1662 | 0x00,
1663 | 0x00,
1664 | 0x00,
1665 | 0x00,
1666 | 0x00,
1667 | 0x00,
1668 | 0x00,
1669 | 0x00,
1670 | 0x00,
1671 | 0x00,
1672 | 0x00,
1673 | 0x00,
1674 | 0x00,
1675 | 0x00,
1676 | 0x00,
1677 | 0x00,
1678 | 0x00,
1679 | 0x00,
1680 | 0x00,
1681 | 0x00,
1682 | 


--------------------------------------------------------------------------------
/design_1_wrapper.v:
--------------------------------------------------------------------------------
  1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
  2 | //--------------------------------------------------------------------------------
  3 | //Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
  4 | //Date        : Mon Nov 18 14:12:13 2019
  5 | //Host        : A133-05 running 64-bit major release  (build 9200)
  6 | //Command     : generate_target design_1_wrapper.bd
  7 | //Design      : design_1_wrapper
  8 | //Purpose     : IP block netlist
  9 | //--------------------------------------------------------------------------------
 10 | `timescale 1 ps / 1 ps
 11 | 
 12 | module design_1_wrapper
 13 |    (AHB_INTERFACE_0_haddr,
 14 |     AHB_INTERFACE_0_hburst,
 15 |     AHB_INTERFACE_0_hprot,
 16 |     AHB_INTERFACE_0_hrdata,
 17 |     AHB_INTERFACE_0_hready_in,
 18 |     AHB_INTERFACE_0_hready_out,
 19 |     AHB_INTERFACE_0_hresp,
 20 |     AHB_INTERFACE_0_hsize,
 21 |     AHB_INTERFACE_0_htrans,
 22 |     AHB_INTERFACE_0_hwdata,
 23 |     AHB_INTERFACE_0_hwrite,
 24 |     AHB_INTERFACE_0_sel,
 25 |     DDR_0_addr,
 26 |     DDR_0_ba,
 27 |     DDR_0_cas_n,
 28 |     DDR_0_ck_n,
 29 |     DDR_0_ck_p,
 30 |     DDR_0_cke,
 31 |     DDR_0_cs_n,
 32 |     DDR_0_dm,
 33 |     DDR_0_dq,
 34 |     DDR_0_dqs_n,
 35 |     DDR_0_dqs_p,
 36 |     DDR_0_odt,
 37 |     DDR_0_ras_n,
 38 |     DDR_0_reset_n,
 39 |     DDR_0_we_n,
 40 |     FIXED_IO_0_ddr_vrn,
 41 |     FIXED_IO_0_ddr_vrp,
 42 |     FIXED_IO_0_mio,
 43 |     FIXED_IO_0_ps_clk,
 44 |     FIXED_IO_0_ps_porb,
 45 |     FIXED_IO_0_ps_srstb,
 46 |     UART0_rxd,
 47 |     UART0_txd,
 48 |     clk,
 49 |     reset);
 50 |   input [31:0]AHB_INTERFACE_0_haddr;
 51 |   input [2:0]AHB_INTERFACE_0_hburst;
 52 |   input [3:0]AHB_INTERFACE_0_hprot;
 53 |   output [31:0]AHB_INTERFACE_0_hrdata;
 54 |   input AHB_INTERFACE_0_hready_in;
 55 |   output AHB_INTERFACE_0_hready_out;
 56 |   output AHB_INTERFACE_0_hresp;
 57 |   input [2:0]AHB_INTERFACE_0_hsize;
 58 |   input [1:0]AHB_INTERFACE_0_htrans;
 59 |   input [31:0]AHB_INTERFACE_0_hwdata;
 60 |   input AHB_INTERFACE_0_hwrite;
 61 |   input AHB_INTERFACE_0_sel;
 62 |   inout [14:0]DDR_0_addr;
 63 |   inout [2:0]DDR_0_ba;
 64 |   inout DDR_0_cas_n;
 65 |   inout DDR_0_ck_n;
 66 |   inout DDR_0_ck_p;
 67 |   inout DDR_0_cke;
 68 |   inout DDR_0_cs_n;
 69 |   inout [3:0]DDR_0_dm;
 70 |   inout [31:0]DDR_0_dq;
 71 |   inout [3:0]DDR_0_dqs_n;
 72 |   inout [3:0]DDR_0_dqs_p;
 73 |   inout DDR_0_odt;
 74 |   inout DDR_0_ras_n;
 75 |   inout DDR_0_reset_n;
 76 |   inout DDR_0_we_n;
 77 |   inout FIXED_IO_0_ddr_vrn;
 78 |   inout FIXED_IO_0_ddr_vrp;
 79 |   inout [53:0]FIXED_IO_0_mio;
 80 |   inout FIXED_IO_0_ps_clk;
 81 |   inout FIXED_IO_0_ps_porb;
 82 |   inout FIXED_IO_0_ps_srstb;
 83 |   input UART0_rxd;
 84 |   output UART0_txd;
 85 |   output clk;
 86 |   output [0:0]reset;
 87 | 
 88 |   wire [31:0]AHB_INTERFACE_0_haddr;
 89 |   wire [2:0]AHB_INTERFACE_0_hburst;
 90 |   wire [3:0]AHB_INTERFACE_0_hprot;
 91 |   wire [31:0]AHB_INTERFACE_0_hrdata;
 92 |   wire AHB_INTERFACE_0_hready_in;
 93 |   wire AHB_INTERFACE_0_hready_out;
 94 |   wire AHB_INTERFACE_0_hresp;
 95 |   wire [2:0]AHB_INTERFACE_0_hsize;
 96 |   wire [1:0]AHB_INTERFACE_0_htrans;
 97 |   wire [31:0]AHB_INTERFACE_0_hwdata;
 98 |   wire AHB_INTERFACE_0_hwrite;
 99 |   wire AHB_INTERFACE_0_sel;
100 |   wire [14:0]DDR_0_addr;
101 |   wire [2:0]DDR_0_ba;
102 |   wire DDR_0_cas_n;
103 |   wire DDR_0_ck_n;
104 |   wire DDR_0_ck_p;
105 |   wire DDR_0_cke;
106 |   wire DDR_0_cs_n;
107 |   wire [3:0]DDR_0_dm;
108 |   wire [31:0]DDR_0_dq;
109 |   wire [3:0]DDR_0_dqs_n;
110 |   wire [3:0]DDR_0_dqs_p;
111 |   wire DDR_0_odt;
112 |   wire DDR_0_ras_n;
113 |   wire DDR_0_reset_n;
114 |   wire DDR_0_we_n;
115 |   wire FIXED_IO_0_ddr_vrn;
116 |   wire FIXED_IO_0_ddr_vrp;
117 |   wire [53:0]FIXED_IO_0_mio;
118 |   wire FIXED_IO_0_ps_clk;
119 |   wire FIXED_IO_0_ps_porb;
120 |   wire FIXED_IO_0_ps_srstb;
121 |   wire UART0_rxd;
122 |   wire UART0_txd;
123 |   wire clk;
124 |   wire [0:0]reset;
125 | 
126 |   design_1 design_1_i
127 |        (.AHB_INTERFACE_0_haddr(AHB_INTERFACE_0_haddr),
128 |         .AHB_INTERFACE_0_hburst(AHB_INTERFACE_0_hburst),
129 |         .AHB_INTERFACE_0_hprot(AHB_INTERFACE_0_hprot),
130 |         .AHB_INTERFACE_0_hrdata(AHB_INTERFACE_0_hrdata),
131 |         .AHB_INTERFACE_0_hready_in(AHB_INTERFACE_0_hready_in),
132 |         .AHB_INTERFACE_0_hready_out(AHB_INTERFACE_0_hready_out),
133 |         .AHB_INTERFACE_0_hresp(AHB_INTERFACE_0_hresp),
134 |         .AHB_INTERFACE_0_hsize(AHB_INTERFACE_0_hsize),
135 |         .AHB_INTERFACE_0_htrans(AHB_INTERFACE_0_htrans),
136 |         .AHB_INTERFACE_0_hwdata(AHB_INTERFACE_0_hwdata),
137 |         .AHB_INTERFACE_0_hwrite(AHB_INTERFACE_0_hwrite),
138 |         .AHB_INTERFACE_0_sel(AHB_INTERFACE_0_sel),
139 |         .DDR_0_addr(DDR_0_addr),
140 |         .DDR_0_ba(DDR_0_ba),
141 |         .DDR_0_cas_n(DDR_0_cas_n),
142 |         .DDR_0_ck_n(DDR_0_ck_n),
143 |         .DDR_0_ck_p(DDR_0_ck_p),
144 |         .DDR_0_cke(DDR_0_cke),
145 |         .DDR_0_cs_n(DDR_0_cs_n),
146 |         .DDR_0_dm(DDR_0_dm),
147 |         .DDR_0_dq(DDR_0_dq),
148 |         .DDR_0_dqs_n(DDR_0_dqs_n),
149 |         .DDR_0_dqs_p(DDR_0_dqs_p),
150 |         .DDR_0_odt(DDR_0_odt),
151 |         .DDR_0_ras_n(DDR_0_ras_n),
152 |         .DDR_0_reset_n(DDR_0_reset_n),
153 |         .DDR_0_we_n(DDR_0_we_n),
154 |         .FIXED_IO_0_ddr_vrn(FIXED_IO_0_ddr_vrn),
155 |         .FIXED_IO_0_ddr_vrp(FIXED_IO_0_ddr_vrp),
156 |         .FIXED_IO_0_mio(FIXED_IO_0_mio),
157 |         .FIXED_IO_0_ps_clk(FIXED_IO_0_ps_clk),
158 |         .FIXED_IO_0_ps_porb(FIXED_IO_0_ps_porb),
159 |         .FIXED_IO_0_ps_srstb(FIXED_IO_0_ps_srstb),
160 |         .UART0_rxd(UART0_rxd),
161 |         .UART0_txd(UART0_txd),
162 |         .clk(clk),
163 |         .reset(reset));
164 | endmodule
165 | 


--------------------------------------------------------------------------------
/diagram.png:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/mayshin10/CNN-Accelerator/17f56cdef814c9433389baff7aaae47a19001006/diagram.png


--------------------------------------------------------------------------------
/main.c:
--------------------------------------------------------------------------------
 1 | #include <stdio.h>
 2 | #include <stdint.h>
 3 | #include <xtime_l.h>
 4 | #include "platform.h"
 5 | #include "xil_printf.h"
 6 | 
 7 | #define SIGN_MASK 0x80
 8 | 
 9 | //weight : (1,0,7)
10 | //image, activations : (1,5,2)
11 | //multiplication & accumulation tmp result : (1,8,7)
12 | //all weight, image, activations, result use 2's complement
13 | 
14 | int main() {
15 | 
16 | 	init_platform();
17 | 
18 | 	uint8_t input_image[7056] = {
19 | #include "image_84_84_x10"
20 | 	};
21 | 	uint8_t conv_weight[9] = {
22 | #include "conv_weight"
23 | 	};
24 | 
25 | 	uint8_t conv_activation[6724] = {
26 | #include "conv_activation_fixed"
27 | 	};
28 | 
29 | 	uint8_t max_pooling_activation[1681] = {
30 | #include "max_pooling_activation_fixed"
31 | 	};
32 | 
33 | 	uint32_t *start_sig = (uint32_t *) 0x50000000;
34 | 	uint32_t *end_sig = (uint32_t *) 0x50000004;
35 | 
36 | 	uint8_t *input_image_fpga = (uint8_t *) 0x40000000;
37 | 	uint8_t *conv_weight_fpga = (uint8_t *) 0x40010000;
38 | 	uint8_t *activation_fpga = (uint8_t *) 0x40020000;
39 | 
40 | 	XTime start, end;
41 | 
42 | 	print("\n@@@@@@ Accel Start @@@@@@\n");
43 | 	//Calculation Start
44 | 	XTime_GetTime(&start);
45 | 
46 | 	memcpy(input_image_fpga, input_image, 7056*sizeof(uint8_t));
47 | 	memcpy(conv_weight_fpga, conv_weight, 9*sizeof(uint8_t));
48 | 
49 | 	start_sig[0] = 0x01020304;
50 | 
51 | 	//Wait for Finishing Sig
52 | 	while(1) {
53 | 		if (end_sig[0] == 0x04030201)
54 | 			break;
55 | 	}
56 | 
57 | 	//Calculation End
58 | 	XTime_GetTime(&end);
59 | 	print("@@@@@@ Accel Finish @@@@@@\n\n");
60 | 
61 | 	int i;
62 | 	//Correctness Check
63 | 	for (i=0; i<1681; i++)
64 | 	{
65 | 		uint8_t act = max_pooling_activation[i];
66 | 		uint8_t lower_bound;
67 | 		uint8_t upper_bound = act +1;
68 | 		if ( act == 0 )
69 | 			lower_bound = act;
70 | 		else
71 | 			lower_bound = act -1;
72 | 
73 | 		if ( activation_fpga[i] & 0x80 != 0 )
74 | 			break;
75 | 		if ( activation_fpga[i] < lower_bound )
76 | 			break;
77 | 		if ( upper_bound < activation_fpga[i] )
78 | 			break;
79 | 	}
80 | 
81 | 	if ( i == SIZE ) {
82 | 		print("@@@@@@ CORRECT @@@@@@\n");
83 | 
84 | 		printf("FPGA:\t%.3lf ms\n", (double)(end-start)/(COUNTS_PER_SECOND/1000));
85 | 	}
86 | 	else {
87 | 		print("@@@@@@ FAIL @@@@@@");
88 | 
89 | 		printf("Index %d : Activation should be %x, but %x is calculated\n", i, max_pooling_activation[i], activation_fpga[i]);
90 | 	}
91 | 
92 | 
93 | 	cleanup_platform();
94 | 	return 0;
95 | }
96 | 


--------------------------------------------------------------------------------
/result.png:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/mayshin10/CNN-Accelerator/17f56cdef814c9433389baff7aaae47a19001006/result.png


--------------------------------------------------------------------------------
/start_end.v:
--------------------------------------------------------------------------------
  1 | module start_end(
  2 |   output reg [31:0]AHB_INTERFACE_0_haddr,
  3 |   output reg [2:0]AHB_INTERFACE_0_hburst,
  4 |   output reg [3:0]AHB_INTERFACE_0_hprot,
  5 |   input [31:0]AHB_INTERFACE_0_hrdata,
  6 |   output reg AHB_INTERFACE_0_hready_in,
  7 |   input AHB_INTERFACE_0_hready_out,
  8 |   input AHB_INTERFACE_0_hresp,
  9 |   output reg [2:0]AHB_INTERFACE_0_hsize,
 10 |   output reg [1:0]AHB_INTERFACE_0_htrans,
 11 |   output reg [31:0]AHB_INTERFACE_0_hwdata,
 12 |   output reg AHB_INTERFACE_0_hwrite,
 13 |   output reg AHB_INTERFACE_0_sel,
 14 |   output reg start,
 15 |   input finish,  
 16 |   input clk,
 17 |   input reset
 18 | );
 19 | 
 20 | reg [3:0] state;
 21 | wire [31:0] start_code;
 22 | assign start_code = 32'h01020304;
 23 | wire [31:0] finish_code;
 24 | assign finish_code = 32'h04030201;
 25 | reg [31:0] read_data_reg;
 26 | always @(posedge clk) begin
 27 |     if ( !reset ) begin
 28 |         AHB_INTERFACE_0_haddr <= 0;
 29 |         AHB_INTERFACE_0_hburst <= 0;
 30 |         AHB_INTERFACE_0_hprot <= 0;
 31 |         AHB_INTERFACE_0_hready_in <= 0;
 32 |         AHB_INTERFACE_0_hsize <= 0;
 33 |         AHB_INTERFACE_0_htrans <= 0;
 34 |         AHB_INTERFACE_0_hwdata <= 0;
 35 |         AHB_INTERFACE_0_hwrite <= 0;
 36 |         AHB_INTERFACE_0_sel <= 0;        
 37 |         start <= 0;
 38 |         state <= 0;
 39 |     end
 40 |     else begin
 41 |     case(state)
 42 |         4'd0: begin // try to read
 43 |             if ( AHB_INTERFACE_0_hready_out == 1 ) begin
 44 |                 AHB_INTERFACE_0_htrans <= 2'b10;
 45 |                 AHB_INTERFACE_0_haddr <= 32'h5000_0000; // start code position
 46 |                 AHB_INTERFACE_0_hburst <= 0;
 47 |                 AHB_INTERFACE_0_hsize <= 3'b010;
 48 |                 AHB_INTERFACE_0_hready_in <= 1;
 49 |                 AHB_INTERFACE_0_sel <= 1;
 50 |                 AHB_INTERFACE_0_hprot <= 1;
 51 |                 
 52 |                 state <= 4'd1;                
 53 |             end
 54 |         end
 55 |         4'd1: begin // read the data
 56 |             if ( AHB_INTERFACE_0_hready_out == 1 ) begin
 57 |                 read_data_reg <= AHB_INTERFACE_0_hrdata;
 58 |                 AHB_INTERFACE_0_sel <= 0;
 59 |                 AHB_INTERFACE_0_hprot <= 0;
 60 |                 AHB_INTERFACE_0_hready_in <= 1;
 61 |                 
 62 |                 state <= 4'd2;
 63 |             end
 64 |             else begin
 65 |                 AHB_INTERFACE_0_hready_in <= 0;
 66 |             end
 67 |             AHB_INTERFACE_0_htrans <= 0;
 68 |         end
 69 |         4'd2: begin // compare the data to start code
 70 |             if ( read_data_reg == start_code ) begin
 71 |                 start <= 1;
 72 |                 state <= 4'd3;
 73 |             end
 74 |             else begin
 75 |                 state <= 4'd0;
 76 |             end
 77 |         end
 78 |         4'd3: begin // wait for finish signal from processing module
 79 |             if ( finish == 1 ) begin
 80 |                 state <= 4'd4;
 81 |             end
 82 |             AHB_INTERFACE_0_haddr <= 0;
 83 |             AHB_INTERFACE_0_hburst <= 0;
 84 |             AHB_INTERFACE_0_hprot <= 0;
 85 |             AHB_INTERFACE_0_hready_in <= 0;
 86 |             AHB_INTERFACE_0_hsize <= 0;
 87 |             AHB_INTERFACE_0_htrans <= 0;
 88 |             AHB_INTERFACE_0_hwdata <= 0;
 89 |             AHB_INTERFACE_0_hwrite <= 0;
 90 |             AHB_INTERFACE_0_sel <= 0;
 91 |         end
 92 |         4'd4: begin // write finish code
 93 |             if ( AHB_INTERFACE_0_hready_out == 1 && AHB_INTERFACE_0_hresp == 0) begin
 94 |                 AHB_INTERFACE_0_htrans <= 2'b10;
 95 |                 AHB_INTERFACE_0_haddr <= 32'h5000_0004;
 96 |                 AHB_INTERFACE_0_hburst <= 0;
 97 |                 AHB_INTERFACE_0_hsize <= 3'b010; //Byte
 98 |                 AHB_INTERFACE_0_hready_in <= 1;
 99 |                 AHB_INTERFACE_0_sel <= 1;
100 |                 AHB_INTERFACE_0_hprot <= 9;
101 |                 AHB_INTERFACE_0_hwdata <= finish_code;
102 |                 AHB_INTERFACE_0_hwrite <= 1;
103 |                 state <= 4'd5;
104 |             end
105 |         end
106 |         4'd5: begin
107 |             AHB_INTERFACE_0_htrans <= 0;
108 |             AHB_INTERFACE_0_hready_in <= 0;
109 |             state <= 4'd6;
110 |         end
111 |         4'd6: begin
112 |             if ( AHB_INTERFACE_0_hready_out == 0 && AHB_INTERFACE_0_hresp == 0) begin
113 |                 AHB_INTERFACE_0_sel <= 0;
114 |                 AHB_INTERFACE_0_hprot <= 0;
115 |                 AHB_INTERFACE_0_hwdata <= 0;
116 |                 AHB_INTERFACE_0_hwrite <= 0;
117 |                 AHB_INTERFACE_0_hready_in <= 1;
118 |                 state <= 4'd7;
119 |             end
120 |         end
121 |         default: begin
122 |         AHB_INTERFACE_0_haddr <= 0;
123 |         AHB_INTERFACE_0_hburst <= 0;
124 |         AHB_INTERFACE_0_hprot <= 0;
125 |         AHB_INTERFACE_0_hready_in <= 0;
126 |         AHB_INTERFACE_0_hsize <= 0;
127 |         AHB_INTERFACE_0_htrans <= 0;
128 |         AHB_INTERFACE_0_hwdata <= 0;
129 |         AHB_INTERFACE_0_hwrite <= 0;
130 |         AHB_INTERFACE_0_sel <= 0;
131 |         end
132 |         
133 |     endcase
134 |     end
135 | end
136 | endmodule


--------------------------------------------------------------------------------
/top.xdc:
--------------------------------------------------------------------------------
 1 | set_property IOSTANDARD "LVCMOS33" [get_ports "UART0_txd"]
 2 | set_property IOSTANDARD "LVCMOS33" [get_ports "UART0_rxd"]
 3 | set_property PACKAGE_PIN "U5" [get_ports "UART0_txd"]
 4 | set_property PACKAGE_PIN "U6" [get_ports "UART0_rxd"]
 5 | 
 6 | set_property IOSTANDARD "LVCMOS33" [get_ports "led[*]"] 
 7 | set_property PACKAGE_PIN "T16" [get_ports "led[7]"]
 8 | set_property PACKAGE_PIN "T17" [get_ports "led[6]"]
 9 | set_property PACKAGE_PIN "R19" [get_ports "led[5]"]
10 | set_property PACKAGE_PIN "T19" [get_ports "led[4]"]
11 | set_property PACKAGE_PIN "R18" [get_ports "led[3]"]
12 | set_property PACKAGE_PIN "T18" [get_ports "led[2]"]
13 | set_property PACKAGE_PIN "P16" [get_ports "led[1]"]
14 | set_property PACKAGE_PIN "R16" [get_ports "led[0]"]
15 | 
16 | 
17 | set_property IOSTANDARD "LVCMOS33" [get_ports "push_n[*]"] 
18 | set_property PACKAGE_PIN "AA19" [get_ports "push_n[2]"]
19 | set_property PACKAGE_PIN "Y19" [get_ports "push_n[1]"]
20 | set_property PACKAGE_PIN "AA18" [get_ports "push_n[0]"]


--------------------------------------------------------------------------------
/top/design_1_wrapper.v:
--------------------------------------------------------------------------------
  1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
  2 | //--------------------------------------------------------------------------------
  3 | //Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
  4 | //Date        : Thu Apr 18 21:10:19 2019
  5 | //Host        : changsu-desktop running 64-bit Ubuntu 16.04.6 LTS
  6 | //Command     : generate_target design_1_wrapper.bd
  7 | //Design      : design_1_wrapper
  8 | //Purpose     : IP block netlist
  9 | //--------------------------------------------------------------------------------
 10 | `timescale 1 ps / 1 ps
 11 | 
 12 | module top
 13 |    (
 14 |     DDR_addr,
 15 |     DDR_ba,
 16 |     DDR_cas_n,
 17 |     DDR_ck_n,
 18 |     DDR_ck_p,
 19 |     DDR_cke,
 20 |     DDR_cs_n,
 21 |     DDR_dm,
 22 |     DDR_dq,
 23 |     DDR_dqs_n,
 24 |     DDR_dqs_p,
 25 |     DDR_odt,
 26 |     DDR_ras_n,
 27 |     DDR_reset_n,
 28 |     DDR_we_n,
 29 |     FIXED_IO_ddr_vrn,
 30 |     FIXED_IO_ddr_vrp,
 31 |     FIXED_IO_mio,
 32 |     FIXED_IO_ps_clk,
 33 |     FIXED_IO_ps_porb,
 34 |     FIXED_IO_ps_srstb,
 35 |     UART0_rxd,
 36 |     UART0_txd,
 37 |     led,
 38 |     push_n);
 39 | 
 40 | 
 41 |   inout [14:0]DDR_addr;
 42 |   inout [2:0]DDR_ba;
 43 |   inout DDR_cas_n;
 44 |   inout DDR_ck_n;
 45 |   inout DDR_ck_p;
 46 |   inout DDR_cke;
 47 |   inout DDR_cs_n;
 48 |   inout [3:0]DDR_dm;
 49 |   inout [31:0]DDR_dq;
 50 |   inout [3:0]DDR_dqs_n;
 51 |   inout [3:0]DDR_dqs_p;
 52 |   inout DDR_odt;
 53 |   inout DDR_ras_n;
 54 |   inout DDR_reset_n;
 55 |   inout DDR_we_n;
 56 |   inout FIXED_IO_ddr_vrn;
 57 |   inout FIXED_IO_ddr_vrp;
 58 |   inout [53:0]FIXED_IO_mio;
 59 |   inout FIXED_IO_ps_clk;
 60 |   inout FIXED_IO_ps_porb;
 61 |   inout FIXED_IO_ps_srstb;
 62 |   input UART0_rxd;
 63 |   output UART0_txd;
 64 |   output [7:0] led;
 65 |   input [2:0] push_n;
 66 |   
 67 |   wire [2:0] push;
 68 |   assign push = ~push_n;
 69 | 
 70 |   wire [14:0]DDR_addr;
 71 |   wire [2:0]DDR_ba;
 72 |   wire DDR_cas_n;
 73 |   wire DDR_ck_n;
 74 |   wire DDR_ck_p;
 75 |   wire DDR_cke;
 76 |   wire DDR_cs_n;
 77 |   wire [3:0]DDR_dm;
 78 |   wire [31:0]DDR_dq;
 79 |   wire [3:0]DDR_dqs_n;
 80 |   wire [3:0]DDR_dqs_p;
 81 |   wire DDR_odt;
 82 |   wire DDR_ras_n;
 83 |   wire DDR_reset_n;
 84 |   wire DDR_we_n;
 85 |   wire FIXED_IO_ddr_vrn;
 86 |   wire FIXED_IO_ddr_vrp;
 87 |   wire [53:0]FIXED_IO_mio;
 88 |   wire FIXED_IO_ps_clk;
 89 |   wire FIXED_IO_ps_porb;
 90 |   wire FIXED_IO_ps_srstb;
 91 |   wire UART0_rxd;
 92 |   wire UART0_txd;
 93 |   
 94 |   wire clk;
 95 |   wire [0:0]reset;
 96 |   
 97 |   wire [31:0]AHB_INTERFACE_0_hrdata;
 98 |   wire AHB_INTERFACE_0_hready_out;
 99 |   wire AHB_INTERFACE_0_hresp;
100 | 
101 |   wire [31:0]AHB_INTERFACE_0_haddr_p;
102 |   wire [2:0]AHB_INTERFACE_0_hburst_p;
103 |   wire [3:0]AHB_INTERFACE_0_hprot_p;
104 |   wire AHB_INTERFACE_0_hready_in_p;
105 |   wire [2:0]AHB_INTERFACE_0_hsize_p;
106 |   wire [1:0]AHB_INTERFACE_0_htrans_p;
107 |   wire [31:0]AHB_INTERFACE_0_hwdata_p;
108 |   wire AHB_INTERFACE_0_hwrite_p;
109 |   wire AHB_INTERFACE_0_sel_p;
110 |   
111 |   wire [31:0]AHB_INTERFACE_0_haddr_sf;
112 |   wire [2:0]AHB_INTERFACE_0_hburst_sf;
113 |   wire [3:0]AHB_INTERFACE_0_hprot_sf;
114 |   wire AHB_INTERFACE_0_hready_in_sf;
115 |   wire [2:0]AHB_INTERFACE_0_hsize_sf;
116 |   wire [1:0]AHB_INTERFACE_0_htrans_sf;
117 |   wire [31:0]AHB_INTERFACE_0_hwdata_sf;
118 |   wire AHB_INTERFACE_0_hwrite_sf;
119 |   wire AHB_INTERFACE_0_sel_sf;
120 |   
121 |   wire [31:0]AHB_INTERFACE_0_haddr;
122 |   wire [2:0]AHB_INTERFACE_0_hburst;
123 |   wire [3:0]AHB_INTERFACE_0_hprot;
124 |   wire AHB_INTERFACE_0_hready_in;
125 |   wire [2:0]AHB_INTERFACE_0_hsize;
126 |   wire [1:0]AHB_INTERFACE_0_htrans;
127 |   wire [31:0]AHB_INTERFACE_0_hwdata;
128 |   wire AHB_INTERFACE_0_hwrite;
129 |   wire AHB_INTERFACE_0_sel;
130 |   
131 |   assign AHB_INTERFACE_0_haddr = AHB_INTERFACE_0_haddr_p | AHB_INTERFACE_0_haddr_sf;
132 |   assign AHB_INTERFACE_0_hburst = AHB_INTERFACE_0_hburst_p | AHB_INTERFACE_0_hburst_sf;
133 |   assign AHB_INTERFACE_0_hprot = AHB_INTERFACE_0_hprot_p | AHB_INTERFACE_0_hprot_sf;
134 |   assign AHB_INTERFACE_0_hready_in = AHB_INTERFACE_0_hready_in_p | AHB_INTERFACE_0_hready_in_sf;
135 |   assign AHB_INTERFACE_0_hsize = AHB_INTERFACE_0_hsize_p | AHB_INTERFACE_0_hsize_sf;
136 |   assign AHB_INTERFACE_0_htrans = AHB_INTERFACE_0_htrans_p | AHB_INTERFACE_0_htrans_sf;
137 |   assign AHB_INTERFACE_0_hwdata = AHB_INTERFACE_0_hwdata_p | AHB_INTERFACE_0_hwdata_sf;
138 |   assign AHB_INTERFACE_0_hwrite = AHB_INTERFACE_0_hwrite_p | AHB_INTERFACE_0_hwrite_sf;
139 |   assign AHB_INTERFACE_0_sel = AHB_INTERFACE_0_sel_p | AHB_INTERFACE_0_sel_sf;
140 |   
141 |   wire [3:0] state_test;
142 |   wire start;
143 |   wire finish;
144 |   
145 |   assign led[7] = start;
146 |   assign led[6] = finish;
147 | 
148 |   vector_add p_1 (
149 |         .AHB_INTERFACE_0_haddr(AHB_INTERFACE_0_haddr_p),
150 |         .AHB_INTERFACE_0_hburst(AHB_INTERFACE_0_hburst_p),
151 |         .AHB_INTERFACE_0_hprot(AHB_INTERFACE_0_hprot_p),
152 |         .AHB_INTERFACE_0_hrdata(AHB_INTERFACE_0_hrdata),//
153 |         .AHB_INTERFACE_0_hready_in(AHB_INTERFACE_0_hready_in_p),
154 |         .AHB_INTERFACE_0_hready_out(AHB_INTERFACE_0_hready_out),//
155 |         .AHB_INTERFACE_0_hresp(AHB_INTERFACE_0_hresp),//
156 |         .AHB_INTERFACE_0_hsize(AHB_INTERFACE_0_hsize_p),
157 |         .AHB_INTERFACE_0_htrans(AHB_INTERFACE_0_htrans_p),
158 |         .AHB_INTERFACE_0_hwdata(AHB_INTERFACE_0_hwdata_p),
159 |         .AHB_INTERFACE_0_hwrite(AHB_INTERFACE_0_hwrite_p),
160 |         .AHB_INTERFACE_0_sel(AHB_INTERFACE_0_sel_p),
161 |         .start(start),
162 |         .finish(finish),
163 |         .clk(clk),
164 |         .reset(reset),
165 |         .state_test(state_test)
166 |     );
167 | 
168 |     start_end sf_1 (
169 |         .AHB_INTERFACE_0_haddr(AHB_INTERFACE_0_haddr_sf),
170 |         .AHB_INTERFACE_0_hburst(AHB_INTERFACE_0_hburst_sf),
171 |         .AHB_INTERFACE_0_hprot(AHB_INTERFACE_0_hprot_sf),
172 |         .AHB_INTERFACE_0_hrdata(AHB_INTERFACE_0_hrdata),//
173 |         .AHB_INTERFACE_0_hready_in(AHB_INTERFACE_0_hready_in_sf),
174 |         .AHB_INTERFACE_0_hready_out(AHB_INTERFACE_0_hready_out),//
175 |         .AHB_INTERFACE_0_hresp(AHB_INTERFACE_0_hresp),//
176 |         .AHB_INTERFACE_0_hsize(AHB_INTERFACE_0_hsize_sf),
177 |         .AHB_INTERFACE_0_htrans(AHB_INTERFACE_0_htrans_sf),
178 |         .AHB_INTERFACE_0_hwdata(AHB_INTERFACE_0_hwdata_sf),
179 |         .AHB_INTERFACE_0_hwrite(AHB_INTERFACE_0_hwrite_sf),
180 |         .AHB_INTERFACE_0_sel(AHB_INTERFACE_0_sel_sf),
181 |         .start(start),
182 |         .finish(finish),
183 |         .clk(clk),
184 |         .reset(reset)
185 |     );
186 | 
187 |   design_1 design_1_i
188 |        (.AHB_INTERFACE_0_haddr(AHB_INTERFACE_0_haddr),
189 |         .AHB_INTERFACE_0_hburst(AHB_INTERFACE_0_hburst),
190 |         .AHB_INTERFACE_0_hprot(AHB_INTERFACE_0_hprot),
191 |         .AHB_INTERFACE_0_hrdata(AHB_INTERFACE_0_hrdata),
192 |         .AHB_INTERFACE_0_hready_in(AHB_INTERFACE_0_hready_in),
193 |         .AHB_INTERFACE_0_hready_out(AHB_INTERFACE_0_hready_out),
194 |         .AHB_INTERFACE_0_hresp(AHB_INTERFACE_0_hresp),
195 |         .AHB_INTERFACE_0_hsize(AHB_INTERFACE_0_hsize),
196 |         .AHB_INTERFACE_0_htrans(AHB_INTERFACE_0_htrans),
197 |         .AHB_INTERFACE_0_hwdata(AHB_INTERFACE_0_hwdata),
198 |         .AHB_INTERFACE_0_hwrite(AHB_INTERFACE_0_hwrite),
199 |         .AHB_INTERFACE_0_sel(AHB_INTERFACE_0_sel),
200 |         .DDR_0_addr(DDR_addr),
201 |         .DDR_0_ba(DDR_ba),
202 |         .DDR_0_cas_n(DDR_cas_n),
203 |         .DDR_0_ck_n(DDR_ck_n),
204 |         .DDR_0_ck_p(DDR_ck_p),
205 |         .DDR_0_cke(DDR_cke),
206 |         .DDR_0_cs_n(DDR_cs_n),
207 |         .DDR_0_dm(DDR_dm),
208 |         .DDR_0_dq(DDR_dq),
209 |         .DDR_0_dqs_n(DDR_dqs_n),
210 |         .DDR_0_dqs_p(DDR_dqs_p),
211 |         .DDR_0_odt(DDR_odt),
212 |         .DDR_0_ras_n(DDR_ras_n),
213 |         .DDR_0_reset_n(DDR_reset_n),
214 |         .DDR_0_we_n(DDR_we_n),
215 |         .FIXED_IO_0_ddr_vrn(FIXED_IO_ddr_vrn),
216 |         .FIXED_IO_0_ddr_vrp(FIXED_IO_ddr_vrp),
217 |         .FIXED_IO_0_mio(FIXED_IO_mio),
218 |         .FIXED_IO_0_ps_clk(FIXED_IO_ps_clk),
219 |         .FIXED_IO_0_ps_porb(FIXED_IO_ps_porb),
220 |         .FIXED_IO_0_ps_srstb(FIXED_IO_ps_srstb),
221 |         .UART0_rxd(UART0_rxd),
222 |         .UART0_txd(UART0_txd),
223 |         .clk(clk),
224 |         .reset(reset));
225 | endmodule
226 | 


--------------------------------------------------------------------------------
/vector_add.v:
--------------------------------------------------------------------------------
  1 | module vector_add
  2 | (
  3 | output reg [31:0]AHB_INTERFACE_0_haddr,     //indicate read/write address
  4 | output reg [2:0]AHB_INTERFACE_0_hburst,     
  5 | output reg [3:0]AHB_INTERFACE_0_hprot,      
  6 | input [31:0]AHB_INTERFACE_0_hrdata,         //datastream you read
  7 | output reg AHB_INTERFACE_0_hready_in,       //indicate whether the slave are ready
  8 | input AHB_INTERFACE_0_hready_out,           //indicate whether the master are ready
  9 | input AHB_INTERFACE_0_hresp,                
 10 | output reg [2:0]AHB_INTERFACE_0_hsize,      //we use 010 value that indicate 4byte word size
 11 | output reg [1:0]AHB_INTERFACE_0_htrans,     
 12 | output reg [31:0]AHB_INTERFACE_0_hwdata,    //datastream you write
 13 | output reg AHB_INTERFACE_0_hwrite,          
 14 | output reg AHB_INTERFACE_0_sel,
 15 | input start,                                //start when this value go to 1 from 0.
 16 | output reg finish,                          //put finish to 1 when this process is over
 17 | input clk,  
 18 | input reset,
 19 | output [6:0] state_test                      //to check the state number when we run simulation
 20 | );
 21 | 
 22 | reg [6:0] state;                             // 7bit state. maximum state is 127
 23 | assign state_test = state;                   
 24 | reg [31:0] address_offset;                   // it is set to read data phase
 25 | reg [31:0] address_offset_max;               // it is set to write data phase
 26 | reg [1:0] max_cnt;                           // count for max_pooling
 27 | reg col;                                     // check whether you read first column or not
 28 | reg row;                                     // check whether you read odd row or not
 29 | reg [7:0] max1;                              // to store max pooling result in first order of 4 byte in write data.
 30 | reg [7:0] max2;                              // to store max pooling result in second order of 4 byte in write data.
 31 | reg [7:0] max3;                              // to store max pooling result in third order of 4 byte in write data.
 32 | reg [7:0] max4;                              // to store max pooling result in last order of 4 byte in write data.
 33 | reg [7:0] temp;                              // to store max pooling result in out of order of 4 byte in write data, temporarily
 34 | 
 35 | reg [671:0] databus_1;                       //the first databus
 36 | reg [671:0] databus_2;                       //the second databus
 37 | reg [671:0] databus_3;                       //the third databus
 38 | 
 39 | reg signed [7:0] w1;                         // 16 of weigh value 
 40 | reg signed [7:0] w2;
 41 | reg signed [7:0] w3;
 42 | reg signed [7:0] w4;
 43 | reg signed [7:0] w5;
 44 | reg signed [7:0] w6;
 45 | reg signed [7:0] w7;
 46 | reg signed [7:0] w8;
 47 | reg signed [7:0] w9;
 48 | reg signed [7:0] im1;                         // 24 of image value
 49 | reg signed [7:0] im2;
 50 | reg signed [7:0] im3;
 51 | reg signed [7:0] im4;
 52 | reg signed [7:0] im5;
 53 | reg signed [7:0] im6;
 54 | reg signed [7:0] im7;
 55 | reg signed [7:0] im8;
 56 | reg signed [7:0] im9;
 57 | reg signed [7:0] im10;
 58 | reg signed [7:0] im11;
 59 | reg signed [7:0] im12;
 60 | reg signed [7:0] im13;
 61 | reg signed [7:0] im14;
 62 | reg signed [7:0] im15;
 63 | reg signed [7:0] im16;
 64 | reg signed [7:0] im17;
 65 | reg signed [7:0] im18;
 66 | reg signed [7:0] im19;
 67 | reg signed [7:0] im20;
 68 | reg signed [7:0] im21;
 69 | reg signed [7:0] im22;
 70 | reg signed [7:0] im23;
 71 | reg signed [7:0] im24;
 72 | 
 73 | wire signed [7:0] temp1;                //8 convolution value
 74 | wire signed [7:0] temp2;
 75 | wire signed [7:0] temp3;
 76 | wire signed [7:0] temp4;
 77 | wire [7:0] temp5;
 78 | wire [7:0] temp6;
 79 | wire [7:0] temp7;
 80 | wire [7:0] temp8;
 81 | 
 82 | // calculate convolution in wire.
 83 | 
 84 | assign temp1 =((im1*w1 + im2*w2 + im3*w3 + im5*w4 + im6*w5 + im7*w6 + im9*w7 + im10*w8 + im11*w9) >0 ?  (((im1*w1 + im2*w2 + im3*w3 + im5*w4 + im6*w5 + im7*w6 + im9*w7 + im10*w8 + im11*w9) >> 7)&255) : 0); 
 85 | assign temp2 =((im2*w1 + im3*w2 + im4*w3 + im6*w4 + im7*w5 + im8*w6 + im10*w7 + im11*w8 + im12*w9) >0 ?  (((im2*w1 + im3*w2 + im4*w3 + im6*w4 + im7*w5 + im8*w6 + im10*w7 + im11*w8 + im12*w9) >> 7)&255) : 0); 
 86 | assign temp3 =((im5*w1 + im6*w2 + im7*w3 + im9*w4 + im10*w5 + im11*w6 + im13*w7 + im14*w8 + im15*w9) >0 ?  (((im5*w1 + im6*w2 + im7*w3 + im9*w4 + im10*w5 + im11*w6 + im13*w7 + im14*w8 + im15*w9)>> 7)&255) : 0); 
 87 | assign temp4 =((im6*w1 + im7*w2 + im8*w3 + im10*w4 + im11*w5 + im12*w6 + im14*w7 + im15*w8 + im16*w9) >0 ?  (((im6*w1 + im7*w2 + im8*w3 + im10*w4 + im11*w5 + im12*w6 + im14*w7 + im15*w8 + im16*w9) >> 7)&255) : 0);
 88 | 
 89 | assign temp5 =((im17*w1 + im18*w2 + im1*w3 + im19*w4 + im20*w5 + im5*w6 + im21*w7 + im22*w8 + im9*w9) >0 ?  (((im17*w1 + im18*w2 + im1*w3 + im19*w4 + im20*w5 + im5*w6 + im21*w7 + im22*w8 + im9*w9) >> 7)&255) : 0); 
 90 | assign temp6 =((im18*w1 + im1*w2 + im2*w3 + im20*w4 + im5*w5 + im6*w6 + im22*w7 + im9*w8 + im10*w9) >0 ?  (((im18*w1 + im1*w2 + im2*w3 + im20*w4 + im5*w5 + im6*w6 + im22*w7 + im9*w8 + im10*w9) >> 7)&255) : 0); 
 91 | assign temp7 =((im19*w1 + im20*w2 + im5*w3 + im21*w4 + im22*w5 + im9*w6 + im23*w7 + im24*w8 + im13*w9) >0 ?  (((im19*w1 + im20*w2 + im5*w3 + im21*w4 + im22*w5 + im9*w6 + im23*w7 + im24*w8 + im13*w9) >> 7)&255) : 0); 
 92 | assign temp8 =((im20*w1 + im5*w2 + im6*w3 + im22*w4 + im9*w5 + im10*w6 + im24*w7 + im13*w8 + im14*w9) >0 ?  (((im20*w1 + im5*w2 + im6*w3 + im22*w4 + im9*w5 + im10*w6 + im24*w7 + im13*w8 + im14*w9) >> 7)&255) : 0);
 93 | 
 94 | 
 95 | always @(posedge clk) begin
 96 | 
 97 | if ( !reset ) begin
 98 | //initialization all registor
 99 | AHB_INTERFACE_0_haddr <= 0;
100 | AHB_INTERFACE_0_hburst <= 0;
101 | AHB_INTERFACE_0_hprot <= 0;
102 | AHB_INTERFACE_0_hready_in <= 0;
103 | AHB_INTERFACE_0_hsize <= 0;
104 | AHB_INTERFACE_0_htrans <= 0;
105 | AHB_INTERFACE_0_hwdata <= 0;
106 | AHB_INTERFACE_0_hwrite <= 0;
107 | AHB_INTERFACE_0_sel <= 0;
108 | address_offset <= 0;
109 | address_offset_max <= 0;
110 | finish <= 0;
111 | state <= 0;
112 | max_cnt <= 0;
113 | col<= 0;
114 | row <=0;
115 | max1<= 0;
116 | max2<= 0;
117 | max3<= 0;
118 | max4<= 0;
119 | temp<= 0;
120 | databus_1 <=0;
121 | databus_2 <=0;
122 | databus_3 <=0;
123 | w1 <= 0;
124 | w2 <= 0;
125 | w3 <= 0;
126 | w4 <= 0;
127 | w5 <= 0;
128 | w6 <= 0;
129 | w7 <= 0;
130 | w8 <= 0;
131 | w9 <= 0;
132 | im1 <= 0;
133 | im2 <= 0;
134 | im3 <= 0;
135 | im4 <= 0;
136 | im5 <= 0;
137 | im6 <= 0;
138 | im7 <= 0;
139 | im8 <= 0;
140 | im9 <= 0;
141 | im10 <= 0;
142 | im11 <= 0;
143 | im12 <= 0;
144 | im13 <= 0;
145 | im14 <= 0;
146 | im15 <= 0;
147 | im16 <= 0;
148 | im17 <= 0;
149 | im18 <= 0;
150 | im19 <= 0;
151 | im20 <= 0;
152 | im21 <= 0;
153 | im22 <= 0;
154 | im23 <= 0;
155 | im24 <= 0;
156 | end
157 | else begin
158 | case(state)
159 | //loop1
160 | 7'd0: begin
161 | if ( start )
162 |     state <= 7'd1;
163 | end
164 | 
165 | 7'd1: begin //try to read first 4 weight value
166 | if ( (AHB_INTERFACE_0_hready_out == 1) ) begin
167 |     AHB_INTERFACE_0_htrans <= 2'b10;
168 |     AHB_INTERFACE_0_haddr <= 32'h4001_0000;
169 |     AHB_INTERFACE_0_hburst <= 0;
170 |     AHB_INTERFACE_0_hsize <= 3'b010;
171 |     AHB_INTERFACE_0_hready_in <= 1;
172 |     AHB_INTERFACE_0_sel <= 1;
173 |     AHB_INTERFACE_0_hprot <= 1;
174 |    
175 |     state <= 7'd2;                
176 | 
177 | end
178 | end
179 | 
180 | 7'd2: begin
181 | AHB_INTERFACE_0_hready_in <= 0;
182 | AHB_INTERFACE_0_htrans <= 0;
183 | state <= 7'd3;    
184 | end
185 | 
186 | 7'd3: begin //write weight value in my registor
187 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
188 |     w1 <= AHB_INTERFACE_0_hrdata[7:0];
189 |     w2 <= AHB_INTERFACE_0_hrdata[15:8];
190 |     w3 <= AHB_INTERFACE_0_hrdata[23:16];
191 |     w4 <= AHB_INTERFACE_0_hrdata[31:24];
192 |     AHB_INTERFACE_0_sel <= 0;
193 |     AHB_INTERFACE_0_hprot <= 0;
194 |     AHB_INTERFACE_0_hready_in <= 1;
195 |     
196 |     state <= 7'd4;
197 | 
198 | end
199 | end
200 | 
201 | 7'd4: begin //try to read second 4 weight value
202 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
203 |     AHB_INTERFACE_0_htrans <= 2'b10;
204 |     AHB_INTERFACE_0_haddr <= 32'h4001_0000 + 4;
205 |     AHB_INTERFACE_0_hburst <= 0;
206 |     AHB_INTERFACE_0_hsize <= 3'b010;
207 |     AHB_INTERFACE_0_hready_in <= 1;
208 |     AHB_INTERFACE_0_sel <= 1;
209 |     AHB_INTERFACE_0_hprot <= 1;    
210 | 
211 |     state <= 7'd5;                
212 | 
213 | end
214 | end
215 | 
216 | 7'd5: begin
217 | AHB_INTERFACE_0_hready_in <= 0;
218 | AHB_INTERFACE_0_htrans <= 0;
219 | state <= 7'd6;    
220 | end
221 | 
222 | 7'd6: begin //write weight value in my registor
223 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
224 |     w5 <= AHB_INTERFACE_0_hrdata[7:0];
225 |     w6 <= AHB_INTERFACE_0_hrdata[15:8];
226 |     w7 <= AHB_INTERFACE_0_hrdata[23:16];
227 |     w8 <= AHB_INTERFACE_0_hrdata[31:24];
228 |     AHB_INTERFACE_0_sel <= 0;
229 |     AHB_INTERFACE_0_hprot <= 0;
230 |     AHB_INTERFACE_0_hready_in <= 1;   
231 |     state <= 7'd7;
232 | end
233 | end
234 | 
235 | 7'd7: begin //try to read last one weight value
236 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
237 |     AHB_INTERFACE_0_htrans <= 2'b10;
238 |     AHB_INTERFACE_0_haddr <= 32'h4001_0000 + 8;
239 |     AHB_INTERFACE_0_hburst <= 0;
240 |     AHB_INTERFACE_0_hsize <= 3'b010;
241 |     AHB_INTERFACE_0_hready_in <= 1;
242 |     AHB_INTERFACE_0_sel <= 1;
243 |     AHB_INTERFACE_0_hprot <= 1;
244 |     state <= 7'd8;                
245 | end
246 | end
247 | 
248 | 7'd8: begin
249 | AHB_INTERFACE_0_hready_in <= 0;
250 | AHB_INTERFACE_0_htrans <= 0;
251 | state <= 7'd9;    
252 | end
253 | 
254 | 7'd9: begin //write weight value in my registor
255 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
256 |     w9 <= AHB_INTERFACE_0_hrdata[7:0];
257 |     AHB_INTERFACE_0_sel <= 0;
258 |     AHB_INTERFACE_0_hprot <= 0;
259 |     AHB_INTERFACE_0_hready_in <= 1;
260 |     state <= 7'd10;
261 | end
262 | end
263 | 
264 | //loop2
265 | 7'd10: begin //try to read first line of image array
266 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
267 |     AHB_INTERFACE_0_htrans <= 2'b10;
268 |     AHB_INTERFACE_0_haddr <= 32'h4000_0000 + address_offset;
269 |     AHB_INTERFACE_0_hburst <= 0;
270 |     AHB_INTERFACE_0_hsize <= 3'b010;
271 |     AHB_INTERFACE_0_hready_in <= 1;
272 |     AHB_INTERFACE_0_sel <= 1;
273 |     AHB_INTERFACE_0_hprot <= 1;
274 |     state <= 7'd11;                
275 | end
276 | end
277 | 
278 | 7'd11: begin
279 | AHB_INTERFACE_0_hready_in <= 0;
280 | AHB_INTERFACE_0_htrans <= 0;
281 | state <= 7'd12;
282 | end
283 | 
284 | 7'd12: begin //store the first row of image array in my databus_1
285 |     if ( AHB_INTERFACE_0_hready_out == 1 ) begin
286 |     databus_1 <= databus_1 | (AHB_INTERFACE_0_hrdata<<(address_offset*8));
287 | 
288 |     
289 |     AHB_INTERFACE_0_sel <= 0;
290 |     AHB_INTERFACE_0_hprot <= 0;
291 |     AHB_INTERFACE_0_hready_in <= 1;
292 |     
293 |     state <= 7'd13;
294 | 
295 | end
296 | end
297 | 
298 | 7'd13: begin //try to read first line of image array
299 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
300 |     AHB_INTERFACE_0_htrans <= 2'b10;
301 |     AHB_INTERFACE_0_haddr <= 32'h4000_0000 + 84 + address_offset;
302 |     AHB_INTERFACE_0_hburst <= 0;
303 |     AHB_INTERFACE_0_hsize <= 3'b010;
304 |     AHB_INTERFACE_0_hready_in <= 1;
305 |     AHB_INTERFACE_0_sel <= 1;
306 |     AHB_INTERFACE_0_hprot <= 1;
307 |     
308 |     
309 |     state <= 7'd14;                
310 | 
311 | end
312 | end
313 | 
314 | 7'd14: begin
315 | AHB_INTERFACE_0_hready_in <= 0;
316 | AHB_INTERFACE_0_htrans <= 0;
317 | 
318 | 
319 | state <= 7'd15;
320 | 
321 | end
322 | 7'd15: begin //store the second row of image array in my databus_2
323 |     if ( AHB_INTERFACE_0_hready_out == 1 ) begin
324 |     databus_2 <=  databus_2 | (AHB_INTERFACE_0_hrdata<<(address_offset*8));
325 | 
326 |     AHB_INTERFACE_0_sel <= 0;
327 |     AHB_INTERFACE_0_hprot <= 0;
328 |     AHB_INTERFACE_0_hready_in <= 1;
329 |     
330 |     state <= 7'd16;
331 | end
332 | end
333 | 
334 | 7'd16: begin//try to read first line of image array
335 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
336 |     AHB_INTERFACE_0_htrans <= 2'b10;
337 |     AHB_INTERFACE_0_haddr <= 32'h4000_0000 + 168 + address_offset;
338 |     AHB_INTERFACE_0_hburst <= 0;
339 |     AHB_INTERFACE_0_hsize <= 3'b010;
340 |     AHB_INTERFACE_0_hready_in <= 1;
341 |     AHB_INTERFACE_0_sel <= 1;
342 |     AHB_INTERFACE_0_hprot <= 1;
343 | 
344 |     state <= 7'd17;                
345 | 
346 | end
347 | end
348 | 
349 | 7'd17: begin
350 | AHB_INTERFACE_0_hready_in <= 0;
351 | AHB_INTERFACE_0_htrans <= 0;
352 | 
353 | 
354 | state <= 7'd18;
355 | 
356 | end
357 | 7'd18: begin //store the third row of image array in my databus_3
358 |     if ( AHB_INTERFACE_0_hready_out == 1 ) begin
359 |     databus_3 <=  databus_3 | (AHB_INTERFACE_0_hrdata<<(address_offset*8));
360 |     AHB_INTERFACE_0_sel <= 0;
361 |     AHB_INTERFACE_0_hprot <= 0;
362 |     AHB_INTERFACE_0_hready_in <= 1;
363 |     
364 |     state <= 7'd19;
365 | end
366 | end
367 | //check the address_offset whether it reach last of column and have to change the row. if it reach the last of column, goto the next state.
368 | //or not, goto state 10 and read repeat.
369 | 7'd19: begin 
370 | if ( AHB_INTERFACE_0_hready_out == 1 && AHB_INTERFACE_0_hresp == 0) begin
371 |     AHB_INTERFACE_0_sel <= 0;
372 |     AHB_INTERFACE_0_hprot <= 0;
373 |     AHB_INTERFACE_0_hwdata <= 0;
374 |     AHB_INTERFACE_0_hwrite <= 0;
375 |     AHB_INTERFACE_0_hready_in <= 1;
376 |         if ( address_offset !=80 ) begin
377 |         address_offset <= address_offset + 4;
378 |         state <= 7'd10;
379 |     end
380 |     else begin
381 |         
382 |         address_offset<=0;
383 |         state <= 7'd20;
384 |         
385 |     end
386 | end
387 | end
388 | 
389 | //try to read new row that does not read by databus
390 | 7'd20: begin
391 | if ( AHB_INTERFACE_0_hready_out == 1 ) begin
392 |     AHB_INTERFACE_0_htrans <= 2'b10;
393 |     AHB_INTERFACE_0_haddr <= 32'h4000_0000 + 252 + address_offset;
394 |     AHB_INTERFACE_0_hburst <= 0;
395 |     AHB_INTERFACE_0_hsize <= 3'b010;
396 |     AHB_INTERFACE_0_hready_in <= 1;
397 |     AHB_INTERFACE_0_sel <= 1;
398 |     AHB_INTERFACE_0_hprot <= 1;
399 |     state <= 7'd21;
400 |                
401 | 
402 | end
403 | end
404 | 
405 | //move the middle of data that have to store to calculate for convolution to im17, im18.. it is like temp registor.
406 | 7'd21: begin
407 |     im17 <= im3;
408 |     im18 <= im4;
409 |     im19 <= im7;
410 |     im20 <= im8;
411 |     im21 <= im11;
412 |     im22 <= im12;
413 |     im23 <= im15;
414 |     im24 <= im16;
415 | AHB_INTERFACE_0_hready_in <= 0;
416 | AHB_INTERFACE_0_htrans <= 0;
417 | state <= 7'd22;
418 | end
419 | 
420 | 
421 | //assign image value for calculate convolution.
422 | 7'd22: begin
423 |     if ( AHB_INTERFACE_0_hready_out == 1 ) begin
424 |    
425 |     im1 <= databus_1[7:0];
426 |     im2 <= databus_1[15:8];
427 |     im3 <= databus_1[23:16];
428 |     im4 <= databus_1[31:24];
429 |     im5 <= databus_2[7:0];
430 |     im6 <= databus_2[15:8];
431 |     im7 <= databus_2[23:16];
432 |     im8 <= databus_2[31:24];
433 |     im9 <= databus_3[7:0];
434 |     im10 <= databus_3[15:8];
435 |     im11 <= databus_3[23:16];
436 |     im12 <= databus_3[31:24];
437 |     im13<=(AHB_INTERFACE_0_hrdata & 255);
438 |     im14<=((AHB_INTERFACE_0_hrdata>>8) & 255);
439 |     im15<=((AHB_INTERFACE_0_hrdata>>16) & 255);
440 |     im16<=((AHB_INTERFACE_0_hrdata>>24) & 255);
441 |  
442 |  //move databus array
443 |     databus_1 <= {databus_2[31:0], databus_1[671:32]};//(databus_1 >>32);
444 |     databus_2 <= {databus_3[31:0], databus_2[671:32]};//(databus_2 >>32);
445 |     
446 |     AHB_INTERFACE_0_sel <= 0;
447 |     AHB_INTERFACE_0_hprot <= 0;
448 |     AHB_INTERFACE_0_hready_in <= 1;
449 |     state<=7'd23;
450 |  end
451 | end
452 | 
453 |  //move databus array. and check whether the read data reach the end of array. if reached, change the row value that make just read phase.
454 |  //And set the col as 0, that make calculate max pooling just one.
455 | 7'd23: begin
456 | databus_3 <= {im16, im15, im14, im13, databus_3[671:32]};//databus_3 | ({im16, im15, im14, im13} << 640); 
457 | address_offset <= address_offset + 4;
458 | if ((address_offset%84)==80) begin
459 |     row <= ~row;
460 |     col <= 0;
461 |     end
462 |  state <= 7'd100;
463 |  end
464 |  
465 |  
466 |  //calculate max pooling.
467 | 7'd100 : begin
468 | if (row==1) begin
469 | state<=7'd20;
470 | end
471 | else if ( max_cnt==0) begin
472 |         if (col==0) begin
473 |                 max1 <= ((temp1 > temp2) ? ((temp1 > temp3) ? ((temp1 > temp4) ? temp1 : temp4) : ( (temp3 > temp4) ? temp3 : temp4)) : ((temp2 > temp3) ? ((temp2 >temp4) ? temp2 : temp4) : ((temp3 > temp4) ? temp3 : temp4 )));
474 |                 col<=1;
475 |                 max_cnt <= 1;
476 |                 state <= 7'd20;        
477 |         end        
478 |         else begin
479 |                 max2 <= ((temp1 > temp2) ? ((temp1 > temp3) ? ((temp1 > temp4) ? temp1 : temp4) : ( (temp3 > temp4) ? temp3 : temp4)) : ((temp2 > temp3) ? ((temp2 >temp4) ? temp2 : temp4) : ((temp3 > temp4) ? temp3 : temp4 )));
480 |                 max1 <= ((temp5 > temp6) ? ((temp5 > temp7) ? ((temp5 > temp8) ? temp5 : temp8) : ( (temp7 > temp8) ? temp7 : temp8)) : ((temp6 > temp7) ? ((temp6 >temp8) ? temp6 : temp8) : ((temp7 > temp8) ? temp7 : temp8 )));                                        
481 |                 max_cnt <= 2;
482 |                 state <= 7'd20;    
483 |         end        
484 | end
485 | else if ( max_cnt==1) begin
486 |             if (col==0) begin
487 |                 max2 <= ((temp1 > temp2) ? ((temp1 > temp3) ? ((temp1 > temp4) ? temp1 : temp4) : ( (temp3 > temp4) ? temp3 : temp4)) : ((temp2 > temp3) ? ((temp2 >temp4) ? temp2 : temp4) : ((temp3 > temp4) ? temp3 : temp4 )));
488 |                 col<=1;
489 |                 max_cnt <= 2;
490 |                 state <= 7'd20;   
491 | 
492 |             end
493 | 
494 |             else begin
495 |                  max3 <= ((temp1 > temp2) ? ((temp1 > temp3) ? ((temp1 > temp4) ? temp1 : temp4) : ( (temp3 > temp4) ? temp3 : temp4)) : ((temp2 > temp3) ? ((temp2 >temp4) ? temp2 : temp4) : ((temp3 > temp4) ? temp3 : temp4 )));
496 |                  max2 <= ((temp5 > temp6) ? ((temp5 > temp7) ? ((temp5 > temp8) ? temp5 : temp8) : ( (temp7 > temp8) ? temp7 : temp8)) : ((temp6 > temp7) ? ((temp6 >temp8) ? temp6 : temp8) : ((temp7 > temp8) ? temp7 : temp8 )));                                        
497 |                  max_cnt <= 3;
498 |                  state <= 7'd20;  
499 | 
500 |             end
501 | end
502 | else if ( max_cnt==2) begin
503 |             if (col==0) begin
504 |                   max3 <= ((temp1 > temp2) ? ((temp1 > temp3) ? ((temp1 > temp4) ? temp1 : temp4) : ( (temp3 > temp4) ? temp3 : temp4)) : ((temp2 > temp3) ? ((temp2 >temp4) ? temp2 : temp4) : ((temp3 > temp4) ? temp3 : temp4 )));
505 |                   col<=1;
506 |                   max_cnt <= 3;
507 |                   state <= 7'd20;  
508 |              end
509 |              else begin
510 |                  max4 <= ((temp1 > temp2) ? ((temp1 > temp3) ? ((temp1 > temp4) ? temp1 : temp4) : ( (temp3 > temp4) ? temp3 : temp4)) : ((temp2 > temp3) ? ((temp2 >temp4) ? temp2 : temp4) : ((temp3 > temp4) ? temp3 : temp4 )));
511 |                  max3 <= ((temp5 > temp6) ? ((temp5 > temp7) ? ((temp5 > temp8) ? temp5 : temp8) : ( (temp7 > temp8) ? temp7 : temp8)) : ((temp6 > temp7) ? ((temp6 >temp8) ? temp6 : temp8) : ((temp7 > temp8) ? temp7 : temp8 )));                                        
512 |                  max_cnt <= 0;
513 |                  state <= 7'd101; 
514 |             end   
515 | end
516 | else if ( max_cnt==3) begin
517 |             if (col==0) begin
518 |                  max4 <= ((temp1 > temp2) ? ((temp1 > temp3) ? ((temp1 > temp4) ? temp1 : temp4) : ( (temp3 > temp4) ? temp3 : temp4)) : ((temp2 > temp3) ? ((temp2 >temp4) ? temp2 : temp4) : ((temp3 > temp4) ? temp3 : temp4 )));
519 |                  col<=1;
520 |                  max_cnt <= 0;
521 |                  state <= 7'd101;  
522 |             end
523 |             else begin
524 |                  temp <= ((temp1 > temp2) ? ((temp1 > temp3) ? ((temp1 > temp4) ? temp1 : temp4) : ( (temp3 > temp4) ? temp3 : temp4)) : ((temp2 > temp3) ? ((temp2 >temp4) ? temp2 : temp4) : ((temp3 > temp4) ? temp3 : temp4 )));
525 |                  max4 <= ((temp5 > temp6) ? ((temp5 > temp7) ? ((temp5 > temp8) ? temp5 : temp8) : ( (temp7 > temp8) ? temp7 : temp8)) : ((temp6 > temp7) ? ((temp6 >temp8) ? temp6 : temp8) : ((temp7 > temp8) ? temp7 : temp8 )));                                        
526 |                  max_cnt <= 1;
527 |                  state <= 7'd101;
528 |              end                        
529 | end
530 | end
531 | 
532 | 7'd101 : begin  // write finish code
533 |       if ( AHB_INTERFACE_0_hready_out == 1 && AHB_INTERFACE_0_hresp == 0) begin
534 |            
535 |                 AHB_INTERFACE_0_htrans <= 2'b10;
536 |                 AHB_INTERFACE_0_haddr <= 32'h4002_0000 + address_offset_max;
537 |                 AHB_INTERFACE_0_hburst <= 0;
538 |                 AHB_INTERFACE_0_hsize <= 3'b010; //Byte
539 |                 AHB_INTERFACE_0_hready_in <= 1;
540 |                 AHB_INTERFACE_0_sel <= 1;
541 |                 AHB_INTERFACE_0_hprot <= 9;
542 |                 AHB_INTERFACE_0_hwdata <= {max4, max3, max2, max1};
543 |                 AHB_INTERFACE_0_hwrite <= 1;
544 |                 address_offset_max <= address_offset_max + 4;
545 |                 state<=7'd102;
546 |         end
547 |      end
548 |      
549 |   7'd102: begin
550 |       AHB_INTERFACE_0_htrans <= 0;
551 |       AHB_INTERFACE_0_hready_in <= 0;
552 |       state <= 7'd103;
553 |   end
554 | 
555 | //check the max_pooling offset whether we reach the end of process.
556 |   7'd103: begin
557 |       if ( AHB_INTERFACE_0_hready_out == 1 && AHB_INTERFACE_0_hresp == 0) begin
558 |           AHB_INTERFACE_0_sel <= 0;
559 |           AHB_INTERFACE_0_hprot <= 0;
560 |           AHB_INTERFACE_0_hwdata <= 0;
561 |           AHB_INTERFACE_0_hwrite <= 0;
562 |           AHB_INTERFACE_0_hready_in <= 1;
563 |           if(address_offset_max==1680) begin
564 |                 state <= 7'd66;
565 |                 end
566 |            else begin
567 |                  max1 <= temp;
568 |                  temp <=0 ;
569 |                  state <= 7'd20;
570 |                  end
571 |               end
572 |     end
573 |     
574 | //write in finish memory
575 | 7'd66: begin
576 | finish <= 1;
577 | AHB_INTERFACE_0_haddr <= 0;
578 | AHB_INTERFACE_0_hburst <= 0;
579 | AHB_INTERFACE_0_hprot <= 0;
580 | AHB_INTERFACE_0_hready_in <= 0;
581 | AHB_INTERFACE_0_hsize <= 0;
582 | AHB_INTERFACE_0_htrans <= 0;
583 | AHB_INTERFACE_0_hwdata <= 0;
584 | AHB_INTERFACE_0_hwrite <= 0;
585 | AHB_INTERFACE_0_sel <= 0;
586 | end
587 | 
588 | endcase
589 | end
590 | end 
591 | 
592 | 
593 | endmodule
594 |  
595 |  
596 |  
597 |  
598 | 


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