├── screenshots
    ├── state.png
    └── guidline.jpg
├── tb.v
├── adder32bit.v
├── concatforJump.v
├── signExt.v
├── PC.v
├── shiftleft.v
├── IFID.v
├── MUX.v
├── RegFile.v
├── ALUcontrol.v
├── DM.v
├── README.md
├── ALU.v
├── Controlstall.v
├── MEMWB.v
├── IDEX.v
├── EXMEM.v
├── stall.v
├── controlunit.v
├── mypip.v
└── InstMem.v


/screenshots/state.png:
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https://raw.githubusercontent.com/maze1377/pipeline-mips-verilog/HEAD/screenshots/state.png


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/screenshots/guidline.jpg:
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https://raw.githubusercontent.com/maze1377/pipeline-mips-verilog/HEAD/screenshots/guidline.jpg


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/tb.v:
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 1 | module TB;
 2 | reg clk;
 3 | initial begin
 4 |     clk=1'b0;
 5 |   end
 6 | always
 7 | begin
 8 | //write your test here
 9 | #3 clk=~clk;
10 | end
11 | Mypip sc1(clk);
12 | endmodule
13 | 


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/adder32bit.v:
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 1 | module adder32bit(in1,in2,out);
 2 | input [31:0]in1;
 3 | input [31:0]in2;
 4 | output [31:0]out;
 5 | reg [31:0]out;
 6 | always@(in1,in2)begin
 7 | out=in1+in2;
 8 | end
 9 | endmodule
10 | 


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/concatforJump.v:
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1 | module concatForJump(part1, part2,result);
2 | input [3:0]part1;
3 | input [27:0]part2;
4 | output reg [31:0]result;
5 | always @(part1,part2)begin
6 | result={part1,part2};
7 | end
8 | endmodule
9 | 


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/signExt.v:
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 1 | module signExt(inData,outData);
 2 | input[15:0] inData;
 3 | output[31:0] outData;
 4 | reg[31:0] outData;
 5 | always@(inData)
 6 | begin
 7 | outData[15:0]=inData[15:0];
 8 | outData[31:16]={16{inData[15]}};
 9 | end
10 | endmodule
11 | 


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/PC.v:
--------------------------------------------------------------------------------
 1 | module PCRegWrite(clock,in,out,enable);
 2 | input [31:0] in;
 3 | input clock,enable;
 4 | output reg [31:0] out;
 5 | 
 6 | initial begin
 7 |  out=32'b0;
 8 | end
 9 | always @(in) begin
10 | if(enable==1'b1)
11 |     out=in;
12 |    end
13 | endmodule
14 | 


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/shiftleft.v:
--------------------------------------------------------------------------------
 1 | module shiftLeft32bitLeft(inData,outData);
 2 | input[31:0] inData;
 3 | output reg[31:0] outData;
 4 | always@(inData)begin
 5 | outData=inData<<2;
 6 | end
 7 | endmodule
 8 | 
 9 | module shiftLeftForJump(inData,outData);
10 | input[25:0] inData;
11 | output reg[27:0] outData;
12 | always@(inData)
13 | begin
14 | outData={inData,2'b0};
15 | end
16 | endmodule
17 | 


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/IFID.v:
--------------------------------------------------------------------------------
 1 |  module IFID(clock,nextPC,instrWireID,nextPCID,instrWireIF,enable);
 2 |  input clock, enable;
 3 |  input [31:0] nextPC;
 4 |  input [31:0] instrWireIF;
 5 |  output [31:0] nextPCID, instrWireID;
 6 |  reg [31:0]  nextPCID,instrWireID;
 7 | always @(posedge clock)  begin 
 8 | if (enable) begin 
 9 | instrWireID <= instrWireIF;
10 | nextPCID <= nextPC;
11 | end 
12 |  end
13 |  endmodule
14 |  


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/MUX.v:
--------------------------------------------------------------------------------
 1 | module mux2(select,a,b,y);
 2 | input select;
 3 | input[31:0] a,b;
 4 | output reg [31:0] y;
 5 | always@(select,a,b) begin
 6 | 
 7 | case(select)
 8 | 	1'b0:y=a;
 9 | 	1'b1:y=b;
10 | endcase
11 | end
12 | endmodule
13 | 
14 | module mux2A(select,a,b,y);
15 | input select;
16 | input[4:0] a,b;
17 | output reg [4:0] y;
18 | always@(select,a,b) begin
19 |  
20 | case(select)
21 | 	1'b0:y=a;
22 | 	1'b1:y=b;
23 | 	endcase
24 | end
25 | endmodule


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/RegFile.v:
--------------------------------------------------------------------------------
 1 | module RegFile (clk, readreg1, readreg2, writereg, writedata, RegWrite, readdata1, readdata2);
 2 |   input [4:0] readreg1, readreg2, writereg;
 3 |   input [31:0] writedata;
 4 |   input clk, RegWrite;
 5 |   output [31:0] readdata1, readdata2;
 6 | 
 7 |   reg [31:0] regfile [31:0];
 8 |   integer i;
 9 |   initial begin
10 |       for (i=1; i<32; i=i+1)   
11 | 	begin
12 |          regfile[i]=i*10;
13 | 	end
14 | end
15 |   always @(posedge clk)
16 |   begin
17 | 	if (RegWrite) 
18 | 	 	regfile[writereg] <= writedata;
19 |     regfile[0]=0;
20 |   end
21 | 
22 |   assign readdata1 = regfile[readreg1];
23 |   assign readdata2 = regfile[readreg2];
24 | endmodule
25 | 
26 | 


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/ALUcontrol.v:
--------------------------------------------------------------------------------
 1 | module ALUcontrol(clk,funct,ALUOp,ALUsignal);
 2 | input clk;
 3 | input[5:0] funct;
 4 | input[2:0] ALUOp;
 5 | output[3:0] ALUsignal;
 6 | reg[3:0] ALUsignal;
 7 | always@(funct , ALUOp ,posedge clk)begin 
 8 | 	case(ALUOp)
 9 | 	3'b010:case(funct)
10 | 6'b100000:ALUsignal=4'b00;//add
11 | 6'b100010:ALUsignal=4'b01;//sub
12 | 6'b100100:ALUsignal=4'b10;//and
13 | 6'b100101:ALUsignal=4'b11;//or
14 | 6'b101010:ALUsignal=4'b101;//stl
15 | endcase 
16 | 3'b001:ALUsignal=4'b0001;//branch
17 | 3'b000:ALUsignal=4'b0000;//Lw and sw
18 | 3'b011:ALUsignal=4'b0010;//andi
19 | 3'b100:ALUsignal=4'b0011;//ori
20 | 3'b111:ALUsignal=4'b0101; //slti
21 | endcase
22 | end
23 | endmodule
24 | 


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/DM.v:
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 1 | module DMemBank(input memread, input memwrite, input [31:0] address, input [31:0] writedata, output reg [31:0] readdata);
 2 |  
 3 |   reg [31:0] mem_array [127:0];
 4 |   wire[6:0]finalAddress;
 5 |   assign finalAddress=address[8:0];
 6 |   integer i;
 7 |   initial 
 8 |   begin
 9 |       for (i=0; i<127; i=i+1)   
10 |      mem_array[i]=i*10;
11 |   end
12 |  
13 |   always@(memread, memwrite, address, mem_array[address], writedata)
14 |   begin
15 |     if(memread)begin
16 |       readdata=mem_array[finalAddress];
17 |     end
18 | 
19 |     if(memwrite)
20 |     begin
21 |       mem_array[finalAddress]= writedata;
22 |     end
23 | 
24 |   end
25 | 
26 | endmodule
27 | 
28 | 


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/README.md:
--------------------------------------------------------------------------------
 1 | 
 2 | # MIPS pipline
 3 | A classic 5-stage pipeline MIPS 32-bit processor.
 4 | 
 5 | five stages of a microprocessor: instruction fetch (IF),
 6 | instruction decode (ID), execution(EX),
 7 | memory access and write (MEM) e write back (WB).
 8 | 
 9 | #name of wire and guideline		
10 | ![wirename](https://github.com/maze1377/pipeline-mips-verilog/blob/master/screenshots/guidline.jpg)
11 | 
12 | #states
13 | ![state](https://github.com/maze1377/pipeline-mips-verilog/blob/master/screenshots/state.png)
14 | 
15 | support most of MIPS instruction and solve every hazard with stall.(Data Hazards and Control Hazards) Verilog code.
16 | 
17 | Developed during the winter 2019 Computer Architecture Laboratory course at the University of Ferdowsi Mashhad.
18 | # Modular design
19 | code start from mypip
20 | 
21 | other modular named same to original model
22 | 


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/ALU.v:
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 1 | module ALU(input [31:0] data1,data2,input [3:0] aluoperation,output reg [31:0] result,output reg zero,lt,gt);
 2 |   always@(aluoperation,data1,data2)
 3 |   begin 
 4 | 	   case (aluoperation)
 5 |       4'b0000 : result = data1 + data2; // ADD
 6 |       4'b0001 : result = data1 - data2; // SUB
 7 |       4'b0010 : result = data1 & data2; // AND
 8 |       4'b0011 : result = data1 | data2; // OR
 9 |       4'b0100 : result = data1 ^ data2; // XOR
10 |       4'b0101 : result = {31'b0,lt};//slt
11 |       // if you want to add new Alu instructions  add here
12 |       default : result = data1 + data2; // ADD
13 |     endcase
14 |     if(data1>data2)
15 |       begin
16 |        gt = 1'b1;
17 |        lt = 1'b0; 
18 |       end else if(data1<data2)
19 |       begin
20 |        gt = 1'b0;
21 |        lt = 1'b1;  
22 |       end
23 |       
24 |     if (result==32'd0) zero=1'b1;
25 |     else zero=1'b0;
26 |   end
27 | 
28 | endmodule
29 | 
30 | 


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/Controlstall.v:
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 1 | module Controlstall(clk,op1,op2,op3,stall);
 2 | input [5:0]op1,op2,op3;
 3 | input clk;
 4 | output reg stall;
 5 | initial begin
 6 | stall=1'b1;
 7 | end
 8 | always @(posedge clk)begin
 9 | 
10 | 
11 | if(op1==6'b000100 | op1==6'b000101 | op1==6'b000010)begin// beq or bne or j
12 | stall=1'b0;
13 | end
14 | if(op2==6'b000100 | op2==6'b000101 | op2==6'b000010)begin// beq or bne or j
15 | stall=1'b0;
16 | end
17 | if(op3==6'b000100 | op3==6'b000101 | op3==6'b000010)begin// beq or bne or j
18 | stall=1'b0;
19 | end
20 | else begin
21 | stall=1'b1;
22 | end
23 | 
24 | end
25 | 
26 | 
27 | endmodule
28 | 
29 | module nopSet(clk,s1,s2,oldF,oldD,newF,newD);
30 | input clk,s1,s2;
31 | input [31:0] oldF,oldD;
32 | output reg[31:0]newD,newF;
33 | 
34 | initial begin
35 | end
36 | always @(posedge clk)begin
37 | if(s1==1'b0 && s2==1'b0)begin
38 | newF=32'b0;
39 | newD=32'b0;
40 | end
41 | else if(s1==1'b0 && s2==1'b1)begin
42 | newD=32'b0;
43 | end
44 | else if(s1==1'b1 && s2==1'b0)begin
45 | newF=32'b0;
46 | end
47 | else
48 | begin
49 | newD=oldD;
50 | newF=oldF;
51 | end
52 | end
53 | endmodule
54 | 


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/MEMWB.v:
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 1 | module MEMWB(clock,iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps,iALUCtrl,
 2 | iIR,iB,iResult,iRegDest,
 3 | oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps,oALUCtrl,
 4 | oIR,oB,oResult,oRegDest,enable);
 5 | input [31:0] iIR,iB,iResult;
 6 | input clock,enable;
 7 | input iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps;
 8 | input [3:0]iALUCtrl;
 9 | input [4:0] iRegDest;
10 | output [31:0] oIR,oB,oResult;
11 | output oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
12 | output [3:0]oALUCtrl;
13 | output [4:0]oRegDest;
14 | reg [31:0] oIR,oB,oResult;
15 | reg oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
16 | reg [3:0]oALUCtrl;
17 | reg [4:0]oRegDest;
18 | initial begin
19 | oIR=32'b0;
20 | end
21 | always @(posedge clock)
22 | begin
23 | if(enable)begin
24 | oRegDests<=iRegDests;
25 | oRegWrite<=iRegWrite;
26 | oALUSrc<=iALUSrc;
27 | oMemRead<=iMemRead;
28 | oMemWrite<=iMemWrite;
29 | oMemToReg<=iMemToReg;
30 | oBranchs<=iBranchs;
31 | oJumps<=iJumps;
32 | oALUCtrl<=iALUCtrl;
33 | oIR<=iIR;
34 | oB<=iB;
35 | oResult<=iResult;
36 | oRegDest<=iRegDest;
37 | end
38 | end
39 | endmodule
40 | 
41 | 


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/IDEX.v:
--------------------------------------------------------------------------------
 1 | 
 2 | module IDEX(clock,iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps,iALUCtrl,
 3 | iIR,iPC,iA,iB,iRegDest,iBranch,iJump,
 4 | oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps,oALUCtrl,
 5 | oIR,oPC,oA,oB,oRegDest,oBranch,oJump,enable);
 6 | input [31:0] iIR,iPC,iA,iB,iBranch,iJump;
 7 | input clock,enable;
 8 | input iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps;
 9 | input [3:0]iALUCtrl;
10 | input [4:0] iRegDest;
11 | output [31:0] oIR,oPC,oA,oB,oBranch,oJump;
12 | output oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
13 | output [3:0]oALUCtrl;
14 | output [4:0]oRegDest;
15 | reg [31:0] oIR,oPC,oA,oB,oResult,oBranch,oJump;
16 | reg oZero;
17 | reg oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
18 | reg [3:0]oALUCtrl;
19 | reg [4:0]oRegDest;
20 | initial begin
21 |  oPC=32'b0;
22 | oIR=32'b0;
23 | end
24 | always @(posedge clock)
25 | begin
26 | if(enable)begin
27 | oRegDests<=iRegDests;
28 | oRegWrite<=iRegWrite;
29 | oALUSrc<=iALUSrc;
30 | oMemRead<=iMemRead;
31 | oMemWrite<=iMemWrite;
32 | oMemToReg<=iMemToReg;
33 | oBranchs<=iBranchs;
34 | oJumps<=iJumps;
35 | oALUCtrl<=iALUCtrl;
36 | oIR<=iIR;
37 | oPC<=iPC;
38 | oA<=iA;
39 | oB<=iB;
40 | oRegDest<=iRegDest;
41 | oBranch<=iBranch;
42 | oJump<=iJump;
43 | end
44 | end
45 | endmodule
46 | 
47 | 


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/EXMEM.v:
--------------------------------------------------------------------------------
 1 | module EXMEM(clock,iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps,iALUCtrl,
 2 | iIR,iPC,iB,iResult,iRegDest,iBranch,iJump,iZero,
 3 | oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps,oALUCtrl,
 4 | oIR,oPC,oB,oResult,oRegDest,oBranch,oJump,oZero,enable);
 5 | input [31:0] iIR,iPC,iB,iResult,iBranch,iJump;
 6 | input iZero,clock,enable;
 7 | input iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps;
 8 | input [3:0]iALUCtrl;
 9 | input [4:0] iRegDest;
10 | output [31:0] oIR,oPC,oB,oResult,oBranch,oJump;
11 | output oZero;
12 | output oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
13 | output [3:0]oALUCtrl;
14 | output [4:0]oRegDest;
15 | reg [31:0] oIR,oPC,oB,oResult,oBranch,oJump;
16 | reg oZero;
17 | reg oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
18 | reg [3:0]oALUCtrl;
19 | reg [4:0]oRegDest;
20 | initial begin
21 |  oPC=32'b0;
22 | oIR=32'b0;
23 | end
24 | always @(posedge clock)
25 | begin
26 | if(enable)begin
27 | oRegDests<=iRegDests;
28 | oRegWrite<=iRegWrite;
29 | oALUSrc<=iALUSrc;
30 | oMemRead<=iMemRead;
31 | oMemWrite<=iMemWrite;
32 | oMemToReg<=iMemToReg;
33 | oBranchs<=iBranchs;
34 | oJumps<=iJumps;
35 | oALUCtrl<=iALUCtrl;
36 | oIR<=iIR;
37 | oPC<=iPC;
38 | oB<=iB;
39 | oResult<=iResult;
40 | oRegDest<=iRegDest;
41 | oBranch<=iBranch;
42 | oJump<=iJump;
43 | oZero<=iZero;
44 | end
45 | end
46 | endmodule
47 | 
48 | 
49 | 


--------------------------------------------------------------------------------
/stall.v:
--------------------------------------------------------------------------------
  1 | module stallUnit(clk,rs,rt,opcode,IRD,IREX,IRMEM,regWB,WWBs,IRWB,stall);
  2 | input clk,WWBs;
  3 | input [5:0]opcode;
  4 | input [4:0]rs,rt,regWB;
  5 | input [31:0]IRD,IREX,IRMEM,IRWB;
  6 | output reg stall;
  7 | reg we1,we2,we3;
  8 | reg [4:0]ws1,ws2,ws3;
  9 | reg res,ret;
 10 | initial begin
 11 | stall=1'b1;
 12 | we1=1'b0;
 13 | we2=1'b0;
 14 | we3=1'b0;
 15 | res=1'b0;
 16 | ret=1'b0;
 17 | end
 18 | 
 19 | always @(posedge clk)begin
 20 | if(IRD != 32'b0)begin
 21 | case(opcode)
 22 | //Rtype
 23 | 6'b0:begin
 24 | res=1'b1;
 25 | ret=1'b1;
 26 | end
 27 | 6'b100011:begin//lw
 28 | res=1'b1;
 29 | ret=1'b0;
 30 | end
 31 | 6'b101011:begin//sw
 32 | res=1'b1;
 33 | ret=1'b1;
 34 | end
 35 | 6'b000010:begin//jump
 36 | res=1'b0;
 37 | ret=1'b0;
 38 | end
 39 | 6'b100:begin//beq
 40 | res=1'b1;
 41 | ret=1'b1;
 42 | end
 43 | 6'b101:begin//bne
 44 | res=1'b1;
 45 | ret=1'b1;
 46 | end
 47 | default begin//IType
 48 | res=1'b1;
 49 | ret=1'b0;
 50 | end
 51 | endcase
 52 | end
 53 | else begin
 54 | res=1'b0;
 55 | ret=1'b0;
 56 | end
 57 | 
 58 | //
 59 | if(IREX != 32'b0)begin
 60 | case(IREX[31:26])//we1,ws1
 61 | //Rtype:opcode 6bit and function 
 62 | 6'b0:begin
 63 | we1=1'b1;
 64 | ws1=IREX[15:11];
 65 | end		 
 66 | 6'b100011:begin//lw
 67 | we1=1'b1;
 68 | ws1=IREX[20:16];
 69 | end
 70 | 6'b101011:begin//sw
 71 | we1=1'b0;
 72 | ws1=5'b0;
 73 | end
 74 | 6'b000010:begin//jump
 75 | we1=1'b0;
 76 | ws1=5'b0;
 77 | end
 78 | 6'b100:begin//beq
 79 | we1=1'b0;
 80 | ws1=5'b0;
 81 | end
 82 | 6'b101:begin//bne
 83 | we1=1'b0;
 84 | ws1=5'b0;
 85 | end
 86 | default begin//IType
 87 | we1=1'b1;
 88 | ws1=IREX[20:16];
 89 | end
 90 | endcase
 91 | end
 92 | else begin
 93 | we1=1'b0;
 94 | end
 95 | 
 96 | //
 97 | if(IRMEM != 32'b0)begin
 98 | case(IRMEM[31:26])//we2,ws2
 99 | //Rtype:opcode 6bit and function 6bit
100 | 6'b0:begin
101 | we2=1'b1;
102 | ws2=IREX[15:11];
103 | end
104 | 6'b100011:begin//lw
105 | we2=1'b1;
106 | ws2=IREX[20:16];
107 | end
108 | 6'b101011:begin//sw
109 | we2=1'b0;
110 | ws2=5'b0;
111 | end
112 | 6'b000010:begin//jump
113 | we2=1'b0;
114 | ws2=5'b0;
115 | end
116 | 6'b100:begin//beq
117 | we2=1'b0;
118 | ws2=5'b0;
119 | end
120 | 6'b101:begin//bne
121 | we2=1'b0;
122 | ws2=5'b0;
123 | end
124 | default begin//IType
125 | we2=1'b1;
126 | ws2=IREX[20:16];
127 | end
128 | endcase
129 | end
130 | else begin
131 | we2=1'b0;
132 | end
133 | 
134 | //
135 | if(IRWB != 32'b0)begin
136 | we3=WWBs;
137 | ws3=regWB;
138 | end
139 | else begin
140 | we3=1'b0;
141 | end
142 | stall=~((((rs==ws1)&we1) + ((rs==ws2)&we2) + ((rs==ws3)&we3))&res + (((rt==ws1)&we1) + ((rt==ws2)&we2) + ((rt==ws3)&we3))&ret);
143 | 
144 | end
145 | endmodule
146 | 


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/controlunit.v:
--------------------------------------------------------------------------------
  1 | module controlUnit(clk,opcode,funct,ALUOp,RegDest,RegWrite,ALUSrc,MemRead,MemWrite,MemToReg,Branch,Jump,IR);
  2 | input[5:0] opcode,funct;
  3 | input clk;
  4 | input [31:0]IR;
  5 | output[2:0] ALUOp;
  6 | output RegDest,RegWrite,ALUSrc,MemRead,MemWrite,MemToReg,Branch,Jump;
  7 | reg[2:0] ALUOp;
  8 | reg RegDest,RegWrite,ALUSrc,MemRead,MemWrite,MemToReg,Branch,Jump;
  9 |  	parameter Rtype = 6'b000000;
 10 | 	parameter beq = 6'b000100;
 11 | 	parameter bne = 6'b000101;
 12 | 	parameter sw = 6'b101011;
 13 | 	parameter lw = 6'b100011;
 14 | 	parameter addi = 6'b001000;
 15 | 	parameter andi = 6'b001100;
 16 | 	parameter ori = 6'b001101;
 17 | 	parameter slti = 6'b001010;
 18 | 	parameter j = 6'b000010;
 19 | 
 20 | always@(opcode,funct,posedge clk)begin
 21 | if(IR==32'b0)
 22 | begin
 23 | ALUOp<=3'b0;
 24 | RegDest<=1'b0;
 25 | RegWrite<=1'b0;
 26 | ALUSrc<=1'b0;
 27 | MemRead<=1'b0;
 28 | MemWrite<=1'b0;
 29 | MemToReg<=1'b0;
 30 | Branch<=1'b0;
 31 | Jump<=1'b0;
 32 | end
 33 | else
 34 | begin
 35 | case(opcode)
 36 | Rtype:begin//rtype
 37 | ALUOp=3'b10;
 38 | RegDest=1'b1;
 39 | RegWrite=1'b1;
 40 | ALUSrc=1'b0;
 41 | MemRead=1'b0;
 42 | MemWrite=1'b0;
 43 | MemToReg=1'b0;
 44 | Branch=1'b0;
 45 | Jump=1'b0;
 46 | end
 47 | lw:begin//lw
 48 | ALUOp<=3'b00;
 49 | RegDest<=1'b0;
 50 | RegWrite<=1'b1;
 51 | ALUSrc<=1'b1;//
 52 | MemRead<=1'b1;
 53 | MemWrite<=1'b0;
 54 | MemToReg<=1'b1;
 55 | Branch<=1'b0;
 56 | Jump<=1'b0;
 57 | end
 58 | sw:begin//sw
 59 | ALUOp<=3'b00;
 60 | RegDest<=1'bx;
 61 | RegWrite<=1'b0;
 62 | ALUSrc<=1'b1;//
 63 | MemRead<=1'b0;
 64 | MemWrite<=1'b1;
 65 | MemToReg<=1'bx;
 66 | Branch<=1'b0;
 67 | Jump<=1'b0;
 68 | end
 69 | j:begin//jump
 70 | ALUOp<=3'bxxx;
 71 | RegDest<=1'bx;
 72 | RegWrite<=1'b0;
 73 | ALUSrc<=1'bx;
 74 | MemRead<=1'bx;
 75 | MemWrite<=1'b0;
 76 | MemToReg<=1'bx;
 77 | Branch<=1'bx;
 78 | Jump<=1'b1;
 79 | end
 80 | beq:begin//beq
 81 | ALUOp<=3'b01;
 82 | RegDest<=1'bx;
 83 | RegWrite<=1'b0;
 84 | ALUSrc<=1'b0;
 85 | MemRead<=1'b0;
 86 | MemWrite<=1'b0;
 87 | MemToReg<=1'bx;
 88 | Branch<=1'b1;
 89 | Jump<=1'b0;
 90 | end
 91 | bne:begin//bne
 92 | ALUOp<=3'b01;
 93 | RegDest<=1'bx;
 94 | RegWrite<=1'b0;
 95 | ALUSrc<=1'b0;
 96 | MemRead<=1'b0;
 97 | MemWrite<=1'b0;
 98 | MemToReg<=1'bx;
 99 | Branch<=1'b1;
100 | Jump<=1'b0;
101 | end
102 | //end
103 | addi:begin//addi
104 | ALUOp<=3'b000;
105 | RegDest<=1'b0;
106 | RegWrite<=1'b1;
107 | ALUSrc<=1'b1;
108 | MemRead<=1'b0;
109 | MemWrite<=1'b0;
110 | MemToReg<=1'b0;
111 | Branch<=1'b0;
112 | Jump<=1'b0;
113 | end
114 | slti:begin//slti
115 | ALUOp<=3'b111;
116 | RegDest<=1'b0;
117 | RegWrite<=1'b1;
118 | ALUSrc<=1'b1;
119 | MemRead<=1'b0;
120 | MemWrite<=1'b0;
121 | MemToReg<=1'b0;
122 | Branch<=1'b0;
123 | Jump<=1'b0;
124 | end
125 | andi:begin//andi
126 | ALUOp<=3'b011;
127 | RegDest<=1'b0;
128 | RegWrite<=1'b1;
129 | ALUSrc<=1'b1;
130 | MemRead<=1'b0;
131 | MemWrite<=1'b0;
132 | MemToReg<=1'b0;
133 | Branch<=1'b0;
134 | Jump<=1'b0;
135 | end
136 | ori:begin//ori
137 | ALUOp<=3'b100;
138 | RegDest<=1'b0;
139 | RegWrite<=1'b1;
140 | ALUSrc<=1'b1;
141 | MemRead<=1'b0;
142 | MemWrite<=1'b0;
143 | MemToReg<=1'b0;
144 | Branch<=1'b0;
145 | Jump<=1'b0;
146 | end
147 | // if you want to add new instructions add here
148 | endcase
149 | end
150 | 
151 | end
152 | endmodule
153 | 
154 | 	
155 | 	
156 | 	
157 | 	
158 | 	
159 | 	


--------------------------------------------------------------------------------
/mypip.v:
--------------------------------------------------------------------------------
  1 | module Mypip(input clk );
  2 | wire [31:0]ctrlSignals;
  3 | wire [31:0] instrWireID,nextPCID;
  4 | wire [31:0] instrWireEX,nextPCEX,readData1EX,readData2EX,NPC1EX,outSignEXTEX;
  5 | wire [4:0]writeRegWireEX;
  6 | wire [31:0]instrWireMEM,readData2MEM,ALUResultMEM,nextPCBranchMEM,NPC1MEM,nextPCMEM;
  7 | wire [4:0]writeRegWireMEM;
  8 | wire ZeroOutMEM;
  9 | wire [31:0]instrWireWB,ALUResultWB,outputDataWB;
 10 | wire [4:0]writeRegWireWB;
 11 | //
 12 | wire RegDestEX,RegWriteEX,ALUSrcEX,MemReadEX,MemWriteEX,MemToRegEX,BranchEX,JumpEX;
 13 | wire [3:0]ALUCtrlEX;
 14 | wire RegDestMEM,RegWriteMEM,ALUSrcMEM,MemReadMEM,MemWriteMEM,MemToRegMEM,BranchMEM,JumpMEM;
 15 | wire [3:0]ALUCtrlMEM;
 16 | wire RegDestWB,RegWriteWB,ALUSrcWB,MemReadWB,MemWriteWB,MemToRegWB,BranchWB,JumpWB;
 17 | wire [3:0]ALUCtrlWB;
 18 | //
 19 | wire dataStall;
 20 | wire controlStall;
 21 | 
 22 | wire [31:0]PC;
 23 | wire [31:0]nextPC;
 24 | wire [31:0]instrWire;
 25 | wire [2:0]ALUOp;
 26 | wire RegDest,RegWrite,ALUSrc,MemRead,MemWrite,MemToReg,Branch,Jump;
 27 | wire [31:0]instrWireIDhazard,instrWireHazard;
 28 | IMemBank u0(1'b1, PC,instrWire);/*IF*/
 29 | 
 30 | adder32bit u4(32'b100,PC,nextPC);/*IF*/
 31 | 
 32 | stallUnit u90(clk, instrWireID[25:21], instrWireID[20:16],instrWireID[31:26]/*opcode*/,instrWireID,
 33 | instrWireEX,instrWireMEM,writeRegWireWB,RegWriteWB,instrWireWB,dataStall);
 34 | 
 35 | Controlstall u92(clk,instrWireID[31:26],instrWireEX[31:26],instrWireMEM[31:26],/*instrWireWB[31:26],*/controlStall);//agar Dstall 0 nop be vorodi midim
 36 | 
 37 | //////////////////////////////////////////////////////
 38 | nopSet u91(clk,dataStall,controlStall,instrWire,instrWireID,instrWireHazard,instrWireIDhazard);
 39 | 
 40 | //////////////////////////////////////////////////////////
 41 | controlUnit u1(clk,instrWireIDhazard[31:26],instrWireIDhazard[5:0],//age enable 0bashe stall darim
 42 | ALUOp,RegDest,RegWrite,ALUSrc,MemRead,MemWrite,MemToReg,Branch,Jump,instrWireIDhazard);/*ID*/
 43 | /////////////////////////////////////////////////////
 44 | 
 45 | wire [4:0]writeRegWire;
 46 | mux2A u10(RegDest,instrWireID[20:16],instrWireID[15:11],writeRegWire);/*ID*/
 47 | 
 48 | wire [31:0]readData1,readData2;
 49 | wire [31:0]WBData;
 50 | RegFile u11(clk, instrWireID[25:21], instrWireID[20:16], 
 51 | writeRegWireWB, WBData, RegWriteWB, 
 52 | readData1, readData2);/*ID*//*WB*/
 53 | 
 54 | wire [31:0]ALUSrc1;
 55 | wire [31:0]outSignEXT;
 56 | signExt u2(instrWireID[15:0],outSignEXT);/*ID*/
 57 | mux2 u12(ALUSrcEX,readData2EX,outSignEXTEX,ALUSrc1);/*EX*/
 58 | 
 59 | wire [3:0]ALUCtrl;
 60 | ALUcontrol u13(clk,instrWireID[5:0],ALUOp,ALUCtrl);/*ID*/
 61 | 
 62 | wire [31:0]ALUResult;
 63 | wire ZeroOut;
 64 | ALU u14(readData1EX,ALUSrc1,ALUCtrlEX,ALUResult,ZeroOut, , );/*EX*/
 65 | 
 66 | wire [31:0]outputData;
 67 | DMemBank u15(MemReadMEM, MemWriteMEM,ALUResultMEM , readData2MEM, outputData);/*MEM*/
 68 | 
 69 | mux2 u16(MemToRegWB,ALUResultWB,outputDataWB,WBData);/*WB*/
 70 | ////////////////////////////////////////////////////////////
 71 | wire [31:0]outputSLL;
 72 | shiftLeft32bitLeft u3(outSignEXTEX,outputSLL);/*EX*/
 73 | 
 74 | wire [31:0]nextPCBranch;
 75 | adder32bit u5(nextPCEX,outputSLL,nextPCBranch);/*EX*/
 76 | 
 77 | wire branchEnable;
 78 | assign branchEnable= ZeroOutMEM & BranchMEM;/*MEM*/
 79 | 
 80 | wire [31:0]NPC0;
 81 | mux2 u6(branchEnable,nextPCMEM,nextPCBranchMEM,NPC0);/*MEM*/
 82 | 
 83 | wire [27:0]nextPCJump;
 84 | shiftLeftForJump u7(instrWireID[25:0],nextPCJump);/*ID*/
 85 | 
 86 | wire [31:0]NPC1;
 87 | concatForJump u20(nextPC[31:28],nextPCJump,NPC1);/*ID*/
 88 | 
 89 | wire [31:0]NPCValue;
 90 | mux2 u8(JumpMEM,NPC0,NPC1MEM,NPCValue);/*MEM*/
 91 | 
 92 | PCRegWrite u9(clk,NPCValue,PC,dataStall);/*MEM*/
 93 | 
 94 | ////////////////////////////////////////////////////////////
 95 | IFID p1(clk,instrWireHazard,nextPC,instrWireID,nextPCID,dataStall);
 96 | IDEX p2(clk,RegDest,RegWrite,ALUSrc,MemRead,MemWrite,MemToReg,Branch,Jump,ALUCtrl,
 97 | instrWireID,nextPCID,readData1,readData2,writeRegWire,outSignEXT,NPC1,
 98 | RegDestEX,RegWriteEX,ALUSrcEX,MemReadEX,MemWriteEX,MemToRegEX,BranchEX,JumpEX,ALUCtrlEX,
 99 | instrWireEX,nextPCEX,readData1EX,readData2EX,writeRegWireEX,outSignEXTEX,NPC1EX,1'b1);
100 | 
101 | EXMEM p3(clk,RegDestEX,RegWriteEX,ALUSrcEX,MemReadEX,MemWriteEX,MemToRegEX,BranchEX,JumpEX,ALUCtrlEX,
102 | instrWireEX,nextPCEX,readData2EX,ALUResult,writeRegWireEX,nextPCBranch,NPC1EX,ZeroOut,
103 | RegDestMEM,RegWriteMEM,ALUSrcMEM,MemReadMEM,MemWriteMEM,MemToRegMEM,BranchMEM,JumpMEM,ALUCtrlMEM,
104 | instrWireMEM,nextPCMEM,readData2MEM,ALUResultMEM,writeRegWireMEM,nextPCBranchMEM,NPC1MEM,ZeroOutMEM,1'b1);
105 | 
106 | MEMWB p4(clk,RegDestMEM,RegWriteMEM,ALUSrcMEM,MemReadMEM,MemWriteMEM,MemToRegMEM,BranchMEM,JumpMEM,ALUCtrlMEM,
107 | instrWireMEM,outputData,ALUResultMEM,writeRegWireMEM,
108 | RegDestWB,RegWriteWB,ALUSrcWB,MemReadWB,MemWriteWB,MemToRegWB,BranchWB,JumpWB,ALUCtrlWB,
109 | instrWireWB,outputDataWB,ALUResultWB,writeRegWireWB,1'b1);
110 | 
111 | endmodule
112 | 


--------------------------------------------------------------------------------
/InstMem.v:
--------------------------------------------------------------------------------
  1 | module IMemBank(input memread, input [31:0] address, output reg [31:0] readdata);
  2 |  
  3 |   reg [31:0] mem_array [255:0];
  4 |   reg [31:0]temp;
  5 |   integer i;
  6 |   initial begin
  7 |     for (i=11; i<255; i=i+1)   
  8 | 	begin
  9 |        	mem_array[i]=32'b0;
 10 | 	end
 11 |   end
 12 |   always@(memread, address, mem_array[address])
 13 |   begin
 14 |     if(memread)begin
 15 |       temp=address>>2;
 16 |       readdata=mem_array[temp];
 17 |     end
 18 |     //////////////////////////////////////////////////////////////////////////////////////////////////////// test bench!
 19 | 	//lvl 1
 20 | 	/*mem_array[0]={6'b0,5'b10,5'b1,5'b11,5'b0,6'b100000};//add reg3,reg2,reg1 =30
 21 | 	mem_array[1]={6'b0,5'b10,5'b1,5'b100,5'b0,6'b100010};//sub reg4,reg2,reg1 =10
 22 | 	mem_array[2]={6'b0,5'b10,5'b1,5'b101,5'b0,6'b100101};//or reg5,reg2,reg1 =30
 23 | 	mem_array[3]={6'b0,5'b10,5'b1,5'b110,5'b0,6'b100100};//and reg6,reg2,reg1 =0
 24 | 	mem_array[4]={6'b0,5'b10,5'b1,5'b111,5'b0,6'b101010};//stl reg7,reg2,reg1 =0
 25 | 	
 26 | 	mem_array[5]={6'b001000,5'b10,5'b1000,16'b1010};//addi r8,r2,10 =30
 27 | 	mem_array[6]={6'b001010,5'b10,5'b1001,16'b1010};//slti r9,r2,10 =0
 28 | 	mem_array[7]={6'b001101,5'b10,5'b1010,16'b1010};//ori r10,r2,10 =30
 29 | 	mem_array[8]={6'b001100,5'b10,5'b1011,16'b1010};//andi r11,r2,10 =0
 30 | 
 31 | 	mem_array[9]={6'b101011,5'b10,5'b0,16'b1};//sw reg0,1(reg2) =mem[21]<=0
 32 | 	mem_array[10]={6'b100011,5'b0,5'b1100,16'b0};//lw reg12,0(reg0) =reg[12]<=0
 33 | */
 34 | /////////////////////////////////////////////////////////////////////////////////////////////////////////////
 35 | 	//lvl 2
 36 | 	/*mem_array[0]={6'b0,5'b10,5'b1,5'b11,5'b0,6'b100000};//add reg3,reg2,reg1 =30
 37 | 	mem_array[1]={6'b0,5'b11,5'b1,5'b100,5'b0,6'b100010};//sub reg4,reg3,reg1 =20
 38 | 	mem_array[2]={6'b0,5'b100,5'b1,5'b101,5'b0,6'b100101};//or reg5,reg4,reg1 =30
 39 | 	mem_array[3]={6'b0,5'b10,5'b1,5'b110,5'b0,6'b100100};//and reg6,reg2,reg1 =0
 40 | 	mem_array[4]={6'b0,5'b10,5'b1,5'b111,5'b0,6'b101010};//stl reg7,reg2,reg1 =0
 41 | 	
 42 | 	mem_array[5]={6'b001000,5'b10,5'b1000,16'b1010};//addi r8,r2,10 =30
 43 | 	mem_array[6]={6'b001010,5'b1000,5'b1001,16'b1000000};//slti r9,r8,32 =1
 44 | 	mem_array[7]={6'b001101,5'b10,5'b1010,16'b1010};//ori r10,r2,10 =30
 45 | 	mem_array[8]={6'b001100,5'b1001,5'b1011,16'b1010};//andi r11,r9,10 =0
 46 | 
 47 | 	mem_array[9]={6'b101011,5'b1010,5'b1011,16'b1};//sw reg11,1(reg10) =mem[31]<=0
 48 | 	mem_array[10]={6'b100011,5'b1010,5'b1100,16'b01};//lw reg12,1(reg10) =reg[12]<=0*/
 49 | ///////////////////////////////////////////////////////////////////////////////////////////////////////////
 50 | 	//lvl 3
 51 | 	// mem_array[0]={6'b0,5'b10,5'b1,5'b11,5'b0,6'b100000};//add reg3,reg2,reg1 =30
 52 | 	// mem_array[1]={6'b0,5'b11,5'b1,5'b100,5'b0,6'b100010};//sub reg4,reg3,reg1 =20
 53 | 	// mem_array[2]={6'b0,5'b100,5'b1,5'b101,5'b0,6'b100101};//or reg5,reg4,reg1 =30
 54 | 
 55 | 	// mem_array[3]={6'b100,5'b100,5'b101,16'b10};//beq r4,r5,2ta
 56 | 
 57 | 	// mem_array[4]={6'b0,5'b10,5'b1,5'b110,5'b0,6'b100100};//and reg6,reg2,reg1 =0
 58 | 
 59 | 	// mem_array[5]={6'b101,5'b110,5'b101,16'b1000};//bne r6,r5,2ta
 60 | 
 61 | 	// mem_array[6]={6'b0,5'b10,5'b1,5'b111,5'b0,6'b101010};//stl reg7,reg2,reg1 =0
 62 | 
 63 | 	// mem_array[7]={6'b10,26'b100};//jump lable4 13 ya 14
 64 | 
 65 | 	// mem_array[8]={6'b001000,5'b10,5'b1000,16'b1010};//addi r8,r2,10 =30
 66 | 	// mem_array[9]={6'b001010,5'b1000,5'b1001,16'b1000000};//slti r9,r8,32 =1
 67 | 	// mem_array[10]={6'b001101,5'b10,5'b1010,16'b1010};//ori r10,r2,10 =30
 68 | 	// mem_array[11]={6'b001100,5'b1001,5'b1011,16'b1010};//andi r11,r9,10 =0
 69 | 
 70 | 	// mem_array[12]={6'b101011,5'b1010,5'b1011,16'b1};//sw reg11,1(reg10) =mem[31]<=0
 71 | 	// mem_array[13]={6'b100011,5'b1010,5'b1100,16'b01};//lw reg12,1(reg10) =reg[12]<=0
 72 | 
 73 | 
 74 | /*
 75 | 	//r2=max , r3=min , r4=1 , r5=i , r6=adress , r7=current
 76 | 	mem_array[0]={6'b001000,5'b0,5'b10,16'b1010};//addi r2,r0,10
 77 | 	mem_array[1]={6'b001000,5'b0,5'b11,16'b1010};//addi r3,r0,10
 78 | 	mem_array[2]={6'b001000,5'b0,5'b100,16'b1};//addi r4,r0,1
 79 | 	mem_array[3]={6'b001000,5'b0,5'b101,16'b1};//addi r5,r0,1
 80 | 	//loop:
 81 | 	mem_array[4]={6'b0,5'b0,5'b00101,5'b00110,11'b0};//add r6,r0,r5
 82 | 	mem_array[5]={6'b100011,5'b00110,5'b00111,16'b0};//lw r7,0(r6)
 83 | 	mem_array[6]={6'b0,5'b10,5'b111,5'b01000,5'b0,6'b101010};//slt r8,r7,r2
 84 | 	mem_array[7]={6'b100,5'b1000,5'b0,16'b10};//beq r8,r0,lable1
 85 | 	mem_array[8]={6'b10,26'b1010};//jump lable2 adrese 9 ya 8
 86 | 	//lable1
 87 | 	mem_array[9]={6'b1000,5'b111,5'b10,16'b0};//addi r2,r7,0
 88 | 	//lable2:
 89 | 	mem_array[10]={6'b0,5'b11,5'b111,5'b1000,5'b0,6'b101010};//slt r8,r3,r7
 90 | 	mem_array[11]={6'b100,5'b1000,5'b0,16'b10};//beq r8,r0,lable3
 91 | 	mem_array[12]={6'b10,26'b1110};//jump lable4 13 ya 14
 92 | 	//lable3:
 93 | 	mem_array[13]={6'b1000,5'b111,5'b11,16'b0};//addi r3,r7,0
 94 | 	//lable4
 95 | 	mem_array[14]={6'b1000,5'b101,5'b101,16'b1};//addi r5,r5,1
 96 | 	mem_array[15]={6'b1010,5'b100,5'b1001,16'b1011};//slti r9,r5,11
 97 | 	mem_array[16]={6'b100,5'b1001,5'b100,16'b1111111111110100};//beq r9,r4,loop
 98 | */
 99 |   end
100 | endmodule
101 | 
102 | 


--------------------------------------------------------------------------------