├── .cproject ├── .gitignore ├── .project ├── .pydevproject ├── .settings └── language.settings.xml ├── .svproject ├── ChangeLog.txt ├── LICENSE ├── README.md ├── doc ├── fwrisc_design.md ├── fwrisc_diagram.graphml ├── fwrisc_diagram.png ├── fwrisc_formal_testbench_diagram.graphml ├── fwrisc_formal_testbench_diagram.png ├── fwrisc_quickstart.md ├── fwrisc_setup.md ├── fwrisc_synthesis.md ├── fwrisc_testbench_diagram.graphml ├── fwrisc_testbench_diagram.png ├── fwrisc_tools.md ├── fwrisc_verification.md ├── fwrisc_zephyr.md └── imgs │ ├── Philosophers.gif │ ├── csrrc.json │ ├── csrrc.png │ ├── csrrc_2.json │ ├── csrrs.json │ ├── csrrs.pmg │ ├── csrrs.png │ ├── csrrw.json │ ├── csrrw.png │ ├── exception.json │ ├── fwrisc_state_machine.epgz │ ├── memread.json │ ├── unit_testbench.epgz │ ├── unit_testbench.png │ └── unit_testbench_crop.png ├── etc ├── fwrisc_env.sh ├── ivpm.info └── packages.mf ├── requirements.txt ├── rtl ├── fwrisc.f ├── fwrisc.sv ├── fwrisc_alu.sv ├── fwrisc_alu_op.svh ├── fwrisc_c_decode.sv ├── fwrisc_csr_addr.svh ├── fwrisc_decode.sv ├── fwrisc_defines.vh ├── fwrisc_exec.sv ├── fwrisc_fetch.sv ├── fwrisc_mem.sv ├── fwrisc_mem_op.svh ├── fwrisc_mul_div_shift.sv ├── fwrisc_mul_div_shift_op.svh ├── fwrisc_op_type.svh ├── fwrisc_regfile.sv ├── fwrisc_system_op.svh ├── fwrisc_tracer.sv ├── regs.hex └── sav │ ├── fwrisc.sv.orig │ ├── fwrisc.sv.orig.sav │ ├── fwrisc_comparator.sv │ └── fwrisc_dbus_if.sv ├── scripts ├── ivpm.mk └── ivpm.py ├── soc ├── fwrisc_fpga_top.sv └── fwrisc_soc.f ├── sve.F ├── synth ├── intel │ └── fwrisc │ │ ├── fwrisc.qpf │ │ ├── fwrisc.qsf │ │ └── fwrisc.sdc ├── lattice │ └── icestorm │ │ ├── Makefile │ │ └── cmds.do └── microsemi │ ├── .gitignore │ ├── Makefile │ ├── bitstream │ └── fwrisc_fpga_top.stp │ ├── constraints │ ├── fwrisc_fpga_top.pdc │ └── fwrisc_fpga_top.sdc │ ├── fwrisc_decode_regfile │ ├── fwrisc_decode_regfile.prj │ └── fwrisc_decode_regfile.sv │ ├── scripts │ └── fwrisc_synthesis.tcl │ ├── sw │ ├── led_flash │ │ ├── CMakeLists.txt │ │ └── src │ │ │ └── led_flash.c │ └── rom.hex │ └── synplify │ ├── fwrisc │ ├── fwrisc.prd │ ├── fwrisc.prj │ ├── fwrisc_alu_op.svh │ ├── fwrisc_csr_addr.svh │ ├── fwrisc_mem_op.svh │ ├── fwrisc_mul_div_shift_op.svh │ ├── fwrisc_op_type.svh │ └── fwrisc_system_op.svh │ └── fwrisc_area.prj └── ve ├── fwrisc ├── fwrisc.F ├── sim │ ├── .simscripts │ ├── scripts │ │ ├── Makefile │ │ ├── embedded.mk │ │ ├── mk_instr_tests.sh │ │ ├── status.sh │ │ ├── vlog.f │ │ ├── vlog_hdl.f │ │ ├── vlog_hdl_ms.f │ │ ├── vlog_hvl.f │ │ ├── vlog_hvl_ms.f │ │ ├── vlog_ms.f │ │ └── vlog_vl-pyhpi_hdl.f │ ├── testlists │ │ ├── fwrisc_riscv_all_tests.tl │ │ ├── fwrisc_riscv_compliance_tests.tl │ │ ├── fwrisc_riscv_instr_tests.tl │ │ ├── fwrisc_riscv_ripe_tests.tl │ │ └── fwrisc_riscv_unit_tests.f │ └── tests │ │ ├── fwrisc_instr_tests_arith_add.f │ │ ├── fwrisc_instr_tests_arith_addi.f │ │ ├── fwrisc_instr_tests_arith_addi_neg.f │ │ ├── fwrisc_instr_tests_arith_and.f │ │ ├── fwrisc_instr_tests_arith_andi.f │ │ ├── fwrisc_instr_tests_arith_or.f │ │ ├── fwrisc_instr_tests_arith_ori.f │ │ ├── fwrisc_instr_tests_arith_sll.f │ │ ├── fwrisc_instr_tests_arith_slli.f │ │ ├── fwrisc_instr_tests_arith_slt_f.f │ │ ├── fwrisc_instr_tests_arith_slt_t_neg.f │ │ ├── fwrisc_instr_tests_arith_slt_t_pos.f │ │ ├── fwrisc_instr_tests_arith_slti_f.f │ │ ├── fwrisc_instr_tests_arith_slti_t.f │ │ ├── fwrisc_instr_tests_arith_sltu_t.f │ │ ├── fwrisc_instr_tests_arith_sra.f │ │ ├── fwrisc_instr_tests_arith_srai.f │ │ ├── fwrisc_instr_tests_arith_srl.f │ │ ├── fwrisc_instr_tests_arith_srli.f │ │ ├── fwrisc_instr_tests_arith_sub.f │ │ ├── fwrisc_instr_tests_arith_xor.f │ │ ├── fwrisc_instr_tests_arith_xori.f │ │ ├── fwrisc_instr_tests_branch_beq_f_back.f │ │ ├── fwrisc_instr_tests_branch_beq_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_beq_t_back.f │ │ ├── fwrisc_instr_tests_branch_beq_t_fwd.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_blt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_blt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bne_f_back.f │ │ ├── fwrisc_instr_tests_branch_bne_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_bne_t_back.f │ │ ├── fwrisc_instr_tests_branch_bne_t_fwd.f │ │ ├── fwrisc_instr_tests_counters_cycle.f │ │ ├── fwrisc_instr_tests_exception_bne.f │ │ ├── fwrisc_instr_tests_exception_j.f │ │ ├── fwrisc_instr_tests_exception_jalr.f │ │ ├── fwrisc_instr_tests_exception_lw.f │ │ ├── fwrisc_instr_tests_jump_j.f │ │ ├── fwrisc_instr_tests_jump_jal.f │ │ ├── fwrisc_instr_tests_jump_jalr.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_neg.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_pos.f │ │ ├── fwrisc_instr_tests_ldst_lb.f │ │ ├── fwrisc_instr_tests_ldst_lb_s.f │ │ ├── fwrisc_instr_tests_ldst_lb_u.f │ │ ├── fwrisc_instr_tests_ldst_lh_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_u.f │ │ ├── fwrisc_instr_tests_ldst_lhu_s.f │ │ ├── fwrisc_instr_tests_ldst_lw.f │ │ ├── fwrisc_instr_tests_ldst_sb_lw.f │ │ ├── fwrisc_instr_tests_ldst_sh_lw.f │ │ ├── fwrisc_instr_tests_ldst_sw_lw.f │ │ ├── fwrisc_instr_tests_long_loop.f │ │ ├── fwrisc_instr_tests_lui.f │ │ ├── fwrisc_instr_tests_system_csrc.f │ │ ├── fwrisc_instr_tests_system_csrr.f │ │ ├── fwrisc_instr_tests_system_csrs.f │ │ ├── fwrisc_instr_tests_system_csrsi.f │ │ ├── fwrisc_instr_tests_system_csrw.f │ │ ├── fwrisc_instr_tests_system_csrw_csrr.f │ │ ├── fwrisc_instr_tests_system_ecall.f │ │ ├── fwrisc_instr_tests_system_eret.f │ │ ├── fwrisc_ripe_1.f │ │ ├── fwrisc_ripe_2.f │ │ ├── fwrisc_ripe_3.f │ │ ├── fwrisc_ripe_4.f │ │ ├── fwrisc_ripe_5.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADD-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AND-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ANDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BEQ-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGEU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BNE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRCI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRSI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRWI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-DELAY_SLOTS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-EBREAK-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ECALL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ENDIANESS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-FENCE.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-IO.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JAL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JALR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LBU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LHU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LUI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_JMP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_LDST-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-NOP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-OR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ORI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_size-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_width-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRA-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRAI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SUB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XOR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XORI-01.f │ │ ├── fwrisc_zephyr_dhrystone.f │ │ ├── fwrisc_zephyr_hello_world.f │ │ ├── fwrisc_zephyr_philosophers.f │ │ └── fwrisc_zephyr_synchronization.f ├── tb │ ├── fwrisc_tb_hdl.sv │ ├── fwrisc_tb_hvl.sv │ ├── tb.F │ └── vl │ │ ├── fwrisc_tb_hdl.cpp │ │ ├── fwrisc_tb_hdl.h │ │ └── fwrisc_tb_vl.mk └── tests │ ├── cpp │ ├── ElfDataReader.cpp │ ├── ElfDataReader.h │ ├── ElfFileReader.cpp │ ├── ElfFileReader.h │ ├── ElfSymtabReader.cpp │ ├── ElfSymtabReader.h │ ├── fwrisc_ctest_base.cpp │ ├── fwrisc_ctest_base.h │ ├── fwrisc_instr_tests.cpp │ ├── fwrisc_instr_tests.h │ ├── fwrisc_instr_tests_counters.cpp │ ├── fwrisc_instr_tests_counters.h │ ├── fwrisc_perf_tests.cpp │ ├── fwrisc_perf_tests.h │ ├── fwrisc_ripe_tests.cpp │ ├── fwrisc_ripe_tests.h │ ├── fwrisc_zephyr_tests.cpp │ ├── fwrisc_zephyr_tests.h │ ├── riscv_compliance_tests.cpp │ └── riscv_compliance_tests.h │ ├── dhrystone │ ├── CMakeLists.txt │ ├── dhrystone.mk │ └── src │ │ ├── dhrystone.c │ │ ├── dhrystone.h │ │ ├── dhrystone_main.c │ │ └── util.h │ ├── fwrisc_tests.mk │ ├── pyfv-hpi │ └── fwrisc_tests │ │ ├── __init__.py │ │ ├── base.py │ │ ├── instr.py │ │ ├── riscv_compliance.py │ │ └── zephyr.py │ ├── riscv-compliance │ ├── .gitignore │ ├── COPYING.BSD │ ├── COPYING.CC │ ├── ChangeLog │ ├── Makefile │ ├── README.md │ ├── doc │ │ ├── .gitignore │ │ ├── ChangeLog │ │ ├── Makefile │ │ ├── README.adoc │ │ └── custom.wordlist │ ├── riscv-target │ │ ├── Codasip-simulator │ │ │ ├── compliance_io.h │ │ │ ├── compliance_test.h │ │ │ └── device │ │ │ │ └── rv32i │ │ │ │ └── Makefile.include │ │ ├── README.md │ │ ├── riscvOVPsim │ │ │ ├── README.md │ │ │ ├── compliance_io.h │ │ │ ├── compliance_test.h │ │ │ └── device │ │ │ │ ├── rv32i │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32im │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32imc │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32mi │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32si │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32ua │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32uc │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32ud │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32uf │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32ui │ │ │ │ └── Makefile.include │ │ │ │ ├── rv64i │ │ │ │ └── Makefile.include │ │ │ │ └── rv64im │ │ │ │ └── Makefile.include │ │ └── spike │ │ │ ├── compliance_io.h │ │ │ ├── compliance_test.h │ │ │ └── device │ │ │ ├── rv32i │ │ │ └── Makefile.include │ │ │ ├── rv32im │ │ │ └── Makefile.include │ │ │ ├── rv32imc │ │ │ └── Makefile.include │ │ │ ├── rv32mi │ │ │ └── Makefile.include │ │ │ ├── rv32si │ │ │ └── Makefile.include │ │ │ ├── rv32ua │ │ │ └── Makefile.include │ │ │ ├── rv32uc │ │ │ └── Makefile.include │ │ │ ├── rv32ud │ │ │ └── Makefile.include │ │ │ ├── rv32uf │ │ │ └── Makefile.include │ │ │ ├── rv32ui │ │ │ └── Makefile.include │ │ │ ├── rv64i │ │ │ └── Makefile.include │ │ │ └── rv64im │ │ │ └── Makefile.include │ ├── riscv-test-env │ │ ├── LICENSE │ │ ├── aw_test_macros.h │ │ ├── encoding.h │ │ ├── p │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ ├── pm │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ ├── pt │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ ├── test_macros.h │ │ ├── v │ │ │ ├── entry.S │ │ │ ├── link.ld │ │ │ ├── riscv_test.h │ │ │ ├── string.c │ │ │ └── vm.c │ │ └── verify.sh │ └── riscv-test-suite │ │ ├── rv32i │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── I-ADD-01.reference_output │ │ │ ├── I-ADDI-01.reference_output │ │ │ ├── I-AND-01.reference_output │ │ │ ├── I-ANDI-01.reference_output │ │ │ ├── I-AUIPC-01.reference_output │ │ │ ├── I-BEQ-01.reference_output │ │ │ ├── I-BGE-01.reference_output │ │ │ ├── I-BGEU-01.reference_output │ │ │ ├── I-BLT-01.reference_output │ │ │ ├── I-BLTU-01.reference_output │ │ │ ├── I-BNE-01.reference_output │ │ │ ├── I-CSRRC-01.reference_output │ │ │ ├── I-CSRRCI-01.reference_output │ │ │ ├── I-CSRRS-01.reference_output │ │ │ ├── I-CSRRSI-01.reference_output │ │ │ ├── I-CSRRW-01.reference_output │ │ │ ├── I-CSRRWI-01.reference_output │ │ │ ├── I-DELAY_SLOTS-01.reference_output │ │ │ ├── I-EBREAK-01.reference_output │ │ │ ├── I-ECALL-01.reference_output │ │ │ ├── I-ENDIANESS-01.reference_output │ │ │ ├── I-FENCE.I-01.reference_output │ │ │ ├── I-IO.reference_output │ │ │ ├── I-JAL-01.reference_output │ │ │ ├── I-JALR-01.reference_output │ │ │ ├── I-LB-01.reference_output │ │ │ ├── I-LBU-01.reference_output │ │ │ ├── I-LH-01.reference_output │ │ │ ├── I-LHU-01.reference_output │ │ │ ├── I-LUI-01.reference_output │ │ │ ├── I-LW-01.reference_output │ │ │ ├── I-MISALIGN_JMP-01.reference_output │ │ │ ├── I-MISALIGN_LDST-01.reference_output │ │ │ ├── I-NOP-01.reference_output │ │ │ ├── I-OR-01.reference_output │ │ │ ├── I-ORI-01.reference_output │ │ │ ├── I-RF_size-01.reference_output │ │ │ ├── I-RF_width-01.reference_output │ │ │ ├── I-RF_x0-01.reference_output │ │ │ ├── I-SB-01.reference_output │ │ │ ├── I-SH-01.reference_output │ │ │ ├── I-SLL-01.reference_output │ │ │ ├── I-SLLI-01.reference_output │ │ │ ├── I-SLT-01.reference_output │ │ │ ├── I-SLTI-01.reference_output │ │ │ ├── I-SLTIU-01.reference_output │ │ │ ├── I-SLTU-01.reference_output │ │ │ ├── I-SRA-01.reference_output │ │ │ ├── I-SRAI-01.reference_output │ │ │ ├── I-SRL-01.reference_output │ │ │ ├── I-SRLI-01.reference_output │ │ │ ├── I-SUB-01.reference_output │ │ │ ├── I-SW-01.reference_output │ │ │ ├── I-XOR-01.reference_output │ │ │ └── I-XORI-01.reference_output │ │ └── src │ │ │ ├── I-ADD-01.S │ │ │ ├── I-ADDI-01.S │ │ │ ├── I-AND-01.S │ │ │ ├── I-ANDI-01.S │ │ │ ├── I-AUIPC-01.S │ │ │ ├── I-BEQ-01.S │ │ │ ├── I-BGE-01.S │ │ │ ├── I-BGEU-01.S │ │ │ ├── I-BLT-01.S │ │ │ ├── I-BLTU-01.S │ │ │ ├── I-BNE-01.S │ │ │ ├── I-CSRRC-01.S │ │ │ ├── I-CSRRCI-01.S │ │ │ ├── I-CSRRS-01.S │ │ │ ├── I-CSRRSI-01.S │ │ │ ├── I-CSRRW-01.S │ │ │ ├── I-CSRRWI-01.S │ │ │ ├── I-DELAY_SLOTS-01.S │ │ │ ├── I-EBREAK-01.S │ │ │ ├── I-ECALL-01.S │ │ │ ├── I-ENDIANESS-01.S │ │ │ ├── I-FENCE.I-01.S │ │ │ ├── I-IO.S │ │ │ ├── I-JAL-01.S │ │ │ ├── I-JALR-01.S │ │ │ ├── I-LB-01.S │ │ │ ├── I-LBU-01.S │ │ │ ├── I-LH-01.S │ │ │ ├── I-LHU-01.S │ │ │ ├── I-LUI-01.S │ │ │ ├── I-LW-01.S │ │ │ ├── I-MISALIGN_JMP-01.S │ │ │ ├── I-MISALIGN_LDST-01.S │ │ │ ├── I-NOP-01.S │ │ │ ├── I-OR-01.S │ │ │ ├── I-ORI-01.S │ │ │ ├── I-RF_size-01.S │ │ │ ├── I-RF_width-01.S │ │ │ ├── I-RF_x0-01.S │ │ │ ├── I-SB-01.S │ │ │ ├── I-SH-01.S │ │ │ ├── I-SLL-01.S │ │ │ ├── I-SLLI-01.S │ │ │ ├── I-SLT-01.S │ │ │ ├── I-SLTI-01.S │ │ │ ├── I-SLTIU-01.S │ │ │ ├── I-SLTU-01.S │ │ │ ├── I-SRA-01.S │ │ │ ├── I-SRAI-01.S │ │ │ ├── I-SRL-01.S │ │ │ ├── I-SRLI-01.S │ │ │ ├── I-SUB-01.S │ │ │ ├── I-SW-01.S │ │ │ ├── I-XOR-01.S │ │ │ └── I-XORI-01.S │ │ ├── rv32im │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── DIV.reference_output │ │ │ ├── DIVU.reference_output │ │ │ ├── MUL.reference_output │ │ │ ├── MULH.reference_output │ │ │ ├── MULHSU.reference_output │ │ │ ├── MULHU.reference_output │ │ │ ├── REM.reference_output │ │ │ └── REMU.reference_output │ │ └── src │ │ │ ├── DIV.S │ │ │ ├── DIVU.S │ │ │ ├── MUL.S │ │ │ ├── MULH.S │ │ │ ├── MULHSU.S │ │ │ ├── MULHU.S │ │ │ ├── REM.S │ │ │ └── REMU.S │ │ ├── rv32imc │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── C-ADD.reference_output │ │ │ ├── C-ADDI.reference_output │ │ │ ├── C-ADDI16SP.reference_output │ │ │ ├── C-ADDI4SPN.reference_output │ │ │ ├── C-AND.reference_output │ │ │ ├── C-ANDI.reference_output │ │ │ ├── C-BEQZ.reference_output │ │ │ ├── C-BNEZ.reference_output │ │ │ ├── C-J.reference_output │ │ │ ├── C-JAL.reference_output │ │ │ ├── C-JALR.reference_output │ │ │ ├── C-JR.reference_output │ │ │ ├── C-LI.reference_output │ │ │ ├── C-LUI.reference_output │ │ │ ├── C-LW.reference_output │ │ │ ├── C-LWSP.reference_output │ │ │ ├── C-MV.reference_output │ │ │ ├── C-OR.reference_output │ │ │ ├── C-SLLI.reference_output │ │ │ ├── C-SRAI.reference_output │ │ │ ├── C-SRLI.reference_output │ │ │ ├── C-SUB.reference_output │ │ │ ├── C-SW.reference_output │ │ │ ├── C-SWSP.reference_output │ │ │ └── C-XOR.reference_output │ │ └── src │ │ │ ├── C-ADD.S │ │ │ ├── C-ADDI.S │ │ │ ├── C-ADDI16SP.S │ │ │ ├── C-ADDI4SPN.S │ │ │ ├── C-AND.S │ │ │ ├── C-ANDI.S │ │ │ ├── C-BEQZ.S │ │ │ ├── C-BNEZ.S │ │ │ ├── C-J.S │ │ │ ├── C-JAL.S │ │ │ ├── C-JALR.S │ │ │ ├── C-JR.S │ │ │ ├── C-LI.S │ │ │ ├── C-LUI.S │ │ │ ├── C-LW.S │ │ │ ├── C-LWSP.S │ │ │ ├── C-MV.S │ │ │ ├── C-OR.S │ │ │ ├── C-SLLI.S │ │ │ ├── C-SRAI.S │ │ │ ├── C-SRLI.S │ │ │ ├── C-SUB.S │ │ │ ├── C-SW.S │ │ │ ├── C-SWSP.S │ │ │ └── C-XOR.S │ │ ├── rv32mi │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── breakpoint.reference_output │ │ │ ├── csr.reference_output │ │ │ ├── illegal.reference_output │ │ │ ├── ma_addr.reference_output │ │ │ ├── ma_fetch.reference_output │ │ │ ├── mcsr.reference_output │ │ │ ├── sbreak.reference_output │ │ │ ├── scall.reference_output │ │ │ └── shamt.reference_output │ │ ├── rv64mi │ │ │ ├── Makefrag │ │ │ ├── access.S │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ └── scall.S │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ └── src │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── shamt.S │ │ ├── rv32si │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── csr.reference_output │ │ │ ├── dirty.reference_output │ │ │ ├── ma_fetch.reference_output │ │ │ ├── sbreak.reference_output │ │ │ ├── scall.reference_output │ │ │ └── wfi.reference_output │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ ├── rv32ua │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── amoadd_w.reference_output │ │ │ ├── amoand_w.reference_output │ │ │ ├── amomax_w.reference_output │ │ │ ├── amomaxu_w.reference_output │ │ │ ├── amomin_w.reference_output │ │ │ ├── amominu_w.reference_output │ │ │ ├── amoor_w.reference_output │ │ │ ├── amoswap_w.reference_output │ │ │ ├── amoxor_w.reference_output │ │ │ └── lrsc.reference_output │ │ ├── rv64ua │ │ │ ├── Makefrag │ │ │ ├── amoadd_d.S │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_d.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_d.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_d.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_d.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_d.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_d.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_d.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_d.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ │ ├── rv32uc │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ └── rvc.reference_output │ │ ├── rv64uc │ │ │ ├── Makefrag │ │ │ └── rvc.S │ │ └── src │ │ │ ├── Makefrag │ │ │ └── rvc.S │ │ ├── rv32ud │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── fadd.reference_output │ │ │ ├── fclass.reference_output │ │ │ ├── fcmp.reference_output │ │ │ ├── fcvt.reference_output │ │ │ ├── fdiv.reference_output │ │ │ ├── fmadd.reference_output │ │ │ ├── fmin.reference_output │ │ │ ├── ldst.reference_output │ │ │ └── recoding.reference_output │ │ ├── rv64ud │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ ├── recoding.S │ │ │ └── structural.S │ │ └── src │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ │ ├── rv32uf │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── fadd.reference_output │ │ │ ├── fclass.reference_output │ │ │ ├── fcmp.reference_output │ │ │ ├── fcvt.reference_output │ │ │ ├── fcvt_w.reference_output │ │ │ ├── fdiv.reference_output │ │ │ ├── fmadd.reference_output │ │ │ ├── fmin.reference_output │ │ │ ├── ldst.reference_output │ │ │ ├── move.reference_output │ │ │ └── recoding.reference_output │ │ ├── rv64uf │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ │ ├── rv32ui │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── add.reference_output │ │ │ ├── addi.reference_output │ │ │ ├── and.reference_output │ │ │ ├── andi.reference_output │ │ │ ├── auipc.reference_output │ │ │ ├── beq.reference_output │ │ │ ├── bge.reference_output │ │ │ ├── bgeu.reference_output │ │ │ ├── blt.reference_output │ │ │ ├── bltu.reference_output │ │ │ ├── bne.reference_output │ │ │ ├── fence_i.reference_output │ │ │ ├── jal.reference_output │ │ │ ├── jalr.reference_output │ │ │ ├── lb.reference_output │ │ │ ├── lbu.reference_output │ │ │ ├── lh.reference_output │ │ │ ├── lhu.reference_output │ │ │ ├── lui.reference_output │ │ │ ├── lw.reference_output │ │ │ ├── or.reference_output │ │ │ ├── ori.reference_output │ │ │ ├── sb.reference_output │ │ │ ├── sh.reference_output │ │ │ ├── simple.reference_output │ │ │ ├── sll.reference_output │ │ │ ├── slli.reference_output │ │ │ ├── slt.reference_output │ │ │ ├── slti.reference_output │ │ │ ├── sltiu.reference_output │ │ │ ├── sltu.reference_output │ │ │ ├── sra.reference_output │ │ │ ├── srai.reference_output │ │ │ ├── srl.reference_output │ │ │ ├── sub.reference_output │ │ │ ├── sw.reference_output │ │ │ ├── xor.reference_output │ │ │ └── xori.reference_output │ │ ├── rv64ui │ │ │ ├── Makefrag │ │ │ ├── add.S │ │ │ ├── addi.S │ │ │ ├── addiw.S │ │ │ ├── addw.S │ │ │ ├── and.S │ │ │ ├── andi.S │ │ │ ├── auipc.S │ │ │ ├── beq.S │ │ │ ├── bge.S │ │ │ ├── bgeu.S │ │ │ ├── blt.S │ │ │ ├── bltu.S │ │ │ ├── bne.S │ │ │ ├── fence_i.S │ │ │ ├── jal.S │ │ │ ├── jalr.S │ │ │ ├── lb.S │ │ │ ├── lbu.S │ │ │ ├── ld.S │ │ │ ├── lh.S │ │ │ ├── lhu.S │ │ │ ├── lui.S │ │ │ ├── lw.S │ │ │ ├── lwu.S │ │ │ ├── or.S │ │ │ ├── ori.S │ │ │ ├── sb.S │ │ │ ├── sd.S │ │ │ ├── sh.S │ │ │ ├── simple.S │ │ │ ├── sll.S │ │ │ ├── slli.S │ │ │ ├── slliw.S │ │ │ ├── sllw.S │ │ │ ├── slt.S │ │ │ ├── slti.S │ │ │ ├── sltiu.S │ │ │ ├── sltu.S │ │ │ ├── sra.S │ │ │ ├── srai.S │ │ │ ├── sraiw.S │ │ │ ├── sraw.S │ │ │ ├── srl.S │ │ │ ├── srli.S │ │ │ ├── srliw.S │ │ │ ├── srlw.S │ │ │ ├── sub.S │ │ │ ├── subw.S │ │ │ ├── sw.S │ │ │ ├── xor.S │ │ │ └── xori.S │ │ └── src │ │ │ ├── Makefrag.spike │ │ │ ├── add.S │ │ │ ├── addi.S │ │ │ ├── and.S │ │ │ ├── andi.S │ │ │ ├── auipc.S │ │ │ ├── beq.S │ │ │ ├── bge.S │ │ │ ├── bgeu.S │ │ │ ├── blt.S │ │ │ ├── bltu.S │ │ │ ├── bne.S │ │ │ ├── fence_i.S │ │ │ ├── jal.S │ │ │ ├── jalr.S │ │ │ ├── lb.S │ │ │ ├── lbu.S │ │ │ ├── lh.S │ │ │ ├── lhu.S │ │ │ ├── lui.S │ │ │ ├── lw.S │ │ │ ├── or.S │ │ │ ├── ori.S │ │ │ ├── sb.S │ │ │ ├── sh.S │ │ │ ├── simple.S │ │ │ ├── sll.S │ │ │ ├── slli.S │ │ │ ├── slt.S │ │ │ ├── slti.S │ │ │ ├── sltiu.S │ │ │ ├── sltu.S │ │ │ ├── sra.S │ │ │ ├── srai.S │ │ │ ├── srl.S │ │ │ ├── srli.S │ │ │ ├── sub.S │ │ │ ├── sw.S │ │ │ ├── xor.S │ │ │ └── xori.S │ │ ├── rv64i │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── ADDIW.reference_output │ │ │ ├── ADDW.reference_output │ │ │ ├── SLLIW.reference_output │ │ │ ├── SLLW.reference_output │ │ │ ├── SRAIW.reference_output │ │ │ ├── SRAW.reference_output │ │ │ ├── SRLIW.reference_output │ │ │ ├── SRLW.reference_output │ │ │ └── SUBW.reference_output │ │ └── src │ │ │ ├── ADDIW.S │ │ │ ├── ADDW.S │ │ │ ├── SLLIW.S │ │ │ ├── SLLW.S │ │ │ ├── SRAIW.S │ │ │ ├── SRAW.S │ │ │ ├── SRLIW.S │ │ │ ├── SRLW.S │ │ │ └── SUBW.S │ │ └── rv64im │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ ├── DIVW.reference_output │ │ ├── MULW.reference_output │ │ ├── REMUW.reference_output │ │ └── REMW.reference_output │ │ └── src │ │ ├── DIVW.S │ │ ├── MULW.S │ │ ├── REMUW.S │ │ └── REMW.S │ ├── tests.F │ ├── unit │ ├── arith_add.S │ ├── arith_addi.S │ ├── arith_addi_neg.S │ ├── arith_and.S │ ├── arith_andi.S │ ├── arith_or.S │ ├── arith_ori.S │ ├── arith_sll.S │ ├── arith_slli.S │ ├── arith_slt_f.S │ ├── arith_slt_t_neg.S │ ├── arith_slt_t_pos.S │ ├── arith_slti_f.S │ ├── arith_slti_t.S │ ├── arith_sltu_t.S │ ├── arith_sra.S │ ├── arith_srai.S │ ├── arith_srl.S │ ├── arith_srli.S │ ├── arith_sub.S │ ├── arith_xor.S │ ├── arith_xori.S │ ├── branch_beq_f_back.S │ ├── branch_beq_f_fwd.S │ ├── branch_beq_t_back.S │ ├── branch_beq_t_fwd.S │ ├── branch_bge_eq_t_neg.S │ ├── branch_bge_eq_t_pos.S │ ├── branch_bge_gt_t_neg.S │ ├── branch_bge_gt_t_pos.S │ ├── branch_blt_t_neg.S │ ├── branch_blt_t_pos.S │ ├── branch_bltu_t_neg.S │ ├── branch_bltu_t_pos.S │ ├── branch_bne_f_back.S │ ├── branch_bne_f_fwd.S │ ├── branch_bne_t_back.S │ ├── branch_bne_t_fwd.S │ ├── exception_bne.S │ ├── exception_j.S │ ├── exception_jalr.S │ ├── exception_lw.S │ ├── jump_j.S │ ├── jump_jal.S │ ├── jump_jalr.S │ ├── jump_jalr_off_neg.S │ ├── jump_jalr_off_pos.S │ ├── ldst_lb.S │ ├── ldst_lb_s.S │ ├── ldst_lb_u.S │ ├── ldst_lh_s.S │ ├── ldst_lh_u.S │ ├── ldst_lhu_s.S │ ├── ldst_lw.S │ ├── ldst_sb_lw.S │ ├── ldst_sh_lw.S │ ├── ldst_sw_lw.S │ ├── long_loop.S │ ├── lui.S │ ├── system_csrc.S │ ├── system_csrr.S │ ├── system_csrs.S │ ├── system_csrsi.S │ ├── system_csrw.S │ ├── system_csrw_csrr.S │ ├── system_ecall.S │ ├── system_eret.S │ ├── unit.ld │ └── unit_header.h │ └── uvm │ ├── elf_symtab_reader.svh │ ├── fwrisc_instr_test.svh │ ├── fwrisc_riscv_compliance_tests.svh │ ├── fwrisc_test_base.svh │ └── fwrisc_tests_pkg.sv ├── fwrisc_decode_formal ├── formal │ ├── fwrisc_decode_formal.py │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_decode_formal.sby │ │ ├── status.sh │ │ └── vsc.py │ ├── testlists │ │ └── fwrisc_decode_formal_all.f │ └── tests │ │ ├── fwrisc_decode_formal_all_sims.py │ │ ├── fwrisc_decode_formal_i32_btype.f │ │ ├── fwrisc_decode_formal_i32_itype.f │ │ ├── fwrisc_decode_formal_i32_lui.f │ │ ├── fwrisc_decode_formal_i32_rtype.f │ │ └── fwrisc_decode_formal_tests.py ├── tb │ ├── fwrisc_decode_formal_i32_btype_checker.sv │ ├── fwrisc_decode_formal_i32_checker.sv │ ├── fwrisc_decode_formal_i32_itype_checker.sv │ ├── fwrisc_decode_formal_i32_lui_checker.sv │ ├── fwrisc_decode_formal_i32_rtype_checker.sv │ ├── fwrisc_decode_formal_smoke_checker.sv │ └── fwrisc_decode_formal_tb.sv └── tests │ ├── fwrisc_decode_formal_i32_btype_test.sv │ ├── fwrisc_decode_formal_i32_itype_test.sv │ ├── fwrisc_decode_formal_i32_lui_test.sv │ ├── fwrisc_decode_formal_i32_rtype_test.sv │ ├── fwrisc_decode_formal_opcode_defines.svh │ └── fwrisc_decode_formal_smoke_test.sv ├── fwrisc_exec_formal ├── formal │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_exec_formal.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_exec_formal_all.f │ └── tests │ │ ├── fwrisc_exec_formal_arith.f │ │ ├── fwrisc_exec_formal_branch.f │ │ ├── fwrisc_exec_formal_call.f │ │ ├── fwrisc_exec_formal_csr.f │ │ ├── fwrisc_exec_formal_jump.f │ │ ├── fwrisc_exec_formal_mds.f │ │ ├── fwrisc_exec_formal_mem.f │ │ └── fwrisc_exec_formal_smoke.f ├── sve.F ├── tb │ ├── fwrisc_exec_formal_arith_checker.sv │ ├── fwrisc_exec_formal_branch_checker.sv │ ├── fwrisc_exec_formal_call_checker.sv │ ├── fwrisc_exec_formal_csr_checker.sv │ ├── fwrisc_exec_formal_defines.svh │ ├── fwrisc_exec_formal_jump_checker.sv │ ├── fwrisc_exec_formal_mds_checker.sv │ ├── fwrisc_exec_formal_mem_checker.sv │ ├── fwrisc_exec_formal_smoke_checker.sv │ └── fwrisc_exec_formal_tb.sv └── tests │ ├── fwrisc_exec_formal_arith_test.sv │ ├── fwrisc_exec_formal_branch_test.sv │ ├── fwrisc_exec_formal_call_test.sv │ ├── fwrisc_exec_formal_csr_test.sv │ ├── fwrisc_exec_formal_jump_test.sv │ ├── fwrisc_exec_formal_mds_test.sv │ ├── fwrisc_exec_formal_mem_test.sv │ └── fwrisc_exec_formal_smoke_test.sv ├── fwrisc_fetch_formal ├── formal │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_fetch_formal.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_fetch_formal_all.f │ └── tests │ │ ├── fwrisc_fetch_formal_seq16.f │ │ ├── fwrisc_fetch_formal_seq32.f │ │ ├── fwrisc_fetch_formal_seqmix.f │ │ └── fwrisc_fetch_formal_smoke.f ├── tb │ ├── fwrisc_fetch_formal_defines.svh │ ├── fwrisc_fetch_formal_seqmix_checker.sv │ ├── fwrisc_fetch_formal_smoke_checker.sv │ └── fwrisc_fetch_formal_tb.sv └── tests │ ├── fwrisc_fetch_formal_seq16_test.sv │ ├── fwrisc_fetch_formal_seq32_test.sv │ ├── fwrisc_fetch_formal_seqmix_test.sv │ └── fwrisc_fetch_formal_smoke_test.sv ├── fwrisc_formal ├── sim │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_formal.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_formal_all.f │ └── tests │ │ ├── fwrisc_formal_add_i.f │ │ ├── fwrisc_formal_add_r.f │ │ ├── fwrisc_formal_and_r.f │ │ ├── fwrisc_formal_auipc.f │ │ ├── fwrisc_formal_jal.f │ │ ├── fwrisc_formal_jalr.f │ │ ├── fwrisc_formal_ld.f │ │ ├── fwrisc_formal_lui.f │ │ ├── fwrisc_formal_or_i.f │ │ ├── fwrisc_formal_or_r.f │ │ ├── fwrisc_formal_sll_i.f │ │ ├── fwrisc_formal_sll_r.f │ │ ├── fwrisc_formal_slt_i.f │ │ ├── fwrisc_formal_slt_r.f │ │ ├── fwrisc_formal_sltu_i.f │ │ ├── fwrisc_formal_sltu_r.f │ │ ├── fwrisc_formal_srl_r.f │ │ ├── fwrisc_formal_sub_r.f │ │ ├── fwrisc_formal_xor_i.f │ │ └── fwrisc_formal_xor_r.f ├── tb │ ├── fwrisc.sby │ ├── fwrisc_formal_arith_checker.sv │ ├── fwrisc_formal_jump_checker.sv │ ├── fwrisc_formal_ldst_checker.sv │ ├── fwrisc_formal_opcode_defines.svh │ └── fwrisc_formal_tb.sv └── tests │ ├── fwrisc_formal_add_i.svh │ ├── fwrisc_formal_add_r.svh │ ├── fwrisc_formal_and_r.svh │ ├── fwrisc_formal_auipc.svh │ ├── fwrisc_formal_jal.svh │ ├── fwrisc_formal_jalr.svh │ ├── fwrisc_formal_ld.svh │ ├── fwrisc_formal_lui.svh │ ├── fwrisc_formal_or_i.svh │ ├── fwrisc_formal_or_r.svh │ ├── fwrisc_formal_sll_i.svh │ ├── fwrisc_formal_sll_r.svh │ ├── fwrisc_formal_slt_i.svh │ ├── fwrisc_formal_slt_r.svh │ ├── fwrisc_formal_sltu_i.svh │ ├── fwrisc_formal_sltu_r.svh │ ├── fwrisc_formal_sra_r.svh │ ├── fwrisc_formal_srl_r.svh │ ├── fwrisc_formal_sub_r.svh │ ├── fwrisc_formal_xor_i.svh │ └── fwrisc_formal_xor_r.svh ├── fwrisc_fpga ├── sim │ ├── .simscripts │ ├── mk_testlist.sh │ ├── scripts │ │ ├── Makefile │ │ ├── embedded.mk │ │ ├── mk_instr_tests.sh │ │ ├── status.sh │ │ ├── vlog_hdl.f │ │ └── vlog_hvl.f │ ├── testlists │ │ ├── fwrisc_riscv_compliance_tests.tl │ │ └── fwrisc_riscv_unit_tests.f │ └── tests │ │ ├── fwrisc_fpga_led_flash.f │ │ └── fwrisc_fpga_zephyr_hello_world.f ├── tb │ ├── fwrisc_fpga_tb_hdl.sv │ └── tb.F └── tests │ ├── fwrisc_fpga_tests.cpp │ ├── fwrisc_fpga_tests.h │ ├── fwrisc_fpga_tests.mk │ └── sw │ ├── baremetal.ld │ ├── fwrisc_fpga_tests_sw.mk │ └── led_flash.S ├── fwrisc_mem ├── formal │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_mem.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_mem_all.f │ └── tests │ │ └── fwrisc_mem_smoke.f ├── tb │ ├── fwrisc_mem_defines.svh │ ├── fwrisc_mem_smoke_checker.sv │ └── fwrisc_mem_tb.sv └── tests │ └── fwrisc_mem_smoke_test.sv ├── fwrisc_mul_div_shift_formal ├── sim │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_mul_div_shift_formal.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_mul_div_shift_formal_all.f │ └── tests │ │ ├── fwrisc_mul_div_shift_formal_mul.f │ │ ├── fwrisc_mul_div_shift_formal_mulh.f │ │ ├── fwrisc_mul_div_shift_formal_muls.f │ │ ├── fwrisc_mul_div_shift_formal_mulsh.f │ │ ├── fwrisc_mul_div_shift_formal_shl.f │ │ ├── fwrisc_mul_div_shift_formal_sra.f │ │ └── fwrisc_mul_div_shift_formal_srl.f ├── tb │ ├── fwrisc_mul_div_shift_formal_mul_checker.sv │ ├── fwrisc_mul_div_shift_formal_shift_checker.sv │ └── fwrisc_mul_div_shift_formal_tb.sv └── tests │ ├── fwrisc_mul_div_shift_formal_mul.sv │ ├── fwrisc_mul_div_shift_formal_mulh.sv │ ├── fwrisc_mul_div_shift_formal_muls.sv │ ├── fwrisc_mul_div_shift_formal_mulsh.sv │ ├── fwrisc_mul_div_shift_formal_shl.sv │ ├── fwrisc_mul_div_shift_formal_sra.sv │ └── fwrisc_mul_div_shift_formal_srl.sv ├── fwrisc_rv32imc ├── fwrisc.F ├── sim │ ├── .simscripts │ ├── scripts │ │ ├── Makefile │ │ ├── embedded.mk │ │ ├── mk_instr_tests.sh │ │ ├── status.sh │ │ ├── vlog.f │ │ ├── vlog_hdl.f │ │ ├── vlog_hdl_ms.f │ │ ├── vlog_hvl.f │ │ ├── vlog_hvl_ms.f │ │ ├── vlog_ms.f │ │ └── vlog_vl-pyhpi_hdl.f │ ├── testlists │ │ ├── fwrisc_riscv_all_tests.tl │ │ ├── fwrisc_riscv_compliance_tests.tl │ │ ├── fwrisc_riscv_instr_tests.tl │ │ ├── fwrisc_riscv_ripe_tests.tl │ │ └── fwrisc_riscv_unit_tests.f │ └── tests │ │ ├── fwrisc_instr_tests_arith_add.f │ │ ├── fwrisc_instr_tests_arith_addi.f │ │ ├── fwrisc_instr_tests_arith_addi_neg.f │ │ ├── fwrisc_instr_tests_arith_and.f │ │ ├── fwrisc_instr_tests_arith_andi.f │ │ ├── fwrisc_instr_tests_arith_or.f │ │ ├── fwrisc_instr_tests_arith_ori.f │ │ ├── fwrisc_instr_tests_arith_sll.f │ │ ├── fwrisc_instr_tests_arith_slli.f │ │ ├── fwrisc_instr_tests_arith_slt_f.f │ │ ├── fwrisc_instr_tests_arith_slt_t_neg.f │ │ ├── fwrisc_instr_tests_arith_slt_t_pos.f │ │ ├── fwrisc_instr_tests_arith_slti_f.f │ │ ├── fwrisc_instr_tests_arith_slti_t.f │ │ ├── fwrisc_instr_tests_arith_sltu_t.f │ │ ├── fwrisc_instr_tests_arith_sra.f │ │ ├── fwrisc_instr_tests_arith_srai.f │ │ ├── fwrisc_instr_tests_arith_srl.f │ │ ├── fwrisc_instr_tests_arith_srli.f │ │ ├── fwrisc_instr_tests_arith_sub.f │ │ ├── fwrisc_instr_tests_arith_xor.f │ │ ├── fwrisc_instr_tests_arith_xori.f │ │ ├── fwrisc_instr_tests_branch_beq_f_back.f │ │ ├── fwrisc_instr_tests_branch_beq_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_beq_t_back.f │ │ ├── fwrisc_instr_tests_branch_beq_t_fwd.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_blt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_blt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bne_f_back.f │ │ ├── fwrisc_instr_tests_branch_bne_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_bne_t_back.f │ │ ├── fwrisc_instr_tests_branch_bne_t_fwd.f │ │ ├── fwrisc_instr_tests_counters_cycle.f │ │ ├── fwrisc_instr_tests_exception_bne.f │ │ ├── fwrisc_instr_tests_exception_dep_x.f │ │ ├── fwrisc_instr_tests_exception_j.f │ │ ├── fwrisc_instr_tests_exception_jalr.f │ │ ├── fwrisc_instr_tests_exception_lw.f │ │ ├── fwrisc_instr_tests_jump_j.f │ │ ├── fwrisc_instr_tests_jump_jal.f │ │ ├── fwrisc_instr_tests_jump_jalr.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_neg.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_pos.f │ │ ├── fwrisc_instr_tests_ldst_lb.f │ │ ├── fwrisc_instr_tests_ldst_lb_s.f │ │ ├── fwrisc_instr_tests_ldst_lb_u.f │ │ ├── fwrisc_instr_tests_ldst_lbu_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_u.f │ │ ├── fwrisc_instr_tests_ldst_lhu_s.f │ │ ├── fwrisc_instr_tests_ldst_lw.f │ │ ├── fwrisc_instr_tests_ldst_sb_lw.f │ │ ├── fwrisc_instr_tests_ldst_sh_lw.f │ │ ├── fwrisc_instr_tests_ldst_sw_lw.f │ │ ├── fwrisc_instr_tests_long_loop.f │ │ ├── fwrisc_instr_tests_lui.f │ │ ├── fwrisc_instr_tests_system_csrc.f │ │ ├── fwrisc_instr_tests_system_csrr.f │ │ ├── fwrisc_instr_tests_system_csrs.f │ │ ├── fwrisc_instr_tests_system_csrsi.f │ │ ├── fwrisc_instr_tests_system_csrw.f │ │ ├── fwrisc_instr_tests_system_csrw_csrr.f │ │ ├── fwrisc_instr_tests_system_ecall.f │ │ ├── fwrisc_instr_tests_system_eret.f │ │ ├── fwrisc_ripe_1.f │ │ ├── fwrisc_ripe_2.f │ │ ├── fwrisc_ripe_3.f │ │ ├── fwrisc_ripe_4.f │ │ ├── fwrisc_ripe_5.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADD-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AND-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ANDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BEQ-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGEU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BNE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRCI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRSI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRWI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-DELAY_SLOTS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-EBREAK-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ECALL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ENDIANESS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-FENCE.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-IO.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JAL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JALR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LBU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LHU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LUI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_JMP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_LDST-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-NOP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-OR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ORI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_size-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_width-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRA-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRAI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SUB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XOR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XORI-01.f │ │ ├── fwrisc_zephyr_dhrystone.f │ │ ├── fwrisc_zephyr_hello_world.f │ │ ├── fwrisc_zephyr_philosophers.f │ │ └── fwrisc_zephyr_synchronization.f ├── tb │ ├── fwrisc_tb_hdl.sv │ ├── fwrisc_tb_hvl.sv │ ├── tb.F │ └── vl │ │ ├── fwrisc_tb_hdl.cpp │ │ ├── fwrisc_tb_hdl.h │ │ └── fwrisc_tb_vl.mk └── tests │ ├── cpp │ ├── ElfDataReader.cpp │ ├── ElfDataReader.h │ ├── ElfFileReader.cpp │ ├── ElfFileReader.h │ ├── ElfSymtabReader.cpp │ ├── ElfSymtabReader.h │ ├── fwrisc_ctest_base.cpp │ ├── fwrisc_ctest_base.h │ ├── fwrisc_instr_tests.cpp │ ├── fwrisc_instr_tests.h │ ├── fwrisc_instr_tests_counters.cpp │ ├── fwrisc_instr_tests_counters.h │ ├── fwrisc_perf_tests.cpp │ ├── fwrisc_perf_tests.h │ ├── fwrisc_ripe_tests.cpp │ ├── fwrisc_ripe_tests.h │ ├── fwrisc_zephyr_tests.cpp │ ├── fwrisc_zephyr_tests.h │ ├── riscv_compliance_tests.cpp │ └── riscv_compliance_tests.h │ ├── dhrystone │ ├── CMakeLists.txt │ ├── dhrystone.mk │ └── src │ │ ├── dhrystone.c │ │ ├── dhrystone.h │ │ ├── dhrystone_main.c │ │ └── util.h │ ├── fwrisc_tests.mk │ ├── pyfv-hpi │ └── fwrisc_tests │ │ ├── __init__.py │ │ ├── base.py │ │ ├── instr.py │ │ ├── riscv_compliance.py │ │ └── zephyr.py │ ├── riscv-compliance │ ├── .gitignore │ ├── COPYING.BSD │ ├── COPYING.CC │ ├── ChangeLog │ ├── Makefile │ ├── README.md │ ├── doc │ │ ├── .gitignore │ │ ├── ChangeLog │ │ ├── Makefile │ │ ├── README.adoc │ │ └── custom.wordlist │ ├── riscv-target │ │ ├── Codasip-simulator │ │ │ ├── compliance_io.h │ │ │ ├── compliance_test.h │ │ │ └── device │ │ │ │ └── rv32i │ │ │ │ └── Makefile.include │ │ ├── README.md │ │ ├── riscvOVPsim │ │ │ ├── README.md │ │ │ ├── compliance_io.h │ │ │ ├── compliance_test.h │ │ │ └── device │ │ │ │ ├── rv32i │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32im │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32imc │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32mi │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32si │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32ua │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32uc │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32ud │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32uf │ │ │ │ └── Makefile.include │ │ │ │ ├── rv32ui │ │ │ │ └── Makefile.include │ │ │ │ ├── rv64i │ │ │ │ └── Makefile.include │ │ │ │ └── rv64im │ │ │ │ └── Makefile.include │ │ └── spike │ │ │ ├── compliance_io.h │ │ │ ├── compliance_test.h │ │ │ └── device │ │ │ ├── rv32i │ │ │ └── Makefile.include │ │ │ ├── rv32im │ │ │ └── Makefile.include │ │ │ ├── rv32imc │ │ │ └── Makefile.include │ │ │ ├── rv32mi │ │ │ └── Makefile.include │ │ │ ├── rv32si │ │ │ └── Makefile.include │ │ │ ├── rv32ua │ │ │ └── Makefile.include │ │ │ ├── rv32uc │ │ │ └── Makefile.include │ │ │ ├── rv32ud │ │ │ └── Makefile.include │ │ │ ├── rv32uf │ │ │ └── Makefile.include │ │ │ ├── rv32ui │ │ │ └── Makefile.include │ │ │ ├── rv64i │ │ │ └── Makefile.include │ │ │ └── rv64im │ │ │ └── Makefile.include │ ├── riscv-test-env │ │ ├── LICENSE │ │ ├── aw_test_macros.h │ │ ├── encoding.h │ │ ├── p │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ ├── pm │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ ├── pt │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ ├── test_macros.h │ │ ├── v │ │ │ ├── entry.S │ │ │ ├── link.ld │ │ │ ├── riscv_test.h │ │ │ ├── string.c │ │ │ └── vm.c │ │ └── verify.sh │ └── riscv-test-suite │ │ ├── rv32i │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── I-ADD-01.reference_output │ │ │ ├── I-ADDI-01.reference_output │ │ │ ├── I-AND-01.reference_output │ │ │ ├── I-ANDI-01.reference_output │ │ │ ├── I-AUIPC-01.reference_output │ │ │ ├── I-BEQ-01.reference_output │ │ │ ├── I-BGE-01.reference_output │ │ │ ├── I-BGEU-01.reference_output │ │ │ ├── I-BLT-01.reference_output │ │ │ ├── I-BLTU-01.reference_output │ │ │ ├── I-BNE-01.reference_output │ │ │ ├── I-CSRRC-01.reference_output │ │ │ ├── I-CSRRCI-01.reference_output │ │ │ ├── I-CSRRS-01.reference_output │ │ │ ├── I-CSRRSI-01.reference_output │ │ │ ├── I-CSRRW-01.reference_output │ │ │ ├── I-CSRRWI-01.reference_output │ │ │ ├── I-DELAY_SLOTS-01.reference_output │ │ │ ├── I-EBREAK-01.reference_output │ │ │ ├── I-ECALL-01.reference_output │ │ │ ├── I-ENDIANESS-01.reference_output │ │ │ ├── I-FENCE.I-01.reference_output │ │ │ ├── I-IO.reference_output │ │ │ ├── I-JAL-01.reference_output │ │ │ ├── I-JALR-01.reference_output │ │ │ ├── I-LB-01.reference_output │ │ │ ├── I-LBU-01.reference_output │ │ │ ├── I-LH-01.reference_output │ │ │ ├── I-LHU-01.reference_output │ │ │ ├── I-LUI-01.reference_output │ │ │ ├── I-LW-01.reference_output │ │ │ ├── I-MISALIGN_JMP-01.reference_output │ │ │ ├── I-MISALIGN_LDST-01.reference_output │ │ │ ├── I-NOP-01.reference_output │ │ │ ├── I-OR-01.reference_output │ │ │ ├── I-ORI-01.reference_output │ │ │ ├── I-RF_size-01.reference_output │ │ │ ├── I-RF_width-01.reference_output │ │ │ ├── I-RF_x0-01.reference_output │ │ │ ├── I-SB-01.reference_output │ │ │ ├── I-SH-01.reference_output │ │ │ ├── I-SLL-01.reference_output │ │ │ ├── I-SLLI-01.reference_output │ │ │ ├── I-SLT-01.reference_output │ │ │ ├── I-SLTI-01.reference_output │ │ │ ├── I-SLTIU-01.reference_output │ │ │ ├── I-SLTU-01.reference_output │ │ │ ├── I-SRA-01.reference_output │ │ │ ├── I-SRAI-01.reference_output │ │ │ ├── I-SRL-01.reference_output │ │ │ ├── I-SRLI-01.reference_output │ │ │ ├── I-SUB-01.reference_output │ │ │ ├── I-SW-01.reference_output │ │ │ ├── I-XOR-01.reference_output │ │ │ └── I-XORI-01.reference_output │ │ └── src │ │ │ ├── I-ADD-01.S │ │ │ ├── I-ADDI-01.S │ │ │ ├── I-AND-01.S │ │ │ ├── I-ANDI-01.S │ │ │ ├── I-AUIPC-01.S │ │ │ ├── I-BEQ-01.S │ │ │ ├── I-BGE-01.S │ │ │ ├── I-BGEU-01.S │ │ │ ├── I-BLT-01.S │ │ │ ├── I-BLTU-01.S │ │ │ ├── I-BNE-01.S │ │ │ ├── I-CSRRC-01.S │ │ │ ├── I-CSRRCI-01.S │ │ │ ├── I-CSRRS-01.S │ │ │ ├── I-CSRRSI-01.S │ │ │ ├── I-CSRRW-01.S │ │ │ ├── I-CSRRWI-01.S │ │ │ ├── I-DELAY_SLOTS-01.S │ │ │ ├── I-EBREAK-01.S │ │ │ ├── I-ECALL-01.S │ │ │ ├── I-ENDIANESS-01.S │ │ │ ├── I-FENCE.I-01.S │ │ │ ├── I-IO.S │ │ │ ├── I-JAL-01.S │ │ │ ├── I-JALR-01.S │ │ │ ├── I-LB-01.S │ │ │ ├── I-LBU-01.S │ │ │ ├── I-LH-01.S │ │ │ ├── I-LHU-01.S │ │ │ ├── I-LUI-01.S │ │ │ ├── I-LW-01.S │ │ │ ├── I-MISALIGN_JMP-01.S │ │ │ ├── I-MISALIGN_LDST-01.S │ │ │ ├── I-NOP-01.S │ │ │ ├── I-OR-01.S │ │ │ ├── I-ORI-01.S │ │ │ ├── I-RF_size-01.S │ │ │ ├── I-RF_width-01.S │ │ │ ├── I-RF_x0-01.S │ │ │ ├── I-SB-01.S │ │ │ ├── I-SH-01.S │ │ │ ├── I-SLL-01.S │ │ │ ├── I-SLLI-01.S │ │ │ ├── I-SLT-01.S │ │ │ ├── I-SLTI-01.S │ │ │ ├── I-SLTIU-01.S │ │ │ ├── I-SLTU-01.S │ │ │ ├── I-SRA-01.S │ │ │ ├── I-SRAI-01.S │ │ │ ├── I-SRL-01.S │ │ │ ├── I-SRLI-01.S │ │ │ ├── I-SUB-01.S │ │ │ ├── I-SW-01.S │ │ │ ├── I-XOR-01.S │ │ │ └── I-XORI-01.S │ │ ├── rv32im │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── DIV.reference_output │ │ │ ├── DIVU.reference_output │ │ │ ├── MUL.reference_output │ │ │ ├── MULH.reference_output │ │ │ ├── MULHSU.reference_output │ │ │ ├── MULHU.reference_output │ │ │ ├── REM.reference_output │ │ │ └── REMU.reference_output │ │ └── src │ │ │ ├── DIV.S │ │ │ ├── DIVU.S │ │ │ ├── MUL.S │ │ │ ├── MULH.S │ │ │ ├── MULHSU.S │ │ │ ├── MULHU.S │ │ │ ├── REM.S │ │ │ └── REMU.S │ │ ├── rv32imc │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── C-ADD.reference_output │ │ │ ├── C-ADDI.reference_output │ │ │ ├── C-ADDI16SP.reference_output │ │ │ ├── C-ADDI4SPN.reference_output │ │ │ ├── C-AND.reference_output │ │ │ ├── C-ANDI.reference_output │ │ │ ├── C-BEQZ.reference_output │ │ │ ├── C-BNEZ.reference_output │ │ │ ├── C-J.reference_output │ │ │ ├── C-JAL.reference_output │ │ │ ├── C-JALR.reference_output │ │ │ ├── C-JR.reference_output │ │ │ ├── C-LI.reference_output │ │ │ ├── C-LUI.reference_output │ │ │ ├── C-LW.reference_output │ │ │ ├── C-LWSP.reference_output │ │ │ ├── C-MV.reference_output │ │ │ ├── C-OR.reference_output │ │ │ ├── C-SLLI.reference_output │ │ │ ├── C-SRAI.reference_output │ │ │ ├── C-SRLI.reference_output │ │ │ ├── C-SUB.reference_output │ │ │ ├── C-SW.reference_output │ │ │ ├── C-SWSP.reference_output │ │ │ └── C-XOR.reference_output │ │ └── src │ │ │ ├── C-ADD.S │ │ │ ├── C-ADDI.S │ │ │ ├── C-ADDI16SP.S │ │ │ ├── C-ADDI4SPN.S │ │ │ ├── C-AND.S │ │ │ ├── C-ANDI.S │ │ │ ├── C-BEQZ.S │ │ │ ├── C-BNEZ.S │ │ │ ├── C-J.S │ │ │ ├── C-JAL.S │ │ │ ├── C-JALR.S │ │ │ ├── C-JR.S │ │ │ ├── C-LI.S │ │ │ ├── C-LUI.S │ │ │ ├── C-LW.S │ │ │ ├── C-LWSP.S │ │ │ ├── C-MV.S │ │ │ ├── C-OR.S │ │ │ ├── C-SLLI.S │ │ │ ├── C-SRAI.S │ │ │ ├── C-SRLI.S │ │ │ ├── C-SUB.S │ │ │ ├── C-SW.S │ │ │ ├── C-SWSP.S │ │ │ └── C-XOR.S │ │ ├── rv32mi │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── breakpoint.reference_output │ │ │ ├── csr.reference_output │ │ │ ├── illegal.reference_output │ │ │ ├── ma_addr.reference_output │ │ │ ├── ma_fetch.reference_output │ │ │ ├── mcsr.reference_output │ │ │ ├── sbreak.reference_output │ │ │ ├── scall.reference_output │ │ │ └── shamt.reference_output │ │ ├── rv64mi │ │ │ ├── Makefrag │ │ │ ├── access.S │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ └── scall.S │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ └── src │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── shamt.S │ │ ├── rv32si │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── csr.reference_output │ │ │ ├── dirty.reference_output │ │ │ ├── ma_fetch.reference_output │ │ │ ├── sbreak.reference_output │ │ │ ├── scall.reference_output │ │ │ └── wfi.reference_output │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ ├── rv32ua │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── amoadd_w.reference_output │ │ │ ├── amoand_w.reference_output │ │ │ ├── amomax_w.reference_output │ │ │ ├── amomaxu_w.reference_output │ │ │ ├── amomin_w.reference_output │ │ │ ├── amominu_w.reference_output │ │ │ ├── amoor_w.reference_output │ │ │ ├── amoswap_w.reference_output │ │ │ ├── amoxor_w.reference_output │ │ │ └── lrsc.reference_output │ │ ├── rv64ua │ │ │ ├── Makefrag │ │ │ ├── amoadd_d.S │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_d.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_d.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_d.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_d.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_d.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_d.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_d.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_d.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ │ ├── rv32uc │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ └── rvc.reference_output │ │ ├── rv64uc │ │ │ ├── Makefrag │ │ │ └── rvc.S │ │ └── src │ │ │ ├── Makefrag │ │ │ └── rvc.S │ │ ├── rv32ud │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── fadd.reference_output │ │ │ ├── fclass.reference_output │ │ │ ├── fcmp.reference_output │ │ │ ├── fcvt.reference_output │ │ │ ├── fdiv.reference_output │ │ │ ├── fmadd.reference_output │ │ │ ├── fmin.reference_output │ │ │ ├── ldst.reference_output │ │ │ └── recoding.reference_output │ │ ├── rv64ud │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ ├── recoding.S │ │ │ └── structural.S │ │ └── src │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ │ ├── rv32uf │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── fadd.reference_output │ │ │ ├── fclass.reference_output │ │ │ ├── fcmp.reference_output │ │ │ ├── fcvt.reference_output │ │ │ ├── fcvt_w.reference_output │ │ │ ├── fdiv.reference_output │ │ │ ├── fmadd.reference_output │ │ │ ├── fmin.reference_output │ │ │ ├── ldst.reference_output │ │ │ ├── move.reference_output │ │ │ └── recoding.reference_output │ │ ├── rv64uf │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ │ ├── rv32ui │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── add.reference_output │ │ │ ├── addi.reference_output │ │ │ ├── and.reference_output │ │ │ ├── andi.reference_output │ │ │ ├── auipc.reference_output │ │ │ ├── beq.reference_output │ │ │ ├── bge.reference_output │ │ │ ├── bgeu.reference_output │ │ │ ├── blt.reference_output │ │ │ ├── bltu.reference_output │ │ │ ├── bne.reference_output │ │ │ ├── fence_i.reference_output │ │ │ ├── jal.reference_output │ │ │ ├── jalr.reference_output │ │ │ ├── lb.reference_output │ │ │ ├── lbu.reference_output │ │ │ ├── lh.reference_output │ │ │ ├── lhu.reference_output │ │ │ ├── lui.reference_output │ │ │ ├── lw.reference_output │ │ │ ├── or.reference_output │ │ │ ├── ori.reference_output │ │ │ ├── sb.reference_output │ │ │ ├── sh.reference_output │ │ │ ├── simple.reference_output │ │ │ ├── sll.reference_output │ │ │ ├── slli.reference_output │ │ │ ├── slt.reference_output │ │ │ ├── slti.reference_output │ │ │ ├── sltiu.reference_output │ │ │ ├── sltu.reference_output │ │ │ ├── sra.reference_output │ │ │ ├── srai.reference_output │ │ │ ├── srl.reference_output │ │ │ ├── sub.reference_output │ │ │ ├── sw.reference_output │ │ │ ├── xor.reference_output │ │ │ └── xori.reference_output │ │ ├── rv64ui │ │ │ ├── Makefrag │ │ │ ├── add.S │ │ │ ├── addi.S │ │ │ ├── addiw.S │ │ │ ├── addw.S │ │ │ ├── and.S │ │ │ ├── andi.S │ │ │ ├── auipc.S │ │ │ ├── beq.S │ │ │ ├── bge.S │ │ │ ├── bgeu.S │ │ │ ├── blt.S │ │ │ ├── bltu.S │ │ │ ├── bne.S │ │ │ ├── fence_i.S │ │ │ ├── jal.S │ │ │ ├── jalr.S │ │ │ ├── lb.S │ │ │ ├── lbu.S │ │ │ ├── ld.S │ │ │ ├── lh.S │ │ │ ├── lhu.S │ │ │ ├── lui.S │ │ │ ├── lw.S │ │ │ ├── lwu.S │ │ │ ├── or.S │ │ │ ├── ori.S │ │ │ ├── sb.S │ │ │ ├── sd.S │ │ │ ├── sh.S │ │ │ ├── simple.S │ │ │ ├── sll.S │ │ │ ├── slli.S │ │ │ ├── slliw.S │ │ │ ├── sllw.S │ │ │ ├── slt.S │ │ │ ├── slti.S │ │ │ ├── sltiu.S │ │ │ ├── sltu.S │ │ │ ├── sra.S │ │ │ ├── srai.S │ │ │ ├── sraiw.S │ │ │ ├── sraw.S │ │ │ ├── srl.S │ │ │ ├── srli.S │ │ │ ├── srliw.S │ │ │ ├── srlw.S │ │ │ ├── sub.S │ │ │ ├── subw.S │ │ │ ├── sw.S │ │ │ ├── xor.S │ │ │ └── xori.S │ │ └── src │ │ │ ├── Makefrag.spike │ │ │ ├── add.S │ │ │ ├── addi.S │ │ │ ├── and.S │ │ │ ├── andi.S │ │ │ ├── auipc.S │ │ │ ├── beq.S │ │ │ ├── bge.S │ │ │ ├── bgeu.S │ │ │ ├── blt.S │ │ │ ├── bltu.S │ │ │ ├── bne.S │ │ │ ├── fence_i.S │ │ │ ├── jal.S │ │ │ ├── jalr.S │ │ │ ├── lb.S │ │ │ ├── lbu.S │ │ │ ├── lh.S │ │ │ ├── lhu.S │ │ │ ├── lui.S │ │ │ ├── lw.S │ │ │ ├── or.S │ │ │ ├── ori.S │ │ │ ├── sb.S │ │ │ ├── sh.S │ │ │ ├── simple.S │ │ │ ├── sll.S │ │ │ ├── slli.S │ │ │ ├── slt.S │ │ │ ├── slti.S │ │ │ ├── sltiu.S │ │ │ ├── sltu.S │ │ │ ├── sra.S │ │ │ ├── srai.S │ │ │ ├── srl.S │ │ │ ├── srli.S │ │ │ ├── sub.S │ │ │ ├── sw.S │ │ │ ├── xor.S │ │ │ └── xori.S │ │ ├── rv64i │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── ADDIW.reference_output │ │ │ ├── ADDW.reference_output │ │ │ ├── SLLIW.reference_output │ │ │ ├── SLLW.reference_output │ │ │ ├── SRAIW.reference_output │ │ │ ├── SRAW.reference_output │ │ │ ├── SRLIW.reference_output │ │ │ ├── SRLW.reference_output │ │ │ └── SUBW.reference_output │ │ └── src │ │ │ ├── ADDIW.S │ │ │ ├── ADDW.S │ │ │ ├── SLLIW.S │ │ │ ├── SLLW.S │ │ │ ├── SRAIW.S │ │ │ ├── SRAW.S │ │ │ ├── SRLIW.S │ │ │ ├── SRLW.S │ │ │ └── SUBW.S │ │ └── rv64im │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ ├── DIVW.reference_output │ │ ├── MULW.reference_output │ │ ├── REMUW.reference_output │ │ └── REMW.reference_output │ │ └── src │ │ ├── DIVW.S │ │ ├── MULW.S │ │ ├── REMUW.S │ │ └── REMW.S │ ├── tests.F │ ├── unit │ ├── arith_add.S │ ├── arith_addi.S │ ├── arith_addi_neg.S │ ├── arith_and.S │ ├── arith_andi.S │ ├── arith_or.S │ ├── arith_ori.S │ ├── arith_sll.S │ ├── arith_slli.S │ ├── arith_slt_f.S │ ├── arith_slt_t_neg.S │ ├── arith_slt_t_pos.S │ ├── arith_slti_f.S │ ├── arith_slti_t.S │ ├── arith_sltu_t.S │ ├── arith_sra.S │ ├── arith_srai.S │ ├── arith_srl.S │ ├── arith_srli.S │ ├── arith_sub.S │ ├── arith_xor.S │ ├── arith_xori.S │ ├── branch_beq_f_back.S │ ├── branch_beq_f_fwd.S │ ├── branch_beq_t_back.S │ ├── branch_beq_t_fwd.S │ ├── branch_bge_eq_t_neg.S │ ├── branch_bge_eq_t_pos.S │ ├── branch_bge_gt_t_neg.S │ ├── branch_bge_gt_t_pos.S │ ├── branch_blt_t_neg.S │ ├── branch_blt_t_pos.S │ ├── branch_bltu_t_neg.S │ ├── branch_bltu_t_pos.S │ ├── branch_bne_f_back.S │ ├── branch_bne_f_fwd.S │ ├── branch_bne_t_back.S │ ├── branch_bne_t_fwd.S │ ├── exception_bne.S │ ├── exception_dep_x.S │ ├── exception_j.S │ ├── exception_jalr.S │ ├── exception_lw.S │ ├── jump_j.S │ ├── jump_jal.S │ ├── jump_jalr.S │ ├── jump_jalr_off_neg.S │ ├── jump_jalr_off_pos.S │ ├── ldst_lb.S │ ├── ldst_lb_s.S │ ├── ldst_lb_u.S │ ├── ldst_lbu_s.S │ ├── ldst_lh_s.S │ ├── ldst_lh_u.S │ ├── ldst_lhu_s.S │ ├── ldst_lw.S │ ├── ldst_sb_lw.S │ ├── ldst_sh_lw.S │ ├── ldst_sw_lw.S │ ├── long_loop.S │ ├── lui.S │ ├── system_csrc.S │ ├── system_csrr.S │ ├── system_csrs.S │ ├── system_csrsi.S │ ├── system_csrw.S │ ├── system_csrw_csrr.S │ ├── system_ecall.S │ ├── system_eret.S │ ├── unit.ld │ └── unit_header.h │ └── uvm │ ├── elf_symtab_reader.svh │ ├── fwrisc_instr_test.svh │ ├── fwrisc_riscv_compliance_tests.svh │ ├── fwrisc_test_base.svh │ └── fwrisc_tests_pkg.sv ├── fwrisc_rv32imc_fpga ├── sim │ ├── .simscripts │ ├── mk_testlist.sh │ ├── scripts │ │ ├── Makefile │ │ ├── embedded.mk │ │ ├── mk_instr_tests.sh │ │ ├── status.sh │ │ ├── vlog_hdl.f │ │ └── vlog_hvl.f │ ├── testlists │ │ ├── fwrisc_riscv_compliance_tests.tl │ │ └── fwrisc_riscv_unit_tests.f │ └── tests │ │ ├── fwrisc_fpga_led_flash.f │ │ ├── fwrisc_fpga_memtest.f │ │ └── fwrisc_fpga_zephyr_hello_world.f ├── stdout.log ├── tb │ ├── fwrisc_fpga_tb_hdl.sv │ ├── tb.F │ └── vl │ │ ├── fwrisc_fpga_tb_hdl.cpp │ │ ├── fwrisc_fpga_tb_hdl.h │ │ └── fwrisc_fpga_tb_vl.mk └── tests │ ├── fwrisc_fpga_tests.cpp │ ├── fwrisc_fpga_tests.h │ ├── fwrisc_fpga_tests.mk │ └── sw │ ├── baremetal.ld │ ├── fwrisc_fpga_tests_sw.mk │ ├── led_flash.S │ └── memtest.S ├── fwrisc_tracer_bfm ├── fwrisc_tracer_bfm.bid ├── fwrisc_tracer_bfm.sv ├── fwrisc_tracer_bfm_api.svh ├── fwrisc_tracer_bfm_api_pkg.sv ├── gvm │ ├── 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