├── .github └── workflows │ └── rust-build-and-test.yml ├── .gitignore ├── Cargo.toml ├── LICENSE ├── README.md ├── benches ├── segvec_benchmark.rs ├── segvec_benchmark2.rs └── slice_and_iter.rs └── src ├── lib.rs ├── mem_config.rs ├── slice.rs └── tests.rs /.github/workflows/rust-build-and-test.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/.github/workflows/rust-build-and-test.yml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/.gitignore -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/Cargo.toml -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/README.md -------------------------------------------------------------------------------- /benches/segvec_benchmark.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/benches/segvec_benchmark.rs -------------------------------------------------------------------------------- /benches/segvec_benchmark2.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/benches/segvec_benchmark2.rs -------------------------------------------------------------------------------- /benches/slice_and_iter.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/benches/slice_and_iter.rs -------------------------------------------------------------------------------- /src/lib.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/src/lib.rs -------------------------------------------------------------------------------- /src/mem_config.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/src/mem_config.rs -------------------------------------------------------------------------------- /src/slice.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/src/slice.rs -------------------------------------------------------------------------------- /src/tests.rs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mccolljr/segvec/HEAD/src/tests.rs --------------------------------------------------------------------------------