├── LICENSE ├── README.md └── axis_uart_1.0 ├── bd └── bd.tcl ├── component.xml ├── hdl ├── axis_uart_v1_0.v ├── uart_fifo.v ├── uart_prescaler.v ├── uart_rx.v └── uart_tx.v └── xgui └── axis_uart_v1_0.tcl /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Dmitry Matyunin 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # axis-uart 2 | AXI Stream UART 3 | 4 | 5 | ## Features 6 | * Parity: None, Even, Odd, Mark, Space 7 | * Byte Size: up to 16 bits 8 | * Stop Bits: One, Two 9 | * Flow Control: None, RTS/CTS 10 | * Static and Dynamic Configuration 11 | 12 | ## Baudrate Calculation 13 | 14 | Baudrate ~ `aclk / prescaler_value` 15 | Example: if aclk is 100MHz, and desired baudrate is 115200, then the prescaler value must be approximately equal ~868. 16 | 17 | ## Dynamic Configuration 18 | 19 | Use s_axis_config_* interface to dynamically configurate UART. 20 | Bits: 21 | * [15:0] - prescaler 22 | * [18:16] - parity (0 - none, 1 - even, 2 - odd, 3 - mark, 4 - space) 23 | * [22:19] - byte_size (from 1 to 16) 24 | * [23] - stop_bits (0 - one stop, 1 - two stops) 25 | 26 | ## Component 27 | 28 | Component created in Vivado v2018.3. -------------------------------------------------------------------------------- /axis_uart_1.0/bd/bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | proc init { cellpath otherInfo } { 3 | 4 | set cell_handle [get_bd_cells $cellpath] 5 | set all_busif [get_bd_intf_pins $cellpath/*] 6 | set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] 7 | set full_sbusif_list [list ] 8 | 9 | foreach busif $all_busif { 10 | if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { 11 | set busif_param_list [list] 12 | set busif_name [get_property NAME $busif] 13 | if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { 14 | continue 15 | } 16 | foreach tparam $axi_standard_param_list { 17 | lappend busif_param_list "C_${busif_name}_${tparam}" 18 | } 19 | bd::mark_propagate_only $cell_handle $busif_param_list 20 | } 21 | } 22 | } 23 | 24 | 25 | proc pre_propagate {cellpath otherInfo } { 26 | 27 | set cell_handle [get_bd_cells $cellpath] 28 | set all_busif [get_bd_intf_pins $cellpath/*] 29 | set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] 30 | 31 | foreach busif $all_busif { 32 | if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { 33 | continue 34 | } 35 | if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { 36 | continue 37 | } 38 | 39 | set busif_name [get_property NAME $busif] 40 | foreach tparam $axi_standard_param_list { 41 | set busif_param_name "C_${busif_name}_${tparam}" 42 | 43 | set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] 44 | set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] 45 | 46 | if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { 47 | if { $val_on_cell != "" } { 48 | set_property CONFIG.${tparam} $val_on_cell $busif 49 | } 50 | } 51 | } 52 | } 53 | } 54 | 55 | 56 | proc propagate {cellpath otherInfo } { 57 | 58 | set cell_handle [get_bd_cells $cellpath] 59 | set all_busif [get_bd_intf_pins $cellpath/*] 60 | set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] 61 | 62 | foreach busif $all_busif { 63 | if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { 64 | continue 65 | } 66 | if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { 67 | continue 68 | } 69 | 70 | set busif_name [get_property NAME $busif] 71 | foreach tparam $axi_standard_param_list { 72 | set busif_param_name "C_${busif_name}_${tparam}" 73 | 74 | set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] 75 | set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] 76 | 77 | if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { 78 | #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. 79 | if { $val_on_cell_intf_pin != "" } { 80 | set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle 81 | } 82 | } 83 | } 84 | } 85 | } 86 | 87 | -------------------------------------------------------------------------------- /axis_uart_1.0/component.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | mcjtag 4 | ip 5 | axis_uart 6 | 1.0 7 | 8 | 9 | aresetn 10 | 11 | 12 | 13 | 14 | 15 | 16 | RST 17 | 18 | 19 | aresetn 20 | 21 | 22 | 23 | 24 | 25 | POLARITY 26 | ACTIVE_LOW 27 | 28 | 29 | 30 | 31 | aclk 32 | 33 | 34 | 35 | 36 | 37 | 38 | CLK 39 | 40 | 41 | aclk 42 | 43 | 44 | 45 | 46 | 47 | ASSOCIATED_RESET 48 | aresetn 49 | 50 | 51 | ASSOCIATED_BUSIF 52 | s_axis:m_axis:s_axis_config 53 | 54 | 55 | 56 | 57 | s_axis_config 58 | 59 | 60 | 61 | 62 | 63 | 64 | TDATA 65 | 66 | 67 | s_axis_config_tdata 68 | 69 | 70 | 71 | 72 | TVALID 73 | 74 | 75 | s_axis_config_tvalid 76 | 77 | 78 | 79 | 80 | TREADY 81 | 82 | 83 | s_axis_config_tready 84 | 85 | 86 | 87 | 88 | 89 | 90 | false 91 | 92 | 93 | 94 | 95 | 96 | m_axis 97 | 98 | 99 | 100 | 101 | 102 | 103 | TUSER 104 | 105 | 106 | m_axis_tuser 107 | 108 | 109 | 110 | 111 | TDATA 112 | 113 | 114 | m_axis_tdata 115 | 116 | 117 | 118 | 119 | TVALID 120 | 121 | 122 | m_axis_tvalid 123 | 124 | 125 | 126 | 127 | TREADY 128 | 129 | 130 | m_axis_tready 131 | 132 | 133 | 134 | 135 | 136 | uart 137 | 138 | 139 | 140 | 141 | 142 | 143 | TxD 144 | 145 | 146 | tx 147 | 148 | 149 | 150 | 151 | RxD 152 | 153 | 154 | rx 155 | 156 | 157 | 158 | 159 | RTSn 160 | 161 | 162 | rts 163 | 164 | 165 | 166 | 167 | CTSn 168 | 169 | 170 | cts 171 | 172 | 173 | 174 | 175 | 176 | s_axis 177 | 178 | 179 | 180 | 181 | 182 | 183 | TDATA 184 | 185 | 186 | s_axis_tdata 187 | 188 | 189 | 190 | 191 | TVALID 192 | 193 | 194 | s_axis_tvalid 195 | 196 | 197 | 198 | 199 | TREADY 200 | 201 | 202 | s_axis_tready 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | xilinx_verilogsynthesis 212 | Verilog Synthesis 213 | verilogSource:vivado.xilinx.com:synthesis 214 | verilog 215 | axis_uart_v1_0 216 | 217 | xilinx_verilogsynthesis_view_fileset 218 | 219 | 220 | 221 | viewChecksum 222 | 648e7ae1 223 | 224 | 225 | 226 | 227 | xilinx_verilogbehavioralsimulation 228 | Verilog Simulation 229 | verilogSource:vivado.xilinx.com:simulation 230 | verilog 231 | axis_uart_v1_0 232 | 233 | xilinx_verilogbehavioralsimulation_view_fileset 234 | 235 | 236 | 237 | viewChecksum 238 | 648e7ae1 239 | 240 | 241 | 242 | 243 | xilinx_xpgui 244 | UI Layout 245 | :vivado.xilinx.com:xgui.ui 246 | 247 | xilinx_xpgui_view_fileset 248 | 249 | 250 | 251 | viewChecksum 252 | a3e4d263 253 | 254 | 255 | 256 | 257 | bd_tcl 258 | Block Diagram 259 | :vivado.xilinx.com:block.diagram 260 | 261 | bd_tcl_view_fileset 262 | 263 | 264 | 265 | viewChecksum 266 | 16328387 267 | 268 | 269 | 270 | 271 | 272 | 273 | aclk 274 | 275 | in 276 | 277 | 278 | wire 279 | xilinx_verilogsynthesis 280 | xilinx_verilogbehavioralsimulation 281 | 282 | 283 | 284 | 285 | 286 | aresetn 287 | 288 | in 289 | 290 | 291 | wire 292 | xilinx_verilogsynthesis 293 | xilinx_verilogbehavioralsimulation 294 | 295 | 296 | 297 | 298 | 299 | s_axis_config_tdata 300 | 301 | in 302 | 303 | 23 304 | 0 305 | 306 | 307 | 308 | wire 309 | xilinx_verilogsynthesis 310 | xilinx_verilogbehavioralsimulation 311 | 312 | 313 | 314 | 315 | 316 | s_axis_config_tvalid 317 | 318 | in 319 | 320 | 321 | wire 322 | xilinx_verilogsynthesis 323 | xilinx_verilogbehavioralsimulation 324 | 325 | 326 | 327 | 328 | 329 | s_axis_config_tready 330 | 331 | out 332 | 333 | 334 | wire 335 | xilinx_verilogsynthesis 336 | xilinx_verilogbehavioralsimulation 337 | 338 | 339 | 340 | 341 | 342 | s_axis_tdata 343 | 344 | in 345 | 346 | 15 347 | 0 348 | 349 | 350 | 351 | wire 352 | xilinx_verilogsynthesis 353 | xilinx_verilogbehavioralsimulation 354 | 355 | 356 | 357 | 358 | 359 | s_axis_tvalid 360 | 361 | in 362 | 363 | 364 | wire 365 | xilinx_verilogsynthesis 366 | xilinx_verilogbehavioralsimulation 367 | 368 | 369 | 370 | 371 | 372 | s_axis_tready 373 | 374 | out 375 | 376 | 377 | wire 378 | xilinx_verilogsynthesis 379 | xilinx_verilogbehavioralsimulation 380 | 381 | 382 | 383 | 384 | 385 | m_axis_tdata 386 | 387 | out 388 | 389 | 15 390 | 0 391 | 392 | 393 | 394 | wire 395 | xilinx_verilogsynthesis 396 | xilinx_verilogbehavioralsimulation 397 | 398 | 399 | 400 | 401 | 402 | m_axis_tuser 403 | 404 | out 405 | 406 | 407 | wire 408 | xilinx_verilogsynthesis 409 | xilinx_verilogbehavioralsimulation 410 | 411 | 412 | 413 | 414 | 415 | m_axis_tvalid 416 | 417 | out 418 | 419 | 420 | wire 421 | xilinx_verilogsynthesis 422 | xilinx_verilogbehavioralsimulation 423 | 424 | 425 | 426 | 427 | 428 | m_axis_tready 429 | 430 | in 431 | 432 | 433 | wire 434 | xilinx_verilogsynthesis 435 | xilinx_verilogbehavioralsimulation 436 | 437 | 438 | 439 | 440 | 441 | tx 442 | 443 | out 444 | 445 | 446 | wire 447 | xilinx_verilogsynthesis 448 | xilinx_verilogbehavioralsimulation 449 | 450 | 451 | 452 | 453 | 454 | rx 455 | 456 | in 457 | 458 | 459 | wire 460 | xilinx_verilogsynthesis 461 | xilinx_verilogbehavioralsimulation 462 | 463 | 464 | 465 | 466 | 467 | rts 468 | 469 | out 470 | 471 | 472 | wire 473 | xilinx_verilogsynthesis 474 | xilinx_verilogbehavioralsimulation 475 | 476 | 477 | 478 | 0 479 | 480 | 481 | 482 | 483 | 484 | false 485 | 486 | 487 | 488 | 489 | 490 | cts 491 | 492 | in 493 | 494 | 495 | wire 496 | xilinx_verilogsynthesis 497 | xilinx_verilogbehavioralsimulation 498 | 499 | 500 | 501 | 0 502 | 503 | 504 | 505 | 506 | 507 | false 508 | 509 | 510 | 511 | 512 | 513 | 514 | 515 | BAUD_PRESCALER 516 | Baud Prescaler 517 | 10 518 | 519 | 520 | PARITY 521 | Parity 522 | 0 523 | 524 | 525 | BYTE_SIZE 526 | Byte Size 527 | 8 528 | 529 | 530 | STOP_BITS 531 | Stop Bits 532 | 0 533 | 534 | 535 | FIFO_DEPTH 536 | Fifo Depth 537 | 16 538 | 539 | 540 | FLOW_CONTROL 541 | Flow Control 542 | 0 543 | 544 | 545 | DYNAMIC_CONFIG 546 | Dynamic Config 547 | 0 548 | 549 | 550 | 551 | 552 | 553 | choice_list_9d8b0d81 554 | ACTIVE_HIGH 555 | ACTIVE_LOW 556 | 557 | 558 | choice_list_cbe05b28 559 | 4 560 | 8 561 | 16 562 | 32 563 | 564 | 565 | choice_pairs_0bc02c7a 566 | 0 567 | 1 568 | 569 | 570 | choice_pairs_0ccf33c2 571 | 1 572 | 0 573 | 574 | 575 | choice_pairs_376a2037 576 | 0 577 | 1 578 | 579 | 580 | choice_pairs_377cf9cb 581 | 0 582 | 1 583 | 2 584 | 3 585 | 4 586 | 587 | 588 | 589 | 590 | xilinx_verilogsynthesis_view_fileset 591 | 592 | hdl/uart_fifo.v 593 | verilogSource 594 | 595 | 596 | hdl/uart_prescaler.v 597 | verilogSource 598 | 599 | 600 | hdl/uart_rx.v 601 | verilogSource 602 | 603 | 604 | hdl/uart_tx.v 605 | verilogSource 606 | 607 | 608 | hdl/axis_uart_v1_0.v 609 | verilogSource 610 | CHECKSUM_cab83566 611 | 612 | 613 | 614 | xilinx_verilogbehavioralsimulation_view_fileset 615 | 616 | hdl/uart_fifo.v 617 | verilogSource 618 | 619 | 620 | hdl/uart_prescaler.v 621 | verilogSource 622 | 623 | 624 | hdl/uart_rx.v 625 | verilogSource 626 | 627 | 628 | hdl/uart_tx.v 629 | verilogSource 630 | 631 | 632 | hdl/axis_uart_v1_0.v 633 | verilogSource 634 | 635 | 636 | 637 | xilinx_xpgui_view_fileset 638 | 639 | xgui/axis_uart_v1_0.tcl 640 | tclSource 641 | CHECKSUM_a3e4d263 642 | XGUI_VERSION_2 643 | 644 | 645 | 646 | bd_tcl_view_fileset 647 | 648 | bd/bd.tcl 649 | tclSource 650 | 651 | 652 | 653 | AXI4-Stream UART IP 654 | 655 | 656 | Component_Name 657 | axis_uart_v1_0 658 | 659 | 660 | BAUD_PRESCALER 661 | Baud Prescaler 662 | 10 663 | 664 | 665 | PARITY 666 | Parity 667 | 0 668 | 669 | 670 | BYTE_SIZE 671 | Byte Size 672 | 8 673 | 674 | 675 | STOP_BITS 676 | Stop Bits 677 | 0 678 | 679 | 680 | FIFO_DEPTH 681 | FIFO Depth 682 | 16 683 | 684 | 685 | FLOW_CONTROL 686 | Flow Control 687 | 0 688 | 689 | 690 | DYNAMIC_CONFIG 691 | Dynamic Config 692 | 0 693 | 694 | 695 | 696 | 697 | 698 | artix7 699 | artix7l 700 | kintex7 701 | kintex7l 702 | spartan7 703 | aartix7 704 | aspartan7 705 | azynq 706 | zynq 707 | 708 | 709 | /Embedded_Processing/AXI_Peripheral/Low_Speed_Peripheral 710 | 711 | AXI4-Stream UART 712 | 3 713 | 2019-10-03T13:18:58Z 714 | 715 | 716 | 717 | 718 | 2018.3 719 | 720 | 721 | 722 | 723 | 724 | 725 | 726 | 727 | -------------------------------------------------------------------------------- /axis_uart_1.0/hdl/axis_uart_v1_0.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: mcjtag 5 | // 6 | // Create Date: 03.10.2019 14:07:08 7 | // Design Name: 8 | // Module Name: uart_tx 9 | // Project Name: axis_uart 10 | // Target Devices: All 11 | // Tool Versions: 2018.3 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module axis_uart_v1_0 #( 23 | parameter integer BAUD_PRESCALER = 10, /* Baudrate Prescaler */ 24 | parameter integer PARITY = 0, /* 0(none), 1(even), 2(odd), 3(mark), 4(space) */ 25 | parameter integer BYTE_SIZE = 8, /* Byte Size (16 max) */ 26 | parameter integer STOP_BITS = 0, /* 0(one stop), 1(two stops) */ 27 | parameter integer FIFO_DEPTH = 16, /* FIFO Depth */ 28 | parameter integer FLOW_CONTROL = 0, /* RTS/CTS */ 29 | parameter integer DYNAMIC_CONFIG = 0 /* Dynamic Configuration */ 30 | ) 31 | ( 32 | input wire aclk, 33 | input wire aresetn, 34 | /* Dynamic Configuration */ /* Active when DYNAMIC_CONFIG == 1 */ 35 | input wire [23:0]s_axis_config_tdata, /* bits: prescaler = [15:0], parity = [18:16], byte_size <= [22:19], stop_bits = [23] */ 36 | input wire s_axis_config_tvalid, 37 | output wire s_axis_config_tready, 38 | /* AXI-Stream Interface (Slave) */ 39 | input wire [15:0]s_axis_tdata, 40 | input wire s_axis_tvalid, 41 | output wire s_axis_tready, 42 | /* AXI-Stream Interface (Master) */ 43 | output wire [15:0]m_axis_tdata, 44 | output wire m_axis_tuser, /* Parity Error */ 45 | output wire m_axis_tvalid, 46 | input wire m_axis_tready, 47 | // UART Port 48 | output wire tx, 49 | input wire rx, 50 | output wire rts, /* Active when FLOW_CONTROL == 1 */ 51 | input wire cts /* Active when FLOW_CONTROL == 1 */ 52 | ); 53 | 54 | wire s_axis_config_tx_tready; 55 | wire s_axis_config_rx_tready; 56 | 57 | assign s_axis_config_tready = (DYNAMIC_CONFIG) ? s_axis_config_tx_tready & s_axis_config_rx_tready : 1'b0; 58 | 59 | uart_tx #( 60 | .BAUD_PRESCALER(BAUD_PRESCALER), 61 | .PARITY(PARITY), 62 | .BYTE_SIZE(BYTE_SIZE), 63 | .STOP_BITS(STOP_BITS), 64 | .FIFO_DEPTH(FIFO_DEPTH) 65 | ) uart_tx_inst ( 66 | .aclk(aclk), 67 | .aresetn(aresetn), 68 | .s_axis_config_tdata(s_axis_config_tdata), 69 | .s_axis_config_tvalid((DYNAMIC_CONFIG) ? s_axis_config_tvalid : 1'b0), 70 | .s_axis_config_tready(s_axis_config_tx_tready), 71 | .s_axis_tdata(s_axis_tdata), 72 | .s_axis_tvalid(s_axis_tvalid), 73 | .s_axis_tready(s_axis_tready), 74 | .txd(tx), 75 | .ctsn(FLOW_CONTROL ? cts : 1'b0) 76 | ); 77 | 78 | uart_rx #( 79 | .BAUD_PRESCALER(BAUD_PRESCALER), 80 | .PARITY(PARITY), 81 | .BYTE_SIZE(BYTE_SIZE), 82 | .STOP_BITS(STOP_BITS), 83 | .FIFO_DEPTH(FIFO_DEPTH) 84 | ) uart_rx_inst ( 85 | .aclk(aclk), 86 | .aresetn(aresetn), 87 | .s_axis_config_tdata(s_axis_config_tdata), 88 | .s_axis_config_tvalid((DYNAMIC_CONFIG) ? s_axis_config_tvalid : 1'b0), 89 | .s_axis_config_tready(s_axis_config_rx_tready), 90 | .m_axis_tdata(m_axis_tdata), 91 | .m_axis_tuser(m_axis_tuser), 92 | .m_axis_tvalid(m_axis_tvalid), 93 | .m_axis_tready(m_axis_tready), 94 | .rxd(rx), 95 | .rtsn(rts) 96 | ); 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /axis_uart_1.0/hdl/uart_fifo.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: mcjtag 5 | // 6 | // Create Date: 03.10.2019 14:19:09 7 | // Design Name: 8 | // Module Name: uart_fifo 9 | // Project Name: axis_uart 10 | // Target Devices: All 11 | // Tool Versions: 2018.3 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module uart_fifo #( 23 | parameter DATA_WIDTH = 8, 24 | parameter DATA_DEPTH = 8 25 | ) 26 | ( 27 | input wire aclk, 28 | input wire aresetn, 29 | input wire [DATA_WIDTH-1:0]s_axis_tdata, 30 | input wire s_axis_tvalid, 31 | output wire s_axis_tready, 32 | output wire [DATA_WIDTH-1:0]m_axis_tdata, 33 | output wire m_axis_tvalid, 34 | input wire m_axis_tready, 35 | output wire almost_empty, 36 | output wire almost_full 37 | ); 38 | 39 | function integer clogb2; 40 | input [31:0]value; 41 | begin 42 | value = value - 1; 43 | for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin 44 | value = value >> 1; 45 | end 46 | end 47 | endfunction 48 | 49 | localparam RWIDTH = clogb2(DATA_DEPTH); 50 | localparam CWIDTH = RWIDTH+1; 51 | 52 | reg [DATA_WIDTH-1:0]data[DATA_DEPTH-1:0]; 53 | reg [RWIDTH-1:0]head; 54 | reg [RWIDTH-1:0]tail; 55 | reg [CWIDTH-1:0]count; 56 | 57 | reg tready; 58 | reg [DATA_WIDTH-1:0]tdata; 59 | reg tvalid; 60 | 61 | reg aempty; 62 | reg afull; 63 | 64 | wire wr_valid; 65 | wire rd_valid; 66 | 67 | integer i; 68 | 69 | assign s_axis_tready = tready; 70 | assign m_axis_tdata = tdata; 71 | assign m_axis_tvalid = tvalid; 72 | 73 | assign wr_valid = s_axis_tvalid & s_axis_tready; 74 | assign rd_valid = m_axis_tvalid & m_axis_tready; 75 | 76 | assign almost_empty = aempty; 77 | assign almost_full = afull; 78 | 79 | always @(posedge aclk) begin 80 | if (aresetn == 1'b0) begin 81 | for (i = 0; i < DATA_DEPTH-1; i = i + 1) begin 82 | data[i] <= 0; 83 | end 84 | head <= 0; 85 | tail <= 0; 86 | count <= 0; 87 | end else begin 88 | case ({wr_valid,rd_valid}) 89 | 2'b00: begin 90 | head <= head; 91 | tail <= tail; 92 | count <= count; 93 | end 94 | 2'b01: begin 95 | head <= head; 96 | tail <= tail + 1; 97 | count <= count - 1; 98 | end 99 | 2'b10: begin 100 | data[head] <= s_axis_tdata; 101 | head <= head + 1; 102 | tail <= tail; 103 | count <= count + 1; 104 | end 105 | 2'b11: begin 106 | data[head] <= s_axis_tdata; 107 | head <= head + 1; 108 | tail <= tail + 1; 109 | count <= count; 110 | end 111 | endcase 112 | end 113 | end 114 | 115 | always @(*) begin 116 | if (aresetn == 1'b0) begin 117 | tready <= 1'b0; 118 | tdata <= 0; 119 | tvalid <= 1'b0; 120 | end else begin 121 | tready <= (count < DATA_DEPTH) ? 1'b1 : 1'b0; 122 | tdata <= data[tail]; 123 | tvalid <= (count > 0) ? 1'b1 : 1'b0; 124 | end 125 | end 126 | 127 | always @(*) begin 128 | if (aresetn == 1'b0) begin 129 | aempty <= 1'b0; 130 | afull <= 1'b0; 131 | end else begin 132 | aempty <= (count <= 1) ? 1'b1 : 1'b0; 133 | afull <= (count >= (DATA_DEPTH - 1)) ? 1'b1 : 1'b0; 134 | end 135 | end 136 | 137 | endmodule 138 | -------------------------------------------------------------------------------- /axis_uart_1.0/hdl/uart_prescaler.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: mcjtag 5 | // 6 | // Create Date: 03.10.2019 14:24:13 7 | // Design Name: 8 | // Module Name: uart_prescaler 9 | // Project Name: axis_uart 10 | // Target Devices: All 11 | // Tool Versions: 2018.3 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module uart_prescaler 23 | ( 24 | input wire clk, 25 | input wire rst, 26 | input wire en, 27 | input wire [15:0]div, 28 | output wire stb, 29 | output wire half 30 | ); 31 | 32 | reg [15:0]cnt; 33 | reg stb_out; 34 | reg half_out; 35 | 36 | assign stb = stb_out; 37 | assign half = half_out; 38 | 39 | always @(posedge clk) begin 40 | if (rst == 1'b1) begin 41 | cnt <= 0; 42 | end else begin 43 | if (en == 1'b1) begin 44 | if (cnt == (div - 1)) begin 45 | cnt <= 0; 46 | end else begin 47 | cnt <= cnt + 1; 48 | end 49 | end else begin 50 | cnt <= 0; 51 | end 52 | end 53 | end 54 | 55 | always @(*) begin 56 | if (rst == 1'b1) begin 57 | stb_out <= 1'b0; 58 | end else begin 59 | stb_out <= (cnt == (div - 1)) ? 1'b1 : 1'b0; 60 | end 61 | end 62 | 63 | always @(*) begin 64 | if (rst == 1'b1) begin 65 | half_out <= 1'b0; 66 | end else begin 67 | half_out <= (cnt == ({1'b0,div[15:1]} - 1)) ? 1'b1 : 1'b0; 68 | end 69 | end 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /axis_uart_1.0/hdl/uart_rx.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: mcjtag 5 | // 6 | // Create Date: 03.10.2019 14:15:45 7 | // Design Name: 8 | // Module Name: uart_rx 9 | // Project Name: axis_uart 10 | // Target Devices: All 11 | // Tool Versions: 2018.3 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module uart_rx #( 23 | parameter BAUD_PRESCALER = 12, 24 | parameter PARITY = 0, 25 | parameter BYTE_SIZE = 8, 26 | parameter STOP_BITS = 0, 27 | parameter FIFO_DEPTH = 16 28 | ) 29 | ( 30 | /* AXI-Stream Ports */ 31 | input wire aclk, 32 | input wire aresetn, 33 | /* Dynamic Configuration */ 34 | input wire [23:0]s_axis_config_tdata, 35 | input wire s_axis_config_tvalid, 36 | output wire s_axis_config_tready, 37 | /* Data */ 38 | output wire [15:0]m_axis_tdata, 39 | output wire [0:0]m_axis_tuser, 40 | output wire m_axis_tvalid, 41 | input wire m_axis_tready, 42 | /* UART Port */ 43 | input wire rxd, 44 | output wire rtsn 45 | ); 46 | 47 | localparam STATE_IDLE = 0; 48 | localparam STATE_START = 1; 49 | localparam STATE_BYTE = 2; 50 | localparam STATE_PAR = 3; 51 | localparam STATE_STOP = 4; 52 | localparam STATE_END = 5; 53 | 54 | localparam PARITY_NONE = 3'd0; 55 | localparam PARITY_EVEN = 3'd1; 56 | localparam PARITY_ODD = 3'd2; 57 | localparam PARITY_MARK = 3'd3; 58 | localparam PARITY_SPACE = 3'd4; 59 | 60 | localparam STOP_BITS_ONE = 1'd0; 61 | localparam STOP_BITS_TWO = 1'd1; 62 | 63 | reg [3:0]state; 64 | 65 | reg [15:0]prescaler; 66 | reg [2:0]parity; 67 | reg [3:0]byte_size; 68 | reg [0:0]stop_bits; 69 | 70 | reg pre_en; 71 | wire pre_stb; 72 | wire pre_half; 73 | 74 | reg [15:0]s_data; 75 | reg s_valid; 76 | wire s_ready; 77 | 78 | reg [15:0]rx_data; 79 | reg rx_par; 80 | reg rx_par_rcv; 81 | 82 | reg [7:0]byte_cnt; 83 | reg [15:0]bit_cnt; 84 | reg bit_rec; 85 | 86 | reg parity_error; 87 | 88 | wire afull; 89 | 90 | (* IOB = "TRUE" *) reg rxd_in; 91 | (* IOB = "TRUE" *) reg rtsn_out; 92 | 93 | wire rx_fall; 94 | wire rx_rise; 95 | 96 | assign s_axis_config_tready = (state == STATE_IDLE) ? 1'b1 : 1'b0; 97 | 98 | /* Configuration */ 99 | always @(posedge aclk) begin 100 | if (aresetn == 1'b0) begin 101 | prescaler <= BAUD_PRESCALER; 102 | parity <= PARITY; 103 | byte_size <= BYTE_SIZE; 104 | stop_bits <= STOP_BITS; 105 | end else begin 106 | if ((s_axis_config_tvalid == 1'b1) && (s_axis_config_tready == 1'b1)) begin 107 | prescaler <= s_axis_config_tdata[15:0]; 108 | parity <= s_axis_config_tdata[18:16]; 109 | byte_size <= s_axis_config_tdata[22:19]; 110 | stop_bits <= s_axis_config_tdata[23]; 111 | end 112 | end 113 | end 114 | 115 | /* In */ 116 | always @(posedge aclk) begin 117 | if (aresetn == 1'b0) begin 118 | rxd_in <= 1'b0; 119 | rtsn_out <= 1'b1; 120 | end else begin 121 | rxd_in <= rxd; 122 | rtsn_out <= (afull) ? 1'b1 : 1'b0; 123 | end 124 | end 125 | 126 | /* Bit recognition */ 127 | always @(posedge aclk) begin 128 | if (aresetn == 1'b0) begin 129 | bit_cnt <= 0; 130 | end else begin 131 | if (state != STATE_IDLE) begin 132 | if (pre_stb == 1'b1) begin 133 | bit_cnt <= 0; 134 | end else begin 135 | bit_cnt <= bit_cnt + rxd_in; 136 | end 137 | end else begin 138 | bit_cnt <= 0; 139 | end 140 | end 141 | end 142 | 143 | always @(*) begin 144 | if (aresetn == 1'b0) begin 145 | bit_rec <= 1'b0; 146 | end else begin 147 | if (pre_stb == 1'b1) begin 148 | bit_rec <= (bit_cnt >= {1'b0,prescaler[15:1]}) ? 1'b1 : 1'b0; 149 | end 150 | end 151 | end 152 | 153 | /* State Machine */ 154 | always @(posedge aclk) begin 155 | if (aresetn == 1'b0) begin 156 | pre_en <= 1'b0; 157 | s_data <= 0; 158 | s_valid <= 1'b0; 159 | rx_data <= 0; 160 | byte_cnt <= 0; 161 | rx_par_rcv <= 1'b0; 162 | state <= STATE_IDLE; 163 | end else begin 164 | case (state) 165 | STATE_IDLE: begin 166 | if (rx_fall == 1'b1) begin 167 | pre_en <= 1'b1; 168 | state <= STATE_START; 169 | end else begin 170 | pre_en <= 1'b0; 171 | end 172 | end 173 | STATE_START: begin 174 | if (pre_stb == 1'b1) begin 175 | if (bit_rec == 1'b0) begin 176 | byte_cnt <= 0; 177 | rx_data <= 0; 178 | state <= STATE_BYTE; 179 | end else begin 180 | state <= STATE_IDLE; 181 | end 182 | end 183 | end 184 | STATE_BYTE: begin 185 | if (pre_stb == 1'b1) begin 186 | rx_data[byte_cnt] <= bit_rec; 187 | if (byte_cnt == (byte_size - 1)) begin 188 | if (parity == PARITY_NONE) begin 189 | state <= STATE_STOP; 190 | end else begin 191 | state <= STATE_PAR; 192 | end 193 | end else begin 194 | byte_cnt <= byte_cnt + 1; 195 | end 196 | end 197 | end 198 | STATE_PAR: begin 199 | if (pre_stb == 1'b1) begin 200 | rx_par_rcv <= bit_rec; 201 | state <= STATE_STOP; 202 | end 203 | end 204 | STATE_STOP: begin 205 | if (pre_half == 1'b1) begin 206 | state <= STATE_END; 207 | end 208 | end 209 | STATE_END: begin 210 | if (s_valid == 1'b0) begin 211 | s_valid <= 1'b1; 212 | s_data <= rx_data; 213 | if (rx_par != rx_par_rcv) begin 214 | parity_error <= 1'b1; 215 | end else begin 216 | parity_error <= 1'b0; 217 | end 218 | end else begin 219 | s_valid <= 1'b0; 220 | if (s_ready == 1'b1) begin 221 | end else begin 222 | end 223 | state <= STATE_IDLE; 224 | end 225 | pre_en <= 1'b0; 226 | end 227 | endcase 228 | end 229 | end 230 | 231 | /* Parity Calculation */ 232 | always @(posedge aclk) begin 233 | if (aresetn == 1'b0) begin 234 | rx_par <= 1'b0; 235 | end else begin 236 | case (state) 237 | STATE_BYTE: begin 238 | if (pre_stb == 1'b1) begin 239 | case (parity) 240 | PARITY_EVEN: rx_par <= rx_par + bit_rec; 241 | PARITY_ODD: rx_par <= rx_par + bit_rec; 242 | default: rx_par <= rx_par; 243 | endcase 244 | end 245 | end 246 | STATE_PAR: begin 247 | rx_par <= rx_par; 248 | end 249 | STATE_STOP: begin 250 | rx_par <= rx_par; 251 | end 252 | default: begin 253 | case (parity) 254 | PARITY_EVEN: rx_par <= 1'b0; 255 | PARITY_ODD: rx_par <= 1'b1; 256 | PARITY_MARK: rx_par <= 1'b1; 257 | PARITY_SPACE: rx_par <= 1'b0; 258 | endcase 259 | end 260 | endcase 261 | end 262 | end 263 | 264 | uart_fifo #( 265 | .DATA_WIDTH(16+1), 266 | .DATA_DEPTH(FIFO_DEPTH) 267 | ) fifo_sync_inst ( 268 | .aclk(aclk), 269 | .aresetn(aresetn), 270 | .s_axis_tdata({parity_error,s_data}), 271 | .s_axis_tvalid(s_valid), 272 | .s_axis_tready(s_ready), 273 | .m_axis_tdata({m_axis_tuser,m_axis_tdata}), 274 | .m_axis_tvalid(m_axis_tvalid), 275 | .m_axis_tready(m_axis_tready), 276 | .almost_full(afull) 277 | ); 278 | 279 | uart_prescaler prescaler_inst ( 280 | .clk(aclk), 281 | .rst(~aresetn), 282 | .en(pre_en), 283 | .div(prescaler), 284 | .stb(pre_stb), 285 | .half(pre_half) 286 | ); 287 | 288 | edge_detect #( 289 | .ZERO_DELAY("TRUE") 290 | ) edge_detect_inst ( 291 | .clk(aclk), 292 | .sig(rxd_in), 293 | .fall(rx_fall), 294 | .rise(rx_rise) 295 | ); 296 | 297 | endmodule 298 | 299 | module edge_detect #( 300 | parameter ZERO_DELAY = "FALSE" 301 | ) 302 | ( 303 | input wire clk, 304 | input wire sig, 305 | output wire fall, 306 | output wire rise 307 | ); 308 | 309 | reg [1:0]sig_ff; 310 | reg fall_out; 311 | reg rise_out; 312 | 313 | assign fall = fall_out; 314 | assign rise = rise_out; 315 | 316 | always @(posedge clk) begin 317 | sig_ff[0] <= sig; 318 | sig_ff[1] <= sig_ff[0]; 319 | end 320 | 321 | generate if (ZERO_DELAY == "FALSE") begin 322 | always @(posedge clk) begin 323 | if (sig_ff[0] & ~sig_ff[1]) begin 324 | rise_out <= 1'b1; 325 | end else begin 326 | rise_out <= 1'b0; 327 | end 328 | if (~sig_ff[0] & sig_ff[1]) begin 329 | fall_out <= 1'b1; 330 | end else begin 331 | fall_out <= 1'b0; 332 | end 333 | end 334 | end else begin 335 | always @(sig, sig_ff[0]) begin 336 | rise_out <= sig & ~sig_ff[0]; 337 | fall_out <= ~sig & sig_ff[0]; 338 | end 339 | end endgenerate 340 | 341 | endmodule 342 | -------------------------------------------------------------------------------- /axis_uart_1.0/hdl/uart_tx.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: mcjtag 5 | // 6 | // Create Date: 02.10.2019 14:42:23 7 | // Design Name: 8 | // Module Name: uart_tx 9 | // Project Name: axis_uart 10 | // Target Devices: All 11 | // Tool Versions: 2018.3 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module uart_tx #( 23 | parameter BAUD_PRESCALER = 12, 24 | parameter PARITY = 0, 25 | parameter BYTE_SIZE = 8, 26 | parameter STOP_BITS = 0, 27 | parameter FIFO_DEPTH = 16 28 | ) 29 | ( 30 | /* AXI-Stream Ports */ 31 | input wire aclk, 32 | input wire aresetn, 33 | /* Dynamic Configuration */ 34 | input wire [23:0]s_axis_config_tdata, 35 | input wire s_axis_config_tvalid, 36 | output wire s_axis_config_tready, 37 | /* Data */ 38 | input wire [15:0]s_axis_tdata, 39 | input wire s_axis_tvalid, 40 | output wire s_axis_tready, 41 | /* UART Port */ 42 | output wire txd, 43 | input wire ctsn 44 | ); 45 | 46 | localparam PARITY_NONE = 3'd0; 47 | localparam PARITY_EVEN = 3'd1; 48 | localparam PARITY_ODD = 3'd2; 49 | localparam PARITY_MARK = 3'd3; 50 | localparam PARITY_SPACE = 3'd4; 51 | 52 | localparam STOP_BITS_ONE = 1'd0; 53 | localparam STOP_BITS_TWO = 1'd1; 54 | 55 | localparam STATE_IDLE = 0; 56 | localparam STATE_START = 1; 57 | localparam STATE_BYTE = 2; 58 | localparam STATE_PAR = 3; 59 | localparam STATE_STOP = 4; 60 | localparam STATE_END = 5; 61 | 62 | reg [3:0]state; 63 | 64 | reg [15:0]prescaler; 65 | reg [2:0]parity; 66 | reg [3:0]byte_size; 67 | reg [0:0]stop_bits; 68 | 69 | wire [15:0]m_data; 70 | wire m_valid; 71 | reg m_ready; 72 | 73 | reg [15:0]counter; 74 | 75 | reg pre_en; 76 | wire pre_stb; 77 | 78 | reg [15:0]tx_data; 79 | reg tx_par; 80 | (* IOB = "TRUE" *) reg txd_out; 81 | 82 | assign txd = txd_out; 83 | assign s_axis_config_tready = (state == STATE_IDLE) ? 1'b1 : 1'b0; 84 | 85 | /* Configuration */ 86 | always @(posedge aclk) begin 87 | if (aresetn == 1'b0) begin 88 | prescaler <= BAUD_PRESCALER; 89 | parity <= PARITY; 90 | byte_size <= BYTE_SIZE; 91 | stop_bits <= STOP_BITS; 92 | end else begin 93 | if ((s_axis_config_tvalid == 1'b1) && (s_axis_config_tready == 1'b1)) begin 94 | prescaler <= s_axis_config_tdata[15:0]; 95 | parity <= s_axis_config_tdata[18:16]; 96 | byte_size <= s_axis_config_tdata[22:19]; 97 | stop_bits <= s_axis_config_tdata[23]; 98 | end 99 | end 100 | end 101 | 102 | /* Out */ 103 | always @(posedge aclk) begin 104 | if (aresetn <= 1'b0) begin 105 | txd_out <= 1'b0; 106 | end else begin 107 | case (state) 108 | STATE_IDLE: begin 109 | txd_out <= 1'b1; 110 | end 111 | STATE_START: begin 112 | txd_out <= 1'b0; 113 | end 114 | STATE_BYTE: begin 115 | txd_out <= tx_data[0]; 116 | end 117 | STATE_PAR: begin 118 | txd_out <= tx_par; 119 | end 120 | STATE_STOP: begin 121 | txd_out <= 1'b1; 122 | end 123 | STATE_END: begin 124 | txd_out <= 1'b1; 125 | end 126 | default: begin 127 | txd_out <= 1'b1; 128 | end 129 | endcase 130 | end 131 | end 132 | 133 | /* State Machine */ 134 | always @(posedge aclk) begin 135 | if (aresetn == 1'b0) begin 136 | pre_en <= 1'b0; 137 | m_ready <= 1'b0; 138 | tx_data <= 0; 139 | counter <= 0; 140 | end else begin 141 | case (state) 142 | STATE_IDLE: begin 143 | if (m_ready == 1'b0) begin 144 | if (ctsn == 1'b0) begin 145 | m_ready <= 1'b1; 146 | end 147 | end else begin 148 | if (m_valid == 1'b1) begin 149 | m_ready <= 1'b0; 150 | tx_data <= m_data; 151 | counter <= 0; 152 | pre_en <= 1'b1; 153 | state <= STATE_START; 154 | end 155 | end 156 | end 157 | STATE_START: begin 158 | if (pre_stb == 1'b1) begin 159 | state <= STATE_BYTE; 160 | end 161 | end 162 | STATE_BYTE: begin 163 | if (pre_stb == 1'b1) begin 164 | tx_data[14:0] <= tx_data[15:1]; 165 | if (counter == (byte_size - 1)) begin 166 | counter <= 0; 167 | if (parity == PARITY_NONE) begin 168 | state <= STATE_STOP; 169 | end else begin 170 | state <= STATE_PAR; 171 | end 172 | end else begin 173 | counter <= counter + 1; 174 | end 175 | end 176 | end 177 | STATE_PAR: begin 178 | if (pre_stb == 1'b1) begin 179 | state <= STATE_STOP; 180 | end 181 | end 182 | STATE_STOP: begin 183 | if (pre_stb == 1'b1) begin 184 | case (stop_bits) 185 | STOP_BITS_ONE: begin 186 | state <= STATE_END; 187 | end 188 | STOP_BITS_TWO: begin 189 | if (counter == 1) begin 190 | counter <= 0; 191 | state <= STATE_END; 192 | end else begin 193 | counter <= counter + 1; 194 | end 195 | end 196 | endcase 197 | end 198 | end 199 | STATE_END: begin 200 | if (m_ready == 1'b0) begin 201 | pre_en <= 1'b0; 202 | m_ready <= 1'b1; 203 | end else begin 204 | m_ready <= 1'b0; 205 | if (m_valid == 1'b1) begin 206 | tx_data <= m_data; 207 | pre_en <= 1'b1; 208 | state <= STATE_START; 209 | end else begin 210 | state <= STATE_IDLE; 211 | end 212 | end 213 | end 214 | default: begin 215 | state <= STATE_IDLE; 216 | end 217 | endcase 218 | end 219 | end 220 | 221 | /* Parity Calculation */ 222 | always @(posedge aclk) begin 223 | if (aresetn == 1'b0) begin 224 | tx_par <= 1'b0; 225 | end else begin 226 | case (state) 227 | STATE_BYTE: begin 228 | case (parity) 229 | PARITY_EVEN: tx_par <= tx_par + tx_data[0]; 230 | PARITY_ODD: tx_par <= tx_par + tx_data[0]; 231 | default: tx_par <= tx_par; 232 | endcase 233 | end 234 | STATE_PAR: begin 235 | tx_par <= tx_par; 236 | end 237 | default: begin 238 | case (parity) 239 | PARITY_EVEN: tx_par <= 1'b0; 240 | PARITY_ODD: tx_par <= 1'b1; 241 | PARITY_MARK: tx_par <= 1'b1; 242 | PARITY_SPACE: tx_par <= 1'b0; 243 | endcase 244 | end 245 | endcase 246 | end 247 | end 248 | 249 | uart_fifo #( 250 | .DATA_WIDTH(16), 251 | .DATA_DEPTH(FIFO_DEPTH) 252 | ) fifo_sync_inst ( 253 | .aclk(aclk), 254 | .aresetn(aresetn), 255 | .s_axis_tdata(s_axis_tdata), 256 | .s_axis_tvalid(s_axis_tvalid), 257 | .s_axis_tready(s_axis_tready), 258 | .m_axis_tdata(m_data), 259 | .m_axis_tvalid(m_valid), 260 | .m_axis_tready(m_ready) 261 | ); 262 | 263 | uart_prescaler prescaler_inst ( 264 | .clk(aclk), 265 | .rst(~aresetn), 266 | .en(pre_en), 267 | .div(prescaler), 268 | .stb(pre_stb) 269 | ); 270 | 271 | endmodule 272 | -------------------------------------------------------------------------------- /axis_uart_1.0/xgui/axis_uart_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0" -display_name {Settings}] 6 | set_property tooltip {Settings} ${Page_0} 7 | ipgui::add_param $IPINST -name "BAUD_PRESCALER" -parent ${Page_0} 8 | ipgui::add_param $IPINST -name "PARITY" -parent ${Page_0} -widget comboBox 9 | ipgui::add_param $IPINST -name "BYTE_SIZE" -parent ${Page_0} 10 | ipgui::add_param $IPINST -name "STOP_BITS" -parent ${Page_0} -widget comboBox 11 | ipgui::add_param $IPINST -name "FIFO_DEPTH" -parent ${Page_0} -widget comboBox 12 | ipgui::add_param $IPINST -name "FLOW_CONTROL" -parent ${Page_0} -widget comboBox 13 | ipgui::add_param $IPINST -name "DYNAMIC_CONFIG" -parent ${Page_0} -widget comboBox 14 | 15 | 16 | } 17 | 18 | proc update_PARAM_VALUE.BAUD_PRESCALER { PARAM_VALUE.BAUD_PRESCALER } { 19 | # Procedure called to update BAUD_PRESCALER when any of the dependent parameters in the arguments change 20 | } 21 | 22 | proc validate_PARAM_VALUE.BAUD_PRESCALER { PARAM_VALUE.BAUD_PRESCALER } { 23 | # Procedure called to validate BAUD_PRESCALER 24 | return true 25 | } 26 | 27 | proc update_PARAM_VALUE.BYTE_SIZE { PARAM_VALUE.BYTE_SIZE } { 28 | # Procedure called to update BYTE_SIZE when any of the dependent parameters in the arguments change 29 | } 30 | 31 | proc validate_PARAM_VALUE.BYTE_SIZE { PARAM_VALUE.BYTE_SIZE } { 32 | # Procedure called to validate BYTE_SIZE 33 | return true 34 | } 35 | 36 | proc update_PARAM_VALUE.DYNAMIC_CONFIG { PARAM_VALUE.DYNAMIC_CONFIG } { 37 | # Procedure called to update DYNAMIC_CONFIG when any of the dependent parameters in the arguments change 38 | } 39 | 40 | proc validate_PARAM_VALUE.DYNAMIC_CONFIG { PARAM_VALUE.DYNAMIC_CONFIG } { 41 | # Procedure called to validate DYNAMIC_CONFIG 42 | return true 43 | } 44 | 45 | proc update_PARAM_VALUE.FIFO_DEPTH { PARAM_VALUE.FIFO_DEPTH } { 46 | # Procedure called to update FIFO_DEPTH when any of the dependent parameters in the arguments change 47 | } 48 | 49 | proc validate_PARAM_VALUE.FIFO_DEPTH { PARAM_VALUE.FIFO_DEPTH } { 50 | # Procedure called to validate FIFO_DEPTH 51 | return true 52 | } 53 | 54 | proc update_PARAM_VALUE.FLOW_CONTROL { PARAM_VALUE.FLOW_CONTROL } { 55 | # Procedure called to update FLOW_CONTROL when any of the dependent parameters in the arguments change 56 | } 57 | 58 | proc validate_PARAM_VALUE.FLOW_CONTROL { PARAM_VALUE.FLOW_CONTROL } { 59 | # Procedure called to validate FLOW_CONTROL 60 | return true 61 | } 62 | 63 | proc update_PARAM_VALUE.PARITY { PARAM_VALUE.PARITY } { 64 | # Procedure called to update PARITY when any of the dependent parameters in the arguments change 65 | } 66 | 67 | proc validate_PARAM_VALUE.PARITY { PARAM_VALUE.PARITY } { 68 | # Procedure called to validate PARITY 69 | return true 70 | } 71 | 72 | proc update_PARAM_VALUE.STOP_BITS { PARAM_VALUE.STOP_BITS } { 73 | # Procedure called to update STOP_BITS when any of the dependent parameters in the arguments change 74 | } 75 | 76 | proc validate_PARAM_VALUE.STOP_BITS { PARAM_VALUE.STOP_BITS } { 77 | # Procedure called to validate STOP_BITS 78 | return true 79 | } 80 | 81 | 82 | proc update_MODELPARAM_VALUE.BAUD_PRESCALER { MODELPARAM_VALUE.BAUD_PRESCALER PARAM_VALUE.BAUD_PRESCALER } { 83 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 84 | set_property value [get_property value ${PARAM_VALUE.BAUD_PRESCALER}] ${MODELPARAM_VALUE.BAUD_PRESCALER} 85 | } 86 | 87 | proc update_MODELPARAM_VALUE.PARITY { MODELPARAM_VALUE.PARITY PARAM_VALUE.PARITY } { 88 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 89 | set_property value [get_property value ${PARAM_VALUE.PARITY}] ${MODELPARAM_VALUE.PARITY} 90 | } 91 | 92 | proc update_MODELPARAM_VALUE.BYTE_SIZE { MODELPARAM_VALUE.BYTE_SIZE PARAM_VALUE.BYTE_SIZE } { 93 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 94 | set_property value [get_property value ${PARAM_VALUE.BYTE_SIZE}] ${MODELPARAM_VALUE.BYTE_SIZE} 95 | } 96 | 97 | proc update_MODELPARAM_VALUE.STOP_BITS { MODELPARAM_VALUE.STOP_BITS PARAM_VALUE.STOP_BITS } { 98 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 99 | set_property value [get_property value ${PARAM_VALUE.STOP_BITS}] ${MODELPARAM_VALUE.STOP_BITS} 100 | } 101 | 102 | proc update_MODELPARAM_VALUE.FIFO_DEPTH { MODELPARAM_VALUE.FIFO_DEPTH PARAM_VALUE.FIFO_DEPTH } { 103 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 104 | set_property value [get_property value ${PARAM_VALUE.FIFO_DEPTH}] ${MODELPARAM_VALUE.FIFO_DEPTH} 105 | } 106 | 107 | proc update_MODELPARAM_VALUE.FLOW_CONTROL { MODELPARAM_VALUE.FLOW_CONTROL PARAM_VALUE.FLOW_CONTROL } { 108 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 109 | set_property value [get_property value ${PARAM_VALUE.FLOW_CONTROL}] ${MODELPARAM_VALUE.FLOW_CONTROL} 110 | } 111 | 112 | proc update_MODELPARAM_VALUE.DYNAMIC_CONFIG { MODELPARAM_VALUE.DYNAMIC_CONFIG PARAM_VALUE.DYNAMIC_CONFIG } { 113 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 114 | set_property value [get_property value ${PARAM_VALUE.DYNAMIC_CONFIG}] ${MODELPARAM_VALUE.DYNAMIC_CONFIG} 115 | } 116 | 117 | --------------------------------------------------------------------------------