├── design
    ├── adder.v
    ├── mux.v
    ├── mux3to1.v
    ├── First_register.v
    ├── Control_unit.v
    ├── registerfile.v
    ├── alu.v
    ├── alucontrol.v
    ├── Second_Register.v
    ├── datamem.v
    ├── immext.v
    ├── controlunit.v
    ├── Fifth_register.v
    ├── Fourth_register.v
    ├── Hazard_unit.v
    ├── Third_register.v
    ├── Risc_v_pipelined.v
    └── instmem.v
├── testbench
    └── Risc_v_pipelined_tb.v
├── LICENSE
└── README.md


/design/adder.v:
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1 | `timescale 1ns / 1ps
2 | module adder(s,t,u);
3 | input [31:0] s,t;
4 | output [31:0] u;
5 | assign u = s+t;
6 | endmodule


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/design/mux.v:
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1 | `timescale 1ns / 1ps
2 | module mux(m,n,sel,out);
3 | input [31:0]m,n;
4 | input sel;
5 | output [31:0]out;
6 | assign out = sel ? n : m;
7 | endmodule 


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/design/mux3to1.v:
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1 | `timescale 1ns / 1ps
2 | module mux3to1(m,n,o,sel,out);
3 | input [31:0]m,n,o;
4 | input [1:0] sel;
5 | output [31:0]out;
6 | assign out = (sel==2'b00) ? m : 
7 | 				 (sel==2'b01) ? n :
8 | 				 (sel==2'b10) ? o : 32'bx;
9 | endmodule 


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/design/First_register.v:
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 1 | `timescale 1ns / 1ps
 2 | module First_register (clk, reset, enable, PC, PCF);
 3 | 
 4 | input clk, reset, enable;
 5 | input [31:0] PC;
 6 | output reg [31:0] PCF;
 7 | 
 8 | always @ (posedge clk)
 9 | begin
10 | if (reset)
11 | PCF <= 0;
12 | 
13 | else if (enable)
14 | PCF <= PCF;
15 | 
16 | else
17 | PCF <= PC;
18 | 
19 | end
20 | 
21 | endmodule
22 | 


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/testbench/Risc_v_pipelined_tb.v:
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 1 | `timescale 1ns / 1ps
 2 | module Risc_v_pipelined_tb;
 3 |   reg clk, reset;
 4 |   Risc_v_pipelined dut (
 5 |     .clk(clk),
 6 |     .reset(reset)
 7 |   );
 8 |   initial begin
 9 |     clk = 0;
10 |     forever #5 clk = ~clk;
11 |   end
12 |   initial begin
13 |     reset = 1;
14 |     #10 reset = 0;  
15 |     #100 $stop; 
16 |   end
17 |   initial begin
18 |     $monitor("Time: %0t | clk: %b | reset: %b", $time, clk, reset);
19 |   end
20 | 
21 | endmodule
22 | 


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/design/Control_unit.v:
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 1 | `timescale 1ns / 1ps
 2 | module Control_unit(opcode,funct3,funct7,alusrc,resultsrc,immsrc,regwrite,memwrite,alucontrol,branch, jump);
 3 | input [6:0] opcode;
 4 | input funct7;
 5 | input [2:0] funct3;
 6 | output [2:0] alucontrol;
 7 | output [1:0] immsrc,resultsrc;
 8 | output memwrite,alusrc,regwrite;
 9 | output branch,jump;
10 | wire [1:0] aluop;
11 | 
12 | controlunit u1(opcode,branch,jump,immsrc,resultsrc,aluop,memwrite,alusrc,regwrite);
13 | alucontrol u2(aluop,funct3,funct7,alucontrol);
14 | endmodule


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/design/registerfile.v:
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 1 | `timescale 1ns / 1ps
 2 | module registerfile(rs1,rs2,rd,writedata,regwrite,rd1,rd2,clk);
 3 | input [4:0] rs1,rs2,rd;
 4 | input [31:0] writedata;
 5 | input regwrite,clk;
 6 | output [31:0] rd1,rd2;
 7 | reg [31:0] rf [31:0];
 8 | assign rd1 = rf[rs1];
 9 | assign rd2 = rf[rs2];
10 | integer i;
11 | always @(negedge clk)
12 | if (regwrite)
13 |  begin
14 |  rf[rd] = writedata;
15 |  end
16 | initial 
17 | begin
18 |   for(i=0; i<32; i=i+1)
19 |  begin
20 |  rf[i] = 0;
21 |  end
22 | end
23 | endmodule
24 | 


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/design/alu.v:
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 1 | `timescale 1ns / 1ps
 2 | module alu(a,b,aluoperation,zero,result);
 3 | input [31:0] a,b;
 4 | input [2:0]aluoperation;
 5 | output reg zero;
 6 | output reg [31:0] result;
 7 | 
 8 |  always @ (*)
 9 | begin
10 |  case(aluoperation)
11 |  3'b000: result=a+b;
12 |  3'b001: result=a-b;
13 |  3'b101: result=a<b;
14 |  3'b011: result=a|b;
15 |  3'b010: result=a&b;
16 |  default: result=32'bx;
17 |  endcase
18 | end
19 | always @ (result)
20 | begin 
21 |  if (result)
22 |  zero = 0;
23 |  else
24 |  zero = 1;
25 | end
26 | endmodule


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/design/alucontrol.v:
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 1 | `timescale 1ns / 1ps
 2 | module alucontrol(aluop,funct3,funct7,operation);
 3 | input [1:0] aluop;
 4 | input [2:0] funct3;
 5 | input funct7;
 6 | output reg [2:0] operation;
 7 | 
 8 |   always @(*)
 9 | begin 
10 | case(aluop)
11 | 2'b00: operation=3'b000;
12 | 2'b01: operation=3'b001;
13 | 2'b10: begin
14 |        case(funct3)
15 |        3'b000:operation=funct7? 3'b001 : 3'b000;
16 |        3'b111:operation=3'b010;
17 |        3'b110:operation=3'b011;
18 |        3'b010:operation=3'b101;
19 |        default: operation = 3'bxxx;
20 |        endcase
21 |        end
22 | default: operation= 3'bxxx;
23 | endcase
24 | end
25 | endmodule 


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/design/Second_Register.v:
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 1 | `timescale 1ns / 1ps
 2 | module Second_Register (clk, reset, clr,en,InstrF,PCF,PCplus4F, InstrD, PCD, PCplus4D);
 3 | input clk, reset, clr, en;
 4 | input [31:0] InstrF, PCF, PCplus4F;
 5 | output reg [31:0] InstrD, PCD, PCplus4D;
 6 | 
 7 | always @ (posedge clk)
 8 | begin
 9 | if (reset | clr)
10 | begin
11 | PCD      <= 0;
12 | InstrD   <= 0;
13 | PCplus4D <= 0;
14 | end
15 | 
16 | else if (en)
17 | begin
18 | PCD      <= PCD;
19 | InstrD   <= InstrD;
20 | PCplus4D <= PCplus4D;
21 | end
22 | 
23 | else 
24 | begin
25 | PCD      <= PCF;
26 | InstrD   <= InstrF;
27 | PCplus4D <= PCplus4F;
28 | end
29 | 
30 | end
31 | 
32 | endmodule 


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/design/datamem.v:
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 1 | `timescale 1ns / 1ps
 2 | module datamem(mem_addr,write_data,clk,memwrite,read_data);
 3 | input [31:0] mem_addr,write_data;
 4 | input clk,memwrite;
 5 | output [31:0] read_data;
 6 | reg [7:0] ram_dm [109:0];
 7 | integer i;
 8 | initial 
 9 | begin
10 |  for(i=0; i<109; i=i+4) 
11 |  ram_dm[i] = i;
12 | end
13 | initial 
14 | begin
15 |  for(i=0; i<109; i=i+1) 
16 |  ram_dm[i] = 0;
17 | end
18 | assign read_data = {ram_dm[mem_addr+3],ram_dm[mem_addr+2],ram_dm[mem_addr+1],ram_dm[mem_addr]};
19 | always @(posedge clk)
20 | begin
21 |  if (memwrite)
22 |  {ram_dm[mem_addr+3],ram_dm[mem_addr+2],ram_dm[mem_addr+1],ram_dm[mem_addr]} = write_data;
23 | end
24 | endmodule 


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/design/immext.v:
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 1 | `timescale 1ns / 1ps
 2 | module immext(instruction,immsrc,imm_data);
 3 | input [31:0] instruction;
 4 | input [1:0] immsrc;
 5 | output [31:0] imm_data;
 6 | reg [31:0] imm_data;
 7 | always @(*)
 8 | begin
 9 |   case(immsrc)
10 |  2'b00: imm_data = {{20{instruction[31]}},instruction[31:20]};                                         //I
11 |  2'b01: imm_data = {{20{instruction[31]}},instruction[31:25],instruction[11:7]};                       //S
12 |  2'b10: imm_data = {{20{instruction[31]}},instruction[7],instruction[30:25],instruction[11:8],1'b0};   //B
13 |  2'b11: imm_data = {{12{instruction[31]}},instruction[19:12],instruction[20],instruction[30:21],1'b0}; //J
14 |  default: imm_data = 32'bx;
15 |  endcase
16 | end
17 | endmodule


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/design/controlunit.v:
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 1 | `timescale 1ns / 1ps
 2 | module controlunit(opcode,branch, jump,immsrc,resultsrc,aluop,memwrite,alusrc,regwrite);
 3 | input [6:0] opcode;
 4 | output [1:0] immsrc,resultsrc,aluop;
 5 | output branch, jump,memwrite,alusrc,regwrite;
 6 | wire [10:0] controls;
 7 | assign {alusrc, resultsrc, immsrc, regwrite, memwrite, branch,jump, aluop} = controls;
 8 | 
 9 | assign controls = 
10 |         (opcode == 7'b0110011) ? 11'b0_00_xx_1_0_0_0_10: // r type
11 | 		  (opcode == 7'b0000011) ? 11'b1_01_00_1_0_0_0_00: // lw type
12 | 		  (opcode == 7'b0100011) ? 11'b1_xx_01_0_1_0_0_00: // sw type (sw)
13 | 		  (opcode == 7'b1100011) ? 11'b0_xx_10_0_0_1_0_01: // sb  type(beq)
14 | 		  (opcode == 7'b0010011) ? 11'b1_00_00_1_0_0_0_00: // addi type (addi)
15 | 		  (opcode == 7'b1101111) ? 11'bx_10_11_1_0_0_1_xx: // j type (jal)  
16 | 		                           11'b0_00_00_0_0_0_0_00;
17 | endmodule
18 | 


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/design/Fifth_register.v:
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 1 | `timescale 1ns / 1ps
 2 | module Fifth_register (clk, reset, RegWriteM, ResultSrcM, rdM, PCplus4M, RegWriteW, ResultSrcW, rdW, PCplus4W, ALUResultW, ReadDataW, ALUResultM, ReadDataM);
 3 | input clk, reset, RegWriteM; 
 4 | input [1:0] ResultSrcM;
 5 | input [4:0] rdM;
 6 | input [31:0] PCplus4M, ALUResultM, ReadDataM;
 7 | output reg RegWriteW;   
 8 | output reg [1:0] ResultSrcW;
 9 | output reg [4:0] rdW;
10 | output reg [31:0] PCplus4W, ALUResultW, ReadDataW;
11 | 
12 | always @ (posedge clk)
13 | begin
14 | if (reset)
15 | begin
16 | PCplus4W   <= 0;
17 | rdW        <= 0;
18 | ResultSrcW <= 0;
19 | RegWriteW  <= 0;
20 | ALUResultW <= 0;
21 | ReadDataW  <= 0;
22 | end
23 | 
24 | else 
25 | begin
26 | PCplus4W   <= PCplus4M;
27 | rdW        <= rdM;
28 | ResultSrcW <= ResultSrcM;
29 | RegWriteW  <= RegWriteM;
30 | ALUResultW <= ALUResultM;
31 | ReadDataW  <= ReadDataM;
32 | end
33 | 
34 | end
35 | 
36 | endmodule 


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/design/Fourth_register.v:
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 1 | `timescale 1ns / 1ps
 2 | module Fourth_register (clk, reset, RegWriteM,MemWriteM, ResultSrcM, rdM, PCplus4M, RegWriteE, MemWriteE, ResultSrcE, rdE, PCplus4E, ALUResultE, WriteDataE, ALUResultM, WriteDataM);
 3 | input clk, reset, RegWriteE,MemWriteE; 
 4 | input [1:0] ResultSrcE;
 5 | input [4:0] rdE;
 6 | input [31:0] PCplus4E, ALUResultE, WriteDataE;
 7 | output reg RegWriteM,MemWriteM;   
 8 | output reg [1:0] ResultSrcM;
 9 | output reg [4:0] rdM;
10 | output reg [31:0] PCplus4M, ALUResultM, WriteDataM;
11 | 
12 | always @ (posedge clk)
13 | begin
14 | if (reset)
15 | begin
16 | PCplus4M   <= 0;
17 | rdM        <= 0;
18 | ResultSrcM <= 0;
19 | RegWriteM  <= 0;
20 | MemWriteM  <= 0;
21 | ALUResultM <= 0;
22 | WriteDataM <= 0;
23 | end
24 | 
25 | else
26 | begin 
27 | PCplus4M   <= PCplus4E;
28 | rdM        <= rdE;
29 | ResultSrcM <= ResultSrcE;
30 | RegWriteM  <= RegWriteE;
31 | MemWriteM  <= MemWriteE;
32 | ALUResultM <= ALUResultE;
33 | WriteDataM <= WriteDataE;
34 | end
35 | 
36 | end
37 | 
38 | endmodule 


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/design/Hazard_unit.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | module Hazard_unit (rs1D,rs2D,rs1E,rs2E,rdM,rdW,RegWriteM,RegWriteW,rdE,ResultSrcE,PCSrcE,ForwardAE,ForwardBE,StallD,StallF,FlushE,FlushD);
 3 | input [4:0] rs1E,rs2E,rs1D,rs2D,rdM,rdW,rdE;
 4 | input PCSrcE,RegWriteM,RegWriteW;
 5 | input [1:0] ResultSrcE;
 6 | output reg [1:0] ForwardAE,ForwardBE;
 7 | output StallF,StallD,FlushE,FlushD;
 8 | wire lwstall;
 9 | 
10 | always @(*)
11 | begin
12 | if (((rs1E == rdM) & RegWriteM) & (rs1E !=0))
13 | ForwardAE=2'b10;
14 | else if (((rs1E == rdW) & RegWriteW) & (rs1E !=0))
15 | ForwardAE=2'b01;
16 | else
17 | ForwardAE=2'b00; 
18 | end
19 | 
20 | always @(*)
21 | begin
22 | if (((rs2E == rdM) & RegWriteM) & (rs2E !=0))
23 | ForwardBE=2'b10;
24 | else if (((rs2E == rdW) & RegWriteW) & (rs2E !=0))
25 | ForwardBE=2'b01;
26 | else
27 | ForwardBE=2'b00; 
28 | end
29 | 
30 | assign lwstall = (ResultSrcE && ((rs1D==rdE)|(rs2D==rdE)));
31 | assign StallF = lwstall;
32 | assign StallD = lwstall;
33 | assign FlushE = lwstall | PCSrcE;
34 | assign FlushD = PCSrcE;
35 | 
36 | endmodule 


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/LICENSE:
--------------------------------------------------------------------------------
 1 | MIT License
 2 | 
 3 | Copyright (c) 2024 Mehwish Aleem
 4 | 
 5 | Permission is hereby granted, free of charge, to any person obtaining a copy
 6 | of this software and associated documentation files (the "Software"), to deal
 7 | in the Software without restriction, including without limitation the rights
 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 9 | copies of the Software, and to permit persons to whom the Software is
10 | furnished to do so, subject to the following conditions:
11 | 
12 | The above copyright notice and this permission notice shall be included in all
13 | copies or substantial portions of the Software.
14 | 
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 | SOFTWARE.
22 | 


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/design/Third_register.v:
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 1 | `timescale 1ns / 1ps
 2 | module Third_register (clk, reset, clr,RegWriteD,MemWriteD, JumpD, BranchD, ALUSrcD, ALUControlD,ResultSrcD, ImmSrcD, rdD, RD1D, RD2D, PCD, ImmExtD, PCplus4D, RegWriteE,MemWriteE, JumpE, BranchE, ALUSrcE, ALUControlE, ResultSrcE, rdE, RD1E, RD2E, PCE, ImmExtE, PCplus4E,rs1D,rs2D,rs1E,rs2E);
 3 | input clk, reset, clr, RegWriteD,MemWriteD, JumpD, BranchD, ALUSrcD; 
 4 | input [2:0] ALUControlD;  
 5 | input [1:0] ResultSrcD, ImmSrcD;
 6 | input [4:0] rdD,rs1D,rs2D;
 7 | input [31:0] RD1D, RD2D, PCD, ImmExtD, PCplus4D;
 8 | output reg RegWriteE,MemWriteE, JumpE, BranchE, ALUSrcE; 
 9 | output reg  [2:0] ALUControlE;  
10 | output reg [1:0] ResultSrcE;
11 | output reg [4:0] rdE,rs1E,rs2E;
12 | output reg [31:0] RD1E, RD2E, PCE, ImmExtE, PCplus4E;
13 | 
14 | always @ (posedge clk)
15 | begin
16 | if (reset | clr)
17 | begin
18 | RD1E       <= 0;
19 | RD2E       <= 0;
20 | PCE        <= 0;
21 | ImmExtE    <= 0;
22 | PCplus4E   <= 0;
23 | rdE        <= 0;
24 | rs1E       <= 0;
25 | rs2E       <= 0;
26 | ResultSrcE <= 0;
27 | ALUControlE<= 0;
28 | RegWriteE  <= 0;
29 | MemWriteE  <= 0;
30 | JumpE      <= 0;
31 | BranchE    <= 0;
32 | ALUSrcE    <= 0;
33 | end
34 | 
35 | else 
36 | begin
37 | RD1E       <= RD1D;
38 | RD2E       <= RD2D;
39 | PCE        <= PCD;
40 | ImmExtE    <= ImmExtD;
41 | PCplus4E   <= PCplus4D;
42 | rdE        <= rdD;
43 | rs1E       <= rs1D;
44 | rs2E       <= rs2D;
45 | ResultSrcE <= ResultSrcD;
46 | ALUControlE<= ALUControlD;
47 | RegWriteE  <= RegWriteD;
48 | MemWriteE  <= MemWriteD;
49 | JumpE      <= JumpD;
50 | BranchE    <= BranchD;
51 | ALUSrcE    <= ALUSrcD;
52 | end
53 | 
54 | end
55 | 
56 | endmodule 


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/README.md:
--------------------------------------------------------------------------------
 1 | # 5-Staged-Pipelined-RISC-V-32I-Processor
 2 | 5 stage pipeline implementation of RISC-V 32I Processor.
 3 | In this repository, I have implemented a 5-stage pipelined processor. This project displays the design and implementation of a processor with pipelining, showing the transition from a theoretical single-cycle processor design to an efficient pipelined architecture.
 4 | 
 5 | For 5 staged pipelining, we'll divide our instruction into 5 different stages:
 6 | * Instruction Fetch
 7 | * Instruction Decode
 8 | * Instruction Execution
 9 | * Memory Read/Write
10 | * Write Back
11 |   
12 | This pipelined implementation of processor supports six basic instructions:
13 | * R-Type
14 | * I-Type
15 | * S-Type
16 | * B-Type
17 | * J-Type
18 | * U-Type <br>
19 | 
20 | A Hazard Unit has been implemented in this design to handle both data hazards and control hazards in the pipelined processor architecture.
21 | # Architecture
22 | We will add four registers in between the complete datapath. These registers store and track different parts of instructions as they pass through the pipeline. They make sure the instructions are properly moved through all five stages so they can execute correctly. This setup ensures the needed data is available to each stage at the right time for proper execution.
23 | ![image](https://github.com/user-attachments/assets/cbbb7163-a9d1-4dff-8df3-c15852db8c57)
24 | 
25 | # RTL View:
26 | ![image](https://github.com/user-attachments/assets/95489537-a116-459d-b97e-ace88d61a31d)
27 | 
28 | ## Instructions Used:
29 | * addi x1, x0, 0xA	   
30 | * addi x2, x0, 0x5	   
31 | * addi x3, x0, 0xF	   
32 | * add x4, x1, x2	      
33 | * xor x5, x4, x3	      
34 | * or x6, x4, x3        	
35 | * and x7, x5, x6	     
36 | * sll x8, x7, 2	        
37 | * srl x9, x8, 1	        
38 | * sw x4, 0x100(x0)	  
39 | * sw x5, 0x104(x0)	    
40 | * lw x10, 0x100(x0)    
41 | * lw x11, 0x104(x0)   
42 | * slt x12, x10, x11   
43 | * bne x12, x0, Skip	   
44 | * addi x13, x0, 0xFF	  
45 | * sub x14, x11, x10	   
46 | * mul x15, x14, x3	   
47 | 
48 | # Simulation Results
49 | ![sim1](https://github.com/user-attachments/assets/8200b374-569f-4efc-8076-6a795114cbde)
50 | ![sim2](https://github.com/user-attachments/assets/63aef183-cac5-4fe6-b8d0-a217deb7a509)
51 | ![sim3](https://github.com/user-attachments/assets/3a48fda7-7390-4266-9983-112e561da53a)
52 | ![sim5](https://github.com/user-attachments/assets/ede61faf-d743-4618-b134-3a94c966e46f)
53 | 


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/design/Risc_v_pipelined.v:
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 1 | `timescale 1ns / 1ps
 2 | module Risc_v_pipelined (clk,reset);
 3 | input clk, reset;
 4 | wire [31:0] PCplus4F,PC, PCF,InstrF;
 5 | wire [31:0] RD1D,RD2D, InstrD,PCD, PCplus4D,ImmExtD;
 6 | wire [31:0] PCTargetE,RD1E, RD2E, PCE, ImmExtE,PCplus4E, SrcAE, SrcBE, Src2BE,ALUResultE;
 7 | wire [31:0] PCplus4M,ALUResultM, WriteDataM,ReadDataM;
 8 | wire [31:0] ResultW, PCplus4W,ALUResultW,ReadDataW;
 9 | wire [4:0] rdW, rdE, rdM,rs1E,rs2E;
10 | wire [2:0] ALUControlE,ALUControlD;
11 | wire [1:0] ResultSrcE,ResultSrcD,ImmSrcD,ResultSrcM,ResultSrcW,ForwardAE,ForwardBE;
12 | wire PCSrcE,BranchE,JumpE,ALUSrcE,RegWriteE,MemWriteE,ZeroE;
13 | wire BranchD,JumpD,ALUSrcD,RegWriteD,MemWriteD;
14 | wire RegWriteM,MemWriteM;
15 | wire RegWriteW;
16 | wire StallD,StallF,FlushE,FlushD;
17 | //sub_blocks:
18 | mux PCSrc (PCplus4F,PCTargetE,PCSrcE,PC);
19 | First_register FR (clk, reset, StallF, PC, PCF);
20 | instmem IM (PCF,InstrF);
21 | adder PCplus4 (PCF,32'b100,PCplus4F);
22 | Second_Register SR (clk, reset, FlushD,StallD,InstrF,PCF,PCplus4F, InstrD, PCD, PCplus4D);
23 | Control_unit CU (InstrD[6:0],InstrD[14:12],InstrD[30],ALUSrcD,ResultSrcD,ImmSrcD,RegWriteD,MemWriteD,ALUControlD,BranchD,JumpD);
24 | registerfile RF (InstrD[19:15],InstrD[24:20],rdW,ResultW,RegWriteW,RD1D,RD2D,clk);
25 | immext Im_Ext (InstrD,ImmSrcD,ImmExtD);
26 | Third_register TR (clk, reset, FlushE,RegWriteD,MemWriteD, JumpD, BranchD, ALUSrcD, ALUControlD,ResultSrcD, ImmSrcD, InstrD[11:7], RD1D, RD2D, PCD, ImmExtD, PCplus4D, RegWriteE,MemWriteE, JumpE, BranchE, ALUSrcE, ALUControlE, ResultSrcE, rdE, RD1E, RD2E, PCE, ImmExtE, PCplus4E,InstrD[19:15],InstrD[24:20],rs1E,rs2E);
27 | mux ALUSrc (SrcBE,ImmExtE,ALUSrcE,Src2BE);
28 | adder PCplusImm	(PCE,ImmExtE,PCTargetE);
29 | alu ALU (SrcAE,Src2BE,ALUControlE,ZeroE,ALUResultE);
30 | assign PCSrcE = JumpE | (BranchE & ZeroE);
31 | Fourth_register FRR (clk, reset, RegWriteM,MemWriteM, ResultSrcM, rdM, PCplus4M, RegWriteE, MemWriteE, ResultSrcE, rdE, PCplus4E, ALUResultE, SrcBE, ALUResultM, WriteDataM);
32 | datamem DM (ALUResultM,WriteDataM,clk,MemWriteM,ReadDataM);
33 | Fifth_register FIFR (clk, reset, RegWriteM, ResultSrcM, rdM, PCplus4M, RegWriteW, ResultSrcW, rdW, PCplus4W, ALUResultW, ReadDataW, ALUResultM, ReadDataM);
34 | mux3to1 resultSrc (ALUResultW,ReadDataW,PCplus4W,ResultSrcW,ResultW);
35 | Hazard_unit HU (InstrD[19:15],InstrD[24:20],rs1E,rs2E,rdM,rdW,RegWriteM,RegWriteW,rdE,ResultSrcE,PCSrcE,ForwardAE,ForwardBE,StallD,StallF,FlushE,FlushD);
36 | mux3to1 SrcA (RD1E,ResultW,ALUResultM,ForwardAE,SrcAE);
37 | mux3to1 SrcB (RD2E,ResultW,ALUResultM,ForwardBE,SrcBE);
38 | endmodule 
39 | 
40 | 


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/design/instmem.v:
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  1 | `timescale 1ns / 1ps
  2 | module instmem(instr_addr,instruction);
  3 | input [31:0] instr_addr;
  4 | output [31:0] instruction;
  5 | reg[31:0] instruction;
  6 | reg [7:0] ram [90:0];
  7 | initial
  8 |   begin
  9 |     ram[0]  = 8'b00010011;
 10 | ram[1]  = 8'b00000000;
 11 | ram[2]  = 8'b10100000;
 12 | ram[3]  = 8'b00000000;
 13 | 
 14 | ram[4]  = 8'b10010011;
 15 | ram[5]  = 8'b00000101;
 16 | ram[6]  = 8'b01010000;
 17 | ram[7]  = 8'b00000000;
 18 | 
 19 | ram[8]  = 8'b00010011;
 20 | ram[9]  = 8'b00000000;
 21 | ram[10] = 8'b11110000;
 22 | ram[11] = 8'b00000000;
 23 | 
 24 | ram[12] = 8'b10110011;
 25 | ram[13] = 8'b10000001;
 26 | ram[14] = 8'b00100000;
 27 | ram[15] = 8'b00000000;
 28 | 
 29 | ram[16] = 8'b00110011;
 30 | ram[17] = 8'b10100010;
 31 | ram[18] = 8'b00110001;
 32 | ram[19] = 8'b00000000;
 33 | 
 34 | ram[20] = 8'b00110011;
 35 | ram[21] = 8'b10110010;
 36 | ram[22] = 8'b00110001;
 37 | ram[23] = 8'b00000000;
 38 | 
 39 | ram[24] = 8'b00110011;
 40 | ram[25] = 8'b10110011;
 41 | ram[26] = 8'b01100010;
 42 | ram[27] = 8'b00000000;
 43 | 
 44 | ram[28] = 8'b10110011;
 45 | ram[29] = 8'b10110011;
 46 | ram[30] = 8'b00100011;
 47 | ram[31] = 8'b00000000;
 48 | 
 49 | ram[32] = 8'b10110011;
 50 | ram[33] = 8'b11000011;
 51 | ram[34] = 8'b00010011;
 52 | ram[35] = 8'b00000000;
 53 | 
 54 | ram[36] = 8'b00100011;
 55 | ram[37] = 8'b00100000;
 56 | ram[38] = 8'b01000001;
 57 | ram[39] = 8'b00000000;
 58 | 
 59 | ram[40] = 8'b10100011;
 60 | ram[41] = 8'b00100000;
 61 | ram[42] = 8'b01010001;
 62 | ram[43] = 8'b00000000;
 63 | 
 64 | ram[44] = 8'b10000011;
 65 | ram[45] = 8'b00100010;
 66 | ram[46] = 8'b00000001;
 67 | ram[47] = 8'b00000000;
 68 | 
 69 | ram[48] = 8'b00000011;
 70 | ram[49] = 8'b00100011;
 71 | ram[50] = 8'b01000001;
 72 | ram[51] = 8'b00000000;
 73 | 
 74 | ram[52] = 8'b00110011;
 75 | ram[53] = 8'b01100011;
 76 | ram[54] = 8'b10110010;
 77 | ram[55] = 8'b00000000;
 78 | 
 79 | ram[56] = 8'b11100011;
 80 | ram[57] = 8'b00011100;
 81 | ram[58] = 8'b00100010;
 82 | ram[59] = 8'b11111110;
 83 | 
 84 | ram[60] = 8'b10010011;
 85 | ram[61] = 8'b00000110;
 86 | ram[62] = 8'b11111111;
 87 | ram[63] = 8'b00000000;
 88 | 
 89 | ram[64] = 8'b00110011;
 90 | ram[65] = 8'b01100011;
 91 | ram[66] = 8'b10100011;
 92 | ram[67] = 8'b01000000;
 93 | 
 94 | ram[68] = 8'b10110011;
 95 | ram[69] = 8'b11100011;
 96 | ram[70] = 8'b00110011;
 97 | ram[71] = 8'b00000000;
 98 | 
 99 |   end
100 |     always @(instr_addr)
101 | instruction = {ram[instr_addr+3],ram[instr_addr+2],ram[instr_addr+1],ram[instr_addr]};
102 | endmodule
103 | 


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