├── .gitignore
├── DiyLC
├── Clock_Bias.diy
├── FlipFlop.diy
├── Latch1.diy
├── Ring.diy
├── Shaper.diy
└── Startpulse.diy
├── GenerateKCS
└── GenerateKCS.ino
├── Images
├── 3Ddisplay-1.jpg
├── 3Ddisplay-2.jpg
├── 3d-display-cad.png
├── 5stageRing-PCB.jpg
├── AllHookedUp.jpg
├── ArduinoOutput1.png
├── Audio_Serial-Breadboard.jpg
├── Audio_Serial-Layout.png
├── Audio_Serial-Oscilloscope.png
├── Audio_Serial-PCB-built.jpg
├── Audio_Serial-PCB-empty.jpg
├── Audio_Serial-Schematics.png
├── Bias-Schematics.png
├── BlockDiagram1.png
├── Clock_Bias-Layout.png
├── Clock_Bias-PCB.jpg
├── Clockgen-Breadboard.jpg
├── Clockgen-Schematics.png
├── DoublePulses.png
├── Filter.png
├── FilterSchematics.png
├── IntegrationTesting.jpg
├── Latch1-schematics.png
├── LatchWbuffer-pcb.jpg
├── MoreParts.jpg
├── PageHeader.gvdesign
├── PageHeader.png
├── QuadLatch-PCB.jpg
├── Ring-Layout.png
├── RingCounter-Breadboard.jpg
├── RingCounter_Clock_Bias-Block.png
├── Ringcounter-Oscilloscope.png
├── Ringcounter_Stage-Schematics.png
├── SR-test.png
├── SR_FlipFlop-Test.jpg
├── SR_FlipFlop-schematics.png
├── StartbitDelay.jpg
├── Startbit_delayer-schematics.png
├── TwoRingcounters.jpg
├── startbit-delay.png
├── startbit_monoflop-schematics.png
├── tape.jpg
├── vcc-after.png
└── vcc-before.png
├── README.md
└── notes.txt
/.gitignore:
--------------------------------------------------------------------------------
1 | #-------------------------------------
2 | # OSX
3 | #-------------------------------------
4 | .DS_Store
5 |
6 | #-------------------------------------
7 | # EDITOR BACKUP FILES
8 | #-------------------------------------
9 | *~
10 |
11 | #-------------------------------------
12 | # C
13 | #-------------------------------------
14 |
15 | # Prerequisites
16 | *.d
17 |
18 | # Object files
19 | *.o
20 | *.ko
21 | *.obj
22 | *.elf
23 |
24 | # Linker output
25 | *.ilk
26 | *.map
27 | *.exp
28 |
29 | # Precompiled Headers
30 | *.gch
31 | *.pch
32 |
33 | # Libraries
34 | *.lib
35 | *.a
36 | *.la
37 | *.lo
38 |
39 | # Shared objects (inc. Windows DLLs)
40 | *.dll
41 | *.so
42 | *.so.*
43 | *.dylib
44 |
45 | # Executables
46 | *.exe
47 | *.out
48 | *.app
49 | *.i*86
50 | *.x86_64
51 | *.hex
52 |
53 | # Debug files
54 | *.dSYM/
55 | *.su
56 | *.idb
57 | *.pdb
58 |
59 | # Kernel Module Compile Results
60 | *.mod*
61 | *.cmd
62 | .tmp_versions/
63 | modules.order
64 | Module.symvers
65 | Mkfile.old
66 | dkms.conf
67 |
68 |
69 | #-------------------------------------
70 | # EAGLE CAD project files
71 | #-------------------------------------
72 | eagle.epf
73 |
74 | # Autorouter files
75 | *.pro
76 | *.job
77 |
78 | # CAM files
79 | *.$$$
80 | *.cmp
81 | *.ly2
82 | *.l15
83 | *.sol
84 | *.plc
85 | *.stc
86 | *.sts
87 | *.crc
88 | *.crs
89 |
90 | *.dri
91 | *.drl
92 | *.gpi
93 | *.pls
94 | *.ger
95 | *.xln
96 |
97 | *.drd
98 | *.drd.*
99 |
100 | *.s#*
101 | *.b#*
102 |
103 | *.info
104 |
105 | *.eps
106 |
107 | # file locks introduced since 7.x
108 | *.lck
109 |
110 |
--------------------------------------------------------------------------------
/DiyLC/FlipFlop.diy:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 | 3
5 | 0
6 | 0
7 |
8 | New Project
9 | mats
10 |
11 | 9.0
12 | cm
13 |
14 |
15 | 6.0
16 | cm
17 |
18 |
19 | 0.1
20 | in
21 |
22 |
23 |
24 | Board1
25 | 127
26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 | 248
35 | 235
36 | 179
37 | 255
38 |
39 |
40 | 173
41 | 164
42 | 125
43 | 255
44 |
45 |
46 | 182
47 | 182
48 | 182
49 | 255
50 |
51 | true
52 |
53 | 0.1
54 | in
55 |
56 |
57 | 218
58 | 138
59 | 103
60 | 255
61 |
62 |
63 |
64 | Trace86
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66 |
67 |
68 |
69 |
70 |
71 | 255
72 | 255
73 | 255
74 | 255
75 |
76 |
77 | 0
78 | 0
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90 | _1
91 |
92 |
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94 | 127
95 |
96 |
97 |
98 |
99 |
100 | 255
101 | 255
102 | 255
103 | 255
104 |
105 |
106 | 0
107 | 0
108 | 0
109 | 255
110 |
111 |
112 |
113 | NAME
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119 | _1
120 |
121 |
122 | Trace2
123 | 127
124 |
125 |
126 |
127 |
128 |
129 | 255
130 | 255
131 | 255
132 | 255
133 |
134 |
135 | 0
136 | 0
137 | 0
138 | 255
139 |
140 |
141 |
142 | NAME
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144 |
145 | 1.0
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148 | _1
149 |
150 |
151 | Trace3
152 | 127
153 |
154 |
155 |
156 |
157 |
158 |
159 |
160 |
161 | NAME
162 | false
163 |
164 | _1
165 |
166 |
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168 | 127
169 |
170 |
171 |
172 |
173 |
174 |
175 |
176 |
177 | NAME
178 | false
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180 | _1
181 |
182 |
183 | Trace10
184 | 127
185 |
186 |
187 |
188 |
189 |
190 |
191 |
192 |
193 | NAME
194 | false
195 |
196 | _1
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198 |
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200 | 127
201 |
202 |
203 |
204 |
205 |
206 |
207 |
208 |
209 | NAME
210 | false
211 |
212 | _1
213 |
214 |
215 | Trace13
216 | 127
217 |
218 |
219 |
220 |
221 |
222 |
223 |
224 |
225 | NAME
226 | false
227 |
228 | _1
229 |
230 |
231 | Trace19
232 | 127
233 |
234 |
235 |
236 |
237 |
238 |
239 |
240 |
241 | NAME
242 | false
243 |
244 | _1
245 |
246 |
247 | Trace20
248 | 127
249 |
250 |
251 |
252 |
253 |
254 |
255 |
256 |
257 | NAME
258 | false
259 |
260 | _1
261 |
262 |
263 | Trace11
264 | 127
265 |
266 |
267 |
268 |
269 |
270 |
271 |
272 |
273 | NAME
274 | false
275 |
276 | _1
277 |
278 |
279 | Trace14
280 | 127
281 |
282 |
283 |
284 |
285 |
286 |
287 |
288 |
289 | NAME
290 | false
291 |
292 | _1
293 |
294 |
295 | Trace15
296 | 127
297 |
298 |
299 |
300 |
301 |
302 |
303 |
304 |
305 | NAME
306 | false
307 |
308 | _1
309 |
310 |
311 | Trace16
312 | 127
313 |
314 |
315 |
316 |
317 |
318 |
319 |
320 |
321 | NAME
322 | false
323 |
324 | _1
325 |
326 |
327 | Trace17
328 | 127
329 |
330 |
331 |
332 |
333 |
334 |
335 |
336 |
337 | NAME
338 | false
339 |
340 | _1
341 |
342 |
343 | Trace18
344 | 127
345 |
346 |
347 |
348 |
349 |
350 |
351 |
352 |
353 | NAME
354 | false
355 |
356 | _1
357 |
358 |
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360 | 127
361 |
362 |
363 |
364 |
365 |
366 |
367 |
368 |
369 | NAME
370 | false
371 |
372 | _1
373 |
374 |
375 | Trace23
376 | 127
377 |
378 |
379 |
380 |
381 |
382 |
383 |
384 |
385 | NAME
386 | false
387 |
388 | _1
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390 |
391 | Trace24
392 | 127
393 |
394 |
395 |
396 |
397 |
398 |
399 |
400 |
401 | NAME
402 | false
403 |
404 | _1
405 |
406 |
407 | Trace25
408 | 127
409 |
410 |
411 |
412 |
413 |
414 |
415 |
416 |
417 | NAME
418 | false
419 |
420 | _1
421 |
422 |
423 | Trace26
424 | 127
425 |
426 |
427 |
428 |
429 |
430 |
431 |
432 |
433 | NAME
434 | false
435 |
436 | _1
437 |
438 |
439 | Trace6
440 | 127
441 |
442 |
443 |
444 |
445 |
446 |
447 |
448 |
449 | NAME
450 | false
451 |
452 | _1
453 |
454 |
455 | Trace8
456 | 127
457 |
458 |
459 |
460 |
461 |
462 |
463 |
464 |
465 | NAME
466 | false
467 |
468 | _1
469 |
470 |
471 | Trace27
472 | 127
473 |
474 |
475 |
476 |
477 |
478 |
479 |
480 |
481 | NAME
482 | false
483 |
484 | _1
485 |
486 |
487 | Trace1
488 | 127
489 |
490 |
491 |
492 |
493 |
494 |
495 |
496 |
497 | NAME
498 | false
499 |
500 | _1
501 |
502 |
503 | Trace4
504 | 127
505 |
506 |
507 |
508 |
509 |
510 |
511 |
512 |
513 | NAME
514 | false
515 |
516 | _1
517 |
518 |
519 | Trace5
520 | 127
521 |
522 |
523 |
524 |
525 |
526 |
527 |
528 |
529 | NAME
530 | false
531 |
532 | _1
533 |
534 |
535 | Trace7
536 | 127
537 |
538 |
539 |
540 |
541 |
542 |
543 |
544 |
545 | NAME
546 | false
547 |
548 | _1
549 |
550 |
551 | Trace22
552 | 127
553 |
554 |
555 |
556 |
557 |
558 |
559 |
560 |
561 | NAME
562 | false
563 |
564 | _1
565 |
566 |
567 | Trace28
568 | 127
569 |
570 |
571 |
572 |
573 |
574 |
575 |
576 |
577 | NAME
578 | false
579 |
580 | _1
581 |
582 |
583 | Trace29
584 | 127
585 |
586 |
587 |
588 |
589 |
590 |
591 |
592 |
593 | NAME
594 | false
595 |
596 | _1
597 |
598 |
599 | Trace30
600 | 127
601 |
602 |
603 |
604 |
605 |
606 |
607 |
608 |
609 | NAME
610 | false
611 |
612 | _1
613 |
614 |
615 | Trace31
616 | 127
617 |
618 |
619 |
620 |
621 |
622 |
623 |
624 |
625 | NAME
626 | false
627 |
628 | _1
629 |
630 |
631 | Trace32
632 | 127
633 |
634 |
635 |
636 |
637 |
638 |
639 |
640 |
641 | NAME
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646 |
647 | Eyelet1
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649 | 0.12
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652 |
653 | 0.05
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656 |
657 | 195
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661 |
662 |
663 |
664 |
665 |
666 | Eyelet1
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668 | 0.12
669 | in
670 |
671 |
672 | 0.05
673 | in
674 |
675 |
676 | 195
677 | 228
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680 |
681 |
682 |
683 |
684 |
685 | Eyelet1
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687 | 0.12
688 | in
689 |
690 |
691 | 0.05
692 | in
693 |
694 |
695 | 195
696 | 228
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699 |
700 |
701 |
702 |
703 |
704 | Eyelet1
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706 | 0.12
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709 |
710 | 0.05
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713 |
714 | 195
715 | 228
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719 |
720 |
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722 |
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728 |
729 | 0.05
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732 |
733 | 195
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739 |
740 |
741 |
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747 |
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749 | in
750 |
751 |
752 | 195
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756 |
757 |
758 |
759 |
760 |
761 | Eyelet1
762 |
763 | 0.12
764 | in
765 |
766 |
767 | 0.05
768 | in
769 |
770 |
771 | 195
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773 | 237
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776 |
777 |
778 |
779 |
780 | Eyelet1
781 |
782 | 0.12
783 | in
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785 |
786 | 0.05
787 | in
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789 |
790 | 195
791 | 228
792 | 237
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795 |
796 |
797 |
798 |
799 | W1
800 | 127
801 |
802 |
803 |
804 |
805 |
806 |
807 |
808 | 0
809 | 255
810 | 0
811 | 255
812 |
813 | FOUR
814 | _22
815 |
816 |
817 | W2
818 | 127
819 |
820 |
821 |
822 |
823 |
824 |
825 |
826 | 0
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828 | 0
829 | 255
830 |
831 | FOUR
832 | _22
833 |
834 |
835 | W2
836 | 127
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838 |
839 |
840 |
841 |
842 |
843 |
844 | 0
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848 |
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851 |
852 |
853 | Q2
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856 | DEFAULT
857 |
858 |
859 |
860 |
861 |
862 |
863 | 128
864 | 128
865 | 128
866 | 255
867 |
868 |
869 | 89
870 | 89
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872 | 255
873 |
874 |
875 | 255
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879 |
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883 | 0.1
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886 |
887 |
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894 |
895 | 0.1
896 | in
897 |
898 |
899 |
900 |
901 |
902 |
903 | 130
904 | 207
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907 |
908 |
909 | 91
910 | 144
911 | 177
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914 |
915 | 0
916 | 0
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919 |
920 |
921 | 204
922 | 204
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924 | 255
925 |
926 | NAME
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930 | Standard
931 |
932 |
933 | W1
934 | 127
935 |
936 |
937 |
938 |
939 |
940 |
941 |
942 | 0
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947 | FOUR
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950 |
951 | Q1
952 | 68
953 |
954 | DEFAULT
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956 |
957 |
958 |
959 |
960 |
961 | 128
962 | 128
963 | 128
964 | 255
965 |
966 |
967 | 89
968 | 89
969 | 89
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971 |
972 |
973 | 255
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977 |
978 | NAME
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981 | 0.1
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984 |
985 |
986 | C1
987 | 127
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992 |
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996 |
997 |
998 |
999 |
1000 |
1001 | 240
1002 | 230
1003 | 140
1004 | 255
1005 |
1006 |
1007 | 168
1008 | 161
1009 | 98
1010 | 255
1011 |
1012 |
1013 |
1014 | 204
1015 | 204
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1018 |
1019 | NAME
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1021 |
1022 | 0.1
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1026 |
1027 |
1028 | C2
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1031 | 0.25
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1034 |
1035 | 0.125
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1037 |
1038 |
1039 |
1040 |
1041 |
1042 |
1043 | 240
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1047 |
1048 |
1049 | 168
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1052 | 255
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1054 |
1055 | 0
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1060 |
1061 | 204
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1066 | NAME
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1072 | _63V
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1074 |
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1078 | 0.3
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1081 |
1082 | 0.1
1083 | in
1084 |
1085 |
1086 |
1087 |
1088 |
1089 |
1090 | 130
1091 | 207
1092 | 253
1093 | 255
1094 |
1095 |
1096 | 91
1097 | 144
1098 | 177
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1100 |
1101 |
1102 | 0
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1104 | 0
1105 | 255
1106 |
1107 |
1108 | 204
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1112 |
1113 | NAME
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1115 | HALF
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1119 |
1120 | R5
1121 | 76
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1123 | 0.3
1124 | in
1125 |
1126 |
1127 | 0.1
1128 | in
1129 |
1130 |
1131 |
1132 |
1133 |
1134 |
1135 | 130
1136 | 207
1137 | 253
1138 | 255
1139 |
1140 |
1141 | 91
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1146 |
1147 | 0
1148 | 0
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1152 |
1153 | 204
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1158 | NAME
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1165 | R2
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1170 |
1171 |
1172 | 0.1
1173 | in
1174 |
1175 |
1176 |
1177 |
1178 |
1179 |
1180 | 130
1181 | 207
1182 | 253
1183 | 255
1184 |
1185 |
1186 | 91
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1188 | 177
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1190 |
1191 |
1192 | 0
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1197 |
1198 | 204
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1205 | HALF
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1213 | 0.3
1214 | in
1215 |
1216 |
1217 | 0.1
1218 | in
1219 |
1220 |
1221 |
1222 |
1223 |
1224 |
1225 | 130
1226 | 207
1227 | 253
1228 | 255
1229 |
1230 |
1231 | 91
1232 | 144
1233 | 177
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1235 |
1236 |
1237 | 0
1238 | 0
1239 | 0
1240 | 255
1241 |
1242 |
1243 | 204
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1247 |
1248 | NAME
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1250 | HALF
1251 | _5_BAND
1252 | Standard
1253 |
1254 |
1255 | R7
1256 | 76
1257 |
1258 | 0.3
1259 | in
1260 |
1261 |
1262 | 0.1
1263 | in
1264 |
1265 |
1266 |
1267 |
1268 |
1269 |
1270 | 130
1271 | 207
1272 | 253
1273 | 255
1274 |
1275 |
1276 | 91
1277 | 144
1278 | 177
1279 | 255
1280 |
1281 |
1282 | 0
1283 | 0
1284 | 0
1285 | 255
1286 |
1287 |
1288 | 204
1289 | 204
1290 | 204
1291 | 255
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1293 | NAME
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1295 | HALF
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1297 | Standard
1298 |
1299 |
1300 | R3
1301 | 76
1302 |
1303 | 0.3
1304 | in
1305 |
1306 |
1307 | 0.1
1308 | in
1309 |
1310 |
1311 |
1312 |
1313 |
1314 |
1315 | 130
1316 | 207
1317 | 253
1318 | 255
1319 |
1320 |
1321 | 91
1322 | 144
1323 | 177
1324 | 255
1325 |
1326 |
1327 | 0
1328 | 0
1329 | 0
1330 | 255
1331 |
1332 |
1333 | 204
1334 | 204
1335 | 204
1336 | 255
1337 |
1338 | NAME
1339 | false
1340 | HALF
1341 | _5_BAND
1342 | Standard
1343 |
1344 |
1345 | Q10
1346 | 68
1347 |
1348 | DEFAULT
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1350 |
1351 |
1352 |
1353 |
1354 |
1355 | 128
1356 | 128
1357 | 128
1358 | 255
1359 |
1360 |
1361 | 89
1362 | 89
1363 | 89
1364 | 255
1365 |
1366 |
1367 | 255
1368 | 255
1369 | 255
1370 | 255
1371 |
1372 | NAME
1373 | false
1374 |
1375 | 0.1
1376 | in
1377 |
1378 |
1379 |
1380 | J1
1381 | 127
1382 |
1383 |
1384 |
1385 |
1386 |
1387 |
1388 |
1389 |
1390 | 0
1391 | 0
1392 | 255
1393 | 255
1394 |
1395 | NAME
1396 | false
1397 |
1398 |
1399 | D1
1400 | 127
1401 |
1402 | 0.2
1403 | in
1404 |
1405 |
1406 | 0.09
1407 | in
1408 |
1409 |
1410 |
1411 |
1412 |
1413 |
1414 | 225
1415 | 240
1416 | 255
1417 | 255
1418 |
1419 |
1420 | 128
1421 | 128
1422 | 128
1423 | 255
1424 |
1425 |
1426 | 255
1427 | 255
1428 | 255
1429 | 255
1430 |
1431 |
1432 | 204
1433 | 204
1434 | 204
1435 | 255
1436 |
1437 | NAME
1438 | false
1439 |
1440 |
1441 |
1442 | 230
1443 | 110
1444 | 49
1445 | 255
1446 |
1447 |
1448 |
1449 | D2
1450 | 127
1451 |
1452 | 0.2
1453 | in
1454 |
1455 |
1456 | 0.09
1457 | in
1458 |
1459 |
1460 |
1461 |
1462 |
1463 |
1464 | 225
1465 | 240
1466 | 255
1467 | 255
1468 |
1469 |
1470 | 128
1471 | 128
1472 | 128
1473 | 255
1474 |
1475 |
1476 | 255
1477 | 255
1478 | 255
1479 | 255
1480 |
1481 |
1482 | 204
1483 | 204
1484 | 204
1485 | 255
1486 |
1487 | NAME
1488 | false
1489 |
1490 |
1491 |
1492 | 230
1493 | 110
1494 | 49
1495 | 255
1496 |
1497 |
1498 |
1499 | R8
1500 | 76
1501 |
1502 | 0.3
1503 | in
1504 |
1505 |
1506 | 0.1
1507 | in
1508 |
1509 |
1510 |
1511 |
1512 |
1513 |
1514 | 130
1515 | 207
1516 | 253
1517 | 255
1518 |
1519 |
1520 | 91
1521 | 144
1522 | 177
1523 | 255
1524 |
1525 |
1526 | 0
1527 | 0
1528 | 0
1529 | 255
1530 |
1531 |
1532 | 204
1533 | 204
1534 | 204
1535 | 255
1536 |
1537 | NAME
1538 | false
1539 | HALF
1540 | _5_BAND
1541 | Standard
1542 |
1543 |
1544 | W2
1545 | 127
1546 |
1547 |
1548 |
1549 |
1550 |
1551 |
1552 |
1553 | 0
1554 | 255
1555 | 0
1556 | 255
1557 |
1558 | FOUR
1559 | _22
1560 |
1561 |
1562 | W2
1563 | 127
1564 |
1565 |
1566 |
1567 |
1568 |
1569 |
1570 |
1571 | 0
1572 | 255
1573 | 0
1574 | 255
1575 |
1576 | FOUR
1577 | _22
1578 |
1579 |
1580 | W1
1581 | 127
1582 |
1583 |
1584 |
1585 |
1586 |
1587 |
1588 |
1589 | 0
1590 | 255
1591 | 0
1592 | 255
1593 |
1594 | FOUR
1595 | _22
1596 |
1597 |
1598 | W1
1599 | 127
1600 |
1601 |
1602 |
1603 |
1604 |
1605 |
1606 |
1607 | 0
1608 | 255
1609 | 0
1610 | 255
1611 |
1612 | FOUR
1613 | _22
1614 |
1615 |
1616 | L1
1617 |
1618 | VCC
1619 |
1620 |
1621 |
1622 | width
1623 |
1624 |
1625 |
1626 | superscript
1627 |
1628 |
1629 |
1630 | transform
1631 |
1632 |
1633 |
1634 | posture
1635 |
1636 |
1637 |
1638 | tracking
1639 |
1640 |
1641 |
1642 | size
1643 | 14.0
1644 |
1645 |
1646 | family
1647 | Tahoma
1648 |
1649 |
1650 | weight
1651 |
1652 |
1653 |
1654 |
1655 |
1656 | false
1657 | CENTER
1658 | CENTER
1659 | DEFAULT
1660 |
1661 |
1662 | L4
1663 |
1664 | GND
1665 |
1666 |
1667 | false
1668 | CENTER
1669 | CENTER
1670 | DEFAULT
1671 |
1672 |
1673 | L1
1674 |
1675 | VCC
1676 |
1677 |
1678 |
1679 | width
1680 |
1681 |
1682 |
1683 | superscript
1684 |
1685 |
1686 |
1687 | transform
1688 |
1689 |
1690 |
1691 | posture
1692 |
1693 |
1694 |
1695 | tracking
1696 |
1697 |
1698 |
1699 | size
1700 | 14.0
1701 |
1702 |
1703 | family
1704 | Tahoma
1705 |
1706 |
1707 | weight
1708 |
1709 |
1710 |
1711 |
1712 |
1713 | 0
1714 | 0
1715 | 0
1716 | 255
1717 |
1718 | false
1719 | CENTER
1720 | CENTER
1721 | DEFAULT
1722 |
1723 |
1724 | L4
1725 |
1726 | GND
1727 |
1728 |
1729 |
1730 | width
1731 |
1732 |
1733 |
1734 | superscript
1735 |
1736 |
1737 |
1738 | transform
1739 |
1740 |
1741 |
1742 | posture
1743 |
1744 |
1745 |
1746 | tracking
1747 |
1748 |
1749 |
1750 | size
1751 | 14.0
1752 |
1753 |
1754 | family
1755 | Tahoma
1756 |
1757 |
1758 | weight
1759 |
1760 |
1761 |
1762 |
1763 |
1764 | 0
1765 | 0
1766 | 0
1767 | 255
1768 |
1769 | false
1770 | CENTER
1771 | CENTER
1772 | DEFAULT
1773 |
1774 |
1775 | L1
1776 |
1777 | R
1778 |
1779 |
1780 |
1781 | width
1782 |
1783 |
1784 |
1785 | superscript
1786 |
1787 |
1788 |
1789 | transform
1790 |
1791 |
1792 |
1793 | posture
1794 |
1795 |
1796 |
1797 | tracking
1798 |
1799 |
1800 |
1801 | size
1802 | 14.0
1803 |
1804 |
1805 | family
1806 | Tahoma
1807 |
1808 |
1809 | weight
1810 |
1811 |
1812 |
1813 |
1814 |
1815 | 0
1816 | 0
1817 | 0
1818 | 255
1819 |
1820 | false
1821 | CENTER
1822 | CENTER
1823 | DEFAULT
1824 |
1825 |
1826 | L1
1827 |
1828 | S
1829 |
1830 |
1831 |
1832 | width
1833 |
1834 |
1835 |
1836 | superscript
1837 |
1838 |
1839 |
1840 | transform
1841 |
1842 |
1843 |
1844 | posture
1845 |
1846 |
1847 |
1848 | tracking
1849 |
1850 |
1851 |
1852 | size
1853 | 14.0
1854 |
1855 |
1856 | family
1857 | Tahoma
1858 |
1859 |
1860 | weight
1861 |
1862 |
1863 |
1864 |
1865 |
1866 | 0
1867 | 0
1868 | 0
1869 | 255
1870 |
1871 | false
1872 | CENTER
1873 | CENTER
1874 | DEFAULT
1875 |
1876 |
1877 | L1
1878 |
1879 | /Q
1880 |
1881 |
1882 |
1883 | width
1884 |
1885 |
1886 |
1887 | superscript
1888 |
1889 |
1890 |
1891 | transform
1892 |
1893 |
1894 |
1895 | posture
1896 |
1897 |
1898 |
1899 | tracking
1900 |
1901 |
1902 |
1903 | size
1904 | 14.0
1905 |
1906 |
1907 | family
1908 | Tahoma
1909 |
1910 |
1911 | weight
1912 |
1913 |
1914 |
1915 |
1916 |
1917 | 0
1918 | 0
1919 | 0
1920 | 255
1921 |
1922 | false
1923 | CENTER
1924 | CENTER
1925 | DEFAULT
1926 |
1927 |
1928 | L1
1929 |
1930 | Q
1931 |
1932 |
1933 |
1934 | width
1935 |
1936 |
1937 |
1938 | superscript
1939 |
1940 |
1941 |
1942 | transform
1943 |
1944 |
1945 |
1946 | posture
1947 |
1948 |
1949 |
1950 | tracking
1951 |
1952 |
1953 |
1954 | size
1955 | 14.0
1956 |
1957 |
1958 | family
1959 | Tahoma
1960 |
1961 |
1962 | weight
1963 |
1964 |
1965 |
1966 |
1967 |
1968 | 0
1969 | 0
1970 | 0
1971 | 255
1972 |
1973 | false
1974 | CENTER
1975 | CENTER
1976 | DEFAULT
1977 |
1978 |
1979 |
1980 |
1981 | 2
1982 |
1983 |
1984 |
1985 |
1986 |
1987 | width
1988 |
1989 |
1990 |
1991 | superscript
1992 |
1993 |
1994 |
1995 | transform
1996 |
1997 |
1998 |
1999 | posture
2000 |
2001 |
2002 |
2003 | tracking
2004 |
2005 |
2006 |
2007 | size
2008 | 14.0
2009 |
2010 |
2011 | family
2012 | Tahoma
2013 |
2014 |
2015 | weight
2016 |
2017 |
2018 |
2019 |
2020 |
--------------------------------------------------------------------------------
/DiyLC/Startpulse.diy:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 | 3
5 | 0
6 | 0
7 |
8 | New Project
9 | mats
10 |
11 | 9.0
12 | cm
13 |
14 |
15 | 6.0
16 | cm
17 |
18 |
19 | 0.1
20 | in
21 |
22 |
23 |
24 | Board1
25 | 127
26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 | 248
35 | 235
36 | 179
37 | 255
38 |
39 |
40 | 173
41 | 164
42 | 125
43 | 255
44 |
45 |
46 | 182
47 | 182
48 | 182
49 | 255
50 |
51 | true
52 |
53 | 0.1
54 | in
55 |
56 |
57 | 218
58 | 138
59 | 103
60 | 255
61 |
62 |
63 |
64 | Trace86
65 | 127
66 |
67 |
68 |
69 |
70 |
71 | 255
72 | 255
73 | 255
74 | 255
75 |
76 |
77 | 0
78 | 0
79 | 0
80 | 255
81 |
82 |
83 |
84 | NAME
85 | false
86 |
87 | 1.0
88 | mm
89 |
90 | _1
91 |
92 |
93 | Trace86
94 | 127
95 |
96 |
97 |
98 |
99 |
100 | 255
101 | 255
102 | 255
103 | 255
104 |
105 |
106 | 0
107 | 0
108 | 0
109 | 255
110 |
111 |
112 |
113 | NAME
114 | false
115 |
116 | 1.0
117 | mm
118 |
119 | _1
120 |
121 |
122 | Trace1
123 | 127
124 |
125 |
126 |
127 |
128 |
129 | 255
130 | 255
131 | 255
132 | 255
133 |
134 |
135 | 0
136 | 0
137 | 0
138 | 255
139 |
140 |
141 |
142 | NAME
143 | false
144 |
145 | 1.0
146 | mm
147 |
148 | _1
149 |
150 |
151 | Trace5
152 | 127
153 |
154 |
155 |
156 |
157 |
158 |
159 |
160 |
161 | NAME
162 | false
163 |
164 | _1
165 |
166 |
167 | Trace6
168 | 127
169 |
170 |
171 |
172 |
173 |
174 |
175 |
176 |
177 | NAME
178 | false
179 |
180 | _1
181 |
182 |
183 | Trace7
184 | 127
185 |
186 |
187 |
188 |
189 |
190 |
191 |
192 |
193 | NAME
194 | false
195 |
196 | _1
197 |
198 |
199 | Trace8
200 | 127
201 |
202 |
203 |
204 |
205 |
206 |
207 |
208 |
209 | NAME
210 | false
211 |
212 | _1
213 |
214 |
215 | Trace9
216 | 127
217 |
218 |
219 |
220 |
221 |
222 |
223 |
224 |
225 | NAME
226 | false
227 |
228 | _1
229 |
230 |
231 | Trace10
232 | 127
233 |
234 |
235 |
236 |
237 |
238 |
239 |
240 |
241 | NAME
242 | false
243 |
244 | _1
245 |
246 |
247 | Trace11
248 | 127
249 |
250 |
251 |
252 |
253 |
254 |
255 |
256 |
257 | NAME
258 | false
259 |
260 | _1
261 |
262 |
263 | Trace12
264 | 127
265 |
266 |
267 |
268 |
269 |
270 |
271 |
272 |
273 | NAME
274 | false
275 |
276 | _1
277 |
278 |
279 | Trace13
280 | 127
281 |
282 |
283 |
284 |
285 |
286 |
287 |
288 |
289 | NAME
290 | false
291 |
292 | _1
293 |
294 |
295 | Trace2
296 | 127
297 |
298 |
299 |
300 |
301 |
302 |
303 |
304 |
305 | NAME
306 | false
307 |
308 | _1
309 |
310 |
311 | Trace3
312 | 127
313 |
314 |
315 |
316 |
317 |
318 |
319 |
320 |
321 | NAME
322 | false
323 |
324 | _1
325 |
326 |
327 | Trace4
328 | 127
329 |
330 |
331 |
332 |
333 |
334 |
335 |
336 |
337 | NAME
338 | false
339 |
340 | _1
341 |
342 |
343 | Trace14
344 | 127
345 |
346 |
347 |
348 |
349 |
350 |
351 |
352 |
353 | NAME
354 | false
355 |
356 | _1
357 |
358 |
359 | Trace15
360 | 127
361 |
362 |
363 |
364 |
365 |
366 |
367 |
368 |
369 | NAME
370 | false
371 |
372 | _1
373 |
374 |
375 | Trace16
376 | 127
377 |
378 |
379 |
380 |
381 |
382 |
383 |
384 |
385 | NAME
386 | false
387 |
388 | _1
389 |
390 |
391 | Trace17
392 | 127
393 |
394 |
395 |
396 |
397 |
398 |
399 |
400 |
401 | NAME
402 | false
403 |
404 | _1
405 |
406 |
407 | Trace18
408 | 127
409 |
410 |
411 |
412 |
413 |
414 |
415 |
416 |
417 | NAME
418 | false
419 |
420 | _1
421 |
422 |
423 | Trace22
424 | 127
425 |
426 |
427 |
428 |
429 |
430 |
431 |
432 |
433 | NAME
434 | false
435 |
436 | _1
437 |
438 |
439 | Trace23
440 | 127
441 |
442 |
443 |
444 |
445 |
446 |
447 |
448 |
449 | NAME
450 | false
451 |
452 | _1
453 |
454 |
455 | Trace24
456 | 127
457 |
458 |
459 |
460 |
461 |
462 |
463 |
464 |
465 | NAME
466 | false
467 |
468 | _1
469 |
470 |
471 | Trace21
472 | 127
473 |
474 |
475 |
476 |
477 |
478 |
479 |
480 |
481 | NAME
482 | false
483 |
484 | _1
485 |
486 |
487 | Trace25
488 | 127
489 |
490 |
491 |
492 |
493 |
494 |
495 |
496 |
497 | NAME
498 | false
499 |
500 | _1
501 |
502 |
503 | Trace26
504 | 127
505 |
506 |
507 |
508 |
509 |
510 |
511 |
512 |
513 | NAME
514 | false
515 |
516 | _1
517 |
518 |
519 | Trace27
520 | 127
521 |
522 |
523 |
524 |
525 |
526 |
527 |
528 |
529 | NAME
530 | false
531 |
532 | _1
533 |
534 |
535 | Trace28
536 | 127
537 |
538 |
539 |
540 |
541 |
542 |
543 |
544 |
545 | NAME
546 | false
547 |
548 | _1
549 |
550 |
551 | Trace19
552 | 127
553 |
554 |
555 |
556 |
557 |
558 |
559 |
560 |
561 | NAME
562 | false
563 |
564 | _1
565 |
566 |
567 | Trace20
568 | 127
569 |
570 |
571 |
572 |
573 |
574 |
575 |
576 |
577 | NAME
578 | false
579 |
580 | _1
581 |
582 |
583 | Trace29
584 | 127
585 |
586 |
587 |
588 |
589 |
590 |
591 |
592 |
593 | NAME
594 | false
595 |
596 | _1
597 |
598 |
599 | Trace30
600 | 127
601 |
602 |
603 |
604 |
605 |
606 |
607 |
608 |
609 | NAME
610 | false
611 |
612 | _1
613 |
614 |
615 | Trace31
616 | 127
617 |
618 |
619 |
620 |
621 |
622 |
623 |
624 |
625 | NAME
626 | false
627 |
628 | _1
629 |
630 |
631 | Trace32
632 | 127
633 |
634 |
635 |
636 |
637 |
638 |
639 |
640 |
641 | NAME
642 | false
643 |
644 | _1
645 |
646 |
647 | Trace33
648 | 127
649 |
650 |
651 |
652 |
653 |
654 |
655 |
656 |
657 | NAME
658 | false
659 |
660 | _1
661 |
662 |
663 | Trace34
664 | 127
665 |
666 |
667 |
668 |
669 |
670 |
671 |
672 |
673 | NAME
674 | false
675 |
676 | _1
677 |
678 |
679 | Trace35
680 | 127
681 |
682 |
683 |
684 |
685 |
686 |
687 |
688 |
689 | NAME
690 | false
691 |
692 | _1
693 |
694 |
695 | Trace36
696 | 127
697 |
698 |
699 |
700 |
701 |
702 |
703 |
704 |
705 | NAME
706 | false
707 |
708 | _1
709 |
710 |
711 | Trace37
712 | 127
713 |
714 |
715 |
716 |
717 |
718 |
719 |
720 |
721 | NAME
722 | false
723 |
724 | _1
725 |
726 |
727 | Trace38
728 | 127
729 |
730 |
731 |
732 |
733 |
734 |
735 |
736 |
737 | NAME
738 | false
739 |
740 | _1
741 |
742 |
743 | Trace39
744 | 127
745 |
746 |
747 |
748 |
749 |
750 |
751 |
752 |
753 | NAME
754 | false
755 |
756 | _1
757 |
758 |
759 | Trace40
760 | 127
761 |
762 |
763 |
764 |
765 |
766 |
767 |
768 |
769 | NAME
770 | false
771 |
772 | _1
773 |
774 |
775 | Trace41
776 | 127
777 |
778 |
779 |
780 |
781 |
782 |
783 |
784 |
785 | NAME
786 | false
787 |
788 | _1
789 |
790 |
791 | Trace42
792 | 127
793 |
794 |
795 |
796 |
797 |
798 |
799 |
800 |
801 | NAME
802 | false
803 |
804 | _1
805 |
806 |
807 | Trace43
808 | 127
809 |
810 |
811 |
812 |
813 |
814 |
815 |
816 |
817 | NAME
818 | false
819 |
820 | _1
821 |
822 |
823 | Trace44
824 | 127
825 |
826 |
827 |
828 |
829 |
830 |
831 |
832 |
833 | NAME
834 | false
835 |
836 | _1
837 |
838 |
839 | Trace45
840 | 127
841 |
842 |
843 |
844 |
845 |
846 |
847 |
848 |
849 | NAME
850 | false
851 |
852 | _1
853 |
854 |
855 | Trace46
856 | 127
857 |
858 |
859 |
860 |
861 |
862 |
863 |
864 |
865 | NAME
866 | false
867 |
868 | _1
869 |
870 |
871 | Trace47
872 | 127
873 |
874 |
875 |
876 |
877 |
878 |
879 |
880 |
881 | NAME
882 | false
883 |
884 | _1
885 |
886 |
887 | Trace48
888 | 127
889 |
890 |
891 |
892 |
893 |
894 |
895 |
896 |
897 | NAME
898 | false
899 |
900 | _1
901 |
902 |
903 | Trace49
904 | 127
905 |
906 |
907 |
908 |
909 |
910 |
911 |
912 |
913 | NAME
914 | false
915 |
916 | _1
917 |
918 |
919 | Trace50
920 | 127
921 |
922 |
923 |
924 |
925 |
926 |
927 |
928 |
929 | NAME
930 | false
931 |
932 | _1
933 |
934 |
935 | Trace51
936 | 127
937 |
938 |
939 |
940 |
941 |
942 |
943 |
944 |
945 | NAME
946 | false
947 |
948 | _1
949 |
950 |
951 | Trace52
952 | 127
953 |
954 |
955 |
956 |
957 |
958 |
959 |
960 |
961 | NAME
962 | false
963 |
964 | _1
965 |
966 |
967 | Eyelet1
968 |
969 | 0.12
970 | in
971 |
972 |
973 | 0.05
974 | in
975 |
976 |
977 | 195
978 | 228
979 | 237
980 | 255
981 |
982 |
983 |
984 |
985 |
986 | Eyelet1
987 |
988 | 0.12
989 | in
990 |
991 |
992 | 0.05
993 | in
994 |
995 |
996 | 195
997 | 228
998 | 237
999 | 255
1000 |
1001 |
1002 |
1003 |
1004 |
1005 | Eyelet1
1006 |
1007 | 0.12
1008 | in
1009 |
1010 |
1011 | 0.05
1012 | in
1013 |
1014 |
1015 | 195
1016 | 228
1017 | 237
1018 | 255
1019 |
1020 |
1021 |
1022 |
1023 |
1024 | Eyelet1
1025 |
1026 | 0.12
1027 | in
1028 |
1029 |
1030 | 0.05
1031 | in
1032 |
1033 |
1034 | 195
1035 | 228
1036 | 237
1037 | 255
1038 |
1039 |
1040 |
1041 |
1042 |
1043 | Eyelet1
1044 |
1045 | 0.12
1046 | in
1047 |
1048 |
1049 | 0.05
1050 | in
1051 |
1052 |
1053 | 195
1054 | 228
1055 | 237
1056 | 255
1057 |
1058 |
1059 |
1060 |
1061 |
1062 | Eyelet1
1063 |
1064 | 0.12
1065 | in
1066 |
1067 |
1068 | 0.05
1069 | in
1070 |
1071 |
1072 | 195
1073 | 228
1074 | 237
1075 | 255
1076 |
1077 |
1078 |
1079 |
1080 |
1081 | Eyelet1
1082 |
1083 | 0.12
1084 | in
1085 |
1086 |
1087 | 0.05
1088 | in
1089 |
1090 |
1091 | 195
1092 | 228
1093 | 237
1094 | 255
1095 |
1096 |
1097 |
1098 |
1099 |
1100 | Eyelet1
1101 |
1102 | 0.12
1103 | in
1104 |
1105 |
1106 | 0.05
1107 | in
1108 |
1109 |
1110 | 195
1111 | 228
1112 | 237
1113 | 255
1114 |
1115 |
1116 |
1117 |
1118 |
1119 | W1
1120 | 127
1121 |
1122 |
1123 |
1124 |
1125 |
1126 |
1127 |
1128 | 0
1129 | 255
1130 | 0
1131 | 255
1132 |
1133 | FOUR
1134 | _22
1135 |
1136 |
1137 | W2
1138 | 127
1139 |
1140 |
1141 |
1142 |
1143 |
1144 |
1145 |
1146 | 0
1147 | 255
1148 | 0
1149 | 255
1150 |
1151 | FOUR
1152 | _22
1153 |
1154 |
1155 | W2
1156 | 127
1157 |
1158 |
1159 |
1160 |
1161 |
1162 |
1163 |
1164 | 0
1165 | 255
1166 | 0
1167 | 255
1168 |
1169 | FOUR
1170 | _22
1171 |
1172 |
1173 | R8
1174 | 76
1175 |
1176 | 0.3
1177 | in
1178 |
1179 |
1180 | 0.1
1181 | in
1182 |
1183 |
1184 |
1185 |
1186 |
1187 |
1188 | 130
1189 | 207
1190 | 253
1191 | 255
1192 |
1193 |
1194 | 91
1195 | 144
1196 | 177
1197 | 255
1198 |
1199 |
1200 | 0
1201 | 0
1202 | 0
1203 | 255
1204 |
1205 |
1206 | 204
1207 | 204
1208 | 204
1209 | 255
1210 |
1211 | NAME
1212 | false
1213 | HALF
1214 | _5_BAND
1215 | Standard
1216 |
1217 |
1218 | Q10
1219 | 68
1220 |
1221 | _270
1222 |
1223 |
1224 |
1225 |
1226 |
1227 |
1228 | 128
1229 | 128
1230 | 128
1231 | 255
1232 |
1233 |
1234 | 89
1235 | 89
1236 | 89
1237 | 255
1238 |
1239 |
1240 | 255
1241 | 255
1242 | 255
1243 | 255
1244 |
1245 | NAME
1246 | false
1247 |
1248 | 0.1
1249 | in
1250 |
1251 |
1252 |
1253 | R8
1254 | 76
1255 |
1256 | 0.3
1257 | in
1258 |
1259 |
1260 | 0.1
1261 | in
1262 |
1263 |
1264 |
1265 |
1266 |
1267 |
1268 | 130
1269 | 207
1270 | 253
1271 | 255
1272 |
1273 |
1274 | 91
1275 | 144
1276 | 177
1277 | 255
1278 |
1279 |
1280 | 0
1281 | 0
1282 | 0
1283 | 255
1284 |
1285 |
1286 | 204
1287 | 204
1288 | 204
1289 | 255
1290 |
1291 | NAME
1292 | false
1293 | HALF
1294 | _5_BAND
1295 | Standard
1296 |
1297 |
1298 | Q10
1299 | 68
1300 |
1301 | _270
1302 |
1303 |
1304 |
1305 |
1306 |
1307 |
1308 | 128
1309 | 128
1310 | 128
1311 | 255
1312 |
1313 |
1314 | 89
1315 | 89
1316 | 89
1317 | 255
1318 |
1319 |
1320 | 255
1321 | 255
1322 | 255
1323 | 255
1324 |
1325 | NAME
1326 | false
1327 |
1328 | 0.1
1329 | in
1330 |
1331 |
1332 |
1333 | R8
1334 | 76
1335 |
1336 | 0.3
1337 | in
1338 |
1339 |
1340 | 0.1
1341 | in
1342 |
1343 |
1344 |
1345 |
1346 |
1347 |
1348 | 130
1349 | 207
1350 | 253
1351 | 255
1352 |
1353 |
1354 | 91
1355 | 144
1356 | 177
1357 | 255
1358 |
1359 |
1360 | 0
1361 | 0
1362 | 0
1363 | 255
1364 |
1365 |
1366 | 204
1367 | 204
1368 | 204
1369 | 255
1370 |
1371 | NAME
1372 | false
1373 | HALF
1374 | _5_BAND
1375 | Standard
1376 |
1377 |
1378 | Q10
1379 | 68
1380 |
1381 | _180
1382 |
1383 |
1384 |
1385 |
1386 |
1387 |
1388 | 128
1389 | 128
1390 | 128
1391 | 255
1392 |
1393 |
1394 | 89
1395 | 89
1396 | 89
1397 | 255
1398 |
1399 |
1400 | 255
1401 | 255
1402 | 255
1403 | 255
1404 |
1405 | NAME
1406 | false
1407 |
1408 | 0.1
1409 | in
1410 |
1411 |
1412 |
1413 | Q10
1414 | 68
1415 |
1416 | _180
1417 |
1418 |
1419 |
1420 |
1421 |
1422 |
1423 | 128
1424 | 128
1425 | 128
1426 | 255
1427 |
1428 |
1429 | 89
1430 | 89
1431 | 89
1432 | 255
1433 |
1434 |
1435 | 255
1436 | 255
1437 | 255
1438 | 255
1439 |
1440 | NAME
1441 | false
1442 |
1443 | 0.1
1444 | in
1445 |
1446 |
1447 |
1448 | Q10
1449 | 68
1450 |
1451 | _180
1452 |
1453 |
1454 |
1455 |
1456 |
1457 |
1458 | 128
1459 | 128
1460 | 128
1461 | 255
1462 |
1463 |
1464 | 89
1465 | 89
1466 | 89
1467 | 255
1468 |
1469 |
1470 | 255
1471 | 255
1472 | 255
1473 | 255
1474 |
1475 | NAME
1476 | false
1477 |
1478 | 0.1
1479 | in
1480 |
1481 |
1482 |
1483 | C1
1484 | 76
1485 |
1486 | 0.25
1487 | in
1488 |
1489 |
1490 | 0.125
1491 | in
1492 |
1493 |
1494 |
1495 |
1496 |
1497 |
1498 | 240
1499 | 230
1500 | 140
1501 | 255
1502 |
1503 |
1504 | 168
1505 | 161
1506 | 98
1507 | 255
1508 |
1509 |
1510 | 0
1511 | 0
1512 | 0
1513 | 255
1514 |
1515 |
1516 | 204
1517 | 204
1518 | 204
1519 | 255
1520 |
1521 | NAME
1522 | false
1523 |
1524 | 0.1
1525 | in
1526 |
1527 | _63V
1528 |
1529 |
1530 | R8
1531 | 76
1532 |
1533 | 0.3
1534 | in
1535 |
1536 |
1537 | 0.1
1538 | in
1539 |
1540 |
1541 |
1542 |
1543 |
1544 |
1545 | 130
1546 | 207
1547 | 253
1548 | 255
1549 |
1550 |
1551 | 91
1552 | 144
1553 | 177
1554 | 255
1555 |
1556 |
1557 | 0
1558 | 0
1559 | 0
1560 | 255
1561 |
1562 |
1563 | 204
1564 | 204
1565 | 204
1566 | 255
1567 |
1568 | NAME
1569 | false
1570 | HALF
1571 | _5_BAND
1572 | Standard
1573 |
1574 |
1575 | C1
1576 | 76
1577 |
1578 | 0.25
1579 | in
1580 |
1581 |
1582 | 0.125
1583 | in
1584 |
1585 |
1586 |
1587 |
1588 |
1589 |
1590 | 240
1591 | 230
1592 | 140
1593 | 255
1594 |
1595 |
1596 | 168
1597 | 161
1598 | 98
1599 | 255
1600 |
1601 |
1602 | 0
1603 | 0
1604 | 0
1605 | 255
1606 |
1607 |
1608 | 204
1609 | 204
1610 | 204
1611 | 255
1612 |
1613 | NAME
1614 | false
1615 |
1616 | 0.1
1617 | in
1618 |
1619 | _63V
1620 |
1621 |
1622 | R8
1623 | 76
1624 |
1625 | 0.3
1626 | in
1627 |
1628 |
1629 | 0.1
1630 | in
1631 |
1632 |
1633 |
1634 |
1635 |
1636 |
1637 | 130
1638 | 207
1639 | 253
1640 | 255
1641 |
1642 |
1643 | 91
1644 | 144
1645 | 177
1646 | 255
1647 |
1648 |
1649 | 0
1650 | 0
1651 | 0
1652 | 255
1653 |
1654 |
1655 | 204
1656 | 204
1657 | 204
1658 | 255
1659 |
1660 | NAME
1661 | false
1662 | HALF
1663 | _5_BAND
1664 | Standard
1665 |
1666 |
1667 | R8
1668 | 76
1669 |
1670 | 0.3
1671 | in
1672 |
1673 |
1674 | 0.1
1675 | in
1676 |
1677 |
1678 |
1679 |
1680 |
1681 |
1682 | 130
1683 | 207
1684 | 253
1685 | 255
1686 |
1687 |
1688 | 91
1689 | 144
1690 | 177
1691 | 255
1692 |
1693 |
1694 | 0
1695 | 0
1696 | 0
1697 | 255
1698 |
1699 |
1700 | 204
1701 | 204
1702 | 204
1703 | 255
1704 |
1705 | NAME
1706 | false
1707 | HALF
1708 | _5_BAND
1709 | Standard
1710 |
1711 |
1712 | R8
1713 | 76
1714 |
1715 | 0.3
1716 | in
1717 |
1718 |
1719 | 0.1
1720 | in
1721 |
1722 |
1723 |
1724 |
1725 |
1726 |
1727 | 130
1728 | 207
1729 | 253
1730 | 255
1731 |
1732 |
1733 | 91
1734 | 144
1735 | 177
1736 | 255
1737 |
1738 |
1739 | 0
1740 | 0
1741 | 0
1742 | 255
1743 |
1744 |
1745 | 204
1746 | 204
1747 | 204
1748 | 255
1749 |
1750 | NAME
1751 | false
1752 | HALF
1753 | _5_BAND
1754 | Standard
1755 |
1756 |
1757 | R8
1758 | 76
1759 |
1760 | 0.3
1761 | in
1762 |
1763 |
1764 | 0.1
1765 | in
1766 |
1767 |
1768 |
1769 |
1770 |
1771 |
1772 | 130
1773 | 207
1774 | 253
1775 | 255
1776 |
1777 |
1778 | 91
1779 | 144
1780 | 177
1781 | 255
1782 |
1783 |
1784 | 0
1785 | 0
1786 | 0
1787 | 255
1788 |
1789 |
1790 | 204
1791 | 204
1792 | 204
1793 | 255
1794 |
1795 | NAME
1796 | false
1797 | HALF
1798 | _5_BAND
1799 | Standard
1800 |
1801 |
1802 | J1
1803 | 127
1804 |
1805 |
1806 |
1807 |
1808 |
1809 |
1810 |
1811 |
1812 | 0
1813 | 0
1814 | 255
1815 | 255
1816 |
1817 | NAME
1818 | false
1819 |
1820 |
1821 | VR1
1822 | 127
1823 |
1824 |
1825 |
1826 |
1827 |
1828 | DEFAULT
1829 | LIN
1830 |
1831 | 255
1832 | 255
1833 | 224
1834 | 255
1835 |
1836 |
1837 | 142
1838 | 142
1839 | 56
1840 | 255
1841 |
1842 | NAME
1843 | FLAT_SMALL
1844 |
1845 |
1846 | Q10
1847 | 68
1848 |
1849 | _180
1850 |
1851 |
1852 |
1853 |
1854 |
1855 |
1856 | 128
1857 | 128
1858 | 128
1859 | 255
1860 |
1861 |
1862 | 89
1863 | 89
1864 | 89
1865 | 255
1866 |
1867 |
1868 | 255
1869 | 255
1870 | 255
1871 | 255
1872 |
1873 | NAME
1874 | false
1875 |
1876 | 0.1
1877 | in
1878 |
1879 |
1880 |
1881 | R8
1882 | 76
1883 |
1884 | 0.3
1885 | in
1886 |
1887 |
1888 | 0.1
1889 | in
1890 |
1891 |
1892 |
1893 |
1894 |
1895 |
1896 | 130
1897 | 207
1898 | 253
1899 | 255
1900 |
1901 |
1902 | 91
1903 | 144
1904 | 177
1905 | 255
1906 |
1907 |
1908 | 0
1909 | 0
1910 | 0
1911 | 255
1912 |
1913 |
1914 | 204
1915 | 204
1916 | 204
1917 | 255
1918 |
1919 | NAME
1920 | false
1921 | HALF
1922 | _5_BAND
1923 | Standard
1924 |
1925 |
1926 | R8
1927 | 76
1928 |
1929 | 0.3
1930 | in
1931 |
1932 |
1933 | 0.1
1934 | in
1935 |
1936 |
1937 |
1938 |
1939 |
1940 |
1941 | 130
1942 | 207
1943 | 253
1944 | 255
1945 |
1946 |
1947 | 91
1948 | 144
1949 | 177
1950 | 255
1951 |
1952 |
1953 | 0
1954 | 0
1955 | 0
1956 | 255
1957 |
1958 |
1959 | 204
1960 | 204
1961 | 204
1962 | 255
1963 |
1964 | NAME
1965 | false
1966 | HALF
1967 | _5_BAND
1968 | Standard
1969 |
1970 |
1971 | C1
1972 | 76
1973 |
1974 | 0.25
1975 | in
1976 |
1977 |
1978 | 0.125
1979 | in
1980 |
1981 |
1982 |
1983 |
1984 |
1985 |
1986 | 240
1987 | 230
1988 | 140
1989 | 255
1990 |
1991 |
1992 | 168
1993 | 161
1994 | 98
1995 | 255
1996 |
1997 |
1998 | 0
1999 | 0
2000 | 0
2001 | 255
2002 |
2003 |
2004 | 204
2005 | 204
2006 | 204
2007 | 255
2008 |
2009 | NAME
2010 | false
2011 |
2012 | 0.1
2013 | in
2014 |
2015 | _63V
2016 |
2017 |
2018 | R8
2019 | 76
2020 |
2021 | 0.3
2022 | in
2023 |
2024 |
2025 | 0.1
2026 | in
2027 |
2028 |
2029 |
2030 |
2031 |
2032 |
2033 | 130
2034 | 207
2035 | 253
2036 | 255
2037 |
2038 |
2039 | 91
2040 | 144
2041 | 177
2042 | 255
2043 |
2044 |
2045 | 0
2046 | 0
2047 | 0
2048 | 255
2049 |
2050 |
2051 | 204
2052 | 204
2053 | 204
2054 | 255
2055 |
2056 | NAME
2057 | false
2058 | HALF
2059 | _5_BAND
2060 | Standard
2061 |
2062 |
2063 | R8
2064 | 76
2065 |
2066 | 0.3
2067 | in
2068 |
2069 |
2070 | 0.1
2071 | in
2072 |
2073 |
2074 |
2075 |
2076 |
2077 |
2078 | 130
2079 | 207
2080 | 253
2081 | 255
2082 |
2083 |
2084 | 91
2085 | 144
2086 | 177
2087 | 255
2088 |
2089 |
2090 | 0
2091 | 0
2092 | 0
2093 | 255
2094 |
2095 |
2096 | 204
2097 | 204
2098 | 204
2099 | 255
2100 |
2101 | NAME
2102 | false
2103 | HALF
2104 | _5_BAND
2105 | Standard
2106 |
2107 |
2108 | Q10
2109 | 68
2110 |
2111 | _180
2112 |
2113 |
2114 |
2115 |
2116 |
2117 |
2118 | 128
2119 | 128
2120 | 128
2121 | 255
2122 |
2123 |
2124 | 89
2125 | 89
2126 | 89
2127 | 255
2128 |
2129 |
2130 | 255
2131 | 255
2132 | 255
2133 | 255
2134 |
2135 | NAME
2136 | false
2137 |
2138 | 0.1
2139 | in
2140 |
2141 |
2142 |
2143 | W1
2144 | 127
2145 |
2146 |
2147 |
2148 |
2149 |
2150 |
2151 |
2152 | 0
2153 | 255
2154 | 0
2155 | 255
2156 |
2157 | FOUR
2158 | _22
2159 |
2160 |
2161 | W2
2162 | 127
2163 |
2164 |
2165 |
2166 |
2167 |
2168 |
2169 |
2170 | 0
2171 | 255
2172 | 0
2173 | 255
2174 |
2175 | FOUR
2176 | _22
2177 |
2178 |
2179 | W2
2180 | 127
2181 |
2182 |
2183 |
2184 |
2185 |
2186 |
2187 |
2188 | 0
2189 | 255
2190 | 0
2191 | 255
2192 |
2193 | FOUR
2194 | _22
2195 |
2196 |
2197 | W2
2198 | 127
2199 |
2200 |
2201 |
2202 |
2203 |
2204 |
2205 |
2206 | 0
2207 | 255
2208 | 0
2209 | 255
2210 |
2211 | FOUR
2212 | _22
2213 |
2214 |
2215 | L1
2216 |
2217 | VCC
2218 |
2219 |
2220 |
2221 | width
2222 |
2223 |
2224 |
2225 | superscript
2226 |
2227 |
2228 |
2229 | transform
2230 |
2231 |
2232 |
2233 | posture
2234 |
2235 |
2236 |
2237 | tracking
2238 |
2239 |
2240 |
2241 | size
2242 | 14.0
2243 |
2244 |
2245 | family
2246 | Tahoma
2247 |
2248 |
2249 | weight
2250 |
2251 |
2252 |
2253 |
2254 |
2255 | false
2256 | CENTER
2257 | CENTER
2258 | DEFAULT
2259 |
2260 |
2261 | L4
2262 |
2263 | GND
2264 |
2265 |
2266 | false
2267 | CENTER
2268 | CENTER
2269 | DEFAULT
2270 |
2271 |
2272 | L1
2273 |
2274 | VCC
2275 |
2276 |
2277 |
2278 | width
2279 |
2280 |
2281 |
2282 | superscript
2283 |
2284 |
2285 |
2286 | transform
2287 |
2288 |
2289 |
2290 | posture
2291 |
2292 |
2293 |
2294 | tracking
2295 |
2296 |
2297 |
2298 | size
2299 | 14.0
2300 |
2301 |
2302 | family
2303 | Tahoma
2304 |
2305 |
2306 | weight
2307 |
2308 |
2309 |
2310 |
2311 |
2312 | 0
2313 | 0
2314 | 0
2315 | 255
2316 |
2317 | false
2318 | CENTER
2319 | CENTER
2320 | DEFAULT
2321 |
2322 |
2323 | L4
2324 |
2325 | GND
2326 |
2327 |
2328 |
2329 | width
2330 |
2331 |
2332 |
2333 | superscript
2334 |
2335 |
2336 |
2337 | transform
2338 |
2339 |
2340 |
2341 | posture
2342 |
2343 |
2344 |
2345 | tracking
2346 |
2347 |
2348 |
2349 | size
2350 | 14.0
2351 |
2352 |
2353 | family
2354 | Tahoma
2355 |
2356 |
2357 | weight
2358 |
2359 |
2360 |
2361 |
2362 |
2363 | 0
2364 | 0
2365 | 0
2366 | 255
2367 |
2368 | false
2369 | CENTER
2370 | CENTER
2371 | DEFAULT
2372 |
2373 |
2374 | L4
2375 |
2376 | INHIBIT
2377 |
2378 |
2379 |
2380 | width
2381 |
2382 |
2383 |
2384 | superscript
2385 |
2386 |
2387 |
2388 | transform
2389 |
2390 |
2391 |
2392 | posture
2393 |
2394 |
2395 |
2396 | tracking
2397 |
2398 |
2399 |
2400 | size
2401 | 14.0
2402 |
2403 |
2404 | family
2405 | Tahoma
2406 |
2407 |
2408 | weight
2409 |
2410 |
2411 |
2412 |
2413 |
2414 | 0
2415 | 0
2416 | 0
2417 | 255
2418 |
2419 | false
2420 | CENTER
2421 | CENTER
2422 | DEFAULT
2423 |
2424 |
2425 | L4
2426 |
2427 | (IN)
2428 |
2429 |
2430 |
2431 | width
2432 |
2433 |
2434 |
2435 | superscript
2436 |
2437 |
2438 |
2439 | transform
2440 |
2441 |
2442 |
2443 | posture
2444 |
2445 |
2446 |
2447 | tracking
2448 |
2449 |
2450 |
2451 | size
2452 | 14.0
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/GenerateKCS/GenerateKCS.ino:
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1 | //
2 | // Generates a Kansas City Standard compatible audio output
3 | // on the selected PWM pin.
4 | //
5 | // This is part of the KCSviewer repo at https://github.com/SmallRoomLabs/KCSviewer
6 | // for the RetroChallenge 2018/09 competition
7 | //
8 | //
9 |
10 | #define REFCLK (16000000.0/510.0)
11 |
12 |
13 | #define MARK 1
14 | #define MARK_CYCLES 8
15 | #define MARK_FREQ 2400.0
16 | #define MARK_INCR (4294967296.0*MARK_FREQ)/REFCLK
17 |
18 | #define SPACE 0
19 | #define SPACE_CYCLES 4
20 | #define SPACE_FREQ 1200.0
21 | #define SPACE_INCR (4294967296.0*SPACE_FREQ)/REFCLK
22 |
23 | #define IDLE 65535
24 |
25 | #define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
26 | #define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
27 |
28 | const uint8_t sine256[] = {
29 | 127, 130, 133, 136, 139, 143, 146, 149, 152, 155, 158, 161, 164, 167, 170, 173,
30 | 176, 178, 181, 184, 187, 190, 192, 195, 198, 200, 203, 205, 208, 210, 212, 215,
31 | 217, 219, 221, 223, 225, 227, 229, 231, 233, 234, 236, 238, 239, 240, 242, 243,
32 | 244, 245, 247, 248, 249, 249, 250, 251, 252, 252, 253, 253, 253, 254, 254, 254,
33 | 254, 254, 254, 254, 253, 253, 253, 252, 252, 251, 250, 249, 249, 248, 247, 245,
34 | 244, 243, 242, 240, 239, 238, 236, 234, 233, 231, 229, 227, 225, 223, 221, 219,
35 | 217, 215, 212, 210, 208, 205, 203, 200, 198, 195, 192, 190, 187, 184, 181, 178,
36 | 176, 173, 170, 167, 164, 161, 158, 155, 152, 149, 146, 143, 139, 136, 133, 130,
37 | 128, 124, 121, 118, 115, 111, 108, 105, 102, 99, 96, 93, 90, 87, 84 , 81,
38 | 78, 76, 73, 70, 67, 64, 62, 59, 56, 54, 51, 49, 46, 44, 42, 39,
39 | 37, 35, 33, 31, 29, 27, 25, 23, 21, 20, 18, 16, 15, 14, 12, 11,
40 | 10, 9, 7, 6, 5, 5, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0,
41 | 0, 0, 0, 0, 1, 1, 1, 2, 2, 3, 4, 5, 5, 6, 7, 9,
42 | 10, 11, 12, 14, 15, 16, 18, 20, 21, 23, 25, 27, 29, 31, 33, 35,
43 | 37, 39, 42, 44, 46, 49, 51, 54, 56, 59, 62, 64, 67, 70, 73, 76,
44 | 78, 81, 84, 87, 90, 93, 96, 99, 102, 105, 108, 111, 115, 118, 121, 124
45 | };
46 |
47 |
48 | //const uint8_t bits[] = {0, 1, 0, 0, 0, 0, 0, 0, 0}; // Short for testing the Audio->Serial pcb
49 |
50 | uint8_t bits[] = {
51 | // 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
52 | // 0, 1, 0, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
53 | // 0, 1, 1, 0, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
54 | // 0, 1, 1, 1, 0, 1, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
55 | // 0, 1, 1, 1, 1, 0, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
56 | // 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
57 | // 0, 1, 1, 1, 1, 1, 1, 0, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
58 | // 0, 1, 1, 1, 1, 1, 1, 1, 0, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
59 | // 0, 1, 1, 1, 1, 1, 1, 0, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
60 | // 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
61 | // 0, 1, 1, 1, 1, 0, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
62 | // 0, 1, 1, 1, 0, 1, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
63 | // 0, 1, 1, 0, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
64 | // 0, 1, 0, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
65 | // 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
66 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,1,1,1,1,1
67 | };
68 |
69 | uint16_t sequencelength = sizeof(bits);
70 |
71 | volatile uint16_t bitp = IDLE;
72 |
73 | #define PWMPIN 3
74 | #define BITPIN 2
75 |
76 |
77 | void setup() {
78 | Serial.begin(115200);
79 | Serial.println("Kansas City Standard tape simulator");
80 |
81 | pinMode(PWMPIN, OUTPUT); // PWM pin for OCR2B
82 | pinMode(BITPIN, OUTPUT);
83 | pinMode(LED_BUILTIN, OUTPUT);
84 |
85 | // Timer2 Clock Prescaler to /1
86 | sbi (TCCR2B, CS20);
87 | cbi (TCCR2B, CS21);
88 | cbi (TCCR2B, CS22);
89 |
90 | // Timer2 PWM Mode set to Phase Correct PWM
91 | cbi (TCCR2A, COM2A0); // Clear the Compare Match
92 | sbi (TCCR2A, COM2A1);
93 |
94 | cbi (TCCR2A, COM2B0); // Clear the Compare Match
95 | sbi (TCCR2A, COM2B1);
96 |
97 |
98 | sbi (TCCR2A, WGM20); // Mode 1, Phase correct PWM
99 | cbi (TCCR2A, WGM21);
100 | cbi (TCCR2B, WGM22);
101 |
102 | OCR2B = 128;
103 |
104 | // disable interrupts to avoid timing distortion
105 | cbi (TIMSK0, TOIE0); // disable Timer0 aka delay()
106 | sbi (TIMSK2, TOIE2); // enable Timer2 Interrupt
107 |
108 |
109 | // pinMode (9, OUTPUT) ;
110 | // pinMode (10, OUTPUT) ;
111 | // TCCR1A = 0xE2 ; // pins 9 and 10 in antiphase, mode 14 = fast 16 bit
112 | // TCCR1B = 0x1A ; // clock divide by 8
113 | // ICR1 = 20000 - 1 ; // 20000 * 8 = 160000 clocks = 10ms
114 | // OCR1A = 10000 - 1 ; // 50% duty cycle for pin 9
115 | // OCR1B = 200 - 1 ; // 1% duty cycle for pin 10
116 | // TCNT1 = 0x0000 ;
117 | //
118 | // pinMode (5, OUTPUT) ;
119 | // pinMode (6, OUTPUT) ;
120 | }
121 |
122 |
123 | //
124 | //
125 | //
126 | void Delay1ms() {
127 | for (uint16_t j = 0; j < 2500; j++) __asm__ __volatile__ ("nop\n\t");
128 | }
129 |
130 | void wait() {
131 | for (uint16_t i=0; i<200; i++) Delay1ms();
132 | }
133 |
134 |
135 |
136 | void Send1(uint8_t v) {
137 | while (bitp != IDLE);
138 | bits[1] = !(v & 0x01);
139 | bits[2] = !(v & 0x02);
140 | bits[3] = !(v & 0x04);
141 | bits[4] = !(v & 0x08);
142 | bits[5] = !(v & 0x10);
143 | bits[6] = !(v & 0x20);
144 | bits[7] = !(v & 0x40);
145 | bits[8] = !(v & 0x80);
146 | bitp = 0;
147 | }
148 |
149 |
150 | void Send(uint8_t v) {
151 | for (uint16_t i=0; i<6; i++) Send1(v);
152 | wait();
153 | }
154 |
155 |
156 | //
157 | //
158 | //
159 | void loop() {
160 | digitalWrite(LED_BUILTIN, HIGH); // turn the LED on
161 | Send(0x74); /* h */
162 | Send(0x79); /* E */
163 | Send(0x38); /* L */
164 | Send(0x38); /* L */
165 | Send(0x5C); /* o */
166 | Send(0x00);
167 | Send(0x50); /* r */
168 | Send(0x79); /* E */
169 | Send(0x78); /* T */
170 | Send(0x50); /* r */
171 | Send(0x5C); /* o */
172 | Send(0x58); /* c */
173 | Send(0x74); /* h */
174 | Send(0x77); /* A */
175 | Send(0x38); /* L */
176 | Send(0x38); /* L */
177 | Send(0x79); /* E */
178 | Send(0x54); /* n */
179 | Send(0x3D); /* G */
180 | Send(0x79); /* E */
181 | Send(0x00);
182 | Send(0x5B); /* 2 */
183 | Send(0x3F); /* 0 */
184 | Send(0x06); /* 1 */
185 | Send(0x7F); /* 8 */
186 | Send(0x40); /* - */
187 | Send(0x3F); /* 0 */
188 | Send(0x6F); /* 9 */
189 | Send(0x00);
190 | Send(0x00);
191 | Send(0x00);
192 | Send(0x00);
193 | Send(0x00);
194 | Send(0x00);
195 |
196 | digitalWrite(LED_BUILTIN, LOW); // turn the LED on
197 | delay(500);
198 | }
199 |
200 | //
201 | //
202 | //
203 | ISR(TIMER2_OVF_vect) {
204 | static uint32_t accu = 0; // phase accumulator
205 | static uint32_t incr = MARK_INCR; // accumulator increment value
206 | static uint8_t firstcycle = true;
207 | static uint8_t cyclecnt = 1;
208 | uint8_t isin; // index into sine table
209 |
210 | accu = accu + incr; // soft DDS, phase accu with 32 bits
211 | isin = accu >> 24; // use upper 8 bits for phase accu as frequency information
212 | OCR2B = sine256[isin];; // read from sine table and send vauleto PWM DAC
213 |
214 | if (isin > 127) {
215 | if (firstcycle) {
216 | firstcycle = false;
217 | cyclecnt--;
218 | if (cyclecnt == 0) {
219 | if ((bitp == IDLE) || (bits[bitp++] == MARK)) {
220 | incr = MARK_INCR;
221 | cyclecnt = MARK_CYCLES;
222 | sbi(PORTD, BITPIN);
223 | } else {
224 | incr = SPACE_INCR;
225 | cyclecnt = SPACE_CYCLES;
226 | cbi(PORTD, BITPIN);
227 | }
228 | if (bitp >= sequencelength) bitp = IDLE;
229 | }
230 | }
231 | } else firstcycle = true;
232 | }
233 |
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/README.md:
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1 | 
2 |
3 | #### A discrete transistor implemenation of a Kansas City Standard data tape decoder and viewer. This is my entry for the [RetroChallenge RC2018/09](http://www.retrochallenge.org/).
4 |
5 | The entries/blog here will be kept in chronological order with the newest post at the bottom.
6 |
7 | ---
8 |
9 | ## Sep 01 - Intro
10 |
11 | For this challenge I'll attempt to make a decoder/viewer for the old [Kansas City Standard](https://en.wikipedia.org/wiki/Kansas_City_standard) tapes that once was the standard for storing data and programs on regular cassette tapes.
12 |
13 | Since I have a thing for using discrete transistors instead of ICs I'll make it with just Q's R's and C's. Maybe a D and some LEDs will appear as well, but definitely no ICs.
14 |
15 | The KCS is a simple low speed (300 bps) [FSK](https://en.wikipedia.org/wiki/Frequency-shift_keying) (Frequency Shift Keying) that are using 1200 and 2400 Hz to represent the zeros and ones in the data stream. A zero is four cycles of 1200Hz, and a one is eight cycles of 2400Hz.
16 |
17 | Every byte are, just as in a regular asynchronous UART, prepended with a startbit that is a zero, followed by the eight databits, and then finally one or two stopbits that are high.
18 |
19 | The next byte can then start directly after that (with its own startbit of course) or after an arbitrary number of high bits.
20 |
21 | This fully asynchronous signalling makes it rather easy to decode since there's no real need to make a PLL to recover the clock. Just as in an UART it's ok to just have a freerunning clock that is re-synchronized to the leading edge of each startbit. If the tape speed doesn't vary more than 5% the data should be decoded correctly.
22 |
23 | ---
24 |
25 | ## Sep 01 - Plan of attack
26 |
27 | The final goal is to be able to decode the FSK audio coming from a cassette tape or a sound file into a 8-bit parallel data with a data-valid strobe so it can be read by a computer to load software into it.
28 |
29 | As an extended more fun goal would be to connect the outputs to a 7-segment display to display the data in real time. Considering the asynchronous nature of the KCS the audio stream could have just a single byte every second and fill the rest with just idle/mark data. Then a tape would display a message character by character on the display. Or to be a bit more fancy the eight databits could drive a standard HD44780 display in 4-bit mode to display a message on the 2x16 characters there.
30 |
31 | Alternatively I could modify the standard a bit and have 14 databits instead of 8 and collect them all to be shown on a startbust display instead of the 7-segment. But that would require a higher degree of match between the freerunning clock and the actual speed of the tape.
32 |
33 | So the high level overview of the design looks something like this
34 |
35 | 
36 |
37 | The pulse shaper will take the analog audio from the tape recorders line output, I guess something between 100 and 700mV, and shape it up into a nice digital square wave with logic (0/5 volt) levels.
38 |
39 | This digital audio will still be modulated with the 1200/2400 Hz carrier so the next order of business will be to demodulate that so we get something that looks just like the output of a serial port.
40 |
41 | The serial stream will enter both a shift register as well as a startbit detector.
42 |
43 | The startbit detector will trigger (or resynchronize?) the oscillator that runs at 300 Hz, driving the SIPO (Serial In Parallel Out) shiftregister.
44 |
45 | When all eight bits are shifted into the shiftregister it needs to be latched and a strobe pulse should be asserted. (This is not shown in the diagram above)
46 |
47 | ---
48 |
49 | # Sep 01 - Simulating the tape
50 |
51 | I recently got hold of a working casette tape deck, but it will be a bit of a hassle to use that during development so I made an Arduino sketch that outputs any FSK bit sequence I need.
52 |
53 | The Arduino doesn't have any analog out so it's emulated with a PWM followed by a simple lowpass filter to get rid of most of the PWM frequency.
54 |
55 | 
56 |
57 | I just soldered it up directly between a pinheader and a screw terminal. The pinheader connects to GND, D2 and D3 which conveniently are located next to each other on a Nano. D3 is used for the PWM and D2 is a reference output of the zeros and ones sent on the audio stream. This makes it easy to see what data bit that is actually being sent and how it passes through the circuit.
58 |
59 | 
60 |
61 | After writing some quick and dirty code (what else can be done using an Ardunio? ^__^ ) the output of a few bits looks like this
62 |
63 | 
64 |
65 | The code is available at [GenerateKCS](https://github.com/SmallRoomLabs/KCSviewer/tree/master/GenerateKCS)
66 |
67 | As can be seen the lowpass filter isn't the best since the 2400 Hz of the ones are getting attenuated a bit more than I had wished for, but it's good enough for the time being. Maybe I'll make a steeper filter with a bit higher center frequency someday, we'll see....
68 |
69 | ---
70 |
71 | # Sep 02 - FSK→UART
72 |
73 | ### Design & Schematics
74 |
75 | The first part of the process to convert the FSK-audio into a plain UART-like serial stream would be to shape it up into a nice square wave with full swing between GND and VCC.
76 |
77 | I'm sure there's many ways of doing this, but I just made a long tailed differential amplifier with the second side fixed to the same bias voltage as is set on the fist side. This basically makes it into a comparator. Maybe some hysteresis would be a good thing to have as well, but I'll leave that out for the time being.
78 |
79 | The now digital output (DIGITAL in the schematic) is used as a trigger for a monostable set at 300us. The 300us is longer than the 2400Hz pulse width so while 2400Hz is present the monoflop will continuously be re-triggered and will never time out. As soon as the input frequency changes to 1200Hz the timer will timeout and thus output a pulse before the next re-trigger some 10's of microseconds later.
80 |
81 | At this point (LONGS in the schematic) there will be a pulse train whenever 1200Hz is present and a steady level whenever 2400Hz is present.
82 |
83 | If this is fed into another monostable set at a even longer timeout (1100us) then the pulses in the pulse train will re-trigger the monostable and keep it active as long as the pulses are available.
84 |
85 | The output from this last monostable is a plain and simple UART serial stream.
86 |
87 | 
88 |
89 | ### Prototype
90 |
91 | I first built this on a solderless breadboard to verify my previous LTspice simulations. It worked like a charm!
92 |
93 | 
94 |
95 | ### PCB
96 |
97 | Lately I've started to actually plan and design whenever I solder something on veroboard or donut-boards. For this I use [DiyLC](http://diy-fever.com/software/diylc/)
98 |
99 | So after a bit of trying out a few different layouts I came up with this design.
100 |
101 | 
102 |
103 | I find it easier to follow the layout during soldering if I first mark the tracks-to-be on the top with a pen like this:
104 |
105 | 
106 |
107 | After this it's easy enough to just plonk down the parts, bend the component leads at the bottom in the right directions and solder&snip.
108 |
109 | 
110 |
111 | ### Testing
112 |
113 | Feeding it a short FSK sequence from the Arduino KCS simulator I built/wrote yesterday it looks very good.
114 |
115 | 
116 |
117 | On the top in orange color we have the AUDIO input starting out at a (slightly attenuated) 2400 Hz followed by four cycles of 1200Hz, eight cycles 2400 and then some more 1200.
118 |
119 | The next trace is the green DIGITAL output from the comparator.
120 |
121 | The yellow trace is the LONGS pulse train from the output of the first 300us monostable.
122 |
123 | And finally the blue trace which is the SERIAL output from the second 1100us monostable.
124 |
125 | ---
126 |
127 | ## Sep 17 - Baud clock & Ring counter
128 |
129 | No noes! Real life happened and made me work basically around the clock for two weeks, but now I got some breathing room to play with my #retrochallenge project for a bit again.
130 |
131 | ### Done this time
132 |
133 | I was running out of 2.2k resistors and also started to get log on NPN's in TO-92 so I ordered 500 each of 2k2 and 10k plus a hundred each of NPN & PNP transistors. I hope they will not run out while doing this project..
134 |
135 | 
136 |
137 | My original plan was to do the startbit detection mono- and flipflops, but I realized that I needed the ring counter first in order to test that part of the design. So I went ahead with the clock generator, ring-bias and ring-stages this week.
138 |
139 | 
140 |
141 |
142 | ### Baudrate generator
143 |
144 | In order to be able to collect the bits as they come in at 300 bits per second I need a 300Hz clock pulse that can be synched to the leading edge of the startbit. Without the syncing the sample point might end up anywhere in each bitslot and we want to sample as close to the middle as possible to have as much margin as possible if the playback tape speed is a tad slower or faster than the recording tape deck. Also the frequency of the clock generator here will vary a bit in response to the temperature.
145 |
146 | A regular UART-chip usually have a clock that is 16 times the bit rate so it can digitally select the correct number of clock pulses to wait before reaching the mid-point, and they can also make multiple samples in each bit to ignore glitches. That is fine and dandy when you do it digitally and can use huge number of transistors inside the chip, but this project is more of less analog and have to be a bit frugal on the parts count so something else has to be done.
147 |
148 | The idea is to have the clock generator stopped until a flipflop is "set" by the rising edge of the startbit in the serial bitstream. When the flipflop is set then the clock generator is started and will be free-running until all data bits are collected. At the stopbit the flipflop will be "reset" and the clock will be stopped.
149 |
150 | The clock circuit looks like this:
151 |
152 | 
153 |
154 | The C1 and the resistors R8 and R9 (together with D1 ) controls the frequency as well as the pulse width ratio. The diode makes sure that only the charging cycle of C1 will be affected by the low resistance of R9 (making it fast). The discharge will be done thru the much higher resistance of R8 making it slow.
155 |
156 | This gives me pulses at 300 Hz with a very short low-going output that will be used to advance the ring counter one step.
157 |
158 |
159 | The RESET/stop input of this module merely keeps the C1 capacitor in a permanent discharged state as long as it is asserted.
160 |
161 | I just now discovered that there's a direct path between V+ and GND via Q3 and Q5 when the circuit is in the reset state - not good. The simulation says only 36 mA will flow though - that's only 180mW. But that is if one can trust the simulation to 100%.
162 |
163 | I guess I have to come up with some better solution to the reset. I'd probably be better to hoo kQ5 directly up to C1 - I think my original thought was that I wanted to force the output transistor off directly with the reset, but that's probably not really necessary.
164 |
165 |
166 | ### The bias generator
167 |
168 | The chain of ring counter modules needs two things to operate. A the clock pulse (which is merely a short interruption of the VCC supply current into the modules), and a adjustable bias voltage.
169 |
170 | The bias module is as simple as it gets - just a simple emitter follower controlled by a pot to adjust the voltage.
171 |
172 | In the schematics (from the LTspice simulations) below I replaced the pot with the two R1 & R2 transistors.
173 |
174 | 
175 |
176 | Both the clockgen and the bias got fitted onto a single PCB without any issues.
177 |
178 | 
179 |
180 | Ending up in real life as this:
181 |
182 | 
183 |
184 | The picture was taken before I changed the R1/R2 voltage divider into a pot to be able to tweak the bias voltage.
185 |
186 | ### Ring counter
187 |
188 | Each step of the ring counter is rather easy. They are being based on on a discrete BJT version of the usual thyristor-based ring counters.
189 |
190 | The thyristors are build out of a tightly coupled NPN/PNP pair so they almost end up a 4-layer N/P device.
191 |
192 | 
193 |
194 | The RI and RO connects from/to the previous/next stage by a 100nF capacitor. The STEP is the power supply with brief interruptions coming from the baudrate/clock generator. Each dip in the power moves the active stage one step to the right. It works almost by magic ;-)
195 |
196 | I hooked up three staked on the breadboard and connected the clock/bias PCB to it and the pulses shifted around beautifully just as planned.
197 |
198 | 
199 |
200 | Screenshot from the oscilloscope showing the incoming STEP pulses and the outputs from each of the three stages.
201 |
202 | 
203 |
204 | I did a quick layout with five stages on one of the usual PCBs - easy peasy.
205 |
206 | 
207 |
208 |
209 | By some reason the soldering took a while to do and I might have fscked up something because it didn't behave properly at 5 volts. I got a lot of double pulses at the outputs or all just toggled in tandem. Fiddling a bit with the bias voltage and raising the input voltage up to 12 made it better - but something is just simply wrong.
210 |
211 | 
212 |
213 | I didn't have time last weekend (when I snuck a few hours to solder all of this up) to debug the issue further. I didn't even have time to make this blogpost back then.
214 |
215 | But tomorrow I'll spend some time to get to the bottom with this and also then solder up the second 5-stage ring counter.
216 |
217 | ---
218 | ## Sep 22 - Debugging the ring counter
219 |
220 | Well, it actually seems like there wasn't any real problem with it after all. It turns out that if I connect the scope probes while it is running some extra pulses will be injected into the loop.
221 |
222 | 
223 |
224 | After discovering this I built the second ring counter PCB and hooked it up to the 300Hz generator PCB.
225 |
226 | 
227 |
228 | Initially I forgot to link the output of the second board back to the first which of course made it not-working. But after a nice cup of coffee I realized this fsckup. After attaching one more green alligator wire a single pulse walked around the ring just as it should.
229 |
230 | --
231 | ## Sep 24 - mono & s/r flops
232 |
233 | ### Monoflop for delaying the first bit
234 |
235 | Each byte in the serial bit stream have a initial zero-startbit, this startbit is used to startup the 300Hz clock generator. But we really can't have it start the clock at the leading edge of the pulse, we must wait for 1.5 bit times so we're in the middle of the first data bit. Then we can sample that bit immediately. Then at the next tick of the clock we're in the middle of the next bit.
236 |
237 | 
238 | 
239 |
240 | There's not many parts for this PCB so it's really sparse and easy to solder up.
241 |
242 | 
243 |
244 | The input of the monoflop is edge-triggered and the output is also routed through a pulse shortener. So even if I give it a long input pulse I get a short outgoing pulse after the designated delay.
245 |
246 | 
247 |
248 | Ok, this seems to work as intended. Onwards to the next module.
249 |
250 | ### S/R FlipFlop
251 |
252 | Next up is the Set/Reset flipclop that is set by the delayed startbit and then reset again by the last output of the ringcounter. This flipflop is controlling whether the 300Hz clock generator is running or not.
253 |
254 | This is also a very simple PCB ans was very quick to solder up and test. I'm really happy to have a four channel oscilloscope, it makes testing of stuff like this so much easier.
255 |
256 | 
257 |
258 | The S/R Flipflop hooked up to the oscilloscope and the arduino that generates the test signals.
259 |
260 | 
261 | Oh yes, it is flipping and flopping as expected.
262 |
263 | 
264 |
265 | ### A bit of a problem
266 | So with the clock generator, the delayer, the flopflop and the full ring counter PCBs done and tested individually it was time to connect them and test them together.
267 |
268 | But by some reason the 3.9 ms monoflop didn't act like a monoflop, it did continously cycle acting like a astable. Even if I grounded the trigger input it still just oscillated.
269 |
270 | After much head-scratching and beard-pulling I realized that the clock generator did inject enough hash on the power rail to retrigger the edge detector in the monoflop.
271 |
272 | 
273 |
274 | The blue line shows the VCC line up at the monostable. There's about 120mV dips in the power each time the ring counter advances.
275 |
276 | So I hooked up a 100uF cap across the rail close to the power stage in the ring counter oscillator.
277 |
278 | 
279 |
280 | The hash didn't go away completely, but it got reduced to about 50mV which is low enough to not disturb the monoflop.
281 |
282 | Good enough for the time being, but I probably should have both a small bulk and decoupling at each module and possibly also make a star power&ground distribution. If I ever make this into a kit I definitely will have to do that. Can't have shitty power for paying customers ;-)
283 |
284 | ---
285 |
286 | ## Sep 27 - latches
287 |
288 | In my original design I did some elaborate DTL NAND logic latches, but I now realized that that was too many parts to fit onto the small PCBs. I would have had to use at least four PCBs for it.
289 |
290 | I did a redesign and came up with something simpler. Each latch have two inputs. One shared line connected to the SERIAL output from the first PCB and then a edge triggered input that is connected to the outputs of each stage in the ring counter.
291 |
292 | So the latch stores the value of the serial line when triggered by the ring counter outputs.
293 |
294 | This is how the new latch looks. Easy-peasy I thought - it will be a piece of cake to fit four of those on each PCB.
295 |
296 | 
297 |
298 | Well, it turned out to be a bit cramped. I had to resort ugly things like putting the legs of two components into the same hole and using horizontal buses above the parts as well. But ok, why not as long as it works. This isn't a beauty contest...
299 |
300 | 
301 |
302 | Time for some full integration testing of the entire system. Some conenction points have soldered wires and some are still with alligator clips. It kinda worked, but the ring counter was very finicky and didn't really want step properly.
303 |
304 | 
305 |
306 | It turned out that the pulse-shortening input stage of the latches loaded down the unbuffered outputs at the ring counter stages. So I had to patch on a thin extra PCB between the ring counter pcb and the latch pcb.
307 |
308 | At the same time I had to change the output on the ring counters from Q to /Q since the buffer pcb did invert the signals. That was easy enough since I had both outputs next to each other on the pcb.
309 |
310 | 
311 |
312 | After this it worked just fine - at least with using the pwm-sine output from the Arduino.
313 |
314 | ### Tape recorder
315 |
316 | Tape recorders seems to be a thing of the past. Even CD players seems to be a bit past their prime today. I've been looking for a 70's style small mono tape recorder for a while now and found one for just $10 in a second-hand shop near me.
317 |
318 | The reason for being so cheap was that it did't output any sound, but the mechanics seemed ok so I bought it in the hopes of being able to easily fix it. It turned out that it just contained a single single-in-line IC that handled both the pre-amplifier form the head as well as the power amplifier for the built-in speaker. It was hot to touch and dead. I ordered a replacement for it from ebay, but it hasn't arrived yet.
319 |
320 | Luckily a friend that I told that I was looking for a tape recorder found one in her recycling garbage room in her building and grabbed it for me.
321 |
322 | It turned out to be a new fully working device for transferring old tapes to a computer via USB. It even had a cassette tape with 70's disco music on it. Nice!
323 |
324 | 
325 |
326 |
327 | So I hooked up the arduino and recorded a minute of sound from it. Switched over the audio cables to my project and hit the play button.
328 |
329 | IT WORKS! No problems whatsoever.
330 |
331 | At this time I only had a couple of LEDs loosely patched into the outputs of the latches and it was past midnight. Better fix the rest of the things tomorrow. I'm happy enough as it is.
332 |
333 | ---
334 |
335 | ## Sep 29 - Final touches
336 |
337 | With the deadline looming just around the corner I'd better finish up the last things.
338 |
339 | ### The case of the missing display
340 |
341 | By some reason I didn't have any single-digit seven segment displays in by box of displays, but I'm the happy owner of a Zortrax M200 so I spent 20 minutes in Fusion followed by 40 minutes of printing a holder for fourteen 3mm LEDs to make my own display.
342 | 
343 |
344 | 
345 | 
346 |
347 | ### Mounting
348 |
349 | Of course I had to replace all loose wire and alligator clips with some real wiring and also tack the PCBs neatly down with double sided tape onto a piece of acrylics. I didn't bother to remove the protective plastic film from the acrylic - hence the pink tint of it.
350 |
351 | I used hot glue to fill the segment slots in the, but it turned out to be yet another thing hotsnot is not a good match for. It looks totally horrible and it doesn't diffuse the LEDs particulary well, but that's what I got for now.
352 |
353 | 
354 | ---
355 |
356 |
357 |
358 |
359 | ## Sep 30 - The video
360 |
361 | Here's a video of the (almost) full circuit in action. I have recorded the message HELLO RETROCHALLENGE 2018-09 on the tape and is playing it back. Since the design currently lack the final latch I've encoded each character multiple times to keep the display more or less for enough time to see each character.
362 |
363 | [](https://www.youtube.com/watch?v=Zs1BC_5-5ak)
364 |
365 | [ Click the image to play the video at YouTube ]
366 |
367 | I'll probably will make two more cards with the missing final latch so I can hook up a HD44780 display and show a message in a more readable way, but I really think that this is good enough to show that it is not that hard to make reasonably complex stuff with only transistors.
368 |
369 | I must admit that I'm slightly amazed that my original design made on paper and LTspice from two years back actually works and also that I had the time to pull it off during this short month.
370 |
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/notes.txt:
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1 | Online Graphical editor https://designer.gravit.io
2 | Vero/Breadboard designer http://diy-fever.com/software/diylc/
3 | java -jar Contents/Resources/Java/diylc.jar
4 |
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