├── LICENSE ├── README.md ├── doc └── Pipeline Architecture.pdf └── src ├── ALU.v ├── ALU_Decoder.v ├── Control_Unit_Top.v ├── Data_Memory.v ├── Decode_Cyle.v ├── Execute_Cycle.v ├── Fetch_Cycle.v ├── Hazard_unit.v ├── Instruction_Memory.v ├── Main_Decoder.v ├── Memory_Cycle.v ├── Mux.v ├── PC.v ├── PC_Adder.v ├── Pipeline_Top.v ├── Register_File.v ├── Sign_Extend.v ├── Writeback_Cycle.v ├── memfile.hex ├── pipeline.gtkw └── pipeline_tb.v /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/merldsu/RISCV_Pipeline_Core/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/merldsu/RISCV_Pipeline_Core/HEAD/README.md -------------------------------------------------------------------------------- /doc/Pipeline Architecture.pdf: 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