├── LICENSE ├── README.md ├── doc └── Pipeline Architecture.pdf └── src ├── ALU.v ├── ALU_Decoder.v ├── Control_Unit_Top.v ├── Data_Memory.v ├── Decode_Cyle.v ├── Execute_Cycle.v ├── Fetch_Cycle.v ├── Hazard_unit.v ├── Instruction_Memory.v ├── Main_Decoder.v ├── Memory_Cycle.v ├── Mux.v ├── PC.v ├── PC_Adder.v ├── Pipeline_Top.v ├── Register_File.v ├── Sign_Extend.v ├── Writeback_Cycle.v ├── memfile.hex ├── pipeline.gtkw └── pipeline_tb.v /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright 2023 MERL-DSU 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISCV_Pipeline_Core 2 | This repository contains the design files of RISC-V Pipeline Core 3 | 4 | # TOP Architecture 5 | ![Screenshot from 2023-05-11 11-34-13](https://github.com/merldsu/RISCV_Pipeline_Core/assets/53592110/4caaeee5-e804-42ae-b0f0-264a62f2d385) 6 | 7 | 8 | # LICENSE 9 | 10 | Copyright 2023 MERL-DSU 11 | 12 | Licensed under the Apache License, Version 2.0 (the "License"); 13 | you may not use this file except in compliance with the License. 14 | You may obtain a copy of the License at 15 | 16 | http://www.apache.org/licenses/LICENSE-2.0 17 | 18 | Unless required by applicable law or agreed to in writing, software 19 | distributed under the License is distributed on an "AS IS" BASIS, 20 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | See the License for the specific language governing permissions and 22 | limitations under the License. 23 | -------------------------------------------------------------------------------- /doc/Pipeline Architecture.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/merldsu/RISCV_Pipeline_Core/4c006ac2a4e5326253f668894e9a237327391e49/doc/Pipeline Architecture.pdf -------------------------------------------------------------------------------- /src/ALU.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module ALU(A,B,Result,ALUControl,OverFlow,Carry,Zero,Negative); 16 | 17 | input [31:0]A,B; 18 | input [2:0]ALUControl; 19 | output Carry,OverFlow,Zero,Negative; 20 | output [31:0]Result; 21 | 22 | wire Cout; 23 | wire [31:0]Sum; 24 | 25 | assign Sum = (ALUControl[0] == 1'b0) ? A + B : 26 | (A + ((~B)+1)) ; 27 | assign {Cout,Result} = (ALUControl == 3'b000) ? Sum : 28 | (ALUControl == 3'b001) ? Sum : 29 | (ALUControl == 3'b010) ? A & B : 30 | (ALUControl == 3'b011) ? A | B : 31 | (ALUControl == 3'b101) ? {{32{1'b0}},(Sum[31])} : 32 | {33{1'b0}}; 33 | assign OverFlow = ((Sum[31] ^ A[31]) & 34 | (~(ALUControl[0] ^ B[31] ^ A[31])) & 35 | (~ALUControl[1])); 36 | assign Carry = ((~ALUControl[1]) & Cout); 37 | assign Zero = &(~Result); 38 | assign Negative = Result[31]; 39 | 40 | endmodule -------------------------------------------------------------------------------- /src/ALU_Decoder.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module ALU_Decoder(ALUOp,funct3,funct7,op,ALUControl); 16 | 17 | input [1:0]ALUOp; 18 | input [2:0]funct3; 19 | input [6:0]funct7,op; 20 | output [2:0]ALUControl; 21 | 22 | // Method 1 23 | // assign ALUControl = (ALUOp == 2'b00) ? 3'b000 : 24 | // (ALUOp == 2'b01) ? 3'b001 : 25 | // (ALUOp == 2'b10) ? ((funct3 == 3'b000) ? ((({op[5],funct7[5]} == 2'b00) | ({op[5],funct7[5]} == 2'b01) | ({op[5],funct7[5]} == 2'b10)) ? 3'b000 : 3'b001) : 26 | // (funct3 == 3'b010) ? 3'b101 : 27 | // (funct3 == 3'b110) ? 3'b011 : 28 | // (funct3 == 3'b111) ? 3'b010 : 3'b000) : 29 | // 3'b000; 30 | 31 | // Method 2 32 | assign ALUControl = (ALUOp == 2'b00) ? 3'b000 : 33 | (ALUOp == 2'b01) ? 3'b001 : 34 | ((ALUOp == 2'b10) & (funct3 == 3'b000) & ({op[5],funct7[5]} == 2'b11)) ? 3'b001 : 35 | ((ALUOp == 2'b10) & (funct3 == 3'b000) & ({op[5],funct7[5]} != 2'b11)) ? 3'b000 : 36 | ((ALUOp == 2'b10) & (funct3 == 3'b010)) ? 3'b101 : 37 | ((ALUOp == 2'b10) & (funct3 == 3'b110)) ? 3'b011 : 38 | ((ALUOp == 2'b10) & (funct3 == 3'b111)) ? 3'b010 : 39 | 3'b000 ; 40 | endmodule -------------------------------------------------------------------------------- /src/Control_Unit_Top.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | `include "ALU_Decoder.v" 16 | `include "Main_Decoder.v" 17 | 18 | module Control_Unit_Top(Op,RegWrite,ImmSrc,ALUSrc,MemWrite,ResultSrc,Branch,funct3,funct7,ALUControl); 19 | 20 | input [6:0]Op,funct7; 21 | input [2:0]funct3; 22 | output RegWrite,ALUSrc,MemWrite,ResultSrc,Branch; 23 | output [1:0]ImmSrc; 24 | output [2:0]ALUControl; 25 | 26 | wire [1:0]ALUOp; 27 | 28 | Main_Decoder Main_Decoder( 29 | .Op(Op), 30 | .RegWrite(RegWrite), 31 | .ImmSrc(ImmSrc), 32 | .MemWrite(MemWrite), 33 | .ResultSrc(ResultSrc), 34 | .Branch(Branch), 35 | .ALUSrc(ALUSrc), 36 | .ALUOp(ALUOp) 37 | ); 38 | 39 | ALU_Decoder ALU_Decoder( 40 | .ALUOp(ALUOp), 41 | .funct3(funct3), 42 | .funct7(funct7), 43 | .op(Op), 44 | .ALUControl(ALUControl) 45 | ); 46 | 47 | 48 | endmodule -------------------------------------------------------------------------------- /src/Data_Memory.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module Data_Memory(clk,rst,WE,WD,A,RD); 16 | 17 | input clk,rst,WE; 18 | input [31:0]A,WD; 19 | output [31:0]RD; 20 | 21 | reg [31:0] mem [1023:0]; 22 | 23 | always @ (posedge clk) 24 | begin 25 | if(WE) 26 | mem[A] <= WD; 27 | end 28 | 29 | assign RD = (~rst) ? 32'd0 : mem[A]; 30 | 31 | initial begin 32 | mem[0] = 32'h00000000; 33 | //mem[40] = 32'h00000002; 34 | end 35 | 36 | 37 | endmodule -------------------------------------------------------------------------------- /src/Decode_Cyle.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | 16 | module decode_cycle(clk, rst, InstrD, PCD, PCPlus4D, RegWriteW, RDW, ResultW, RegWriteE, ALUSrcE, MemWriteE, ResultSrcE, 17 | BranchE, ALUControlE, RD1_E, RD2_E, Imm_Ext_E, RD_E, PCE, PCPlus4E, RS1_E, RS2_E); 18 | 19 | // Declaring I/O 20 | input clk, rst, RegWriteW; 21 | input [4:0] RDW; 22 | input [31:0] InstrD, PCD, PCPlus4D, ResultW; 23 | 24 | output RegWriteE,ALUSrcE,MemWriteE,ResultSrcE,BranchE; 25 | output [2:0] ALUControlE; 26 | output [31:0] RD1_E, RD2_E, Imm_Ext_E; 27 | output [4:0] RS1_E, RS2_E, RD_E; 28 | output [31:0] PCE, PCPlus4E; 29 | 30 | // Declare Interim Wires 31 | wire RegWriteD,ALUSrcD,MemWriteD,ResultSrcD,BranchD; 32 | wire [1:0] ImmSrcD; 33 | wire [2:0] ALUControlD; 34 | wire [31:0] RD1_D, RD2_D, Imm_Ext_D; 35 | 36 | // Declaration of Interim Register 37 | reg RegWriteD_r,ALUSrcD_r,MemWriteD_r,ResultSrcD_r,BranchD_r; 38 | reg [2:0] ALUControlD_r; 39 | reg [31:0] RD1_D_r, RD2_D_r, Imm_Ext_D_r; 40 | reg [4:0] RD_D_r, RS1_D_r, RS2_D_r; 41 | reg [31:0] PCD_r, PCPlus4D_r; 42 | 43 | 44 | // Initiate the modules 45 | // Control Unit 46 | Control_Unit_Top control ( 47 | .Op(InstrD[6:0]), 48 | .RegWrite(RegWriteD), 49 | .ImmSrc(ImmSrcD), 50 | .ALUSrc(ALUSrcD), 51 | .MemWrite(MemWriteD), 52 | .ResultSrc(ResultSrcD), 53 | .Branch(BranchD), 54 | .funct3(InstrD[14:12]), 55 | .funct7(InstrD[31:25]), 56 | .ALUControl(ALUControlD) 57 | ); 58 | 59 | // Register File 60 | Register_File rf ( 61 | .clk(clk), 62 | .rst(rst), 63 | .WE3(RegWriteW), 64 | .WD3(ResultW), 65 | .A1(InstrD[19:15]), 66 | .A2(InstrD[24:20]), 67 | .A3(RDW), 68 | .RD1(RD1_D), 69 | .RD2(RD2_D) 70 | ); 71 | 72 | // Sign Extension 73 | Sign_Extend extension ( 74 | .In(InstrD[31:0]), 75 | .Imm_Ext(Imm_Ext_D), 76 | .ImmSrc(ImmSrcD) 77 | ); 78 | 79 | // Declaring Register Logic 80 | always @(posedge clk or negedge rst) begin 81 | if(rst == 1'b0) begin 82 | RegWriteD_r <= 1'b0; 83 | ALUSrcD_r <= 1'b0; 84 | MemWriteD_r <= 1'b0; 85 | ResultSrcD_r <= 1'b0; 86 | BranchD_r <= 1'b0; 87 | ALUControlD_r <= 3'b000; 88 | RD1_D_r <= 32'h00000000; 89 | RD2_D_r <= 32'h00000000; 90 | Imm_Ext_D_r <= 32'h00000000; 91 | RD_D_r <= 5'h00; 92 | PCD_r <= 32'h00000000; 93 | PCPlus4D_r <= 32'h00000000; 94 | RS1_D_r <= 5'h00; 95 | RS2_D_r <= 5'h00; 96 | end 97 | else begin 98 | RegWriteD_r <= RegWriteD; 99 | ALUSrcD_r <= ALUSrcD; 100 | MemWriteD_r <= MemWriteD; 101 | ResultSrcD_r <= ResultSrcD; 102 | BranchD_r <= BranchD; 103 | ALUControlD_r <= ALUControlD; 104 | RD1_D_r <= RD1_D; 105 | RD2_D_r <= RD2_D; 106 | Imm_Ext_D_r <= Imm_Ext_D; 107 | RD_D_r <= InstrD[11:7]; 108 | PCD_r <= PCD; 109 | PCPlus4D_r <= PCPlus4D; 110 | RS1_D_r <= InstrD[19:15]; 111 | RS2_D_r <= InstrD[24:20]; 112 | end 113 | end 114 | 115 | // Output asssign statements 116 | assign RegWriteE = RegWriteD_r; 117 | assign ALUSrcE = ALUSrcD_r; 118 | assign MemWriteE = MemWriteD_r; 119 | assign ResultSrcE = ResultSrcD_r; 120 | assign BranchE = BranchD_r; 121 | assign ALUControlE = ALUControlD_r; 122 | assign RD1_E = RD1_D_r; 123 | assign RD2_E = RD2_D_r; 124 | assign Imm_Ext_E = Imm_Ext_D_r; 125 | assign RD_E = RD_D_r; 126 | assign PCE = PCD_r; 127 | assign PCPlus4E = PCPlus4D_r; 128 | assign RS1_E = RS1_D_r; 129 | assign RS2_E = RS2_D_r; 130 | 131 | endmodule -------------------------------------------------------------------------------- /src/Execute_Cycle.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module execute_cycle(clk, rst, RegWriteE, ALUSrcE, MemWriteE, ResultSrcE, BranchE, ALUControlE, 16 | RD1_E, RD2_E, Imm_Ext_E, RD_E, PCE, PCPlus4E, PCSrcE, PCTargetE, RegWriteM, MemWriteM, ResultSrcM, RD_M, PCPlus4M, WriteDataM, ALU_ResultM, ResultW, ForwardA_E, ForwardB_E); 17 | 18 | // Declaration I/Os 19 | input clk, rst, RegWriteE,ALUSrcE,MemWriteE,ResultSrcE,BranchE; 20 | input [2:0] ALUControlE; 21 | input [31:0] RD1_E, RD2_E, Imm_Ext_E; 22 | input [4:0] RD_E; 23 | input [31:0] PCE, PCPlus4E; 24 | input [31:0] ResultW; 25 | input [1:0] ForwardA_E, ForwardB_E; 26 | 27 | output PCSrcE, RegWriteM, MemWriteM, ResultSrcM; 28 | output [4:0] RD_M; 29 | output [31:0] PCPlus4M, WriteDataM, ALU_ResultM; 30 | output [31:0] PCTargetE; 31 | 32 | // Declaration of Interim Wires 33 | wire [31:0] Src_A, Src_B_interim, Src_B; 34 | wire [31:0] ResultE; 35 | wire ZeroE; 36 | 37 | // Declaration of Register 38 | reg RegWriteE_r, MemWriteE_r, ResultSrcE_r; 39 | reg [4:0] RD_E_r; 40 | reg [31:0] PCPlus4E_r, RD2_E_r, ResultE_r; 41 | 42 | // Declaration of Modules 43 | // 3 by 1 Mux for Source A 44 | Mux_3_by_1 srca_mux ( 45 | .a(RD1_E), 46 | .b(ResultW), 47 | .c(ALU_ResultM), 48 | .s(ForwardA_E), 49 | .d(Src_A) 50 | ); 51 | 52 | // 3 by 1 Mux for Source B 53 | Mux_3_by_1 srcb_mux ( 54 | .a(RD2_E), 55 | .b(ResultW), 56 | .c(ALU_ResultM), 57 | .s(ForwardB_E), 58 | .d(Src_B_interim) 59 | ); 60 | // ALU Src Mux 61 | Mux alu_src_mux ( 62 | .a(Src_B_interim), 63 | .b(Imm_Ext_E), 64 | .s(ALUSrcE), 65 | .c(Src_B) 66 | ); 67 | 68 | // ALU Unit 69 | ALU alu ( 70 | .A(Src_A), 71 | .B(Src_B), 72 | .Result(ResultE), 73 | .ALUControl(ALUControlE), 74 | .OverFlow(), 75 | .Carry(), 76 | .Zero(ZeroE), 77 | .Negative() 78 | ); 79 | 80 | // Adder 81 | PC_Adder branch_adder ( 82 | .a(PCE), 83 | .b(Imm_Ext_E), 84 | .c(PCTargetE) 85 | ); 86 | 87 | // Register Logic 88 | always @(posedge clk or negedge rst) begin 89 | if(rst == 1'b0) begin 90 | RegWriteE_r <= 1'b0; 91 | MemWriteE_r <= 1'b0; 92 | ResultSrcE_r <= 1'b0; 93 | RD_E_r <= 5'h00; 94 | PCPlus4E_r <= 32'h00000000; 95 | RD2_E_r <= 32'h00000000; 96 | ResultE_r <= 32'h00000000; 97 | end 98 | else begin 99 | RegWriteE_r <= RegWriteE; 100 | MemWriteE_r <= MemWriteE; 101 | ResultSrcE_r <= ResultSrcE; 102 | RD_E_r <= RD_E; 103 | PCPlus4E_r <= PCPlus4E; 104 | RD2_E_r <= Src_B_interim; 105 | ResultE_r <= ResultE; 106 | end 107 | end 108 | 109 | // Output Assignments 110 | assign PCSrcE = ZeroE & BranchE; 111 | assign RegWriteM = RegWriteE_r; 112 | assign MemWriteM = MemWriteE_r; 113 | assign ResultSrcM = ResultSrcE_r; 114 | assign RD_M = RD_E_r; 115 | assign PCPlus4M = PCPlus4E_r; 116 | assign WriteDataM = RD2_E_r; 117 | assign ALU_ResultM = ResultE_r; 118 | 119 | endmodule -------------------------------------------------------------------------------- /src/Fetch_Cycle.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module fetch_cycle(clk, rst, PCSrcE, PCTargetE, InstrD, PCD, PCPlus4D); 16 | 17 | // Declare input & outputs 18 | input clk, rst; 19 | input PCSrcE; 20 | input [31:0] PCTargetE; 21 | output [31:0] InstrD; 22 | output [31:0] PCD, PCPlus4D; 23 | 24 | // Declaring interim wires 25 | wire [31:0] PC_F, PCF, PCPlus4F; 26 | wire [31:0] InstrF; 27 | 28 | // Declaration of Register 29 | reg [31:0] InstrF_reg; 30 | reg [31:0] PCF_reg, PCPlus4F_reg; 31 | 32 | 33 | // Initiation of Modules 34 | // Declare PC Mux 35 | Mux PC_MUX (.a(PCPlus4F), 36 | .b(PCTargetE), 37 | .s(PCSrcE), 38 | .c(PC_F) 39 | ); 40 | 41 | // Declare PC Counter 42 | PC_Module Program_Counter ( 43 | .clk(clk), 44 | .rst(rst), 45 | .PC(PCF), 46 | .PC_Next(PC_F) 47 | ); 48 | 49 | // Declare Instruction Memory 50 | Instruction_Memory IMEM ( 51 | .rst(rst), 52 | .A(PCF), 53 | .RD(InstrF) 54 | ); 55 | 56 | // Declare PC adder 57 | PC_Adder PC_adder ( 58 | .a(PCF), 59 | .b(32'h00000004), 60 | .c(PCPlus4F) 61 | ); 62 | 63 | // Fetch Cycle Register Logic 64 | always @(posedge clk or negedge rst) begin 65 | if(rst == 1'b0) begin 66 | InstrF_reg <= 32'h00000000; 67 | PCF_reg <= 32'h00000000; 68 | PCPlus4F_reg <= 32'h00000000; 69 | end 70 | else begin 71 | InstrF_reg <= InstrF; 72 | PCF_reg <= PCF; 73 | PCPlus4F_reg <= PCPlus4F; 74 | end 75 | end 76 | 77 | 78 | // Assigning Registers Value to the Output port 79 | assign InstrD = (rst == 1'b0) ? 32'h00000000 : InstrF_reg; 80 | assign PCD = (rst == 1'b0) ? 32'h00000000 : PCF_reg; 81 | assign PCPlus4D = (rst == 1'b0) ? 32'h00000000 : PCPlus4F_reg; 82 | 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /src/Hazard_unit.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module hazard_unit(rst, RegWriteM, RegWriteW, RD_M, RD_W, Rs1_E, Rs2_E, ForwardAE, ForwardBE); 16 | 17 | // Declaration of I/Os 18 | input rst, RegWriteM, RegWriteW; 19 | input [4:0] RD_M, RD_W, Rs1_E, Rs2_E; 20 | output [1:0] ForwardAE, ForwardBE; 21 | 22 | assign ForwardAE = (rst == 1'b0) ? 2'b00 : 23 | ((RegWriteM == 1'b1) & (RD_M != 5'h00) & (RD_M == Rs1_E)) ? 2'b10 : 24 | ((RegWriteW == 1'b1) & (RD_W != 5'h00) & (RD_W == Rs1_E)) ? 2'b01 : 2'b00; 25 | 26 | assign ForwardBE = (rst == 1'b0) ? 2'b00 : 27 | ((RegWriteM == 1'b1) & (RD_M != 5'h00) & (RD_M == Rs2_E)) ? 2'b10 : 28 | ((RegWriteW == 1'b1) & (RD_W != 5'h00) & (RD_W == Rs2_E)) ? 2'b01 : 2'b00; 29 | 30 | endmodule -------------------------------------------------------------------------------- /src/Instruction_Memory.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module Instruction_Memory(rst,A,RD); 16 | 17 | input rst; 18 | input [31:0]A; 19 | output [31:0]RD; 20 | 21 | reg [31:0] mem [1023:0]; 22 | 23 | assign RD = (rst == 1'b0) ? {32{1'b0}} : mem[A[31:2]]; 24 | 25 | initial begin 26 | $readmemh("memfile.hex",mem); 27 | end 28 | 29 | 30 | /* 31 | initial begin 32 | //mem[0] = 32'hFFC4A303; 33 | //mem[1] = 32'h00832383; 34 | // mem[0] = 32'h0064A423; 35 | // mem[1] = 32'h00B62423; 36 | mem[0] = 32'h0062E233; 37 | // mem[1] = 32'h00B62423; 38 | 39 | end 40 | */ 41 | endmodule -------------------------------------------------------------------------------- /src/Main_Decoder.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module Main_Decoder(Op,RegWrite,ImmSrc,ALUSrc,MemWrite,ResultSrc,Branch,ALUOp); 16 | input [6:0]Op; 17 | output RegWrite,ALUSrc,MemWrite,ResultSrc,Branch; 18 | output [1:0]ImmSrc,ALUOp; 19 | 20 | assign RegWrite = (Op == 7'b0000011 | Op == 7'b0110011 | Op == 7'b0010011 ) ? 1'b1 : 21 | 1'b0 ; 22 | assign ImmSrc = (Op == 7'b0100011) ? 2'b01 : 23 | (Op == 7'b1100011) ? 2'b10 : 24 | 2'b00 ; 25 | assign ALUSrc = (Op == 7'b0000011 | Op == 7'b0100011 | Op == 7'b0010011) ? 1'b1 : 26 | 1'b0 ; 27 | assign MemWrite = (Op == 7'b0100011) ? 1'b1 : 28 | 1'b0 ; 29 | assign ResultSrc = (Op == 7'b0000011) ? 1'b1 : 30 | 1'b0 ; 31 | assign Branch = (Op == 7'b1100011) ? 1'b1 : 32 | 1'b0 ; 33 | assign ALUOp = (Op == 7'b0110011) ? 2'b10 : 34 | (Op == 7'b1100011) ? 2'b01 : 35 | 2'b00 ; 36 | 37 | endmodule -------------------------------------------------------------------------------- /src/Memory_Cycle.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module memory_cycle(clk, rst, RegWriteM, MemWriteM, ResultSrcM, RD_M, PCPlus4M, WriteDataM, 16 | ALU_ResultM, RegWriteW, ResultSrcW, RD_W, PCPlus4W, ALU_ResultW, ReadDataW); 17 | 18 | // Declaration of I/Os 19 | input clk, rst, RegWriteM, MemWriteM, ResultSrcM; 20 | input [4:0] RD_M; 21 | input [31:0] PCPlus4M, WriteDataM, ALU_ResultM; 22 | 23 | output RegWriteW, ResultSrcW; 24 | output [4:0] RD_W; 25 | output [31:0] PCPlus4W, ALU_ResultW, ReadDataW; 26 | 27 | // Declaration of Interim Wires 28 | wire [31:0] ReadDataM; 29 | 30 | // Declaration of Interim Registers 31 | reg RegWriteM_r, ResultSrcM_r; 32 | reg [4:0] RD_M_r; 33 | reg [31:0] PCPlus4M_r, ALU_ResultM_r, ReadDataM_r; 34 | 35 | // Declaration of Module Initiation 36 | Data_Memory dmem ( 37 | .clk(clk), 38 | .rst(rst), 39 | .WE(MemWriteM), 40 | .WD(WriteDataM), 41 | .A(ALU_ResultM), 42 | .RD(ReadDataM) 43 | ); 44 | 45 | // Memory Stage Register Logic 46 | always @(posedge clk or negedge rst) begin 47 | if (rst == 1'b0) begin 48 | RegWriteM_r <= 1'b0; 49 | ResultSrcM_r <= 1'b0; 50 | RD_M_r <= 5'h00; 51 | PCPlus4M_r <= 32'h00000000; 52 | ALU_ResultM_r <= 32'h00000000; 53 | ReadDataM_r <= 32'h00000000; 54 | end 55 | else begin 56 | RegWriteM_r <= RegWriteM; 57 | ResultSrcM_r <= ResultSrcM; 58 | RD_M_r <= RD_M; 59 | PCPlus4M_r <= PCPlus4M; 60 | ALU_ResultM_r <= ALU_ResultM; 61 | ReadDataM_r <= ReadDataM; 62 | end 63 | end 64 | 65 | // Declaration of output assignments 66 | assign RegWriteW = RegWriteM_r; 67 | assign ResultSrcW = ResultSrcM_r; 68 | assign RD_W = RD_M_r; 69 | assign PCPlus4W = PCPlus4M_r; 70 | assign ALU_ResultW = ALU_ResultM_r; 71 | assign ReadDataW = ReadDataM_r; 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /src/Mux.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module Mux (a,b,s,c); 16 | 17 | input [31:0]a,b; 18 | input s; 19 | output [31:0]c; 20 | 21 | assign c = (~s) ? a : b ; 22 | 23 | endmodule 24 | 25 | module Mux_3_by_1 (a,b,c,s,d); 26 | input [31:0] a,b,c; 27 | input [1:0] s; 28 | output [31:0] d; 29 | 30 | assign d = (s == 2'b00) ? a : (s == 2'b01) ? b : (s == 2'b10) ? c : 32'h00000000; 31 | 32 | endmodule -------------------------------------------------------------------------------- /src/PC.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module PC_Module(clk,rst,PC,PC_Next); 16 | input clk,rst; 17 | input [31:0]PC_Next; 18 | output [31:0]PC; 19 | reg [31:0]PC; 20 | 21 | always @(posedge clk) 22 | begin 23 | if(rst == 1'b0) 24 | PC <= {32{1'b0}}; 25 | else 26 | PC <= PC_Next; 27 | end 28 | endmodule -------------------------------------------------------------------------------- /src/PC_Adder.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module PC_Adder (a,b,c); 16 | 17 | input [31:0]a,b; 18 | output [31:0]c; 19 | 20 | assign c = a + b; 21 | 22 | endmodule -------------------------------------------------------------------------------- /src/Pipeline_Top.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | `include "Fetch_Cycle.v" 16 | `include "Decode_Cyle.v" 17 | `include "Execute_Cycle.v" 18 | `include "Memory_Cycle.v" 19 | `include "Writeback_Cycle.v" 20 | `include "PC.v" 21 | `include "PC_Adder.v" 22 | `include "Mux.v" 23 | `include "Instruction_Memory.v" 24 | `include "Control_Unit_Top.v" 25 | `include "Register_File.v" 26 | `include "Sign_Extend.v" 27 | `include "ALU.v" 28 | `include "Data_Memory.v" 29 | `include "Hazard_unit.v" 30 | 31 | 32 | module Pipeline_top(clk, rst); 33 | 34 | // Declaration of I/O 35 | input clk, rst; 36 | 37 | // Declaration of Interim Wires 38 | wire PCSrcE, RegWriteW, RegWriteE, ALUSrcE, MemWriteE, ResultSrcE, BranchE, RegWriteM, MemWriteM, ResultSrcM, ResultSrcW; 39 | wire [2:0] ALUControlE; 40 | wire [4:0] RD_E, RD_M, RDW; 41 | wire [31:0] PCTargetE, InstrD, PCD, PCPlus4D, ResultW, RD1_E, RD2_E, Imm_Ext_E, PCE, PCPlus4E, PCPlus4M, WriteDataM, ALU_ResultM; 42 | wire [31:0] PCPlus4W, ALU_ResultW, ReadDataW; 43 | wire [4:0] RS1_E, RS2_E; 44 | wire [1:0] ForwardBE, ForwardAE; 45 | 46 | 47 | // Module Initiation 48 | // Fetch Stage 49 | fetch_cycle Fetch ( 50 | .clk(clk), 51 | .rst(rst), 52 | .PCSrcE(PCSrcE), 53 | .PCTargetE(PCTargetE), 54 | .InstrD(InstrD), 55 | .PCD(PCD), 56 | .PCPlus4D(PCPlus4D) 57 | ); 58 | 59 | // Decode Stage 60 | decode_cycle Decode ( 61 | .clk(clk), 62 | .rst(rst), 63 | .InstrD(InstrD), 64 | .PCD(PCD), 65 | .PCPlus4D(PCPlus4D), 66 | .RegWriteW(RegWriteW), 67 | .RDW(RDW), 68 | .ResultW(ResultW), 69 | .RegWriteE(RegWriteE), 70 | .ALUSrcE(ALUSrcE), 71 | .MemWriteE(MemWriteE), 72 | .ResultSrcE(ResultSrcE), 73 | .BranchE(BranchE), 74 | .ALUControlE(ALUControlE), 75 | .RD1_E(RD1_E), 76 | .RD2_E(RD2_E), 77 | .Imm_Ext_E(Imm_Ext_E), 78 | .RD_E(RD_E), 79 | .PCE(PCE), 80 | .PCPlus4E(PCPlus4E), 81 | .RS1_E(RS1_E), 82 | .RS2_E(RS2_E) 83 | ); 84 | 85 | // Execute Stage 86 | execute_cycle Execute ( 87 | .clk(clk), 88 | .rst(rst), 89 | .RegWriteE(RegWriteE), 90 | .ALUSrcE(ALUSrcE), 91 | .MemWriteE(MemWriteE), 92 | .ResultSrcE(ResultSrcE), 93 | .BranchE(BranchE), 94 | .ALUControlE(ALUControlE), 95 | .RD1_E(RD1_E), 96 | .RD2_E(RD2_E), 97 | .Imm_Ext_E(Imm_Ext_E), 98 | .RD_E(RD_E), 99 | .PCE(PCE), 100 | .PCPlus4E(PCPlus4E), 101 | .PCSrcE(PCSrcE), 102 | .PCTargetE(PCTargetE), 103 | .RegWriteM(RegWriteM), 104 | .MemWriteM(MemWriteM), 105 | .ResultSrcM(ResultSrcM), 106 | .RD_M(RD_M), 107 | .PCPlus4M(PCPlus4M), 108 | .WriteDataM(WriteDataM), 109 | .ALU_ResultM(ALU_ResultM), 110 | .ResultW(ResultW), 111 | .ForwardA_E(ForwardAE), 112 | .ForwardB_E(ForwardBE) 113 | ); 114 | 115 | // Memory Stage 116 | memory_cycle Memory ( 117 | .clk(clk), 118 | .rst(rst), 119 | .RegWriteM(RegWriteM), 120 | .MemWriteM(MemWriteM), 121 | .ResultSrcM(ResultSrcM), 122 | .RD_M(RD_M), 123 | .PCPlus4M(PCPlus4M), 124 | .WriteDataM(WriteDataM), 125 | .ALU_ResultM(ALU_ResultM), 126 | .RegWriteW(RegWriteW), 127 | .ResultSrcW(ResultSrcW), 128 | .RD_W(RDW), 129 | .PCPlus4W(PCPlus4W), 130 | .ALU_ResultW(ALU_ResultW), 131 | .ReadDataW(ReadDataW) 132 | ); 133 | 134 | // Write Back Stage 135 | writeback_cycle WriteBack ( 136 | .clk(clk), 137 | .rst(rst), 138 | .ResultSrcW(ResultSrcW), 139 | .PCPlus4W(PCPlus4W), 140 | .ALU_ResultW(ALU_ResultW), 141 | .ReadDataW(ReadDataW), 142 | .ResultW(ResultW) 143 | ); 144 | 145 | // Hazard Unit 146 | hazard_unit Forwarding_block ( 147 | .rst(rst), 148 | .RegWriteM(RegWriteM), 149 | .RegWriteW(RegWriteW), 150 | .RD_M(RD_M), 151 | .RD_W(RDW), 152 | .Rs1_E(RS1_E), 153 | .Rs2_E(RS2_E), 154 | .ForwardAE(ForwardAE), 155 | .ForwardBE(ForwardBE) 156 | ); 157 | endmodule 158 | -------------------------------------------------------------------------------- /src/Register_File.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module Register_File(clk,rst,WE3,WD3,A1,A2,A3,RD1,RD2); 16 | 17 | input clk,rst,WE3; 18 | input [4:0]A1,A2,A3; 19 | input [31:0]WD3; 20 | output [31:0]RD1,RD2; 21 | 22 | reg [31:0] Register [31:0]; 23 | 24 | always @ (posedge clk) 25 | begin 26 | if(WE3 & (A3 != 5'h00)) 27 | Register[A3] <= WD3; 28 | end 29 | 30 | assign RD1 = (rst==1'b0) ? 32'd0 : Register[A1]; 31 | assign RD2 = (rst==1'b0) ? 32'd0 : Register[A2]; 32 | 33 | initial begin 34 | Register[0] = 32'h00000000; 35 | end 36 | 37 | endmodule -------------------------------------------------------------------------------- /src/Sign_Extend.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module Sign_Extend (In,ImmSrc,Imm_Ext); 16 | input [31:0] In; 17 | input [1:0] ImmSrc; 18 | output [31:0] Imm_Ext; 19 | 20 | assign Imm_Ext = (ImmSrc == 2'b00) ? {{20{In[31]}},In[31:20]} : 21 | (ImmSrc == 2'b01) ? {{20{In[31]}},In[31:25],In[11:7]} : 32'h00000000; 22 | 23 | endmodule -------------------------------------------------------------------------------- /src/Writeback_Cycle.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 MERL-DSU 2 | 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | module writeback_cycle(clk, rst, ResultSrcW, PCPlus4W, ALU_ResultW, ReadDataW, ResultW); 16 | 17 | // Declaration of IOs 18 | input clk, rst, ResultSrcW; 19 | input [31:0] PCPlus4W, ALU_ResultW, ReadDataW; 20 | 21 | output [31:0] ResultW; 22 | 23 | // Declaration of Module 24 | Mux result_mux ( 25 | .a(ALU_ResultW), 26 | .b(ReadDataW), 27 | .s(ResultSrcW), 28 | .c(ResultW) 29 | ); 30 | endmodule -------------------------------------------------------------------------------- /src/memfile.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00500293 3 | 00300313 4 | 006283B3 5 | 00002403 6 | 00100493 7 | 00940533 -------------------------------------------------------------------------------- /src/pipeline.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Wed May 3 06:16:33 2023 4 | [*] 5 | [dumpfile] "/home/hshabbir/tutorials/RISCV_Pipeline_Core/src/dump.vcd" 6 | [dumpfile_mtime] "Wed May 3 06:14:08 2023" 7 | [dumpfile_size] 16068 8 | [savefile] "/home/hshabbir/tutorials/RISCV_Pipeline_Core/src/pipeline.gtkw" 9 | [timestart] 0 10 | [size] 1848 1016 11 | [pos] -39 -39 12 | *0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] tb. 14 | [treeopen] tb.dut. 15 | [sst_width] 233 16 | [signals_width] 250 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 579 19 | @800200 20 | -Global Inputs 21 | @28 22 | tb.clk 23 | tb.rst 24 | @1000200 25 | -Global Inputs 26 | @800200 27 | -Fetch_Cycle 28 | @28 29 | tb.dut.PCSrcE 30 | @22 31 | tb.dut.PCTargetE[31:0] 32 | tb.dut.PCD[31:0] 33 | tb.dut.InstrD[31:0] 34 | tb.dut.PCPlus4D[31:0] 35 | @1000200 36 | -Fetch_Cycle 37 | @800200 38 | -Decode_Cycle 39 | @22 40 | tb.dut.PCE[31:0] 41 | tb.dut.PCPlus4E[31:0] 42 | tb.dut.RD_E[4:0] 43 | @28 44 | tb.dut.ALUControlE[2:0] 45 | tb.dut.ALUSrcE 46 | tb.dut.BranchE 47 | tb.dut.MemWriteE 48 | tb.dut.RegWriteE 49 | tb.dut.ResultSrcE 50 | @c00022 51 | tb.dut.RD1_E[31:0] 52 | @28 53 | (0)tb.dut.RD1_E[31:0] 54 | (1)tb.dut.RD1_E[31:0] 55 | (2)tb.dut.RD1_E[31:0] 56 | (3)tb.dut.RD1_E[31:0] 57 | (4)tb.dut.RD1_E[31:0] 58 | (5)tb.dut.RD1_E[31:0] 59 | (6)tb.dut.RD1_E[31:0] 60 | (7)tb.dut.RD1_E[31:0] 61 | (8)tb.dut.RD1_E[31:0] 62 | (9)tb.dut.RD1_E[31:0] 63 | (10)tb.dut.RD1_E[31:0] 64 | (11)tb.dut.RD1_E[31:0] 65 | (12)tb.dut.RD1_E[31:0] 66 | (13)tb.dut.RD1_E[31:0] 67 | (14)tb.dut.RD1_E[31:0] 68 | (15)tb.dut.RD1_E[31:0] 69 | (16)tb.dut.RD1_E[31:0] 70 | (17)tb.dut.RD1_E[31:0] 71 | (18)tb.dut.RD1_E[31:0] 72 | (19)tb.dut.RD1_E[31:0] 73 | (20)tb.dut.RD1_E[31:0] 74 | (21)tb.dut.RD1_E[31:0] 75 | (22)tb.dut.RD1_E[31:0] 76 | (23)tb.dut.RD1_E[31:0] 77 | (24)tb.dut.RD1_E[31:0] 78 | (25)tb.dut.RD1_E[31:0] 79 | (26)tb.dut.RD1_E[31:0] 80 | (27)tb.dut.RD1_E[31:0] 81 | (28)tb.dut.RD1_E[31:0] 82 | (29)tb.dut.RD1_E[31:0] 83 | (30)tb.dut.RD1_E[31:0] 84 | (31)tb.dut.RD1_E[31:0] 85 | @1401200 86 | -group_end 87 | @22 88 | tb.dut.RD2_E[31:0] 89 | tb.dut.Imm_Ext_E[31:0] 90 | @1000200 91 | -Decode_Cycle 92 | @800200 93 | -Execute_Cycle 94 | @22 95 | tb.dut.PCPlus4M[31:0] 96 | tb.dut.RD_M[4:0] 97 | @28 98 | tb.dut.MemWriteM 99 | tb.dut.RegWriteM 100 | tb.dut.ResultSrcM 101 | @22 102 | tb.dut.ALU_ResultM[31:0] 103 | tb.dut.WriteDataM[31:0] 104 | @1000200 105 | -Execute_Cycle 106 | @800200 107 | -Memory 108 | @22 109 | tb.dut.PCPlus4W[31:0] 110 | @28 111 | tb.dut.ResultSrcW 112 | @23 113 | tb.dut.ALU_ResultW[31:0] 114 | @22 115 | tb.dut.ReadDataW[31:0] 116 | @1000200 117 | -Memory 118 | @800200 119 | -Register Writeback 120 | @28 121 | tb.dut.RegWriteW 122 | @22 123 | tb.dut.RDW[4:0] 124 | tb.dut.ResultW[31:0] 125 | @1000200 126 | -Register Writeback 127 | [pattern_trace] 1 128 | [pattern_trace] 0 129 | -------------------------------------------------------------------------------- /src/pipeline_tb.v: -------------------------------------------------------------------------------- 1 | module tb(); 2 | 3 | reg clk=0, rst; 4 | 5 | always begin 6 | clk = ~clk; 7 | #50; 8 | end 9 | 10 | initial begin 11 | rst <= 1'b0; 12 | #200; 13 | rst <= 1'b1; 14 | #1000; 15 | $finish; 16 | end 17 | 18 | initial begin 19 | $dumpfile("dump.vcd"); 20 | $dumpvars(0); 21 | end 22 | 23 | Pipeline_top dut (.clk(clk), .rst(rst)); 24 | endmodule --------------------------------------------------------------------------------