├── LICENSE ├── README.md ├── codecs ├── compression ├── constraints ├── csr-fields ├── csrs ├── enums ├── extensions ├── formats ├── glossary ├── notation ├── opcode-classes ├── opcode-descriptions ├── opcode-fullnames ├── opcode-majors ├── opcode-pseudocode-alt ├── opcode-pseudocode-c ├── opcodes ├── operands ├── pseudos ├── registers └── types /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2013, The Regents of the University of California (Regents). 2 | All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V Metadata 2 | 3 | This directory contains metadata for the RISC-V Instruction Set 4 | 5 | |File|Description| 6 | |:---|:----------| 7 | |`codecs` |Instruction encodings| 8 | |`compression` |Compressed instruction| 9 | |`constraints` |Constraint definitions| 10 | |`csrs` |Control and status registers| 11 | |`csr-fields` |Control and status register fields| 12 | |`enums` |Enumerated types| 13 | |`extensions` |Instruction set extensions| 14 | |`formats` |Disassembly formats| 15 | |`opcodes` |Opcode encoding information| 16 | |`opcode-classes` |Instruction classes| 17 | |`opcode-descriptions` |Instruction descriptions| 18 | |`opcode-fullnames` |Instruction full names| 19 | |`opcode-majors` |Major opcodes| 20 | |`opcode-pseudocode-c` |Instruction pseudo code (C)| 21 | |`opcode-pseudocode-alt`|Instruction pseudo code (Alternative)| 22 | |`operands` |Operand bit encodings| 23 | |`pseudos` |Pseudo instructions| 24 | |`registers` |Registers ABI definitions| 25 | |`types` |Instruction types| 26 | 27 | riscv-meta is derived from [riscv-opcodes](https://github.com/riscv/riscv-opcodes) 28 | -------------------------------------------------------------------------------- /codecs: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # [ ... ] 3 | # 4 | # denotes a distinct instruction type, subtype and format 5 | # 6 | # [ ... ] lists operands declared in opcodes as a cross-check 7 | # 8 | # Codecs with a · sign denote a subtype of the higher level type 9 | # Codecs with a + sign denote a format variant for the same type 10 | # i.e. where codec is the distinct codec 11 | 12 | none none 13 | u rd,imm rd imm20 14 | u+o rd,offset rd oimm20 15 | uj rd,offset rd jimm20 16 | i+o rd,rs1,offset rd rs1 imm12 17 | i rd,rs1,imm rd rs1 imm12 18 | i·sh5 rd,rs1,imm rd rs1 shamt5 19 | i·sh6 rd,rs1,imm rd rs1 shamt6 20 | i·sh7 rd,rs1,imm rd rs1 shamt7 21 | i·csr rd,csr,rs1 rd rs1 csr12 22 | i·csr+i rd,csr,zimm rd zimm csr12 23 | i+l rd,offset(rs1) rd rs1 oimm12 24 | i+lf frd,offset(rs1) frd rs1 oimm12 25 | s rs2,offset(rs1) rs1 rs2 simm12 26 | sb rs1,rs2,offset rs1 rs2 sbimm12 27 | s+f frs2,offset(rs1) rs1 frs2 simm12 28 | r rd,rs1,rs2 rd rs1 rs2 29 | r+fr frd,rs1 frd rs1 30 | r+rf rd,frs1 rd frs1 31 | r+rff rd,frs1,frs2 rd frs1 frs2 32 | r+3f frd,frs1,frs2 frd frs1 frs2 33 | r·m+ff rm,frd,frs1 frd frs1 rm 34 | r·m+fr rm,frd,rs1 frd rs1 rm 35 | r·m+rf rm,rd,frs1 rd frs1 rm 36 | r·m+3f rm,frd,frs1,frs2 frd frs1 frs2 rm 37 | r4·m rm,frd,frs1,frs2,frs3 frd frs1 frs2 frs3 rm 38 | r·a aqrl,rd,rs2,(rs1) rd rs1 rs2 aq rl 39 | r·l aqrl,rd,(rs1) rd rs1 aq rl 40 | r·f pred,succ pred succ 41 | r+sf rs1 rs1 42 | r+sfa rs1,rs2 rs1 rs2 43 | cb rs1,rs2,offset crs1q cimmb 44 | cb·imm rd,rs1,imm crs1rdq cnzimmi 45 | cb·sh5 rd,rs1,imm crs1rdq cimmsh5 46 | cb·sh6 rd,rs1,imm crs1rdq cimmsh6 47 | ci rd,rs1,imm crs1rd cnzimmi 48 | ci·sh5 rd,rs1,imm crs1rd cimmsh5 49 | ci·sh6 rd,rs1,imm crs1rd cimmsh6 50 | ci·16sp rd,rs1,imm crs1rd cimm16sp 51 | ci·lwsp rd,offset(rs1) crd cimmlwsp 52 | ci·ldsp rd,offset(rs1) crd cimmldsp 53 | ci·lqsp rd,offset(rs1) crd cimmlqsp 54 | ci·lwsp+f frd,offset(rs1) cfrd cimmlwsp 55 | ci·ldsp+f frd,offset(rs1) cfrd cimmldsp 56 | ci·li rd,rs1,imm crs1rd cimmi 57 | ci·lui rd,imm crd cimmui 58 | ci·none none 59 | ciw·4spn rd,rs1,imm crdq cimm4spn 60 | cj rd,offset cimmj 61 | cj·jal rd,offset cimmj 62 | cl·lw rd,offset(rs1) crdq crs1q cimmw 63 | cl·ld rd,offset(rs1) crdq crs1q cimmd 64 | cl·lq rd,offset(rs1) crdq crs1q cimmq 65 | cl·lw+f frd,offset(rs1) cfrdq crs1q cimmw 66 | cl·ld+f frd,offset(rs1) cfrdq crs1q cimmd 67 | cr rd,rs1,rs2 crs1rd crs2 68 | cr·mv rd,rs1,rs2 crd crs2 69 | cr·jalr rd,rs1,offset crd0 crs1 70 | cr·jr rd,rs1,offset crd0 crs1 71 | cs rd,rs1,rs2 crs1rdq crs2q 72 | cs·sw+f frs2,offset(rs1) crs1q cfrs2q cimmw 73 | cs·sd+f frs2,offset(rs1) crs1q cfrs2q cimmd 74 | cs·sw rs2,offset(rs1) crs1q crs2q cimmw 75 | cs·sd rs2,offset(rs1) crs1q crs2q cimmd 76 | cs·sq rs2,offset(rs1) crs1q crs2q cimmq 77 | css·swsp rs2,offset(rs1) crs2 cimmswsp 78 | css·sdsp rs2,offset(rs1) crs2 cimmsdsp 79 | css·sqsp rs2,offset(rs1) crs2 cimmsqsp 80 | css·swsp+f frs2,offset(rs1) cfrs2 cimmswsp 81 | css·sdsp+f frs2,offset(rs1) cfrs2 cimmsdsp 82 | -------------------------------------------------------------------------------- /compression: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # [ ...] 3 | # 4 | # is one of imm_6, imm_7, imm_8, imm_9, imm_10, imm_12, 5 | # imm_18, imm_nz, imm_x2, imm_x4, imm_x8, rd_b3, rs1_b3, rs2_b3, 6 | # rs1_eq_sp, rd_eq_x0, rs1_eq_x0, rs2_eq_x0, rd_ne_x0, rs1_ne_x0, 7 | # rs2_ne_x0, rd_eq_rs1, rd_eq_ra, rd_ne_x0_x2, rd_eq_sp 8 | 9 | c.addi4spn addi imm_10 imm_x4 imm_nz rd_b3 rs1_eq_sp 10 | c.fld fld imm_8 imm_x8 rd_b3 rs1_b3 11 | c.lw lw imm_7 imm_x4 rd_b3 rs1_b3 12 | c.flw flw imm_7 imm_x4 rd_b3 rs1_b3 13 | c.fsd fsd imm_8 imm_x8 rs1_b3 rs2_b3 14 | c.sw sw imm_7 imm_x4 rs1_b3 rs2_b3 15 | c.fsw fsw imm_7 imm_x4 rs1_b3 rs2_b3 16 | c.nop addi rd_eq_x0 rs1_eq_x0 rs2_eq_x0 17 | c.addi addi simm_6 imm_nz rd_ne_x0 rd_eq_rs1 18 | c.jal jal imm_12 imm_x2 rd_eq_ra 19 | c.li addi simm_6 rd_ne_x0 rs1_eq_x0 20 | c.lui lui imm_18 imm_nz rd_ne_x0_x2 21 | c.addi16sp addi simm_10 imm_x4 imm_nz rd_eq_sp rs1_eq_sp 22 | c.srli srli imm_5 imm_nz rd_eq_rs1 rd_b3 rs1_b3 23 | c.srai srai imm_5 imm_nz rd_eq_rs1 rd_b3 rs1_b3 24 | c.andi andi imm_5 imm_nz rd_eq_rs1 rd_b3 rs1_b3 25 | c.sub sub rd_eq_rs1 rd_b3 rs1_b3 rs2_b3 26 | c.xor xor rd_eq_rs1 rd_b3 rs1_b3 rs2_b3 27 | c.or or rd_eq_rs1 rd_b3 rs1_b3 rs2_b3 28 | c.and and rd_eq_rs1 rd_b3 rs1_b3 rs2_b3 29 | c.subw subw rd_eq_rs1 rd_b3 rs1_b3 rs2_b3 30 | c.addw addw rd_eq_rs1 rd_b3 rs1_b3 rs2_b3 31 | c.j jal simm_12 imm_x2 rd_eq_x0 32 | c.beqz beq simm_9 imm_x2 rs1_b3 rs2_eq_x0 33 | c.bnez bne simm_9 imm_x2 rs1_b3 rs2_eq_x0 34 | c.slli slli imm_5 imm_nz rd_ne_x0 rd_eq_rs1 35 | c.fldsp fld imm_9 imm_x8 rs1_eq_sp 36 | c.lwsp lw imm_8 imm_x4 rd_ne_x0 rs1_eq_sp 37 | c.flwsp flw imm_8 imm_x4 rs1_eq_sp 38 | c.jr jalr imm_eq_zero rd_eq_x0 rs1_ne_x0 39 | c.mv addi imm_eq_zero rd_ne_x0 40 | c.ebreak ebreak 41 | c.jalr jalr imm_eq_zero rd_eq_ra rs1_ne_x0 42 | c.add add rd_eq_rs1 rd_ne_x0 rs2_ne_x0 43 | c.fsdsp fsd imm_9 imm_x8 rs1_eq_sp 44 | c.swsp sw imm_8 imm_x4 rs1_eq_sp 45 | c.fswsp fsw imm_8 imm_x4 rs1_eq_sp 46 | c.ld ld imm_8 imm_x8 rd_b3 rs1_b3 47 | c.sd sd imm_8 imm_x8 rs1_b3 rs2_b3 48 | c.lq lq imm_9 imm_x16 49 | c.sq sq imm_9 imm_x16 50 | c.addiw addiw simm_6 rd_ne_x0 rd_eq_rs1 51 | c.ldsp ld imm_9 imm_x8 rd_ne_x0 rs1_eq_sp 52 | c.sdsp sd imm_9 imm_x8 rs1_eq_sp 53 | c.lqsp lq imm_10 imm_x16 rs1_eq_sp 54 | c.sqsp sq imm_10 imm_x16 rs1_eq_sp 55 | -------------------------------------------------------------------------------- /constraints: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # 3 | 4 | simm_6 "imm >= -32 && imm < 32" 5 | simm_9 "imm >= -256 && imm < 256" 6 | simm_10 "imm >= -512 && imm < 512" 7 | simm_12 "imm >= -2048 && imm < 2048" 8 | imm_5 "imm >= 0 && imm <= 0b11111" 9 | imm_6 "imm >= 0 && imm <= 0b111111" 10 | imm_7 "imm >= 0 && imm <= 0b1111111" 11 | imm_8 "imm >= 0 && imm <= 0b11111111" 12 | imm_9 "imm >= 0 && imm <= 0b111111111" 13 | imm_10 "imm >= 0 && imm <= 0b1111111111" 14 | imm_12 "imm >= 0 && imm <= 0b111111111111" 15 | imm_18 "imm >= 0 && imm <= 0b111111111111111111" 16 | imm_nz "imm != 0" 17 | imm_x2 "(imm & 0b1) == 0" 18 | imm_x4 "(imm & 0b11) == 0" 19 | imm_x8 "(imm & 0b111) == 0" 20 | imm_x16 "(imm & 0b1111) == 0" 21 | rd_b3 "rd >= 8 && rd <= 15" 22 | rs1_b3 "rs1 >= 8 && rs1 <= 15" 23 | rs2_b3 "rs2 >= 8 && rs2 <= 15" 24 | rd_eq_rs1 "rd == rs1" 25 | rd_eq_ra "rd == 1" "rd=1" 26 | rd_eq_sp "rd == 2" "rd=2" 27 | rd_eq_x0 "rd == 0" "rd=0" 28 | rs1_eq_sp "rs1 == 2" 29 | rs1_eq_x0 "rs1 == 0" 30 | rs2_eq_x0 "rs2 == 0" "rs2=0" 31 | rd_ne_x0_x2 "rd != 0 && rd != 2" "rd≠{0,2}" 32 | rd_ne_x0 "rd != 0" "rd≠0" 33 | rs1_ne_x0 "rs1 != 0" 34 | rs2_ne_x0 "rs2 != 0" "rs2≠0" 35 | rs2_eq_rs1 "rs2 == rs1" 36 | rs1_eq_ra "rs1 == 1" 37 | imm_eq_zero "imm == 0" 38 | imm_eq_n1 "imm == -1" 39 | imm_eq_p1 "imm == 1" 40 | csr_eq_0x001 "imm == 0x001" 41 | csr_eq_0x002 "imm == 0x002" 42 | csr_eq_0x003 "imm == 0x003" 43 | csr_eq_0xc00 "imm == 0xc00" 44 | csr_eq_0xc01 "imm == 0xc01" 45 | csr_eq_0xc02 "imm == 0xc02" 46 | csr_eq_0xc80 "imm == 0xc80" 47 | csr_eq_0xc81 "imm == 0xc81" 48 | csr_eq_0xc82 "imm == 0xc82" 49 | -------------------------------------------------------------------------------- /csr-fields: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # "" 3 | # 4 | 5 | # machine status 6 | status ie 0 m "Interrupt Enable Stack 0" 1.7 7 | status prv 2:1 m "Privilege Mode Stack 0" 1.7 8 | status ie1 3 m "Interrupt Enable Stack 1" 1.7 9 | status prv1 5:4 m "Privilege Mode Stack 1" 1.7 10 | status ie2 6 m "Interrupt Enable Stack 2" 1.7 11 | status prv2 8:7 m "Privilege Mode Stack 2" 1.7 12 | status ie3 9 m "Interrupt Enable Stack 3" 1.7 13 | status prv3 11:10 m "Privilege Mode Stack 3" 1.7 14 | status fs 13:12 mhs "FPU register status" 1.7 15 | status xs 15:14 mhs "Extension status" 1.7 16 | status mprv 16 m "Data access at prv1 privilege level" 1.7 17 | status vm 21:17 m "Virtual Memory Mode" 1.7 18 | status uie 0 mhsu "User mode Interrupt Enable" 1.9- 19 | status sie 1 mhs "Supervisor mode Interrupt Enable" 1.9- 20 | status hie 2 mh "Hypervisor mode Interrupt Enable" 1.9- 21 | status mie 3 m "Machine mode Interrupt Enable" 1.9- 22 | status upie 4 mhsu "Prior User mode Interrupt Enable" 1.9- 23 | status spie 5 mhs "Prior Supervisor mode Interrupt Enable" 1.9- 24 | status hpie 6 mh "Prior Hypervisor mode Interrupt Enable" 1.9- 25 | status mpie 7 m "Prior Machine mode Interrupt Enable" 1.9- 26 | status spp 8 mhs "SRET pop privilege" 1.9- 27 | status hpp 10:9 mh "HRET pop privilege" 1.9- 28 | status mpp 12:11 m "MRET pop privilege" 1.9- 29 | status fs 14:13 mhs "FPU register status" 1.9- 30 | status xs 16:15 mhs "Extension status" 1.9- 31 | status mprv 17 m "Data access at mpp privilege level" 1.9- 32 | status pum 18 mhs "Protect User Memory" 1.9-1.9.1 33 | status sum 18 mhs "Supervisor User Memory" 1.10- 34 | status mxr 19 m "Make eXecute Readable" 1.9- 35 | status tvm 20 mhs "Trap Virtual Memory" 1.10- 36 | status tw 21 mhs "Timeout Wait" 1.10- 37 | status tsr 22 mhs "Trap SRET" 1.10- 38 | status vm 28:24 m "Virtual Memory Mode" 1.9-1.9.1 39 | 40 | # address translation 41 | ptbr base 31:12 s "Page Table Base Register" 1.7,rv32 42 | ptbr base 63:12 s "Page Table Base Register" 1.7,rv64 43 | ptbr ppn 21:0 s "Page Table Base Register (PPN)" 1.9-1.9.1,rv32 44 | ptbr asid 31:22 s "Page Table Base Register (ASID)" 1.9-1.9.1,rv32 45 | ptbr ppn 37:0 s "Page Table Base Register (PPN)" 1.9-1.9.1,rv64 46 | ptbr asid 63:38 s "Page Table Base Register (ASID)" 1.9-1.9.1,rv64 47 | atp ppn 21:0 s "Address Translation Register (PPN)" 1.10,rv32 48 | atp asid 30:22 s "Address Translation Register (ASID)" 1.10,rv32 49 | atp mode 31 s "Address Translation Register (Mode)" 1.10,rv32 50 | atp ppn 43:0 s "Address Translation Register (PPN)" 1.10,rv64 51 | atp asid 59:44 s "Address Translation Register (ASID)" 1.10,rv64 52 | atp mode 63:60 s "Address Translation Register (Mode)" 1.10,rv64 53 | 54 | # machine interrupt pending 55 | ip usip 0 mhsu "User Software Interrupt Pending" 1.9- 56 | ip ssip 1 mhs "Supervisor Software Interrupt Pending" 1.9- 57 | ip hsip 2 mh "Hypervisor Software Interrupt Pending" 1.9- 58 | ip msip 3 m "Machine Software Interrupt Pending" 1.9- 59 | ip utip 4 mhsu "User Timer Interrupt Pending" 1.9- 60 | ip stip 5 mhs "Supervisor Timer Interrupt Pending" 1.9- 61 | ip htip 6 mh "Hypervisor Timer Interrupt Pending" 1.9- 62 | ip mtip 7 m "Machine Timer Interrupt Pending" 1.9- 63 | ip ueip 8 mhsu "User External Interrupt Pending" 1.9- 64 | ip seip 9 mhs "Supervisor External Interrupt Pending" 1.9- 65 | ip heip 10 mh "Hypervisor External Interrupt Pending" 1.9- 66 | ip meip 11 m "Machine External Interrupt Pending" 1.9- 67 | 68 | # machine interrupt enable 69 | ie usie 0 mhsu "User Software Interrupt Enable" 1.9- 70 | ie ssie 1 mhs "Supervisor Software Interrupt Enable" 1.9- 71 | ie hsie 2 mh "Hypervisor Software Interrupt Enable" 1.9- 72 | ie msie 3 m "Machine Software Interrupt Enable" 1.9- 73 | ie utie 4 mhsu "User Timer Interrupt Enable" 1.9- 74 | ie stie 5 mhs "Supervisor Timer Interrupt Enable" 1.9- 75 | ie htie 6 mh "Hypervisor Timer Interrupt Enable" 1.9- 76 | ie mtie 7 m "Machine Timer Interrupt Enable" 1.9- 77 | ie ueie 8 mhsu "User External Interrupt Enable" 1.9- 78 | ie seie 9 mhs "Supervisor External Interrupt Enable" 1.9- 79 | ie heie 10 mh "Hypervisor External Interrupt Enable" 1.9- 80 | ie meie 11 m "Machine External Interrupt Enable" 1.9- 81 | -------------------------------------------------------------------------------- /csrs: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # "" 3 | # 4 | # is one of urw, uro, srw, sro, hrw, hro, mrw, mro 5 | # 6 | # is [introduced]-[deprecated] 7 | 8 | # User Trap Setup 9 | 0x000 urw ustatus "User status register" 1.9- 10 | 0x004 urw uie "User interrupt-enable register" 1.9- 11 | 0x005 urw utvec "User trap handler base address" 1.9- 12 | 13 | # User Trap Handling 14 | 0x040 urw uscratch "Scratch handler for user trap handlers" 1.9- 15 | 0x041 urw uepc "User exception program counter" 1.9- 16 | 0x042 urw ucause "User trap cause" 1.9- 17 | 0x043 urw ubadaddr "User bad address" 1.7-1.9.1 18 | 0x043 urw utval "User bad address or instruction" 1.10- 19 | 0x044 urw uip "User interrupt pending" 1.9- 20 | 21 | # User Floating-Point CSRs 22 | 0x001 urw fflags "Floating-Point Accrued Exceptions" 1.7- 23 | 0x002 urw frm "Floating-Point Dynamic Rounding Mode" 1.7- 24 | 0x003 urw fcsr "Floating-Point Control and Status (frm + fflags)" 1.7- 25 | 26 | # User Timers and Counters 27 | 0xC00 uro cycle "Cycle counter (for RDCYCLE)" 1.7- 28 | 0xC01 uro time "Wall-clock time (for RDTIME)" 1.7- 29 | 0xC02 uro instret "Instructions-retired counter (for RDINSTRET)" 1.7- 30 | 0xC80 uro cycleh "Upper 32 bits of cycle, RV32I only" 1.7-,rv32 31 | 0xC81 uro timeh "Upper 32 bits of time, RV32I only" 1.7-,rv32 32 | 0xC82 uro instreth "Upper 32 bits of instret, RV32I only" 1.7-,rv32 33 | 34 | # Supervisor Trap Setup 35 | 0x100 srw sstatus "Supervisor status register" 1.7- 36 | 0x102 srw sedeleg "Supervisor exception delegation register" 1.9- 37 | 0x103 srw sideleg "Supervisor interrupt delegation register" 1.9- 38 | 0x104 src sie "Supervisor interrupt-enable register" 1.7- 39 | 0x105 srw stvec "Supervisor trap handler base address" 1.7- 40 | 0x106 swr scounteren "Supervisor counter enable" 1.10- 41 | 42 | # Supervisor Trap Handling 43 | 0x140 srw sscratch "Scratch register for supervisor trap handlers" 1.7- 44 | 0x141 srw sepc "Supervisor exception program counter" 1.7- 45 | 0x142 srw scause "Supervisor trap cause" 1.7- 46 | 0x143 srw sbadaddr "Supervisor bad address" 1.7-1.9.1 47 | 0x143 srw stval "Supervisor bad address or instruction" 1.10- 48 | 0x144 srw sip "Supervisor interrupt pending" 1.7- 49 | 50 | # Supervisor Protection and Translation 51 | 0x180 srw sptbr "Page-table base register" 1.7-1.9.1 52 | 0x180 srw satp "Supervisor address translation and protection" 1.10- 53 | 54 | # Supervisor Timers and Counters 55 | 0xD00 sro scycle "Supervisor cycle counter" 1.9- 56 | 0xD01 sro stime "Supervisor wall-clock time" 1.7-1.9 57 | 0xD02 sro sinstret "Supervisor instructions-retired counter" 1.9- 58 | 0xD80 sro scycleh "Upper 32 bits of scycle, RV32I only" 1.9-,rv32 59 | 0xD81 sro stimeh "Upper 32 bits of stime, RV32I only" 1.7-,rv32 60 | 0xD82 sro sinstreth "Upper 32 bits of sinstret, RV32I only" 1.9-,rv32 61 | 62 | # Hypervisor Trap Setup 63 | 0x200 hrw hstatus "Hypervisor status register" 1.7-1.9.1 64 | 0x202 mrw hedeleg "Hypervisor exception delegation register" 1.9-1.9.1 65 | 0x203 mrw hideleg "Hypervisor interrupt delegation register" 1.9-1.9.1 66 | 0x204 mrw hie "Hypervisor interrupt-enable register" 1.7-1.9.1 67 | 0x205 hrw htvec "Hypervisor trap handler base address" 1.7-1.9.1 68 | 69 | # Hypervisor Trap Handling 70 | 0x240 hrw hscratch "Scratch register for hypervisor trap handlers" 1.7-1.9.1 71 | 0x241 hrw hepc "Hypervisor exception program counter" 1.7-1.9.1 72 | 0x242 hrw hcause "Hypervisor trap cause" 1.7-1.9.1 73 | 0x243 hrw hbadaddr "Hypervisor bad address" 1.7-1.9.1 74 | 0x244 hrw hip "Hypervisor interrupt pending" 1.7-1.9.1 75 | 76 | # Hypervisor Protection and Translation 77 | 78 | # Hypervisor Timers and Counters 79 | 0xE00 sro hcycle "Hypervisor cycle counter" 1.7-1.9.1 80 | 0xE01 sro htime "Hypervisor wall-clock time" 1.7-1.9 81 | 0xE02 sro hinstret "Hypervisor instructions-retired counter" 1.9-1.9.1 82 | 0xE80 sro hcycleh "Upper 32 bits of hcycle, RV32I only" 1.7-1.9.1,rv32 83 | 0xE81 sro htimeh "Upper 32 bits of htime, RV32I only" 1.7-1.9,rv32 84 | 0xE82 sro hinstreth "Upper 32 bits of hinstret, RV32I only" 1.9-1.9.1,rv32 85 | 86 | # Machine Information Registers 87 | 0xF11 mro mvendorid "Vendor ID" 1.9- 88 | 0xF12 mro marchid "Architecture ID" 1.9- 89 | 0xF13 mro mimpid "Implementation ID" 1.9- 90 | 0xF14 mro mhartid "Hardware thread ID" 1.7- 91 | 92 | # Machine Trap Setup 93 | 0x300 mrw mstatus "Machine status register" 1.7- 94 | 0x301 mrw misa "ISA and extensions supported" 1.7- 95 | 0x302 mrw medeleg "Machine exception delegation register" 1.9- 96 | 0x303 mrw mideleg "Machine interrupt delegation register" 1.9- 97 | 0x304 mrw mie "Machine interrupt-enable register" 1.7- 98 | 0x305 mrw mtvec "Machine trap-handler base address" 1.7- 99 | 0x306 mrw mcounteren "Machine counter enable" 1.10- 100 | 101 | # Machine Trap Handling 102 | 0x340 mrw mscratch "Scratch register for machine trap handlers" 1.7- 103 | 0x341 mrw mepc "Machine exception program counter" 1.7- 104 | 0x342 mrw mcause "Machine trap cause" 1.7- 105 | 0x343 mrw mbadaddr "Machine bad address" 1.7-1.9.1 106 | 0x343 mrw mtval "Machine bad address or instruction" 1.10- 107 | 0x344 mrw mip "Machine interrupt pending" 1.7- 108 | 0x3A0 mrw pmpcfg0 "Physical memory protection configuration" 1.10- 109 | 0x3A1 mrw pmpcfg1 "Physical memory protection configuration (RV32 only)" 1.10- 110 | 0x3A2 mrw pmpcfg2 "Physical memory protection configuration" 1.10- 111 | 0x3A3 mrw pmpcfg3 "Physical memory protection configuration (RV32 only)" 1.10- 112 | 0x3B0 mrw pmpaddr0 "Physical memory protection address register" 1.10- 113 | 0x3B1 mrw pmpaddr1 "Physical memory protection address register" 1.10- 114 | 0x3B2 mrw pmpaddr2 "Physical memory protection address register" 1.10- 115 | 0x3B3 mrw pmpaddr3 "Physical memory protection address register" 1.10- 116 | 0x3B4 mrw pmpaddr4 "Physical memory protection address register" 1.10- 117 | 0x3B5 mrw pmpaddr5 "Physical memory protection address register" 1.10- 118 | 0x3B6 mrw pmpaddr6 "Physical memory protection address register" 1.10- 119 | 0x3B7 mrw pmpaddr7 "Physical memory protection address register" 1.10- 120 | 0x3B8 mrw pmpaddr8 "Physical memory protection address register" 1.10- 121 | 0x3B9 mrw pmpaddr9 "Physical memory protection address register" 1.10- 122 | 0x3BA mrw pmpaddr10 "Physical memory protection address register" 1.10- 123 | 0x3BB mrw pmpaddr11 "Physical memory protection address register" 1.10- 124 | 0x3BC mrw pmpaddr12 "Physical memory protection address register" 1.10- 125 | 0x3BE mrw pmpaddr13 "Physical memory protection address register" 1.10- 126 | 0x3BD mrw pmpaddr14 "Physical memory protection address register" 1.10- 127 | 0x3BF mrw pmpaddr15 "Physical memory protection address register" 1.10- 128 | 129 | # Machine Protection and Translation 130 | 0x380 mrw mbase "Base register" 1.7- 131 | 0x381 mrw mbound "Bound register" 1.7- 132 | 0x382 mrw mibase "Instruction base register" 1.7- 133 | 0x383 mrw mibound "Instruction bound register" 1.7- 134 | 0x384 mrw mdbase "Data base register" 1.7- 135 | 0x385 mrw mdbound "Data bound register" 1.7- 136 | 137 | # Machine Counters / Timers 138 | 0xB00 mrw mcycle "Machine cycle counter" 1.7- 139 | 0xB01 mrw mtime "Machine wall-clock time" 1.7-1.9 140 | 0xB02 mrw minstret "Machine instructions-retired counter" 1.7- 141 | 0xB03 mrw mhpmcounter3 "Machine performance-monitoring counter" 1.9.1- 142 | 0xB04 mrw mhpmcounter4 "Machine performance-monitoring counter" 1.9.1- 143 | 0xB05 mrw mhpmcounter5 "Machine performance-monitoring counter" 1.9.1- 144 | 0xB06 mrw mhpmcounter6 "Machine performance-monitoring counter" 1.9.1- 145 | 0xB07 mrw mhpmcounter7 "Machine performance-monitoring counter" 1.9.1- 146 | 0xB08 mrw mhpmcounter8 "Machine performance-monitoring counter" 1.9.1- 147 | 0xB09 mrw mhpmcounter9 "Machine performance-monitoring counter" 1.9.1- 148 | 0xB0A mrw mhpmcounter10 "Machine performance-monitoring counter" 1.9.1- 149 | 0xB0B mrw mhpmcounter11 "Machine performance-monitoring counter" 1.9.1- 150 | 0xB0C mrw mhpmcounter12 "Machine performance-monitoring counter" 1.9.1- 151 | 0xB0D mrw mhpmcounter13 "Machine performance-monitoring counter" 1.9.1- 152 | 0xB0E mrw mhpmcounter14 "Machine performance-monitoring counter" 1.9.1- 153 | 0xB0F mrw mhpmcounter15 "Machine performance-monitoring counter" 1.9.1- 154 | 0xB10 mrw mhpmcounter16 "Machine performance-monitoring counter" 1.9.1- 155 | 0xB11 mrw mhpmcounter17 "Machine performance-monitoring counter" 1.9.1- 156 | 0xB12 mrw mhpmcounter18 "Machine performance-monitoring counter" 1.9.1- 157 | 0xB13 mrw mhpmcounter19 "Machine performance-monitoring counter" 1.9.1- 158 | 0xB14 mrw mhpmcounter20 "Machine performance-monitoring counter" 1.9.1- 159 | 0xB15 mrw mhpmcounter21 "Machine performance-monitoring counter" 1.9.1- 160 | 0xB16 mrw mhpmcounter22 "Machine performance-monitoring counter" 1.9.1- 161 | 0xB17 mrw mhpmcounter23 "Machine performance-monitoring counter" 1.9.1- 162 | 0xB18 mrw mhpmcounter24 "Machine performance-monitoring counter" 1.9.1- 163 | 0xB19 mrw mhpmcounter25 "Machine performance-monitoring counter" 1.9.1- 164 | 0xB1A mrw mhpmcounter26 "Machine performance-monitoring counter" 1.9.1- 165 | 0xB1B mrw mhpmcounter27 "Machine performance-monitoring counter" 1.9.1- 166 | 0xB1C mrw mhpmcounter28 "Machine performance-monitoring counter" 1.9.1- 167 | 0xB1D mrw mhpmcounter29 "Machine performance-monitoring counter" 1.9.1- 168 | 0xB1E mrw mhpmcounter30 "Machine performance-monitoring counter" 1.9.1- 169 | 0xB1F mrw mhpmcounter31 "Machine performance-monitoring counter" 1.9.1- 170 | 0xB80 mrw mcycleh "Upper 32 bits of mcycle, RV32I only" 1.7-,rv32 171 | 0xB81 mrw mtimeh "Upper 32 bits of mtime, RV32I only" 1.7-1.9,rv32 172 | 0xB82 mrw minstreth "Upper 32 bits of minstret, RV32I only" 1.7-,rv32 173 | 0xB83 mrw mhpmcounter3h "Upper 32 bits of mhpmcounter3, RV32I only" 1.9.1- 174 | 0xB84 mrw mhpmcounter4h "Upper 32 bits of mhpmcounter4, RV32I only" 1.9.1- 175 | 0xB85 mrw mhpmcounter5h "Upper 32 bits of mhpmcounter5, RV32I only" 1.9.1- 176 | 0xB86 mrw mhpmcounter6h "Upper 32 bits of mhpmcounter6, RV32I only" 1.9.1- 177 | 0xB87 mrw mhpmcounter7h "Upper 32 bits of mhpmcounter7, RV32I only" 1.9.1- 178 | 0xB88 mrw mhpmcounter8h "Upper 32 bits of mhpmcounter8, RV32I only" 1.9.1- 179 | 0xB89 mrw mhpmcounter9h "Upper 32 bits of mhpmcounter9, RV32I only" 1.9.1- 180 | 0xB8A mrw mhpmcounter10h "Upper 32 bits of mhpmcounter10, RV32I only" 1.9.1- 181 | 0xB8B mrw mhpmcounter11h "Upper 32 bits of mhpmcounter11, RV32I only" 1.9.1- 182 | 0xB8C mrw mhpmcounter12h "Upper 32 bits of mhpmcounter12, RV32I only" 1.9.1- 183 | 0xB8D mrw mhpmcounter13h "Upper 32 bits of mhpmcounter13, RV32I only" 1.9.1- 184 | 0xB8E mrw mhpmcounter14h "Upper 32 bits of mhpmcounter14, RV32I only" 1.9.1- 185 | 0xB8F mrw mhpmcounter15h "Upper 32 bits of mhpmcounter15, RV32I only" 1.9.1- 186 | 0xB90 mrw mhpmcounter16h "Upper 32 bits of mhpmcounter16, RV32I only" 1.9.1- 187 | 0xB91 mrw mhpmcounter17h "Upper 32 bits of mhpmcounter17, RV32I only" 1.9.1- 188 | 0xB92 mrw mhpmcounter18h "Upper 32 bits of mhpmcounter18, RV32I only" 1.9.1- 189 | 0xB93 mrw mhpmcounter19h "Upper 32 bits of mhpmcounter19, RV32I only" 1.9.1- 190 | 0xB94 mrw mhpmcounter20h "Upper 32 bits of mhpmcounter20, RV32I only" 1.9.1- 191 | 0xB95 mrw mhpmcounter21h "Upper 32 bits of mhpmcounter21, RV32I only" 1.9.1- 192 | 0xB96 mrw mhpmcounter22h "Upper 32 bits of mhpmcounter22, RV32I only" 1.9.1- 193 | 0xB97 mrw mhpmcounter23h "Upper 32 bits of mhpmcounter23, RV32I only" 1.9.1- 194 | 0xB98 mrw mhpmcounter24h "Upper 32 bits of mhpmcounter24, RV32I only" 1.9.1- 195 | 0xB99 mrw mhpmcounter25h "Upper 32 bits of mhpmcounter25, RV32I only" 1.9.1- 196 | 0xB9A mrw mhpmcounter26h "Upper 32 bits of mhpmcounter26, RV32I only" 1.9.1- 197 | 0xB9B mrw mhpmcounter27h "Upper 32 bits of mhpmcounter27, RV32I only" 1.9.1- 198 | 0xB9C mrw mhpmcounter28h "Upper 32 bits of mhpmcounter28, RV32I only" 1.9.1- 199 | 0xB9D mrw mhpmcounter29h "Upper 32 bits of mhpmcounter29, RV32I only" 1.9.1- 200 | 0xB9E mrw mhpmcounter30h "Upper 32 bits of mhpmcounter30, RV32I only" 1.9.1- 201 | 0xB9F mrw mhpmcounter31h "Upper 32 bits of mhpmcounter31, RV32I only" 1.9.1- 202 | 203 | # Machine Counter Setup 204 | 0x320 mrw mucounteren "Machine interrupt-enable register" 1.9-1.9.1 205 | 0x321 mrw mscounteren "Supervisor-mode counter enable" 1.9-1.9.1 206 | 0x322 mrw mhcounteren "Hypervisor-mode counter enable" 1.9-1.9.1 207 | 0x323 mrw mhpmevent3 "Machine performance-monitoring event selector" 1.9.1- 208 | 0x324 mrw mhpmevent4 "Machine performance-monitoring event selector" 1.9.1- 209 | 0x325 mrw mhpmevent5 "Machine performance-monitoring event selector" 1.9.1- 210 | 0x326 mrw mhpmevent6 "Machine performance-monitoring event selector" 1.9.1- 211 | 0x327 mrw mhpmevent7 "Machine performance-monitoring event selector" 1.9.1- 212 | 0x328 mrw mhpmevent8 "Machine performance-monitoring event selector" 1.9.1- 213 | 0x329 mrw mhpmevent9 "Machine performance-monitoring event selector" 1.9.1- 214 | 0x32A mrw mhpmevent10 "Machine performance-monitoring event selector" 1.9.1- 215 | 0x32B mrw mhpmevent11 "Machine performance-monitoring event selector" 1.9.1- 216 | 0x32C mrw mhpmevent12 "Machine performance-monitoring event selector" 1.9.1- 217 | 0x32D mrw mhpmevent13 "Machine performance-monitoring event selector" 1.9.1- 218 | 0x32E mrw mhpmevent14 "Machine performance-monitoring event selector" 1.9.1- 219 | 0x32F mrw mhpmevent15 "Machine performance-monitoring event selector" 1.9.1- 220 | 0x330 mrw mhpmevent16 "Machine performance-monitoring event selector" 1.9.1- 221 | 0x331 mrw mhpmevent17 "Machine performance-monitoring event selector" 1.9.1- 222 | 0x332 mrw mhpmevent18 "Machine performance-monitoring event selector" 1.9.1- 223 | 0x333 mrw mhpmevent19 "Machine performance-monitoring event selector" 1.9.1- 224 | 0x334 mrw mhpmevent20 "Machine performance-monitoring event selector" 1.9.1- 225 | 0x335 mrw mhpmevent21 "Machine performance-monitoring event selector" 1.9.1- 226 | 0x336 mrw mhpmevent22 "Machine performance-monitoring event selector" 1.9.1- 227 | 0x337 mrw mhpmevent23 "Machine performance-monitoring event selector" 1.9.1- 228 | 0x338 mrw mhpmevent24 "Machine performance-monitoring event selector" 1.9.1- 229 | 0x339 mrw mhpmevent25 "Machine performance-monitoring event selector" 1.9.1- 230 | 0x33A mrw mhpmevent26 "Machine performance-monitoring event selector" 1.9.1- 231 | 0x33B mrw mhpmevent27 "Machine performance-monitoring event selector" 1.9.1- 232 | 0x33C mrw mhpmevent28 "Machine performance-monitoring event selector" 1.9.1- 233 | 0x33D mrw mhpmevent29 "Machine performance-monitoring event selector" 1.9.1- 234 | 0x33E mrw mhpmevent30 "Machine performance-monitoring event selector" 1.9.1- 235 | 0x33F mrw mhpmevent31 "Machine performance-monitoring event selector" 1.9.1- 236 | 237 | # Debug/Trace Registers (shared with Debug Mode) 238 | 0x7A0 mrw tselect "Debug/Trace trigger register select" 1.9.1- 239 | 0x7A1 mrw tdata1 "First Debug/Trace trigger data register" 1.9.1- 240 | 0x7A2 mrw tdata2 "Second Debug/Trace trigger data register" 1.9.1- 241 | 0x7A3 mrw tdata3 "Third Debug/Trace trigger data register" 1.9.1- 242 | 243 | # Debug Mode Registers 244 | 0x7B0 mrw dcsr "Debug control and status register" 1.9.1- 245 | 0x7B1 mrw dpc "Debug program counter" 1.9.1- 246 | 0x7B2 mrw dscratch "Debug scratch register" 1.9.1- 247 | 248 | # Nonstandard 249 | 0x780 mrw mtohost "IO to Host" 1.7- 250 | 0x781 mrw mfromhost "IO from Host" 1.7- 251 | 0x782 mrw mreset "Reset" 1.7- 252 | 0x783 mrw mipi "Inter Processor Interrupt" 1.7- 253 | 0x784 mrw miobase "IO Base" 1.7- 254 | -------------------------------------------------------------------------------- /enums: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # "" 3 | 4 | # Types 5 | type none 0 "None" 1.7- 6 | type arg 1 "Argument" 1.7- 7 | type creg 2 "Compressed Register" 1.7- 8 | type ireg 3 "Integer Register" 1.7- 9 | type freg 4 "Floating Point Register" 1.7- 10 | type offset 5 "Signed Offset" 1.7- 11 | type simm 6 "Sign Extended Immediate" 1.7- 12 | type uimm 7 "Zero Extended Immediate" 1.7- 13 | 14 | # Round Mode 15 | rm rne 0b000 "Round to Nearest, ties to Even" 1.7- 16 | rm rtz 0b001 "Round towards Zero" 1.7- 17 | rm rdn 0b010 "Round Down (towards -∞)" 1.7- 18 | rm rup 0b011 "Round Up (towards +∞)" 1.7- 19 | rm rmm 0b100 "Round to Nearest, ties to Max Magnitude" 1.7- 20 | rm dyn 0b111 "Dynamic Rounding Mode" 1.7- 21 | 22 | # Memory order (AMO aqrl argument) 23 | aqrl relaxed 0 "Atomicity - no explicit ordering" 1.7- 24 | aqrl acquire 2 "Acquire - prior writes from other harts visible" 1.7- 25 | aqrl release 1 "Release - subsequent reads visible to other harts" 1.7- 26 | aqrl acq_rel 3 "Acquire-Release - global order of reads and writes" 1.7- 27 | 28 | # Fence (pred and succ values) 29 | fence i 8 "Input" 1.7- 30 | fence o 4 "Output" 1.7- 31 | fence r 2 "Read" 1.7- 32 | fence w 1 "Write" 1.7- 33 | 34 | # Floating Point Exception Register (fcsr) 35 | fcsr NX 1 "Inexact" 1.7- 36 | fcsr UF 2 "Underflow" 1.7- 37 | fcsr OF 4 "Overflow" 1.7- 38 | fcsr DZ 8 "Divide by Zero" 1.7- 39 | fcsr NV 16 "Invalid Operation" 1.7- 40 | 41 | # Floating Point types returned by fclass 42 | fclass neg_inf 1 "negative infinity" 1.7- 43 | fclass neg_norm 2 "negative normal number" 1.7- 44 | fclass neg_subnorm 4 "negative subnormal number" 1.7- 45 | fclass neg_zero 8 "negative zero" 1.7- 46 | fclass pos_zero 16 "positive zero" 1.7- 47 | fclass pos_subnorm 32 "positive subnormal number" 1.7- 48 | fclass pos_norm 64 "positive normal number" 1.7- 49 | fclass pos_inf 128 "positive infinity" 1.7- 50 | fclass signaling_nan 256 "signaling NaN" 1.7- 51 | fclass quiet_nan 512 "quiet NaN" 1.7- 52 | 53 | # FPU Status (mstatus.fs) 54 | fs off 0 "Off" 1.7- 55 | fs initial 1 "Initial" 1.7- 56 | fs clean 2 "Clean" 1.7- 57 | fs dirty 3 "Dirty" 1.7- 58 | 59 | # Extension Status (mstatus.xs) 60 | xs all 0 "All off" 1.7- 61 | xs initial 1 "None dirty or clean, some on" 1.7- 62 | xs clean 2 "None dirty, some clean" 1.7- 63 | xs dirty 3 "Some dirty" 1.7- 64 | 65 | # Base ISA field (misa) 66 | isa rv32 1 "RV32" 1.7- 67 | isa rv64 2 "RV64" 1.7- 68 | isa rv128 3 "RV128" 1.7- 69 | 70 | # ISA Extensions (misa) 71 | ext I 256 "RV32I/64I/128I Base ISA" 1.7- 72 | ext M 4096 "Integer Multiply/Divide extension" 1.7- 73 | ext A 1 "Atomic Extension" 1.7- 74 | ext F 32 "Single-precision foating-point extension" 1.7- 75 | ext D 8 "Double-precision foating-point extension" 1.7- 76 | ext C 4 "Compressed extension" 1.7- 77 | 78 | # Privilege mode 79 | mode U 0 "User mode" 1.7- 80 | mode S 1 "Supervisor mode" 1.7- 81 | mode H 2 "Hypervisor mode" 1.7- 82 | mode M 3 "Machine mode" 1.7- 83 | 84 | # Virtualization Management field (mstatus.vm) 85 | vm mbare 0 "No translation or protection" 1.7-1.9.1 86 | vm mbb 1 "Single base-and-bound" 1.7-1.9.1 87 | vm mbid 2 "Separate instruction and data base-and-bound" 1.7-1.9.1 88 | vm sv32 8 "Page-based 32-bit virtual addressing" 1.7-1.9.1 89 | vm sv39 9 "Page-based 39-bit virtual addressing" 1.7-1.9.1 90 | vm sv48 10 "Page-based 48-bit virtual addressing" 1.7-1.9.1 91 | vm sv57 11 "Reserved for page-based 48-bit virtual addressing" 1.7-1.9.1 92 | vm sv64 12 "Reserved for page-based 48-bit virtual addressing" 1.7-1.9.1 93 | 94 | # Virtualization Management field (satp.vm) 95 | svm mbare 0 "No translation or protection" 1.10 96 | svm sv32 1 "Page-based 32-bit virtual addressing" 1.10,rv32 97 | svm sv39 8 "Page-based 39-bit virtual addressing" 1.10,rv64 98 | svm sv48 9 "Page-based 48-bit virtual addressing" 1.10,rv64 99 | svm sv57 10 "Reserved for page-based 48-bit virtual addressing" 1.10,rv64 100 | svm sv64 11 "Reserved for page-based 48-bit virtual addressing" 1.10,rv64 101 | 102 | # Machine Cause Register faults (mcause), interrupt bit clear 103 | cause misaligned_fetch 0 "Instruction address misaligned" 1.7- 104 | cause fault_fetch 1 "Instruction access fault" 1.7- 105 | cause illegal_instruction 2 "Illegal instruction" 1.7- 106 | cause breakpoint 3 "Breakpoint" 1.7- 107 | cause misaligned_load 4 "Load address misaligned" 1.7- 108 | cause fault_load 5 "Load access fault" 1.7- 109 | cause misaligned_store 6 "Store/AMO address misaligned" 1.7- 110 | cause fault_store 7 "Store/AMO access fault" 1.7- 111 | cause user_ecall 8 "Environment call from U-mode" 1.7- 112 | cause supervisor_ecall 9 "Environment call from S-mode" 1.7- 113 | cause hypervisor_ecall 10 "Environment call from H-mode" 1.7-1.9.1 114 | cause machine_ecall 11 "Environment call from M-mode" 1.7- 115 | cause exec_page_fault 12 "Instruction page fault" 1.10- 116 | cause load_page_fault 13 "Load page fault" 1.10- 117 | cause store_page_fault 15 "Store/AMO page fault" 1.10- 118 | 119 | # Machine Cause Register interrupts (mcause) interrupt bit set 120 | intr u_software 0 "User software interrupt" 1.7- 121 | intr s_software 1 "Supervisor software interrupt" 1.7- 122 | intr h_software 2 "Hypervisor software interrupt" 1.7-1.9.1 123 | intr m_software 3 "Machine software interrupt" 1.7-1.9.1 124 | intr u_timer 4 "User timer interrupt" 1.7- 125 | intr s_timer 5 "Supervisor timer interrupt" 1.7- 126 | intr h_timer 6 "Hypervisor timer interrupt" 1.7-1.9.1 127 | intr m_timer 7 "Machine timer interrupt" 1.7-1.9.1 128 | intr u_external 8 "User external interrupt" 1.7- 129 | intr s_external 9 "Supervisor external interrupt" 1.7- 130 | intr h_external 10 "Hypervisor external interrupt" 1.7-1.9.1 131 | intr m_external 11 "Machine external interrupt" 1.7-1.9.1 132 | -------------------------------------------------------------------------------- /extensions: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # "" 3 | 4 | rv 32 i 32 "RV32I Base Integer Instruction Set" 5 | rv 64 i 32 "RV64I Base Integer Instruction Set (in addition to RV32I)" 6 | rv 128 i 32 "RV128I Base Integer Instruction Set (in addition to RV64I)" 7 | rv 32 m 32 "RV32M Standard Extension for Integer Multiply and Divide" 8 | rv 64 m 32 "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)" 9 | rv 128 m 32 "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)" 10 | rv 32 a 32 "RV32A Standard Extension for Atomic Instructions" 11 | rv 64 a 32 "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" 12 | rv 128 a 32 "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)" 13 | rv 32 s 32 "RV32S Standard Extension for Supervisor-level Instructions" 14 | rv 64 s 32 "RV64S Standard Extension for Supervisor-level Instructions" 15 | rv 128 s 32 "RV128S Standard Extension for Supervisor-level Instructions" 16 | rv 32 f 32 "RV32F Standard Extension for Single-Precision Floating-Point" 17 | rv 64 f 32 "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" 18 | rv 128 f 32 "RV128F Standard Extension for Single-Precision Floating-Point (in addition to RV64F)" 19 | rv 32 d 32 "RV32D Standard Extension for Double-Precision Floating-Point" 20 | rv 64 d 32 "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)" 21 | rv 128 d 32 "RV128D Standard Extension for Double-Precision Floating-Point (in addition to RV64D)" 22 | rv 32 q 32 "RV32Q Standard Extension for Quadruple-Precision Floating-Point" 23 | rv 64 q 32 "RV64Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV32Q)" 24 | rv 128 q 32 "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)" 25 | rv 32 c 16 "RV32C Standard Extension for Compressed Instructions" 26 | rv 64 c 16 "RV64C Standard Extension for Compressed Instructions (in addition to RV32C)" 27 | rv 128 c 16 "RV128C Standard Extension for Compressed Instructions (in addition to RV64C)" 28 | -------------------------------------------------------------------------------- /formats: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # 3 | 4 | none 5 | rs1 6 | pred,succ 7 | offset 8 | rs1,rs2 9 | rd,imm 10 | rd,offset 11 | rd,rs1,rs2 12 | frd,rs1 13 | rd,frs1 14 | rd,frs1,frs2 15 | frd,frs1,frs2 16 | rm,frd,frs1 17 | rm,frd,rs1 18 | rm,rd,frs1 19 | rm,frd,frs1,frs2 20 | rm,frd,frs1,frs2,frs3 21 | rd,rs1,imm 22 | rd,rs1,offset 23 | rd,offset(rs1) 24 | frd,offset(rs1) 25 | rd,csr,rs1 26 | rd,csr,zimm 27 | rs2,offset(rs1) 28 | frs2,offset(rs1) 29 | rs1,rs2,offset 30 | rs2,rs1,offset 31 | aqrl,rd,rs2,(rs1) 32 | aqrl,rd,(rs1) 33 | 34 | # pseudo opcode formats 35 | rd 36 | rd,zimm 37 | rd,rs1 38 | rd,rs2 39 | rs1,offset 40 | rs2,offset 41 | -------------------------------------------------------------------------------- /glossary: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # description> 3 | 4 | s8,b "Signed 8-bit Byte" 5 | u8,bu "Unsigned 8-bit Byte" 6 | s16,h "Signed 16-bit Word" 7 | u16,hu "Unsigned 16-bit Half Word" 8 | s32,w "Signed 32-bit Word" 9 | u32,wu "Unsigned 32-bit Word" 10 | s64,l,d "Signed 64-bit Word" 11 | u64,lu "Unsigned 64-bit Word" 12 | s128,c,q "Signed 128-bit Word" # c,cu are placeholders for fcvt 13 | u128,cu "Unsigned 128-bit Word" 14 | sx "Signed Full Width Word (32, 64 or 128-bit)" 15 | ux "Unsigned Full width Word (32, 64 or 128-bit)" 16 | 17 | f32,s "Single Precision Floating-point" 18 | f64,d "Double Precision Floating-point" 19 | f128,q "Quadruple Precision Floating-point" 20 | 21 | XLEN "Integer Register Width in Bits (32, 64 or 128)" 22 | FLEN "Floating-point Register Width in Bits (32, 64 or 128)" 23 | 24 | rd "Integer Register Destination" 25 | rs[n] "Integer Register Source [n]" 26 | 27 | frd "Floating-point Register Destination" 28 | frs[n] "Floating-point Register Source [n]" 29 | 30 | hart "hardware thread" 31 | pc "Program Counter" 32 | imm "Immediate Value encoded in an instruction" 33 | offset "Immediate Value decoded as a relative offset" 34 | shamt "Immediate Value decoded as a shift amount" 35 | 36 | SP "Single Precision" 37 | DP "Double Precision" 38 | QP "Quadruple Precision" 39 | 40 | M "Machine" 41 | U "User" 42 | S "Supervisor" 43 | H "Hypervisor" 44 | 45 | ABI "Application Binary Interface" 46 | AEE "Application Execution Environment" 47 | SBI "Supervisor Binary Interface" 48 | SEE "Supervisor Execution Environment" 49 | HBI "Hypervisor Binary Interface" 50 | HEE "Hypervisor Execution Environment" 51 | 52 | CSR "Control and Status Register" 53 | 54 | PA "Physical Address" 55 | VA "Virtual Address" 56 | PPN "Physical Page Number" 57 | 58 | ASID "Address Space Identifier" 59 | PDID "Protection Domain Identifier" 60 | PMA "Physical Memory Attribute" 61 | PMP "Physical Memory Protection" 62 | PPN "Physical Page Number" 63 | VPN "Virtual Page Number" 64 | VCLN "Virtual Cache Line Number" 65 | -------------------------------------------------------------------------------- /notation: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # 3 | 4 | = == 2 "Equal To" = 5 | ≠ != 2 "Not Equal To" \neq 6 | < < 2 "Less Than" < 7 | > > 2 "Greater Than" > 8 | ≤ <= 2 "Less Than Equal To" \leq 9 | ≥ >= 2 "Greater Than Equal To" \geq 10 | « << 2 "Shift Left" \ll 11 | » >> 2 "Shift Right" \gg 12 | ← = 2 "Assignment" \leftarrow 13 | ¬ ~ 1 "Bitwise Not" \neg 14 | ∧ & 2 "Bitwise And" \wedge 15 | ∨ | 2 "Bitwise Or" \vee 16 | ⊻ ^ 2 "Bitwise Xor" \oplus 17 | - - 1 "Arithmetic Negate" - 18 | - - 2 "Subtract" - 19 | + + 2 "Add" + 20 | × * 2 "Multiply" \times 21 | ÷ / 2 "Divide" \div 22 | ∥ , 2 "In Parallel" \parallel 23 | ; ; 2 "Statement Separator" , 24 | mod % 2 "Modulus" mod 25 | T[x] *(T*)(x) 1 "Memory Reference" T[x] 26 | T(x) T(x) 1 "Type Cast" T(x) 27 | f(x...) f(x...) n "Function Call" f(x...) 28 | ∞ inf 0 "Infinity" \infty 29 | -------------------------------------------------------------------------------- /opcode-classes: -------------------------------------------------------------------------------- 1 | # RV32I 2 | lui alu 3 | auipc alu 4 | jal jump 5 | jalr jump,indirect 6 | beq branch 7 | bne branch 8 | blt branch 9 | bge branch 10 | bltu branch 11 | bgeu branch 12 | lb load 13 | lh load 14 | lw load 15 | lbu load 16 | lhu load 17 | lwu load 18 | sb store 19 | sh store 20 | sw store 21 | addi alu 22 | slti alu 23 | sltiu alu 24 | xori alu 25 | ori alu 26 | andi alu 27 | slli alu 28 | srli alu 29 | srai alu 30 | add alu 31 | sub alu 32 | sll alu 33 | slt alu 34 | sltu alu 35 | xor alu 36 | srl alu 37 | sra alu 38 | or alu 39 | and alu 40 | fence fence 41 | fence.i fence 42 | 43 | # RV64I 44 | ld load 45 | sd store 46 | addiw alu 47 | slliw alu 48 | srliw alu 49 | sraiw alu 50 | addw alu 51 | subw alu 52 | sllw alu 53 | srlw alu 54 | sraw alu 55 | 56 | # RV32M 57 | mul alu,multiply 58 | mulh alu,multiply 59 | mulhsu alu,multiply 60 | mulhu alu,multiply 61 | div alu,divide 62 | divu alu,divide 63 | rem alu,divide 64 | remu alu,divide 65 | 66 | # RV64M 67 | mulw alu,multiply 68 | divw alu,multiply 69 | divuw alu,multiply 70 | remw alu,divide 71 | remuw alu,divide 72 | 73 | # RV32A "RV32A Standard Extension for Atomic Instructions" 74 | 75 | lr.w atomic 76 | sc.w atomic 77 | amoswap.w atomic 78 | amoadd.w atomic 79 | amoxor.w atomic 80 | amoor.w atomic 81 | amoand.w atomic 82 | amomin.w atomic 83 | amomax.w atomic 84 | amominu.w atomic 85 | amomaxu.w atomic 86 | 87 | # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" 88 | 89 | lr.d atomic 90 | sc.d atomic 91 | amoswap.d atomic 92 | amoadd.d atomic 93 | amoxor.d atomic 94 | amoor.d atomic 95 | amoand.d atomic 96 | amomin.d atomic 97 | amomax.d atomic 98 | amominu.d atomic 99 | amomaxu.d atomic 100 | 101 | # RV32S "RV32S Standard Extension for Supervisor-level Instructions" 102 | 103 | ecall system 104 | ebreak system 105 | uret system 106 | sret system 107 | hret system 108 | mret system 109 | dret system 110 | sfence.vm system 111 | wfi system 112 | rdcycle csr 113 | rdtime csr 114 | rdinstret csr 115 | rdcycleh csr 116 | rdtimeh csr 117 | rdinstreth csr 118 | csrrw csr 119 | csrrs csr 120 | csrrc csr 121 | csrrwi csr 122 | csrrsi csr 123 | csrrci csr 124 | 125 | # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" 126 | 127 | flw fpu,load 128 | fsw fpu,store 129 | fmadd.s fpu,fma 130 | fmsub.s fpu,fma 131 | fnmadd.s fpu,fma 132 | fnmsub.s fpu,fma 133 | fadd.s fpu 134 | fsub.s fpu 135 | fmul.s fpu 136 | fdiv.s fpu,fdiv 137 | fsgnj.s fpu 138 | fsgnjn.s fpu 139 | fsgnjx.s fpu 140 | fmin.s fpu 141 | fmax.s fpu 142 | fsqrt.s fpu,fsqrt 143 | fle.s fpu 144 | flt.s fpu 145 | feq.s fpu 146 | fcvt.w.s fpu,fcvt 147 | fcvt.wu.s fpu,fcvt 148 | fcvt.s.w fpu,fcvt 149 | fcvt.s.wu fpu,fcvt 150 | fmv.x.s fpu,fmove 151 | fclass.s fpu 152 | fmv.s.x fpu,fmove 153 | 154 | # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" 155 | 156 | fcvt.l.s fpu,fcvt 157 | fcvt.lu.s fpu,fcvt 158 | fcvt.s.l fpu,fcvt 159 | fcvt.s.lu fpu,fcvt 160 | 161 | # RV32D "RV32D Standard Extension for Double-Precision Floating-Point" 162 | 163 | fld fpu,load 164 | fsd fpu,store 165 | fmadd.d fpu,fma 166 | fmsub.d fpu,fma 167 | fnmadd.d fpu,fma 168 | fnmsub.d fpu,fma 169 | fadd.d fpu 170 | fsub.d fpu 171 | fmul.d fpu 172 | fdiv.d fpu,fdiv 173 | fsgnj.d fpu 174 | fsgnjn.d fpu 175 | fsgnjx.d fpu 176 | fmin.d fpu 177 | fmax.d fpu 178 | fcvt.s.d fpu,fcvt 179 | fcvt.d.s fpu,fcvt 180 | fsqrt.d fpu,fsqrt 181 | fle.d fpu 182 | flt.d fpu 183 | feq.d fpu 184 | fcvt.w.d fpu,fcvt 185 | fcvt.wu.d fpu,fcvt 186 | fcvt.d.w fpu,fcvt 187 | fcvt.d.wu fpu,fcvt 188 | fclass.d fpu 189 | 190 | # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)" 191 | 192 | fcvt.l.d fpu,fcvt 193 | fcvt.lu.d fpu,fcvt 194 | fmv.x.d fpu,fmove 195 | fcvt.d.l fpu,fcvt 196 | fcvt.d.lu fpu,fcvt 197 | fmv.d.x fpu,fmove 198 | 199 | # RV32FD "RV32F and RV32D Common Floating-Point Instructions" 200 | 201 | frcsr csr 202 | frrm csr 203 | frflags csr 204 | fscsr csr 205 | fsrm csr 206 | fsflags csr 207 | fsrmi csr 208 | fsflagsi csr 209 | -------------------------------------------------------------------------------- /opcode-descriptions: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # "" 3 | 4 | # RV32I "RV32I Base Integer Instruction Set" 5 | 6 | lui "Set and sign extend the 20-bit immediate (shited 12 bits left) and zero the bottom 12 bits into rd" 7 | auipc "Place the PC plus the 20-bit signed immediate (shited 12 bits left) into rd (used before JALR)" 8 | jal "Jump to the PC plus 20-bit signed immediate while saving PC+4 into rd" 9 | jalr "Jump to rs1 plus the 12-bit signed immediate while saving PC+4 into rd" 10 | beq "Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 == rs2" 11 | bne "Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 != rs2" 12 | blt "Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 < rs2 (signed)" 13 | bge "Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 >= rs2 (signed)" 14 | bltu "Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 < rs2 (unsigned)" 15 | bgeu "Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 >= rs2 (unsigned)" 16 | lb "Load 8-bit value from addr in rs1 plus the 12-bit signed immediate and place sign-extended result into rd" 17 | lh "Load 16-bit value from addr in rs1 plus the 12-bit signed immediate and place sign-extended result into rd" 18 | lw "Load 32-bit value from addr in rs1 plus the 12-bit signed immediate and place sign-extended result into rd" 19 | lbu "Load 8-bit value from addr in rs1 plus the 12-bit signed immediate and place zero-extended result into rd" 20 | lhu "Load 32-bit value from addr in rs1 plus the 12-bit signed immediate and place zero-extended result into rd" 21 | lwu "Load 32-bit value from addr in rs1 plus the 12-bit signed immediate and place zero-extended result into rd" 22 | sb "Store 8-bit value from the low bits of rs2 to addr in rs1 plus the 12-bit signed immediate" 23 | sh "Store 16-bit value from the low bits of rs2 to addr in rs1 plus the 12-bit signed immediate" 24 | sw "Store 32-bit value from the low bits of rs2 to addr in rs1 plus the 12-bit signed immediate" 25 | addi "Add sign-extended 12-bit immediate to register rs1 and place the result in rd" 26 | slti "Set rd to 1 if rs1 is less than the sign-extended 12-bit immediate, otherwise set rd to 0 (signed)" 27 | sltiu "Set rd to 1 if rs1 is less than the sign-extended 12-bit immediate, otherwise set rd to 0 (unsigned)" 28 | xori "Set rd to the bitwise xor of rs1 with the sign-extended 12-bit immediate" 29 | ori "Set rd to the bitwise or of rs1 with the sign-extended 12-bit immediate" 30 | andi "Set rd to the bitwise and of rs1 with the sign-extended 12-bit immediate" 31 | slli "Shift rs1 left by the 5 or 6 (RV32/64) bit (RV64) immediate and place the result into rd" 32 | srli "Shift rs1 right by the 5 or 6 (RV32/64) bit immediate and place the result into rd" 33 | srai "Shift rs1 right by the 5 or 6 (RV32/64) bit immediate and place the result into rd while retaining the sign" 34 | add "Add rs2 to rs1 and place the result into rd" 35 | sub "Subtract rs2 from rs1 and place the result into rd" 36 | sll "Shift rs1 left by the by the lower 5 or 6 (RV32/64) bits in rs2 and place the result into rd" 37 | slt "Set rd to 1 if rs1 is less than rs2, otherwise set rd to 0 (signed)" 38 | sltu "Set rd to 1 if rs1 is less than rs2, otherwise set rd to 0 (unsigned)" 39 | xor "Set rd to the bitwise xor of rs1 and rs2" 40 | srl "Shift rs1 right by the by the lower 5 or 6 (RV32/64) bits in rs2 and place the result into rd" 41 | sra "Shift rs1 right by the by the lower 5 or 6 (RV32/64) bits in rs2 and place the result into rd while retaining the sign" 42 | or "Set rd to the bitwise or of rs1 and rs2" 43 | and "Set rd to the bitwise and of rs1 and rs2" 44 | fence "Order device I/O and memory accesses viewed by other threads and devices" 45 | fence.i "Synchronize the instruction and data streams" 46 | 47 | # RV64I "RV64I Base Integer Instruction Set (in addition to RV32I)" 48 | 49 | ld "Load 64-bit value from addr in rs1 plus 12-bit signed immediate and place sign-extended result into rd" 50 | sd "Store 64-bit value from the low bits of rs2 to addr in rs1 plus the 12-bit signed immediate" 51 | addiw "Add sign-extended 12-bit immediate to register rs1 and place 32-bit sign extended result in rs2 zeroing upper bits" 52 | slliw "Shift 32-bit value in rs1 left by the 5 bit immediate and place the result into rd while zeroing upper bits" 53 | srliw "Shift 32-bit value in rs1 right by the 5 bit immediate and place the result into rd while zeroing upper bits" 54 | sraiw "Shift 32-bit value in rs1 right by the 5 bit immediate and place the result into rd and retaining the sign" 55 | addw "Add 32-bit value in rs2 to rs1 and place the 32-bit result into rd" 56 | subw "Subtract 32-bit value in rs2 from rs1 and place the 32-bit result into rd" 57 | sllw "Shift 32-bit value in rs1 left by the by the lower 5 bits in rs2 and place the 32-bit result into rd" 58 | srlw "Shift 32-bit value in rs1 right by the by the lower 5 bits in rs2 and place the 32-bit result into rd" 59 | sraw "Shift 32-bit value in rs1 right by the by the lower 5 bits in rs2 and place the 32-bit result into rd while retaining the sign" 60 | 61 | # RV32M "RV32M Standard Extension for Integer Multiply and Divide" 62 | 63 | mul "Multiply rs1 by rs2 and place the result in rd" 64 | mulh "Multiply signed rs1 by signed rs2 and place the high bits of the result in rd" 65 | mulhsu "Multiply signed rs1 by unsigned rs2 and place the high bits of the result in rd" 66 | mulhu "Multiply unsigned rs1 by unsigned rs2 and place the high bits of the result in rd" 67 | div "Divide rs1 (dividend) by rs2 (divisor) and place the quotient in rd (signed)" 68 | divu "Divide rs1 (dividend) by rs2 (divisor) and place the quotient in rd (unsigned)" 69 | rem "Divide rs1 (dividend) by rs2 (divisor) and place the remainder in rd (signed)" 70 | remu "Divide rs1 (dividend) by rs2 (divisor) and place the remainder in rd (unsigned)" 71 | 72 | # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)" 73 | 74 | mulw "Multiply with lower 32-bits of rs1 by the lower 32-bits of rs2 and place the result in rd" 75 | divw "Divide lower 32-bits of rs1 (dividend) by lower 32-bits of rs2 (divisor) and place the quotient in rd (signed)" 76 | divuw "Divide lower 32-bits of rs1 (dividend) by lower 32-bits of rs2 (divisor) and place the quotient in rd (unsigned)" 77 | remw "Divide lower 32-bits of rs1 (dividend) by lower 32-bits of rs2 (divisor) and place the remainder in rd (signed)" 78 | remuw "Divide lower 32-bits of rs1 (dividend) by lower 32-bits of rs2 (divisor) and place the remainder in rd (unsigned)" 79 | 80 | # RV32A "RV32A Standard Extension for Atomic Instructions" 81 | 82 | lr.w "Load word from address in rs1, place the sign-extended result in rd and register a reservation on the memory word" 83 | sc.w "Write word in rs1 to the address in rs2 if a valid reservation exists, write 0 on success or 1 on failure to rd" 84 | amoswap.w "Load word from address in rs1 into rd, swap rd and rs2, write the result to the address in rs1" 85 | amoadd.w "Load word from address in rs1 into rd, add rd and rs2, write the result to the address in rs1" 86 | amoxor.w "Load word from address in rs1 into rd, xor rd and rs2, write the result to the address in rs1" 87 | amoor.w "Load word from address in rs1 into rd, or rd and rs2, write the result to the address in rs1" 88 | amoand.w "Load word from address in rs1 into rd, and rd and rs2, write the result to the address in rs1" 89 | amomin.w "Load word from address in rs1 into rd, find minimum of rd and rs2, write the result to the address in rs1 (signed)" 90 | amomax.w "Load word from address in rs1 into rd, find maximum of rd and rs2, write the result to the address in rs1 (signed)" 91 | amominu.w "Load word from address in rs1 into rd, find minimum of rd and rs2, write the result to the address in rs1 (unsigned)" 92 | amomaxu.w "Load word from address in rs1 into rd, find maximum of rd and rs2, write the result to the address in rs1 (unsigned)" 93 | 94 | # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" 95 | 96 | lr.d "Load double word from address in rs1, place the sign-extended result in rd and register a reservation on the memory word" 97 | sc.d "Write double word in rs1 to the address in rs2 if a valid reservation exists, write 0 on success or 1 on failure to rd" 98 | amoswap.d "Load double word from address in rs1 into rd, swap rd and rs2, write the result to the address in rs1" 99 | amoadd.d "Load double word from address in rs1 into rd, add rd and rs2, write the result to the address in rs1" 100 | amoxor.d "Load double word from address in rs1 into rd, xor rd and rs2, write the result to the address in rs1" 101 | amoor.d "Load double word from address in rs1 into rd, or rd and rs2, write the result to the address in rs1" 102 | amoand.d "Load double word from address in rs1 into rd, and rd and rs2, write the result to the address in rs1" 103 | amomin.d "Load double word from address in rs1 into rd, find minimum of rd and rs2, write the result to the address in rs1 (signed)" 104 | amomax.d "Load double word from address in rs1 into rd, find maximum of rd and rs2, write the result to the address in rs1 (signed)" 105 | amominu.d "Load double word from address in rs1 into rd, find minimum of rd and rs2, write the result to the address in rs1 (unsigned)" 106 | amomaxu.d "Load double word from address in rs1 into rd, find maximum of rd and rs2, write the result to the address in rs1 (unsigned)" 107 | 108 | # RV32S "RV32S Standard Extension for Supervisor-level Instructions" 109 | 110 | scall "System call is used to make a request to a higher privilege level" 111 | sbreak "Break to Debugger causes control to be transferred back to the debugging environment via a breakpoint exception" 112 | sret "System Return returns to the supervisor mode privilege level after handling a trap" 113 | sfence.vm "Supervisor memory-management fence synchronizes updates to in-memory memory-management data structures" 114 | wfi "Wait for Interrupt indicates the hart can be stalled until an interrupt needs servicing" 115 | rdcycle "Read cycle counter status register" 116 | rdtime "Read timer status register" 117 | rdinstret "Read instructions retired status register" 118 | rdcycleh "Read cycle counter status register (upper 32-bits on RV32)" 119 | rdtimeh "Read timer status register (upper 32-bits on RV32)" 120 | rdinstreth "Read instructions retired status register (upper 32-bits on RV32)" 121 | csrrw "CSR Atomic Read Write writes the value in rs1 to the CSR, and writes previous value to rd" 122 | csrrs "CSR Atomic Set Bit reads the CSR, sets CSR bits set in rs1, and writes previous value to rd" 123 | csrrc "CSR Atomic Clear Bit reads the CSR, clears CSR bits set in rs1, and writes previous value to rd" 124 | csrrwi "CSR Atomic Read Write Immediate writes the immediate value to the CSR, and writes previous value to rd" 125 | csrrsi "CSR Atomic Set Bit Immediate reads the CSR, sets CSR bits set in the immediate, and writes previous value to rd" 126 | csrrci "CSR Atomic Clear Bit Immediate reads the CSR, clears CSR bits set in the immediate, and writes previous value to rd" 127 | 128 | # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" 129 | 130 | flw "Loads a single-precision foating-point value from memory into foating-point register frd" 131 | fsw "Stores a single-precision foating-point value from foating-point register frs2 to memory" 132 | fmadd.s "Multiply the single-precision values in frs1 and frs2, then add rs3 and write the result to frd" 133 | fmsub.s "Multiply the single-precision values in frs1 and frs2, then subtract rs3 and write the result to frd" 134 | fnmsub.s "Multiply the single-precision value in frs1 with the negated value in frs2, then add rs3 and write the result to frd" 135 | fnmadd.s "Multiply the single-precision value in frs1 with the negated value in frs2, then subtract rs3 and write the result to frd" 136 | fadd.s "Add the single-precision values in frs1 and frs2, then write the result to frd" 137 | fsub.s "Subtract the single-precision values in frs1 from frs2, then write the result to frd" 138 | fmul.s "Multiply the single-precision values in frs1 and frs2, then write the result to frd" 139 | fdiv.s "Divide the single-precision value in frs1 into frs2, then write the result to frd" 140 | fsgnj.s "Take the single-precision value from frs1 and inject the sign bit from frs2, then write the result to frd" 141 | fsgnjn.s "Take the single-precision value from frs1 and inject the negated sign bit from frs2, then write the result to frd" 142 | fsgnjx.s "Take the single-precision value from frs1 and inject the xor of the sign bits frs1 and frs2, then write the result to frd" 143 | fmin.s "Take the smaller single-precision value from frs1 and frs2, then write the result to frd" 144 | fmax.s "Take the larger single-precision value from frs1 and frs2, then write the result to frd" 145 | fsqrt.s "Calculate the square root of the single-precision value in frs1, then write the result to frd" 146 | fle.s "Set rd to 1 if the single-precision value in frs1 is less than or equal to frs2, otherwise set rd to 0" 147 | flt.s "Set rd to 1 if the single-precision value in frs1 is less than frs2, otherwise set rd to 0" 148 | feq.s "Set rd to 1 if the single-precision value in frs1 is equal to frs2, otherwise set rd to 0" 149 | fcvt.w.s "Convert the single-precision value in frs1 to a 32-bit signed integer, then write the result to rd" 150 | fcvt.wu.s "Convert the single-precision value in frs1 to a 32-bit unsigned integer, then write the result to rd" 151 | fcvt.s.w "Convert the 32-bit signed integer in rs1 to a single-precision value, then write the result to frd" 152 | fcvt.s.wu "Convert the 32-bit unsigned integer in rs1 to a single-precision value, then write the result to frd" 153 | fclass.s "Set rd to a 10-bit mask indicating the class of the single-precision value in frs1" 154 | 155 | # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" 156 | 157 | fcvt.l.s "Convert the single-precision value in frs1 to a 64-bit signed integer, then write the result to rd" 158 | fcvt.lu.s "Convert the single-precision value in frs1 to a 64-bit unsigned integer, then write the result to rd" 159 | fmv.x.s "Write the sign extended single-precision value in frs1 into the integer register rd" 160 | fcvt.s.l "Convert the 64-bit signed integer in rs1 to a single-precision value, then write the result to frd" 161 | fcvt.s.lu "Convert the 64-bit unsigned integer in rs1 to a single-precision value, then write the result to frd" 162 | fmv.s.x "Write the lower 32-bits of the integer register rs1 into the single-precision register frd" 163 | 164 | # RV32D "RV32D Standard Extension for Double-Precision Floating-Point" 165 | 166 | fld "Loads a double-precision foating-point value from memory into foating-point register frd" 167 | fsd "Stores a double-precision foating-point value from foating-point register frs2 to memory" 168 | fmadd.d "Multiply the double-precision values in frs1 and frs2, then add rs3 and write the result to frd" 169 | fmsub.d "Multiply the double-precision values in frs1 and frs2, then subtract rs3 and write the result to frd" 170 | fnmsub.d "Multiply the double-precision value in frs1 with the negated value in frs2, then add rs3 and write the result to frd" 171 | fnmadd.d "Multiply the double-precision value in frs1 with the negated value in frs2, then subtract rs3 and write the result to frd" 172 | fadd.d "Add the double-precision values in frs1 and frs2, then write the result to frd" 173 | fsub.d "Subtract the double-precision values in frs1 from frs2, then write the result to frd" 174 | fmul.d "Multiply the double-precision values in frs1 and frs2, then write the result to frd" 175 | fdiv.d "Divide the double-precision value in frs1 into frs2, then write the result to frd" 176 | fsgnj.d "Take the double-precision value from frs1 and inject the sign bit from frs2, then write the result to frd" 177 | fsgnjn.d "Take the double-precision value from frs1 and inject the negated sign bit from frs2, then write the result to frd" 178 | fsgnjx.d "Take the double-precision value from frs1 and inject the xor of the sign bits frs1 and frs2, then write the result to frd" 179 | fmin.s "Take the smaller double-precision value from frs1 and frs2, then write the result to frd" 180 | fmax.s "Take the larger double-precision value from frs1 and frs2, then write the result to frd" 181 | fcvt.s.d "Convert the double-precision value in frs1 to single-precision, then write the result to frd" 182 | fcvt.d.s "Convert the single-precision value in frs1 to double-precision, then write the result to frd" 183 | fsqrt.d "Calculate the square root of the double-precision value in frs1, then write the result to frd" 184 | fle.d "Set rd to 1 if frs1 is less than or equal to frs2, otherwise set rd to 0" 185 | flt.d "Set rd to 1 if frs1 is less than frs2, otherwise set rd to 0" 186 | feq.d "Set rd to 1 if frs1 is equal to frs2, otherwise set rd to 0" 187 | fcvt.w.d "Convert the double-precision value in frs1 to a 32-bit signed integer, then write the result to rd" 188 | fcvt.wu.d "Convert the double-precision value in frs1 to a 32-bit unsigned integer, then write the result to rd" 189 | fcvt.d.w "Convert the 64-bit signed integer in rs1 to a double-precision value, then write the result to frd" 190 | fcvt.d.wu "Convert the 64-bit unsigned integer in rs1 to a double-precision value, then write the result to frd" 191 | fmv.x.d "Write the sign extended double-precision value in frs1 into integer register rd" 192 | fclass.d "Set rd to a 10-bit mask indicating the class of the double-precision value in frs1" 193 | fmv.d.x "Write the 64-bit integer register rs1 into the double-precision register frd" 194 | 195 | # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32F)" 196 | 197 | fcvt.l.d "Convert the double-precision value in frs1 to a 64-bit signed integer, then write the result to rd" 198 | fcvt.lu.d "Convert the double-precision value in frs1 to a 64-bit unsigned integer, then write the result to rd" 199 | fcvt.d.l "Convert the 64-bit signed integer in rs1 to a double-precision value, then write the result to frd" 200 | fcvt.d.lu "Convert the 64-bit unsigned integer in rs1 to a double-precision value, then write the result to frd" 201 | 202 | # RV32Q "RV32D Standard Extension for Quadruple-Precision Floating-Point" 203 | 204 | flq "Loads a quadruple-precision foating-point value from memory into foating-point register frd" 205 | fsq "Stores a quadruple-precision foating-point value from foating-point register frs2 to memory" 206 | fmadd.q "Multiply the quadruple-precision values in frs1 and frs2, then add rs3 and write the result to frd" 207 | fmsub.q "Multiply the quadruple-precision values in frs1 and frs2, then subtract rs3 and write the result to frd" 208 | fnmsub.q "Multiply the quadruple-precision value in frs1 with the negated value in frs2, then add rs3 and write the result to frd" 209 | fnmadd.q "Multiply the quadruple-precision value in frs1 with the negated value in frs2, then subtract rs3 and write the result to frd" 210 | fadd.q "Add the quadruple-precision values in frs1 and frs2, then write the result to frd" 211 | fsub.q "Subtract the quadruple-precision values in frs1 from frs2, then write the result to frd" 212 | fmul.q "Multiply the quadruple-precision values in frs1 and frs2, then write the result to frd" 213 | fdiv.q "Divide the quadruple-precision value in frs1 into frs2, then write the result to frd" 214 | fsgnj.q "Take the quadruple-precision value from frs1 and inject the sign bit from frs2, then write the result to frd" 215 | fsgnjn.q "Take the quadruple-precision value from frs1 and inject the negated sign bit from frs2, then write the result to frd" 216 | fsgnjx.q "Take the quadruple-precision value from frs1 and inject the xor of the sign bits frs1 and frs2, then write the result to frd" 217 | fmin.s "Take the smaller quadruple-precision value from frs1 and frs2, then write the result to frd" 218 | fmax.s "Take the larger quadruple-precision value from frs1 and frs2, then write the result to frd" 219 | fcvt.s.q "Convert the quadruple-precision value in frs1 to single-precision, then write the result to frd" 220 | fcvt.q.s "Convert the single-precision value in frs1 to quadruple-precision, then write the result to frd" 221 | fcvt.d.q "Convert the quadruple-precision value in frs1 to double-precision, then write the result to frd" 222 | fcvt.q.d "Convert the double-precision value in frs1 to quadruple-precision, then write the result to frd" 223 | fsqrt.q "Calculate the square root of the quadruple-precision value in frs1, then write the result to frd" 224 | fle.q "Set rd to 1 if frs1 is less than or equal to frs2, otherwise set rd to 0" 225 | flt.q "Set rd to 1 if frs1 is less than frs2, otherwise set rd to 0" 226 | feq.q "Set rd to 1 if frs1 is equal to frs2, otherwise set rd to 0" 227 | fcvt.w.q "Convert the quadruple-precision value in frs1 to a 32-bit signed integer, then write the result to rd" 228 | fcvt.wu.q "Convert the quadruple-precision value in frs1 to a 32-bit unsigned integer, then write the result to rd" 229 | fcvt.q.w "Convert the 64-bit signed integer in rs1 to a quadruple-precision value, then write the result to frd" 230 | fcvt.q.wu "Convert the 64-bit unsigned integer in rs1 to a quadruple-precision value, then write the result to frd" 231 | fclass.q "Set rd to a 10-bit mask indicating the class of the quadruple-precision value in frs1" 232 | 233 | # RV64Q "RV64Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV32Q)" 234 | 235 | fcvt.l.q "Convert the quadruple-precision value in frs1 to a 64-bit signed integer, then write the result to rd" 236 | fcvt.lu.q "Convert the quadruple-precision value in frs1 to a 64-bit unsigned integer, then write the result to rd" 237 | fcvt.q.l "Convert the 64-bit signed integer in rs1 to a quadruple-precision value, then write the result to frd" 238 | fcvt.q.lu "Convert the 64-bit unsigned integer in rs1 to a quadruple-precision value, then write the result to frd" 239 | 240 | # RV128Q "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)" 241 | 242 | fmv.x.q "Write the sign extended quadruple-precision value in frs1 into integer register rd" 243 | fmv.q.x "Write the 64-bit integer register rs1 into the quadruple-precision register frd" 244 | 245 | # RV32FD "RV32F and RV32D Common Floating-Point Instructions" 246 | 247 | frcsr "Read FP Control and Status Register" 248 | frrm "Read FP Rounding Mode (Bits 7:5 of fcsr Control and Status Register)" 249 | frflags "Read FP Accrued Exception Flags (Bits 4:0 of fcsr Control and Status Register)" 250 | fscsr "Read FP Control and Status Register" 251 | fsrm "Set FP Rounding Mode (Bits 7:5 of fcsr Control and Status Register)" 252 | fsflags "Set FP Accrued Exception Flags (Bits 4:0 of fcsr Control and Status Register)" 253 | fsrmi "Set FP Rounding Mode Immediate (Bits 7:5 of fcsr Control and Status Register)" 254 | fsflagsi "Set FP Accrued Exception Flags Immediate (Bits 4:0 of fcsr Control and Status Register)" 255 | 256 | # Pseudo Instructions 257 | 258 | nop "No operation" 259 | #li "Load immediate" 260 | mv "Copy register" 261 | not "One’s complement" 262 | neg "Two’s complement" 263 | negw "Two’s complement Word" 264 | sext.w "Sign extend Word" 265 | seqz "Set if = zero" 266 | snez "Set if ≠ zero" 267 | sltz "Set if < zero" 268 | sgtz "Set if > zero" 269 | fmv.s "Single-precision move" 270 | fabs.s "Single-precision absolute value" 271 | fneg.s "Single-precision negate" 272 | fmv.d "Double-precision move" 273 | fabs.d "Double-precision absolute value" 274 | fneg.d "Double-precision negate" 275 | fmv.q "Quadruple-precision move" 276 | fabs.q "Quadruple-precision absolute value" 277 | fneg.q "Quadruple-precision negate" 278 | beqz "Branch if = zero" 279 | bnez "Branch if ≠ zero" 280 | blez "Branch if ≤ zero" 281 | bgez "Branch if ≥ zero" 282 | bltz "Branch if < zero" 283 | bgtz "Branch if > zero" 284 | j "Jump" 285 | jr "Jump register" 286 | ret "Return from subroutine" 287 | -------------------------------------------------------------------------------- /opcode-fullnames: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # "" 3 | 4 | # RV32I "RV32I Base Integer Instruction Set" 5 | 6 | lui "Load Upper Immediate" 7 | auipc "Add Upper Immediate to PC" 8 | jal "Jump and Link" 9 | jalr "Jump and Link Register" 10 | beq "Branch Equal" 11 | bne "Branch Not Equal" 12 | blt "Branch Less Than" 13 | bge "Branch Greater than Equal" 14 | bltu "Branch Less Than Unsigned" 15 | bgeu "Branch Greater than Equal Unsigned" 16 | lb "Load Byte" 17 | lh "Load Half" 18 | lw "Load Word" 19 | lbu "Load Byte Unsigned" 20 | lhu "Load Half Unsigned" 21 | lwu "Load Word Unsigned" 22 | sb "Store Byte" 23 | sh "Store Half" 24 | sw "Store Word" 25 | addi "Add Immediate" 26 | slti "Set Less Than Immediate" 27 | sltiu "Set Less Than Immediate Unsigned" 28 | xori "Xor Immediate" 29 | ori "Or Immediate" 30 | andi "And Immediate" 31 | slli "Shift Left Logical Immediate" 32 | srli "Shift Right Logical Immediate" 33 | srai "Shift Right Arithmetic Immediate" 34 | add "Add" 35 | sub "Subtract" 36 | sll "Shift Left Logical" 37 | slt "Set Less Than" 38 | sltu "Set Less Than Unsigned" 39 | xor "Xor" 40 | srl "Shift Right Logical" 41 | sra "Shift Right Arithmetic" 42 | or "Or" 43 | and "And" 44 | fence "Fence" 45 | fence.i "Fence Instruction" 46 | 47 | # RV64I "RV64I Base Integer Instruction Set (in addition to RV32I)" 48 | 49 | ld "Load Double" 50 | sd "Store Double" 51 | addiw "Add Immediate Word" 52 | slliw "Shift Left Logical Immediate Word" 53 | srliw "Shift Right Logical Immediate Word" 54 | sraiw "Shift Right Arithmetic Immediate Word" 55 | addw "Add Word" 56 | subw "Subtract Word" 57 | sllw "Shift Left Logical Word" 58 | srlw "Shift Right Logical Word" 59 | sraw "Shift Right Arithmetic Word" 60 | 61 | # RV32M "RV32M Standard Extension for Integer Multiply and Divide" 62 | 63 | mul "Multiply" 64 | mulh "Multiply High Signed Signed" 65 | mulhsu "Multiply High Signed Unsigned" 66 | mulhu "Multiply High Unsigned Unsigned" 67 | div "Divide Signed" 68 | divu "Divide Unsigned" 69 | rem "Remainder Signed" 70 | remu "Remainder Unsigned" 71 | 72 | # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)" 73 | 74 | mulw "Multiple Word" 75 | divw "Divide Signed Word" 76 | divuw "Divide Unsigned Word" 77 | remw "Remainder Signed Word" 78 | remuw "Remainder Unsigned Word" 79 | 80 | # RV32A "RV32A Standard Extension for Atomic Instructions" 81 | 82 | lr.w "Load Reserved Word" 83 | sc.w "Store Conditional Word" 84 | amoswap.w "Atomic Swap Word" 85 | amoadd.w "Atomic Add Word" 86 | amoxor.w "Atomic Xor Word" 87 | amoor.w "Atomic Or Word" 88 | amoand.w "Atomic And Word" 89 | amomin.w "Atomic Minimum Word" 90 | amomax.w "Atomic Maximum Word" 91 | amominu.w "Atomic Minimum Unsigned Word" 92 | amomaxu.w "Atomic Maximum Unsigned Word" 93 | 94 | # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" 95 | 96 | lr.d "Load Reserved Double Word" 97 | sc.d "Store Conditional Double Word" 98 | amoswap.d "Atomic Swap Double Word" 99 | amoadd.d "Atomic Add Double Word" 100 | amoxor.d "Atomic Xor Double Word" 101 | amoor.d "Atomic Or Double Word" 102 | amoand.d "Atomic And Double Word" 103 | amomin.d "Atomic Minimum Double Word" 104 | amomax.d "Atomic Maximum Double Word" 105 | amominu.d "Atomic Minimum Unsigned Double Word" 106 | amomaxu.d "Atomic Maximum Unsigned Double Word" 107 | 108 | # RV32S "RV32S Standard Extension for Supervisor-level Instructions" 109 | 110 | ecall "Environment Call" 111 | ebreak "Environment Break to Debugger" 112 | uret "User Return" 113 | sret "System Return" 114 | hret "Hypervisor Return" 115 | mret "Machine-Mode Return" 116 | dret "Debug-Mode Return" 117 | sfence.vm "Supervisor Memory Management Fence" 118 | wfi "Wait For Interrupt" 119 | rdcycle "Read Cycle Counter Status Register" 120 | rdtime "Read Timer Status register" 121 | rdinstret "Read Instructions Retired Status Register" 122 | rdcycleh "Read Cycle Counter Status Register (upper 32-bits on RV32)" 123 | rdtimeh "Read Timer Status register (upper 32-bits on RV32)" 124 | rdinstreth "Read Instructions Retired Status Register (upper 32-bits on RV32)" 125 | csrrw "CSR Atomic Read Write" 126 | csrrs "CSR Atomic Set Bit" 127 | csrrc "CSR Atomic Clear Bit" 128 | csrrwi "CSR Atomic Read Write Immediate" 129 | csrrsi "CSR Atomic Set Bit Immediate" 130 | csrrci "CSR Atomic Clear Bit Immediate" 131 | 132 | # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" 133 | 134 | flw "FP Load (SP)" 135 | fsw "FP Store (SP)" 136 | fmadd.s "FP Fused Multiply Add (SP)" 137 | fmsub.s "FP Fused Multiply Subtract (SP)" 138 | fnmadd.s "FP Negate fused Multiply Add (SP)" 139 | fnmsub.s "FP Negate fused Multiply Subtract (SP)" 140 | fadd.s "FP Add (SP)" 141 | fsub.s "FP Subtract (SP)" 142 | fmul.s "FP Multiply (SP)" 143 | fdiv.s "FP Divide (SP)" 144 | fsgnj.s "FP Sign-injection (SP)" 145 | fsgnjn.s "FP Sign-injection Negate (SP)" 146 | fsgnjx.s "FP Sign-injection Xor (SP)" 147 | fmin.s "FP Minimum (SP)" 148 | fmax.s "FP Maximum (SP)" 149 | fsqrt.s "FP Square Root (SP)" 150 | fle.s "FP Less Than Equal (SP)" 151 | flt.s "FP Less Than (SP)" 152 | feq.s "FP Equal (SP)" 153 | fcvt.w.s "FP Convert Float to Word (SP)" 154 | fcvt.wu.s "FP Convert Float to Word Unsigned (SP)" 155 | fcvt.s.w "FP Convert Word to Float (SP)" 156 | fcvt.s.wu "FP Convert Word Unsigned to Float (SP)" 157 | fmv.x.s "FP Move to Integer Register (SP)" 158 | fclass.s "FP Classify (SP)" 159 | fmv.s.x "FP Move from Integer Register (SP)" 160 | 161 | # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" 162 | 163 | fcvt.l.s "FP Convert Float to Double Word (SP)" 164 | fcvt.lu.s "FP Convert Float to Double Word Unsigned (SP)" 165 | fcvt.s.l "FP Convert Double Word to Float (SP)" 166 | fcvt.s.lu "FP Convert Double Word Unsigned to Float (SP)" 167 | 168 | # RV32D "RV32D Standard Extension for Double-Precision Floating-Point" 169 | 170 | fld "FP Load (DP)" 171 | fsd "FP Store (DP)" 172 | fmadd.d "FP Fused Multiply Add (DP)" 173 | fmsub.d "FP Fused Multiply Subtract (DP)" 174 | fnmadd.d "FP Negate fused Multiply Add (DP)" 175 | fnmsub.d "FP Negate fused Multiply Subtract (DP)" 176 | fadd.d "FP Add (DP)" 177 | fsub.d "FP Subtract (DP)" 178 | fmul.d "FP Multiply (DP)" 179 | fdiv.d "FP Divide (DP)" 180 | fsgnj.d "FP to Sign-injection (DP)" 181 | fsgnjn.d "FP to Sign-injection Negate (DP)" 182 | fsgnjx.d "FP to Sign-injection Xor (DP)" 183 | fmin.d "FP Minimum (DP)" 184 | fmax.d "FP Maximum (DP)" 185 | fcvt.s.d "FP Convert DP to SP" 186 | fcvt.d.s "FP Convert SP to DP" 187 | fsqrt.d "Floating Square Root (DP)" 188 | fle.d "FP Less Than Equal (DP)" 189 | flt.d "FP Less Than (DP)" 190 | feq.d "FP Equal (DP)" 191 | fcvt.w.d "FP Convert Float to Word (DP)" 192 | fcvt.wu.d "FP Convert Float to Word Unsigned (DP)" 193 | fcvt.d.w "FP Convert Word to Float (DP)" 194 | fcvt.d.wu "FP Convert Word Unsigned to Float (DP)" 195 | fclass.d "FP Classify (DP)" 196 | 197 | # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32F)" 198 | 199 | fcvt.l.d "FP Convert Float to Double Word (DP)" 200 | fcvt.lu.d "FP Convert Float to Double Word Unsigned (DP)" 201 | fmv.x.d "FP Move to Integer Register (DP)" 202 | fcvt.d.l "FP Convert Double Word to Float (DP)" 203 | fcvt.d.lu "FP Convert Double Word Unsigned Float (DP)" 204 | fmv.d.x "FP Move from Integer Register (DP)" 205 | 206 | # RV32Q "RV32Q Standard Extension for Quadruple-Precision Floating-Point" 207 | 208 | flq "FP Load (QP)" 209 | fsq "FP Store (QP)" 210 | fmadd.q "FP Fused Multiply Add (QP)" 211 | fmsub.q "FP Fused Multiply Subtract (QP)" 212 | fnmadd.q "FP Negate fused Multiply Add (QP)" 213 | fnmsub.q "FP Negate fused Multiply Subtract (QP)" 214 | fadd.q "FP Add (QP)" 215 | fsub.q "FP Subtract (QP)" 216 | fmul.q "FP Multiply (QP)" 217 | fdiv.q "FP Divide (QP)" 218 | fsgnj.q "FP to Sign-injection (QP)" 219 | fsgnjn.q "FP to Sign-injection Negate (QP)" 220 | fsgnjx.q "FP to Sign-injection Xor (QP)" 221 | fmin.q "FP Minimum (QP)" 222 | fmax.q "FP Maximum (QP)" 223 | fcvt.s.q "FP Convert QP to SP" 224 | fcvt.q.s "FP Convert SP to QP" 225 | fcvt.d.q "FP Convert QP to DP" 226 | fcvt.q.d "FP Convert DP to QP" 227 | fsqrt.q "Floating Square Root (QP)" 228 | fle.q "FP Less Than Equal (QP)" 229 | flt.q "FP Less Than (QP)" 230 | feq.q "FP Equal (QP)" 231 | fcvt.w.q "FP Convert Float to Word (QP)" 232 | fcvt.wu.q "FP Convert Float to Word Unsigned (QP)" 233 | fcvt.q.w "FP Convert Word to Float (QP)" 234 | fcvt.q.wu "FP Convert Word Unsigned to Float (QP)" 235 | fclass.q "FP Classify (QP)" 236 | 237 | # RV64Q "RV64Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV32Q)" 238 | 239 | fcvt.l.q "FP Convert Float to Double Word (QP)" 240 | fcvt.lu.q "FP Convert Float to Double Word Unsigned (QP)" 241 | fcvt.q.l "FP Convert Double Word to Float (QP)" 242 | fcvt.q.lu "FP Convert Double Word Unsigned Float (QP)" 243 | 244 | # RV128Q "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)" 245 | 246 | fmv.x.q "FP Move to Integer Register (QP)" 247 | fmv.q.x "FP Move from Integer Register (QP)" 248 | 249 | # RV32FD "RV32F and RV32D Common Floating-Point Instructions" 250 | 251 | frcsr "Read FP Control and Status Register" 252 | frrm "Read FP Rounding Mode" 253 | frflags "Read FP Accrued Exception Flags" 254 | fscsr "Set FP Control and Status Register" 255 | fsrm "Set FP Rounding Mode" 256 | fsflags "Set FP Accrued Exception Flags" 257 | fsrmi "Set FP Rounding Mode Immediate" 258 | fsflagsi "Set FP Accrued Exception Flags Immediate" 259 | 260 | # Pseudo Instructions 261 | 262 | nop "No operation" 263 | #li "Load immediate" 264 | mv "Copy register" 265 | not "One’s complement" 266 | neg "Two’s complement" 267 | negw "Two’s complement Word" 268 | sext.w "Sign extend Word" 269 | seqz "Set if = zero" 270 | snez "Set if ≠ zero" 271 | sltz "Set if < zero" 272 | sgtz "Set if > zero" 273 | fmv.s "Single-precision move" 274 | fabs.s "Single-precision absolute value" 275 | fneg.s "Single-precision negate" 276 | fmv.d "Double-precision move" 277 | fabs.d "Double-precision absolute value" 278 | fneg.d "Double-precision negate" 279 | fmv.q "Quadruple-precision move" 280 | fabs.q "Quadruple-precision absolute value" 281 | fneg.q "Quadruple-precision negate" 282 | beqz "Branch if = zero" 283 | bnez "Branch if ≠ zero" 284 | blez "Branch if ≤ zero" 285 | bgez "Branch if ≥ zero" 286 | bltz "Branch if < zero" 287 | bgtz "Branch if > zero" 288 | j "Jump" 289 | jr "Jump register" 290 | ret "Return from subroutine" 291 | -------------------------------------------------------------------------------- /opcode-majors: -------------------------------------------------------------------------------- 1 | 6..5=0 4..2=0 LOAD 2 | 6..5=0 4..2=1 LOAD-FP 3 | 6..5=0 4..2=2 custom-0 4 | 6..5=0 4..2=3 MISC-MEM 5 | 6..5=0 4..2=4 OP-IMM 6 | 6..5=0 4..2=5 AUIPC 7 | 6..5=0 4..2=6 OP-IMM-32 8 | 6..5=0 4..2=7 48-bit 9 | 6..5=1 4..2=0 STORE 10 | 6..5=1 4..2=1 STORE-FP 11 | 6..5=1 4..2=2 custom-1 12 | 6..5=1 4..2=3 AMO 13 | 6..5=1 4..2=4 OP 14 | 6..5=1 4..2=5 LUI 15 | 6..5=1 4..2=6 OP-32 16 | 6..5=1 4..2=7 64-bit 17 | 6..5=2 4..2=0 MADD 18 | 6..5=2 4..2=1 MSUB 19 | 6..5=2 4..2=2 NMSUB 20 | 6..5=2 4..2=3 NMADD 21 | 6..5=2 4..2=4 OP-FP 22 | 6..5=2 4..2=5 reserved 23 | 6..5=2 4..2=6 custom-2,rv128 24 | 6..5=2 4..2=7 48-bit 25 | 6..5=3 4..2=0 BRANCH 26 | 6..5=3 4..2=1 JALR 27 | 6..5=3 4..2=2 reserved 28 | 6..5=3 4..2=3 JAL 29 | 6..5=3 4..2=4 SYSTEM 30 | 6..5=3 4..2=5 reserved 31 | 6..5=3 4..2=6 custom-3,rv128 32 | 6..5=3 4..2=7 >80-bit 33 | -------------------------------------------------------------------------------- /opcode-pseudocode-alt: -------------------------------------------------------------------------------- 1 | # RV32I 2 | lui "rd ← imm" 3 | auipc "rd ← pc + imm" 4 | jal "rd ← pc + length(inst) ; pc ← pc + imm" 5 | jalr "rd ← pc + length(inst) ; pc ← (rs1 + imm) ∧ -2" 6 | beq "if rs1 = rs2 then pc ← pc + imm" 7 | bne "if rs1 ≠ rs2 then pc ← pc + imm" 8 | blt "if rs1 < rs2 then pc ← pc + imm" 9 | bge "if rs1 ≥ rs2 then pc ← pc + imm" 10 | bltu "if rs1 < rs2 then pc ← pc + imm" 11 | bgeu "if rs1 ≥ rs2 then pc ← pc + imm" 12 | lb "rd ← s8[rs1 + imm]" 13 | lh "rd ← s16[rs1 + imm]" 14 | lw "rd ← s32[rs1 + imm]" 15 | lbu "rd ← u8[rs1 + imm]" 16 | lhu "rd ← u16[rs1 + imm]" 17 | lwu "rd ← u32[rs1 + imm]" 18 | sb "u8[rs1 + imm] ← rs2" 19 | sh "u16[rs1 + imm] ← rs2" 20 | sw "u32[rs1 + imm] ← rs2" 21 | addi "rd ← rs1 + sx(imm)" 22 | slti "rd ← sx(rs1) < sx(imm)" 23 | sltiu "rd ← ux(rs1) < ux(imm)" 24 | xori "rd ← ux(rs1) ⊻ ux(imm)" 25 | ori "rd ← ux(rs1) ∨ ux(imm)" 26 | andi "rd ← ux(rs1) ∧ ux(imm)" 27 | slli "rd ← ux(rs1) « ux(imm)" 28 | srli "rd ← ux(rs1) » ux(imm)" 29 | srai "rd ← sx(rs1) » ux(imm)" 30 | add "rd ← sx(rs1) + sx(rs2)" 31 | sub "rd ← sx(rs1) - sx(rs2)" # rs1 + ¬rs2 + 1 32 | sll "rd ← ux(rs1) « rs2" 33 | slt "rd ← sx(rs1) < sx(rs2)" 34 | sltu "rd ← ux(rs1) < ux(rs2)" 35 | xor "rd ← ux(rs1) ⊻ ux(rs2)" 36 | srl "rd ← ux(rs1) » rs2" 37 | sra "rd ← sx(rs1) » rs2" 38 | or "rd ← ux(rs1) ∨ ux(rs2)" 39 | and "rd ← ux(rs1) ∧ ux(rs2)" 40 | fence 41 | fence.i 42 | 43 | # RV64I 44 | ld "rd ← u64[rs1 + imm]" 45 | sd "u64[rs1 + imm] ← rs2" 46 | addiw "rd ← s32(rs1) + imm" 47 | slliw "rd ← s32(u32(rs1) « imm)" 48 | srliw "rd ← s32(u32(rs1) » imm)" 49 | sraiw "rd ← s32(rs1) » imm" 50 | addw "rd ← s32(rs1) + s32(rs2)" 51 | subw "rd ← s32(rs1) - s32(rs2)" 52 | sllw "rd ← s32(u32(rs1) « rs2)" 53 | srlw "rd ← s32(u32(rs1) » rs2)" 54 | sraw "rd ← s32(rs1) » rs2" 55 | 56 | # RV32M 57 | mul "rd ← ux(rs1) × ux(rs2)" 58 | mulh "rd ← (sx(rs1) × sx(rs2)) » xlen" 59 | mulhsu "rd ← (sx(rs1) × ux(rs2)) » xlen" 60 | mulhu "rd ← (ux(rs1) × ux(rs2)) » xlen" 61 | div "rd ← sx(rs1) ÷ sx(rs2)" 62 | divu "rd ← ux(rs1) ÷ ux(rs2)" 63 | rem "rd ← sx(rs1) mod sx(rs2)" 64 | remu "rd ← ux(rs1) mod ux(rs2)" 65 | 66 | # RV64M 67 | mulw "rd ← u32(rs1) × u32(rs2)" 68 | divw "rd ← s32(rs1) ÷ s32(rs2)" 69 | divuw "rd ← u32(rs1) ÷ u32(rs2)" 70 | remw "rd ← s32(rs1) mod s32(rs2)" 71 | remuw "rd ← u32(rs1) mod u32(rs2)" 72 | 73 | # RV32A "RV32A Standard Extension for Atomic Instructions" 74 | 75 | lr.w "lr ← rs1 ∥ rd ← sx(s32[rs1])" 76 | sc.w "if lr = rs1 then u32[rs1] ← u32(rs2); rd ← 0 else rd ← 1" 77 | amoswap.w "rd ← s32[rs1] ∥ u32[rs1] ← s32(rs2)" 78 | amoadd.w "rd ← s32[rs1] ∥ u32[rs1] ← s32(rs2) + s32[rs1]" 79 | amoxor.w "rd ← s32[rs1] ∥ u32[rs1] ← s32(rs2) ⊻ s32[rs1]" 80 | amoor.w "rd ← s32[rs1] ∥ u32[rs1] ← s32(rs2) ∨ s32[rs1]" 81 | amoand.w "rd ← s32[rs1] ∥ u32[rs1] ← s32(rs2) ∧ s32[rs1]" 82 | amomin.w "rd ← s32[rs1] ∥ u32[rs1] ← s32_min(s32(rs2), s32[rs1])" 83 | amomax.w "rd ← s32[rs1] ∥ u32[rs1] ← s32_max(s32(rs2), s32[rs1])" 84 | amominu.w "rd ← s32[rs1] ∥ u32[rs1] ← u32_min(u32(rs2), u32[rs1])" 85 | amomaxu.w "rd ← s32[rs1] ∥ u32[rs1] ← u32_max(u32(rs2), u32[rs1])" 86 | 87 | # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" 88 | 89 | lr.d "lr ← rs1 ∥ rd ← sx(s64[rs1])" 90 | sc.d "if lr = rs1 then u64[rs1] ← u64(rs2); rd ← 0 else rd ← 1" 91 | amoswap.d "rd ← s64[rs1] ∥ u64[rs1] ← s64(rs2)" 92 | amoadd.d "rd ← s64[rs1] ∥ u64[rs1] ← s64(rs2) + s64[rs1]" 93 | amoxor.d "rd ← s64[rs1] ∥ u64[rs1] ← s64(rs2) ⊻ s64[rs1]" 94 | amoor.d "rd ← s64[rs1] ∥ u64[rs1] ← s64(rs2) ∨ s64[rs1]" 95 | amoand.d "rd ← s64[rs1] ∥ u64[rs1] ← s64(rs2) ∧ s64[rs1]" 96 | amomin.d "rd ← s64[rs1] ∥ u64[rs1] ← s64_min(s64(rs2), s64[rs1])" 97 | amomax.d "rd ← s64[rs1] ∥ u64[rs1] ← s64_max(s64(rs2), s64[rs1])" 98 | amominu.d "rd ← s64[rs1] ∥ u64[rs1] ← u64_min(u64(rs2), u64[rs1])" 99 | amomaxu.d "rd ← s64[rs1] ∥ u64[rs1] ← u64_max(u64(rs2), u64[rs1])" 100 | 101 | # RV32S "RV32S Standard Extension for Supervisor-level Instructions" 102 | 103 | ecall 104 | ebreak 105 | uret 106 | sret 107 | hret 108 | mret 109 | dret 110 | sfence.vm 111 | wfi 112 | rdcycle 113 | rdtime 114 | rdinstret 115 | rdcycleh 116 | rdtimeh 117 | rdinstreth 118 | csrrw 119 | csrrs 120 | csrrc 121 | csrrwi 122 | csrrsi 123 | csrrci 124 | 125 | # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" 126 | 127 | flw "frd ← f32[rs1 + imm]" 128 | fsw "f32[rs1 + imm] ← f32(frs2)" 129 | fmadd.s "frm ← rm ; frd ← f32(frs1) × f32(frs2) + f32(frs3)" 130 | fmsub.s "frm ← rm ; frd ← f32(frs1) × f32(frs2) - f32(frs3)" 131 | fnmadd.s "frm ← rm ; frd ← f32(frs1) × -f32(frs2) - f32(frs3)" 132 | fnmsub.s "frm ← rm ; frd ← f32(frs1) × -f32(frs2) + f32(frs3)" 133 | fadd.s "frm ← rm ; frd ← f32(frs1) + f32(frs2)" 134 | fsub.s "frm ← rm ; frd ← f32(frs1) - f32(frs2)" 135 | fmul.s "frm ← rm ; frd ← f32(frs1) × f32(frs2)" 136 | fdiv.s "frm ← rm ; frd ← f32(frs1) ÷ f32(frs2)" 137 | fsgnj.s "frd ← f32_copysign(f32(frs1), f32(frs2))" 138 | fsgnjn.s "frd ← f32_copysign(f32(frs1), -f32(frs2))" 139 | fsgnjx.s "frd ← f32_xorsign(f32(frs1), f32(frs2))" 140 | fmin.s "frd ← f32_min(f32(frs1), f32(frs2))" 141 | fmax.s "frd ← f32_max(f32(frs1), f32(frs2))" 142 | fsqrt.s "frm ← rm ; frd ← f32_sqrt(f32(frs1))" 143 | fle.s "if f32(frs1) ≤ f32(frs2) then rd ← 1 else rd ← 0" 144 | flt.s "if f32(frs1) < f32(frs2) then rd ← 1 else rd ← 0" 145 | feq.s "if f32(frs1) = f32(frs2) then rd ← 1 else rd ← 0" 146 | fcvt.w.s "frm ← rm ; rd ← s32(f32(frs1))" 147 | fcvt.wu.s "frm ← rm ; if f32(frs1) > 0 then rd ← u32(f32(frs1) else rd ← 0" 148 | fcvt.s.w "frm ← rm ; frd ← f32(s32(rs1))" 149 | fcvt.s.wu "frm ← rm ; frd ← f32(u32(rs1))" 150 | fmv.x.s "rd ← s32(frs1)" 151 | fclass.s "rd ← f32_classify(f32(frs1))" 152 | fmv.s.x "frd ← s32(rs1)" 153 | 154 | # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" 155 | 156 | fcvt.l.s "frm ← rm ; rd ← s64(f32(frs1))" 157 | fcvt.lu.s "frm ← rm ; rd ← u64(f32(frs1))" 158 | fcvt.s.l "frm ← rm ; frd ← f32(s64(rs1))" 159 | fcvt.s.lu "frm ← rm ; frd ← f32(u64(rs1))" 160 | 161 | # RV32D "RV32D Standard Extension for Double-Precision Floating-Point" 162 | 163 | fld "frd ← f64[rs1 + imm]" 164 | fsd "f64[rs1 + imm] ← f64(frs2)" 165 | fmadd.d "frm ← rm ; frd ← f64(frs1) × f64(frs2) + f64(frs3)" 166 | fmsub.d "frm ← rm ; frd ← f64(frs1) × f64(frs2) - f64(frs3)" 167 | fnmadd.d "frm ← rm ; frd ← f64(frs1) × -f64(frs2) - f64(frs3)" 168 | fnmsub.d "frm ← rm ; frd ← f64(frs1) × -f64(frs2) + f64(frs3)" 169 | fadd.d "frm ← rm ; frd ← f64(frs1) + f64(frs2)" 170 | fsub.d "frm ← rm ; frd ← f64(frs1) - f64(frs2)" 171 | fmul.d "frm ← rm ; frd ← f64(frs1) × f64(frs2)" 172 | fdiv.d "frm ← rm ; frd ← f64(frs1) ÷ f64(frs2)" 173 | fsgnj.d "frd ← f64_copysign(f64(frs1), f64(frs2))" 174 | fsgnjn.d "frd ← f64_copysign(f64(frs1), -f64(frs2))" 175 | fsgnjx.d "frd ← f64_xorsign(f64(frs1), f64(frs2))" 176 | fmin.d "frd ← f64_min(f64(frs1), f64(frs2))" 177 | fmax.d "frd ← f64_max(f64(frs1), f64(frs2))" 178 | fcvt.s.d "frm ← rm ; frd ← f32(f64(frs1))" 179 | fcvt.d.s "frm ← rm ; frd ← f64(f32(frs1))" 180 | fsqrt.d "frm ← rm ; frd ← f64_sqrt(f64(frs1))" 181 | fle.d "if f64(frs1) ≤ f64(frs2) then rd ← 1 else rd ← 0" 182 | flt.d "if f64(frs1) < f64(frs2) then rd ← 1 else rd ← 0" 183 | feq.d "if f64(frs1) = f64(frs2) then rd ← 1 else rd ← 0" 184 | fcvt.w.d "frm ← rm ; rd ← s32(f64(frs1))" 185 | fcvt.wu.d "frm ← rm ; if f64(frs1) > 0 then rd ← u32(f64(frs1) else rd ← 0" 186 | fcvt.d.w "frm ← rm ; frd ← f64(s32(rs1))" 187 | fcvt.d.wu "frm ← rm ; frd ← f64(u32(rs1))" 188 | fclass.d "rd ← rd ← f64_classify(f64(frs1))" 189 | 190 | # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)" 191 | 192 | fcvt.l.d "frm ← rm ; rd ← s64(f64(frs1))" 193 | fcvt.lu.d "frm ← rm ; if f64(frs1) > 0 then rd ← u64(f64(frs1) else rd ← 0" 194 | fmv.x.d "rd ← s64(frs1)" 195 | fcvt.d.l "frm ← rm ; frd ← f64(u64(rs1))" 196 | fcvt.d.lu "frm ← rm ; frd ← f64(s64(rs1))" 197 | fmv.d.x "frd ← u64(rs1)" 198 | 199 | # RV32Q "RV32Q Standard Extension for Quadruple-Precision Floating-Point" 200 | 201 | flq "frd ← f128[rs1 + imm]" 202 | fsq "f128[rs1 + imm] ← f128(frs2)" 203 | fmadd.q "frm ← rm ; frd ← f128(frs1) × f128(frs2) + f128(frs3)" 204 | fmsub.q "frm ← rm ; frd ← f128(frs1) × f128(frs2) - f128(frs3)" 205 | fnmadd.q "frm ← rm ; frd ← f128(frs1) × -f128(frs2) - f128(frs3)" 206 | fnmsub.q "frm ← rm ; frd ← f128(frs1) × -f128(frs2) + f128(frs3)" 207 | fadd.q "frm ← rm ; frd ← f128(frs1) + f128(frs2)" 208 | fsub.q "frm ← rm ; frd ← f128(frs1) - f128(frs2)" 209 | fmul.q "frm ← rm ; frd ← f128(frs1) × f128(frs2)" 210 | fdiv.q "frm ← rm ; frd ← f128(frs1) ÷ f128(frs2)" 211 | fsgnj.q "frd ← f128_copysign(f128(frs1), f128(frs2))" 212 | fsgnjn.q "frd ← f128_copysign(f128(frs1), -f128(frs2))" 213 | fsgnjx.q "frd ← f128_xorsign(f128(frs1), f128(frs2))" 214 | fmin.q "frd ← f128_min(f128(frs1), f128(frs2))" 215 | fmax.q "frd ← f128_max(f128(frs1), f128(frs2))" 216 | fcvt.s.q "frm ← rm ; frd ← f32(f128(frs1))" 217 | fcvt.q.s "frm ← rm ; frd ← f128(f32(frs1))" 218 | fcvt.d.q "frm ← rm ; frd ← f64(f128(frs1))" 219 | fcvt.q.d "frm ← rm ; frd ← f128(f64(frs1))" 220 | fsqrt.q "frm ← rm ; frd ← f128_sqrt(f128(frs1))" 221 | fle.q "if f128(frs1) ≤ f128(frs2) then rd ← 1 else rd ← 0" 222 | flt.q "if f128(frs1) < f128(frs2) then rd ← 1 else rd ← 0" 223 | feq.q "if f128(frs1) = f128(frs2) then rd ← 1 else rd ← 0" 224 | fcvt.w.q "frm ← rm ; rd ← s32(f128(frs1))" 225 | fcvt.wu.q "frm ← rm ; if f128(frs1) > 0 then rd ← u32(f128(frs1) else rd ← 0" 226 | fcvt.q.w "frm ← rm ; frd ← f128(s32(rs1))" 227 | fcvt.q.wu "frm ← rm ; frd ← f128(u32(rs1))" 228 | fclass.q "rd ← rd ← f128_classify(f128(frs1))" 229 | 230 | # RV64Q "RV64Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV32Q)" 231 | 232 | fcvt.l.q "frm ← rm ; rd ← s64(f128(frs1))" 233 | fcvt.lu.q "frm ← rm ; if f128(frs1) > 0 then rd ← u64(f128(frs1) else rd ← 0" 234 | fcvt.q.l "frm ← rm ; frd ← f128(u64(rs1))" 235 | fcvt.q.lu "frm ← rm ; frd ← f128(s64(rs1))" 236 | 237 | # RV128Q "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)" 238 | 239 | fmv.x.q "rd ← s64(frs1)" 240 | fmv.q.x "frd ← u64(rs1)" 241 | 242 | # RV32FD "RV32F and RV32D Common Floating-Point Instructions" 243 | 244 | frcsr 245 | frrm 246 | frflags 247 | fscsr 248 | fsrm 249 | fsflags 250 | fsrmi 251 | fsflagsi 252 | -------------------------------------------------------------------------------- /opcode-pseudocode-c: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # "" 3 | 4 | # RV32I "RV32I Base Integer Instruction Set" 5 | 6 | lui "rd = imm" 7 | auipc "rd = pc + imm" 8 | jal "rd = pc + length(inst); pc_offset = imm" 9 | jalr "ux new_offset = (rs1 + imm - pc) & ~1; rd = pc + length(inst); pc_offset = new_offset" 10 | beq "if (sx(rs1) == sx(rs2)) pc_offset = imm" 11 | bne "if (sx(rs1) != sx(rs2)) pc_offset = imm" 12 | blt "if (sx(rs1) < sx(rs2)) pc_offset = imm" 13 | bge "if (sx(rs1) >= sx(rs2)) pc_offset = imm" 14 | bltu "if (ux(rs1) < ux(rs2)) pc_offset = imm" 15 | bgeu "if (ux(rs1) >= ux(rs2)) pc_offset = imm" 16 | lb "s8 t; mmu.load(rs1 + imm, t); rd = t" # rd = sx(*(s8*)ptr(rs1 + imm)) 17 | lh "s16 t; mmu.load(rs1 + imm, t); rd = t" # rd = sx(*(s16*)ptr(rs1 + imm)) 18 | lw "s32 t; mmu.load(rs1 + imm, t); rd = t" # rd = sx(*(s32*)ptr(rs1 + imm)) 19 | lbu "u8 t; mmu.load(rs1 + imm, t); rd = t" # rd = ux(*(u8*)ptr(rs1 + imm)) 20 | lhu "u16 t; mmu.load(rs1 + imm, t); rd = t" # rd = ux(*(u16*)ptr(rs1 + imm)) 21 | lwu "u32 t; mmu.load(rs1 + imm, t); rd = t" # rd = ux(*(u32*)ptr(rs1 + imm)) 22 | sb "mmu.store(rs1 + imm, s8(rs2))" # *((u8*)ptr(rs1 + imm)) = rs2 23 | sh "mmu.store(rs1 + imm, s16(rs2))" # *((u16*)ptr(rs1 + imm)) = rs2 24 | sw "mmu.store(rs1 + imm, s32(rs2))" # *((u32*)ptr(rs1 + imm)) = rs2 25 | addi "rd = sx(rs1) + sx(imm)" 26 | slti "rd = sx(rs1) < sx(imm)" 27 | sltiu "rd = ux(rs1) < ux(imm)" 28 | xori "rd = ux(rs1) ^ ux(imm)" 29 | ori "rd = ux(rs1) | ux(imm)" 30 | andi "rd = ux(rs1) & ux(imm)" 31 | slli "rd = ux(rs1) << imm" 32 | srli "rd = ux(rs1) >> imm" 33 | srai "rd = sx(rs1) >> imm" 34 | add "rd = sx(rs1) + sx(rs2)" 35 | sub "rd = sx(rs1) - sx(rs2)" 36 | sll "rd = ux(rs1) << (rs2 & 0b1111111)" # 7-bit mask for RV128I 37 | slt "rd = sx(rs1) < sx(rs2)" 38 | sltu "rd = ux(rs1) < ux(rs2)" 39 | xor "rd = ux(rs1) ^ ux(rs2)" 40 | srl "rd = ux(rs1) >> (rs2 & 0b1111111)" # 7-bit mask for RV128I 41 | sra "rd = sx(rs1) >> (rs2 & 0b1111111)" # 7-bit mask for RV128I 42 | or "rd = ux(rs1) | ux(rs2)" 43 | and "rd = ux(rs1) & ux(rs2)" 44 | fence "" 45 | fence.i "" 46 | 47 | # RV64I "RV64I Base Integer Instruction Set (in addition to RV32I)" 48 | 49 | ld "s64 t; mmu.load(rs1 + imm, t); rd = t" # rd = sx(*(s64*)ptr(rs1 + imm)) 50 | sd "mmu.store(rs1 + imm, s64(rs2))" # *(u64*)ptr(rs1 + imm) = rs2 51 | addiw "rd = s32(s32(rs1) + imm)" # clang requires -fwrapv 52 | slliw "rd = s32(u32(rs1) << imm)" 53 | srliw "rd = s32(u32(rs1) >> imm)" 54 | sraiw "rd = s32(rs1) >> imm" 55 | addw "rd = s32(s32(rs1) + s32(rs2))" # clang requires -fwrapv 56 | subw "rd = s32(s32(rs1) - s32(rs2))" # clang requires -fwrapv 57 | sllw "rd = s32(u32(rs1) << (rs2 & 0b11111))" 58 | srlw "rd = s32(u32(rs1) >> (rs2 & 0b11111))" 59 | sraw "rd = s32(s32(rs1) >> (rs2 & 0b11111))" 60 | 61 | # RV32M "RV32M Standard Extension for Integer Multiply and Divide" 62 | 63 | mul "rd = sx(rs1) * sx(rs2)" 64 | mulh "rd = riscv::mulh(sx(rs1), sx(rs2))" 65 | mulhsu "rd = riscv::mulhsu(sx(rs1), ux(rs2))" 66 | mulhu "rd = riscv::mulhu(ux(rs1), ux(rs2))" 67 | div "rd = sx(rs1) == sx(INT_MIN) && sx(rs2) == -1 ? sx(INT_MIN) : sx(rs2) == 0 ? -1 : sx(rs1) / sx(rs2)" 68 | divu "rd = sx(rs2) == 0 ? -1 : sx(ux(rs1) / ux(rs2))" 69 | rem "rd = sx(rs1) == sx(INT_MIN) && sx(rs2) == -1 ? 0 : sx(rs2) == 0 ? sx(rs1) : sx(rs1) % sx(rs2)" 70 | remu "rd = sx(rs2) == 0 ? sx(rs1) : sx(ux(rs1) % ux(rs2))" 71 | 72 | # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)" 73 | 74 | mulw "rd = s32(u32(rs1) * u32(rs2))" 75 | divw "rd = s32(rs1) == s32(INT_MIN) && s32(rs2) == -1 ? s32(INT_MIN) : s32(rs2) == 0 ? -1 : s32(rs1) / s32(rs2)" 76 | divuw "rd = s32(rs2) == 0 ? -1 : s32(u32(rs1) / u32(rs2))" 77 | remw "rd = s32(rs1) == s32(INT_MIN) && s32(rs2) == -1 ? 0 : s32(rs2) == 0 ? s32(rs1) : s32(rs1) % s32(rs2)" 78 | remuw "rd = s32(rs2) == 0 ? s32(rs1) : s32(u32(rs1) % u32(rs2))" 79 | 80 | # RV32A "RV32A Standard Extension for Atomic Instructions" 81 | 82 | lr.w "lr = rs1; s32 t; mmu.load(rs1, t); rd = t" 83 | sc.w "ux res = 0; if (lr != rs1) res = 1; else mmu.store(rs1, s32(rs2)); rd = res" 84 | amoswap.w "s32 t1, t2 = s32(rs2); mmu.amo(amoswap, rs1, t1, t2); rd = t1" 85 | amoadd.w "s32 t1, t2 = s32(rs2); mmu.amo(amoadd, rs1, t1, t2); rd = t1" 86 | amoxor.w "s32 t1, t2 = s32(rs2); mmu.amo(amoxor, rs1, t1, t2); rd = t1" 87 | amoor.w "s32 t1, t2 = s32(rs2); mmu.amo(amoor, rs1, t1, t2); rd = t1" 88 | amoand.w "s32 t1, t2 = s32(rs2); mmu.amo(amoand, rs1, t1, t2); rd = t1" 89 | amomin.w "s32 t1, t2 = s32(rs2); mmu.amo(amomin, rs1, t1, t2); rd = t1" 90 | amomax.w "s32 t1, t2 = s32(rs2); mmu.amo(amomax, rs1, t1, t2); rd = t1" 91 | amominu.w "s32 t1, t2 = s32(rs2); mmu.amo(amominu, rs1, t1, t2); rd = t1" 92 | amomaxu.w "s32 t1, t2 = s32(rs2); mmu.amo(amomaxu, rs1, t1, t2); rd = t1" 93 | 94 | # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" 95 | 96 | lr.d "lr = rs1; s64 t; mmu.load(rs1, t); rd = t" 97 | sc.d "ux res = 0; if (lr != rs1) res = 1; else mmu.store(rs1, s64(rs2)); rd = res" 98 | amoswap.d "s64 t1, t2 = s64(rs2); mmu.amo(amoswap, rs1, t1, t2); rd = t1" 99 | amoadd.d "s64 t1, t2 = s64(rs2); mmu.amo(amoadd, rs1, t1, t2); rd = t1" 100 | amoxor.d "s64 t1, t2 = s64(rs2); mmu.amo(amoxor, rs1, t1, t2); rd = t1" 101 | amoor.d "s64 t1, t2 = s64(rs2); mmu.amo(amoor, rs1, t1, t2); rd = t1" 102 | amoand.d "s64 t1, t2 = s64(rs2); mmu.amo(amoand, rs1, t1, t2); rd = t1" 103 | amomin.d "s64 t1, t2 = s64(rs2); mmu.amo(amomin, rs1, t1, t2); rd = t1" 104 | amomax.d "s64 t1, t2 = s64(rs2); mmu.amo(amomax, rs1, t1, t2); rd = t1" 105 | amominu.d "s64 t1, t2 = s64(rs2); mmu.amo(amominu, rs1, t1, t2); rd = t1" 106 | amomaxu.d "s64 t1, t2 = s64(rs2); mmu.amo(amomaxu, rs1, t1, t2); rd = t1" 107 | 108 | # RV32S "RV32S Standard Extension for Supervisor-level Instructions" 109 | 110 | ecall 111 | ebreak 112 | uret 113 | sret 114 | hret 115 | mret 116 | dret 117 | sfence.vm 118 | wfi 119 | rdcycle 120 | rdtime 121 | rdinstret 122 | rdcycleh 123 | rdtimeh 124 | rdinstreth 125 | csrrw 126 | csrrs 127 | csrrc 128 | csrrwi 129 | csrrsi 130 | csrrci 131 | 132 | # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" 133 | 134 | flw "u32 t; mmu.load(rs1 + imm, t); u32(frd) = t" # f32(frd) = *(f32*)ptr(rs1 + imm) 135 | fsw "mmu.store(rs1 + imm, f32(frs2))" # *(f32*)ptr(rs1 + imm) = f32(frs2) 136 | fmadd.s "fenv_setrm(rm); f32(frd) = f32(frs1) * f32(frs2) + f32(frs3)" # -mfma 137 | fmsub.s "fenv_setrm(rm); f32(frd) = f32(frs1) * f32(frs2) - f32(frs3)" 138 | fnmadd.s "fenv_setrm(rm); f32(frd) = f32(frs1) * -f32(frs2) - f32(frs3)" 139 | fnmsub.s "fenv_setrm(rm); f32(frd) = f32(frs1) * -f32(frs2) + f32(frs3)" 140 | fadd.s "fenv_setrm(rm); f32(frd) = f32(frs1) + f32(frs2)" 141 | fsub.s "fenv_setrm(rm); f32(frd) = f32(frs1) - f32(frs2)" 142 | fmul.s "fenv_setrm(rm); f32(frd) = f32(frs1) * f32(frs2)" 143 | fdiv.s "fenv_setrm(rm); f32(frd) = f32(frs1) / f32(frs2)" 144 | fsgnj.s "u32(frd) = (u32(frs1) & u32(~(1U<<31))) | (u32(frs2) & u32(1U<<31))" 145 | fsgnjn.s "u32(frd) = (u32(frs1) & u32(~(1U<<31))) | (~u32(frs2) & u32(1U<<31))" 146 | fsgnjx.s "u32(frd) = u32(frs1) ^ (u32(frs2) & u32(1U<<31))" 147 | fmin.s "f32(frd) = (f32(frs1) < f32(frs2)) || isnan(f32(frs2)) ? f32(frs1) : f32(frs2)" 148 | fmax.s "f32(frd) = (f32(frs1) > f32(frs2)) || isnan(f32(frs2)) ? f32(frs1) : f32(frs2)" 149 | fsqrt.s "fenv_setrm(rm); f32(frd) = riscv::f32_sqrt(f32(frs1))" 150 | fle.s "rd = f32(frs1) <= f32(frs2)" 151 | flt.s "rd = f32(frs1) < f32(frs2)" 152 | feq.s "rd = f32(frs1) == f32(frs2)" 153 | fcvt.w.s "fenv_setrm(rm); rd = riscv::fcvt_w(fcsr, f32(frs1))" # s32(f32(frs1)) 154 | fcvt.wu.s "fenv_setrm(rm); rd = riscv::fcvt_wu(fcsr, f32(frs1))" # s32(u32(f32(frs1))) 155 | fcvt.s.w "fenv_setrm(rm); f32(frd) = f32(s32(rs1))" 156 | fcvt.s.wu "fenv_setrm(rm); f32(frd) = f32(u32(rs1))" 157 | fmv.x.s "rd = isnan(f32(frs1)) ? s32(u32(f32(NAN))) : s32(frs1)" # s32(frs1) 158 | fclass.s "rd = f32_classify(f32(frs1))" 159 | fmv.s.x "u32(frd) = u32(rs1)" 160 | 161 | # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" 162 | 163 | fcvt.l.s "fenv_setrm(rm); rd = riscv::fcvt_l(fcsr, f32(frs1))" # s64(f32(frs1)) 164 | fcvt.lu.s "fenv_setrm(rm); rd = riscv::fcvt_lu(fcsr, f32(frs1))" # s64(u32(f32(frs1))) 165 | fcvt.s.l "fenv_setrm(rm); f32(frd) = f32(s64(rs1))" 166 | fcvt.s.lu "fenv_setrm(rm); f32(frd) = f32(u64(rs1))" 167 | 168 | # RV32D "RV32D Standard Extension for Double-Precision Floating-Point" 169 | 170 | fld "u64 t; mmu.load(rs1 + imm, t); u64(frd) = t" # f64(frd) = *(f64*)ptr(rs1 + imm) 171 | fsd "mmu.store(rs1 + imm, f64(frs2))" # *(f64*)ptr(rs1 + imm) = f64(frs2) 172 | fmadd.d "fenv_setrm(rm); f64(frd) = f64(frs1) * f64(frs2) + f64(frs3)" 173 | fmsub.d "fenv_setrm(rm); f64(frd) = f64(frs1) * f64(frs2) - f64(frs3)" 174 | fnmadd.d "fenv_setrm(rm); f64(frd) = f64(frs1) * -f64(frs2) - f64(frs3)" 175 | fnmsub.d "fenv_setrm(rm); f64(frd) = f64(frs1) * -f64(frs2) + f64(frs3)" 176 | fadd.d "fenv_setrm(rm); f64(frd) = f64(frs1) + f64(frs2)" 177 | fsub.d "fenv_setrm(rm); f64(frd) = f64(frs1) - f64(frs2)" 178 | fmul.d "fenv_setrm(rm); f64(frd) = f64(frs1) * f64(frs2)" 179 | fdiv.d "fenv_setrm(rm); f64(frd) = f64(frs1) / f64(frs2)" 180 | fsgnj.d "u64(frd) = (u64(frs1) & u64(~(1ULL<<63))) | (u64(frs2) & u64(1ULL<<63))" 181 | fsgnjn.d "u64(frd) = (u64(frs1) & u64(~(1ULL<<63))) | (~u64(frs2) & u64(1ULL<<63))" 182 | fsgnjx.d "u64(frd) = u64(frs1) ^ (u64(frs2) & u64(1ULL<<63))" 183 | fmin.d "f64(frd) = (f64(frs1) < f64(frs2)) || isnan(f64(frs2)) ? f64(frs1) : f64(frs2)" 184 | fmax.d "f64(frd) = (f64(frs1) > f64(frs2)) || isnan(f64(frs2)) ? f64(frs1) : f64(frs2)" 185 | fcvt.s.d "fenv_setrm(rm); f32(frd) = f32(f64(frs1))" 186 | fcvt.d.s "fenv_setrm(rm); f64(frd) = f64(f32(frs1))" 187 | fsqrt.d "fenv_setrm(rm); f64(frd) = riscv::f64_sqrt(f64(frs1))" 188 | fle.d "rd = f64(frs1) <= f64(frs2)" 189 | flt.d "rd = f64(frs1) < f64(frs2)" 190 | feq.d "rd = f64(frs1) == f64(frs2)" 191 | fcvt.w.d "fenv_setrm(rm); rd = riscv::fcvt_w(fcsr, f64(frs1))" # s32(f64(frs1)) 192 | fcvt.wu.d "fenv_setrm(rm); rd = riscv::fcvt_wu(fcsr, f64(frs1))" # s32(u32(f64(frs1))) 193 | fcvt.d.w "fenv_setrm(rm); f64(frd) = f64(s32(rs1))" 194 | fcvt.d.wu "fenv_setrm(rm); f64(frd) = f64(u32(rs1))" 195 | fclass.d "rd = f64_classify(f64(frs1))" 196 | 197 | # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32F)" 198 | 199 | fcvt.l.d "fenv_setrm(rm); rd = riscv::fcvt_l(fcsr, f64(frs1))" # s64(f64(frs1)) 200 | fcvt.lu.d "fenv_setrm(rm); rd = riscv::fcvt_lu(fcsr, f64(frs1))" # s64(u64(f64(frs1))) 201 | fmv.x.d "rd = isnan(f64(frs1)) ? s64(u64(f64(NAN))) : s64(frs1)" # s64(frs1) 202 | fcvt.d.l "fenv_setrm(rm); f64(frd) = f64(s64(rs1))" 203 | fcvt.d.lu "fenv_setrm(rm); f64(frd) = f64(u64(rs1))" 204 | fmv.d.x "u64(frd) = u64(rs1)" 205 | 206 | # RV32FD "RV32F and RV32D Common Floating-Point Instructions" 207 | 208 | frcsr 209 | frrm 210 | frflags 211 | fscsr 212 | fsrm 213 | fsflags 214 | fsrmi 215 | fsflagsi 216 | -------------------------------------------------------------------------------- /opcodes: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # [ ...] 3 | # 4 | # is one of rd, rs1, rs2, frd, frs1, frs2, frs3, imm20, imm12, 5 | # sbimm12, simm12, shamt5, shamt6, rm, aq, rl, pred, succ 6 | # 7 | # is given by specifying one or more range/value pairs: 8 | # hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1) 9 | # 10 | # is one of r, i, s, sb, u, uj, ... 11 | # 12 | # is one of { rv32, rv64, rv128 } · { i, m, a, f, d, s, c } 13 | 14 | # RV32I "RV32I Base Integer Instruction Set" 15 | 16 | lui rd imm20 6..2=0x0D 1..0=3 u rv32i rv64i rv128i 17 | auipc rd oimm20 6..2=0x05 1..0=3 u+o rv32i rv64i rv128i 18 | jal rd jimm20 6..2=0x1b 1..0=3 uj rv32i rv64i rv128i 19 | jalr rd rs1 oimm12 14..12=0 6..2=0x19 1..0=3 i+o rv32i rv64i rv128i 20 | beq rs1 rs2 sbimm12 14..12=0 6..2=0x18 1..0=3 sb rv32i rv64i rv128i 21 | bne rs1 rs2 sbimm12 14..12=1 6..2=0x18 1..0=3 sb rv32i rv64i rv128i 22 | blt rs1 rs2 sbimm12 14..12=4 6..2=0x18 1..0=3 sb rv32i rv64i rv128i 23 | bge rs1 rs2 sbimm12 14..12=5 6..2=0x18 1..0=3 sb rv32i rv64i rv128i 24 | bltu rs1 rs2 sbimm12 14..12=6 6..2=0x18 1..0=3 sb rv32i rv64i rv128i 25 | bgeu rs1 rs2 sbimm12 14..12=7 6..2=0x18 1..0=3 sb rv32i rv64i rv128i 26 | lb rd rs1 oimm12 14..12=0 6..2=0x00 1..0=3 i+l rv32i rv64i rv128i 27 | lh rd rs1 oimm12 14..12=1 6..2=0x00 1..0=3 i+l rv32i rv64i rv128i 28 | lw rd rs1 oimm12 14..12=2 6..2=0x00 1..0=3 i+l rv32i rv64i rv128i 29 | lbu rd rs1 oimm12 14..12=4 6..2=0x00 1..0=3 i+l rv32i rv64i rv128i 30 | lhu rd rs1 oimm12 14..12=5 6..2=0x00 1..0=3 i+l rv32i rv64i rv128i 31 | sb rs1 rs2 simm12 14..12=0 6..2=0x08 1..0=3 s rv32i rv64i rv128i 32 | sh rs1 rs2 simm12 14..12=1 6..2=0x08 1..0=3 s rv32i rv64i rv128i 33 | sw rs1 rs2 simm12 14..12=2 6..2=0x08 1..0=3 s rv32i rv64i rv128i 34 | addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3 i rv32i rv64i rv128i 35 | slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3 i rv32i rv64i rv128i 36 | sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3 i rv32i rv64i rv128i 37 | xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3 i rv32i rv64i rv128i 38 | ori rd rs1 imm12 14..12=6 6..2=0x04 1..0=3 i rv32i rv64i rv128i 39 | andi rd rs1 imm12 14..12=7 6..2=0x04 1..0=3 i rv32i rv64i rv128i 40 | slli rd rs1 shamt5 31..27=0 14..12=1 6..2=0x04 1..0=3 i·sh5 rv32i 41 | srli rd rs1 shamt5 31..27=0 14..12=5 6..2=0x04 1..0=3 i·sh5 rv32i 42 | srai rd rs1 shamt5 31..27=8 14..12=5 6..2=0x04 1..0=3 i·sh5 rv32i 43 | add rd rs1 rs2 31..25=0 14..12=0 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 44 | sub rd rs1 rs2 31..25=32 14..12=0 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 45 | sll rd rs1 rs2 31..25=0 14..12=1 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 46 | slt rd rs1 rs2 31..25=0 14..12=2 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 47 | sltu rd rs1 rs2 31..25=0 14..12=3 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 48 | xor rd rs1 rs2 31..25=0 14..12=4 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 49 | srl rd rs1 rs2 31..25=0 14..12=5 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 50 | sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 51 | or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 52 | and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 r rv32i rv64i rv128i 53 | fence 31..28=ignore pred succ 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3 r·f rv32i rv64i rv128i 54 | fence.i 31..28=ignore 27..20=ignore 19..15=ignore 14..12=1 11..7=ignore 6..2=0x03 1..0=3 none rv32i rv64i rv128i 55 | 56 | # RV64I "RV64I Base Integer Instruction Set (in addition to RV32I)" 57 | 58 | lwu rd rs1 oimm12 14..12=6 6..2=0x00 1..0=3 i+l rv64i rv128i 59 | ld rd rs1 oimm12 14..12=3 6..2=0x00 1..0=3 i+l rv64i rv128i 60 | sd rs1 rs2 simm12 14..12=3 6..2=0x08 1..0=3 s rv64i rv128i 61 | slli rd rs1 shamt6 31..27=0 14..12=1 6..2=0x04 1..0=3 i·sh6 rv64i 62 | srli rd rs1 shamt6 31..27=0 14..12=5 6..2=0x04 1..0=3 i·sh6 rv64i 63 | srai rd rs1 shamt6 31..27=8 14..12=5 6..2=0x04 1..0=3 i·sh6 rv64i 64 | addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 i rv64i rv128i 65 | slliw rd rs1 shamt5 31..25=0 14..12=1 6..2=0x06 1..0=3 i·sh5 rv64i rv128i 66 | srliw rd rs1 shamt5 31..25=0 14..12=5 6..2=0x06 1..0=3 i·sh5 rv64i rv128i 67 | sraiw rd rs1 shamt5 31..25=32 14..12=5 6..2=0x06 1..0=3 i·sh5 rv64i rv128i 68 | addw rd rs1 rs2 31..25=0 14..12=0 6..2=0x0E 1..0=3 r rv64i rv128i 69 | subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 r rv64i rv128i 70 | sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 r rv64i rv128i 71 | srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 r rv64i rv128i 72 | sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 r rv64i rv128i 73 | 74 | # RV128I "RV128I Base Integer Instruction Set (in addition to RV64I)" 75 | 76 | ldu rd rs1 oimm12 14..12=7 6..2=0x00 1..0=3 i+l rv128i 77 | lq rd rs1 oimm12 14..12=2 6..2=0x03 1..0=3 i+l rv128i 78 | sq rs1 rs2 simm12 14..12=4 6..2=0x08 1..0=3 s rv128i 79 | slli rd rs1 shamt7 31..27=0 14..12=1 6..2=0x04 1..0=3 i·sh7 rv128i 80 | srli rd rs1 shamt7 31..27=0 14..12=5 6..2=0x04 1..0=3 i·sh7 rv128i 81 | srai rd rs1 shamt7 31..27=8 14..12=5 6..2=0x04 1..0=3 i·sh7 rv128i 82 | addid rd rs1 imm12 14..12=0 6..2=0x16 1..0=3 i rv128i 83 | sllid rd rs1 shamt6 31..26=0 14..12=1 6..2=0x16 1..0=3 i·sh6 rv128i 84 | srlid rd rs1 shamt6 31..26=0 14..12=5 6..2=0x16 1..0=3 i·sh6 rv128i 85 | sraid rd rs1 shamt6 31..26=16 14..12=5 6..2=0x16 1..0=3 i·sh6 rv128i 86 | addd rd rs1 rs2 31..25=0 14..12=0 6..2=0x1E 1..0=3 r rv128i 87 | subd rd rs1 rs2 31..25=32 14..12=0 6..2=0x1E 1..0=3 r rv128i 88 | slld rd rs1 rs2 31..25=0 14..12=1 6..2=0x1E 1..0=3 r rv128i 89 | srld rd rs1 rs2 31..25=0 14..12=5 6..2=0x1E 1..0=3 r rv128i 90 | srad rd rs1 rs2 31..25=32 14..12=5 6..2=0x1E 1..0=3 r rv128i 91 | 92 | # RV32M "RV32M Standard Extension for Integer Multiply and Divide" 93 | 94 | mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 r rv32m rv64m rv128m 95 | mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 r rv32m rv64m rv128m 96 | mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 r rv32m rv64m rv128m 97 | mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 r rv32m rv64m rv128m 98 | div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 r rv32m rv64m rv128m 99 | divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 r rv32m rv64m rv128m 100 | rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 r rv32m rv64m rv128m 101 | remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 r rv32m rv64m rv128m 102 | 103 | # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)" 104 | 105 | mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 r rv64m rv128m 106 | divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 r rv64m rv128m 107 | divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 r rv64m rv128m 108 | remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 r rv64m rv128m 109 | remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 r rv64m rv128m 110 | 111 | # RV128M "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)" 112 | 113 | muld rd rs1 rs2 31..25=1 14..12=0 6..2=0x1E 1..0=3 r rv128m 114 | divd rd rs1 rs2 31..25=1 14..12=4 6..2=0x1E 1..0=3 r rv128m 115 | divud rd rs1 rs2 31..25=1 14..12=5 6..2=0x1E 1..0=3 r rv128m 116 | remd rd rs1 rs2 31..25=1 14..12=6 6..2=0x1E 1..0=3 r rv128m 117 | remud rd rs1 rs2 31..25=1 14..12=7 6..2=0x1E 1..0=3 r rv128m 118 | 119 | # RV32A "RV32A Standard Extension for Atomic Instructions" 120 | 121 | lr.w rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3 r·l rv32a rv64a rv128a 122 | sc.w rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 123 | amoswap.w rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 124 | amoadd.w rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 125 | amoxor.w rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 126 | amoor.w rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 127 | amoand.w rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 128 | amomin.w rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 129 | amomax.w rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 130 | amominu.w rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 131 | amomaxu.w rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3 r·a rv32a rv64a rv128a 132 | 133 | # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" 134 | 135 | lr.d rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 r·l rv64a rv128a 136 | sc.d rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 137 | amoswap.d rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 138 | amoadd.d rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 139 | amoxor.d rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 140 | amoor.d rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 141 | amoand.d rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 142 | amomin.d rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 143 | amomax.d rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 144 | amominu.d rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 145 | amomaxu.d rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=3 6..2=0x0B 1..0=3 r·a rv64a rv128a 146 | 147 | # RV128A "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)" 148 | 149 | lr.q rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=4 6..2=0x0B 1..0=3 r·l rv128a 150 | sc.q rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 151 | amoswap.q rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 152 | amoadd.q rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 153 | amoxor.q rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 154 | amoor.q rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 155 | amoand.q rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 156 | amomin.q rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 157 | amomax.q rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 158 | amominu.q rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 159 | amomaxu.q rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=4 6..2=0x0B 1..0=3 r·a rv128a 160 | 161 | # RV32S "RV32S Standard Extension for Supervisor-level Instructions" 162 | 163 | ecall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 none rv32s rv64s rv128s 164 | ebreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 none rv32s rv64s rv128s 165 | uret 11..7=0 19..15=0 31..20=0x002 14..12=0 6..2=0x1C 1..0=3 none rv32s rv64s rv128s 166 | sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 none rv32s rv64s rv128s 167 | hret 11..7=0 19..15=0 31..20=0x202 14..12=0 6..2=0x1C 1..0=3 none rv32s rv64s rv128s 168 | mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 none rv32s rv64s rv128s 169 | dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 none rv32s rv64s rv128s 170 | sfence.vm 11..7=0 rs1 31..20=0x104 14..12=0 6..2=0x1C 1..0=3 r+sf rv32s rv64s rv128s 171 | sfence.vma 11..7=0 rs1 rs2 31..25=0x009 14..12=0 6..2=0x1C 1..0=3 r+sfa rv32s rv64s rv128s 172 | wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 none rv32s rv64s rv128s 173 | #rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3 i·csr rv32s rv64s rv128s 174 | #rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3 i·csr rv32s rv64s rv128s 175 | #rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3 i·csr rv32s rv64s rv128s 176 | #rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3 i·csr rv32s 177 | #rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3 i·csr rv32s 178 | #rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3 i·csr rv32s 179 | csrrw rd rs1 csr12 14..12=1 6..2=0x1C 1..0=3 i·csr rv32s rv64s rv128s 180 | csrrs rd rs1 csr12 14..12=2 6..2=0x1C 1..0=3 i·csr rv32s rv64s rv128s 181 | csrrc rd rs1 csr12 14..12=3 6..2=0x1C 1..0=3 i·csr rv32s rv64s rv128s 182 | csrrwi rd zimm csr12 14..12=5 6..2=0x1C 1..0=3 i·csr+i rv32s rv64s rv128s 183 | csrrsi rd zimm csr12 14..12=6 6..2=0x1C 1..0=3 i·csr+i rv32s rv64s rv128s 184 | csrrci rd zimm csr12 14..12=7 6..2=0x1C 1..0=3 i·csr+i rv32s rv64s rv128s 185 | 186 | # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" 187 | 188 | flw frd rs1 oimm12 14..12=2 6..2=0x01 1..0=3 i+lf rv32f rv64f rv128f 189 | fsw rs1 frs2 simm12 14..12=2 6..2=0x09 1..0=3 s+f rv32f rv64f rv128f 190 | fmadd.s frd frs1 frs2 frs3 rm 26..25=0 6..2=0x10 1..0=3 r4·m rv32f rv64f rv128f 191 | fmsub.s frd frs1 frs2 frs3 rm 26..25=0 6..2=0x11 1..0=3 r4·m rv32f rv64f rv128f 192 | fnmsub.s frd frs1 frs2 frs3 rm 26..25=0 6..2=0x12 1..0=3 r4·m rv32f rv64f rv128f 193 | fnmadd.s frd frs1 frs2 frs3 rm 26..25=0 6..2=0x13 1..0=3 r4·m rv32f rv64f rv128f 194 | fadd.s frd frs1 frs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 r·m+3f rv32f rv64f rv128f 195 | fsub.s frd frs1 frs2 31..27=0x01 rm 26..25=0 6..2=0x14 1..0=3 r·m+3f rv32f rv64f rv128f 196 | fmul.s frd frs1 frs2 31..27=0x02 rm 26..25=0 6..2=0x14 1..0=3 r·m+3f rv32f rv64f rv128f 197 | fdiv.s frd frs1 frs2 31..27=0x03 rm 26..25=0 6..2=0x14 1..0=3 r·m+3f rv32f rv64f rv128f 198 | fsgnj.s frd frs1 frs2 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 r+3f rv32f rv64f rv128f 199 | fsgnjn.s frd frs1 frs2 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 r+3f rv32f rv64f rv128f 200 | fsgnjx.s frd frs1 frs2 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 r+3f rv32f rv64f rv128f 201 | fmin.s frd frs1 frs2 31..27=0x05 14..12=0 26..25=0 6..2=0x14 1..0=3 r+3f rv32f rv64f rv128f 202 | fmax.s frd frs1 frs2 31..27=0x05 14..12=1 26..25=0 6..2=0x14 1..0=3 r+3f rv32f rv64f rv128f 203 | fsqrt.s frd frs1 24..20=0 31..27=0x0B rm 26..25=0 6..2=0x14 1..0=3 r·m+ff rv32f rv64f rv128f 204 | fle.s rd frs1 frs2 31..27=0x14 14..12=0 26..25=0 6..2=0x14 1..0=3 r+rff rv32f rv64f rv128f 205 | flt.s rd frs1 frs2 31..27=0x14 14..12=1 26..25=0 6..2=0x14 1..0=3 r+rff rv32f rv64f rv128f 206 | feq.s rd frs1 frs2 31..27=0x14 14..12=2 26..25=0 6..2=0x14 1..0=3 r+rff rv32f rv64f rv128f 207 | fcvt.w.s rd frs1 24..20=0 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 r·m+rf rv32f rv64f rv128f 208 | fcvt.wu.s rd frs1 24..20=1 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 r·m+rf rv32f rv64f rv128f 209 | fcvt.s.w frd rs1 24..20=0 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 r·m+fr rv32f rv64f rv128f 210 | fcvt.s.wu frd rs1 24..20=1 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 r·m+fr rv32f rv64f rv128f 211 | fmv.x.s rd frs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 r+rf rv32f rv64f rv128f 212 | fclass.s rd frs1 24..20=0 31..27=0x1C 14..12=1 26..25=0 6..2=0x14 1..0=3 r+rf rv32f rv64f rv128f 213 | fmv.s.x frd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 r+fr rv32f rv64f rv128f 214 | 215 | # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" 216 | 217 | fcvt.l.s rd frs1 24..20=2 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 r·m+rf rv64f rv128f 218 | fcvt.lu.s rd frs1 24..20=3 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 r·m+rf rv64f rv128f 219 | fcvt.s.l frd rs1 24..20=2 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 r·m+fr rv64f rv128f 220 | fcvt.s.lu frd rs1 24..20=3 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 r·m+fr rv64f rv128f 221 | 222 | # RV32D "RV32D Standard Extension for Double-Precision Floating-Point" 223 | 224 | fld frd rs1 oimm12 14..12=3 6..2=0x01 1..0=3 i+lf rv32d rv64d rv128d 225 | fsd rs1 frs2 simm12 14..12=3 6..2=0x09 1..0=3 s+f rv32d rv64d rv128d 226 | fmadd.d frd frs1 frs2 frs3 rm 26..25=1 6..2=0x10 1..0=3 r4·m rv32d rv64d rv128d 227 | fmsub.d frd frs1 frs2 frs3 rm 26..25=1 6..2=0x11 1..0=3 r4·m rv32d rv64d rv128d 228 | fnmsub.d frd frs1 frs2 frs3 rm 26..25=1 6..2=0x12 1..0=3 r4·m rv32d rv64d rv128d 229 | fnmadd.d frd frs1 frs2 frs3 rm 26..25=1 6..2=0x13 1..0=3 r4·m rv32d rv64d rv128d 230 | fadd.d frd frs1 frs2 31..27=0x00 rm 26..25=1 6..2=0x14 1..0=3 r·m+3f rv32d rv64d rv128d 231 | fsub.d frd frs1 frs2 31..27=0x01 rm 26..25=1 6..2=0x14 1..0=3 r·m+3f rv32d rv64d rv128d 232 | fmul.d frd frs1 frs2 31..27=0x02 rm 26..25=1 6..2=0x14 1..0=3 r·m+3f rv32d rv64d rv128d 233 | fdiv.d frd frs1 frs2 31..27=0x03 rm 26..25=1 6..2=0x14 1..0=3 r·m+3f rv32d rv64d rv128d 234 | fsgnj.d frd frs1 frs2 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 r+3f rv32d rv64d rv128d 235 | fsgnjn.d frd frs1 frs2 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 r+3f rv32d rv64d rv128d 236 | fsgnjx.d frd frs1 frs2 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 r+3f rv32d rv64d rv128d 237 | fmin.d frd frs1 frs2 31..27=0x05 14..12=0 26..25=1 6..2=0x14 1..0=3 r+3f rv32d rv64d rv128d 238 | fmax.d frd frs1 frs2 31..27=0x05 14..12=1 26..25=1 6..2=0x14 1..0=3 r+3f rv32d rv64d rv128d 239 | fcvt.s.d frd frs1 24..20=1 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 r·m+ff rv32d rv64d rv128d 240 | fcvt.d.s frd frs1 24..20=0 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 r·m+ff rv32d rv64d rv128d 241 | fsqrt.d frd frs1 24..20=0 31..27=0x0B rm 26..25=1 6..2=0x14 1..0=3 r·m+ff rv32d rv64d rv128d 242 | fle.d rd frs1 frs2 31..27=0x14 14..12=0 26..25=1 6..2=0x14 1..0=3 r+rff rv32d rv64d rv128d 243 | flt.d rd frs1 frs2 31..27=0x14 14..12=1 26..25=1 6..2=0x14 1..0=3 r+rff rv32d rv64d rv128d 244 | feq.d rd frs1 frs2 31..27=0x14 14..12=2 26..25=1 6..2=0x14 1..0=3 r+rff rv32d rv64d rv128d 245 | fcvt.w.d rd frs1 24..20=0 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 r·m+rf rv32d rv64d rv128d 246 | fcvt.wu.d rd frs1 24..20=1 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 r·m+rf rv32d rv64d rv128d 247 | fcvt.d.w frd rs1 24..20=0 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 r·m+fr rv32d rv64d rv128d 248 | fcvt.d.wu frd rs1 24..20=1 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 r·m+fr rv32d rv64d rv128d 249 | fclass.d rd frs1 24..20=0 31..27=0x1C 14..12=1 26..25=1 6..2=0x14 1..0=3 r+rf rv32d rv64d rv128d 250 | 251 | # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)" 252 | 253 | fcvt.l.d rd frs1 24..20=2 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 r·m+rf rv64d rv128d 254 | fcvt.lu.d rd frs1 24..20=3 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 r·m+rf rv64d rv128d 255 | fmv.x.d rd frs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 r+rf rv64d rv128d 256 | fcvt.d.l frd rs1 24..20=2 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 r·m+fr rv64d rv128d 257 | fcvt.d.lu frd rs1 24..20=3 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 r·m+fr rv64d rv128d 258 | fmv.d.x frd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 r+fr rv64d rv128d 259 | 260 | # RV32Q "RV32Q Standard Extension for Quad-Precision Floating-Point" 261 | 262 | flq frd rs1 oimm12 14..12=4 6..2=0x01 1..0=3 i+lf rv32q rv64q rv128q 263 | fsq rs1 frs2 simm12 14..12=4 6..2=0x09 1..0=3 s+f rv32q rv64q rv128q 264 | fmadd.q frd frs1 frs2 frs3 rm 26..25=3 6..2=0x10 1..0=3 r4·m rv32q rv64q rv128q 265 | fmsub.q frd frs1 frs2 frs3 rm 26..25=3 6..2=0x11 1..0=3 r4·m rv32q rv64q rv128q 266 | fnmsub.q frd frs1 frs2 frs3 rm 26..25=3 6..2=0x12 1..0=3 r4·m rv32q rv64q rv128q 267 | fnmadd.q frd frs1 frs2 frs3 rm 26..25=3 6..2=0x13 1..0=3 r4·m rv32q rv64q rv128q 268 | fadd.q frd frs1 frs2 31..27=0x00 rm 26..25=3 6..2=0x14 1..0=3 r·m+3f rv32q rv64q rv128q 269 | fsub.q frd frs1 frs2 31..27=0x01 rm 26..25=3 6..2=0x14 1..0=3 r·m+3f rv32q rv64q rv128q 270 | fmul.q frd frs1 frs2 31..27=0x02 rm 26..25=3 6..2=0x14 1..0=3 r·m+3f rv32q rv64q rv128q 271 | fdiv.q frd frs1 frs2 31..27=0x03 rm 26..25=3 6..2=0x14 1..0=3 r·m+3f rv32q rv64q rv128q 272 | fsgnj.q frd frs1 frs2 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 r+3f rv32q rv64q rv128q 273 | fsgnjn.q frd frs1 frs2 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 r+3f rv32q rv64q rv128q 274 | fsgnjx.q frd frs1 frs2 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 r+3f rv32q rv64q rv128q 275 | fmin.q frd frs1 frs2 31..27=0x05 14..12=0 26..25=3 6..2=0x14 1..0=3 r+3f rv32q rv64q rv128q 276 | fmax.q frd frs1 frs2 31..27=0x05 14..12=1 26..25=3 6..2=0x14 1..0=3 r+3f rv32q rv64q rv128q 277 | fcvt.s.q frd frs1 24..20=3 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 r·m+ff rv32q rv64q rv128q 278 | fcvt.q.s frd frs1 24..20=0 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 r·m+ff rv32q rv64q rv128q 279 | fcvt.d.q frd frs1 24..20=3 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 r·m+ff rv32q rv64q rv128q 280 | fcvt.q.d frd frs1 24..20=1 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 r·m+ff rv32q rv64q rv128q 281 | fsqrt.q frd frs1 24..20=0 31..27=0x0B rm 26..25=3 6..2=0x14 1..0=3 r·m+ff rv32q rv64q rv128q 282 | fle.q rd frs1 frs2 31..27=0x14 14..12=0 26..25=3 6..2=0x14 1..0=3 r+rff rv32q rv64q rv128q 283 | flt.q rd frs1 frs2 31..27=0x14 14..12=1 26..25=3 6..2=0x14 1..0=3 r+rff rv32q rv64q rv128q 284 | feq.q rd frs1 frs2 31..27=0x14 14..12=2 26..25=3 6..2=0x14 1..0=3 r+rff rv32q rv64q rv128q 285 | fcvt.w.q rd frs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 r·m+rf rv32q rv64q rv128q 286 | fcvt.wu.q rd frs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 r·m+rf rv32q rv64q rv128q 287 | fcvt.q.w frd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 r·m+fr rv32q rv64q rv128q 288 | fcvt.q.wu frd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 r·m+fr rv32q rv64q rv128q 289 | fclass.q rd frs1 24..20=0 31..27=0x1C 14..12=1 26..25=3 6..2=0x14 1..0=3 r+rf rv32q rv64q rv128q 290 | 291 | # RV64Q "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)" 292 | 293 | fcvt.l.q rd frs1 24..20=2 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 r·m+rf rv64q rv128q 294 | fcvt.lu.q rd frs1 24..20=3 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 r·m+rf rv64q rv128q 295 | fcvt.q.l frd rs1 24..20=2 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 r·m+fr rv64q rv128q 296 | fcvt.q.lu frd rs1 24..20=3 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 r·m+fr rv64q rv128q 297 | 298 | # RV128Q "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)" 299 | 300 | fmv.x.q rd frs1 24..20=0 31..27=0x1C 14..12=0 26..25=3 6..2=0x14 1..0=3 r+rf rv64q rv128q 301 | fmv.q.x frd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=3 6..2=0x14 1..0=3 r+fr rv64q rv128q 302 | 303 | # RV32FD "RV32F and RV32D žommon Floating-Point Instructions" 304 | 305 | #frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 i·csr rv32f rv64f rv128f 306 | #frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 i·csr rv32f rv64f rv128f 307 | #frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 i·csr rv32f rv64f rv128f 308 | #fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 i·csr rv32f rv64f rv128f 309 | #fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 i·csr rv32f rv64f rv128f 310 | #fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 i·csr rv32f rv64f rv128f 311 | #fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 i·csri rv32f rv64f rv128f 312 | #fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 i·csri rv32f rv64f rv128f 313 | 314 | # RV32C "RV32C Standard Extension for Compressed Instructions" 315 | 316 | c.addi4spn crdq cimm4spn 1..0=0 15..13=0 ciw·4spn rv32c rv64c 317 | c.fld cfrdq crs1q cimmd 1..0=0 15..13=1 cl·ld+f rv32c rv64c 318 | c.lw crdq crs1q cimmw 1..0=0 15..13=2 cl·lw rv32c rv64c 319 | c.flw cfrdq crs1q cimmw 1..0=0 15..13=3 cl·lw+f rv32c 320 | c.fsd crs1q cfrs2q cimmd 1..0=0 15..13=5 cs·sd+f rv32c rv64c 321 | c.sw crs1q crs2q cimmw 1..0=0 15..13=6 cs·sw rv32c rv64c 322 | c.fsw crs1q cfrs2q cimmw 1..0=0 15..13=7 cs·sw+f rv32c 323 | c.nop 1..0=1 15..13=0 12=0 11..7=0 6..2=0 ci·none rv32c rv64c 324 | c.addi crs1rd cnzimmi 1..0=1 15..13=0 ci rv32c rv64c 325 | c.jal cimmj 1..0=1 15..13=1 cj·jal rv32c 326 | c.li crs1rd cimmi 1..0=1 15..13=2 ci·li rv32c rv64c 327 | c.addi16sp crs1rd cimm16sp 1..0=1 15..13=3 11..7=2 ci·16sp rv32c rv64c 328 | c.lui crd cimmui 1..0=1 15..13=3 ci·lui rv32c rv64c 329 | c.srli crs1rdq cimmsh5 1..0=1 15..13=4 11..10=0 cb·sh5 rv32c 330 | c.srai crs1rdq cimmsh5 1..0=1 15..13=4 11..10=1 cb·sh5 rv32c 331 | c.andi crs1rdq cnzimmi 1..0=1 15..13=4 11..10=2 cb·imm rv32c rv64c 332 | c.sub crs1rdq crs2q 1..0=1 15..13=4 12=0 11..10=3 6..5=0 cs rv32c rv64c 333 | c.xor crs1rdq crs2q 1..0=1 15..13=4 12=0 11..10=3 6..5=1 cs rv32c rv64c 334 | c.or crs1rdq crs2q 1..0=1 15..13=4 12=0 11..10=3 6..5=2 cs rv32c rv64c 335 | c.and crs1rdq crs2q 1..0=1 15..13=4 12=0 11..10=3 6..5=3 cs rv32c rv64c 336 | c.subw crs1rdq crs2q 1..0=1 15..13=4 12=1 11..10=3 6..5=0 cs rv32c rv64c 337 | c.addw crs1rdq crs2q 1..0=1 15..13=4 12=1 11..10=3 6..5=1 cs rv32c rv64c 338 | c.j cimmj 1..0=1 15..13=5 cj rv32c rv64c 339 | c.beqz crs1q cimmb 1..0=1 15..13=6 cb rv32c rv64c 340 | c.bnez crs1q cimmb 1..0=1 15..13=7 cb rv32c rv64c 341 | c.slli crs1rd cimmsh5 1..0=2 15..13=0 ci·sh5 rv32c 342 | c.fldsp cfrd cimmldsp 1..0=2 15..13=1 ci·ldsp+f rv32c rv64c 343 | c.lwsp crd cimmlwsp 1..0=2 15..13=2 ci·lwsp rv32c rv64c 344 | c.flwsp cfrd cimmlwsp 1..0=2 15..13=3 ci·lwsp+f rv32c 345 | c.jr crd0 crs1 1..0=2 15..13=4 12=0 6..2=0 cr·jr rv32c rv64c 346 | c.mv crd crs2 1..0=2 15..13=4 12=0 cr·mv rv32c rv64c 347 | c.ebreak 1..0=2 15..13=4 12=1 11..7=0 6..2=0 ci·none rv32c rv64c 348 | c.jalr crd0 crs1 1..0=2 15..13=4 12=1 6..2=0 cr·jalr rv32c rv64c 349 | c.add crs1rd crs2 1..0=2 15..13=4 12=1 cr rv32c rv64c 350 | c.fsdsp cfrs2 cimmsdsp 1..0=2 15..13=5 css·sdsp+f rv32c rv64c 351 | c.swsp crs2 cimmswsp 1..0=2 15..13=6 css·swsp rv32c rv64c 352 | c.fswsp cfrs2 cimmswsp 1..0=2 15..13=7 css·swsp+f rv32c 353 | 354 | # RV64C "RV64C Standard Extension for Compressed Instructions (in addition to RV32C)" 355 | 356 | c.ld crdq crs1q cimmd 1..0=0 15..13=3 cl·ld rv64c 357 | c.sd crs1q crs2q cimmd 1..0=0 15..13=7 cs·sd rv64c 358 | c.addiw crs1rd cimmi 1..0=1 15..13=1 ci rv64c 359 | c.srli crs1rdq cimmsh6 1..0=1 15..13=4 11..10=0 cb·sh6 rv64c 360 | c.srai crs1rdq cimmsh6 1..0=1 15..13=4 11..10=1 cb·sh6 rv64c 361 | c.slli crs1rd cimmsh6 1..0=2 15..13=0 ci·sh6 rv64c 362 | c.ldsp crd cimmldsp 1..0=2 15..13=3 ci·ldsp rv64c 363 | c.sdsp crs2 cimmsdsp 1..0=2 15..13=7 css·sdsp rv64c 364 | 365 | # RV128C "RV128C Standard Extension for Compressed Instructions (in addition to RV64C)" 366 | 367 | c.lq crdq crs1q cimmq 1..0=0 15..13=1 cl·lq rv128c 368 | c.sq crs1q crs2q cimmq 1..0=0 15..13=5 cs·sq rv128c 369 | c.lqsp crd cimmlqsp 1..0=2 15..13=1 ci·lqsp rv128c 370 | c.sqsp crs2 cimmsqsp 1..0=2 15..13=5 css·sqsp rv128c 371 | -------------------------------------------------------------------------------- /operands: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # 3 | # 4 | # contains a comma list of gather[scatter] bits. e.g. 5 | # 6 | # 12:10[8|4:3],6:2[7:6|2:1|5] 7 | # 8 | # is equivalent to the RISC-V Compressed Instruction Set notation: 9 | # 10 | # 12 10 6 2 11 | # offset[8|4:3] offset[7:6|2:1|5] 12 | # 13 | # when [scatter] is ommitted, bits are right justified from bit 0 14 | # 15 | # type is one of arg, creg, ireg, freg, offset, simm, uimm 16 | 17 | rd 11:7 ireg rd 18 | rs1 19:15 ireg rs1 19 | rs2 24:20 ireg rs2 20 | rs3 31:27 ireg rs3 21 | frd 11:7 freg frd 22 | frs1 19:15 freg frs1 23 | frs2 24:20 freg frs2 24 | frs3 31:27 freg frs3 25 | aq 26 arg aq # Acquire 26 | rl 25 arg rl # Release 27 | pred 27:24 arg pred # Predecessor 28 | succ 23:20 arg succ # Successor 29 | rm 14:12 arg rm # Rounding Mode 30 | imm20 31:12[31:12] simm simm 31 | oimm20 31:12[31:12] offset simm 32 | jimm20 31:12[20|10:1|11|19:12] offset simm # PC relative jump 33 | imm12 31:20[11:0] simm simm 34 | oimm12 31:20[11:0] offset simm 35 | csr12 31:20[11:0] uimm csr 36 | simm12 31:25[11:5],11:7[4:0] offset simm 37 | sbimm12 31:25[12|10:5],11:7[4:1|11] offset simm # PC relative branch 38 | zimm 19:15[4:0] uimm uimm 39 | shamt5 24:20[4:0] uimm shamt # 32-bit shift amount 40 | shamt6 25:20[5:0] uimm shamt # 64-bit shift amount 41 | shamt7 26:20[6:0] uimm shamt # 128-bit shift amount 42 | crd0 12 creg rd'' 43 | crdq 4:2 creg rd' 44 | crs1q 9:7 creg rs1' 45 | crs1rdq 9:7 creg rs1'/rd' 46 | crs2q 4:2 creg rs2' 47 | crd 11:7 ireg rd 48 | crs1 11:7 ireg rs1 49 | crs1rd 11:7 ireg rs1/rd 50 | crs2 6:2 ireg rs2 51 | cfrdq 4:2 creg frd' 52 | cfrs2q 4:2 creg frs2' 53 | cfrs2 6:2 freg frs2 54 | cfrd 11:7 freg frd 55 | cimmsh5 6:2[4:0] uimm nzuimm 56 | cimmsh6 12[5],6:2[4:0] uimm nzuimm 57 | cimmi 12[5],6:2[4:0] simm simm 58 | cnzimmi 12[5],6:2[4:0] simm nzsimm 59 | cimmui 12[17],6:2[16:12] simm nzsimm 60 | cimmlwsp 12[5],6:2[4:2|7:6] uimm uimm 61 | cimmldsp 12[5],6:2[4:3|8:6] uimm uimm 62 | cimmlqsp 12[5],6:2[4|9:6] uimm uimm 63 | cimm16sp 12[9],6:2[4|6|8:7|5] simm nzsimm 64 | cimmj 12:2[11|4|9:8|10|6|7|3:1|5] simm simm # PC relative jump 65 | cimmb 12:10[8|4:3],6:2[7:6|2:1|5] simm simm # PC relative branch 66 | cimmswsp 12:7[5:2|7:6] uimm uimm 67 | cimmsdsp 12:7[5:3|8:6] uimm uimm 68 | cimmsqsp 12:7[5:4|9:6] uimm uimm 69 | cimm4spn 12:5[5:4|9:6|2|3] uimm nzuimm 70 | cimmw 12:10[5:3],6:5[2|6] uimm uimm 71 | cimmd 12:10[5:3],6:5[7:6] uimm uimm 72 | cimmq 12:10[5:4|8],6:5[7:6] uimm uimm 73 | -------------------------------------------------------------------------------- /pseudos: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # 3 | 4 | nop addi none rd_eq_x0 rs1_eq_x0 imm_eq_zero 5 | #lla,la {lui,slli,addi,addiw} rd,symbol # ; Constant 6 | #la auipc,{ld,lw} rd,symbol # (R_RISCV_GOT_HI20, R_RISCV_PCREL_LO12_I) ; -fpic symbol 7 | #lla,la auipc,addi rd,symbol # (R_RISCV_PCREL_HI20, R_RISCV_PCREL_LO12_I) ; -fno-pic symbol (default) 8 | #la.tls.gd auipc,addi rd,symbol # (R_RISCV_TLS_GD_HI20, R_RISCV_PCREL_LO12_I) ; TLS model global dynamic 9 | #la.tls.ie auipc,{ld,lw} rd,symbol # (R_RISCV_TLS_GOT_HI20, R_RISCV_PCREL_LO12_I) ; TLS model initial exec 10 | #li {lui,slli,addi,addiw} rd,rs1 11 | mv addi rd,rs1 imm_eq_zero 12 | not xori rd,rs1 imm_eq_n1 13 | neg sub rd,rs2 rs1_eq_x0 14 | negw subw rd,rs2 rs1_eq_x0 15 | sext.w addiw rd,rs1 imm_eq_zero 16 | seqz sltiu rd,rs1 imm_eq_p1 17 | snez sltu rd,rs2 rs1_eq_x0 18 | sltz slt rd,rs1 rs2_eq_x0 19 | sgtz slt rd,rs2 rs1_eq_x0 20 | fmv.s fsgnj.s rd,rs1 rs2_eq_rs1 21 | fabs.s fsgnjx.s rd,rs1 rs2_eq_rs1 22 | fneg.s fsgnjn.s rd,rs1 rs2_eq_rs1 23 | fmv.d fsgnj.d rd,rs1 rs2_eq_rs1 24 | fabs.d fsgnjx.d rd,rs1 rs2_eq_rs1 25 | fneg.d fsgnjn.d rd,rs1 rs2_eq_rs1 26 | fmv.q fsgnj.q rd,rs1 rs2_eq_rs1 27 | fabs.q fsgnjx.q rd,rs1 rs2_eq_rs1 28 | fneg.q fsgnjn.q rd,rs1 rs2_eq_rs1 29 | beqz beq rs1,offset rs2_eq_x0 30 | bnez bne rs1,offset rs2_eq_x0 31 | blez bge rs2,offset rs1_eq_x0 32 | bgez bge rs1,offset rs2_eq_x0 33 | bltz blt rs1,offset rs2_eq_x0 34 | bgtz blt rs2,offset rs1_eq_x0 35 | ble bge rs2,rs1,offset 36 | bleu bgeu rs2,rs1,offset 37 | bgt blt rs2,rs1,offset 38 | bgtu bltu rs2,rs1,offset 39 | j jal offset rd_eq_x0 40 | jal jal offset rd_eq_ra 41 | ret jalr none rd_eq_x0 rs1_eq_ra 42 | jr jalr rs1 rd_eq_x0 imm_eq_zero 43 | jalr jalr rs1 rd_eq_ra imm_eq_zero 44 | #call {auipc,jalr} offset 45 | #tail {auipc,jalr} offset 46 | rdcycle csrrs rd rs1_eq_x0 csr_eq_0xc00 47 | rdtime csrrs rd rs1_eq_x0 csr_eq_0xc01 48 | rdinstret csrrs rd rs1_eq_x0 csr_eq_0xc02 49 | rdcycleh csrrs rd rs1_eq_x0 csr_eq_0xc80 50 | rdtimeh csrrs rd rs1_eq_x0 csr_eq_0xc81 51 | rdinstreth csrrs rd rs1_eq_x0 csr_eq_0xc82 52 | frcsr csrrs rd rs1_eq_x0 csr_eq_0x003 53 | frrm csrrs rd rs1_eq_x0 csr_eq_0x002 54 | frflags csrrs rd rs1_eq_x0 csr_eq_0x001 55 | fscsr csrrw rd,rs1 csr_eq_0x003 56 | fsrm csrrw rd,rs1 csr_eq_0x002 57 | fsflags csrrw rd,rs1 csr_eq_0x001 58 | fsrmi csrrwi rd,zimm csr_eq_0x002 59 | fsflagsi csrrwi rd,zimm csr_eq_0x001 60 | -------------------------------------------------------------------------------- /registers: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # 3 | # 4 | # is one of ireg, freg 5 | # 6 | # is one of caller, callee, global, zero 7 | 8 | x0 zero ireg zero "Hard-wired zero" 9 | x1 ra ireg caller "Return address Caller" 10 | x2 sp ireg callee "Stack pointer Callee" 11 | x3 gp ireg global "Global pointer" 12 | x4 tp ireg callee "Thread pointer Callee" 13 | x5 t0 ireg caller "Temporaries Caller" 14 | x6 t1 ireg caller "Temporaries Caller" 15 | x7 t2 ireg caller "Temporaries Caller" 16 | x8 s0 ireg callee "Saved register/frame pointer Callee" 17 | x9 s1 ireg callee "Saved registers Callee" 18 | x10 a0 ireg caller "Function arguments Caller" 19 | x11 a1 ireg caller "Function arguments Caller" 20 | x12 a2 ireg caller "Function arguments Caller" 21 | x13 a3 ireg caller "Function arguments Caller" 22 | x14 a4 ireg caller "Function arguments Caller" 23 | x15 a5 ireg caller "Function arguments Caller" 24 | x16 a6 ireg caller "Function arguments Caller" 25 | x17 a7 ireg caller "Function arguments Caller" 26 | x18 s2 ireg callee "Saved registers Callee" 27 | x19 s3 ireg callee "Saved registers Callee" 28 | x20 s4 ireg callee "Saved registers Callee" 29 | x21 s5 ireg callee "Saved registers Callee" 30 | x22 s6 ireg callee "Saved registers Callee" 31 | x23 s7 ireg callee "Saved registers Callee" 32 | x24 s8 ireg callee "Saved registers Callee" 33 | x25 s9 ireg callee "Saved registers Callee" 34 | x26 s10 ireg callee "Saved registers Callee" 35 | x27 s11 ireg callee "Saved registers Callee" 36 | x28 t3 ireg caller "Temporaries Caller" 37 | x29 t4 ireg caller "Temporaries Caller" 38 | x30 t5 ireg caller "Temporaries Caller" 39 | x31 t6 ireg caller "Temporaries Caller" 40 | 41 | f0 ft0 freg caller "FP temporaries Caller" 42 | f1 ft1 freg caller "FP temporaries Caller" 43 | f2 ft2 freg caller "FP temporaries Caller" 44 | f3 ft3 freg caller "FP temporaries Caller" 45 | f4 ft4 freg caller "FP temporaries Caller" 46 | f5 ft5 freg caller "FP temporaries Caller" 47 | f6 ft6 freg caller "FP temporaries Caller" 48 | f7 ft7 freg caller "FP temporaries Caller" 49 | f8 fs0 freg callee "FP saved registers Callee" 50 | f9 fs1 freg callee "FP saved registers Callee" 51 | f10 fa0 freg caller "FP arguments Caller" 52 | f11 fa1 freg caller "FP arguments Caller" 53 | f12 fa2 freg caller "FP arguments Caller" 54 | f13 fa3 freg caller "FP arguments Caller" 55 | f14 fa4 freg caller "FP arguments Caller" 56 | f15 fa5 freg caller "FP arguments Caller" 57 | f16 fa6 freg caller "FP arguments Caller" 58 | f17 fa7 freg caller "FP arguments Caller" 59 | f18 fs2 freg callee "FP saved registers Callee" 60 | f19 fs3 freg callee "FP saved registers Callee" 61 | f20 fs4 freg callee "FP saved registers Callee" 62 | f21 fs5 freg callee "FP saved registers Callee" 63 | f22 fs6 freg callee "FP saved registers Callee" 64 | f23 fs7 freg callee "FP saved registers Callee" 65 | f24 fs8 freg callee "FP saved registers Callee" 66 | f25 fs9 freg callee "FP saved registers Callee" 67 | f26 fs10 freg callee "FP saved registers Callee" 68 | f27 fs11 freg callee "FP saved registers Callee" 69 | f28 ft8 freg caller "FP temporaries Caller" 70 | f29 ft9 freg caller "FP temporaries Caller" 71 | f30 ft10 freg caller "FP temporaries Caller" 72 | f31 ft11 freg caller "FP temporaries Caller" 73 | -------------------------------------------------------------------------------- /types: -------------------------------------------------------------------------------- 1 | # format of a line in this file: 2 | # [=] ... 3 | 4 | none "None" 5 | 6 | 32 "Base" 31:25 24:20 19:15 14:12 11:7 6:0 7 | r "Register" 31:27=funct5 26:25=funct2 24:20=rs2 19:15=rs1 14:12=funct3 11:7=rd 6:0=opcode 8 | r4 "Register" 31:27=rs3 26:25=funct2 24:20=rs2 19:15=rs1 14:12=funct3 11:7=rd 6:0=opcode 9 | i "Immediate" 31:20[11:0]=imm 19:15=rs1 14:12=funct3 11:7=rd 6:0=opcode 10 | s "Store" 31:25[11:5]=imm 24:20=rs2 19:15=rs1 14:12=funct3 11:7[4:0]=imm 6:0=opcode 11 | sb "Branch" 31:25[12|10:5]=imm 24:20=rs2 19:15=rs1 14:12=funct3 11:7[4:1|11]=imm 6:0=opcode 12 | u "Upper" 31:12[31:12]=imm 11:7=rd 6:0=opcode 13 | uj "Jump" 31:12[20|10:1|11|19:12]=imm 11:7=rd 6:0=opcode 14 | 15 | 16 "Compressed" 15:13 12:10 9:7 6:5 4:2 1:0 16 | cr "Register" 15:12=funct4 11:7=rd/rs1 6:2=rs2 1:0=op 17 | ci "Immediate" 15:13=funct3 12=imm 11:7=rd/rs1 6:2=imm 1:0=op 18 | css "Stack-relative Store" 15:13=funct3 12:7=imm 6:2=rs2 1:0=op 19 | ciw "Wide Immediate" 15:13=funct3 12:5=imm 4:2=rd' 1:0=op 20 | cl "Load" 15:13=funct3 12:10=imm 9:7=rs1' 6:5=imm 4:2=rd' 1:0=op 21 | cs "Store" 15:13=funct3 12:10=imm 9:7=rs1' 6:5=imm 4:2=rs2' 1:0=op 22 | cb "Branch" 15:13=funct3 12:10=imm 9:7=rs1' 6:2=imm 1:0=op 23 | cj "Jump" 15:13=funct3 12:2=imm 1:0=op 24 | --------------------------------------------------------------------------------