├── blaster.py ├── dbgjtag.py ├── mkfw.py ├── murax ├── Murax.v ├── main.cpp ├── makefile ├── ocd.py └── quartus │ ├── ftdi │ ├── murax.qpf │ └── murax.qsf │ └── virtual │ ├── Murax.scala │ ├── Murax.v │ ├── VJTAG.v │ ├── murax.qpf │ └── murax.qsf ├── ppci ├── __init__.py ├── __main__.py ├── api.py ├── arch │ ├── __init__.py │ ├── arch.py │ ├── arch_info.py │ ├── arm │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── arm_instructions.py │ │ ├── arm_relocations.py │ │ ├── isa.py │ │ ├── neon.py │ │ ├── registers.py │ │ ├── thumb_instructions.py │ │ ├── thumb_relocations.py │ │ └── vfp.py │ ├── asm_printer.py │ ├── avr │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ └── registers.py │ ├── cc.py │ ├── data_instructions.py │ ├── effects.py │ ├── encoding.py │ ├── example.py │ ├── generic_instructions.py │ ├── isa.py │ ├── jvm │ │ ├── __init__.py │ │ ├── __main__.py │ │ ├── class2ir.py │ │ ├── class_loader.py │ │ ├── dynload.py │ │ ├── enums.py │ │ ├── io.py │ │ ├── jarfile.py │ │ ├── nodes.py │ │ ├── opcodes.py │ │ └── printer.py │ ├── m68k │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ └── registers.py │ ├── mcs6500 │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ └── registers.py │ ├── microblaze │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ └── registers.py │ ├── mips │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ └── registers.py │ ├── msp430 │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ └── registers.py │ ├── or1k │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ ├── isa.py │ │ ├── orfpx32.py │ │ └── registers.py │ ├── registers.py │ ├── riscv │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── asm_printer.py │ │ ├── instructions.py │ │ ├── registers.py │ │ ├── relocations.py │ │ ├── rva_instructions.py │ │ ├── rvc_instructions.py │ │ ├── rvc_relocations.py │ │ ├── rvf_instructions.py │ │ ├── rvfx_instructions.py │ │ └── tokens.py │ ├── runtime.py │ ├── stack.py │ ├── stm8 │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ ├── opcodes.txt │ │ └── registers.py │ ├── target_list.py │ ├── token.py │ ├── x86_64 │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ ├── registers.py │ │ ├── sse2_instructions.py │ │ └── x87_instructions.py │ └── xtensa │ │ ├── __init__.py │ │ ├── arch.py │ │ ├── instructions.py │ │ └── registers.py ├── binutils │ ├── __init__.py │ ├── archive.py │ ├── assembler.py │ ├── dbg │ │ ├── __init__.py │ │ ├── cli.py │ │ ├── debug_driver.py │ │ ├── debugger.py │ │ ├── dummy_driver.py │ │ ├── event.py │ │ ├── gdb │ │ │ ├── __init__.py │ │ │ ├── client.py │ │ │ ├── rsp.py │ │ │ └── transport.py │ │ ├── linux64debugdriver.py │ │ └── ptcli.py │ ├── debuginfo.py │ ├── disasm.py │ ├── layout.py │ ├── linker.py │ ├── objectfile.py │ └── outstream.py ├── build │ ├── __init__.py │ ├── buildtasks.py │ ├── recipe.py │ └── tasks.py ├── cil.py ├── cil │ ├── __init__.py │ └── io.py ├── cli │ ├── __init__.py │ ├── archive.py │ ├── asm.py │ ├── base.py │ ├── build.py │ ├── c3c.py │ ├── cc.py │ ├── compile_base.py │ ├── dbg.py │ ├── disasm.py │ ├── hexdump.py │ ├── hexutil.py │ ├── java.py │ ├── link.py │ ├── llc.py │ ├── mkuimage.py │ ├── objcopy.py │ ├── objdump.py │ ├── ocaml.py │ ├── opt.py │ ├── pascal.py │ ├── pedump.py │ ├── pycompile.py │ ├── readelf.py │ ├── wabt.py │ ├── wasm2wat.py │ ├── wasmcompile.py │ ├── wat2wasm.py │ └── yacc.py ├── codegen │ ├── __init__.py │ ├── burg.grammar │ ├── burg.py │ ├── codegen.py │ ├── dagsplit.py │ ├── flowgraph.py │ ├── instructionscheduler.py │ ├── instructionselector.py │ ├── interferencegraph.py │ ├── irdag.py │ ├── peephole.py │ ├── registerallocator.py │ ├── selectiongraph.py │ └── treematcher.py ├── common.py ├── cpu │ └── __init__.py ├── format │ ├── __init__.py │ ├── dwarf │ │ ├── __init__.py │ │ ├── die.py │ │ ├── line.py │ │ └── writer.py │ ├── elf │ │ ├── __init__.py │ │ ├── file.py │ │ ├── headers.py │ │ └── reader.py │ ├── exefile.py │ ├── header.py │ ├── hexfile.py │ ├── hunk │ │ ├── __init__.py │ │ ├── __main__.py │ │ ├── enums.py │ │ ├── reader.py │ │ └── writer.py │ ├── io.py │ ├── ldb.py │ ├── pefile │ │ ├── __init__.py │ │ ├── headers.py │ │ └── pefile.py │ ├── srecord.py │ └── uboot_image.py ├── graph │ ├── __init__.py │ ├── algorithm │ │ ├── __init__.py │ │ └── fixed_point_dominator.py │ ├── callgraph.py │ ├── cfg.py │ ├── cyclo.py │ ├── digraph.py │ ├── domtree.py │ ├── graph.py │ ├── lt.py │ ├── maskable_graph.py │ └── relooper.py ├── ir.py ├── irutils │ ├── __init__.py │ ├── builder.py │ ├── instrument.py │ ├── io.py │ ├── link.py │ ├── reader.py │ ├── verify.py │ └── writer.py ├── lang │ ├── __init__.py │ ├── basic │ │ ├── __init__.py │ │ └── c64.py │ ├── befunge.py │ ├── bf.py │ ├── c │ │ ├── __init__.py │ │ ├── api.py │ │ ├── builder.py │ │ ├── castxml.py │ │ ├── codegenerator.py │ │ ├── context.py │ │ ├── eval.py │ │ ├── init.py │ │ ├── lexer.py │ │ ├── macro.py │ │ ├── nodes │ │ │ ├── __init__.py │ │ │ ├── declarations.py │ │ │ ├── expressions.py │ │ │ ├── nodes.py │ │ │ ├── statements.py │ │ │ ├── types.py │ │ │ └── visitor.py │ │ ├── options.py │ │ ├── parser.py │ │ ├── preprocessor.py │ │ ├── printer.py │ │ ├── scope.py │ │ ├── semantics.py │ │ ├── synthesize.py │ │ ├── token.py │ │ └── utils.py │ ├── c3 │ │ ├── __init__.py │ │ ├── astnodes.py │ │ ├── builder.py │ │ ├── codegenerator.py │ │ ├── context.py │ │ ├── lexer.py │ │ ├── parser.py │ │ ├── scope.py │ │ ├── typechecker.py │ │ └── visitor.py │ ├── common.py │ ├── fortran │ │ ├── __init__.py │ │ ├── nodes.py │ │ ├── parser.py │ │ └── utils.py │ ├── generic │ │ ├── __init__.py │ │ └── nodes.py │ ├── llvmir │ │ ├── __init__.py │ │ ├── codegenerator.py │ │ ├── frontend.py │ │ ├── lexer.py │ │ ├── nodes.py │ │ └── parser.py │ ├── ocaml │ │ ├── __init__.py │ │ ├── __main__.py │ │ ├── bytefile.py │ │ ├── cmo.py │ │ ├── code.py │ │ ├── gen_ir.py │ │ ├── io.py │ │ ├── marshall.py │ │ └── opcodes.py │ ├── pascal │ │ ├── __init__.py │ │ ├── builder.py │ │ ├── codegenerator.py │ │ ├── context.py │ │ ├── lexer.py │ │ ├── nodes │ │ │ ├── __init__.py │ │ │ ├── expressions.py │ │ │ ├── statements.py │ │ │ ├── symbols.py │ │ │ └── types.py │ │ ├── parser.py │ │ └── symbol_table.py │ ├── python │ │ ├── __init__.py │ │ ├── ir2py.py │ │ ├── loadpy.py │ │ ├── python2ir.py │ │ ├── python2wasm.py │ │ └── utils.py │ ├── sexpr.py │ ├── tools │ │ ├── __init__.py │ │ ├── baselex.py │ │ ├── common.py │ │ ├── earley.py │ │ ├── grammar.py │ │ ├── handlexer.py │ │ ├── lr.py │ │ ├── recursivedescent.py │ │ ├── regex │ │ │ ├── __init__.py │ │ │ ├── compile.py │ │ │ ├── parser.py │ │ │ ├── regex.py │ │ │ └── symbol_set.py │ │ └── yacc.py │ └── ws.py ├── opt │ ├── __init__.py │ ├── cjmp.py │ ├── clean.py │ ├── constantfolding.py │ ├── cse.py │ ├── inline.py │ ├── load_after_store.py │ ├── mem2reg.py │ ├── tailcall.py │ └── transform.py ├── programs │ ├── __init__.py │ ├── arm_program.py │ ├── base.py │ ├── c3_program.py │ ├── graph.py │ ├── ir_program.py │ ├── python_program.py │ ├── wasm_program.py │ └── x86_64_program.py ├── runtime.py ├── utils │ ├── __init__.py │ ├── binary_txt.py │ ├── bitfun.py │ ├── chunk.py │ ├── codepage.py │ ├── collections.py │ ├── graph2svg.py │ ├── hexdump.py │ ├── leb128.py │ ├── reporting.py │ └── tree.py └── wasm │ ├── __init__.py │ ├── _instantiate.py │ ├── arch.py │ ├── components.py │ ├── io.py │ ├── opcodes.py │ ├── ppci2wasm.py │ ├── runtime.py │ ├── template.html │ ├── template.js │ ├── tuple_parser.py │ ├── util.py │ ├── wabt.py │ ├── wasm2ppci.py │ └── wat.py ├── pulp ├── .editorconfig ├── .gitignore ├── .gitmodules ├── .vscode │ └── launch.json ├── Makefile ├── README.md ├── dockerfile │ └── Dockerfile ├── fpga │ ├── .editorconfig │ ├── .gitignore │ ├── Makefile │ ├── constraints │ │ ├── xc7a100tcsg324-1 │ │ │ ├── arty-config.xdc │ │ │ └── master.xdc │ │ ├── xc7a35ticsg324-1L │ │ │ ├── arty-config.xdc │ │ │ └── master.xdc │ │ └── xc7z020clg400-1 │ │ │ ├── master.xdc │ │ │ └── zynq.xdc │ ├── ips │ │ └── ips.tcl │ └── main │ │ ├── main.mk │ │ └── tcl │ │ ├── bitstream.tcl │ │ ├── import.tcl │ │ ├── opt.tcl │ │ ├── place.tcl │ │ ├── prep_ips.tcl │ │ ├── program_mcs.tcl │ │ ├── report.tcl │ │ ├── route.tcl │ │ ├── run.tcl │ │ ├── start.tcl │ │ ├── synthesis.tcl │ │ └── write_cfgmem.tcl ├── ips │ ├── ahb3lite_apb_bridge │ │ ├── .gitignore │ │ ├── DATASHEET.md │ │ ├── LICENSE.md │ │ ├── README.md │ │ ├── _config.yml │ │ ├── _layouts │ │ │ └── default.html │ │ ├── assets │ │ │ ├── css │ │ │ │ └── style.scss │ │ │ └── img │ │ │ │ ├── RoaLogicLogo.png │ │ │ │ ├── apb4-bridge-per.png │ │ │ │ ├── apb4-bridge-sig.png │ │ │ │ └── apb4-bridge-sys.png │ │ ├── docs │ │ │ ├── ahb3lite_apb_bridge.txss │ │ │ ├── ahb3lite_apb_bridge_datasheet.pdf │ │ │ ├── assets │ │ │ │ ├── graffle │ │ │ │ │ └── AHB-Lite APB4 Bridge.graffle │ │ │ │ └── img │ │ │ │ │ ├── Tagged_Logo-eps-converted-to.pdf │ │ │ │ │ ├── Tagged_Logo.eps │ │ │ │ │ ├── apb4-bridge-per.png │ │ │ │ │ ├── apb4-bridge-sig.png │ │ │ │ │ └── apb4-bridge-sys.png │ │ │ ├── markdown │ │ │ │ ├── compile.sh │ │ │ │ ├── frontmatter.md │ │ │ │ └── lpp.pl │ │ │ ├── pkg │ │ │ │ └── roalogictitle.sty │ │ │ └── tex │ │ │ │ ├── configuration.tex │ │ │ │ ├── history.tex │ │ │ │ ├── interface-ahb.tex │ │ │ │ ├── interface-apb.tex │ │ │ │ ├── interfaces.tex │ │ │ │ ├── introduction.tex │ │ │ │ ├── preamble.tex │ │ │ │ ├── resources.tex │ │ │ │ ├── setup.tex │ │ │ │ └── specification.tex │ │ └── rtl │ │ │ └── verilog │ │ │ └── ahb3lite_apb_bridge.sv │ ├── ahb3lite_interconnect │ │ ├── .gitignore │ │ ├── .gitmodules │ │ ├── DATASHEET.md │ │ ├── LICENSE.md │ │ ├── README.md │ │ ├── _config.yml │ │ ├── _layouts │ │ │ └── default.html │ │ ├── assets │ │ │ ├── css │ │ │ │ └── style.scss │ │ │ └── img │ │ │ │ ├── RoaLogicLogo.png │ │ │ │ ├── ahb-lite-switch-sys.png │ │ │ │ ├── ahb-lite-switch-sys1.png │ │ │ │ ├── ahb-lite-switch-sys2.png │ │ │ │ ├── ahb-lite-switch-sys3.png │ │ │ │ ├── ahb-lite-switch-sys4.png │ │ │ │ └── ahb-lite-switch-sys5.png │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── AHB3LiteBus.sv │ │ │ │ ├── AHB3LiteDrv.sv │ │ │ │ ├── AHB3LiteMon.sv │ │ │ │ ├── AHB3Lite_hdr.sv │ │ │ │ ├── AHBBusTr.sv │ │ │ │ ├── BaseConfig.sv │ │ │ │ ├── BaseDrv.sv │ │ │ │ ├── BaseMon.sv │ │ │ │ ├── BaseScoreBoard.sv │ │ │ │ ├── BaseTr.sv │ │ │ │ ├── BusGenerator.sv │ │ │ │ ├── BusTr.sv │ │ │ │ ├── Config.sv │ │ │ │ ├── Environment.sv │ │ │ │ ├── ScoreBoard.sv │ │ │ │ ├── ahb3lite_if.sv │ │ │ │ ├── test.sv │ │ │ │ └── testbench_top.sv │ │ ├── docs │ │ │ ├── ahb3lite_interconnect.txss │ │ │ ├── ahb3lite_interconnect_datasheet.pdf │ │ │ ├── ahb3lite_interconnect_datasheet.tex │ │ │ ├── ahb3lite_interconnect_markdown.tex │ │ │ ├── assets │ │ │ │ ├── graffle │ │ │ │ │ └── AHB-Lite-Switch.graffle │ │ │ │ └── img │ │ │ │ │ ├── Tagged_Logo-eps-converted-to.pdf │ │ │ │ │ ├── Tagged_Logo.eps │ │ │ │ │ ├── ahb-lite-switch-sys.png │ │ │ │ │ ├── ahb-lite-switch-sys1.png │ │ │ │ │ ├── ahb-lite-switch-sys2.png │ │ │ │ │ ├── ahb-lite-switch-sys3.png │ │ │ │ │ ├── ahb-lite-switch-sys4-eps-converted-to.pdf │ │ │ │ │ ├── ahb-lite-switch-sys4.eps │ │ │ │ │ ├── ahb-lite-switch-sys5-eps-converted-to.pdf │ │ │ │ │ └── ahb-lite-switch-sys5.eps │ │ │ ├── markdown │ │ │ │ ├── compile.sh │ │ │ │ ├── frontmatter.md │ │ │ │ └── lpp.pl │ │ │ ├── pkg │ │ │ │ └── roalogictitle.sty │ │ │ └── tex │ │ │ │ ├── configuration.tex │ │ │ │ ├── history.tex │ │ │ │ ├── interfaces.tex │ │ │ │ ├── introduction.tex │ │ │ │ ├── preamble.tex │ │ │ │ ├── references.tex │ │ │ │ ├── resources.tex │ │ │ │ ├── setup.tex │ │ │ │ └── specification.tex │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── LICENSE.txt │ │ │ │ ├── ahb3lite_interconnect.sv │ │ │ │ ├── ahb3lite_interconnect_master_port.sv │ │ │ │ └── ahb3lite_interconnect_slave_port.sv │ │ ├── sim │ │ │ └── rtlsim │ │ │ │ └── run │ │ │ │ ├── Makefile │ │ │ │ └── Makefile.include │ │ └── submodules │ │ │ └── ahb3lite_pkg │ │ │ ├── README.md │ │ │ └── rtl │ │ │ └── verilog │ │ │ └── ahb3lite_pkg.sv │ ├── ahb3lite_memory │ │ ├── .gitignore │ │ ├── DATASHEET.md │ │ ├── LICENSE.md │ │ ├── README.md │ │ ├── _config.yml │ │ ├── _layouts │ │ │ └── default.html │ │ ├── assets │ │ │ ├── css │ │ │ │ └── style.scss │ │ │ └── img │ │ │ │ ├── AHB-Lite-Memory-PortDiag.png │ │ │ │ ├── AHB-Lite-Memory-SysDiag.png │ │ │ │ ├── RoaLogicLogo.png │ │ │ │ └── Tagged_Logo_50.png │ │ ├── docs │ │ │ ├── ahb3lite_memory.txss │ │ │ ├── ahb3lite_memory_datasheet.pdf │ │ │ ├── ahb3lite_memory_datasheet.tex │ │ │ ├── ahb3lite_memory_markdown.tex │ │ │ ├── assets │ │ │ │ ├── graffle │ │ │ │ │ └── AHB-Lite Memory.graffle │ │ │ │ └── img │ │ │ │ │ ├── AHB-Lite-Memory-PortDiag-eps-converted-to.pdf │ │ │ │ │ ├── AHB-Lite-Memory-PortDiag.eps │ │ │ │ │ ├── AHB-Lite-Memory-SysDiag-eps-converted-to.pdf │ │ │ │ │ ├── AHB-Lite-Memory-SysDiag.eps │ │ │ │ │ ├── Tagged_Logo-eps-converted-to.pdf │ │ │ │ │ └── Tagged_Logo.eps │ │ │ ├── markdown │ │ │ │ ├── compile.sh │ │ │ │ ├── frontmatter.md │ │ │ │ └── lpp.pl │ │ │ ├── pkg │ │ │ │ └── roalogictitle.sty │ │ │ └── tex │ │ │ │ ├── configuration.tex │ │ │ │ ├── history.tex │ │ │ │ ├── interfaces.tex │ │ │ │ ├── introduction.tex │ │ │ │ ├── preamble.tex │ │ │ │ ├── references.tex │ │ │ │ ├── resources.tex │ │ │ │ ├── setup.tex │ │ │ │ ├── specification.tex │ │ │ │ └── technology.tex │ │ └── rtl │ │ │ └── verilog │ │ │ ├── LICENSE.txt │ │ │ └── ahb3lite_sram1rw.sv │ ├── ahb3lite_pkg │ │ ├── README.md │ │ ├── _config.yml │ │ └── rtl │ │ │ └── verilog │ │ │ └── ahb3lite_pkg.sv │ ├── altera │ │ ├── cdc_2phase.sv │ │ ├── fifo_v2.sv │ │ └── fifo_v3.sv │ ├── apb4_mux │ │ ├── .gitignore │ │ ├── DATASHEET.md │ │ ├── LICENSE.md │ │ ├── README.md │ │ ├── _config.yml │ │ ├── assets │ │ │ ├── css │ │ │ │ └── style.scss │ │ │ └── img │ │ │ │ ├── APB4-Mux-Sig.png │ │ │ │ ├── APB4-Mux-Sys.png │ │ │ │ └── RoaLogicLogo.png │ │ ├── docs │ │ │ ├── APB4 Multiplexer.txss │ │ │ ├── APB4-Multiplexer-Datasheet.pdf │ │ │ ├── APB4-Multiplexer-Datasheet.tex │ │ │ ├── APB4-Multiplexer-Markdown.tex │ │ │ ├── assets │ │ │ │ ├── graffle │ │ │ │ │ └── APB4 Multiplexer.graffle │ │ │ │ └── img │ │ │ │ │ ├── APB4-Mux-Sig-eps-converted-to.pdf │ │ │ │ │ ├── APB4-Mux-Sig.eps │ │ │ │ │ ├── APB4-Mux-Sys-eps-converted-to.pdf │ │ │ │ │ ├── APB4-Mux-Sys.eps │ │ │ │ │ ├── Tagged_Logo-eps-converted-to.pdf │ │ │ │ │ └── Tagged_Logo.eps │ │ │ ├── markdown │ │ │ │ ├── compile.sh │ │ │ │ ├── frontmatter.md │ │ │ │ └── lpp.pl │ │ │ ├── pkg │ │ │ │ └── roalogictitle.sty │ │ │ └── tex │ │ │ │ ├── configuration.tex │ │ │ │ ├── history.tex │ │ │ │ ├── interfaces.tex │ │ │ │ ├── introduction.tex │ │ │ │ ├── preamble.tex │ │ │ │ ├── references.tex │ │ │ │ ├── resources.tex │ │ │ │ ├── setup.tex │ │ │ │ └── specification.tex │ │ └── rtl │ │ │ └── verilog │ │ │ ├── LICENSE.txt │ │ │ └── apb_mux.sv │ ├── apb_gpio │ │ ├── .gitignore │ │ ├── Bender.yml │ │ ├── LICENSE │ │ ├── docs │ │ │ ├── APB_GPIO_reference.md │ │ │ └── APB_GPIO_reference.xlsx │ │ ├── rtl │ │ │ └── apb_gpio.sv │ │ └── src_files.yml │ ├── apb_uart_sv │ │ ├── LICENSE │ │ ├── README.md │ │ ├── apb_uart_sv.sv │ │ ├── io_generic_fifo.sv │ │ ├── src_files.yml │ │ ├── uart_interrupt.sv │ │ ├── uart_rx.sv │ │ └── uart_tx.sv │ ├── common_cells │ │ ├── .gitignore │ │ ├── .gitlab-ci.yml │ │ ├── Bender.yml │ │ ├── CHANGELOG.md │ │ ├── LICENSE │ │ ├── README.md │ │ ├── formal │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── counter.sby │ │ │ ├── counter_properties.sv │ │ │ ├── fall_through_register.sby │ │ │ ├── fall_through_register_properties.sv │ │ │ ├── fifo_v3.sby │ │ │ └── fifo_v3_properties.sv │ │ ├── include │ │ │ └── common_cells │ │ │ │ └── registers.svh │ │ ├── src │ │ │ ├── cdc_2phase.sv │ │ │ ├── cdc_fifo_2phase.sv │ │ │ ├── cdc_fifo_gray.sv │ │ │ ├── cf_math_pkg.sv │ │ │ ├── clk_div.sv │ │ │ ├── counter.sv │ │ │ ├── delta_counter.sv │ │ │ ├── deprecated │ │ │ │ ├── clock_divider.sv │ │ │ │ ├── clock_divider_counter.sv │ │ │ │ ├── fifo_v1.sv │ │ │ │ ├── fifo_v2.sv │ │ │ │ ├── find_first_one.sv │ │ │ │ ├── generic_LFSR_8bit.sv │ │ │ │ ├── generic_fifo.sv │ │ │ │ ├── generic_fifo_adv.sv │ │ │ │ ├── prioarbiter.sv │ │ │ │ ├── pulp_sync.sv │ │ │ │ ├── pulp_sync_wedge.sv │ │ │ │ └── rrarbiter.sv │ │ │ ├── edge_detect.sv │ │ │ ├── edge_propagator.sv │ │ │ ├── edge_propagator_rx.sv │ │ │ ├── edge_propagator_tx.sv │ │ │ ├── exp_backoff.sv │ │ │ ├── fall_through_register.sv │ │ │ ├── fifo_v3.sv │ │ │ ├── graycode.sv │ │ │ ├── id_queue.sv │ │ │ ├── lfsr.sv │ │ │ ├── lfsr_16bit.sv │ │ │ ├── lfsr_8bit.sv │ │ │ ├── lzc.sv │ │ │ ├── max_counter.sv │ │ │ ├── mv_filter.sv │ │ │ ├── onehot_to_bin.sv │ │ │ ├── plru_tree.sv │ │ │ ├── popcount.sv │ │ │ ├── rr_arb_tree.sv │ │ │ ├── rstgen.sv │ │ │ ├── rstgen_bypass.sv │ │ │ ├── serial_deglitch.sv │ │ │ ├── shift_reg.sv │ │ │ ├── spill_register.sv │ │ │ ├── sram.sv │ │ │ ├── stream_arbiter.sv │ │ │ ├── stream_arbiter_flushable.sv │ │ │ ├── stream_delay.sv │ │ │ ├── stream_demux.sv │ │ │ ├── stream_filter.sv │ │ │ ├── stream_fork.sv │ │ │ ├── stream_mux.sv │ │ │ ├── stream_register.sv │ │ │ ├── sync.sv │ │ │ ├── sync_wedge.sv │ │ │ └── unread.sv │ │ ├── src_files.yml │ │ └── test │ │ │ ├── cdc_2phase_synth.sv │ │ │ ├── cdc_2phase_synth.tcl │ │ │ ├── cdc_2phase_tb.sv │ │ │ ├── cdc_fifo_tb.sv │ │ │ ├── fifo_tb.sv │ │ │ ├── graycode_tb.sv │ │ │ ├── id_queue_synth.sv │ │ │ ├── id_queue_tb.sv │ │ │ ├── popcount_tb.sv │ │ │ ├── simulate.sh │ │ │ ├── stream_arbiter_synth.sv │ │ │ ├── stream_register_tb.sv │ │ │ ├── synth.sh │ │ │ ├── synth_bench.sv │ │ │ └── waves │ │ │ ├── cdc_2phase.tcl │ │ │ ├── cdc_fifo_2phase.tcl │ │ │ ├── cdc_fifo_gray.tcl │ │ │ └── id_queue.do │ ├── fpnew │ │ ├── .gitignore │ │ ├── .gitmodules │ │ ├── Bender.yml │ │ ├── LICENSE │ │ ├── README.md │ │ ├── docs │ │ │ ├── CHANGELOG.md │ │ │ ├── CODEOWNERS │ │ │ ├── CONTRIBUTING.md │ │ │ ├── README.md │ │ │ └── fig │ │ │ │ ├── multislice_block.png │ │ │ │ ├── opgrp_block.png │ │ │ │ ├── oprecomp_logo_inline1.png │ │ │ │ ├── slice_block.png │ │ │ │ └── top_block.png │ │ ├── ips_list.yml │ │ ├── src │ │ │ ├── common_cells │ │ │ │ ├── .gitignore │ │ │ │ ├── .gitlab-ci.yml │ │ │ │ ├── Bender.yml │ │ │ │ ├── CHANGELOG.md │ │ │ │ ├── LICENSE │ │ │ │ ├── README.md │ │ │ │ ├── include │ │ │ │ │ └── common_cells │ │ │ │ │ │ └── registers.svh │ │ │ │ ├── src │ │ │ │ │ ├── cdc_2phase.sv │ │ │ │ │ ├── cdc_fifo_2phase.sv │ │ │ │ │ ├── cdc_fifo_gray.sv │ │ │ │ │ ├── cf_math_pkg.sv │ │ │ │ │ ├── clk_div.sv │ │ │ │ │ ├── counter.sv │ │ │ │ │ ├── deprecated │ │ │ │ │ │ ├── clock_divider.sv │ │ │ │ │ │ ├── clock_divider_counter.sv │ │ │ │ │ │ ├── fifo_v1.sv │ │ │ │ │ │ ├── fifo_v2.sv │ │ │ │ │ │ ├── find_first_one.sv │ │ │ │ │ │ ├── generic_LFSR_8bit.sv │ │ │ │ │ │ ├── generic_fifo.sv │ │ │ │ │ │ ├── generic_fifo_adv.sv │ │ │ │ │ │ ├── prioarbiter.sv │ │ │ │ │ │ ├── pulp_sync.sv │ │ │ │ │ │ ├── pulp_sync_wedge.sv │ │ │ │ │ │ └── rrarbiter.sv │ │ │ │ │ ├── edge_detect.sv │ │ │ │ │ ├── edge_propagator.sv │ │ │ │ │ ├── edge_propagator_rx.sv │ │ │ │ │ ├── edge_propagator_tx.sv │ │ │ │ │ ├── exp_backoff.sv │ │ │ │ │ ├── fall_through_register.sv │ │ │ │ │ ├── fifo_v3.sv │ │ │ │ │ ├── graycode.sv │ │ │ │ │ ├── id_queue.sv │ │ │ │ │ ├── lfsr.sv │ │ │ │ │ ├── lfsr_16bit.sv │ │ │ │ │ ├── lfsr_8bit.sv │ │ │ │ │ ├── lzc.sv │ │ │ │ │ ├── mv_filter.sv │ │ │ │ │ ├── onehot_to_bin.sv │ │ │ │ │ ├── plru_tree.sv │ │ │ │ │ ├── popcount.sv │ │ │ │ │ ├── rr_arb_tree.sv │ │ │ │ │ ├── rstgen.sv │ │ │ │ │ ├── rstgen_bypass.sv │ │ │ │ │ ├── serial_deglitch.sv │ │ │ │ │ ├── shift_reg.sv │ │ │ │ │ ├── spill_register.sv │ │ │ │ │ ├── sram.sv │ │ │ │ │ ├── stream_arbiter.sv │ │ │ │ │ ├── stream_arbiter_flushable.sv │ │ │ │ │ ├── stream_delay.sv │ │ │ │ │ ├── stream_demux.sv │ │ │ │ │ ├── stream_filter.sv │ │ │ │ │ ├── stream_fork.sv │ │ │ │ │ ├── stream_mux.sv │ │ │ │ │ ├── stream_register.sv │ │ │ │ │ ├── sync.sv │ │ │ │ │ ├── sync_wedge.sv │ │ │ │ │ └── unread.sv │ │ │ │ ├── src_files.yml │ │ │ │ └── test │ │ │ │ │ ├── cdc_2phase_synth.sv │ │ │ │ │ ├── cdc_2phase_synth.tcl │ │ │ │ │ ├── cdc_2phase_tb.sv │ │ │ │ │ ├── cdc_fifo_tb.sv │ │ │ │ │ ├── fifo_tb.sv │ │ │ │ │ ├── graycode_tb.sv │ │ │ │ │ ├── id_queue_synth.sv │ │ │ │ │ ├── id_queue_tb.sv │ │ │ │ │ ├── popcount_tb.sv │ │ │ │ │ ├── simulate.sh │ │ │ │ │ ├── stream_arbiter_synth.sv │ │ │ │ │ ├── stream_register_tb.sv │ │ │ │ │ ├── synth.sh │ │ │ │ │ ├── synth_bench.sv │ │ │ │ │ └── waves │ │ │ │ │ ├── cdc_2phase.tcl │ │ │ │ │ ├── cdc_fifo_2phase.tcl │ │ │ │ │ ├── cdc_fifo_gray.tcl │ │ │ │ │ └── id_queue.do │ │ │ ├── fpnew_cast_multi.sv │ │ │ ├── fpnew_classifier.sv │ │ │ ├── fpnew_divsqrt_multi.sv │ │ │ ├── fpnew_fma.sv │ │ │ ├── fpnew_fma_multi.sv │ │ │ ├── fpnew_noncomp.sv │ │ │ ├── fpnew_opgroup_block.sv │ │ │ ├── fpnew_opgroup_fmt_slice.sv │ │ │ ├── fpnew_opgroup_multifmt_slice.sv │ │ │ ├── fpnew_pkg.sv │ │ │ ├── fpnew_rounding.sv │ │ │ ├── fpnew_top.sv │ │ │ ├── fpu_div_sqrt_mvp │ │ │ │ ├── Bender.yml │ │ │ │ ├── LICENSE │ │ │ │ ├── document │ │ │ │ │ └── Datasheet_of_transprecision.pdf │ │ │ │ ├── hdl │ │ │ │ │ ├── .gitignore │ │ │ │ │ ├── control_mvp.sv │ │ │ │ │ ├── defs_div_sqrt_mvp.sv │ │ │ │ │ ├── div_sqrt_mvp_wrapper.sv │ │ │ │ │ ├── div_sqrt_top_mvp.sv │ │ │ │ │ ├── iteration_div_sqrt_mvp.sv │ │ │ │ │ ├── norm_div_sqrt_mvp.sv │ │ │ │ │ ├── nrbd_nrsc_mvp.sv │ │ │ │ │ └── preprocess_mvp.sv │ │ │ │ └── src_files.yml │ │ │ └── rr_arb_tree_fpu.sv │ │ ├── src_files.yml │ │ └── tb │ │ │ └── flexfloat │ │ │ ├── .gitattributes │ │ │ ├── AUTHORS.md │ │ │ ├── CMakeLists.txt │ │ │ ├── LICENSE │ │ │ ├── README.md │ │ │ ├── examples │ │ │ ├── CMakeLists.txt │ │ │ ├── example01.c │ │ │ ├── example01.cpp │ │ │ ├── example_stats.c │ │ │ └── example_tracking.c │ │ │ ├── include │ │ │ ├── flexfloat.h │ │ │ └── flexfloat.hpp │ │ │ ├── src │ │ │ └── flexfloat.c │ │ │ └── test │ │ │ ├── CMakeLists.txt │ │ │ ├── IEEEHelper.cpp │ │ │ ├── IEEEHelper.h │ │ │ ├── NanInf.cpp │ │ │ ├── arithmetic.cpp │ │ │ ├── assignment.cpp │ │ │ ├── cmake │ │ │ ├── GoogleTest.cmake │ │ │ └── GtestDownloadCMakeLists.txt.in │ │ │ ├── conversion.cpp │ │ │ ├── downward_rounding.cpp │ │ │ ├── nearest_rounding.cpp │ │ │ ├── rel_ops.cpp │ │ │ ├── rounding.cpp │ │ │ ├── sanitize.cpp │ │ │ ├── upward_rounding.cpp │ │ │ ├── value_representation.cpp │ │ │ └── value_representation_half.cpp │ ├── memory │ │ ├── LICENSE.txt │ │ ├── README.md │ │ ├── _config.yml │ │ └── rtl │ │ │ └── verilog │ │ │ ├── rl_queue.sv │ │ │ ├── rl_ram_1r1w.sv │ │ │ ├── rl_ram_1r1w_easic_n3x.sv │ │ │ ├── rl_ram_1r1w_easic_n3xs.sv │ │ │ ├── rl_ram_1r1w_generic.sv │ │ │ ├── rl_ram_1rw.sv │ │ │ ├── rl_ram_1rw_easic_n3x.sv │ │ │ └── rl_ram_1rw_generic.sv │ ├── mpram │ │ ├── LICENSE │ │ ├── README │ │ ├── README.md │ │ ├── config.vh │ │ ├── dpram.v │ │ ├── fpga2014-paper.pdf │ │ ├── fpga2014-slides.pdf │ │ ├── lvt_1ht.v │ │ ├── lvt_bin.v │ │ ├── lvt_reg.v │ │ ├── mpram.qpf │ │ ├── mpram.qsf │ │ ├── mpram.v │ │ ├── mpram_gen.v │ │ ├── mpram_lvt_1ht.v │ │ ├── mpram_lvt_bin.v │ │ ├── mpram_lvt_reg.v │ │ ├── mpram_reg.v │ │ ├── mpram_tb.v │ │ ├── mpram_wrp.v │ │ ├── mpram_xor.v │ │ ├── mrram.v │ │ ├── riscv_register_file.sv │ │ ├── sim │ │ ├── syn │ │ ├── syn.res.example │ │ └── utils.vh │ ├── riscv-dbg │ │ ├── Bender.yml │ │ ├── CHANGELOG.md │ │ ├── LICENSE │ │ ├── LICENSE.SiFive │ │ ├── README.md │ │ ├── debug_rom │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── debug_rom.S │ │ │ ├── debug_rom.h │ │ │ ├── debug_rom.sv │ │ │ ├── encoding.h │ │ │ ├── gen_rom.py │ │ │ └── link.ld │ │ ├── src │ │ │ ├── dm_csrs.sv │ │ │ ├── dm_mem.sv │ │ │ ├── dm_pkg.sv │ │ │ ├── dm_sba.sv │ │ │ ├── dm_top.sv │ │ │ ├── dmi_cdc.sv │ │ │ ├── dmi_jtag.sv │ │ │ └── dmi_jtag_tap.sv │ │ └── src_files.yml │ ├── riscv │ │ ├── .gitignore │ │ ├── .gitlab-ci.yml │ │ ├── .travis.yml │ │ ├── Bender.yml │ │ ├── LICENSE │ │ ├── README.md │ │ ├── ci │ │ │ ├── Jenkinsfile │ │ │ ├── build-riscv-gcc.sh │ │ │ ├── get-gcc.sh │ │ │ ├── get-openocd.sh │ │ │ ├── install-verilator.sh │ │ │ ├── make-tmp.sh │ │ │ ├── openocd-to-junit.py │ │ │ ├── run-openocd-compliance.sh │ │ │ └── rv32tests-to-junit.py │ │ ├── doc │ │ │ ├── NONSECURED_RI5CY_DEBUG_reference.xlsx │ │ │ ├── SECURED_RI5CY_DEBUG_reference.xlsx │ │ │ └── user_manual.doc │ │ ├── rtl │ │ │ ├── include │ │ │ │ ├── apu_core_package.sv │ │ │ │ ├── apu_macros.sv │ │ │ │ ├── riscv_config.sv │ │ │ │ ├── riscv_defines.sv │ │ │ │ └── riscv_tracer_defines.sv │ │ │ ├── register_file_test_wrap.sv │ │ │ ├── riscv_L0_buffer.sv │ │ │ ├── riscv_alu.sv │ │ │ ├── riscv_alu_basic.sv │ │ │ ├── riscv_alu_div.sv │ │ │ ├── riscv_apu_disp.sv │ │ │ ├── riscv_compressed_decoder.sv │ │ │ ├── riscv_controller.sv │ │ │ ├── riscv_core.sv │ │ │ ├── riscv_cs_registers.sv │ │ │ ├── riscv_decoder.sv │ │ │ ├── riscv_ex_stage.sv │ │ │ ├── riscv_fetch_fifo.sv │ │ │ ├── riscv_hwloop_controller.sv │ │ │ ├── riscv_hwloop_regs.sv │ │ │ ├── riscv_id_stage.sv │ │ │ ├── riscv_if_stage.sv │ │ │ ├── riscv_int_controller.sv │ │ │ ├── riscv_load_store_unit.sv │ │ │ ├── riscv_mult.sv │ │ │ ├── riscv_pmp.sv │ │ │ ├── riscv_prefetch_L0_buffer.sv │ │ │ ├── riscv_prefetch_buffer.sv │ │ │ ├── riscv_register_file.sv │ │ │ ├── riscv_register_file_latch.sv │ │ │ ├── riscv_tracer.sv │ │ │ └── riscv_tracer.txt │ │ ├── src_files.yml │ │ └── tb │ │ │ ├── core │ │ │ ├── .clang-format │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── cluster_clock_gating.sv │ │ │ ├── csmith │ │ │ │ ├── license_notes │ │ │ │ ├── link.ld │ │ │ │ ├── riscv-isa-sim.diff │ │ │ │ ├── start.S │ │ │ │ └── syscalls.c │ │ │ ├── custom │ │ │ │ ├── crt0.S │ │ │ │ ├── hello_world.c │ │ │ │ ├── link.ld │ │ │ │ ├── syscalls.c │ │ │ │ └── vectors.S │ │ │ ├── dp_ram.sv │ │ │ ├── firmware │ │ │ │ ├── README │ │ │ │ ├── firmware.h │ │ │ │ ├── link.ld │ │ │ │ ├── makehex.py │ │ │ │ ├── multest.c │ │ │ │ ├── print.c │ │ │ │ ├── riscv.ld │ │ │ │ ├── riscv.ld.orig │ │ │ │ ├── sieve.c │ │ │ │ ├── start.S │ │ │ │ └── stats.c │ │ │ ├── mm_ram.sv │ │ │ ├── riscv_compliance_tests │ │ │ │ ├── I-ADD-01.S │ │ │ │ ├── I-ADDI-01.S │ │ │ │ ├── I-AND-01.S │ │ │ │ ├── I-ANDI-01.S │ │ │ │ ├── I-AUIPC-01.S │ │ │ │ ├── I-BEQ-01.S │ │ │ │ ├── I-BGE-01.S │ │ │ │ ├── I-BGEU-01.S │ │ │ │ ├── I-BLT-01.S │ │ │ │ ├── I-BLTU-01.S │ │ │ │ ├── I-BNE-01.S │ │ │ │ ├── I-CSRRC-01.S │ │ │ │ ├── I-CSRRCI-01.S │ │ │ │ ├── I-CSRRS-01.S │ │ │ │ ├── I-CSRRSI-01.S │ │ │ │ ├── I-CSRRW-01.S │ │ │ │ ├── I-CSRRWI-01.S │ │ │ │ ├── I-DELAY_SLOTS-01.S │ │ │ │ ├── I-EBREAK-01.S │ │ │ │ ├── I-ECALL-01.S │ │ │ │ ├── I-ENDIANESS-01.S │ │ │ │ ├── I-FENCE.I-01.S │ │ │ │ ├── I-IO.S │ │ │ │ ├── I-JAL-01.S │ │ │ │ ├── I-JALR-01.S │ │ │ │ ├── I-LB-01.S │ │ │ │ ├── I-LBU-01.S │ │ │ │ ├── I-LH-01.S │ │ │ │ ├── I-LHU-01.S │ │ │ │ ├── I-LUI-01.S │ │ │ │ ├── I-LW-01.S │ │ │ │ ├── I-NOP-01.S │ │ │ │ ├── I-OR-01.S │ │ │ │ ├── I-ORI-01.S │ │ │ │ ├── I-RF_size-01.S │ │ │ │ ├── I-RF_width-01.S │ │ │ │ ├── I-RF_x0-01.S │ │ │ │ ├── I-SB-01.S │ │ │ │ ├── I-SH-01.S │ │ │ │ ├── I-SLL-01.S │ │ │ │ ├── I-SLLI-01.S │ │ │ │ ├── I-SLT-01.S │ │ │ │ ├── I-SLTI-01.S │ │ │ │ ├── I-SLTIU-01.S │ │ │ │ ├── I-SLTU-01.S │ │ │ │ ├── I-SRA-01.S │ │ │ │ ├── I-SRAI-01.S │ │ │ │ ├── I-SRL-01.S │ │ │ │ ├── I-SRLI-01.S │ │ │ │ ├── I-SUB-01.S │ │ │ │ ├── I-SW-01.S │ │ │ │ ├── I-XOR-01.S │ │ │ │ ├── I-XORI-01.S │ │ │ │ ├── aw_test_macros.h │ │ │ │ ├── compliance_io.h │ │ │ │ ├── compliance_test.h │ │ │ │ ├── disabled │ │ │ │ │ ├── I-FENCE.I-01.S │ │ │ │ │ ├── I-MISALIGN_JMP-01.S │ │ │ │ │ └── I-MISALIGN_LDST-01.S │ │ │ │ ├── riscv_test.h │ │ │ │ └── test_macros.h │ │ │ ├── riscv_tests │ │ │ │ ├── LICENSE │ │ │ │ ├── README.md │ │ │ │ ├── macros │ │ │ │ │ └── scalar │ │ │ │ │ │ └── test_macros.h │ │ │ │ ├── riscv_test.h │ │ │ │ ├── rv32mi │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── breakpoint.S │ │ │ │ │ ├── csr.S │ │ │ │ │ ├── illegal.S │ │ │ │ │ ├── ma_addr.S │ │ │ │ │ ├── ma_fetch.S │ │ │ │ │ ├── mcsr.S │ │ │ │ │ ├── sbreak.S │ │ │ │ │ ├── scall.S │ │ │ │ │ └── shamt.S │ │ │ │ ├── rv32si │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── csr.S │ │ │ │ │ ├── dirty.S │ │ │ │ │ ├── ma_fetch.S │ │ │ │ │ ├── sbreak.S │ │ │ │ │ ├── scall.S │ │ │ │ │ └── wfi.S │ │ │ │ ├── rv32ua │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── amoadd_w.S │ │ │ │ │ ├── amoand_w.S │ │ │ │ │ ├── amomax_w.S │ │ │ │ │ ├── amomaxu_w.S │ │ │ │ │ ├── amomin_w.S │ │ │ │ │ ├── amominu_w.S │ │ │ │ │ ├── amoor_w.S │ │ │ │ │ ├── amoswap_w.S │ │ │ │ │ ├── amoxor_w.S │ │ │ │ │ └── lrsc.S │ │ │ │ ├── rv32uc │ │ │ │ │ ├── Makefrag │ │ │ │ │ └── rvc.S │ │ │ │ ├── rv32ud │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── fadd.S │ │ │ │ │ ├── fclass.S │ │ │ │ │ ├── fcmp.S │ │ │ │ │ ├── fcvt.S │ │ │ │ │ ├── fcvt_w.S │ │ │ │ │ ├── fdiv.S │ │ │ │ │ ├── fmadd.S │ │ │ │ │ ├── fmin.S │ │ │ │ │ ├── ldst.S │ │ │ │ │ ├── move.S │ │ │ │ │ └── recoding.S │ │ │ │ ├── rv32uf │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── fadd.S │ │ │ │ │ ├── fclass.S │ │ │ │ │ ├── fcmp.S │ │ │ │ │ ├── fcvt.S │ │ │ │ │ ├── fcvt_w.S │ │ │ │ │ ├── fdiv.S │ │ │ │ │ ├── fmadd.S │ │ │ │ │ ├── fmin.S │ │ │ │ │ ├── ldst.S │ │ │ │ │ ├── move.S │ │ │ │ │ └── recoding.S │ │ │ │ ├── rv32ui │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── add.S │ │ │ │ │ ├── addi.S │ │ │ │ │ ├── and.S │ │ │ │ │ ├── andi.S │ │ │ │ │ ├── auipc.S │ │ │ │ │ ├── beq.S │ │ │ │ │ ├── bge.S │ │ │ │ │ ├── bgeu.S │ │ │ │ │ ├── blt.S │ │ │ │ │ ├── bltu.S │ │ │ │ │ ├── bne.S │ │ │ │ │ ├── fence_i.S │ │ │ │ │ ├── jal.S │ │ │ │ │ ├── jalr.S │ │ │ │ │ ├── lb.S │ │ │ │ │ ├── lbu.S │ │ │ │ │ ├── lh.S │ │ │ │ │ ├── lhu.S │ │ │ │ │ ├── lui.S │ │ │ │ │ ├── lw.S │ │ │ │ │ ├── or.S │ │ │ │ │ ├── ori.S │ │ │ │ │ ├── sb.S │ │ │ │ │ ├── sh.S │ │ │ │ │ ├── simple.S │ │ │ │ │ ├── sll.S │ │ │ │ │ ├── slli.S │ │ │ │ │ ├── slt.S │ │ │ │ │ ├── slti.S │ │ │ │ │ ├── sltiu.S │ │ │ │ │ ├── sltu.S │ │ │ │ │ ├── sra.S │ │ │ │ │ ├── srai.S │ │ │ │ │ ├── srl.S │ │ │ │ │ ├── srli.S │ │ │ │ │ ├── sub.S │ │ │ │ │ ├── sw.S │ │ │ │ │ ├── xor.S │ │ │ │ │ └── xori.S │ │ │ │ ├── rv32um │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── div.S │ │ │ │ │ ├── divu.S │ │ │ │ │ ├── mul.S │ │ │ │ │ ├── mulh.S │ │ │ │ │ ├── mulhsu.S │ │ │ │ │ ├── mulhu.S │ │ │ │ │ ├── rem.S │ │ │ │ │ └── remu.S │ │ │ │ ├── rv64mi │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── access.S │ │ │ │ │ ├── breakpoint.S │ │ │ │ │ ├── csr.S │ │ │ │ │ ├── illegal.S │ │ │ │ │ ├── ma_addr.S │ │ │ │ │ ├── ma_fetch.S │ │ │ │ │ ├── mcsr.S │ │ │ │ │ ├── sbreak.S │ │ │ │ │ └── scall.S │ │ │ │ ├── rv64si │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── csr.S │ │ │ │ │ ├── dirty.S │ │ │ │ │ ├── ma_fetch.S │ │ │ │ │ ├── sbreak.S │ │ │ │ │ ├── scall.S │ │ │ │ │ └── wfi.S │ │ │ │ ├── rv64ua │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── amoadd_d.S │ │ │ │ │ ├── amoadd_w.S │ │ │ │ │ ├── amoand_d.S │ │ │ │ │ ├── amoand_w.S │ │ │ │ │ ├── amomax_d.S │ │ │ │ │ ├── amomax_w.S │ │ │ │ │ ├── amomaxu_d.S │ │ │ │ │ ├── amomaxu_w.S │ │ │ │ │ ├── amomin_d.S │ │ │ │ │ ├── amomin_w.S │ │ │ │ │ ├── amominu_d.S │ │ │ │ │ ├── amominu_w.S │ │ │ │ │ ├── amoor_d.S │ │ │ │ │ ├── amoor_w.S │ │ │ │ │ ├── amoswap_d.S │ │ │ │ │ ├── amoswap_w.S │ │ │ │ │ ├── amoxor_d.S │ │ │ │ │ ├── amoxor_w.S │ │ │ │ │ └── lrsc.S │ │ │ │ ├── rv64uc │ │ │ │ │ ├── Makefrag │ │ │ │ │ └── rvc.S │ │ │ │ ├── rv64ud │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── fadd.S │ │ │ │ │ ├── fclass.S │ │ │ │ │ ├── fcmp.S │ │ │ │ │ ├── fcvt.S │ │ │ │ │ ├── fcvt_w.S │ │ │ │ │ ├── fdiv.S │ │ │ │ │ ├── fmadd.S │ │ │ │ │ ├── fmin.S │ │ │ │ │ ├── ldst.S │ │ │ │ │ ├── move.S │ │ │ │ │ ├── recoding.S │ │ │ │ │ └── structural.S │ │ │ │ ├── rv64uf │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── fadd.S │ │ │ │ │ ├── fclass.S │ │ │ │ │ ├── fcmp.S │ │ │ │ │ ├── fcvt.S │ │ │ │ │ ├── fcvt_w.S │ │ │ │ │ ├── fdiv.S │ │ │ │ │ ├── fmadd.S │ │ │ │ │ ├── fmin.S │ │ │ │ │ ├── ldst.S │ │ │ │ │ ├── move.S │ │ │ │ │ └── recoding.S │ │ │ │ ├── rv64ui │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── add.S │ │ │ │ │ ├── addi.S │ │ │ │ │ ├── addiw.S │ │ │ │ │ ├── addw.S │ │ │ │ │ ├── and.S │ │ │ │ │ ├── andi.S │ │ │ │ │ ├── auipc.S │ │ │ │ │ ├── beq.S │ │ │ │ │ ├── bge.S │ │ │ │ │ ├── bgeu.S │ │ │ │ │ ├── blt.S │ │ │ │ │ ├── bltu.S │ │ │ │ │ ├── bne.S │ │ │ │ │ ├── fence_i.S │ │ │ │ │ ├── jal.S │ │ │ │ │ ├── jalr.S │ │ │ │ │ ├── lb.S │ │ │ │ │ ├── lbu.S │ │ │ │ │ ├── ld.S │ │ │ │ │ ├── lh.S │ │ │ │ │ ├── lhu.S │ │ │ │ │ ├── lui.S │ │ │ │ │ ├── lw.S │ │ │ │ │ ├── lwu.S │ │ │ │ │ ├── or.S │ │ │ │ │ ├── ori.S │ │ │ │ │ ├── sb.S │ │ │ │ │ ├── sd.S │ │ │ │ │ ├── sh.S │ │ │ │ │ ├── simple.S │ │ │ │ │ ├── sll.S │ │ │ │ │ ├── slli.S │ │ │ │ │ ├── slliw.S │ │ │ │ │ ├── sllw.S │ │ │ │ │ ├── slt.S │ │ │ │ │ ├── slti.S │ │ │ │ │ ├── sltiu.S │ │ │ │ │ ├── sltu.S │ │ │ │ │ ├── sra.S │ │ │ │ │ ├── srai.S │ │ │ │ │ ├── sraiw.S │ │ │ │ │ ├── sraw.S │ │ │ │ │ ├── srl.S │ │ │ │ │ ├── srli.S │ │ │ │ │ ├── srliw.S │ │ │ │ │ ├── srlw.S │ │ │ │ │ ├── sub.S │ │ │ │ │ ├── subw.S │ │ │ │ │ ├── sw.S │ │ │ │ │ ├── xor.S │ │ │ │ │ └── xori.S │ │ │ │ └── rv64um │ │ │ │ │ ├── Makefrag │ │ │ │ │ ├── div.S │ │ │ │ │ ├── divu.S │ │ │ │ │ ├── divuw.S │ │ │ │ │ ├── divw.S │ │ │ │ │ ├── mul.S │ │ │ │ │ ├── mulh.S │ │ │ │ │ ├── mulhsu.S │ │ │ │ │ ├── mulhu.S │ │ │ │ │ ├── mulw.S │ │ │ │ │ ├── rem.S │ │ │ │ │ ├── remu.S │ │ │ │ │ ├── remuw.S │ │ │ │ │ └── remw.S │ │ │ ├── riscv_wrapper.sv │ │ │ ├── tb_top.sv │ │ │ ├── tb_top_verilator.cpp │ │ │ ├── tb_top_verilator.sv │ │ │ ├── vsim.tcl │ │ │ └── waves.tcl │ │ │ ├── dm │ │ │ ├── .clang-format │ │ │ ├── .gitignore │ │ │ ├── LICENSE.Berkeley │ │ │ ├── LICENSE.SiFive │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── SimDTM.sv │ │ │ ├── SimJTAG.sv │ │ │ ├── boot_rom.sv │ │ │ ├── dp_ram.sv │ │ │ ├── mm_ram.sv │ │ │ ├── prog │ │ │ │ ├── link.ld │ │ │ │ ├── start.S │ │ │ │ ├── syscalls.c │ │ │ │ └── test.c │ │ │ ├── pulpissimo_compliance_test.cfg │ │ │ ├── pulpissimo_debug.cfg │ │ │ ├── remote_bitbang │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── rbs_test.c │ │ │ │ ├── remote_bitbang.c │ │ │ │ ├── remote_bitbang.h │ │ │ │ └── sim_jtag.c │ │ │ ├── riscv_tb_pkg.sv │ │ │ ├── tb_test_env.sv │ │ │ ├── tb_top.sv │ │ │ ├── tb_top_verilator.cpp │ │ │ ├── tb_top_verilator.sv │ │ │ ├── vsim_batch.tcl │ │ │ ├── vsim_gui.tcl │ │ │ └── waves.tcl │ │ │ ├── serDiv │ │ │ ├── scripts │ │ │ │ ├── compile.sh │ │ │ │ ├── sim.sh │ │ │ │ ├── tb.do │ │ │ │ ├── tb_nogui.do │ │ │ │ └── wave.do │ │ │ ├── tb.sv │ │ │ ├── tb_div.sv │ │ │ ├── tb_rem.sv │ │ │ ├── tb_udiv.sv │ │ │ └── tb_urem.sv │ │ │ ├── tb_MPU │ │ │ └── tb.sv │ │ │ ├── tb_riscv │ │ │ ├── README.md │ │ │ ├── include │ │ │ │ └── perturbation_defines.sv │ │ │ ├── riscv_perturbation.sv │ │ │ ├── riscv_random_interrupt_generator.sv │ │ │ ├── riscv_random_stall.sv │ │ │ ├── riscv_simchecker.sv │ │ │ └── tb_riscv_core.sv │ │ │ └── verilator-model │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── cluster_clock_gating.sv │ │ │ ├── dp_ram.sv │ │ │ ├── ram.sv │ │ │ ├── testbench.cpp │ │ │ └── top.sv │ └── utils │ │ ├── ahb3lite_if.sv │ │ ├── ahb_dummy.sv │ │ ├── ahb_ri5cy_rom.sv │ │ ├── ahb_to_ri5cy.sv │ │ ├── apb4_if.sv │ │ ├── cluster_clock_inverter.sv │ │ ├── filter_oor.sv │ │ ├── pulp_clock_mux2.sv │ │ └── ri5cy_to_ahb.sv ├── ocd.py ├── quartus │ ├── ftdi │ │ ├── clocks.sdc │ │ ├── pulp_soc.qpf │ │ └── pulp_soc.qsf │ └── virtual │ │ ├── clocks.sdc │ │ ├── dmi_jtag_tapv.sv │ │ ├── dmi_jtagv.sv │ │ ├── pulp_soc.qpf │ │ ├── pulp_soc.qsf │ │ ├── riscv_socv.sv │ │ └── virtual_jtag.v ├── simframework │ ├── framework.h │ ├── jtag.h │ └── uart.h ├── sw │ └── hello_world │ │ ├── .gitignore │ │ ├── API │ │ ├── inc │ │ │ ├── gpio.h │ │ │ ├── i2c.h │ │ │ ├── spi.h │ │ │ └── uart.h │ │ └── src │ │ │ ├── gpio.c │ │ │ ├── i2c.c │ │ │ ├── spi.c │ │ │ └── uart.c │ │ ├── Makefile │ │ ├── common │ │ ├── encoding.h │ │ └── riscv_soc_utils.h │ │ ├── init │ │ ├── startup.c │ │ └── vector.S │ │ ├── scripts │ │ ├── freedom-bin2hex.py │ │ └── gen_rom.py │ │ ├── sections.ld │ │ └── src │ │ └── main.c ├── tb │ ├── cpp │ │ ├── elfio │ │ │ ├── .gitignore │ │ │ ├── AUTHORS │ │ │ ├── COPYING │ │ │ ├── ChangeLog │ │ │ ├── ELFIO.sln │ │ │ ├── ELFIOTest │ │ │ │ ├── ELFIOTest.cpp │ │ │ │ ├── ELFIOTest.vcxproj │ │ │ │ ├── ELFIOTest.vcxproj.filters │ │ │ │ ├── ELFIOTest1.cpp │ │ │ │ ├── Makefile.am │ │ │ │ ├── Makefile.in │ │ │ │ └── runELFtests │ │ │ ├── INSTALL │ │ │ ├── Makefile.am │ │ │ ├── Makefile.in │ │ │ ├── NEWS │ │ │ ├── README │ │ │ ├── aclocal.m4 │ │ │ ├── autogen.sh │ │ │ ├── configure │ │ │ ├── configure.ac │ │ │ ├── cygwin │ │ │ │ └── elfio.cygport │ │ │ ├── depcomp │ │ │ ├── doc │ │ │ │ ├── elfio.docx │ │ │ │ ├── images │ │ │ │ │ ├── annot-close.png │ │ │ │ │ ├── annot-open.png │ │ │ │ │ ├── blank.png │ │ │ │ │ ├── callouts │ │ │ │ │ │ ├── 1.gif │ │ │ │ │ │ ├── 1.png │ │ │ │ │ │ ├── 1.svg │ │ │ │ │ │ ├── 10.gif │ │ │ │ │ │ ├── 10.png │ │ │ │ │ │ ├── 10.svg │ │ │ │ │ │ ├── 11.gif │ │ │ │ │ │ ├── 11.png │ │ │ │ │ │ ├── 11.svg │ │ │ │ │ │ ├── 12.gif │ │ │ │ │ │ ├── 12.png │ │ │ │ │ │ ├── 12.svg │ │ │ │ │ │ ├── 13.gif │ │ │ │ │ │ ├── 13.png │ │ │ │ │ │ ├── 13.svg │ │ │ │ │ │ ├── 14.gif │ │ │ │ │ │ ├── 14.png │ │ │ │ │ │ ├── 14.svg │ │ │ │ │ │ ├── 15.gif │ │ │ │ │ │ ├── 15.png │ │ │ │ │ │ ├── 15.svg │ │ │ │ │ │ ├── 16.svg │ │ │ │ │ │ ├── 17.svg │ │ │ │ │ │ ├── 18.svg │ │ │ │ │ │ ├── 19.svg │ │ │ │ │ │ ├── 2.gif │ │ │ │ │ │ ├── 2.png │ │ │ │ │ │ ├── 2.svg │ │ │ │ │ │ ├── 20.svg │ │ │ │ │ │ ├── 21.svg │ │ │ │ │ │ ├── 22.svg │ │ │ │ │ │ ├── 23.svg │ │ │ │ │ │ ├── 24.svg │ │ │ │ │ │ ├── 25.svg │ │ │ │ │ │ ├── 26.svg │ │ │ │ │ │ ├── 27.svg │ │ │ │ │ │ ├── 28.svg │ │ │ │ │ │ ├── 29.svg │ │ │ │ │ │ ├── 3.gif │ │ │ │ │ │ ├── 3.png │ │ │ │ │ │ ├── 3.svg │ │ │ │ │ │ ├── 30.svg │ │ │ │ │ │ ├── 4.gif │ │ │ │ │ │ ├── 4.png │ │ │ │ │ │ ├── 4.svg │ │ │ │ │ │ ├── 5.gif │ │ │ │ │ │ ├── 5.png │ │ │ │ │ │ ├── 5.svg │ │ │ │ │ │ ├── 6.gif │ │ │ │ │ │ ├── 6.png │ │ │ │ │ │ ├── 6.svg │ │ │ │ │ │ ├── 7.gif │ │ │ │ │ │ ├── 7.png │ │ │ │ │ │ ├── 7.svg │ │ │ │ │ │ ├── 8.gif │ │ │ │ │ │ ├── 8.png │ │ │ │ │ │ ├── 8.svg │ │ │ │ │ │ ├── 9.gif │ │ │ │ │ │ ├── 9.png │ │ │ │ │ │ └── 9.svg │ │ │ │ │ ├── caution.gif │ │ │ │ │ ├── caution.png │ │ │ │ │ ├── caution.svg │ │ │ │ │ ├── caution.tif │ │ │ │ │ ├── colorsvg │ │ │ │ │ │ ├── caution.svg │ │ │ │ │ │ ├── home.svg │ │ │ │ │ │ ├── important.svg │ │ │ │ │ │ ├── next.svg │ │ │ │ │ │ ├── note.svg │ │ │ │ │ │ ├── prev.svg │ │ │ │ │ │ ├── tip.svg │ │ │ │ │ │ ├── up.svg │ │ │ │ │ │ └── warning.svg │ │ │ │ │ ├── draft.png │ │ │ │ │ ├── home.gif │ │ │ │ │ ├── home.png │ │ │ │ │ ├── home.svg │ │ │ │ │ ├── important.gif │ │ │ │ │ ├── important.png │ │ │ │ │ ├── important.svg │ │ │ │ │ ├── important.tif │ │ │ │ │ ├── next.gif │ │ │ │ │ ├── next.png │ │ │ │ │ ├── next.svg │ │ │ │ │ ├── note.gif │ │ │ │ │ ├── note.png │ │ │ │ │ ├── note.svg │ │ │ │ │ ├── note.tif │ │ │ │ │ ├── prev.gif │ │ │ │ │ ├── prev.png │ │ │ │ │ ├── prev.svg │ │ │ │ │ ├── tip.gif │ │ │ │ │ ├── tip.png │ │ │ │ │ ├── tip.svg │ │ │ │ │ ├── tip.tif │ │ │ │ │ ├── toc-blank.png │ │ │ │ │ ├── toc-minus.png │ │ │ │ │ ├── toc-plus.png │ │ │ │ │ ├── up.gif │ │ │ │ │ ├── up.png │ │ │ │ │ ├── up.svg │ │ │ │ │ ├── warning.gif │ │ │ │ │ ├── warning.png │ │ │ │ │ ├── warning.svg │ │ │ │ │ └── warning.tif │ │ │ │ └── site │ │ │ │ │ ├── index.htm │ │ │ │ │ └── style.css │ │ │ ├── elf_examples │ │ │ │ ├── 64bitLOAD.elf │ │ │ │ ├── ARMSCII-8.so │ │ │ │ ├── arm_v7m_test_debug.elf │ │ │ │ ├── arm_v7m_test_release.elf │ │ │ │ ├── asm │ │ │ │ ├── asm.lst │ │ │ │ ├── asm.readelf │ │ │ │ ├── asm.s │ │ │ │ ├── asm64 │ │ │ │ ├── asm64.lst │ │ │ │ ├── crash-060833f08dc14d1712428742b3cad7af17b36bb7 │ │ │ │ ├── crash-7d695153fd8052529d480c2352d4ada33a44bada │ │ │ │ ├── crash-b82f05b0b25c8fdc98480e6d76b6d5f9164ae2bc │ │ │ │ ├── crash-e1ce7cecf01cf800397a4302854d9d76fa19763c │ │ │ │ ├── crash-e3c41070342cf84dea077356ddbb8ebf4326a601 │ │ │ │ ├── elf_header_i386_32.elf │ │ │ │ ├── entropy.so │ │ │ │ ├── hello.c │ │ │ │ ├── hello_32 │ │ │ │ ├── hello_32.txt │ │ │ │ ├── hello_32_o.txt │ │ │ │ ├── hello_64 │ │ │ │ ├── hello_64.txt │ │ │ │ ├── hello_64_o.txt │ │ │ │ ├── hello_arm │ │ │ │ ├── hello_arm_stripped │ │ │ │ ├── libfunc.so │ │ │ │ ├── libfunc32.so │ │ │ │ ├── ls │ │ │ │ ├── ls.readelf │ │ │ │ ├── main │ │ │ │ ├── main32 │ │ │ │ ├── ppc-32bit-specimen3.elf │ │ │ │ ├── read_write_arm_elf32_input │ │ │ │ ├── startup.eln │ │ │ │ ├── startup_orig.eln │ │ │ │ ├── test_ppc │ │ │ │ ├── test_ppc.cpp │ │ │ │ ├── test_ppc.txt │ │ │ │ ├── test_ppc_o.txt │ │ │ │ ├── write_exe_i386_32_match │ │ │ │ └── write_exe_i386_32_work_dump.txt │ │ │ ├── elfio │ │ │ │ ├── elf_types.hpp │ │ │ │ ├── elfio.hpp │ │ │ │ ├── elfio_dump.hpp │ │ │ │ ├── elfio_dynamic.hpp │ │ │ │ ├── elfio_header.hpp │ │ │ │ ├── elfio_note.hpp │ │ │ │ ├── elfio_relocation.hpp │ │ │ │ ├── elfio_section.hpp │ │ │ │ ├── elfio_segment.hpp │ │ │ │ ├── elfio_strings.hpp │ │ │ │ ├── elfio_symbols.hpp │ │ │ │ └── elfio_utils.hpp │ │ │ ├── examples │ │ │ │ ├── Makefile.am │ │ │ │ ├── Makefile.in │ │ │ │ ├── RelocationTable │ │ │ │ │ └── RelocationTable.cpp │ │ │ │ ├── anonymizer │ │ │ │ │ ├── Makefile.am │ │ │ │ │ ├── Makefile.in │ │ │ │ │ └── anonymizer.cpp │ │ │ │ ├── elfdump │ │ │ │ │ ├── ELFDump.vcxproj │ │ │ │ │ ├── Makefile.am │ │ │ │ │ ├── Makefile.in │ │ │ │ │ └── elfdump.cpp │ │ │ │ ├── tutorial │ │ │ │ │ ├── Makefile.am │ │ │ │ │ ├── Makefile.in │ │ │ │ │ └── tutorial.cpp │ │ │ │ ├── write_obj │ │ │ │ │ ├── Makefile.am │ │ │ │ │ ├── Makefile.in │ │ │ │ │ └── write_obj.cpp │ │ │ │ └── writer │ │ │ │ │ ├── Makefile.am │ │ │ │ │ ├── Makefile.in │ │ │ │ │ ├── writer.cpp │ │ │ │ │ ├── writer.vcxproj │ │ │ │ │ ├── writer.vcxproj.filters │ │ │ │ │ └── writer.vcxproj.user │ │ │ ├── install-sh │ │ │ └── missing │ │ ├── jtag_rbb.cpp │ │ ├── jtag_rbb.hpp │ │ └── main.cpp │ ├── debug │ │ ├── bus-pirate.cfg │ │ ├── esp-prog.cfg │ │ ├── riscv_pulp.cfg │ │ └── riscv_pulp_fpga.cfg │ ├── inc │ │ ├── config_ri5cy.v │ │ └── config_soc.v │ ├── waveform_template │ │ ├── ahb_size.tmpl │ │ └── gtkwave_tmpl.gtkw │ └── wrappers │ │ ├── fpga_wrapper │ │ └── fpga_wrapper.sv │ │ ├── ri5cy_ahb_wrapper.sv │ │ └── riscv_soc.sv └── verilator-model │ ├── boot_rom.sv │ ├── cdc_2phase.sv │ ├── cluster_clock_gating.sv │ ├── fifo_v2.sv │ ├── fifo_v3.sv │ ├── riscv_tb_pkg.sv │ ├── rstgen.sv │ └── rstgen_bypass.sv ├── pyftdi ├── INSTALL ├── __init__.py ├── bin │ ├── ftdi_urls.py │ ├── i2cscan.py │ └── uphy.sh ├── bits.py ├── doc │ ├── api │ │ ├── ftdi.rst │ │ ├── gpio.rst │ │ ├── i2c.rst │ │ ├── index.rst │ │ ├── misc.rst │ │ ├── spi.rst │ │ ├── uart.rst │ │ └── usbtools.rst │ ├── authors.rst │ ├── conf.py │ ├── defs.rst │ ├── features.rst │ ├── index.rst │ ├── installation.rst │ ├── licenses.rst │ ├── pinout.rst │ ├── requirements.rst │ ├── troubleshooting.rst │ └── urlscheme.rst ├── ftdi.py ├── gpio.py ├── i2c.py ├── jtag.py ├── misc.py ├── serialext │ ├── __init__.py │ ├── logger.py │ ├── protocol_ftdi.py │ ├── protocol_unix.py │ ├── serialext.rst │ └── tests │ │ ├── pyterm.py │ │ ├── rl.py │ │ └── term.py ├── spi.py ├── tests │ ├── bits.py │ ├── ftdi.py │ ├── gpio.py │ ├── i2c.py │ ├── jtag.py │ ├── spi.py │ ├── timearray.py │ └── uart.py ├── tracer.py └── usbtools.py ├── readme.md ├── reve ├── Makefile ├── apb_master_mux.v ├── apb_target_rv_timer.v ├── apb_target_sram_interface.v ├── apb_target_uart_minimal.v ├── clock_divider.v ├── clock_timer.v ├── jtag_tap.v ├── main.cpp ├── ocd.py ├── quartus │ ├── ftdi │ │ ├── reve.qpf │ │ └── top.qsf │ └── virtual │ │ ├── jtag_tapv.v │ │ ├── reve.qpf │ │ ├── top.qsf │ │ ├── top.v │ │ └── virtual_jtag.v ├── riscv_csrs_decode.v ├── riscv_csrs_machine_debug.v ├── riscv_csrs_machine_only.v ├── riscv_csrs_minimal.v ├── riscv_i32_alu.v ├── riscv_i32_control_flow.v ├── riscv_i32_debug.v ├── riscv_i32_debug_decode.v ├── riscv_i32_decode.v ├── riscv_i32_dmem_read_data.v ├── riscv_i32_dmem_request.v ├── riscv_i32_minimal.v ├── riscv_i32_minimal_apb.v ├── riscv_i32_muldiv.v ├── riscv_i32_pipeline_control.v ├── riscv_i32_pipeline_control_csr_trace.v ├── riscv_i32_pipeline_control_fetch_data.v ├── riscv_i32_pipeline_control_fetch_req.v ├── riscv_i32_pipeline_control_flow.v ├── riscv_i32_pipeline_trap_interposer.v ├── riscv_i32_trace.v ├── riscv_i32_trace_compression.v ├── riscv_i32_trace_decompression.v ├── riscv_i32_trace_pack.v ├── riscv_i32c_decode.v ├── riscv_i32c_pipeline.v ├── riscv_jtag_apb_dm.v ├── srams.v ├── top.v ├── uart_minimal.v └── vlist.txt ├── saxon ├── SmpLinux.scala ├── SmpLinux.v ├── main.cpp ├── makefile ├── ocd.py └── quartus │ ├── ftdi │ ├── saxon.qpf │ └── saxon.qsf │ └── virtual │ ├── SmpLinux.v │ ├── VJTAG.v │ ├── saxon.qpf │ └── saxon.qsf ├── sim.py ├── simframework ├── framework.h ├── jtag.h └── uart.h ├── sw ├── murax │ ├── firmware.mmap │ └── src │ │ ├── bsp.c │ │ ├── crt1.s │ │ ├── hello │ │ └── main.c │ │ ├── lib.c │ │ ├── stdarg.h │ │ └── stdio.h ├── pulp │ ├── firmware.mmap │ └── src │ │ ├── bsp.c │ │ ├── crt1.s │ │ ├── floathw │ │ ├── es │ │ │ ├── es.c │ │ │ ├── printf.h │ │ │ └── printf_cfg.h │ │ ├── main.c │ │ ├── math │ │ │ ├── _ieee.c │ │ │ ├── _poly.c │ │ │ ├── acos.c │ │ │ ├── asin.c │ │ │ ├── atan.c │ │ │ ├── atan2.c │ │ │ ├── ceil.c │ │ │ ├── cos.c │ │ │ ├── cosh.c │ │ │ ├── errno.c │ │ │ ├── errno.h │ │ │ ├── exp.c │ │ │ ├── fabs.c │ │ │ ├── float.h │ │ │ ├── floor.c │ │ │ ├── fmod.c │ │ │ ├── frexp.c │ │ │ ├── ieee.h │ │ │ ├── ldexp.c │ │ │ ├── limits.h │ │ │ ├── log.c │ │ │ ├── log10.c │ │ │ ├── math.h │ │ │ ├── mathlib.h │ │ │ ├── modf.c │ │ │ ├── pow.c │ │ │ ├── sin.c │ │ │ ├── sinh.c │ │ │ ├── sqrt.c │ │ │ ├── tan.c │ │ │ └── tanh.c │ │ └── softfloat │ │ │ ├── milieu.h │ │ │ ├── minimips-lcc.h │ │ │ ├── softfloat-macros │ │ │ ├── softfloat-specialize │ │ │ ├── softfloat.c │ │ │ └── softfloat.h │ │ ├── hello │ │ └── main.c │ │ ├── lib.c │ │ ├── stdarg.h │ │ ├── stdio.h │ │ └── uart_pulp.h ├── reve │ ├── firmware.mmap │ └── src │ │ ├── bsp.c │ │ ├── crt1.s │ │ ├── hello │ │ └── main.c │ │ ├── lib.c │ │ ├── stdarg.h │ │ └── stdio.h └── saxon │ ├── firmware.mmap │ └── src │ ├── bsp.c │ ├── crt1.s │ ├── hello │ ├── bsp.h │ ├── clint.h │ ├── io.h │ ├── main.c │ ├── soc.h │ ├── type.h │ └── uart.h │ ├── lib.c │ ├── stdarg.h │ ├── stdint.h │ └── stdio.h └── usb ├── __init__.py ├── _debug.py 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