├── .gitignore ├── .gitmodules ├── LICENSE ├── MF8A18 ├── fw_sf2 │ ├── brd_mdp.inc │ ├── brd_s7m.inc │ ├── brd_sf2.inc │ ├── do_mf8a18.bat │ ├── hex2mem.exe │ ├── mf8a18.exe │ ├── mf8a18.ini │ ├── riscv.inc │ ├── system.inc │ ├── test.bas │ ├── test.hex │ ├── test.lst │ ├── test.mem │ ├── txuart.inc │ └── txuart_out.inc └── fw_up5k │ ├── brd_mdp.inc │ ├── brd_s7m.inc │ ├── brd_sf2.inc │ ├── do_mf8a18.bat │ ├── hex2mem.exe │ ├── mf8a18.exe │ ├── mf8a18.ini │ ├── riscv.inc │ ├── spi_boot.inc │ ├── system.inc │ ├── test.bas │ ├── test.hex │ ├── test.lst │ ├── test.mem │ ├── txuart.inc │ └── txuart_out.inc ├── README.docx ├── README.md ├── README.pdf ├── boards ├── gowin │ └── TEC0117-LittleBee │ │ └── resources_1NR9.png ├── lattice │ ├── UPDuino2 │ │ └── UART_echoloop │ │ │ ├── UART_echoloop.bin │ │ │ ├── echoloop.vhd │ │ │ └── user.pdc │ └── iCE40-UltraPlus-MDP │ │ ├── MDP_setup.jpg │ │ ├── README.md │ │ ├── demos │ │ └── zephyr │ │ │ ├── README.md │ │ │ ├── mdp_zephyr_philo.bin │ │ │ ├── mdp_zephyr_synch.bin │ │ │ └── philosopher_iCE40UP.png │ │ └── icecube2 │ │ ├── engine_test_Implmnt │ │ └── sbt │ │ │ └── outputs │ │ │ ├── MF8A18_SoC_sbt.rpt │ │ │ ├── bitmap │ │ │ └── MF8A18_SoC_bitmap.bin │ │ │ ├── packer │ │ │ └── MF8A18_SoC_pack.rpt │ │ │ └── placer │ │ │ └── placer.log │ │ ├── engine_test_lse.prj │ │ ├── engine_test_sbt.project │ │ ├── engine_test_syn.prj │ │ ├── pin_constraints.png │ │ ├── radiant_programmer.png │ │ ├── resources_used.png │ │ └── src │ │ ├── MF8A18.v │ │ ├── MF8A18_SoC.v │ │ ├── RAM32K.v │ │ ├── ROM512K16.v │ │ ├── addsub8.v │ │ ├── clk.sdc │ │ ├── io.pcf │ │ ├── mf8_alu.v │ │ ├── mf8_core.v │ │ ├── mf8_pcs.v │ │ └── mf8_reg.v ├── microchip │ ├── CreativeBoard-SF2 │ │ ├── Libero │ │ │ ├── Creative_SF2.zip │ │ │ └── eNVM │ │ │ │ ├── assisted_boot.hex │ │ │ │ ├── mf8a18.hex │ │ │ │ ├── zephyr-philo.hex │ │ │ │ └── zephyr-synch.hex │ │ ├── README.md │ │ ├── SoftConsole │ │ │ └── assisted_boot.7z │ │ ├── bitstreams │ │ │ └── bitstreams.7z │ │ └── doc │ │ │ ├── assisted_boot_console_output.png │ │ │ ├── eNVM_clients.png │ │ │ └── sd_mss.png │ ├── SMF2000 │ │ └── README.md │ └── SmartBerry │ │ └── README.md └── xilinx │ └── bml-S7-Mini │ ├── README.md │ ├── board_files │ └── TE0890_25_1C │ │ └── 1.0 │ │ ├── board.xml │ │ ├── part0_pins.xml │ │ ├── preset.xml │ │ └── te0890_board.png │ └── engine-V-bml-s7-mini.png ├── tools ├── ROM512K16.v └── mem2v.py └── verilator ├── README.md ├── bin └── bin.7z ├── bitstream └── mf8a18_rv32i.bin ├── build ├── do_exe.bat ├── engine-v.exe ├── riscv.mem ├── rv32i.mem └── spiflash.hex ├── build_mss ├── do_exe.bat ├── engine-v.exe ├── riscv.mem └── rv32i.mem ├── dll └── dll.7z ├── hdl ├── 27MHz │ └── baudgen.v ├── 50MHz │ └── baudgen.v ├── MF8A18.v ├── MF8A18_SoC.v ├── RAM32K.v ├── ROM1K16.v ├── addsub8.v ├── baudgen.v ├── build_27MHz.bat ├── mf8_alu.v ├── mf8_core.v ├── mf8_pcs.v ├── mf8_reg.v ├── rx.v ├── spiflash.v ├── tb.cc └── tb.v ├── hdl_mss ├── 50MHz │ └── baudgen.v ├── MF8A18.v ├── MF8A18_SoC.v ├── RAM32K.v ├── RAM32KAHB.v ├── ROM1K16.v ├── addsub8.v ├── baudgen.v ├── build_50MHz.bat ├── mf8_alu.v ├── mf8_core.v ├── mf8_pcs.v ├── mf8_reg.v ├── proc_sys_sb.v ├── rx.v ├── tb.cc └── tb.v ├── images ├── I-ADD-01.bin ├── I-ADD-01.mem ├── I-ADDI-01.bin ├── I-ADDI-01.mem ├── I-AND-01.bin ├── I-AND-01.mem ├── I-ANDI-01.bin ├── I-ANDI-01.mem ├── I-AUIPC-01.bin ├── I-AUIPC-01.mem ├── I-BEQ-01.bin ├── I-BEQ-01.mem ├── I-BGE-01.bin ├── I-BGE-01.mem ├── I-BGEU-01.bin ├── I-BGEU-01.mem ├── I-BLT-01.bin ├── I-BLT-01.mem ├── I-BLTU-01.bin ├── I-BLTU-01.mem ├── I-BNE-01.bin ├── I-BNE-01.mem ├── I-CSRRC-01.bin ├── I-CSRRC-01.mem ├── I-CSRRCI-01.bin ├── I-CSRRCI-01.mem ├── I-CSRRS-01.bin ├── I-CSRRS-01.mem ├── I-CSRRSI-01.bin ├── I-CSRRSI-01.mem ├── I-CSRRW-01.bin ├── I-CSRRW-01.mem ├── I-CSRRWI-01.bin ├── I-CSRRWI-01.mem ├── I-DELAY_SLOTS-01.bin ├── I-DELAY_SLOTS-01.mem ├── I-EBREAK-01.bin ├── I-EBREAK-01.mem ├── I-ECALL-01.bin ├── I-ECALL-01.mem ├── I-ENDIANESS-01.bin ├── I-ENDIANESS-01.mem ├── I-FENCE.I-01.bin ├── I-FENCE.I-01.mem ├── I-IO-01.bin ├── I-IO-01.mem ├── I-JAL-01.bin ├── I-JAL-01.mem ├── I-JALR-01.bin ├── I-JALR-01.mem ├── I-LB-01.bin ├── I-LB-01.mem ├── I-LBU-01.bin ├── I-LBU-01.mem ├── I-LH-01.bin ├── I-LH-01.mem ├── I-LHU-01.bin ├── I-LHU-01.mem ├── I-LUI-01.bin ├── I-LUI-01.mem ├── I-LW-01.bin ├── I-LW-01.mem ├── I-MISALIGN_JMP-01.bin ├── I-MISALIGN_JMP-01.mem ├── I-MISALIGN_LDST-01.bin ├── I-MISALIGN_LDST-01.mem ├── I-NOP-01.bin ├── I-NOP-01.mem ├── I-OR-01.bin ├── I-OR-01.mem ├── I-ORI-01.bin ├── I-ORI-01.mem ├── I-RF_size-01.bin ├── I-RF_size-01.mem ├── I-RF_width-01.bin ├── I-RF_width-01.mem ├── I-RF_x0-01.bin ├── I-RF_x0-01.mem ├── I-SB-01.bin ├── I-SB-01.mem ├── I-SH-01.bin ├── I-SH-01.mem ├── I-SLL-01.bin ├── I-SLL-01.mem ├── I-SLLI-01.bin ├── I-SLLI-01.mem ├── I-SLT-01.bin ├── I-SLT-01.mem ├── I-SLTI-01.bin ├── I-SLTI-01.mem ├── I-SLTIU-01.bin ├── I-SLTIU-01.mem ├── I-SLTU-01.bin ├── I-SLTU-01.mem ├── I-SRA-01.bin ├── I-SRA-01.mem ├── I-SRAI-01.bin ├── I-SRAI-01.mem ├── I-SRL-01.bin ├── I-SRL-01.mem ├── I-SRLI-01.bin ├── I-SRLI-01.mem ├── I-SUB-01.bin ├── I-SUB-01.mem ├── I-SW-01.bin ├── I-SW-01.mem ├── I-XOR-01.bin ├── I-XOR-01.mem ├── I-XORI-01.bin ├── I-XORI-01.mem ├── zephyr-philo.bin ├── zephyr-philo.mem ├── zephyr-synch.bin └── zephyr-synch.mem ├── mf8a18 ├── README.md ├── creative_sf2 │ └── rv32i.mem └── mdp │ └── rv32i.mem ├── references ├── I-ADD-01.reference_output ├── I-ADDI-01.reference_output ├── I-AND-01.reference_output ├── I-ANDI-01.reference_output ├── I-AUIPC-01.reference_output ├── I-BEQ-01.reference_output ├── I-BGE-01.reference_output ├── I-BGEU-01.reference_output ├── I-BLT-01.reference_output ├── I-BLTU-01.reference_output ├── I-BNE-01.reference_output ├── I-CSRRC-01.reference_output ├── I-CSRRCI-01.reference_output ├── I-CSRRS-01.reference_output ├── I-CSRRSI-01.reference_output ├── I-CSRRW-01.reference_output ├── I-CSRRWI-01.reference_output ├── I-DELAY_SLOTS-01.reference_output ├── I-EBREAK-01.reference_output ├── I-ECALL-01.reference_output ├── I-ENDIANESS-01.reference_output ├── I-FENCE.I-01.reference_output ├── I-HI-01.reference_output ├── I-IO-01.reference_output ├── I-JAL-01.reference_output ├── I-JALR-01.reference_output ├── I-LB-01.reference_output ├── I-LBU-01.reference_output ├── I-LH-01.reference_output ├── I-LHU-01.reference_output ├── I-LUI-01.reference_output ├── I-LW-01.reference_output ├── I-MISALIGN_JMP-01.reference_output ├── I-MISALIGN_LDST-01.reference_output ├── I-NOP-01.reference_output ├── I-OR-01.reference_output ├── I-ORI-01.reference_output ├── I-PI-01.reference_output ├── I-RF_size-01.reference_output ├── I-RF_width-01.reference_output ├── I-RF_x0-01.reference_output ├── I-SB-01.reference_output ├── I-SH-01.reference_output ├── I-SLL-01.reference_output ├── I-SLLI-01.reference_output ├── I-SLT-01.reference_output ├── I-SLTI-01.reference_output ├── I-SLTIU-01.reference_output ├── I-SLTU-01.reference_output ├── I-SRA-01.reference_output ├── I-SRAI-01.reference_output ├── I-SRL-01.reference_output ├── I-SRLI-01.reference_output ├── I-SUB-01.reference_output ├── I-SW-01.reference_output ├── I-TEST-01.reference_output ├── I-UART-01.reference_output ├── I-XOR-01.reference_output ├── I-XORI-01.reference_output └── I-dr-01.reference_output ├── run ├── RV32I_Compliance.txt ├── run_philo.bat ├── run_rv32i_add.bat ├── run_rv32i_all.bat ├── run_synch.bat └── runverilator.bat ├── run_mss ├── RV32I_Compliance.txt ├── run_philo.bat ├── run_rv32i_add.bat ├── run_rv32i_all.bat ├── run_synch.bat └── runverilator.bat ├── scripts ├── bin2hex.py ├── concat_up5k.py └── extract_sig.py └── signatures └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | *.local 3 | *.identcache 4 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "riscv-compliance"] 2 | path = riscv-compliance 3 | url = https://github.com/micro-FPGA/riscv-compliance.git 4 | [submodule "zephyr"] 5 | path = zephyr 6 | url = https://github.com/micro-FPGA/zephyr 7 | [submodule "riscv-tests"] 8 | path = riscv-tests 9 | url = https://github.com/micro-FPGA/riscv-tests.git 10 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/brd_mdp.inc: -------------------------------------------------------------------------------- 1 | const UART_BAUDCONST = 77; // 115200 @27MHz 2 | 3 | Const SPI_ADDR3 = $02 4 | 5 | 6 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/brd_s7m.inc: -------------------------------------------------------------------------------- 1 | 2 | const UART_BAUDCONST = 143; // 115200 @50MHz 3 | 4 | Const SPI_ADDR3 = $00 5 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/brd_sf2.inc: -------------------------------------------------------------------------------- 1 | 2 | const UART_BAUDCONST = 143; // 115200 @50MHz 3 | 4 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/do_mf8a18.bat: -------------------------------------------------------------------------------- 1 | set PROJ=test 2 | 3 | del %PROJ%.lst 4 | del %PROJ%.obj 5 | del %PROJ%.rom 6 | 7 | mf8a18 %PROJ%.bas 8 | 9 | copy %PROJ%.rom %PROJ%.hex 10 | del %PROJ%.rom 11 | del %PROJ%.obj 12 | 13 | hex2mem %PROJ%.hex > %PROJ%.mem 14 | copy test.mem ..\build_mss\rv32i.mem 15 | 16 | 17 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/hex2mem.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/MF8A18/fw_sf2/hex2mem.exe -------------------------------------------------------------------------------- /MF8A18/fw_sf2/mf8a18.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/MF8A18/fw_sf2/mf8a18.exe -------------------------------------------------------------------------------- /MF8A18/fw_sf2/mf8a18.ini: -------------------------------------------------------------------------------- 1 | [SFR] 2 | UART_TX = $00 3 | SPI_CS = $08 4 | SPI_SCK = $10 5 | SPI_MOSI = $18 6 | SPI_MISO = $18 7 | FLAGS = $3F 8 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/riscv.inc: -------------------------------------------------------------------------------- 1 | // Microcode Mnemonics for RISC-V 2 | 3 | var ZERO: byte @R0; 4 | var FF: byte @R1; 5 | 6 | var ECAUSE: byte @R9; 7 | var PC: word @R10; 8 | var oldPC: word @R12; 9 | 10 | // Instruction word 11 | var I0: byte @R16; 12 | var I1: byte @R17; 13 | var I2: byte @R18; 14 | var I3: byte @R19; 15 | 16 | // Destination work area 17 | var RD0: byte @R20; 18 | var RD1: byte @R21; 19 | var RD2: byte @R22; 20 | var RD3: byte @R23; 21 | 22 | var RS2_0: byte @R24; 23 | var RS2_1: byte @R25; 24 | var RS2_2: byte @R26; 25 | var RS2_3: byte @R27; 26 | 27 | var TEMP: byte @R28; 28 | // 29 is WREG 29 | var Z: word @W30; 30 | var Zlo: byte @R30; 31 | var Zhi: byte @R31; 32 | 33 | 34 | var RS1_0: byte @R12; 35 | var RS1_1: byte @R13; 36 | var RS1_2: byte @R14; 37 | var RS1_3: byte @R15; 38 | 39 | 40 | 41 | const RRH = $F1; 42 | const CRH = $F2; 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/system.inc: -------------------------------------------------------------------------------- 1 | //////////////////////////////////// 2 | Z.hi := CRH 3 | Z.lo := $10 // mepc 4 | TEMP := 0; 5 | 6 | // EBREAK/ECALL ? 7 | WREG := I1 8 | WREG := WREG and $70 9 | if WREG=0 then 10 | if not I3.4 then SYS_xxx0_xxxx_xxxx 11 | SYS_xxxx_xxxx_xxxx: 12 | if I3.5 then do_exec // MRET 13 | // WFI 14 | TEMP := $80 15 | 16 | 17 | SYS_xxx0_xxxx_xxxx: 18 | // ECALL/EBREAK 19 | RAM[Z] := PC.lo // mepc 20 | RAM[Z+1] := PC.hi // 21 | 22 | WREG := $03 // ECALL/EBREAK 23 | if I2.4 then skip 24 | or WREG, $08 25 | if temp=0 then skip 26 | wreg := 7 // MTIMER intterrupt 27 | Z.lo := $23; 28 | RAM[Z] := TEMP; // Interrupt flag 29 | go_mtvec_ecause: 30 | Z.lo := $20 // mcause 31 | RAM[Z] := WREG // 32 | go_mtvec: 33 | Z.lo := $50 // mtvec 34 | do_exec: 35 | PC.lo := RAM[Z] // 36 | PC.hi := RAM[Z+1] // 37 | 38 | goto MainStart 39 | end 40 | ////////////////////////////////////////////// 41 | 42 | 43 | Z.lo := I2 44 | and Z.lo, $F0 45 | 46 | // if I3=$34 then 47 | 48 | // end 49 | 50 | if I3.7 then 51 | Z.lo := Z.lo or $4 52 | end 53 | 54 | // 55 | // read CSR 56 | // 57 | RD0 := RAM[Z]; 58 | RD1 := RAM[Z+1]; 59 | RD2 := RAM[Z+2]; 60 | RD3 := RAM[Z+3]; 61 | // 62 | // CSR loaded 63 | // 64 | if not I1.6 then goto csr_notimm 65 | // todo get 5 bit immed value 66 | RS1_0 := i2; 67 | RS1_0 := RS1_0 and $0F; 68 | add RS1_0, RS1_0 69 | if not I1.7 then skip; 70 | sub RS1_0,FF 71 | RS1_1 := 0; 72 | RS1_2 := 0; 73 | RS1_3 := 0; 74 | csr_notimm: 75 | if not I1.5 then goto CSR_WRITE 76 | if I1.4 then goto Do_CSRRC 77 | // Set Bits 78 | // Set Bits 79 | RS1_0 := RS1_0 or RD0 80 | RS1_1 := RS1_1 or RD1 81 | RS1_2 := RS1_2 or RD2 82 | RS1_3 := RS1_3 or RD3 83 | goto CSR_WRITE 84 | Do_CSRRC: 85 | WREG := $FF 86 | RS1_0 := RS1_0 xor WREG 87 | RS1_1 := RS1_1 xor WREG 88 | RS1_2 := RS1_2 xor WREG 89 | RS1_3 := RS1_3 xor WREG 90 | 91 | RS1_0 := RS1_0 and RD0 92 | RS1_1 := RS1_1 and RD1 93 | RS1_2 := RS1_2 and RD2 94 | RS1_3 := RS1_3 and RD3 95 | CSR_WRITE: 96 | // 97 | // Write back here 98 | // 99 | // write CSR 100 | RAM[Z+3] := RS1_3; 101 | RAM[Z+2] := RS1_2; 102 | RAM[Z+1] := RS1_1; 103 | RAM[Z] := RS1_0 104 | ////////////////////////////////// 105 | 106 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/test.hex: -------------------------------------------------------------------------------- 1 | :10000000F0E00F2EFFEF1F2EA02CB02C27C0F4E045 2 | :1000100001C0F6E0CA2CDB2CAE2EBF2E14C040E08F 3 | :1000200050E060E070E0E12FE295E07F07FDE860DE 4 | :10003000EE2329F0F1EF4083518362837383FA2D1D 5 | :10004000F1FF09C0F0E0F2EFE0E3A082B182E0E16D 6 | :10005000C082D182CFC0F4E0AF0EB01CCA2CDB2C22 7 | :10006000EA2DFB2D008111812281338102FD72C1B5 8 | :10007000E22FE295E07F17FDE860F1EFC080D180CC 9 | :10008000E280F38005FD97C07FEF6FEF422F42952E 10 | :100090004F703295532F506F307F432B53FD03C069 11 | :1000A0005F7060E070E004FF54C016FD09C015FDEC 12 | :1000B00043C014FD1BC04C0D5D1D6E1D7F1DB3CFD5 13 | :1000C00015FD07C014FD26C04C255D256E257F2536 14 | :1000D000AACF14FD05C04C295D296E297F29A3CF25 15 | :1000E0004C215D216E217F219ECF482F4F7131F031 16 | :1000F000CC0CDD1CEE1CFF1C410DD1F74C2D5D2DF1 17 | :100100006E2D7F2D90CF15FDE4CF14FFDDCF482F4E 18 | :10011000532F52954F7191F352FF07C0F594E79416 19 | :10012000D794C794410DD1F7E9CFF694E794D794CB 20 | :10013000C794410DD1F7E2CF14FD03C0F0E8FF0EE4 21 | :100140007F0FC41AD50AE60AF70A08F068CF41E023 22 | :1001500067CF06FF0FC0C40ED51EF4E0AF0EB01C73 23 | :100160004A2D5B2DFEEFCF22AC2CBD2CF4E0AF1A54 24 | :10017000B00857CFEC2DFD2DE40FF51F408114FD85 25 | :1001800014C015FD0AC016FD4BCF47FF49CF5FEFE6 26 | :1001900057FF47CF6FEF7FEF46CFE0FD38CFE1FD50 27 | :1001A00036CF5181628173813ECFE0FD30CF5181E6 28 | :1001B00016FFEECF36CF06FF4EC004FD05C003FD8F 29 | :1001C0004AC002FF48C060CFF2EFE0E1C0E0F12F8B 30 | :1001D000F077FF23A9F434FF03C035FD0EC0C0E85B 31 | :1001E000A082B182F3E024FFF860CC2309F0F7E0AD 32 | :1001F000E3E2C083E0E2F083E0E5A080B1802ECFAF 33 | :10020000E22FE07F37FF01C0E460408151816281CD 34 | :10021000738116FF09C0C22EFFE0CF22CC0C17FD60 35 | :10022000C118DD24EE24FF2415FF10C014FD05C005 36 | :10023000C42AD52AE62AF72A09C0FFEFCF26DF26EF 37 | :10024000EF26FF26C422D522E622F722F382E2829D 38 | :10025000D182C082E8CE06FD12C004FD10C0412F3D 39 | :10026000440F4E7107FD4160F32FF295F07E4F2B46 40 | :10027000532F5295577037FD586FC40ED51EE22F7D 41 | :10028000E69530FDE068E87FF1EF80819181A28101 42 | :10029000B38106FF2AC015FD03C0F0E8FF26BF2783 43 | :1002A000C81AD90AEA0AFB0A16FF16C014FD02C0D2 44 | :1002B00010F0C5CEB8F0110F1E713295F32FF07EFD 45 | :1002C0001F2B3F7033FD3061377107FD386034FDFF 46 | :1002D000306EA10EB31EC2CECD28CE28CF2814FF7B 47 | :1002E00002C049F7ACCE39F3AACE04FF11C0482FA3 48 | :1002F000592F6A2F7B2F16FD06CF15FD1DCF14FD3C 49 | :10030000F4CE36FFD8CEC81AD90AEA0AFB0AF6CECE 50 | :10031000EC2DFD2D14FD13C015FD11C08083F7FFDA 51 | :100320000DC0F5FD0BC0CAE000B8FFE8F10DF1F714 52 | :1003300080B987958068C10DC1F781CE80CEE0FD80 53 | :1003400068CE14FD04C0E1FD64CEB383A283808334 54 | :10035000918375CE04FD1DC005FF71CE03FF88CECD 55 | :100360003295377F24FD386022952E70C32EF0EF32 56 | :10037000CF22C22AD12EDF223F70D32AF4E0AF0E63 57 | :10038000B01C4A2D5B2DAC0CBD1CF8E0AF1AB008B8 58 | :1003900048CE732F622F512F507F40E005FD43CE92 59 | :0803A0004A2D5B0D40CE4BCE4F 60 | :00000001FF 61 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/txuart.inc: -------------------------------------------------------------------------------- 1 | // HAABBB G@@AAA 2 | // 3 | // Transmit Only UART implementation 4 | // 5 | // RAM[Z] := RS2_0; 6 | // stupid way to exclude CPI 7 | // WREG := Z.hi 8 | // WREG := WREG-$C0 9 | // if not FLAGS.1 then 10 | if not Zhi.7 then not_uart 11 | if Zhi.5 then not_uart 12 | 13 | temp := 10; // number of bits 14 | UART_TX = ZERO; // Start bit 15 | repeat 16 | wreg := UART_BAUDCONST; 17 | repeat 18 | ADD wreg,FF 19 | until FLAGS.1 20 | // until --wreg; // Bit delay 115200 50MHz 21 | UART_TX = RS2_0; // transmit bit 22 | ROR RS2_0; 23 | OR RS2_0, $80 // insert STOP bit 24 | ADD temp,FF 25 | until FLAGS.1 26 | // until --temp; 27 | Goto MainLoop 28 | // end; 29 | not_uart: 30 | 31 | // 32 | // 33 | // 34 | 35 | 36 | -------------------------------------------------------------------------------- /MF8A18/fw_sf2/txuart_out.inc: -------------------------------------------------------------------------------- 1 | temp := 10; // number of bits 2 | UART_TX = ZERO; // Start bit 3 | repeat 4 | wreg := UART_BAUDCONST; 5 | repeat 6 | ADD wreg,FF 7 | until FLAGS.1 8 | UART_TX = RS2_0; // transmit bit 9 | ROR RS2_0; 10 | OR RS2_0, $80 // insert STOP bit 11 | ADD temp,FF 12 | until FLAGS.1 13 | 14 | 15 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/brd_mdp.inc: -------------------------------------------------------------------------------- 1 | const UART_BAUDCONST = 77; // 115200 @27MHz 2 | 3 | Const SPI_ADDR3 = $02 4 | 5 | 6 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/brd_s7m.inc: -------------------------------------------------------------------------------- 1 | 2 | const UART_BAUDCONST = 143; // 115200 @50MHz 3 | 4 | Const SPI_ADDR3 = $00 5 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/brd_sf2.inc: -------------------------------------------------------------------------------- 1 | 2 | const UART_BAUDCONST = 143; // 115200 @50MHz 3 | 4 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/do_mf8a18.bat: -------------------------------------------------------------------------------- 1 | set PROJ=test 2 | 3 | del %PROJ%.lst 4 | del %PROJ%.obj 5 | del %PROJ%.rom 6 | 7 | mf8a18 %PROJ%.bas 8 | 9 | copy %PROJ%.rom %PROJ%.hex 10 | del %PROJ%.rom 11 | del %PROJ%.obj 12 | 13 | hex2mem %PROJ%.hex > %PROJ%.mem 14 | copy test.mem ..\build\rv32i.mem 15 | 16 | 17 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/hex2mem.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/MF8A18/fw_up5k/hex2mem.exe -------------------------------------------------------------------------------- /MF8A18/fw_up5k/mf8a18.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/MF8A18/fw_up5k/mf8a18.exe -------------------------------------------------------------------------------- /MF8A18/fw_up5k/mf8a18.ini: -------------------------------------------------------------------------------- 1 | [SFR] 2 | UART_TX = $00 3 | SPI_CS = $08 4 | SPI_SCK = $10 5 | SPI_MOSI = $18 6 | SPI_MISO = $18 7 | FLAGS = $3F 8 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/riscv.inc: -------------------------------------------------------------------------------- 1 | // Microcode Mnemonics for RISC-V 2 | 3 | var ZERO: byte @R0; 4 | var FF: byte @R1; 5 | 6 | var ECAUSE: byte @R9; 7 | var PC: word @R10; 8 | var oldPC: word @R12; 9 | 10 | // Instruction word 11 | var I0: byte @R16; 12 | var I1: byte @R17; 13 | var I2: byte @R18; 14 | var I3: byte @R19; 15 | 16 | // Destination work area 17 | var RD0: byte @R20; 18 | var RD1: byte @R21; 19 | var RD2: byte @R22; 20 | var RD3: byte @R23; 21 | 22 | var RS2_0: byte @R24; 23 | var RS2_1: byte @R25; 24 | var RS2_2: byte @R26; 25 | var RS2_3: byte @R27; 26 | 27 | var TEMP: byte @R28; 28 | // 29 is WREG 29 | var Z: word @W30; 30 | var Zlo: byte @R30; 31 | var Zhi: byte @R31; 32 | 33 | 34 | var RS1_0: byte @R12; 35 | var RS1_1: byte @R13; 36 | var RS1_2: byte @R14; 37 | var RS1_3: byte @R15; 38 | 39 | 40 | 41 | const RRH = $F1; 42 | const CRH = $F2; 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/spi_boot.inc: -------------------------------------------------------------------------------- 1 | 2 | RD3 := ZERO; // for verilator and simulation 3 | 4 | SPI_CS := FF; 5 | SPI_SCK := ZERO; 6 | 7 | //////////////////// 8 | SPI_CS := ZERO 9 | RD0 := $AB; // wakeup ! 10 | wreg := 0 11 | repeat 12 | SPI_MOSI := RD0; 13 | SPI_SCK := FF; 14 | ADD RD0, RD0 15 | SPI_SCK := ZERO; 16 | //inc wreg; 17 | SUB WREG,FF 18 | until wreg.3; 19 | SPI_CS := FF 20 | //////////////////// 21 | 22 | RD0 := $03; // first byte 23 | RD1 := SPI_ADDR3; //second byte to transmit 24 | 25 | SPI_CS := ZERO 26 | // we start at fake high address so we are at 0 when we get first byte 27 | Z.lo := $FC; 28 | Z.hi := $FF; 29 | 30 | bootloop: 31 | wreg := 0 32 | repeat 33 | RD2 := SPI_MISO; // Get SPI data 34 | AND RD2, 1; // only one 1 bit 35 | ADD RD3, RD3 36 | OR RD3, RD2 37 | SPI_MOSI := RD0; 38 | SPI_SCK := FF; 39 | ADD RD1, RD1 40 | ADC RD0, RD0 41 | SPI_SCK := ZERO; 42 | //inc wreg; 43 | SUB WREG,FF 44 | until wreg.3; 45 | 46 | RAM[Z] := RD3; 47 | ADD Z.lo, 1 48 | SBC Z.hi, FF 49 | if Zhi.6 then bootloop 50 | if not Zhi.7 then bootloop 51 | 52 | SPI_CS := FF; 53 | 54 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/system.inc: -------------------------------------------------------------------------------- 1 | //////////////////////////////////// 2 | Z.hi := CRH 3 | Z.lo := $10 // mepc 4 | TEMP := 0; 5 | 6 | // EBREAK/ECALL ? 7 | WREG := I1 8 | WREG := WREG and $70 9 | if WREG=0 then 10 | if not I3.4 then SYS_xxx0_xxxx_xxxx 11 | SYS_xxxx_xxxx_xxxx: 12 | if I3.5 then do_exec // MRET 13 | // WFI 14 | TEMP := $80 15 | 16 | 17 | SYS_xxx0_xxxx_xxxx: 18 | // ECALL/EBREAK 19 | RAM[Z] := PC.lo // mepc 20 | RAM[Z+1] := PC.hi // 21 | 22 | WREG := $03 // ECALL/EBREAK 23 | if I2.4 then skip 24 | or WREG, $08 25 | if temp=0 then skip 26 | wreg := 7 // MTIMER intterrupt 27 | Z.lo := $23; 28 | RAM[Z] := TEMP; // Interrupt flag 29 | go_mtvec_ecause: 30 | Z.lo := $20 // mcause 31 | RAM[Z] := WREG // 32 | go_mtvec: 33 | Z.lo := $50 // mtvec 34 | do_exec: 35 | PC.lo := RAM[Z] // 36 | PC.hi := RAM[Z+1] // 37 | 38 | goto MainStart 39 | end 40 | ////////////////////////////////////////////// 41 | 42 | 43 | Z.lo := I2 44 | and Z.lo, $F0 45 | 46 | // if I3=$34 then 47 | 48 | // end 49 | 50 | if I3.7 then 51 | Z.lo := Z.lo or $4 52 | end 53 | 54 | // 55 | // read CSR 56 | // 57 | RD0 := RAM[Z]; 58 | RD1 := RAM[Z+1]; 59 | RD2 := RAM[Z+2]; 60 | RD3 := RAM[Z+3]; 61 | // 62 | // CSR loaded 63 | // 64 | if not I1.6 then goto csr_notimm 65 | // todo get 5 bit immed value 66 | RS1_0 := i2; 67 | RS1_0 := RS1_0 and $0F; 68 | add RS1_0, RS1_0 69 | if not I1.7 then skip; 70 | sub RS1_0,FF 71 | RS1_1 := 0; 72 | RS1_2 := 0; 73 | RS1_3 := 0; 74 | csr_notimm: 75 | if not I1.5 then goto CSR_WRITE 76 | if I1.4 then goto Do_CSRRC 77 | // Set Bits 78 | // Set Bits 79 | RS1_0 := RS1_0 or RD0 80 | RS1_1 := RS1_1 or RD1 81 | RS1_2 := RS1_2 or RD2 82 | RS1_3 := RS1_3 or RD3 83 | goto CSR_WRITE 84 | Do_CSRRC: 85 | WREG := $FF 86 | RS1_0 := RS1_0 xor WREG 87 | RS1_1 := RS1_1 xor WREG 88 | RS1_2 := RS1_2 xor WREG 89 | RS1_3 := RS1_3 xor WREG 90 | 91 | RS1_0 := RS1_0 and RD0 92 | RS1_1 := RS1_1 and RD1 93 | RS1_2 := RS1_2 and RD2 94 | RS1_3 := RS1_3 and RD3 95 | CSR_WRITE: 96 | // 97 | // Write back here 98 | // 99 | // write CSR 100 | RAM[Z+3] := RS1_3; 101 | RAM[Z+2] := RS1_2; 102 | RAM[Z+1] := RS1_1; 103 | RAM[Z] := RS1_0 104 | ////////////////////////////////// 105 | 106 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/test.hex: -------------------------------------------------------------------------------- 1 | :10000000F0E00F2EFFEF1F2E702D18B800BA08B8C1 2 | :100010004BEAF0E048BB10BA440F00BAF119F3FF05 3 | :10002000F9CF18B843E052E008B8ECEFFFEFF0E08A 4 | :1000300068B36170770F762B48BB10BA550F441F19 5 | :1000400000BAF119F3FFF4CF7083EF5FF109F6FD09 6 | :10005000EECFF7FFECCF18B8A02CB02C27C0F4E0FF 7 | :1000600001C0F6E0CA2CDB2CAE2EBF2E14C040E03F 8 | :1000700050E060E070E0E12FE295E07F07FDE8608E 9 | :10008000EE2329F0F1EF4083518362837383FA2DCD 10 | :10009000F1FF09C0F0E0F2EFE0E3A082B182E0E11D 11 | :1000A000C082D182CFC0F4E0AF0EB01CCA2CDB2CD2 12 | :1000B000EA2DFB2D008111812281338102FD72C165 13 | :1000C000E22FE295E07F17FDE860F1EFC080D1807C 14 | :1000D000E280F38005FD97C07FEF6FEF422F4295DE 15 | :1000E0004F703295532F506F307F432B53FD03C019 16 | :1000F0005F7060E070E004FF54C016FD09C015FD9C 17 | :1001000043C014FD1BC04C0D5D1D6E1D7F1DB3CF84 18 | :1001100015FD07C014FD26C04C255D256E257F25E5 19 | :10012000AACF14FD05C04C295D296E297F29A3CFD4 20 | :100130004C215D216E217F219ECF482F4F7131F0E0 21 | :10014000CC0CDD1CEE1CFF1C410DD1F74C2D5D2DA0 22 | :100150006E2D7F2D90CF15FDE4CF14FFDDCF482FFE 23 | :10016000532F52954F7191F352FF07C0F594E794C6 24 | :10017000D794C794410DD1F7E9CFF694E794D7947B 25 | :10018000C794410DD1F7E2CF14FD03C0F0E8FF0E94 26 | :100190007F0FC41AD50AE60AF70A08F068CF41E0D3 27 | :1001A00067CF06FF0FC0C40ED51EF4E0AF0EB01C23 28 | :1001B0004A2D5B2DFEEFCF22AC2CBD2CF4E0AF1A04 29 | :1001C000B00857CFEC2DFD2DE40FF51F408114FD35 30 | :1001D00014C015FD0AC016FD4BCF47FF49CF5FEF96 31 | :1001E00057FF47CF6FEF7FEF46CFE0FD38CFE1FD00 32 | :1001F00036CF5181628173813ECFE0FD30CF518196 33 | :1002000016FFEECF36CF06FF4EC004FD05C003FD3E 34 | :100210004AC002FF48C060CFF2EFE0E1C0E0F12F3A 35 | :10022000F077FF23A9F434FF03C035FD0EC0C0E80A 36 | :10023000A082B182F3E024FFF860CC2309F0F7E05C 37 | :10024000E3E2C083E0E2F083E0E5A080B1802ECF5E 38 | :10025000E22FE07F37FF01C0E4604081518162817D 39 | :10026000738116FF09C0C22EFFE0CF22CC0C17FD10 40 | :10027000C118DD24EE24FF2415FF10C014FD05C0B5 41 | :10028000C42AD52AE62AF72A09C0FFEFCF26DF269F 42 | :10029000EF26FF26C422D522E622F722F382E2824D 43 | :1002A000D182C082E8CE06FD12C004FD10C0412FED 44 | :1002B000440F4E7107FD4160F32FF295F07E4F2BF6 45 | :1002C000532F5295577037FD586FC40ED51EE22F2D 46 | :1002D000E69530FDE068E87FF1EF80819181A281B1 47 | :1002E000B38106FF2AC015FD03C0F0E8FF26BF2733 48 | :1002F000C81AD90AEA0AFB0A16FF16C014FD02C082 49 | :1003000010F0C5CEB8F0110F1E713295F32FF07EAC 50 | :100310001F2B3F7033FD3061377107FD386034FDAE 51 | :10032000306EA10EB31EC2CECD28CE28CF2814FF2A 52 | :1003300002C049F7ACCE39F3AACE04FF11C0482F52 53 | :10034000592F6A2F7B2F16FD06CF15FD1DCF14FDEB 54 | :10035000F4CE36FFD8CEC81AD90AEA0AFB0AF6CE7E 55 | :10036000EC2DFD2D14FD13C015FD11C08083F7FF8A 56 | :100370000DC0F5FD0BC0CAE000B8FDE4F10DF1F7CA 57 | :1003800080B987958068C10DC1F781CE80CEE0FD30 58 | :1003900068CE14FD04C0E1FD64CEB383A2838083E4 59 | :1003A000918375CE04FD1DC005FF71CE03FF88CE7D 60 | :1003B0003295377F24FD386022952E70C32EF0EFE2 61 | :1003C000CF22C22AD12EDF223F70D32AF4E0AF0E13 62 | :1003D000B01C4A2D5B2DAC0CBD1CF8E0AF1AB00868 63 | :1003E00048CE732F622F512F507F40E005FD43CE42 64 | :0803F0004A2D5B0D40CE4BCEFF 65 | :00000001FF 66 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/txuart.inc: -------------------------------------------------------------------------------- 1 | // HAABBB G@@AAA 2 | // 3 | // Transmit Only UART implementation 4 | // 5 | // RAM[Z] := RS2_0; 6 | // stupid way to exclude CPI 7 | // WREG := Z.hi 8 | // WREG := WREG-$C0 9 | // if not FLAGS.1 then 10 | if not Zhi.7 then not_uart 11 | if Zhi.5 then not_uart 12 | 13 | temp := 10; // number of bits 14 | UART_TX = ZERO; // Start bit 15 | repeat 16 | wreg := UART_BAUDCONST; 17 | repeat 18 | ADD wreg,FF 19 | until FLAGS.1 20 | // until --wreg; // Bit delay 115200 50MHz 21 | UART_TX = RS2_0; // transmit bit 22 | ROR RS2_0; 23 | OR RS2_0, $80 // insert STOP bit 24 | ADD temp,FF 25 | until FLAGS.1 26 | // until --temp; 27 | Goto MainLoop 28 | // end; 29 | not_uart: 30 | 31 | // 32 | // 33 | // 34 | 35 | 36 | -------------------------------------------------------------------------------- /MF8A18/fw_up5k/txuart_out.inc: -------------------------------------------------------------------------------- 1 | temp := 10; // number of bits 2 | UART_TX = ZERO; // Start bit 3 | repeat 4 | wreg := UART_BAUDCONST; 5 | repeat 6 | ADD wreg,FF 7 | until FLAGS.1 8 | UART_TX = RS2_0; // transmit bit 9 | ROR RS2_0; 10 | OR RS2_0, $80 // insert STOP bit 11 | ADD temp,FF 12 | until FLAGS.1 13 | 14 | 15 | -------------------------------------------------------------------------------- /README.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/README.docx -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # engine-V 2 | 3 | 4 | Documentation will be updated, the contest entry was done to keep the deadline, the documenation in readme was done in the last hours and was kept to bare minimum to get things compiled and tested. 5 | 6 | 7 | 8 | 9 | Files are pushed, but readme comes just before deadline... it did come 1:30 before. 10 | 11 | https://riscv.org/2018contest/ the above weblink has become 404 and is not saved by web.archive either, bummer! 12 | 13 | see here is some info still online: 14 | https://riscv.org/riscv-news/2018/12/risc-v-softcpu-contest-winners-demonstrate-cutting-edge-risc-v-implementations-for-fpgas/ 15 | 16 | readme.pdf was pushed to this repo on 26 November at 22:29 PST ahead of contest deadline and was done so in good faith it is part of the contest entry 17 | -------------------------------------------------------------------------------- /README.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/README.pdf -------------------------------------------------------------------------------- /boards/gowin/TEC0117-LittleBee/resources_1NR9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/gowin/TEC0117-LittleBee/resources_1NR9.png -------------------------------------------------------------------------------- /boards/lattice/UPDuino2/UART_echoloop/UART_echoloop.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/UPDuino2/UART_echoloop/UART_echoloop.bin -------------------------------------------------------------------------------- /boards/lattice/UPDuino2/UART_echoloop/echoloop.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | use IEEE.numeric_std.all; 4 | 5 | entity echoloop is 6 | port( 7 | flash_ss : out std_logic; -- 16 8 | tx : out std_logic; -- 15 9 | rx : in std_logic -- 14 10 | -- 11 | ); 12 | end echoloop; 13 | 14 | architecture rtl of echoloop is 15 | 16 | begin 17 | flash_ss <= '1'; 18 | tx <= rx; 19 | end; 20 | -------------------------------------------------------------------------------- /boards/lattice/UPDuino2/UART_echoloop/user.pdc: -------------------------------------------------------------------------------- 1 | ldc_set_location -site {15} [get_ports rx] 2 | ldc_set_location -site {14} [get_ports tx] 3 | ldc_set_location -site {16} [get_ports flash_ss] 4 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/MDP_setup.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/iCE40-UltraPlus-MDP/MDP_setup.jpg -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/README.md: -------------------------------------------------------------------------------- 1 | Support for Lattice iCE40 UltraPlus Mobile Development Platform (MDP) boards 2 | http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40UltraPlusMobileDevPlatform 3 | 4 | If not otherwise noted, FPGA C (Device U3) is assumed being used. 5 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/demos/zephyr/README.md: -------------------------------------------------------------------------------- 1 | UART Settings 115200, FPGA used - C (Device U3), programming mode Flash 2 | 3 | Note: some demos may need manual reset to start, PB1 (sw6) is soft reset 4 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/demos/zephyr/mdp_zephyr_philo.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/iCE40-UltraPlus-MDP/demos/zephyr/mdp_zephyr_philo.bin -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/demos/zephyr/mdp_zephyr_synch.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/iCE40-UltraPlus-MDP/demos/zephyr/mdp_zephyr_synch.bin -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/demos/zephyr/philosopher_iCE40UP.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/iCE40-UltraPlus-MDP/demos/zephyr/philosopher_iCE40UP.png -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/engine_test_Implmnt/sbt/outputs/bitmap/MF8A18_SoC_bitmap.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/iCE40-UltraPlus-MDP/icecube2/engine_test_Implmnt/sbt/outputs/bitmap/MF8A18_SoC_bitmap.bin -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/engine_test_lse.prj: -------------------------------------------------------------------------------- 1 | #-- Lattice, Inc. 2 | #-- Project file X:\GIT\cube2\engine_test\engine_test_lse.prj 3 | 4 | #device 5 | -a SBTiCE40UP 6 | -d iCE40UP5K 7 | -t UWG30 8 | #constraint file 9 | 10 | #options 11 | -optimization_goal Area 12 | -twr_paths 3 13 | -bram_utilization 100.00 14 | -ramstyle Auto 15 | -romstyle Auto 16 | -use_carry_chain 1 17 | -carry_chain_length 0 18 | -resource_sharing 1 19 | -propagate_constants 1 20 | -remove_duplicate_regs 1 21 | -max_fanout 10000 22 | -fsm_encoding_style Auto 23 | -use_io_insertion 1 24 | -use_io_reg auto 25 | -resolve_mixed_drivers 0 26 | -RWCheckOnRam 0 27 | -fix_gated_clocks 1 28 | -top MF8A18_SoC 29 | -loop_limit 1950 30 | 31 | -ver "src/addsub8.v" 32 | -ver "src/RAM32K.v" 33 | -ver "src/mf8_alu.v" 34 | -ver "src/mf8_pcs.v" 35 | -ver "src/mf8_reg.v" 36 | -ver "src/mf8_core.v" 37 | -ver "src/MF8A18_SoC.v" 38 | -ver "src/MF8A18.v" 39 | -ver "src/ROM512K16.v" 40 | -p "X:/GIT/cube2/engine_test" 41 | 42 | #set result format/file last 43 | -output_edif engine_test_Implmnt/engine_test.edf 44 | 45 | #set log file 46 | -logfile "engine_test_Implmnt/engine_test_lse.log" 47 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/engine_test_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Build Date: Sep 11 2017 17:40:01 4 | ProjectName=engine_test 5 | Vendor=SiliconBlue 6 | Synthesis=lse 7 | ProjectVFiles=src/addsub8.v=work,src/RAM32K.v=work,src/mf8_alu.v=work,src/mf8_pcs.v=work,src/mf8_reg.v=work,src/mf8_core.v=work,src/MF8A18_SoC.v,src/MF8A18.v,src/ROM512K16.v 8 | ProjectCFiles= 9 | CurImplementation=engine_test_Implmnt 10 | Implementations=engine_test_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [engine_test_Implmnt] 15 | DeviceFamily=iCE40UP 16 | Device=5K 17 | DevicePackage=UWG30 18 | DevicePower= 19 | NetlistFile=engine_test_Implmnt/engine_test.edf 20 | AdditionalEDIFFile= 21 | IPEDIFFile= 22 | DesignLib=engine_test_Implmnt/sbt/netlist/oadb-MF8A18_SoC 23 | DesignView=_rt 24 | DesignCell=MF8A18_SoC 25 | SynthesisSDCFile=engine_test_Implmnt/engine_test.scf 26 | UserPinConstraintFile= 27 | UserSDCFile=src/clk.sdc 28 | PhysicalConstraintFile=src/io.pcf 29 | BackendImplPathName= 30 | Devicevoltage=1.14 31 | DevicevoltagePerformance=+/-5%(datasheet default) 32 | DeviceTemperature=85 33 | TimingAnalysisBasedOn=Worst 34 | OperationRange=Commercial 35 | TypicalCustomTemperature=25 36 | WorstCustomTemperature=85 37 | BestCustomTemperature=0 38 | IOBankVoltages=topBank,2.5 bottomBank,2.5 39 | derValue=1.32445 40 | TimingPathNumberStick=0 41 | 42 | [lse options] 43 | CarryChain=True 44 | CarryChainLength=0 45 | CommandLineOptions= 46 | EBRUtilization=100.00 47 | FSMEncodingStyle=Auto 48 | FixGatedClocks=True 49 | I/OInsertion=True 50 | IntermediateFileDump=False 51 | LoopLimit=1950 52 | MaximalFanout=10000 53 | MemoryInitialValueFileSearchPath= 54 | NumberOfCriticalPaths=3 55 | OptimizationGoal=Area 56 | PropagateConstants=True 57 | RAMStyle=Auto 58 | ROMStyle=Auto 59 | RWCheckOnRam=False 60 | RemoveDuplicateRegisters=True 61 | ResolvedMixedDrivers=False 62 | ResourceSharing=True 63 | TargetFrequency= 64 | TopLevelUnit=MF8A18_SoC 65 | UseIORegister=Auto 66 | VHDL2008=False 67 | VerilogIncludeSearchPath= 68 | 69 | [tool options] 70 | PlacerEffortLevel=std 71 | PlacerAutoLutCascade=yes 72 | PlacerAutoRamCascade=yes 73 | PlacerPowerDriven=no 74 | PlacerAreaDriven=no 75 | RouteWithTimingDriven=yes 76 | RouteWithPinPermutation=yes 77 | BitmapSPIFlashMode=yes 78 | BitmapRAM4KInit=yes 79 | BitmapInitRamBank=1111 80 | BitmapOscillatorFR=low 81 | BitmapEnableWarmBoot=yes 82 | BitmapDisableHeader=no 83 | BitmapSetSecurity=no 84 | BitmapSetNoUsedIONoPullup=no 85 | FloorPlannerShowFanInNets=yes 86 | FloorPlannerShowFanOutNets=yes 87 | HookTo3rdPartyTextEditor=no 88 | 89 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/engine_test_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file X:\GIT\cube2\engine_test\engine_test_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "src/addsub8.v" 6 | add_file -verilog -lib work "src/RAM32K.v" 7 | add_file -verilog -lib work "src/mf8_alu.v" 8 | add_file -verilog -lib work "src/mf8_pcs.v" 9 | add_file -verilog -lib work "src/mf8_reg.v" 10 | add_file -verilog -lib work "src/mf8_core.v" 11 | add_file -verilog -lib work "src/MF8A18_SoC.v" 12 | add_file -verilog -lib work "src/MF8A18.v" 13 | add_file -verilog -lib work "src/ROM512K16.v" 14 | #implementation: "engine_test_Implmnt" 15 | impl -add engine_test_Implmnt -type fpga 16 | 17 | #implementation attributes 18 | set_option -vlog_std v2001 19 | set_option -project_relative_includes 1 20 | 21 | #device options 22 | set_option -technology SBTiCE40UP 23 | set_option -part iCE40UP5K 24 | set_option -package UWG30 25 | set_option -speed_grade 26 | set_option -part_companion "" 27 | 28 | #compilation/mapping options 29 | 30 | # mapper_options 31 | set_option -frequency auto 32 | set_option -write_verilog 0 33 | set_option -write_vhdl 0 34 | 35 | # Silicon Blue iCE40UP 36 | set_option -maxfan 10000 37 | set_option -disable_io_insertion 0 38 | set_option -pipe 1 39 | set_option -retiming 0 40 | set_option -update_models_cp 0 41 | set_option -fixgatedclocks 2 42 | set_option -fixgeneratedclocks 0 43 | 44 | # NFilter 45 | set_option -popfeed 0 46 | set_option -constprop 0 47 | set_option -createhierarchy 0 48 | 49 | # sequential_optimization_options 50 | set_option -symbolic_fsm_compiler 1 51 | 52 | # Compiler Options 53 | set_option -compiler_compatible 0 54 | set_option -resource_sharing 1 55 | 56 | #automatic place and route (vendor) options 57 | set_option -write_apr_constraint 1 58 | 59 | #set result format/file last 60 | project -result_format "edif" 61 | project -result_file ./engine_test_Implmnt/engine_test.edf 62 | project -log_file "./engine_test_Implmnt/engine_test.srr" 63 | impl -active engine_test_Implmnt 64 | project -run synthesis -clean 65 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/pin_constraints.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/iCE40-UltraPlus-MDP/icecube2/pin_constraints.png -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/radiant_programmer.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/iCE40-UltraPlus-MDP/icecube2/radiant_programmer.png -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/resources_used.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/lattice/iCE40-UltraPlus-MDP/icecube2/resources_used.png -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/src/MF8A18.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module MF8A18 ( 7 | CLK, 8 | RSTn, 9 | rom_addr, 10 | rom_data, 11 | maddr, 12 | mwdata, 13 | ramdata, 14 | mwrite, 15 | mread, 16 | SPI_MISO, 17 | SPI_MOSI, 18 | SPI_SCK, 19 | SPI_CS, 20 | UART_TXD); 21 | 22 | 23 | input CLK; 24 | input RSTn; 25 | output [9:0] rom_addr; 26 | input [15:0] rom_data; 27 | output [15:0] maddr; 28 | output [7:0] mwdata; 29 | input [7:0] ramdata; 30 | output mwrite; 31 | output mread; 32 | input SPI_MISO; 33 | output SPI_MOSI; 34 | output SPI_SCK; 35 | output SPI_CS; 36 | output UART_TXD; 37 | 38 | 39 | // 40 | wire [9:0] rom_addr; 41 | wire [15:0] maddr; 42 | wire [7:0] mwdata; 43 | wire mwrite; 44 | wire mread; 45 | reg SPI_MOSI; 46 | reg SPI_SCK; 47 | reg SPI_CS; 48 | reg UART_TXD; 49 | reg Reset_s_n; 50 | wire Reset_s_n_i; 51 | wire IO_Rd; 52 | wire IO_Wr; 53 | wire [5:0] IO_Addr; 54 | wire [7:0] IO_WData; 55 | wire [7:0] IO_RData; 56 | 57 | wire [15:0] Z; 58 | wire [7:0] ram_datain; 59 | wire ram_write; 60 | 61 | wire [15:0] maddr_i; 62 | wire [15:0] maddr_s; 63 | wire mread_i; 64 | wire mwrite_i; 65 | 66 | assign maddr = maddr_i; 67 | assign mread = mread_i; 68 | assign mwrite = mwrite_i; 69 | 70 | always @(posedge CLK) 71 | begin : process_1 72 | Reset_s_n <= RSTn; 73 | end 74 | 75 | always @(posedge CLK or negedge Reset_s_n) 76 | begin : process_2 77 | if (Reset_s_n === 1'b 0) 78 | begin 79 | UART_TXD <= 1'b 1; 80 | SPI_CS <= 1'b 1; 81 | SPI_SCK <= 1'b 1; 82 | SPI_MOSI <= 1'b 1; 83 | end else 84 | begin 85 | if (IO_Wr === 1'b 1) 86 | begin 87 | if (IO_Addr[4:3] === 2'b 00) begin UART_TXD <= IO_WData[0]; end // 00 xxxxx 0x20 88 | if (IO_Addr[4:3] === 2'b 01) begin SPI_CS <= IO_WData[7]; end // 01 xxxx 0x10 89 | if (IO_Addr[4:3] === 2'b 10) begin SPI_SCK <= IO_WData[0]; end // 11 xxxx 0x20 90 | if (IO_Addr[4:3] === 2'b 11) begin SPI_MOSI <= IO_WData[7]; end // 10 xxxx 0x30 91 | end 92 | end 93 | end 94 | 95 | assign mwdata = IO_WData; 96 | 97 | mf8_core core ( 98 | .Clk (CLK), 99 | .Reset_n (Reset_s_n), 100 | .ROM_Addr (rom_addr[9:0]), 101 | .ROM_Data (rom_data), 102 | .ZZ (maddr_i), 103 | .ram_datain (ramdata), 104 | .ram_write (mwrite_i), 105 | .ram_read (mread_i), 106 | .IO_Rd (IO_Rd), 107 | .IO_Wr (IO_Wr), 108 | .IO_Addr (IO_Addr), 109 | .IO_RData (IO_RData), 110 | .IO_WData (IO_WData) 111 | ); 112 | 113 | assign IO_RData = {7'b 0000000, SPI_MISO}; 114 | 115 | endmodule // 116 | 117 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/src/MF8A18_SoC.v: -------------------------------------------------------------------------------- 1 | 2 | module MF8A18_SoC 3 | (CLK, 4 | RSTn, 5 | FLASH_CS, 6 | FLASH_MISO, 7 | FLASH_MOSI, 8 | FLASH_SCK, 9 | UART_TXD 10 | ); 11 | 12 | 13 | input CLK; 14 | input RSTn; 15 | 16 | output FLASH_CS; 17 | input FLASH_MISO; 18 | output FLASH_MOSI; 19 | output FLASH_SCK; 20 | output UART_TXD; 21 | 22 | wire Clk_0_1; 23 | wire [7:0]RAM32K_0_dout; 24 | wire RSTn_0_1; 25 | wire SPI_MISO_0_1; 26 | wire [15:0]rom1200_0_D; 27 | wire top_0_DEBUG_LED; 28 | wire top_0_LED; 29 | wire top_0_SPI_CS; 30 | wire top_0_SPI_MOSI; 31 | wire top_0_SPI_SCK; 32 | wire top_0_UART_TXD; 33 | wire [15:0]top_0_maddr; 34 | wire [7:0]top_0_mwdata; 35 | wire top_0_mwrite; 36 | wire [9:0]top_0_rom_addr; 37 | 38 | assign Clk_0_1 = CLK; 39 | assign RSTn_0_1 = RSTn; 40 | assign FLASH_CS = top_0_SPI_CS; 41 | assign SPI_MISO_0_1 = FLASH_MISO; 42 | assign FLASH_MOSI = top_0_SPI_MOSI; 43 | assign FLASH_SCK = top_0_SPI_SCK; 44 | 45 | assign UART_TXD = top_0_UART_TXD; 46 | 47 | 48 | RAM32K RAM32K_0 ( 49 | .addr (top_0_maddr[14:0]), 50 | .clk (Clk_0_1), 51 | .din (top_0_mwdata), 52 | .dout (RAM32K_0_dout), 53 | .we (top_0_mwrite)); 54 | 55 | ROM512K16 mc_rom (.addr(top_0_rom_addr[8:0]), .clk(Clk_0_1), .dout(rom1200_0_D)); 56 | 57 | 58 | MF8A18 top_0 ( 59 | .CLK (Clk_0_1), 60 | .RSTn (RSTn_0_1), 61 | .SPI_CS (top_0_SPI_CS), 62 | .SPI_MISO (SPI_MISO_0_1), 63 | .SPI_MOSI (top_0_SPI_MOSI), 64 | .SPI_SCK (top_0_SPI_SCK), 65 | .UART_TXD (top_0_UART_TXD), 66 | .maddr (top_0_maddr), 67 | .mwdata (top_0_mwdata), 68 | .mwrite (top_0_mwrite), 69 | .ramdata (RAM32K_0_dout), 70 | .rom_addr (top_0_rom_addr), 71 | .rom_data (rom1200_0_D) 72 | ); 73 | endmodule 74 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/src/RAM32K.v: -------------------------------------------------------------------------------- 1 | 2 | module RAM32K ( 3 | clk, 4 | addr, 5 | din, 6 | dout, 7 | we 8 | ); 9 | 10 | input clk; 11 | input we; 12 | input [14:0] addr; 13 | input [7:0] din; 14 | output [7:0] dout; 15 | 16 | wire [13:0] spram_addr; 17 | wire [15:0] spram_wr_data; 18 | wire [15:0] spram_rd_data; 19 | wire [3:0] spram_mask; 20 | 21 | assign spram_wr_data[15:8] = din; 22 | assign spram_wr_data [7:0] = din; 23 | // use word address 24 | assign spram_addr = addr[14:1]; 25 | // assign write masks 26 | assign spram_mask[0] = ~addr[0]; 27 | assign spram_mask[1] = ~addr[0]; 28 | assign spram_mask[2] = addr[0]; 29 | assign spram_mask[3] = addr[0]; 30 | 31 | // latch lower address 32 | reg addr0_s; 33 | always @ (posedge clk) begin 34 | addr0_s <= addr[0]; 35 | end 36 | // return correct byte depending on latched address ! 37 | assign dout = addr0_s ? spram_rd_data[15:8] : spram_rd_data[7:0]; 38 | 39 | // iceCube2.. 40 | 41 | SB_SPRAM256KA inst_SPRAM256KA( 42 | .ADDRESS (spram_addr ), 43 | .DATAIN (spram_wr_data ), 44 | .MASKWREN (spram_mask ), 45 | .WREN (we ), 46 | .CHIPSELECT (1'b1 ), 47 | .CLOCK (clk ), 48 | .STANDBY (1'b0 ), 49 | .SLEEP (1'b0 ), 50 | .POWEROFF (1'b1 ), 51 | .DATAOUT (spram_rd_data ) 52 | ); 53 | 54 | 55 | // Radiant.. 56 | /* 57 | SP256K inst_SPRAM256KA( 58 | .AD (spram_addr ), 59 | .DI (spram_wr_data ), 60 | .MASKWE (spram_mask ), 61 | .WE (we ), 62 | .CS (1'b1 ), 63 | .CK (clk ), 64 | .STDBY (1'b0 ), 65 | .SLEEP (1'b0 ), 66 | .PWROFF_N (1'b1 ), 67 | .DO (spram_rd_data ) 68 | ); 69 | */ 70 | endmodule -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/src/addsub8.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | -- File Type: Verilog HDL 4 | -- Tool Version: VHDL2verilog 20.32 5 | -- Input file was: addsub8.vhd 6 | -- Command line was: C:\SynaptiCAD\bin\win32\vhdl2verilog.exe addsub8.vhd addsub8.v 7 | -- Date Created: Wed Nov 07 20:48:33 2018 8 | 9 | *******************************************************************************/ 10 | 11 | `define false 1'b 0 12 | `define FALSE 1'b 0 13 | `define true 1'b 1 14 | `define TRUE 1'b 1 15 | 16 | `timescale 1 ns / 1 ns // timescale for following modules 17 | 18 | 19 | module addsub8 ( 20 | a, 21 | b, 22 | q, 23 | sub, 24 | cin, 25 | cout); 26 | 27 | 28 | input [7:0] a; 29 | input [7:0] b; 30 | output [7:0] q; 31 | input sub; 32 | input cin; 33 | output cout; 34 | 35 | wire [7:0] q; 36 | wire cout; 37 | wire [8:0] A_i; 38 | wire [8:0] B_i; 39 | wire [8:0] Full_Carry; 40 | wire [8:0] Res_i; 41 | 42 | assign B_i[8] = 1'b 0; 43 | assign B_i[7:0] = sub === 1'b 1 ? ~b : 44 | b; 45 | assign A_i[8] = 1'b 0; 46 | assign A_i[7:0] = a; 47 | assign Full_Carry[8:1] = 8'b 00000000; 48 | assign Full_Carry[0] = cin; 49 | assign Res_i = A_i + B_i + Full_Carry; 50 | assign cout = Res_i[8]; 51 | assign q = Res_i[7:0]; 52 | 53 | endmodule // module addsub8 54 | 55 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/src/clk.sdc: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | 3 | # iCEcube SDC 4 | 5 | # Version: 2017.08.27940 6 | 7 | # File Generated: Nov 25 2018 15:50:28 8 | 9 | # ############################################################################## 10 | 11 | ####---- CreateClock list ----1 12 | create_clock -period 37.00 -name {CLK} [get_ports {CLK}] 13 | 14 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/src/io.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | 3 | # iCEcube PCF 4 | 5 | # Version: 2017.08.27940 6 | 7 | # File Generated: Nov 25 2018 15:57:24 8 | 9 | # Family & Device: iCE40UP5K 10 | 11 | # Package: UWG30 12 | 13 | # ############################################################################## 14 | 15 | ###MergeFF List 1 16 | set_io_ff RSTn -in ON 17 | 18 | ###IOSet List 7 19 | set_io FLASH_MOSI F1 -io_std SB_LVCMOS -pullup no 20 | set_io CLK B3 -io_std SB_LVCMOS -pullup no 21 | set_io FLASH_CS C1 22 | set_io FLASH_MISO E1 -io_std SB_LVCMOS -pullup no 23 | set_io FLASH_SCK D1 -io_std SB_LVCMOS -pullup no 24 | set_io RSTn C3 -io_std SB_LVCMOS -pullup yes -pullup_resistor 3P3K 25 | set_io UART_TXD A1 26 | 27 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/src/mf8_pcs.v: -------------------------------------------------------------------------------- 1 | module mf8_pcs(Clk, Reset_n, Offs_In, Pause, RJmp, NPC, PC); 2 | input Clk; 3 | input Reset_n; 4 | input [11:0] Offs_In; 5 | input Pause; 6 | input RJmp; 7 | output [11:0] NPC; 8 | output [11:0] PC; 9 | 10 | reg [11:0] PC_i; 11 | wire [11:0] NPC_i; 12 | wire [11:0] inc_or_nop; 13 | wire [11:0] real_offset; 14 | 15 | 16 | assign NPC = NPC_i; 17 | assign PC = PC_i; 18 | 19 | assign inc_or_nop = {11'b00000000000, ( ~Pause)}; 20 | assign real_offset = (RJmp == 1'b0) ? (inc_or_nop) 21 | : (Offs_In); 22 | assign NPC_i = PC_i + real_offset; 23 | 24 | always @(posedge Clk or negedge Reset_n) begin 25 | if (Reset_n == 1'b0) begin 26 | PC_i <= 12'b000000000000; 27 | end else begin 28 | PC_i <= NPC_i; 29 | end 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /boards/lattice/iCE40-UltraPlus-MDP/icecube2/src/mf8_reg.v: -------------------------------------------------------------------------------- 1 | module mf8_reg(Clk, Reset_n, Wr, Rd_Addr, Rr_Addr, Data_In, Rd_Data, Rr_Data, Z); 2 | input Clk; 3 | input Reset_n; 4 | input Wr; 5 | input [4:0] Rd_Addr; 6 | input [4:0] Rr_Addr; 7 | input [7:0] Data_In; 8 | output [7:0] Rd_Data; 9 | reg [7:0] Rd_Data; // appended automatically by vhdl2verilog. 10 | output [7:0] Rr_Data; 11 | reg [7:0] Rr_Data; // appended automatically by vhdl2verilog. 12 | output [15:0] Z; 13 | reg [15:0] Z; // appended automatically by vhdl2verilog. 14 | 15 | 16 | reg [7:0] RegD [31:0]; 17 | reg [7:0] RegR [31:0]; 18 | reg [4:0] Rd_Addr_r; 19 | 20 | always @(posedge Clk) begin 21 | Rd_Addr_r <= Rd_Addr; 22 | Rd_Data <= RegD[Rd_Addr]; 23 | Rr_Data <= RegR[Rr_Addr]; 24 | if (Wr == 1'b1) begin 25 | RegD[Rd_Addr_r] <= Data_In; 26 | RegR[Rd_Addr_r] <= Data_In; 27 | if (Rd_Addr_r == Rd_Addr) begin 28 | Rd_Data <= Data_In; 29 | end 30 | if (Rd_Addr_r == Rr_Addr) begin 31 | Rr_Data <= Data_In; 32 | end 33 | if (Rd_Addr_r == 5'b11110) begin 34 | Z[7:0] <= Data_In; 35 | end 36 | if (Rd_Addr_r == 5'b11111) begin 37 | Z[15:8] <= Data_In; 38 | end 39 | end 40 | end 41 | endmodule 42 | -------------------------------------------------------------------------------- /boards/microchip/CreativeBoard-SF2/Libero/Creative_SF2.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/microchip/CreativeBoard-SF2/Libero/Creative_SF2.zip -------------------------------------------------------------------------------- /boards/microchip/CreativeBoard-SF2/Libero/eNVM/mf8a18.hex: -------------------------------------------------------------------------------- 1 | :10000000D0E00D2EDFEF1D2EA02CB02C27C0D4E0A9 2 | :1000100001C0D6E0CA2CDB2CAE2EBF2E14C040E0AF 3 | :1000200050E060E070E0E12FE295E07F07FDE860DE 4 | :10003000EE2329F0F1EF4083518362837383DA2D3D 5 | :10004000D1FF09C0D0E0F2EFE0E3A082B182E0E1AD 6 | :10005000C082D182CFC0D4E0AD0EB01CCA2CDB2C44 7 | :10006000EA2DFB2D008111812281338102FD72C1B5 8 | :10007000E22FE295E07F17FDE860F1EFC080D180CC 9 | :10008000E280F38005FD97C07FEF6FEF422F42952E 10 | :100090004F703295532F506F307F432B53FD03C069 11 | :1000A0005F7060E070E004FF54C016FD09C015FDEC 12 | :1000B00043C014FD1BC04C0D5D1D6E1D7F1DB3CFD5 13 | :1000C00015FD07C014FD26C04C255D256E257F2536 14 | :1000D000AACF14FD05C04C295D296E297F29A3CF25 15 | :1000E0004C215D216E217F219ECF482F4F7131F031 16 | :1000F000CC0CDD1CEE1CFF1C410DD1F74C2D5D2DF1 17 | :100100006E2D7F2D90CF15FDE4CF14FFDDCF482F4E 18 | :10011000532F52954F7191F352FF07C0F594E79416 19 | :10012000D794C794410DD1F7E9CFF694E794D794CB 20 | :10013000C794410DD1F7E2CF14FD03C0D0E8FD0E06 21 | :100140007D0FC41AD50AE60AF70A08F068CF41E025 22 | :1001500067CF06FF0FC0C40ED51ED4E0AD0EB01C95 23 | :100160004A2D5B2DDEEFCD22AC2CBD2CD4E0AD1A98 24 | :10017000B00857CFEC2DFD2DE40FF51F408114FD85 25 | :1001800014C015FD0AC016FD4BCF47FF49CF5FEFE6 26 | :1001900057FF47CF6FEF7FEF46CFE0FD38CFE1FD50 27 | :1001A00036CF5181628173813ECFE0FD30CF5181E6 28 | :1001B00016FFEECF36CF06FF4EC004FD05C003FD8F 29 | :1001C0004AC002FF48C060CFF2EFE0E1C0E0D12FAB 30 | :1001D000D077DD23A9F434FF03C035FD0EC0C0E89D 31 | :1001E000A082B182D3E024FFD860CC2309F0D7E00D 32 | :1001F000E3E2C083E0E2D083E0E5A080B1802ECFCF 33 | :10020000E22FE07F37FF01C0E460408151816281CD 34 | :10021000738116FF09C0C22EDFE0CD22CC0C17FD82 35 | :10022000C118DD24EE24FF2415FF10C014FD05C005 36 | :10023000C42AD52AE62AF72A09C0DFEFCD26DD2613 37 | :10024000ED26FD26C422D522E622F722F382E282A1 38 | :10025000D182C082E8CE06FD12C004FD10C0412F3D 39 | :10026000440F4E7107FD4160D32FD295D07E4D2BA8 40 | :10027000532F5295577037FD586FC40ED51EE22F7D 41 | :10028000E69530FDE068E87FF1EF80819181A28101 42 | :10029000B38106FF2AC015FD03C0D0E8FD26BD27A7 43 | :1002A000C81AD90AEA0AFB0A16FF16C014FD02C0D2 44 | :1002B00010F0C5CEB8F0110F1E713295D32FD07E3D 45 | :1002C0001D2B3F7033FD3061377107FD386034FD01 46 | :1002D000306EA10EB31EC2CECD28CE28CF2814FF7B 47 | :1002E00002C049F7ACCE39F3AACE04FF11C0482FA3 48 | :1002F000592F6A2F7B2F16FD06CF15FD1DCF14FD3C 49 | :10030000F4CE36FFD8CEC81AD90AEA0AFB0AF6CECE 50 | :10031000EC2DFD2D14FD13C015FD11C08083F7FFDA 51 | :100320000DC0F5FD0BC0CAE000B8DFE8D10DF1F754 52 | :1003300080B987958068C10DC1F781CE80CEE0FD80 53 | :1003400068CE14FD04C0E1FD64CEB383A283808334 54 | :10035000918375CE04FD1DC005FF71CE03FF88CECD 55 | :100360003295377F24FD386022952E70C32ED0EF52 56 | :10037000CD22C22AD12EDD223F70D32AD4E0AD0E89 57 | :10038000B01C4A2D5B2DAC0CBD1CD8E0AD1AB008DA 58 | :1003900048CE732F622F512F507F40E005FD43CE92 59 | :0803A0004A2D5B0D40CE4BCE4F 60 | :00000001FF 61 | -------------------------------------------------------------------------------- /boards/microchip/CreativeBoard-SF2/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /boards/microchip/CreativeBoard-SF2/SoftConsole/assisted_boot.7z: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/microchip/CreativeBoard-SF2/SoftConsole/assisted_boot.7z -------------------------------------------------------------------------------- /boards/microchip/CreativeBoard-SF2/bitstreams/bitstreams.7z: -------------------------------------------------------------------------------- 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first MF8A18 and engine-V was initially developed and tested, SPI Flash boot for Lattice was first working and debugged with S7-Mini, then ported to Lattice MDP. 3 | 4 | NOTE: Board support files for S7-mini will be updated and hopefully pushed to Xilinx board part file repo. 5 | 6 | Provided here is minimal board file, it includes only SPI flash and system clock configuration only. 7 | 8 | https://github.com/blackmesalabs/s7_mini_fpga 9 | 10 | Help needed: 11 | 12 | Original schematic had FTDI_0 as net names, they go to FTDI UART dongle that we do not have for testing (we use fly wires to TE0790 always!) so we can not verify with real hardware that we have the uart mapped correctly for this 6 pin cable. 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /boards/xilinx/bml-S7-Mini/board_files/TE0890_25_1C/1.0/part0_pins.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /boards/xilinx/bml-S7-Mini/board_files/TE0890_25_1C/1.0/preset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /boards/xilinx/bml-S7-Mini/board_files/TE0890_25_1C/1.0/te0890_board.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/xilinx/bml-S7-Mini/board_files/TE0890_25_1C/1.0/te0890_board.png -------------------------------------------------------------------------------- /boards/xilinx/bml-S7-Mini/engine-V-bml-s7-mini.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/boards/xilinx/bml-S7-Mini/engine-V-bml-s7-mini.png -------------------------------------------------------------------------------- /tools/mem2v.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import fileinput 4 | 5 | print("module ROM512K16 (clk, addr, dout);") 6 | print("input clk;") 7 | print("input [8:0] addr;") 8 | print("output [15:0] dout;") 9 | 10 | print("reg [15:0] dout; ") 11 | print("reg [8:0] addr_r; ") 12 | print("") 13 | print("always @(posedge clk) begin : process_clk addr_r <= addr; end") 14 | print("") 15 | print("always @(addr_r) begin : process case (addr_r)") 16 | 17 | print("") 18 | 19 | i = 0 20 | for line in fileinput.input(): 21 | print(" ",i, ": begin dout <= 16'h %s; end" % line.strip() ) 22 | i = i + 1 23 | 24 | print(" default: begin dout <= 16'h xxxx; end") 25 | print("endcase") 26 | print("end") 27 | 28 | print("") 29 | print("endmodule") -------------------------------------------------------------------------------- /verilator/README.md: -------------------------------------------------------------------------------- 1 | Ready to run Verilator setup, scripts provided for Windows OS 2 | 3 | Preparation 4 | 5 | Some DLL and EXE files are compressed with 7zip, they should be unzipped into their current location if they are needed, mingw is needed to recompile the verilated executables, if mingw is not installed ready made executables can be used (unzip DLL's in the ./dll folder!). Verilator executable is also included. So it is full standalone package to run verilator from HDL sources. 6 | 7 | 8 | Folders 9 | 10 | * run - scripts to run Zephyr and RV32I Compliance tests for the Lattice, SPI Boot 11 | * run_mss - scripts to run Zephyr and RV32I Compliance tests for Microsemi, M3 Assisted boot from eSRAM 12 | -------------------------------------------------------------------------------- /verilator/bin/bin.7z: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/bin/bin.7z -------------------------------------------------------------------------------- /verilator/bitstream/mf8a18_rv32i.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/bitstream/mf8a18_rv32i.bin -------------------------------------------------------------------------------- /verilator/build/do_exe.bat: -------------------------------------------------------------------------------- 1 | del a.exe 2 | del *.o 3 | 4 | ..\bin\verilator.exe --exe -Wno-fatal --compiler msvc --cc --top-module tb -I../hdl ../hdl/tb.v ../hdl/tb.cc 5 | 6 | set VERI=..\bin 7 | set INC=%VERI%\include 8 | gcc -I .\obj_dir -I %INC% %INC%\verilated.cpp .\obj_dir\Vtb.cpp .\obj_dir\Vtb__Syms.cpp ../hdl/tb.cc -lstdc++ 9 | 10 | del *.o 11 | 12 | copy a.exe engine-v.exe 13 | del a.exe -------------------------------------------------------------------------------- /verilator/build/engine-v.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/build/engine-v.exe -------------------------------------------------------------------------------- /verilator/build_mss/do_exe.bat: -------------------------------------------------------------------------------- 1 | del a.exe 2 | del *.o 3 | 4 | ..\bin\verilator.exe --exe -Wno-fatal --compiler msvc --cc --top-module tb -I../hdl_mss ../hdl_mss/tb.v ../hdl_mss/tb.cc 5 | 6 | set VERI=..\bin 7 | set INC=%VERI%\include 8 | gcc -I .\obj_dir -I %INC% %INC%\verilated.cpp .\obj_dir\Vtb.cpp .\obj_dir\Vtb__Syms.cpp ../hdl_mss/tb.cc -lstdc++ 9 | 10 | del *.o 11 | 12 | copy a.exe engine-v.exe 13 | del a.exe 14 | -------------------------------------------------------------------------------- /verilator/build_mss/engine-v.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/build_mss/engine-v.exe -------------------------------------------------------------------------------- /verilator/dll/dll.7z: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/dll/dll.7z -------------------------------------------------------------------------------- /verilator/hdl/27MHz/baudgen.v: -------------------------------------------------------------------------------- 1 | // from fpga4fun 2 | 3 | module baudgen #( 4 | parameter ClkFrequency = 27000000, // 27MHz 5 | parameter Baud = 115200*4, 6 | parameter BaudGeneratorAccWidth = 16, 7 | parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4) 8 | ) ( 9 | clk, 10 | tick 11 | ); 12 | 13 | input clk; 14 | output tick; 15 | 16 | reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc; 17 | always @(posedge clk) 18 | BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc; 19 | 20 | wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]; 21 | 22 | assign tick = BaudTick; 23 | 24 | endmodule; -------------------------------------------------------------------------------- /verilator/hdl/50MHz/baudgen.v: -------------------------------------------------------------------------------- 1 | // from fpga4fun 2 | 3 | module baudgen #( 4 | parameter ClkFrequency = 50000000, // 50MHz 5 | parameter Baud = 115200*4, 6 | parameter BaudGeneratorAccWidth = 16, 7 | parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4) 8 | ) ( 9 | clk, 10 | tick 11 | ); 12 | 13 | input clk; 14 | output tick; 15 | 16 | reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc; 17 | always @(posedge clk) 18 | BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc; 19 | 20 | wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]; 21 | 22 | assign tick = BaudTick; 23 | 24 | endmodule; -------------------------------------------------------------------------------- /verilator/hdl/MF8A18.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module MF8A18 ( 7 | CLK, 8 | RSTn, 9 | rom_addr, 10 | rom_data, 11 | maddr, 12 | mwdata, 13 | ramdata, 14 | mwrite, 15 | mread, 16 | SPI_MISO, 17 | SPI_MOSI, 18 | SPI_SCK, 19 | SPI_CS, 20 | UART_TXD); 21 | 22 | 23 | input CLK; 24 | input RSTn; 25 | output [9:0] rom_addr; 26 | input [15:0] rom_data; 27 | output [15:0] maddr; 28 | output [7:0] mwdata; 29 | input [7:0] ramdata; 30 | output mwrite; 31 | output mread; 32 | input SPI_MISO; 33 | output SPI_MOSI; 34 | output SPI_SCK; 35 | output SPI_CS; 36 | output UART_TXD; 37 | 38 | 39 | // 40 | wire [9:0] rom_addr; 41 | wire [15:0] maddr; 42 | wire [7:0] mwdata; 43 | wire mwrite; 44 | wire mread; 45 | reg SPI_MOSI; 46 | reg SPI_SCK; 47 | reg SPI_CS; 48 | reg UART_TXD; 49 | reg Reset_s_n; 50 | wire Reset_s_n_i; 51 | wire IO_Rd; 52 | wire IO_Wr; 53 | wire [5:0] IO_Addr; 54 | wire [7:0] IO_WData; 55 | wire [7:0] IO_RData; 56 | 57 | wire [15:0] Z; 58 | wire [7:0] ram_datain; 59 | wire ram_write; 60 | 61 | wire [15:0] maddr_i; 62 | wire [15:0] maddr_s; 63 | wire mread_i; 64 | wire mwrite_i; 65 | 66 | assign maddr = maddr_i; 67 | assign mread = mread_i; 68 | assign mwrite = mwrite_i; 69 | 70 | always @(posedge CLK) 71 | begin : process_1 72 | Reset_s_n <= RSTn; 73 | end 74 | 75 | always @(posedge CLK or negedge Reset_s_n) 76 | begin : process_2 77 | if (Reset_s_n === 1'b 0) 78 | begin 79 | UART_TXD <= 1'b 1; 80 | SPI_CS <= 1'b 1; 81 | SPI_SCK <= 1'b 1; 82 | SPI_MOSI <= 1'b 1; 83 | end else 84 | begin 85 | if (IO_Wr === 1'b 1) 86 | begin 87 | if (IO_Addr[4:3] === 2'b 00) begin UART_TXD <= IO_WData[0]; end // 00 xxxxx 0x20 88 | if (IO_Addr[4:3] === 2'b 01) begin SPI_CS <= IO_WData[7]; end // 01 xxxx 0x10 89 | if (IO_Addr[4:3] === 2'b 10) begin SPI_SCK <= IO_WData[0]; end // 11 xxxx 0x20 90 | if (IO_Addr[4:3] === 2'b 11) begin SPI_MOSI <= IO_WData[7]; end // 10 xxxx 0x30 91 | end 92 | end 93 | end 94 | 95 | assign mwdata = IO_WData; 96 | 97 | mf8_core core ( 98 | .Clk (CLK), 99 | .Reset_n (Reset_s_n), 100 | .ROM_Addr (rom_addr[9:0]), 101 | .ROM_Data (rom_data), 102 | .ZZ (maddr_i), 103 | .ram_datain (ramdata), 104 | .ram_write (mwrite_i), 105 | .ram_read (mread_i), 106 | .IO_Rd (IO_Rd), 107 | .IO_Wr (IO_Wr), 108 | .IO_Addr (IO_Addr), 109 | .IO_RData (IO_RData), 110 | .IO_WData (IO_WData) 111 | ); 112 | 113 | assign IO_RData = {7'b 0000000, SPI_MISO}; 114 | 115 | endmodule // 116 | 117 | -------------------------------------------------------------------------------- /verilator/hdl/MF8A18_SoC.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | 7 | module MF8A18_SoC ( 8 | clk, 9 | resetn, 10 | FLASH_SCK, 11 | FLASH_CS, 12 | FLASH_MISO, 13 | FLASH_MOSI, 14 | UART_TXD 15 | ); 16 | 17 | output FLASH_SCK; 18 | output FLASH_CS; 19 | input FLASH_MISO; 20 | output FLASH_MOSI; 21 | 22 | input clk; 23 | input resetn; 24 | output UART_TXD; 25 | 26 | wire [9:0] rom_addr; 27 | wire [15:0] rom_data; 28 | 29 | wire [15:0] maddr; 30 | wire [7:0] mwdata; 31 | wire [7:0] mrdata; 32 | wire mwrite; 33 | 34 | MF8A18 cpu ( 35 | .CLK (clk), 36 | .RSTn (resetn), 37 | .SPI_CS (FLASH_CS), 38 | .SPI_MISO (FLASH_MISO), 39 | .SPI_MOSI (FLASH_MOSI), 40 | .SPI_SCK (FLASH_SCK), 41 | .UART_TXD (UART_TXD), 42 | .maddr (maddr), 43 | .mread (), 44 | .mwdata (mwdata), 45 | .mwrite (mwrite), 46 | .ramdata (mrdata), 47 | .rom_addr (rom_addr), 48 | .rom_data (rom_data) 49 | ); 50 | 51 | ROM1K16 rom ( 52 | .addr (rom_addr), 53 | .clk (clk), 54 | .dout (rom_data) 55 | ); 56 | 57 | RAM32K ram ( 58 | .addr (maddr[14:0]), 59 | .clk (clk), 60 | .din (mwdata), 61 | .dout (mrdata), 62 | .we (mwrite) 63 | ); 64 | 65 | endmodule -------------------------------------------------------------------------------- /verilator/hdl/RAM32K.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module RAM32K ( 7 | clk, 8 | addr, 9 | din, 10 | dout, 11 | we 12 | ); 13 | 14 | input clk; 15 | input we; 16 | input [14:0] addr; 17 | input [7:0] din; 18 | output [7:0] dout; 19 | 20 | 21 | //wire [13:0] spram_addr; 22 | //wire [15:0] spram_wr_data; 23 | //wire [15:0] spram_rd_data; 24 | //wire [3:0] spram_mask; 25 | 26 | //assign spram_wr_data[15:8] = din; 27 | //assign spram_wr_data [7:0] = din; 28 | // use word address 29 | //assign spram_addr = addr[14:1]; 30 | // assign write masks 31 | //assign spram_mask[0] = ~addr[0]; 32 | //assign spram_mask[1] = ~addr[0]; 33 | //assign spram_mask[2] = addr[0]; 34 | //assign spram_mask[3] = addr[0]; 35 | 36 | // latch lower address 37 | //reg addr0_s; 38 | //always @ (posedge clk) begin 39 | // addr0_s <= addr[0]; 40 | //end 41 | // return correct byte depending on latched address ! 42 | //assign dout = addr0_s ? spram_rd_data[15:8] : spram_rd_data[7:0]; 43 | 44 | // iceCube2.. 45 | /* 46 | SB_SPRAM256KA inst_SPRAM256KA( 47 | .ADDRESS (spram_addr ), 48 | .DATAIN (spram_wr_data ), 49 | .MASKWREN (spram_mask ), 50 | .WREN (we ), 51 | .CHIPSELECT (1'b1 ), 52 | .CLOCK (clk ), 53 | .STANDBY (1'b0 ), 54 | .SLEEP (1'b0 ), 55 | .POWEROFF (1'b1 ), 56 | .DATAOUT (spram_rd_data ) 57 | ); 58 | */ 59 | 60 | // Radiant.. 61 | /* 62 | SP256K inst_SPRAM256KA( 63 | .AD (spram_addr ), 64 | .DI (spram_wr_data ), 65 | .MASKWE (spram_mask ), 66 | .WE (we ), 67 | .CS (1'b1 ), 68 | .CK (clk ), 69 | .STDBY (1'b0 ), 70 | .SLEEP (1'b0 ), 71 | .PWROFF_N (1'b1 ), 72 | .DO (spram_rd_data ) 73 | ); 74 | */ 75 | 76 | /* 77 | * Generic and simulator friendly memory 78 | */ 79 | 80 | reg [7:0] memory [0:32*1024-1]; 81 | reg [7:0] memory_r; 82 | initial $readmemh("riscv.mem", memory); 83 | 84 | assign dout = memory_r; 85 | 86 | always @(posedge clk) begin 87 | if (we) memory[addr] <= din; 88 | memory_r <= memory[addr]; 89 | end 90 | 91 | always @(posedge clk) begin 92 | if (we) begin 93 | if (addr < 40) begin 94 | // $write("\n\rWR: %04X %02X ", addr, din); 95 | end 96 | end 97 | end 98 | 99 | 100 | 101 | endmodule -------------------------------------------------------------------------------- /verilator/hdl/ROM1K16.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module ROM1K16 ( 7 | clk, 8 | addr, 9 | dout 10 | ); 11 | 12 | input clk; 13 | input [9:0] addr; 14 | output [15:0] dout; 15 | 16 | /* 17 | * Generic and simulator friendly memory 18 | */ 19 | 20 | reg [15:0] memory [0:2*1024-1]; 21 | reg [15:0] memory_r; 22 | initial $readmemh("rv32i.mem", memory); 23 | 24 | assign dout = memory_r; 25 | 26 | always @(posedge clk) begin 27 | memory_r <= memory[addr]; 28 | // $write("\n\rROM: %04X", addr); 29 | end 30 | 31 | 32 | endmodule -------------------------------------------------------------------------------- /verilator/hdl/addsub8.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | 7 | module addsub8 ( 8 | a, 9 | b, 10 | q, 11 | sub, 12 | cin, 13 | cout 14 | ); 15 | 16 | 17 | input [7:0] a; 18 | input [7:0] b; 19 | output [7:0] q; 20 | input sub; 21 | input cin; 22 | output cout; 23 | 24 | wire [7:0] q; 25 | wire cout; 26 | wire [8:0] A_i; 27 | wire [8:0] B_i; 28 | wire [8:0] Full_Carry; 29 | wire [8:0] Res_i; 30 | 31 | assign B_i[8] = 1'b 0; 32 | assign B_i[7:0] = sub === 1'b 1 ? ~b : b; 33 | assign A_i[8] = 1'b 0; 34 | assign A_i[7:0] = a; 35 | assign Full_Carry[8:1] = 8'b 00000000; 36 | assign Full_Carry[0] = cin; 37 | assign Res_i = A_i + B_i + Full_Carry; 38 | assign cout = Res_i[8]; 39 | assign q = Res_i[7:0]; 40 | 41 | endmodule // module addsub8 42 | 43 | -------------------------------------------------------------------------------- /verilator/hdl/baudgen.v: -------------------------------------------------------------------------------- 1 | // from fpga4fun 2 | 3 | module baudgen #( 4 | parameter ClkFrequency = 27000000, // 27MHz 5 | parameter Baud = 115200*4, 6 | parameter BaudGeneratorAccWidth = 16, 7 | parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4) 8 | ) ( 9 | clk, 10 | tick 11 | ); 12 | 13 | input clk; 14 | output tick; 15 | 16 | reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc; 17 | always @(posedge clk) 18 | BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc; 19 | 20 | wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]; 21 | 22 | assign tick = BaudTick; 23 | 24 | endmodule; -------------------------------------------------------------------------------- /verilator/hdl/build_27MHz.bat: -------------------------------------------------------------------------------- 1 | copy .\27MHz\baudgen.v baudgen.v 2 | cd ..\build 3 | do_exe.bat -------------------------------------------------------------------------------- /verilator/hdl/mf8_pcs.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module mf8_pcs(Clk, Reset_n, Offs_In, Pause, RJmp, NPC, PC); 7 | input Clk; 8 | input Reset_n; 9 | input [11:0] Offs_In; 10 | input Pause; 11 | input RJmp; 12 | output [11:0] NPC; 13 | output [11:0] PC; 14 | 15 | reg [11:0] PC_i; 16 | wire [11:0] NPC_i; 17 | wire [11:0] inc_or_nop; 18 | wire [11:0] real_offset; 19 | 20 | 21 | assign NPC = NPC_i; 22 | assign PC = PC_i; 23 | 24 | assign inc_or_nop = {11'b00000000000, ( ~Pause)}; 25 | assign real_offset = (RJmp == 1'b0) ? (inc_or_nop) : (Offs_In); 26 | assign NPC_i = PC_i + real_offset; 27 | 28 | always @(posedge Clk or negedge Reset_n) begin 29 | if (Reset_n == 1'b0) begin 30 | PC_i <= 12'b000000000000; 31 | end else begin 32 | PC_i <= NPC_i; 33 | end 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /verilator/hdl/mf8_reg.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | 7 | module mf8_reg(Clk, Reset_n, Wr, Rd_Addr, Rr_Addr, Data_In, Rd_Data, Rr_Data, Z); 8 | input Clk; 9 | input Reset_n; 10 | input Wr; 11 | input [4:0] Rd_Addr; 12 | input [4:0] Rr_Addr; 13 | input [7:0] Data_In; 14 | output [7:0] Rd_Data; 15 | reg [7:0] Rd_Data; 16 | output [7:0] Rr_Data; 17 | reg [7:0] Rr_Data; 18 | output [15:0] Z; 19 | reg [15:0] Z; 20 | 21 | reg [7:0] RegD [31:0]; 22 | reg [7:0] RegR [31:0]; 23 | reg [4:0] Rd_Addr_r; 24 | 25 | always @(posedge Clk) begin 26 | Rd_Addr_r <= Rd_Addr; 27 | Rd_Data <= RegD[Rd_Addr]; 28 | Rr_Data <= RegR[Rr_Addr]; 29 | if (Wr == 1'b1) begin 30 | RegD[Rd_Addr_r] <= Data_In; 31 | RegR[Rd_Addr_r] <= Data_In; 32 | if (Rd_Addr_r == Rd_Addr) begin 33 | Rd_Data <= Data_In; 34 | end 35 | if (Rd_Addr_r == Rr_Addr) begin 36 | Rr_Data <= Data_In; 37 | end 38 | if (Rd_Addr_r == 5'b11110) begin 39 | Z[7:0] <= Data_In; 40 | end 41 | if (Rd_Addr_r == 5'b11111) begin 42 | Z[15:8] <= Data_In; 43 | end 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /verilator/hdl/tb.cc: -------------------------------------------------------------------------------- 1 | #include "Vtb.h" 2 | #include "verilated.h" 3 | 4 | int main(int argc, char **argv, char **env) 5 | { 6 | Verilated::commandArgs(argc, argv); 7 | Vtb* top = new Vtb; 8 | 9 | top->clk = 0; 10 | while (!Verilated::gotFinish()) { 11 | top->clk = !top->clk; 12 | top->eval(); 13 | } 14 | 15 | delete top; 16 | exit(0); 17 | } 18 | 19 | -------------------------------------------------------------------------------- /verilator/hdl/tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ps 2 | 3 | module tb ( 4 | `ifdef VERILATOR 5 | input clk 6 | `endif 7 | ); 8 | `ifndef VERILATOR 9 | reg clk = 1; 10 | always #10 clk = ~clk; 11 | `endif 12 | 13 | reg resetn = 0; 14 | integer resetn_cnt = 0; 15 | 16 | reg uresetn = 0; 17 | integer uresetn_cnt = 0; 18 | 19 | integer cycle = 0; 20 | 21 | wire trap; 22 | 23 | initial begin 24 | $write("\nRISC-V Soft CPU Contest 2018\n"); 25 | $write("Engine-V Contest entry by MicroFPGA UG\n"); 26 | $write("Verilator testbench: MF8A18 booting from SPI Flash\n\n"); 27 | 28 | $write("[TESTBENCH_BEGIN]\n"); 29 | end 30 | 31 | always @(posedge clk) begin 32 | cycle <= cycle + 1; 33 | end 34 | 35 | always @(posedge clk) begin 36 | if (resetn_cnt < 200) 37 | resetn_cnt <= resetn_cnt + 1; 38 | else 39 | resetn <= 1; 40 | end 41 | 42 | wire UART_RX_wire; 43 | wire [7:0] UART_rx_byte; 44 | wire UART_rx_rdy; 45 | wire uart_baud_4x; 46 | 47 | wire FLASH_MISO; 48 | wire FLASH_MOSI; 49 | wire FLASH_SCK; 50 | wire FLASH_CS; 51 | 52 | MF8A18_SoC soc ( 53 | .clk (clk), 54 | .resetn (resetn), 55 | .FLASH_MISO (FLASH_MISO), 56 | .FLASH_MOSI (FLASH_MOSI), 57 | .FLASH_SCK (FLASH_SCK), 58 | .FLASH_CS (FLASH_CS), 59 | .UART_TXD (UART_RX_wire) 60 | ); 61 | 62 | spiflash flash ( 63 | .csb (FLASH_CS), 64 | .clk (FLASH_SCK), 65 | .io0 (FLASH_MOSI), 66 | .io1 (FLASH_MISO), 67 | .io2 (1'b 1), 68 | .io3 (1'b 1) 69 | ); 70 | 71 | 72 | baudgen baud115200 ( 73 | .clk (clk), 74 | .tick (uart_baud_4x) 75 | ); 76 | 77 | rx uart_rx_inst ( 78 | .res_n (uresetn), 79 | .rx (UART_RX_wire), 80 | .clk (uart_baud_4x), /* Baud Rate x 4 (4 posedge's per bit) */ 81 | .rx_byte (UART_rx_byte), 82 | .rdy (UART_rx_rdy) 83 | ); 84 | 85 | always @(posedge clk) begin 86 | if (cycle > 5*50*1000000) begin 87 | // if (cycle > 1000) begin 88 | $display("Finished after about 5 seconds run time...\n\r"); 89 | $finish; 90 | end 91 | end 92 | 93 | always @(posedge uart_baud_4x) begin 94 | if (uresetn_cnt < 2) 95 | uresetn_cnt <= uresetn_cnt + 1; 96 | else 97 | uresetn <= 1; 98 | 99 | if (UART_rx_rdy) begin 100 | if (UART_rx_byte == 8'hff) begin 101 | $write("[TESTBENCH_END]\n\n"); 102 | $write("RV32I Compliance test Halt"); 103 | $finish; 104 | end else 105 | $write("%c", UART_rx_byte); 106 | end 107 | end 108 | 109 | 110 | 111 | endmodule 112 | -------------------------------------------------------------------------------- /verilator/hdl_mss/50MHz/baudgen.v: -------------------------------------------------------------------------------- 1 | // from fpga4fun 2 | 3 | module baudgen #( 4 | parameter ClkFrequency = 50000000, // 50MHz 5 | parameter Baud = 115200*4, 6 | parameter BaudGeneratorAccWidth = 16, 7 | parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4) 8 | ) ( 9 | clk, 10 | tick 11 | ); 12 | 13 | input clk; 14 | output tick; 15 | 16 | reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc; 17 | always @(posedge clk) 18 | BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc; 19 | 20 | wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]; 21 | 22 | assign tick = BaudTick; 23 | 24 | endmodule; -------------------------------------------------------------------------------- /verilator/hdl_mss/MF8A18.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module MF8A18 ( 7 | CLK, 8 | RSTn, 9 | rom_addr, 10 | rom_data, 11 | maddr, 12 | mwdata, 13 | ramdata, 14 | mwrite, 15 | mread, 16 | mready, 17 | UART_TXD 18 | ); 19 | 20 | 21 | input CLK; 22 | input RSTn; 23 | output [9:0] rom_addr; 24 | input [15:0] rom_data; 25 | output [15:0] maddr; 26 | output [7:0] mwdata; 27 | input [7:0] ramdata; 28 | output mwrite; 29 | output mread; 30 | input mready; 31 | output UART_TXD; 32 | 33 | 34 | wire [9:0] rom_addr; 35 | wire [15:0] maddr; 36 | wire [7:0] mwdata; 37 | wire mwrite; 38 | wire mread; 39 | 40 | reg UART_TXD; 41 | reg Reset_s_n; 42 | wire IO_Rd; 43 | wire IO_Wr; 44 | wire IO_Wr_HR; 45 | wire [5:0] IO_Addr; 46 | wire [7:0] IO_WData; 47 | wire [7:0] IO_RData; 48 | wire [15:0] maddr_i; 49 | wire mread_i; 50 | wire mwrite_i; 51 | 52 | assign maddr = maddr_i; 53 | assign mread = mread_i; 54 | assign mwrite = mwrite_i; 55 | assign mwdata = IO_WData; 56 | 57 | always @(posedge CLK) 58 | begin : process_1 59 | Reset_s_n <= RSTn; 60 | end 61 | 62 | always @(posedge CLK or negedge Reset_s_n) 63 | begin : process_2 64 | if (Reset_s_n === 1'b 0) 65 | begin 66 | UART_TXD <= 1'b 1; 67 | end else 68 | begin 69 | if (IO_Wr === 1'b 1) 70 | begin 71 | UART_TXD <= IO_WData[0]; 72 | end 73 | end 74 | end 75 | 76 | mf8_core core ( 77 | .Clk (CLK), 78 | .Reset_n (Reset_s_n), 79 | .ROM_Addr (rom_addr[9:0]), 80 | .ROM_Data (rom_data), 81 | .ZZ (maddr_i), 82 | .ram_datain (ramdata), 83 | .ram_write (mwrite_i), 84 | .ram_read (mread_i), 85 | .ram_ready (mready), 86 | .IO_Rd (IO_Rd), 87 | .IO_Wr (IO_Wr), 88 | .IO_Addr (IO_Addr), 89 | .IO_RData (IO_RData), 90 | .IO_WData (IO_WData) 91 | ); 92 | 93 | assign IO_RData = 8'b 00000000; 94 | 95 | endmodule 96 | 97 | -------------------------------------------------------------------------------- /verilator/hdl_mss/RAM32K.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module RAM32K ( 7 | clk, 8 | addr, 9 | din, 10 | dout, 11 | we 12 | ); 13 | 14 | input clk; 15 | input we; 16 | input [14:0] addr; 17 | input [7:0] din; 18 | output [7:0] dout; 19 | 20 | 21 | //wire [13:0] spram_addr; 22 | //wire [15:0] spram_wr_data; 23 | //wire [15:0] spram_rd_data; 24 | //wire [3:0] spram_mask; 25 | 26 | //assign spram_wr_data[15:8] = din; 27 | //assign spram_wr_data [7:0] = din; 28 | // use word address 29 | //assign spram_addr = addr[14:1]; 30 | // assign write masks 31 | //assign spram_mask[0] = ~addr[0]; 32 | //assign spram_mask[1] = ~addr[0]; 33 | //assign spram_mask[2] = addr[0]; 34 | //assign spram_mask[3] = addr[0]; 35 | 36 | // latch lower address 37 | //reg addr0_s; 38 | //always @ (posedge clk) begin 39 | // addr0_s <= addr[0]; 40 | //end 41 | // return correct byte depending on latched address ! 42 | //assign dout = addr0_s ? spram_rd_data[15:8] : spram_rd_data[7:0]; 43 | 44 | // iceCube2.. 45 | /* 46 | SB_SPRAM256KA inst_SPRAM256KA( 47 | .ADDRESS (spram_addr ), 48 | .DATAIN (spram_wr_data ), 49 | .MASKWREN (spram_mask ), 50 | .WREN (we ), 51 | .CHIPSELECT (1'b1 ), 52 | .CLOCK (clk ), 53 | .STANDBY (1'b0 ), 54 | .SLEEP (1'b0 ), 55 | .POWEROFF (1'b1 ), 56 | .DATAOUT (spram_rd_data ) 57 | ); 58 | */ 59 | 60 | // Radiant.. 61 | /* 62 | SP256K inst_SPRAM256KA( 63 | .AD (spram_addr ), 64 | .DI (spram_wr_data ), 65 | .MASKWE (spram_mask ), 66 | .WE (we ), 67 | .CS (1'b1 ), 68 | .CK (clk ), 69 | .STDBY (1'b0 ), 70 | .SLEEP (1'b0 ), 71 | .PWROFF_N (1'b1 ), 72 | .DO (spram_rd_data ) 73 | ); 74 | */ 75 | 76 | /* 77 | * Generic and simulator friendly memory 78 | */ 79 | 80 | reg [7:0] memory [0:32*1024-1]; 81 | reg [7:0] memory_r; 82 | initial $readmemh("riscv.mem", memory); 83 | 84 | assign dout = memory_r; 85 | 86 | always @(posedge clk) begin 87 | if (we) memory[addr] <= din; 88 | memory_r <= memory[addr]; 89 | end 90 | 91 | always @(posedge clk) begin 92 | if (we) begin 93 | if (addr < 40) begin 94 | $write("\n\rWR: %04X %02X ", addr, din); 95 | end 96 | end 97 | end 98 | 99 | 100 | 101 | endmodule -------------------------------------------------------------------------------- /verilator/hdl_mss/RAM32KAHB.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | 7 | module RAM32KAHB ( 8 | maddr, 9 | mwdata, 10 | mrdata, 11 | mwrite, 12 | mread, 13 | mready, 14 | HADDR, 15 | HTRANS, 16 | HWRITE, 17 | HSIZE, 18 | HWDATA, 19 | HSEL, 20 | HMASTLOCK, 21 | HREADY_OUT, 22 | HREADY, 23 | HRDATA, 24 | HRESP, 25 | Clk); 26 | 27 | 28 | input [15:0] maddr; 29 | input [7:0] mwdata; 30 | output [7:0] mrdata; 31 | input mwrite; 32 | input mread; 33 | output mready; 34 | output [31:0] HADDR; 35 | output [1:0] HTRANS; 36 | output HWRITE; 37 | output [1:0] HSIZE; 38 | output [31:0] HWDATA; 39 | output HSEL; 40 | output HMASTLOCK; 41 | output HREADY_OUT; 42 | input HREADY; 43 | input [31:0] HRDATA; 44 | input HRESP; 45 | input Clk; 46 | 47 | wire [7:0] mrdata; 48 | wire mready; 49 | wire [31:0] HADDR; 50 | wire [1:0] HTRANS; 51 | wire HWRITE; 52 | wire [1:0] HSIZE; 53 | wire [31:0] HWDATA; 54 | wire HSEL; 55 | wire HMASTLOCK; 56 | wire HREADY_OUT; 57 | reg [7:0] mwdata_s; 58 | 59 | assign HREADY_OUT = HREADY; 60 | assign mready = HREADY; 61 | 62 | // 63 | assign HWDATA[31:16] = 16'h 0000; 64 | 65 | // Latch write DATA 66 | assign HWDATA[15:8] = mwdata_s; 67 | assign HWDATA[7:0] = mwdata_s; 68 | 69 | always @(posedge Clk) 70 | begin : process_1 71 | mwdata_s <= mwdata; 72 | end 73 | 74 | assign HSIZE = 2'b 00; 75 | // Byte transfers only 76 | assign HSEL = 1'b 1; 77 | assign HTRANS[0] = 1'b 0; 78 | assign HTRANS[1] = mread | mwrite; 79 | assign HWRITE = mwrite; 80 | assign HADDR[0] = maddr[0]; 81 | assign HADDR[1] = 1'b 0; 82 | assign HADDR[15:2] = maddr[14:1]; 83 | assign HADDR[31:16] = 16'h 2000; 84 | // eSRAM 85 | 86 | // input mux 87 | assign mrdata = maddr[0] === 1'b 0 ? HRDATA[7:0] : 88 | HRDATA[15:8]; 89 | 90 | endmodule // module RAM32KAHB 91 | 92 | -------------------------------------------------------------------------------- /verilator/hdl_mss/ROM1K16.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module ROM1K16 ( 7 | clk, 8 | addr, 9 | dout 10 | ); 11 | 12 | input clk; 13 | input [9:0] addr; 14 | output [15:0] dout; 15 | 16 | /* 17 | * Generic and simulator friendly memory 18 | */ 19 | 20 | reg [15:0] memory [0:2*1024-1]; 21 | reg [15:0] memory_r; 22 | initial $readmemh("rv32i.mem", memory); 23 | 24 | assign dout = memory_r; 25 | 26 | always @(posedge clk) begin 27 | memory_r <= memory[addr]; 28 | // $write("\n\rROM: %04X", addr); 29 | end 30 | 31 | 32 | endmodule -------------------------------------------------------------------------------- /verilator/hdl_mss/addsub8.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | 7 | module addsub8 ( 8 | a, 9 | b, 10 | q, 11 | sub, 12 | cin, 13 | cout 14 | ); 15 | 16 | 17 | input [7:0] a; 18 | input [7:0] b; 19 | output [7:0] q; 20 | input sub; 21 | input cin; 22 | output cout; 23 | 24 | wire [7:0] q; 25 | wire cout; 26 | wire [8:0] A_i; 27 | wire [8:0] B_i; 28 | wire [8:0] Full_Carry; 29 | wire [8:0] Res_i; 30 | 31 | assign B_i[8] = 1'b 0; 32 | assign B_i[7:0] = sub === 1'b 1 ? ~b : b; 33 | assign A_i[8] = 1'b 0; 34 | assign A_i[7:0] = a; 35 | assign Full_Carry[8:1] = 8'b 00000000; 36 | assign Full_Carry[0] = cin; 37 | assign Res_i = A_i + B_i + Full_Carry; 38 | assign cout = Res_i[8]; 39 | assign q = Res_i[7:0]; 40 | 41 | endmodule // module addsub8 42 | 43 | -------------------------------------------------------------------------------- /verilator/hdl_mss/baudgen.v: -------------------------------------------------------------------------------- 1 | // from fpga4fun 2 | 3 | module baudgen #( 4 | parameter ClkFrequency = 50000000, // 50MHz 5 | parameter Baud = 115200*4, 6 | parameter BaudGeneratorAccWidth = 16, 7 | parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4) 8 | ) ( 9 | clk, 10 | tick 11 | ); 12 | 13 | input clk; 14 | output tick; 15 | 16 | reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc; 17 | always @(posedge clk) 18 | BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc; 19 | 20 | wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]; 21 | 22 | assign tick = BaudTick; 23 | 24 | endmodule; -------------------------------------------------------------------------------- /verilator/hdl_mss/build_50MHz.bat: -------------------------------------------------------------------------------- 1 | copy .\50MHz\baudgen.v baudgen.v 2 | cd ..\build_mss 3 | do_exe.bat -------------------------------------------------------------------------------- /verilator/hdl_mss/mf8_pcs.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | module mf8_pcs(Clk, Reset_n, Offs_In, Pause, RJmp, NPC, PC); 7 | input Clk; 8 | input Reset_n; 9 | input [11:0] Offs_In; 10 | input Pause; 11 | input RJmp; 12 | output [11:0] NPC; 13 | output [11:0] PC; 14 | 15 | reg [11:0] PC_i; 16 | wire [11:0] NPC_i; 17 | wire [11:0] inc_or_nop; 18 | wire [11:0] real_offset; 19 | 20 | 21 | assign NPC = NPC_i; 22 | assign PC = PC_i; 23 | 24 | assign inc_or_nop = {11'b00000000000, ( ~Pause)}; 25 | assign real_offset = (RJmp == 1'b0) ? (inc_or_nop) : (Offs_In); 26 | assign NPC_i = PC_i + real_offset; 27 | 28 | always @(posedge Clk or negedge Reset_n) begin 29 | if (Reset_n == 1'b0) begin 30 | PC_i <= 12'b000000000000; 31 | end else begin 32 | PC_i <= NPC_i; 33 | end 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /verilator/hdl_mss/mf8_reg.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 MicroFPGA UG 3 | * Apache 2.0 License 4 | */ 5 | 6 | 7 | module mf8_reg(Clk, Reset_n, Wr, Rd_Addr, Rr_Addr, Data_In, Rd_Data, Rr_Data, Z); 8 | input Clk; 9 | input Reset_n; 10 | input Wr; 11 | input [4:0] Rd_Addr; 12 | input [4:0] Rr_Addr; 13 | input [7:0] Data_In; 14 | output [7:0] Rd_Data; 15 | reg [7:0] Rd_Data; 16 | output [7:0] Rr_Data; 17 | reg [7:0] Rr_Data; 18 | output [15:0] Z; 19 | reg [15:0] Z; 20 | 21 | reg [7:0] RegD [31:0]; 22 | reg [7:0] RegR [31:0]; 23 | reg [4:0] Rd_Addr_r; 24 | 25 | always @(posedge Clk) begin 26 | Rd_Addr_r <= Rd_Addr; 27 | Rd_Data <= RegD[Rd_Addr]; 28 | Rr_Data <= RegR[Rr_Addr]; 29 | if (Wr == 1'b1) begin 30 | RegD[Rd_Addr_r] <= Data_In; 31 | RegR[Rd_Addr_r] <= Data_In; 32 | if (Rd_Addr_r == Rd_Addr) begin 33 | Rd_Data <= Data_In; 34 | end 35 | if (Rd_Addr_r == Rr_Addr) begin 36 | Rr_Data <= Data_In; 37 | end 38 | if (Rd_Addr_r == 5'b11110) begin 39 | Z[7:0] <= Data_In; 40 | end 41 | if (Rd_Addr_r == 5'b11111) begin 42 | Z[15:8] <= Data_In; 43 | end 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /verilator/hdl_mss/tb.cc: -------------------------------------------------------------------------------- 1 | #include "Vtb.h" 2 | #include "verilated.h" 3 | 4 | int main(int argc, char **argv, char **env) 5 | { 6 | Verilated::commandArgs(argc, argv); 7 | Vtb* top = new Vtb; 8 | 9 | top->clk = 0; 10 | while (!Verilated::gotFinish()) { 11 | top->clk = !top->clk; 12 | top->eval(); 13 | } 14 | 15 | delete top; 16 | exit(0); 17 | } 18 | 19 | -------------------------------------------------------------------------------- /verilator/hdl_mss/tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ps 2 | 3 | module tb ( 4 | `ifdef VERILATOR 5 | input clk 6 | `endif 7 | ); 8 | `ifndef VERILATOR 9 | reg clk = 1; 10 | always #10 clk = ~clk; 11 | `endif 12 | 13 | reg resetn = 0; 14 | integer resetn_cnt = 0; 15 | 16 | reg uresetn = 0; 17 | integer uresetn_cnt = 0; 18 | 19 | integer cycle = 0; 20 | 21 | wire trap; 22 | 23 | initial begin 24 | $write("\nRISC-V Soft CPU Contest 2018\n"); 25 | $write("Engine-V Contest entry by MicroFPGA UG\n"); 26 | $write("Verilator testbench: MF8A18 booting from MSS eSRAM\n\n"); 27 | 28 | $write("[TESTBENCH_BEGIN]\n"); 29 | end 30 | 31 | always @(posedge clk) begin 32 | cycle <= cycle + 1; 33 | end 34 | 35 | always @(posedge clk) begin 36 | if (resetn_cnt < 200) 37 | resetn_cnt <= resetn_cnt + 1; 38 | else 39 | resetn <= 1; 40 | end 41 | 42 | wire UART_RX_wire; 43 | wire [7:0] UART_rx_byte; 44 | wire UART_rx_rdy; 45 | wire uart_baud_4x; 46 | 47 | MF8A18_SoC soc ( 48 | .clk (clk), 49 | .resetn (resetn), 50 | .UART_TXD (UART_RX_wire) 51 | ); 52 | 53 | 54 | baudgen baud115200 ( 55 | .clk (clk), 56 | .tick (uart_baud_4x) 57 | ); 58 | 59 | rx uart_rx_inst ( 60 | .res_n (uresetn), 61 | .rx (UART_RX_wire), 62 | .clk (uart_baud_4x), /* Baud Rate x 4 (4 posedge's per bit) */ 63 | .rx_byte (UART_rx_byte), 64 | .rdy (UART_rx_rdy) 65 | ); 66 | 67 | always @(posedge clk) begin 68 | if (cycle > 5*50*1000000) begin 69 | // if (cycle > 1000) begin 70 | $display("Finished after about 5 seconds run time...\n\r"); 71 | $finish; 72 | end 73 | end 74 | 75 | always @(posedge uart_baud_4x) begin 76 | if (uresetn_cnt < 2) 77 | uresetn_cnt <= uresetn_cnt + 1; 78 | else 79 | uresetn <= 1; 80 | 81 | if (UART_rx_rdy) begin 82 | if (UART_rx_byte == 8'hff) begin 83 | $write("[TESTBENCH_END]\n\n"); 84 | $write("RV32I Compliance test Halt"); 85 | $finish; 86 | end else 87 | $write("%c", UART_rx_byte); 88 | end 89 | end 90 | 91 | 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /verilator/images/I-ADD-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-ADD-01.bin -------------------------------------------------------------------------------- /verilator/images/I-ADDI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-ADDI-01.bin -------------------------------------------------------------------------------- /verilator/images/I-ADDI-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 FE 4 | 17 11 00 00 13 01 01 02 83 A1 00 00 13 82 11 00 5 | 93 82 F1 7F 13 83 F1 FF 93 83 01 00 13 84 01 80 6 | 23 20 31 00 23 22 41 00 23 24 51 00 23 26 61 00 7 | 23 28 71 00 23 2A 81 00 97 10 00 00 93 80 C0 FA 8 | 17 11 00 00 13 01 81 FF 03 A4 00 00 93 04 14 00 9 | 13 05 F4 7F 93 05 F4 FF 13 06 04 00 93 06 04 80 10 | 23 20 81 00 23 22 91 00 23 24 A1 00 23 26 B1 00 11 | 23 28 C1 00 23 2A D1 00 97 10 00 00 93 80 00 F7 12 | 17 11 00 00 13 01 01 FD 83 A6 00 00 13 87 16 00 13 | 93 87 F6 7F 13 88 F6 FF 93 88 06 00 13 89 06 80 14 | 23 20 D1 00 23 22 E1 00 23 24 F1 00 23 26 01 01 15 | 23 28 11 01 23 2A 21 01 97 10 00 00 93 80 40 F3 16 | 17 11 00 00 13 01 81 FA 03 A9 00 00 93 09 19 00 17 | 13 0A F9 7F 93 0A F9 FF 13 0B 09 00 93 0B 09 80 18 | 23 20 21 01 23 22 31 01 23 24 41 01 23 26 51 01 19 | 23 28 61 01 23 2A 71 01 97 10 00 00 93 80 80 EF 20 | 17 11 00 00 13 01 01 F8 83 AB 00 00 13 8C 1B 00 21 | 93 8C FB 7F 13 8D FB FF 93 8D 0B 00 13 8E 0B 80 22 | 23 20 71 01 23 22 81 01 23 24 91 01 23 26 A1 01 23 | 23 28 B1 01 23 2A C1 01 17 1D 00 00 13 0D CD EB 24 | 97 1D 00 00 93 8D 8D F5 03 2E 0D 00 93 0E 1E 00 25 | 13 8F 1E 00 93 0F 1F 00 93 80 1F 00 13 81 10 00 26 | 93 01 11 00 23 A0 CD 01 23 A2 DD 01 23 A4 ED 01 27 | 23 A6 FD 01 23 A8 1D 00 23 AA 2D 00 23 AC 3D 00 28 | 97 10 00 00 93 80 80 E7 17 11 00 00 13 01 C1 F2 29 | 83 A2 00 00 13 80 12 00 23 20 01 00 97 10 00 00 30 | 93 80 00 E6 17 11 00 00 13 01 41 F1 83 A2 00 00 31 | 13 80 12 00 93 02 10 00 23 20 01 00 23 22 51 00 32 | 97 10 00 00 93 80 00 E4 17 11 00 00 13 01 81 EF 33 | 83 A1 00 00 13 82 01 00 93 02 02 00 13 83 02 00 34 | 13 07 03 00 93 07 07 00 13 88 07 00 93 0C 08 00 35 | 13 8D 0C 00 93 0D 0D 00 23 20 31 00 23 22 41 00 36 | 23 24 A1 01 23 26 B1 01 17 15 00 00 13 05 85 E1 37 | 97 15 00 00 93 85 05 EC 37 C6 00 00 63 0E B5 04 38 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 39 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 40 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 41 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 42 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 43 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 44 | 6F F0 1F D7 73 10 00 C0 00 00 00 00 00 00 00 00 45 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 | @00001000 47 | 00 00 00 00 01 00 00 00 FF FF FF FF FF FF FF 7F 48 | 00 00 00 80 CD AB 00 00 78 56 34 12 98 BA DC FE 49 | 14 58 92 36 00 00 00 00 00 00 00 00 00 00 00 00 50 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 57 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 58 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 59 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 60 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 61 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 62 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 63 | -------------------------------------------------------------------------------- /verilator/images/I-AND-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-AND-01.bin -------------------------------------------------------------------------------- /verilator/images/I-ANDI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-ANDI-01.bin -------------------------------------------------------------------------------- /verilator/images/I-ANDI-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 FE 4 | 17 11 00 00 13 01 01 02 83 A1 00 00 13 F2 11 00 5 | 93 F2 F1 7F 13 F3 F1 FF 93 F3 01 00 13 F4 01 80 6 | 23 20 31 00 23 22 41 00 23 24 51 00 23 26 61 00 7 | 23 28 71 00 23 2A 81 00 97 10 00 00 93 80 C0 FA 8 | 17 11 00 00 13 01 81 FF 03 A4 00 00 93 74 14 00 9 | 13 75 F4 7F 93 75 F4 FF 13 76 04 00 93 76 04 80 10 | 23 20 81 00 23 22 91 00 23 24 A1 00 23 26 B1 00 11 | 23 28 C1 00 23 2A D1 00 97 10 00 00 93 80 00 F7 12 | 17 11 00 00 13 01 01 FD 83 A6 00 00 13 F7 16 00 13 | 93 F7 F6 7F 13 F8 F6 FF 93 F8 06 00 13 F9 06 80 14 | 23 20 D1 00 23 22 E1 00 23 24 F1 00 23 26 01 01 15 | 23 28 11 01 23 2A 21 01 97 10 00 00 93 80 40 F3 16 | 17 11 00 00 13 01 81 FA 03 A9 00 00 93 79 19 00 17 | 13 7A F9 7F 93 7A F9 FF 13 7B 09 00 93 7B 09 80 18 | 23 20 21 01 23 22 31 01 23 24 41 01 23 26 51 01 19 | 23 28 61 01 23 2A 71 01 97 10 00 00 93 80 80 EF 20 | 17 11 00 00 13 01 01 F8 83 AB 00 00 13 FC 1B 00 21 | 93 FC FB 7F 13 FD FB FF 93 FD 0B 00 13 FE 0B 80 22 | 23 20 71 01 23 22 81 01 23 24 91 01 23 26 A1 01 23 | 23 28 B1 01 23 2A C1 01 17 1D 00 00 13 0D CD EB 24 | 97 1D 00 00 93 8D 8D F5 03 2E 0D 00 93 7E FE 07 25 | 13 FF FE 03 93 7F FF 01 93 F0 FF 00 13 F1 70 00 26 | 93 71 31 00 23 A0 CD 01 23 A2 DD 01 23 A4 ED 01 27 | 23 A6 FD 01 23 A8 1D 00 23 AA 2D 00 23 AC 3D 00 28 | 97 10 00 00 93 80 80 E7 17 11 00 00 13 01 C1 F2 29 | 83 A2 00 00 13 F0 12 00 23 20 01 00 97 10 00 00 30 | 93 80 00 E6 17 11 00 00 13 01 41 F1 83 A2 00 00 31 | 13 F0 12 00 93 72 10 00 23 20 01 00 23 22 51 00 32 | 97 10 00 00 93 80 00 E4 17 11 00 00 13 01 81 EF 33 | 83 A1 00 00 13 F2 F1 FF 93 72 F2 FF 13 F3 F2 FF 34 | 13 77 F3 FF 93 77 F7 FF 13 F8 F7 FF 93 7C F8 FF 35 | 13 FD FC FF 93 7D FD FF 23 20 31 00 23 22 41 00 36 | 23 24 A1 01 23 26 B1 01 17 15 00 00 13 05 85 E1 37 | 97 15 00 00 93 85 05 EC 37 C6 00 00 63 0E B5 04 38 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 39 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 40 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 41 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 42 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 43 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 44 | 6F F0 1F D7 73 10 00 C0 00 00 00 00 00 00 00 00 45 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 | @00001000 47 | 00 00 00 00 01 00 00 00 FF FF FF FF FF FF FF 7F 48 | 00 00 00 80 FF FF CD AB 78 56 34 12 98 BA DC FE 49 | 14 58 92 36 00 00 00 00 00 00 00 00 00 00 00 00 50 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 57 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 58 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 59 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 60 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 61 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 62 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 63 | -------------------------------------------------------------------------------- /verilator/images/I-AUIPC-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-AUIPC-01.bin -------------------------------------------------------------------------------- /verilator/images/I-AUIPC-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 17 17 00 00 13 07 87 FE 4 | 97 17 00 00 93 87 07 01 83 20 07 00 37 11 00 00 5 | 13 01 41 00 B7 F1 FF FF 93 81 81 00 37 F2 FF 7F 6 | 13 02 C2 00 B7 02 00 80 93 82 02 01 33 81 20 00 7 | B3 81 30 00 33 82 40 00 B3 82 50 00 17 03 00 00 8 | 97 13 00 00 17 F8 FF FF 97 FE FF 7F 97 0F 00 80 9 | 33 43 13 00 B3 C3 23 00 33 48 38 00 B3 CE 4E 00 10 | B3 CF 5F 00 23 A0 67 00 23 A2 77 00 23 A4 07 01 11 | 23 A6 D7 01 23 A8 F7 01 97 18 00 00 93 88 C8 F6 12 | 17 18 00 00 13 08 48 FA B7 10 11 11 93 80 10 11 13 | 37 21 22 22 13 01 21 22 B7 37 33 33 93 87 37 33 14 | 37 4E 44 44 13 0E 4E 44 37 5F 55 55 13 0F 5F 55 15 | 83 A1 08 00 37 02 00 80 B7 F2 FF 7F 93 82 42 00 16 | 13 03 80 00 B7 13 00 00 93 83 C3 00 37 F4 FF FF 17 | 13 04 04 01 33 82 41 00 B3 82 51 00 33 83 61 00 18 | B3 83 71 00 33 84 81 00 97 00 00 80 17 F1 FF 7F 19 | 97 07 00 00 17 1E 00 00 17 FF FF FF B3 C0 40 00 20 | 33 41 51 00 B3 C7 67 00 33 4E 7E 00 33 4F 8F 00 21 | 23 20 18 00 23 22 28 00 23 24 F8 00 23 26 C8 01 22 | 23 28 E8 01 17 19 00 00 13 09 49 EC 97 18 00 00 23 | 93 88 C8 F0 83 20 09 00 03 21 49 00 83 21 89 00 24 | 17 02 00 00 13 02 42 FF 97 07 00 00 93 87 87 01 25 | 17 0F 00 00 13 0F 0F 04 97 02 00 00 93 82 C2 FD 26 | 17 08 00 00 13 08 08 00 97 0F 00 00 93 8F 8F 02 27 | 33 42 12 00 B3 C7 27 00 33 4F 3F 00 B3 82 12 40 28 | 33 48 28 00 B3 CF 3F 00 23 A0 48 00 23 A2 F8 00 29 | 23 A4 E8 01 23 A6 58 00 23 A8 08 01 23 AA F8 01 30 | 17 15 00 00 13 05 05 E7 97 15 00 00 93 85 85 EA 31 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 32 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 33 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 34 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 35 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 36 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 37 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DD 73 10 00 C0 38 | @00001000 39 | 5C 00 00 00 08 01 00 00 54 01 00 00 80 01 00 00 40 | B0 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 42 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 43 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 44 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 45 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 46 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 47 | -------------------------------------------------------------------------------- /verilator/images/I-BEQ-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-BEQ-01.bin -------------------------------------------------------------------------------- /verilator/images/I-BGE-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-BGE-01.bin -------------------------------------------------------------------------------- /verilator/images/I-BGEU-01.bin: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-BNE-01.bin -------------------------------------------------------------------------------- /verilator/images/I-CSRRC-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-CSRRC-01.bin -------------------------------------------------------------------------------- /verilator/images/I-CSRRC-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 17 00 00 93 87 87 FF 4 | 93 00 10 00 13 01 00 00 B7 01 F1 7F 93 81 F1 FF 5 | 37 02 00 80 93 02 F0 FF 73 90 02 34 F3 B0 00 34 6 | F3 90 02 34 73 31 01 34 73 91 02 34 F3 B1 01 34 7 | F3 91 02 34 73 32 02 34 73 92 02 34 F3 B2 02 34 8 | F3 12 00 34 23 A0 07 00 23 A2 17 00 23 A4 27 00 9 | 23 A6 37 00 23 A8 47 00 23 AA 57 00 97 12 00 00 10 | 93 82 C2 FA 93 05 10 00 13 06 00 00 B7 06 F1 7F 11 | 93 86 F6 FF 37 07 00 80 93 07 F0 FF 73 90 07 34 12 | F3 B5 05 34 73 36 06 34 F3 B6 06 34 73 37 07 34 13 | F3 B7 07 34 73 38 00 34 23 A0 B2 00 23 A2 C2 00 14 | 23 A4 D2 00 23 A6 E2 00 23 A8 F2 00 23 AA 02 01 15 | 17 1D 00 00 13 0D 0D F7 B7 5A 34 12 93 8A 8A 67 16 | 13 0A F0 FF 73 10 0A 34 73 BB 0A 34 F3 3A 0B 34 17 | F3 1B 0A 34 73 BC 0B 34 F3 3C 00 34 23 20 5D 01 18 | 23 22 6D 01 23 24 7D 01 23 26 8D 01 23 28 9D 01 19 | 97 10 00 00 93 80 40 F4 37 7F 72 42 13 0F FF E6 20 | 73 10 0F 34 73 30 0F 34 23 A0 00 00 23 A2 E0 01 21 | 17 11 00 00 13 01 C1 F2 B7 9F FF F7 93 8F 8F 81 22 | 73 90 0F 34 73 30 00 34 73 30 00 34 F3 3F 00 34 23 | 23 20 01 00 23 22 F1 01 17 11 00 00 13 01 C1 F0 24 | 13 02 F0 FF B7 52 38 96 93 82 42 27 B7 53 16 32 25 | 93 83 83 49 73 10 02 34 F3 B2 02 34 F3 B3 03 34 26 | 73 34 04 34 23 20 51 00 23 22 71 00 23 24 81 00 27 | 17 15 00 00 13 05 05 E8 97 15 00 00 93 85 85 ED 28 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 29 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 30 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 31 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 32 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 33 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 34 | 13 07 F0 0F 23 00 E6 00 6F F0 9F E0 73 10 00 C0 35 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 36 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 37 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 38 | @00001000 39 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 40 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 41 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 42 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 43 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 44 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 45 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 46 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 47 | -------------------------------------------------------------------------------- /verilator/images/I-CSRRCI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-CSRRCI-01.bin -------------------------------------------------------------------------------- /verilator/images/I-CSRRCI-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 17 00 00 93 87 87 FF 4 | 13 04 F0 FF 73 10 04 34 F3 F0 00 34 F3 10 04 34 5 | 73 71 00 34 73 11 04 34 F3 F1 0F 34 F3 11 04 34 6 | 73 72 08 34 73 12 04 34 F3 F2 07 34 F3 12 04 34 7 | 23 A0 07 00 23 A2 17 00 23 A4 27 00 23 A6 37 00 8 | 23 A8 47 00 23 AA 57 00 23 AC 87 00 97 12 00 00 9 | 93 82 02 FC 13 04 F0 FF 73 10 04 34 F3 F5 00 34 10 | 73 76 00 34 F3 F6 0F 34 73 77 08 34 F3 F7 07 34 11 | 73 78 00 34 23 A0 B2 00 23 A2 C2 00 23 A4 D2 00 12 | 23 A6 E2 00 23 A8 F2 00 23 AA 02 01 23 AC 82 00 13 | 97 10 00 00 93 80 80 F9 37 5A 16 32 13 0A 8A 49 14 | 73 10 0A 34 73 F0 07 34 73 1A 0A 34 23 A0 00 00 15 | 23 A2 40 01 17 15 00 00 13 05 C5 F3 97 15 00 00 16 | 93 85 45 F7 37 C6 00 00 63 0E B5 04 93 06 05 01 17 | 93 86 F6 FF 03 87 06 00 93 57 47 40 93 F7 F7 00 18 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 19 | 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 08 A0 00 20 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 21 | E3 10 D5 FC 13 05 05 01 13 07 A0 00 23 00 E6 00 22 | 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 6F F0 5F EC 23 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 24 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 25 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26 | @00001000 27 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 28 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 29 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 30 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 31 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 32 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 33 | -------------------------------------------------------------------------------- /verilator/images/I-CSRRS-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-CSRRS-01.bin -------------------------------------------------------------------------------- /verilator/images/I-CSRRS-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 17 00 00 93 87 87 FF 4 | 93 00 10 00 13 01 00 00 B7 01 F1 7F 93 81 F1 FF 5 | 37 02 00 80 93 02 F0 FF 73 10 00 34 F3 A0 00 34 6 | F3 10 00 34 73 21 01 34 73 11 00 34 F3 A1 01 34 7 | F3 11 00 34 73 22 02 34 73 12 00 34 F3 A2 02 34 8 | F3 12 00 34 23 A0 07 00 23 A2 17 00 23 A4 27 00 9 | 23 A6 37 00 23 A8 47 00 23 AA 57 00 97 12 00 00 10 | 93 82 C2 FA 93 05 10 00 13 06 00 00 B7 06 F1 7F 11 | 93 86 F6 FF 37 07 00 80 93 07 F0 FF 73 10 00 34 12 | F3 A5 05 34 73 26 06 34 F3 A6 06 34 73 27 07 34 13 | F3 A7 07 34 73 28 00 34 23 A0 B2 00 23 A2 C2 00 14 | 23 A4 D2 00 23 A6 E2 00 23 A8 F2 00 23 AA 02 01 15 | 17 1D 00 00 13 0D 0D F7 B7 5A 34 12 93 8A 8A 67 16 | 73 10 00 34 73 AB 0A 34 F3 2B 0B 34 F3 1B 00 34 17 | 73 AC 0B 34 F3 2C 00 34 23 20 5D 01 23 22 6D 01 18 | 23 24 7D 01 23 26 8D 01 23 28 9D 01 97 10 00 00 19 | 93 80 80 F4 37 7F 72 42 13 0F FF E6 73 10 0F 34 20 | 73 20 0F 34 23 A0 00 00 23 A2 E0 01 17 11 00 00 21 | 13 01 01 F3 B7 9F FF F7 93 8F 8F 81 73 90 0F 34 22 | 73 20 00 34 73 20 00 34 F3 2F 00 34 23 20 01 00 23 | 23 22 F1 01 17 11 00 00 13 01 01 F1 B7 53 16 32 24 | 93 83 83 49 B7 52 38 96 93 82 42 27 73 10 00 34 25 | F3 A2 02 34 F3 A3 03 34 73 24 04 34 23 20 51 00 26 | 23 22 71 00 23 24 81 00 17 15 00 00 13 05 85 E8 27 | 97 15 00 00 93 85 05 EE 37 C6 00 00 63 0E B5 04 28 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 29 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 30 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 31 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 32 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 33 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 34 | 6F F0 1F E1 73 10 00 C0 00 00 00 00 00 00 00 00 35 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 36 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 37 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 38 | @00001000 39 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 40 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 41 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 42 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 43 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 44 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 45 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 46 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 47 | -------------------------------------------------------------------------------- /verilator/images/I-CSRRSI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-CSRRSI-01.bin -------------------------------------------------------------------------------- /verilator/images/I-CSRRSI-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 17 00 00 93 87 87 FF 4 | 73 10 00 34 F3 E0 00 34 F3 10 00 34 73 61 00 34 5 | 73 11 00 34 F3 E1 0F 34 F3 11 00 34 73 62 08 34 6 | 73 12 00 34 F3 E2 07 34 F3 12 00 34 23 A0 07 00 7 | 23 A2 17 00 23 A4 27 00 23 A6 37 00 23 A8 47 00 8 | 23 AA 57 00 97 12 00 00 93 82 42 FC 73 10 00 34 9 | F3 E5 00 34 73 66 00 34 F3 E6 0F 34 73 67 08 34 10 | F3 E7 07 34 73 68 00 34 23 A0 02 00 23 A2 B2 00 11 | 23 A4 C2 00 23 A6 D2 00 23 A8 E2 00 23 AA F2 00 12 | 23 AC 02 01 97 10 00 00 93 80 00 FA 37 5A 16 32 13 | 13 0A 8A 49 73 10 0A 34 73 E0 07 34 F3 1A 0A 34 14 | 23 A0 00 00 23 A2 50 01 23 A4 40 01 17 15 00 00 15 | 13 05 45 F4 97 15 00 00 93 85 C5 F7 37 C6 00 00 16 | 63 0E B5 04 93 06 05 01 93 86 F6 FF 03 87 06 00 17 | 93 57 47 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 18 | 93 87 77 02 93 87 07 03 23 00 F6 00 93 57 07 40 19 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 20 | 93 87 07 03 23 00 F6 00 E3 10 D5 FC 13 05 05 01 21 | 13 07 A0 00 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 22 | 23 00 E6 00 6F F0 DF EC 73 10 00 C0 00 00 00 00 23 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 24 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 25 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26 | @00001000 27 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 28 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 29 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 30 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 31 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 32 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 33 | -------------------------------------------------------------------------------- /verilator/images/I-CSRRW-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-CSRRW-01.bin -------------------------------------------------------------------------------- /verilator/images/I-CSRRW-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 17 00 00 93 87 87 FF 4 | 93 00 10 00 93 01 00 00 93 02 F0 FF B7 0D 00 80 5 | 93 8D FD FF B7 0E 00 80 73 10 00 34 73 91 00 34 6 | 73 92 01 34 73 93 02 34 73 9E 0D 34 73 9F 0E 34 7 | F3 1F 00 34 23 A0 27 00 23 A2 47 00 23 A4 67 00 8 | 23 A6 C7 01 23 A8 E7 01 23 AA F7 01 17 1D 00 00 9 | 13 0D CD FB B7 50 34 12 93 80 80 67 37 E1 BC 9A 10 | 13 01 01 EF 73 90 00 34 F3 11 01 34 73 92 01 34 11 | F3 12 02 34 73 13 00 34 23 20 3D 00 23 22 4D 00 12 | 23 24 5D 00 23 26 6D 00 97 10 00 00 93 80 00 F9 13 | 37 71 72 42 13 01 F1 E6 73 10 01 34 73 10 00 34 14 | 23 A0 00 00 17 11 00 00 13 01 81 F7 B7 9D FF F7 15 | 93 8D 8D 81 73 90 0D 34 73 10 00 34 73 10 00 34 16 | F3 12 00 34 23 20 01 00 23 22 51 00 17 11 00 00 17 | 13 01 81 F5 B7 53 16 32 93 83 83 49 37 63 72 14 18 | 13 03 63 83 B7 52 38 96 93 82 42 27 73 10 03 34 19 | F3 92 02 34 F3 93 03 34 73 14 00 34 23 20 51 00 20 | 23 22 71 00 23 24 81 00 17 15 00 00 13 05 85 EE 21 | 97 15 00 00 93 85 05 F2 37 C6 00 00 63 0E B5 04 22 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 23 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 24 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 25 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 26 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 27 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 28 | 6F F0 1F E7 73 10 00 C0 00 00 00 00 00 00 00 00 29 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 | @00001000 31 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 32 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 33 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 34 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 35 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 36 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 37 | -------------------------------------------------------------------------------- /verilator/images/I-CSRRWI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-CSRRWI-01.bin -------------------------------------------------------------------------------- /verilator/images/I-CSRRWI-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 17 00 00 93 87 87 FF 4 | 73 10 00 34 73 D1 00 34 73 52 00 34 73 D3 0F 34 5 | 73 DE 07 34 73 5F 08 34 F3 5F 00 34 23 A0 07 00 6 | 23 A2 27 00 23 A4 47 00 23 A6 67 00 23 A8 C7 01 7 | 23 AA E7 01 23 AC F7 01 97 10 00 00 93 80 40 FD 8 | 73 D0 07 34 73 50 00 34 23 A0 00 00 17 15 00 00 9 | 13 05 45 FA 97 15 00 00 93 85 C5 FB 37 C6 00 00 10 | 63 0E B5 04 93 06 05 01 93 86 F6 FF 03 87 06 00 11 | 93 57 47 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 12 | 93 87 77 02 93 87 07 03 23 00 F6 00 93 57 07 40 13 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 14 | 93 87 07 03 23 00 F6 00 E3 10 D5 FC 13 05 05 01 15 | 13 07 A0 00 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 16 | 23 00 E6 00 6F F0 DF F2 73 10 00 C0 00 00 00 00 17 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 18 | @00001000 19 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 20 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 21 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 22 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 23 | -------------------------------------------------------------------------------- /verilator/images/I-DELAY_SLOTS-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-DELAY_SLOTS-01.bin -------------------------------------------------------------------------------- /verilator/images/I-DELAY_SLOTS-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 FF 4 | 37 11 11 11 13 01 11 11 6F 00 80 00 13 01 00 00 5 | 23 A0 20 00 97 10 00 00 93 80 00 FE 37 21 22 22 6 | 13 01 21 22 17 02 00 00 13 02 02 01 67 00 02 00 7 | 13 01 00 00 23 A0 20 00 97 10 00 00 93 80 00 FC 8 | 93 02 50 00 13 03 60 00 37 31 33 33 13 01 31 33 9 | 63 84 52 00 13 01 00 00 23 A0 20 00 97 10 00 00 10 | 93 80 00 FA 93 02 50 00 13 03 60 00 37 41 44 44 11 | 13 01 41 44 63 94 62 00 13 01 00 00 23 A0 20 00 12 | 97 10 00 00 93 80 00 F8 93 02 50 00 13 03 60 00 13 | 37 51 55 55 13 01 51 55 63 C4 62 00 13 01 00 00 14 | 23 A0 20 00 97 10 00 00 93 80 00 F6 93 02 50 00 15 | 13 03 60 00 37 61 66 66 13 01 61 66 63 E4 62 00 16 | 13 01 00 00 23 A0 20 00 97 10 00 00 93 80 00 F4 17 | 93 02 50 00 13 03 60 00 37 71 77 77 13 01 71 77 18 | 63 54 53 00 13 01 00 00 23 A0 20 00 97 10 00 00 19 | 93 80 00 F2 93 02 50 00 13 03 60 00 37 91 88 88 20 | 13 01 81 88 63 74 53 00 13 01 00 00 23 A0 20 00 21 | 17 15 00 00 13 05 05 EE 97 15 00 00 93 85 85 EF 22 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 23 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 24 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 25 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 26 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 27 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 28 | 13 07 F0 0F 23 00 E6 00 6F F0 9F E6 73 10 00 C0 29 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 | @00001000 31 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 32 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 33 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 34 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 35 | -------------------------------------------------------------------------------- /verilator/images/I-EBREAK-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-EBREAK-01.bin -------------------------------------------------------------------------------- /verilator/images/I-EBREAK-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 00 00 00 93 80 C0 02 4 | F3 9F 50 30 97 10 00 00 93 80 C0 FE 37 11 11 11 5 | 13 01 11 11 73 00 10 00 23 A0 00 00 73 90 5F 30 6 | 6F 00 80 02 73 2F 10 34 13 0F 4F 00 73 10 1F 34 7 | 73 2F 20 34 23 A0 E0 01 23 A2 20 00 23 A4 00 00 8 | 93 80 C0 00 73 00 20 30 17 15 00 00 13 05 85 FA 9 | 97 15 00 00 93 85 05 FB 37 C6 00 00 63 0E B5 04 10 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 11 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 12 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 14 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 15 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 16 | 6F F0 1F F3 73 10 00 C0 00 00 00 00 00 00 00 00 17 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 18 | @00001000 19 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 20 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 21 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 22 | -------------------------------------------------------------------------------- /verilator/images/I-ECALL-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-ECALL-01.bin -------------------------------------------------------------------------------- /verilator/images/I-ECALL-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 00 00 00 93 80 C0 02 4 | F3 9F 50 30 97 10 00 00 93 80 C0 FE 37 11 11 11 5 | 13 01 11 11 73 00 00 00 23 A0 00 00 73 90 5F 30 6 | 6F 00 80 02 73 2F 10 34 13 0F 4F 00 73 10 1F 34 7 | 73 2F 20 34 23 A0 E0 01 23 A2 20 00 23 A4 00 00 8 | 93 80 C0 00 73 00 20 30 17 15 00 00 13 05 85 FA 9 | 97 15 00 00 93 85 05 FB 37 C6 00 00 63 0E B5 04 10 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 11 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 12 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 14 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 15 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 16 | 6F F0 1F F3 73 10 00 C0 00 00 00 00 00 00 00 00 17 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 18 | @00001000 19 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 20 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 21 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 22 | -------------------------------------------------------------------------------- /verilator/images/I-ENDIANESS-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-ENDIANESS-01.bin -------------------------------------------------------------------------------- /verilator/images/I-ENDIANESS-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 17 18 00 00 13 08 C8 FE 4 | 97 18 00 00 93 88 08 00 83 20 08 00 03 51 08 00 5 | 83 51 28 00 03 42 F8 FF 83 42 08 00 03 43 18 00 6 | 83 43 28 00 03 44 38 00 23 A0 18 00 23 A2 28 00 7 | 23 A4 38 00 23 A6 48 00 23 A8 58 00 23 AA 68 00 8 | 23 AC 78 00 23 AE 88 00 17 15 00 00 13 05 85 FB 9 | 97 15 00 00 93 85 05 FD 37 C6 00 00 63 0E B5 04 10 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 11 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 12 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 14 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 15 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 16 | 6F F0 1F F3 73 10 00 C0 00 00 00 00 00 00 00 00 17 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 18 | @00001000 19 | EF CD AB 89 67 45 23 01 00 00 00 00 00 00 00 00 20 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 21 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 22 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 23 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 24 | -------------------------------------------------------------------------------- /verilator/images/I-FENCE.I-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-FENCE.I-01.bin -------------------------------------------------------------------------------- /verilator/images/I-FENCE.I-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 17 18 00 00 13 08 C8 FE 4 | 97 18 00 00 93 88 08 00 93 01 00 00 83 20 08 00 5 | 03 21 48 00 17 1A 00 00 13 0A CA FC 97 0A 00 00 6 | 93 8A 4A 01 83 27 0A 00 23 A0 FA 00 0F 10 00 00 7 | 37 01 00 00 23 A0 18 00 23 A2 28 00 23 A4 38 00 8 | 23 A6 F8 00 17 15 00 00 13 05 C5 FB 97 15 00 00 9 | 93 85 45 FC 37 C6 00 00 63 0E B5 04 93 06 05 01 10 | 93 86 F6 FF 03 87 06 00 93 57 47 40 93 F7 F7 00 11 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 12 | 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 08 A0 00 13 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 14 | E3 10 D5 FC 13 05 05 01 13 07 A0 00 23 00 E6 00 15 | 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 6F F0 5F F3 16 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 17 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 18 | @00001000 19 | B3 01 11 00 30 00 00 00 12 00 00 00 00 00 00 00 20 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 21 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 22 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 23 | -------------------------------------------------------------------------------- /verilator/images/I-IO-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-IO-01.bin -------------------------------------------------------------------------------- /verilator/images/I-JAL-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-JAL-01.bin -------------------------------------------------------------------------------- /verilator/images/I-JAL-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 00 4 | 37 51 34 12 13 01 81 67 6F 00 80 00 13 01 00 00 5 | 23 A0 00 00 23 A2 20 00 97 10 00 00 93 80 00 FF 6 | 13 01 F0 FF 93 01 F0 FF 37 D2 ED 0F 13 02 92 BA 7 | 6F 00 80 02 13 01 00 00 93 01 00 00 13 02 00 00 8 | B7 41 65 87 93 81 11 32 6F 00 80 02 13 01 00 00 9 | 93 01 00 00 13 02 00 00 37 E1 BC 9A 13 01 01 EF 10 | 6F F0 1F FE 13 01 00 00 93 01 00 00 13 02 00 00 11 | 23 A0 00 00 23 A2 20 00 23 A4 30 00 23 A6 40 00 12 | 97 14 00 00 93 84 04 F6 17 15 00 00 13 05 05 F9 13 | 13 01 F0 FF 93 01 F0 FF 13 02 F0 FF 93 02 F0 FF 14 | 37 53 55 55 13 03 53 55 83 AC 04 00 03 AC 44 00 15 | EF 00 C0 01 B7 21 22 22 93 81 21 22 EF 0F 00 03 16 | B7 42 44 44 93 82 42 44 6F 00 40 04 37 11 11 11 17 | 13 01 11 11 67 80 00 00 13 01 00 00 93 01 00 00 18 | 13 02 00 00 93 02 00 00 13 03 00 00 37 32 33 33 19 | 13 02 32 33 67 80 0F 00 13 01 00 00 93 01 00 00 20 | 13 02 00 00 93 02 00 00 13 03 00 00 B3 C3 90 01 21 | 33 C4 8F 01 23 20 25 00 23 22 35 00 23 24 45 00 22 | 23 26 55 00 23 28 65 00 23 2A 75 00 23 2C 85 00 23 | 97 14 00 00 93 84 84 EB 17 15 00 00 13 05 C5 EF 24 | 13 01 F0 FF 93 01 F0 FF 13 02 F0 FF 93 02 F0 FF 25 | 13 03 F0 FF 03 AC 04 00 83 AC 44 00 6F 00 40 02 26 | B7 71 77 77 93 81 71 77 67 80 0F 00 13 01 00 00 27 | 93 01 00 00 13 02 00 00 93 02 00 00 13 03 00 00 28 | 37 61 66 66 13 01 61 66 EF FF 9F FD 37 92 88 88 29 | 13 02 82 88 EF 00 00 01 37 B3 AA AA 13 03 A3 AA 30 | 6F 00 40 02 B7 A2 99 99 93 82 92 99 67 80 00 00 31 | 13 01 00 00 93 01 00 00 13 02 00 00 93 02 00 00 32 | 13 03 00 00 B3 C3 8F 01 33 C4 90 01 23 20 25 00 33 | 23 22 35 00 23 24 45 00 23 26 55 00 23 28 65 00 34 | 23 2A 75 00 23 2C 85 00 17 15 00 00 13 05 85 E1 35 | 97 15 00 00 93 85 05 E6 37 C6 00 00 63 0E B5 04 36 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 37 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 38 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 39 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 40 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 41 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 42 | 6F F0 1F D9 73 10 00 C0 00 00 00 00 00 00 00 00 43 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 44 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 45 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 | @00001000 47 | D4 00 00 00 E0 00 00 00 AC 01 00 00 B8 01 00 00 48 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 55 | -------------------------------------------------------------------------------- /verilator/images/I-JALR-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-JALR-01.bin -------------------------------------------------------------------------------- /verilator/images/I-LB-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-LB-01.bin -------------------------------------------------------------------------------- /verilator/images/I-LB-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 1F 00 00 93 8F 8F FE 4 | 17 11 00 00 13 01 01 03 83 81 0F 00 03 82 1F 00 5 | 83 82 2F 00 03 83 3F 00 23 20 31 00 23 22 41 00 6 | 23 24 51 00 23 26 61 00 17 1C 00 00 13 0C DC FB 7 | 97 12 00 00 93 82 02 01 83 0C FC FF 03 0D 0C 00 8 | 83 0D 1C 00 03 0E 2C 00 23 A0 92 01 23 A2 A2 01 9 | 23 A4 B2 01 23 A6 C2 01 97 13 00 00 93 83 F3 F8 10 | 17 14 00 00 13 04 04 FF 03 8F 13 00 83 8F 23 00 11 | 83 80 33 00 03 81 43 00 23 20 E4 01 23 22 F4 01 12 | 23 24 14 00 23 26 24 00 17 15 00 00 13 05 45 76 13 | 97 15 00 00 93 85 05 FD 03 06 05 80 83 06 15 80 14 | 03 07 25 80 83 07 35 80 23 A0 C5 00 23 A2 D5 00 15 | 23 A4 E5 00 23 A6 F5 00 97 06 00 00 93 86 C6 73 16 | 17 17 00 00 13 07 07 FB 83 87 C6 7F 03 88 D6 7F 17 | 83 88 E6 7F 03 89 F6 7F 23 20 F7 00 23 22 07 01 18 | 23 24 17 01 23 26 27 01 17 18 00 00 13 08 08 F1 19 | 97 18 00 00 93 88 08 F9 03 09 C8 FF 83 09 D8 FF 20 | 03 0A E8 FF 83 0A F8 FF 03 0B 08 00 83 0B 18 00 21 | 03 0C 28 00 83 0C 38 00 03 0D 48 00 83 0D 58 00 22 | 03 0E 68 00 83 0E 78 00 23 A0 28 01 23 A2 38 01 23 | 23 A4 48 01 23 A6 58 01 23 A8 68 01 23 AA 78 01 24 | 23 AC 88 01 23 AE 98 01 23 A0 A8 03 23 A2 B8 03 25 | 23 A4 C8 03 23 A6 D8 03 97 1A 00 00 93 8A 8A EA 26 | 17 1B 00 00 13 0B 0B F5 03 80 0A 00 23 20 0B 00 27 | 97 1A 00 00 93 8A 4A E9 17 1B 00 00 13 0B CB F3 28 | 83 AB 0A 00 03 8C 0B 00 93 0C 0C 00 23 20 9B 01 29 | 97 1C 00 00 93 8C CC E7 17 1D 00 00 13 0D 0D F2 30 | 83 8C 0C 00 23 20 9D 01 97 1D 00 00 93 8D 9D E6 31 | 17 1E 00 00 13 0E CE F0 83 8D FD FF 23 20 BE 01 32 | 17 15 00 00 13 05 05 E7 97 15 00 00 93 85 85 EF 33 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 34 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 35 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 36 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 37 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 38 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 39 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DB 73 10 00 C0 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | @00001000 43 | 22 F2 F1 11 F4 44 33 F3 66 F6 F5 55 F8 88 77 F7 44 | AA 0A 09 99 0C CC BB 0B EE 0E 0D DD F0 00 FF 0F 45 | 78 56 34 12 28 10 00 00 F0 DE BC 9A 10 32 54 76 46 | 98 BA DC FE 00 00 00 00 00 00 00 00 00 00 00 00 47 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 57 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 58 | -------------------------------------------------------------------------------- /verilator/images/I-LBU-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-LBU-01.bin -------------------------------------------------------------------------------- /verilator/images/I-LBU-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 1F 00 00 93 8F 8F FE 4 | 17 11 00 00 13 01 01 03 83 C1 0F 00 03 C2 1F 00 5 | 83 C2 2F 00 03 C3 3F 00 23 20 31 00 23 22 41 00 6 | 23 24 51 00 23 26 61 00 17 1C 00 00 13 0C DC FB 7 | 97 12 00 00 93 82 02 01 83 4C FC FF 03 4D 0C 00 8 | 83 4D 1C 00 03 4E 2C 00 23 A0 92 01 23 A2 A2 01 9 | 23 A4 B2 01 23 A6 C2 01 97 13 00 00 93 83 F3 F8 10 | 17 14 00 00 13 04 04 FF 03 CF 13 00 83 CF 23 00 11 | 83 C0 33 00 03 C1 43 00 23 20 E4 01 23 22 F4 01 12 | 23 24 14 00 23 26 24 00 17 15 00 00 13 05 45 76 13 | 97 15 00 00 93 85 05 FD 03 46 05 80 83 46 15 80 14 | 03 47 25 80 83 47 35 80 23 A0 C5 00 23 A2 D5 00 15 | 23 A4 E5 00 23 A6 F5 00 97 06 00 00 93 86 C6 73 16 | 17 17 00 00 13 07 07 FB 83 C7 C6 7F 03 C8 D6 7F 17 | 83 C8 E6 7F 03 C9 F6 7F 23 20 F7 00 23 22 07 01 18 | 23 24 17 01 23 26 27 01 17 18 00 00 13 08 08 F1 19 | 97 18 00 00 93 88 08 F9 03 49 C8 FF 83 49 D8 FF 20 | 03 4A E8 FF 83 4A F8 FF 03 4B 08 00 83 4B 18 00 21 | 03 4C 28 00 83 4C 38 00 03 4D 48 00 83 4D 58 00 22 | 03 4E 68 00 83 4E 78 00 23 A0 28 01 23 A2 38 01 23 | 23 A4 48 01 23 A6 58 01 23 A8 68 01 23 AA 78 01 24 | 23 AC 88 01 23 AE 98 01 23 A0 A8 03 23 A2 B8 03 25 | 23 A4 C8 03 23 A6 D8 03 97 1A 00 00 93 8A 8A EA 26 | 17 1B 00 00 13 0B 0B F5 03 C0 0A 00 23 20 0B 00 27 | 97 1A 00 00 93 8A 4A E9 17 1B 00 00 13 0B CB F3 28 | 83 AB 0A 00 03 CC 0B 00 93 0C 0C 00 23 20 9B 01 29 | 97 1C 00 00 93 8C CC E7 17 1D 00 00 13 0D 0D F2 30 | 83 CC 0C 00 23 20 9D 01 97 1D 00 00 93 8D 9D E6 31 | 17 1E 00 00 13 0E CE F0 83 CD FD FF 23 20 BE 01 32 | 17 15 00 00 13 05 05 E7 97 15 00 00 93 85 85 EF 33 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 34 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 35 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 36 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 37 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 38 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 39 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DB 73 10 00 C0 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | @00001000 43 | 22 F2 F1 11 F4 44 33 F3 66 F6 F5 55 F8 88 77 F7 44 | AA 0A 09 99 0C CC BB 0B EE 0E 0D DD F0 00 FF 0F 45 | 78 56 34 12 28 10 00 00 F0 DE BC 9A 10 32 54 76 46 | 98 BA DC FE 00 00 00 00 00 00 00 00 00 00 00 00 47 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 57 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 58 | -------------------------------------------------------------------------------- /verilator/images/I-LH-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-LH-01.bin -------------------------------------------------------------------------------- /verilator/images/I-LH-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 1F 00 00 93 8F 8F FE 4 | 17 11 00 00 13 01 01 03 83 91 0F 00 03 92 2F 00 5 | 23 20 31 00 23 22 41 00 17 1C 00 00 13 0C DC FC 6 | 97 12 00 00 93 82 82 01 83 1C FC FF 03 1D 1C 00 7 | 23 A0 92 01 23 A2 A2 01 97 13 00 00 93 83 F3 FA 8 | 17 14 00 00 13 04 04 00 03 9F 13 00 83 9F 33 00 9 | 23 20 E4 01 23 22 F4 01 17 15 00 00 13 05 45 79 10 | 97 15 00 00 93 85 85 FE 03 16 05 80 83 16 25 80 11 | 23 A0 C5 00 23 A2 D5 00 97 06 00 00 93 86 B6 77 12 | 17 17 00 00 13 07 07 FD 83 97 D6 7F 03 98 F6 7F 13 | 23 20 F7 00 23 22 07 01 17 18 00 00 13 08 08 F6 14 | 97 18 00 00 93 88 88 FB 03 19 C8 FF 83 19 E8 FF 15 | 03 1A 08 00 83 1A 28 00 03 1B 48 00 83 1B 68 00 16 | 23 A0 28 01 23 A2 38 01 23 A4 48 01 23 A6 58 01 17 | 23 A8 68 01 23 AA 78 01 97 1A 00 00 93 8A 8A F2 18 | 17 1B 00 00 13 0B 0B F9 03 90 0A 00 23 20 0B 00 19 | 97 1A 00 00 93 8A 4A F1 17 1B 00 00 13 0B CB F7 20 | 83 AB 0A 00 03 9C 0B 00 93 0C 0C 00 23 20 9B 01 21 | 97 1C 00 00 93 8C CC EF 17 1D 00 00 13 0D 0D F6 22 | 83 9C 0C 00 23 20 9D 01 97 1D 00 00 93 8D 9D EE 23 | 17 1E 00 00 13 0E CE F4 83 9D FD FF 23 20 BE 01 24 | 17 15 00 00 13 05 05 EF 97 15 00 00 93 85 85 F3 25 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 26 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 27 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 28 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 29 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 30 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 31 | 13 07 F0 0F 23 00 E6 00 6F F0 9F E3 73 10 00 C0 32 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 33 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 34 | @00001000 35 | 22 F2 F1 11 F4 44 33 F3 66 F6 F5 55 F8 88 77 F7 36 | AA 0A 09 99 0C CC BB 0B EE 0E 0D DD F0 00 FF 0F 37 | 78 56 34 12 28 10 00 00 F0 DE BC 9A 10 32 54 76 38 | 98 BA DC FE 00 00 00 00 00 00 00 00 00 00 00 00 39 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 40 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 41 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 42 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 43 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 44 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 45 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 46 | -------------------------------------------------------------------------------- /verilator/images/I-LHU-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-LHU-01.bin -------------------------------------------------------------------------------- /verilator/images/I-LHU-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 1F 00 00 93 8F 8F FE 4 | 17 11 00 00 13 01 01 03 83 D1 0F 00 03 D2 2F 00 5 | 23 20 31 00 23 22 41 00 17 1C 00 00 13 0C DC FC 6 | 97 12 00 00 93 82 82 01 83 5C FC FF 03 5D 1C 00 7 | 23 A0 92 01 23 A2 A2 01 97 13 00 00 93 83 F3 FA 8 | 17 14 00 00 13 04 04 00 03 DF 13 00 83 DF 33 00 9 | 23 20 E4 01 23 22 F4 01 17 15 00 00 13 05 45 79 10 | 97 15 00 00 93 85 85 FE 03 56 05 80 83 56 25 80 11 | 23 A0 C5 00 23 A2 D5 00 97 06 00 00 93 86 B6 77 12 | 17 17 00 00 13 07 07 FD 83 D7 D6 7F 03 D8 F6 7F 13 | 23 20 F7 00 23 22 07 01 17 18 00 00 13 08 08 F6 14 | 97 18 00 00 93 88 88 FB 03 59 C8 FF 83 59 E8 FF 15 | 03 5A 08 00 83 5A 28 00 03 5B 48 00 83 5B 68 00 16 | 23 A0 28 01 23 A2 38 01 23 A4 48 01 23 A6 58 01 17 | 23 A8 68 01 23 AA 78 01 97 1A 00 00 93 8A 8A F2 18 | 17 1B 00 00 13 0B 0B F9 03 D0 0A 00 23 20 0B 00 19 | 97 1A 00 00 93 8A 4A F1 17 1B 00 00 13 0B CB F7 20 | 83 AB 0A 00 03 DC 0B 00 93 0C 0C 00 23 20 9B 01 21 | 97 1C 00 00 93 8C CC EF 17 1D 00 00 13 0D 0D F6 22 | 83 DC 0C 00 23 20 9D 01 97 1D 00 00 93 8D 9D EE 23 | 17 1E 00 00 13 0E CE F4 83 DD FD FF 23 20 BE 01 24 | 17 15 00 00 13 05 05 EF 97 15 00 00 93 85 85 F3 25 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 26 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 27 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 28 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 29 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 30 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 31 | 13 07 F0 0F 23 00 E6 00 6F F0 9F E3 73 10 00 C0 32 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 33 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 34 | @00001000 35 | 22 F2 F1 11 F4 44 33 F3 66 F6 F5 55 F8 88 77 F7 36 | AA 0A 09 99 0C CC BB 0B EE 0E 0D DD F0 00 FF 0F 37 | 78 56 34 12 28 10 00 00 F0 DE BC 9A 10 32 54 76 38 | 98 BA DC FE 00 00 00 00 00 00 00 00 00 00 00 00 39 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 40 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 41 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 42 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 43 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 44 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 45 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 46 | -------------------------------------------------------------------------------- /verilator/images/I-LUI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-LUI-01.bin -------------------------------------------------------------------------------- /verilator/images/I-LUI-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 17 00 00 93 87 87 00 4 | B7 00 00 00 B7 11 00 00 B7 F2 FF FF B7 FE FF 7F 5 | B7 0F 00 80 23 A0 17 00 23 A2 37 00 23 A4 57 00 6 | 23 A6 D7 01 23 A8 F7 01 97 17 00 00 93 87 87 FB 7 | 17 18 00 00 13 08 48 FE 03 A1 07 00 03 A2 07 00 8 | 03 A3 07 00 03 AE 07 00 03 AF 07 00 37 01 00 80 9 | 37 F2 FF 7F 37 03 00 00 37 1E 00 00 37 FF FF FF 10 | 23 20 28 00 23 22 48 00 23 24 68 00 23 26 C8 01 11 | 23 28 E8 01 97 18 00 00 93 88 48 FB B7 70 72 42 12 | 93 80 F0 E6 B7 57 34 12 93 87 87 67 37 EF BC 9A 13 | 13 0F 0F EF 37 71 72 42 13 01 F1 E6 37 58 34 12 14 | 13 08 88 67 B7 EF BC 9A 93 8F 0F EF 23 A0 18 00 15 | 23 A2 F8 00 23 A4 E8 01 23 A6 28 00 23 A8 08 01 16 | 23 AA F8 01 17 15 00 00 13 05 C5 F3 97 15 00 00 17 | 93 85 45 F7 37 C6 00 00 63 0E B5 04 93 06 05 01 18 | 93 86 F6 FF 03 87 06 00 93 57 47 40 93 F7 F7 00 19 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 20 | 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 08 A0 00 21 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 22 | E3 10 D5 FC 13 05 05 01 13 07 A0 00 23 00 E6 00 23 | 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 6F F0 5F EB 24 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 25 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26 | @00001000 27 | 11 11 11 11 00 00 00 00 00 00 00 00 00 00 00 00 28 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 29 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 30 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 31 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 32 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 33 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 34 | -------------------------------------------------------------------------------- /verilator/images/I-LW-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-LW-01.bin -------------------------------------------------------------------------------- /verilator/images/I-LW-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 1F 00 00 93 8F 8F FE 4 | 17 11 00 00 13 01 01 03 83 A1 0F 00 23 20 31 00 5 | 17 1C 00 00 13 0C 5C FD 97 12 00 00 93 82 C2 01 6 | 83 2C FC FF 23 A0 92 01 97 13 00 00 93 83 F3 FB 7 | 17 14 00 00 13 04 84 00 83 AF 13 00 23 20 F4 01 8 | 17 15 00 00 13 05 C5 7A 97 15 00 00 93 85 45 FF 9 | 03 26 05 80 23 A0 C5 00 97 06 00 00 93 86 96 79 10 | 17 17 00 00 13 07 07 FE 83 A7 F6 7F 23 20 F7 00 11 | 17 18 00 00 13 08 88 F8 97 18 00 00 93 88 C8 FC 12 | 03 29 C8 FF 83 29 08 00 03 2A 48 00 23 A0 28 01 13 | 23 A2 38 01 23 A4 48 01 97 1A 00 00 93 8A 8A F6 14 | 17 1B 00 00 13 0B 0B FB 03 A0 0A 00 23 20 0B 00 15 | 97 1A 00 00 93 8A 4A F5 17 1B 00 00 13 0B CB F9 16 | 83 AB 0A 00 03 AC 0B 00 93 0C 0C 00 23 20 9B 01 17 | 97 1C 00 00 93 8C CC F3 17 1D 00 00 13 0D 0D F8 18 | 83 AC 0C 00 23 20 9D 01 97 1D 00 00 93 8D 9D F2 19 | 17 1E 00 00 13 0E CE F6 83 AD FD FF 23 20 BE 01 20 | 17 15 00 00 13 05 05 F3 97 15 00 00 93 85 85 F5 21 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 22 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 23 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 24 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 25 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 26 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 27 | 13 07 F0 0F 23 00 E6 00 6F F0 9F E7 73 10 00 C0 28 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 | @00001000 31 | 22 F2 F1 11 F4 44 33 F3 66 F6 F5 55 F8 88 77 F7 32 | AA 0A 09 99 0C CC BB 0B EE 0E 0D DD F0 00 FF 0F 33 | 78 56 34 12 28 10 00 00 F0 DE BC 9A 10 32 54 76 34 | 98 BA DC FE 00 00 00 00 00 00 00 00 00 00 00 00 35 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 36 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 37 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 38 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 39 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 40 | -------------------------------------------------------------------------------- /verilator/images/I-MISALIGN_JMP-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-MISALIGN_JMP-01.bin -------------------------------------------------------------------------------- /verilator/images/I-MISALIGN_JMP-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 00 00 00 93 80 80 20 4 | F3 9F 50 30 73 70 12 30 97 10 00 00 93 80 80 FE 5 | 37 11 11 11 13 01 11 11 6F 00 A0 00 13 01 00 00 6 | 97 10 00 00 93 80 C0 FD 37 21 22 22 13 01 21 22 7 | 17 02 00 00 13 02 12 01 67 00 02 00 13 01 00 00 8 | 23 A0 20 00 93 80 40 00 37 31 33 33 13 01 31 33 9 | 17 02 00 00 13 02 02 01 67 00 12 00 13 01 00 00 10 | 23 A0 20 00 93 80 40 00 37 41 44 44 13 01 41 44 11 | 17 02 00 00 13 02 42 01 67 00 D2 FF 13 01 00 00 12 | 23 A0 20 00 93 80 40 00 97 10 00 00 93 80 00 F8 13 | 37 51 55 55 13 01 51 55 17 02 00 00 13 02 22 01 14 | 67 00 02 00 13 01 00 00 37 61 66 66 13 01 61 66 15 | 17 02 00 00 13 02 32 01 67 00 02 00 13 01 00 00 16 | 37 71 77 77 13 01 71 77 17 02 00 00 13 02 02 01 17 | 67 00 22 00 13 01 00 00 37 91 88 88 13 01 81 88 18 | 17 02 00 00 13 02 02 01 67 00 32 00 13 01 00 00 19 | 97 10 00 00 93 80 80 F4 93 02 50 00 13 03 60 00 20 | 63 87 62 00 37 A1 99 99 13 01 91 99 13 00 00 00 21 | 13 00 00 00 63 85 52 00 13 01 00 00 97 10 00 00 22 | 93 80 80 F2 93 02 50 00 13 03 60 00 63 97 52 00 23 | 37 B1 AA AA 13 01 A1 AA 13 00 00 00 13 00 00 00 24 | 63 95 62 00 13 01 00 00 97 10 00 00 93 80 80 F0 25 | 93 02 50 00 13 03 60 00 63 47 53 00 37 C1 BB BB 26 | 13 01 B1 BB 13 00 00 00 13 00 00 00 63 C5 62 00 27 | 13 01 00 00 97 10 00 00 93 80 80 EE 93 02 50 00 28 | 13 03 60 00 63 67 53 00 37 D1 CC CC 13 01 C1 CC 29 | 13 00 00 00 13 00 00 00 63 E5 62 00 13 01 00 00 30 | 97 10 00 00 93 80 80 EC 93 02 50 00 13 03 60 00 31 | 63 D7 62 00 37 E1 DD DD 13 01 D1 DD 13 00 00 00 32 | 13 00 00 00 63 55 53 00 13 01 00 00 97 10 00 00 33 | 93 80 80 EA 93 02 50 00 13 03 60 00 63 F7 62 00 34 | 37 F1 EE EE 13 01 E1 EE 13 00 00 00 13 00 00 00 35 | 63 75 53 00 13 01 00 00 73 90 5F 30 6F 00 00 03 36 | 73 2F 30 34 13 0F EF FF 73 10 1F 34 73 2F 30 34 37 | 13 7F 3F 00 23 A0 E0 01 73 2F 20 34 23 A2 E0 01 38 | 23 A4 20 00 93 80 C0 00 73 00 20 30 17 15 00 00 39 | 13 05 45 DC 97 15 00 00 93 85 C5 E4 37 C6 00 00 40 | 63 0E B5 04 93 06 05 01 93 86 F6 FF 03 87 06 00 41 | 93 57 47 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 42 | 93 87 77 02 93 87 07 03 23 00 F6 00 93 57 07 40 43 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 44 | 93 87 07 03 23 00 F6 00 E3 10 D5 FC 13 05 05 01 45 | 13 07 A0 00 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 46 | 23 00 E6 00 6F F0 DF D4 73 10 00 C0 00 00 00 00 47 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 48 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 49 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 | @00001000 51 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 57 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 58 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 59 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 60 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 61 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 62 | -------------------------------------------------------------------------------- /verilator/images/I-MISALIGN_LDST-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-MISALIGN_LDST-01.bin -------------------------------------------------------------------------------- /verilator/images/I-MISALIGN_LDST-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 00 00 00 93 80 40 14 4 | F3 9F 50 30 97 11 00 00 93 81 C1 FD 17 11 00 00 5 | 13 01 41 FF 97 10 00 00 93 80 C0 FF 93 02 50 00 6 | 13 03 60 00 03 A2 01 00 23 20 41 00 03 A2 11 00 7 | 23 22 41 00 03 A2 21 00 23 24 41 00 03 A2 31 00 8 | 23 26 41 00 97 11 00 00 93 81 01 FA 17 11 00 00 9 | 13 01 C1 FD 97 10 00 00 93 80 40 FF 93 02 50 00 10 | 13 03 60 00 03 92 01 00 23 20 41 00 03 92 11 00 11 | 23 22 41 00 03 92 21 00 23 24 41 00 03 92 31 00 12 | 23 26 41 00 03 D2 01 00 23 28 41 00 03 D2 11 00 13 | 23 2A 41 00 03 D2 21 00 23 2C 41 00 03 D2 31 00 14 | 23 2E 41 00 17 11 00 00 13 01 41 FC 97 10 00 00 15 | 93 80 C0 FC 13 03 00 00 B7 A2 99 99 93 82 92 99 16 | 23 20 51 00 23 22 51 00 23 24 51 00 23 26 51 00 17 | 23 20 61 00 13 01 41 00 A3 20 61 00 13 01 41 00 18 | 23 21 61 00 13 01 41 00 A3 21 61 00 17 11 00 00 19 | 13 01 41 FA 97 10 00 00 93 80 C0 FA 13 03 00 00 20 | B7 A2 99 99 93 82 92 99 23 20 51 00 23 22 51 00 21 | 23 24 51 00 23 26 51 00 23 10 61 00 13 01 41 00 22 | A3 10 61 00 13 01 41 00 23 11 61 00 13 01 41 00 23 | A3 11 61 00 73 90 5F 30 6F 00 C0 02 73 2F 10 34 24 | 13 0F 4F 00 73 10 1F 34 73 2F 30 34 13 7F 3F 00 25 | 23 A0 E0 01 73 2F 20 34 23 A2 E0 01 93 80 80 00 26 | 73 00 20 30 17 15 00 00 13 05 C5 E9 97 15 00 00 27 | 93 85 45 F4 37 C6 00 00 63 0E B5 04 93 06 05 01 28 | 93 86 F6 FF 03 87 06 00 93 57 47 40 93 F7 F7 00 29 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 30 | 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 08 A0 00 31 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 32 | E3 10 D5 FC 13 05 05 01 13 07 A0 00 23 00 E6 00 33 | 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 6F F0 5F E1 34 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 35 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 36 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 37 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 38 | @00001000 39 | C1 B1 A1 91 02 F2 E2 D2 00 00 00 00 00 00 00 00 40 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 41 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 42 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 43 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 44 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 45 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 46 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 47 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 53 | -------------------------------------------------------------------------------- /verilator/images/I-NOP-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-NOP-01.bin -------------------------------------------------------------------------------- /verilator/images/I-NOP-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 FF 4 | 13 01 20 00 93 01 30 00 13 02 40 00 93 02 50 00 5 | 13 03 60 00 93 03 70 00 13 04 80 00 93 04 90 00 6 | 13 05 A0 00 93 05 B0 00 13 06 C0 00 93 06 D0 00 7 | 13 07 E0 00 93 07 F0 00 13 08 00 01 93 08 10 01 8 | 13 09 20 01 93 09 30 01 13 0A 40 01 93 0A 50 01 9 | 13 0B 60 01 93 0B 70 01 13 0C 80 01 93 0C 90 01 10 | 13 0D A0 01 93 0D B0 01 13 0E C0 01 93 0E D0 01 11 | 13 0F E0 01 93 0F F0 01 13 00 00 00 13 00 00 00 12 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 | 23 A0 00 00 23 A2 20 00 23 A4 30 00 23 A6 40 00 14 | 23 A8 50 00 23 AA 60 00 23 AC 70 00 23 AE 80 00 15 | 23 A0 90 02 23 A2 A0 02 23 A4 B0 02 23 A6 C0 02 16 | 23 A8 D0 02 23 AA E0 02 23 AC F0 02 23 AE 00 03 17 | 23 A0 10 05 23 A2 20 05 23 A4 30 05 23 A6 40 05 18 | 23 A8 50 05 23 AA 60 05 23 AC 70 05 23 AE 80 05 19 | 23 A0 90 07 23 A2 A0 07 23 A4 B0 07 23 A6 C0 07 20 | 23 A8 D0 07 23 AA E0 07 23 AC F0 07 97 11 00 00 21 | 93 81 01 F6 17 04 00 00 13 00 00 00 13 00 00 00 22 | 13 00 00 00 13 00 00 00 13 00 00 00 97 04 00 00 23 | B3 84 84 40 23 A0 91 00 17 15 00 00 13 05 85 EB 24 | 97 15 00 00 93 85 05 F3 37 C6 00 00 63 0E B5 04 25 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 26 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 27 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 28 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 29 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 30 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 31 | 6F F0 1F E4 73 10 00 C0 00 00 00 00 00 00 00 00 32 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 33 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 34 | @00001000 35 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 36 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 37 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 38 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 39 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 40 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 41 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 42 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 43 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 44 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 45 | 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-------------------------------------------------------------------------------- /verilator/images/I-RF_size-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 17 18 00 00 13 08 88 FF 4 | 37 70 72 42 13 00 F0 E6 B7 30 33 56 93 80 90 24 5 | 37 21 56 2D 13 01 21 05 B7 71 69 52 93 81 31 36 6 | 37 82 6B 73 13 02 02 92 B7 62 74 73 93 82 22 57 7 | 37 53 20 6E 13 03 F3 E6 B7 73 69 4D 93 83 13 C6 8 | 37 64 64 6F 13 04 34 17 B7 44 79 6B 93 84 34 06 9 | 37 75 65 74 13 05 35 27 B7 75 6E 28 93 85 35 F7 10 | 37 26 6B 65 13 06 86 04 B7 66 52 20 93 86 46 16 11 | 37 37 6D 6F 13 07 C7 92 B7 37 70 69 93 87 37 E6 12 | 23 20 08 00 23 22 18 00 23 24 28 00 23 26 38 00 13 | 23 28 48 00 23 2A 58 00 23 2C 68 00 23 2E 78 00 14 | 23 20 88 02 23 22 98 02 23 24 A8 02 23 26 B8 02 15 | 23 28 C8 02 23 2A D8 02 23 2C E8 02 23 2E F8 02 16 | 17 12 00 00 13 02 02 F7 37 68 6F 63 13 08 18 46 17 | B7 78 65 6A 93 88 08 B4 37 79 28 20 13 09 19 86 18 | B7 69 6A 61 93 89 B9 56 37 6A 76 61 13 0A 0A 52 19 | B7 5A 20 2E 93 8A 5A C6 37 7B 6F 63 13 0B 9B D2 20 | B7 7B 69 73 93 8B EB 02 37 8C 20 66 13 0C FC 96 21 | B7 2C 65 67 93 8C 9C 06 37 7D 73 65 13 0D 1D 36 22 | B7 2D 73 75 93 8D DD 06 37 1E 29 3A 13 0E AE D0 23 | B7 7E 69 68 93 8E 0E 32 37 2F 64 61 13 0F 4F 07 24 | B7 7F 20 75 93 8F 5F 26 23 20 02 01 23 22 12 01 25 | 23 24 22 01 23 26 32 01 23 28 42 01 23 2A 52 01 26 | 23 2C 62 01 23 2E 72 01 23 20 82 03 23 22 92 03 27 | 23 24 A2 03 23 26 B2 03 23 28 C2 03 23 2A D2 03 28 | 23 2C E2 03 23 2E F2 03 17 12 00 00 13 02 82 EE 29 | 23 20 02 00 23 22 12 00 23 24 22 00 23 26 32 00 30 | 17 15 00 00 13 05 05 E5 97 15 00 00 93 85 85 ED 31 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 32 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 33 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 34 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 35 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 36 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 37 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DD 73 10 00 C0 38 | @00001000 39 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 40 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 41 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 42 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 43 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 44 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 45 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 46 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 47 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 50 | -------------------------------------------------------------------------------- /verilator/images/I-RF_width-01.bin: -------------------------------------------------------------------------------- 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00 13 04 80 01 17 E0 CD AB 9 | 33 00 10 00 33 60 20 00 33 70 30 00 33 40 40 00 10 | 33 10 50 00 33 50 60 40 33 50 70 00 33 00 80 40 11 | 23 A0 0F 00 97 1F 00 00 93 8F 4F F9 93 00 10 00 12 | 13 01 20 00 33 A0 20 00 23 A0 0F 00 33 B0 20 00 13 | 23 A2 0F 00 13 A0 20 00 23 A4 0F 00 13 B0 20 00 14 | 23 A6 0F 00 97 1F 00 00 93 8F 4F F7 6F 00 40 00 15 | 23 A0 0F 00 97 00 00 00 93 80 C0 00 67 80 00 00 16 | 23 A2 0F 00 97 10 00 00 93 80 C0 F1 97 1F 00 00 17 | 93 8F 4F F5 03 A0 00 00 23 A0 0F 00 03 90 00 00 18 | 23 A2 0F 00 03 80 00 00 23 A4 0F 00 03 C0 00 00 19 | 23 A6 0F 00 17 15 00 00 13 05 C5 F0 97 15 00 00 20 | 93 85 45 F3 37 C6 00 00 63 0E B5 04 93 06 05 01 21 | 93 86 F6 FF 03 87 06 00 93 57 47 40 93 F7 F7 00 22 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 23 | 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 08 A0 00 24 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 25 | E3 10 D5 FC 13 05 05 01 13 07 A0 00 23 00 E6 00 26 | 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 6F F0 5F E8 27 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 28 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 | @00001000 31 | 4F 4E 52 42 00 00 00 00 00 00 00 00 00 00 00 00 32 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 33 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 34 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 35 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 36 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 37 | -------------------------------------------------------------------------------- /verilator/images/I-SB-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SB-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SB-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 00 4 | B7 CF AA AA 93 8F BF BB 23 A0 F0 01 37 F1 F1 11 5 | 13 01 21 22 23 80 20 00 97 12 00 00 93 82 D2 FE 6 | A3 AF 02 FE B7 4C 33 F3 93 8C 4C 4F A3 8F 92 FF 7 | 17 14 00 00 13 04 74 FD A3 20 04 00 B7 FF F5 55 8 | 93 8F 6F 66 A3 00 F4 01 97 15 00 00 93 85 45 7C 9 | 23 A0 05 80 37 96 77 F7 13 06 86 8F 23 80 C5 80 10 | 17 07 00 00 13 07 17 7B A3 2F 07 7E B7 17 09 99 11 | 93 87 A7 AA A3 0F F7 7E 97 18 00 00 93 88 08 FA 12 | 37 19 11 11 13 09 C9 10 B7 29 22 22 93 89 C9 2C 13 | 37 3A 33 33 13 0A BA 3B B7 4A 44 44 93 8A BA 40 14 | 37 5B 55 55 13 0B EB 5E B7 6B 66 66 93 8B EB 60 15 | 37 7C 77 77 13 0C DC 70 B7 9C 88 88 93 8C DC 8D 16 | 37 AD 99 99 13 0D 0D 9F B7 BD AA AA 93 8D 0D A0 17 | 37 CE BB BB 13 0E FE BF B7 DE CC CC 93 8E FE C0 18 | 23 8E 28 FF A3 8E 38 FF 23 8F 48 FF A3 8F 58 FF 19 | 23 80 68 01 A3 80 78 01 23 81 88 01 A3 81 98 01 20 | 23 82 A8 01 A3 82 B8 01 23 83 C8 01 A3 83 D8 01 21 | 17 1B 00 00 13 0B 0B F1 B7 40 65 87 93 80 10 32 22 | 23 20 1B 00 37 50 34 12 13 00 80 67 23 00 0B 00 23 | 97 1A 00 00 93 8A 0A EB 83 A0 0A 00 23 A0 00 00 24 | B7 39 22 11 93 89 49 34 83 AB 0A 00 23 80 3B 01 25 | 97 1B 00 00 93 8B 4B E9 17 1C 00 00 13 0C 0C ED 26 | 23 20 0C 00 83 AC 0B 00 23 00 9C 01 17 1D 00 00 27 | 13 0D 0D EC 23 20 0D 00 B7 3C 54 76 93 8C 0C 21 28 | 23 00 9D 01 93 0C 00 00 17 1E 00 00 13 0E 8E EA 29 | 23 20 0E 00 B7 DD AB 89 93 8D FD DE 23 00 BE 01 30 | 13 0E CE FF 97 1E 00 00 93 8E 0E E9 23 A0 0E 00 31 | 23 A2 0E 00 B7 6D 72 14 93 8D 6D 83 23 80 BE 01 32 | 03 AF 0E 00 23 82 EE 01 97 10 00 00 93 80 40 E7 33 | 23 A0 00 00 37 51 38 96 13 01 11 20 B7 51 81 25 34 | 93 81 31 96 23 80 20 00 23 80 30 00 17 15 00 00 35 | 13 05 45 E1 97 15 00 00 93 85 C5 E4 37 C6 00 00 36 | 63 0E B5 04 93 06 05 01 93 86 F6 FF 03 87 06 00 37 | 93 57 47 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 38 | 93 87 77 02 93 87 07 03 23 00 F6 00 93 57 07 40 39 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 40 | 93 87 07 03 23 00 F6 00 E3 10 D5 FC 13 05 05 01 41 | 13 07 A0 00 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 42 | 23 00 E6 00 6F F0 DF D8 73 10 00 C0 00 00 00 00 43 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 44 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 45 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 | @00001000 47 | 44 10 00 00 F0 DE BC 9A 00 00 00 00 00 00 00 00 48 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 54 | -------------------------------------------------------------------------------- /verilator/images/I-SH-01.bin: -------------------------------------------------------------------------------- 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93 8B FB FF 15 | 23 9E 28 FF 23 9F 38 FF 23 90 48 01 23 91 58 01 16 | 23 92 68 01 23 93 78 01 17 1B 00 00 13 0B 8B F5 17 | B7 40 65 87 93 80 10 32 23 20 1B 00 37 50 34 12 18 | 13 00 80 67 23 10 0B 00 97 1A 00 00 93 8A 8A EF 19 | 83 A0 0A 00 23 A0 00 00 B7 39 22 11 93 89 49 34 20 | 83 AB 0A 00 23 90 3B 01 97 1B 00 00 93 8B CB ED 21 | 17 1C 00 00 13 0C 8C F1 23 20 0C 00 83 AC 0B 00 22 | 23 10 9C 01 17 1D 00 00 13 0D 8D F0 23 20 0D 00 23 | B7 3C 54 76 93 8C 0C 21 23 10 9D 01 93 0C 00 00 24 | 17 1E 00 00 13 0E 0E EF 23 20 0E 00 B7 DD AB 89 25 | 93 8D FD DE 23 10 BE 01 13 0E CE FF 97 1E 00 00 26 | 93 8E 8E ED 23 A0 0E 00 23 A2 0E 00 B7 6D 72 14 27 | 93 8D 6D 83 23 90 BE 01 03 AF 0E 00 23 92 EE 01 28 | 97 10 00 00 93 80 C0 EB 23 A0 00 00 37 51 38 96 29 | 13 01 11 20 B7 51 81 25 93 81 31 96 23 90 20 00 30 | 23 90 30 00 17 15 00 00 13 05 C5 E5 97 15 00 00 31 | 93 85 45 E9 37 C6 00 00 63 0E B5 04 93 06 05 01 32 | 93 86 F6 FF 03 87 06 00 93 57 47 40 93 F7 F7 00 33 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 34 | 23 00 F6 00 93 57 07 40 93 F7 F7 00 13 08 A0 00 35 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 36 | E3 10 D5 FC 13 05 05 01 13 07 A0 00 23 00 E6 00 37 | 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 6F F0 5F DD 38 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 39 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | @00001000 43 | 44 10 00 00 F0 DE BC 9A 00 00 00 00 00 00 00 00 44 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 45 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 46 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 47 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 50 | -------------------------------------------------------------------------------- /verilator/images/I-SLL-01.bin: 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23 28 71 00 23 2A 81 00 97 10 00 00 93 80 C0 FA 8 | 17 11 00 00 13 01 81 FE 03 A4 00 00 93 14 14 00 9 | 13 15 F4 00 93 15 F4 01 13 16 04 00 93 16 04 01 10 | 23 20 81 00 23 22 91 00 23 24 A1 00 23 26 B1 00 11 | 23 28 C1 00 23 2A D1 00 97 10 00 00 93 80 00 F7 12 | 17 11 00 00 13 01 01 FC 83 A6 00 00 13 97 16 00 13 | 93 97 F6 00 13 98 F6 01 93 98 06 00 13 99 06 01 14 | 23 20 D1 00 23 22 E1 00 23 24 F1 00 23 26 01 01 15 | 23 28 11 01 23 2A 21 01 17 16 00 00 13 06 46 F3 16 | 97 16 00 00 93 86 86 F9 03 29 06 00 93 19 19 00 17 | 13 1A F9 00 93 1A F9 01 13 1B 09 00 93 1B 09 01 18 | 23 A0 26 01 23 A2 36 01 23 A4 46 01 23 A6 56 01 19 | 23 A8 66 01 23 AA 76 01 17 16 00 00 13 06 86 EF 20 | 97 16 00 00 93 86 06 F7 83 2B 06 00 13 9C 1B 00 21 | 93 9C FB 00 13 9D FB 01 93 9D 0B 00 13 9E 0B 01 22 | 23 A0 76 01 23 A2 86 01 23 A4 96 01 23 A6 A6 01 23 | 23 A8 B6 01 23 AA C6 01 17 1D 00 00 13 0D CD EB 24 | 97 1D 00 00 93 8D 8D F4 03 2E 0D 00 93 1E 1E 00 25 | 13 9F 1E 00 93 1F 1F 00 93 90 1F 00 13 91 10 00 26 | 93 11 11 00 23 A0 CD 01 23 A2 DD 01 23 A4 ED 01 27 | 23 A6 FD 01 23 A8 1D 00 23 AA 2D 00 23 AC 3D 00 28 | 97 10 00 00 93 80 80 E7 17 11 00 00 13 01 C1 F1 29 | 83 A2 00 00 13 90 12 00 23 20 01 00 97 10 00 00 30 | 93 80 00 E6 17 11 00 00 13 01 41 F0 83 A2 00 00 31 | 13 90 12 00 93 12 10 00 23 20 01 00 23 22 51 00 32 | 17 15 00 00 13 05 05 E5 97 15 00 00 93 85 85 EE 33 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 34 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 35 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 36 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 37 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 38 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 39 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DB 73 10 00 C0 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | @00001000 43 | 00 00 00 00 01 00 00 00 FF FF FF FF FF FF FF 7F 44 | 00 00 00 80 10 EF CD AB 78 56 34 12 98 BA DC FE 45 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 46 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 47 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 57 | -------------------------------------------------------------------------------- /verilator/images/I-SLT-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SLT-01.bin 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11 | 23 28 C1 00 23 2A D1 00 97 10 00 00 93 80 00 F7 12 | 17 11 00 00 13 01 01 FC 83 A6 00 00 13 A7 16 00 13 | 93 A7 F6 7F 13 A8 F6 FF 93 A8 06 00 13 A9 06 80 14 | 23 20 D1 00 23 22 E1 00 23 24 F1 00 23 26 01 01 15 | 23 28 11 01 23 2A 21 01 97 10 00 00 93 80 40 F3 16 | 17 11 00 00 13 01 81 F9 03 A9 00 00 93 29 19 00 17 | 13 2A F9 7F 93 2A F9 FF 13 2B 09 00 93 2B 09 80 18 | 23 20 21 01 23 22 31 01 23 24 41 01 23 26 51 01 19 | 23 28 61 01 23 2A 71 01 97 10 00 00 93 80 80 EF 20 | 17 11 00 00 13 01 01 F7 83 AB 00 00 13 AC 1B 00 21 | 93 AC FB 7F 13 AD FB FF 93 AD 0B 00 13 AE 0B 80 22 | 23 20 71 01 23 22 81 01 23 24 91 01 23 26 A1 01 23 | 23 28 B1 01 23 2A C1 01 17 1D 00 00 13 0D CD EB 24 | 97 1D 00 00 93 8D 8D F4 83 20 0D 00 13 A0 10 00 25 | 23 A0 1D 00 23 A2 0D 00 97 1F 00 00 93 8F 8F F3 26 | 93 20 10 00 13 21 F0 7F 93 21 F0 FF 13 22 00 00 27 | 93 22 00 80 23 A0 0F 00 23 A2 1F 00 23 A4 2F 00 28 | 23 A6 3F 00 23 A8 4F 00 23 AA 5F 00 97 1F 00 00 29 | 93 8F CF F1 93 20 10 00 13 A1 10 00 13 2E 11 00 30 | 93 2E 1E 00 13 AF 1E 00 23 A0 0F 00 23 A2 1F 00 31 | 23 A4 2F 00 23 A6 CF 01 23 A8 DF 01 23 AA EF 01 32 | 17 15 00 00 13 05 05 E5 97 15 00 00 93 85 85 EF 33 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 34 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 35 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 36 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 37 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 38 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 39 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DB 73 10 00 C0 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | @00001000 43 | 00 00 00 00 01 00 00 00 FF FF FF FF FF FF FF 7F 44 | 00 00 00 80 FF FF FF FF 00 00 00 00 00 00 00 00 45 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 46 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 47 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 57 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 58 | -------------------------------------------------------------------------------- /verilator/images/I-SLTIU-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SLTIU-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SLTIU-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 FE 4 | 17 11 00 00 13 01 01 01 83 A1 00 00 13 B2 11 00 5 | 93 B2 F1 7F 13 B3 F1 FF 93 B3 01 00 13 B4 01 80 6 | 23 20 31 00 23 22 41 00 23 24 51 00 23 26 61 00 7 | 23 28 71 00 23 2A 81 00 97 10 00 00 93 80 C0 FA 8 | 17 11 00 00 13 01 81 FE 03 A4 00 00 93 34 14 00 9 | 13 35 F4 7F 93 35 F4 FF 13 36 04 00 93 36 04 80 10 | 23 20 81 00 23 22 91 00 23 24 A1 00 23 26 B1 00 11 | 23 28 C1 00 23 2A D1 00 97 10 00 00 93 80 00 F7 12 | 17 11 00 00 13 01 01 FC 83 A6 00 00 13 B7 16 00 13 | 93 B7 F6 7F 13 B8 F6 FF 93 B8 06 00 13 B9 06 80 14 | 23 20 D1 00 23 22 E1 00 23 24 F1 00 23 26 01 01 15 | 23 28 11 01 23 2A 21 01 97 10 00 00 93 80 40 F3 16 | 17 11 00 00 13 01 81 F9 03 A9 00 00 93 39 19 00 17 | 13 3A F9 7F 93 3A F9 FF 13 3B 09 00 93 3B 09 80 18 | 23 20 21 01 23 22 31 01 23 24 41 01 23 26 51 01 19 | 23 28 61 01 23 2A 71 01 97 10 00 00 93 80 80 EF 20 | 17 11 00 00 13 01 01 F7 83 AB 00 00 13 BC 1B 00 21 | 93 BC FB 7F 13 BD FB FF 93 BD 0B 00 13 BE 0B 80 22 | 23 20 71 01 23 22 81 01 23 24 91 01 23 26 A1 01 23 | 23 28 B1 01 23 2A C1 01 17 1D 00 00 13 0D CD EB 24 | 97 1D 00 00 93 8D 8D F4 83 20 0D 00 13 B0 F0 FF 25 | 23 A0 1D 00 23 A2 0D 00 97 1F 00 00 93 8F 8F F3 26 | 93 30 10 00 13 31 F0 7F 93 31 F0 FF 13 32 00 00 27 | 93 32 00 80 23 A0 0F 00 23 A2 1F 00 23 A4 2F 00 28 | 23 A6 3F 00 23 A8 4F 00 23 AA 5F 00 97 1F 00 00 29 | 93 8F CF F1 93 30 10 00 13 B1 10 00 13 3E 11 00 30 | 93 3E 1E 00 13 BF 1E 00 23 A0 0F 00 23 A2 1F 00 31 | 23 A4 2F 00 23 A6 CF 01 23 A8 DF 01 23 AA EF 01 32 | 17 15 00 00 13 05 05 E5 97 15 00 00 93 85 85 EF 33 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 34 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 35 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 36 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 37 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 38 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 39 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DB 73 10 00 C0 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | @00001000 43 | 00 00 00 00 01 00 00 00 FF FF FF FF FF FF FF 7F 44 | 00 00 00 80 01 00 00 00 00 00 00 00 00 00 00 00 45 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 46 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 47 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 57 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 58 | -------------------------------------------------------------------------------- /verilator/images/I-SLTU-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SLTU-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SRA-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SRA-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SRAI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SRAI-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SRAI-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 FE 4 | 17 11 00 00 13 01 01 01 83 A1 00 00 13 D2 11 40 5 | 93 D2 F1 40 13 D3 F1 41 93 D3 01 40 13 D4 01 41 6 | 23 20 31 00 23 22 41 00 23 24 51 00 23 26 61 00 7 | 23 28 71 00 23 2A 81 00 97 10 00 00 93 80 C0 FA 8 | 17 11 00 00 13 01 81 FE 03 A4 00 00 93 54 14 40 9 | 13 55 F4 40 93 55 F4 41 13 56 04 40 93 56 04 41 10 | 23 20 81 00 23 22 91 00 23 24 A1 00 23 26 B1 00 11 | 23 28 C1 00 23 2A D1 00 97 10 00 00 93 80 00 F7 12 | 17 11 00 00 13 01 01 FC 83 A6 00 00 13 D7 16 40 13 | 93 D7 F6 40 13 D8 F6 41 93 D8 06 40 13 D9 06 41 14 | 23 20 D1 00 23 22 E1 00 23 24 F1 00 23 26 01 01 15 | 23 28 11 01 23 2A 21 01 17 16 00 00 13 06 46 F3 16 | 97 16 00 00 93 86 86 F9 03 29 06 00 93 59 19 40 17 | 13 5A F9 40 93 5A F9 41 13 5B 09 40 93 5B 09 41 18 | 23 A0 26 01 23 A2 36 01 23 A4 46 01 23 A6 56 01 19 | 23 A8 66 01 23 AA 76 01 17 16 00 00 13 06 86 EF 20 | 97 16 00 00 93 86 06 F7 83 2B 06 00 13 DC 1B 40 21 | 93 DC FB 40 13 DD FB 41 93 DD 0B 40 13 DE 0B 41 22 | 23 A0 76 01 23 A2 86 01 23 A4 96 01 23 A6 A6 01 23 | 23 A8 B6 01 23 AA C6 01 17 1D 00 00 13 0D CD EB 24 | 97 1D 00 00 93 8D 8D F4 03 2E 0D 00 93 5E 1E 40 25 | 13 DF 1E 40 93 5F 1F 40 93 D0 1F 40 13 D1 10 40 26 | 93 51 11 40 23 A0 CD 01 23 A2 DD 01 23 A4 ED 01 27 | 23 A6 FD 01 23 A8 1D 00 23 AA 2D 00 23 AC 3D 00 28 | 97 10 00 00 93 80 80 E7 17 11 00 00 13 01 C1 F1 29 | 83 A2 00 00 13 D0 12 40 23 20 01 00 97 10 00 00 30 | 93 80 00 E6 17 11 00 00 13 01 41 F0 83 A2 00 00 31 | 13 D0 12 40 93 52 10 40 23 20 01 00 23 22 51 00 32 | 17 15 00 00 13 05 05 E5 97 15 00 00 93 85 85 EE 33 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 34 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 35 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 36 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 37 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 38 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 39 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DB 73 10 00 C0 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | @00001000 43 | 00 00 00 00 01 00 00 00 FF FF FF FF FF FF FF 7F 44 | 00 00 00 80 10 EF CD AB 78 56 34 12 98 BA DC FE 45 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 46 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 47 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 57 | -------------------------------------------------------------------------------- /verilator/images/I-SRL-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SRL-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SRLI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SRLI-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SRLI-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 FE 4 | 17 11 00 00 13 01 01 01 83 A1 00 00 13 D2 11 00 5 | 93 D2 F1 00 13 D3 F1 01 93 D3 01 00 13 D4 01 01 6 | 23 20 31 00 23 22 41 00 23 24 51 00 23 26 61 00 7 | 23 28 71 00 23 2A 81 00 97 10 00 00 93 80 C0 FA 8 | 17 11 00 00 13 01 81 FE 03 A4 00 00 93 54 14 00 9 | 13 55 F4 00 93 55 F4 01 13 56 04 00 93 56 04 01 10 | 23 20 81 00 23 22 91 00 23 24 A1 00 23 26 B1 00 11 | 23 28 C1 00 23 2A D1 00 97 10 00 00 93 80 00 F7 12 | 17 11 00 00 13 01 01 FC 83 A6 00 00 13 D7 16 00 13 | 93 D7 F6 00 13 D8 F6 01 93 D8 06 00 13 D9 06 01 14 | 23 20 D1 00 23 22 E1 00 23 24 F1 00 23 26 01 01 15 | 23 28 11 01 23 2A 21 01 17 16 00 00 13 06 46 F3 16 | 97 16 00 00 93 86 86 F9 03 29 06 00 93 59 19 00 17 | 13 5A F9 00 93 5A F9 01 13 5B 09 00 93 5B 09 01 18 | 23 A0 26 01 23 A2 36 01 23 A4 46 01 23 A6 56 01 19 | 23 A8 66 01 23 AA 76 01 17 16 00 00 13 06 86 EF 20 | 97 16 00 00 93 86 06 F7 83 2B 06 00 13 DC 1B 00 21 | 93 DC FB 00 13 DD FB 01 93 DD 0B 00 13 DE 0B 01 22 | 23 A0 76 01 23 A2 86 01 23 A4 96 01 23 A6 A6 01 23 | 23 A8 B6 01 23 AA C6 01 17 1D 00 00 13 0D CD EB 24 | 97 1D 00 00 93 8D 8D F4 03 2E 0D 00 93 5E 1E 00 25 | 13 DF 1E 00 93 5F 1F 00 93 D0 1F 00 13 D1 10 00 26 | 93 51 11 00 23 A0 CD 01 23 A2 DD 01 23 A4 ED 01 27 | 23 A6 FD 01 23 A8 1D 00 23 AA 2D 00 23 AC 3D 00 28 | 97 10 00 00 93 80 80 E7 17 11 00 00 13 01 C1 F1 29 | 83 A2 00 00 13 D0 12 00 23 20 01 00 97 10 00 00 30 | 93 80 00 E6 17 11 00 00 13 01 41 F0 83 A2 00 00 31 | 13 D0 12 00 93 52 10 00 23 20 01 00 23 22 51 00 32 | 17 15 00 00 13 05 05 E5 97 15 00 00 93 85 85 EE 33 | 37 C6 00 00 63 0E B5 04 93 06 05 01 93 86 F6 FF 34 | 03 87 06 00 93 57 47 40 93 F7 F7 00 13 08 A0 00 35 | 63 C4 07 01 93 87 77 02 93 87 07 03 23 00 F6 00 36 | 93 57 07 40 93 F7 F7 00 13 08 A0 00 63 C4 07 01 37 | 93 87 77 02 93 87 07 03 23 00 F6 00 E3 10 D5 FC 38 | 13 05 05 01 13 07 A0 00 23 00 E6 00 6F F0 9F FA 39 | 13 07 F0 0F 23 00 E6 00 6F F0 9F DB 73 10 00 C0 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | @00001000 43 | 00 00 00 00 01 00 00 00 FF FF FF FF FF FF FF 7F 44 | 00 00 00 80 10 EF CD AB 78 56 34 12 98 BA DC FE 45 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 46 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 47 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 48 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 49 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 51 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 52 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 53 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 54 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 55 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 56 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 57 | -------------------------------------------------------------------------------- /verilator/images/I-SUB-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SUB-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SW-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-SW-01.bin -------------------------------------------------------------------------------- /verilator/images/I-SW-01.mem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 40 01 6F 00 00 00 13 00 00 00 13 00 00 00 3 | 6F 00 00 00 93 01 00 00 97 10 00 00 93 80 80 00 4 | 37 F1 F1 11 13 01 21 22 23 A0 20 00 97 12 00 00 5 | 93 82 92 FF B7 4C 33 F3 93 8C 4C 4F A3 AF 92 FF 6 | 17 14 00 00 13 04 74 FE B7 FF F5 55 93 8F 6F 66 7 | A3 20 F4 01 97 15 00 00 93 85 85 7D 37 96 77 F7 8 | 13 06 86 8F 23 A0 C5 80 17 07 00 00 13 07 97 7C 9 | B7 17 09 99 93 87 A7 AA A3 2F F7 7E 97 18 00 00 10 | 93 88 C8 FB 37 D9 BB 0B 13 09 C9 C0 B7 19 0D DD 11 | 93 89 E9 EE 37 0A FF 0F 13 0A 0A 0F 23 AE 28 FF 12 | 23 A0 38 01 23 A2 48 01 17 1B 00 00 13 0B 8B F9 13 | 37 50 34 12 13 00 80 67 23 20 0B 00 97 1A 00 00 14 | 93 8A 4A F4 B7 39 22 11 93 89 49 34 83 AB 0A 00 15 | 23 A0 3B 01 97 1B 00 00 93 8B 0B F3 17 1C 00 00 16 | 13 0C CC F6 83 AC 0B 00 23 20 9C 01 17 1D 00 00 17 | 13 0D 0D F6 B7 3C 54 76 93 8C 0C 21 23 20 9D 01 18 | 93 0C 00 00 17 1E 00 00 13 0E CE F4 B7 DD AB 89 19 | 93 8D FD DE 23 20 BE 01 13 0E CE FF 97 1E 00 00 20 | 93 8E 8E F3 B7 6D 72 14 93 8D 6D 83 23 A0 BE 01 21 | 03 AF 0E 00 23 A2 EE 01 97 10 00 00 93 80 40 F2 22 | 37 51 38 96 13 01 11 20 B7 51 81 25 93 81 31 96 23 | 23 A0 20 00 23 A0 30 00 17 15 00 00 13 05 85 EC 24 | 97 15 00 00 93 85 05 F0 37 C6 00 00 63 0E B5 04 25 | 93 06 05 01 93 86 F6 FF 03 87 06 00 93 57 47 40 26 | 93 F7 F7 00 13 08 A0 00 63 C4 07 01 93 87 77 02 27 | 93 87 07 03 23 00 F6 00 93 57 07 40 93 F7 F7 00 28 | 13 08 A0 00 63 C4 07 01 93 87 77 02 93 87 07 03 29 | 23 00 F6 00 E3 10 D5 FC 13 05 05 01 13 07 A0 00 30 | 23 00 E6 00 6F F0 9F FA 13 07 F0 0F 23 00 E6 00 31 | 6F F0 1F E4 73 10 00 C0 00 00 00 00 00 00 00 00 32 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 33 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 34 | @00001000 35 | 44 10 00 00 F0 DE BC 9A 00 00 00 00 00 00 00 00 36 | BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 37 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 38 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 39 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 40 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 41 | EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE 42 | -------------------------------------------------------------------------------- /verilator/images/I-XOR-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-XOR-01.bin -------------------------------------------------------------------------------- /verilator/images/I-XORI-01.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/I-XORI-01.bin -------------------------------------------------------------------------------- /verilator/images/zephyr-philo.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/zephyr-philo.bin -------------------------------------------------------------------------------- /verilator/images/zephyr-synch.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/micro-FPGA/engine-V/87ba9cadbbbd9e179a14431287045590027e502a/verilator/images/zephyr-synch.bin -------------------------------------------------------------------------------- /verilator/mf8a18/README.md: -------------------------------------------------------------------------------- 1 | Microcode for MF8A18 Microcode engine -------------------------------------------------------------------------------- /verilator/references/I-ADD-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 80000001800000000000000000000002 4 | fffffffe00000000ffffffffffffffff 5 | 7fffffff7fffffff7fffffff7ffffffe 6 | fffffffffffffffe7ffffffe80000000 7 | 7fffffff800000018000000080000000 8 | 0000abcd0000000100000000ffffffff 9 | 0000abd10000abd00000abcf0000abce 10 | 00000000000000000000abd30000abd2 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-ADDI-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000007ff0000000100000000 2 | 0000000200000001fffff80000000000 3 | fffff801000000010000000000000800 4 | fffffffe000007fe00000000ffffffff 5 | 800000007ffffffffffff7ffffffffff 6 | 7ffff7ff7fffffff7ffffffe800007fe 7 | 7fffffff800007ff8000000180000000 8 | 0000abce0000abcd7ffff80080000000 9 | 0000abd20000abd10000abd00000abcf 10 | 0000000100000000000000000000abd3 11 | 36925814369258143692581436925814 12 | -------------------------------------------------------------------------------- /verilator/references/I-AND-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000010000000000000000 3 | 00000000000000010000000100000001 4 | ffffffff0000000100000000ffffffff 5 | 000000007fffffff800000007fffffff 6 | 000000007fffffff7fffffff00000001 7 | 80000000000000000000000080000000 8 | abcdffff0000007f8000000000000000 9 | 0000000f0000001f0000003f0000007f 10 | 00000000000000000000000300000007 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-ANDI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000001000000010000000000000000 3 | 00000000000000000000000100000001 4 | ffffffff000007ff00000001ffffffff 5 | 000000017ffffffffffff80000000000 6 | 7ffff800000000007fffffff000007ff 7 | 80000000000000000000000080000000 8 | 0000007fabcdffff8000000000000000 9 | 000000070000000f0000001f0000003f 10 | 00000000000000000000000000000003 11 | 36925814369258143692581436925814 12 | -------------------------------------------------------------------------------- /verilator/references/I-AUIPC-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | -------------------------------------------------------------------------------- /verilator/references/I-BEQ-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 000000010000001e800000007fffffff 3 | 7fffffffffffffff0000000100000000 4 | 00000000ffffffff0000001d80000000 5 | 800000007fffffffffffffff00000001 6 | 00000001000000007fffffff0000001b 7 | 00000017800000007fffffffffffffff 8 | ffffffff000000010000000080000000 9 | 000003de0000000f800000007fffffff 10 | 0fedcba9876543219abcdef000000000 11 | -------------------------------------------------------------------------------- /verilator/references/I-BGE-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 000000010000000a800000007fffffff 3 | 7fffffffffffffff0000000100000000 4 | 00000000ffffffff0000000880000000 5 | 800000007fffffffffffffff00000001 6 | 00000001000000007fffffff0000000b 7 | 00000000800000007fffffffffffffff 8 | ffffffff000000010000000080000000 9 | 000001540000000f800000007fffffff 10 | 0fedcba9876543219abcdef000000000 11 | -------------------------------------------------------------------------------- /verilator/references/I-BGEU-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 000000010000001e800000007fffffff 3 | 7fffffffffffffff0000000100000000 4 | 00000000ffffffff0000001c80000000 5 | 800000007fffffffffffffff00000001 6 | 00000001000000007fffffff00000000 7 | 00000014800000007fffffffffffffff 8 | ffffffff000000010000000080000000 9 | 000003c000000004800000007fffffff 10 | 0fedcba9876543219abcdef000000000 11 | -------------------------------------------------------------------------------- /verilator/references/I-BLT-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000015800000007fffffff 3 | 7fffffffffffffff0000000100000000 4 | 00000000ffffffff0000001780000000 5 | 800000007fffffffffffffff00000001 6 | 00000001000000007fffffff00000014 7 | 0000001f800000007fffffffffffffff 8 | ffffffff000000010000000080000000 9 | 000002ab00000010800000007fffffff 10 | 0fedcba9876543219abcdef000000000 11 | -------------------------------------------------------------------------------- /verilator/references/I-BLTU-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 7fffffffffffffff0000000100000000 4 | 00000000ffffffff0000000380000000 5 | 800000007fffffffffffffff00000001 6 | 00000001000000007fffffff0000001f 7 | 0000000b800000007fffffffffffffff 8 | ffffffff000000010000000080000000 9 | 0000003f0000001b800000007fffffff 10 | 0fedcba9876543219abcdef000000000 11 | -------------------------------------------------------------------------------- /verilator/references/I-BNE-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 7fffffffffffffff0000000100000000 4 | 00000000ffffffff0000000280000000 5 | 800000007fffffffffffffff00000001 6 | 00000001000000007fffffff00000004 7 | 00000008800000007fffffffffffffff 8 | ffffffff000000010000000080000000 9 | 0000002100000010800000007fffffff 10 | 0fedcba9876543219abcdef000000000 11 | -------------------------------------------------------------------------------- /verilator/references/I-CSRRC-01.reference_output: -------------------------------------------------------------------------------- 1 | 800f0000fffffffffffffffe00000000 2 | fffffffeffffffff000000007fffffff 3 | 00000000000f0000800f0000fffffffe 4 | ffffffff00000000ffffffffedcba987 5 | 0000000042726e6f00000000ffffffff 6 | 49c1a90369c7ad8bfffffffff7ff8818 7 | -------------------------------------------------------------------------------- /verilator/references/I-CSRRCI-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffe0fffffffffffffffe00000000 2 | fffffffffffffffffffffff0ffffffef 3 | ffffffe0ffffffe0fffffffefffffffe 4 | 3216549000000000ffffffffffffffe0 5 | -------------------------------------------------------------------------------- /verilator/references/I-CSRRS-01.reference_output: -------------------------------------------------------------------------------- 1 | 7ff0ffff000000000000000100000000 2 | 0000000100000000ffffffff80000000 3 | fffffffffff0ffff7ff0ffff00000001 4 | 00000000123456780000000012345678 5 | 0000000042726e6f0000000012345678 6 | b63e56fc9638527400000000f7ff8818 7 | -------------------------------------------------------------------------------- /verilator/references/I-CSRRSI-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000001f000000000000000100000000 2 | 00000000000000000000000f00000010 3 | 0000001f0000001f0000000100000001 4 | 321654983216549f000000000000001f 5 | -------------------------------------------------------------------------------- /verilator/references/I-CSRRW-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000000000000100000000 2 | 9abcdef012345678800000007fffffff 3 | 00000000000000009abcdef012345678 4 | 32165498963852741472583600000000 5 | -------------------------------------------------------------------------------- /verilator/references/I-CSRRWI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000010000000000000000 2 | 00000000000000100000000f0000001f 3 | -------------------------------------------------------------------------------- /verilator/references/I-DELAY_SLOTS-01.reference_output: -------------------------------------------------------------------------------- 1 | 44444444333333332222222211111111 2 | 88888888777777776666666655555555 3 | -------------------------------------------------------------------------------- /verilator/references/I-EBREAK-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000001111111100000003 2 | -------------------------------------------------------------------------------- /verilator/references/I-ECALL-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000000000000000111111110000000b 2 | -------------------------------------------------------------------------------- /verilator/references/I-ENDIANESS-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000089000001230000456701234567 2 | 00000001000000230000004500000067 3 | -------------------------------------------------------------------------------- /verilator/references/I-FENCE.I-01.reference_output: -------------------------------------------------------------------------------- 1 | 001101b3000000420000001200000030 2 | -------------------------------------------------------------------------------- /verilator/references/I-HI-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 80000001800000000000000000000002 4 | fffffffe00000000ffffffffffffffff 5 | 7fffffff7fffffff7fffffff7ffffffe 6 | fffffffffffffffe7ffffffe80000000 7 | 7fffffff800000018000000080000000 8 | 0000abcd0000000100000000ffffffff 9 | 0000abd10000abd00000abcf0000abce 10 | 00000000000000000000abd30000abd2 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-IO-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 80000001800000000000000000000002 4 | fffffffe00000000ffffffffffffffff 5 | 7fffffff7fffffff7fffffff7ffffffe 6 | fffffffffffffffe7ffffffe80000000 7 | 7fffffff800000018000000080000000 8 | 0000abcd0000000100000000ffffffff 9 | 0000abd10000abd00000abcf0000abce 10 | 00000000000000000000abd30000abd2 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-JAL-01.reference_output: -------------------------------------------------------------------------------- 1 | 9abcdef0000000001234567800000000 2 | 22222222111111110fedcba987654321 3 | 00000000555555554444444433333333 4 | 88888888777777776666666600000000 5 | 0000000000000000aaaaaaaa99999999 6 | -------------------------------------------------------------------------------- /verilator/references/I-JALR-01.reference_output: -------------------------------------------------------------------------------- 1 | 9abcdef0000000001234567800000000 2 | 22222222111111110fedcba987654321 3 | 00000000555555554444444433333333 4 | 88888888777777776666666600000000 5 | 0000000000000000aaaaaaaa99999999 6 | 44444444333333332222222211111111 7 | -------------------------------------------------------------------------------- /verilator/references/I-LB-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000011fffffff1fffffff200000022 2 | fffffff30000003300000044fffffff4 3 | 00000055fffffff5fffffff600000066 4 | fffffff700000077ffffff88fffffff8 5 | ffffff99000000090000000affffffaa 6 | 0000000bffffffbbffffffcc0000000c 7 | ffffffdd0000000d0000000effffffee 8 | 0000000fffffffff00000000fffffff0 9 | ffffff9800000010fffffff000000000 10 | -------------------------------------------------------------------------------- /verilator/references/I-LBU-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000011000000f1000000f200000022 2 | 000000f30000003300000044000000f4 3 | 00000055000000f5000000f600000066 4 | 000000f70000007700000088000000f8 5 | 00000099000000090000000a000000aa 6 | 0000000b000000bb000000cc0000000c 7 | 000000dd0000000d0000000e000000ee 8 | 0000000f000000ff00000000000000f0 9 | 0000009800000010000000f000000000 10 | -------------------------------------------------------------------------------- /verilator/references/I-LH-01.reference_output: -------------------------------------------------------------------------------- 1 | fffff333000044f4000011f1fffff222 2 | fffff777ffff88f8000055f5fffff666 3 | 00000bbbffffcc0cffff990900000aaa 4 | 00000fff000000f0ffffdd0d00000eee 5 | ffffba9800003210ffffdef000000000 6 | -------------------------------------------------------------------------------- /verilator/references/I-LHU-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000f333000044f4000011f10000f222 2 | 0000f777000088f8000055f50000f666 3 | 00000bbb0000cc0c0000990900000aaa 4 | 00000fff000000f00000dd0d00000eee 5 | 0000ba98000032100000def000000000 6 | -------------------------------------------------------------------------------- /verilator/references/I-LUI-01.reference_output: -------------------------------------------------------------------------------- 1 | 7ffff000fffff0000000100000000000 2 | 000000007ffff0008000000080000000 3 | 1234567842726e6ffffff00000001000 4 | 9abcdef01234567842726e6f9abcdef0 5 | -------------------------------------------------------------------------------- /verilator/references/I-LW-01.reference_output: -------------------------------------------------------------------------------- 1 | f77788f855f5f666f33344f411f1f222 2 | 0fff00f0dd0d0eee0bbbcc0c99090aaa 3 | fedcba98765432109abcdef000000000 4 | -------------------------------------------------------------------------------- /verilator/references/I-MISALIGN_JMP-01.reference_output: -------------------------------------------------------------------------------- 1 | 22222222111111110000000000000002 2 | 00000000000000024444444433333333 3 | 66666666000000000000000255555555 4 | 00000002777777770000000000000002 5 | 00000000000000028888888800000000 6 | aaaaaaaa000000000000000299999999 7 | 00000002bbbbbbbb0000000000000002 8 | 0000000000000002cccccccc00000000 9 | eeeeeeee0000000000000002dddddddd 10 | -------------------------------------------------------------------------------- /verilator/references/I-MISALIGN_LDST-01.reference_output: -------------------------------------------------------------------------------- 1 | 91a1b1c191a1b1c191a1b1c191a1b1c1 2 | 00000004000000020000000400000001 3 | fffff202fffff2020000000400000003 4 | 0000f2020000f202ffffd2e2ffffd2e2 5 | 00000004000000010000d2e20000d2e2 6 | 00000004000000010000000400000003 7 | 99999999000000000000000400000003 8 | 00000006000000019999999999999999 9 | 00000006000000030000000600000002 10 | 99999999000099999999999999990000 11 | 00000006000000030000000600000001 12 | -------------------------------------------------------------------------------- /verilator/references/I-NOP-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000004000000030000000200000000 2 | 00000008000000070000000600000005 3 | 0000000c0000000b0000000a00000009 4 | 000000100000000f0000000e0000000d 5 | 00000014000000130000001200000011 6 | 00000018000000170000001600000015 7 | 0000001c0000001b0000001a00000019 8 | 000000180000001f0000001e0000001d 9 | -------------------------------------------------------------------------------- /verilator/references/I-OR-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 800000017fffffffffffffff00000001 4 | ffffffffffffffffffffffffffffffff 5 | 7fffffff7fffffffffffffffffffffff 6 | ffffffff7fffffffffffffff7fffffff 7 | ffffffff800000018000000080000000 8 | 0000000d0000001080000000ffffffff 9 | 000000fd0000007d0000003d0000001d 10 | 0000000000000000fffff9fd000001fd 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-ORI-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000007ff0000000100000000 2 | 0000000100000001fffff80000000000 3 | fffff80100000001ffffffff000007ff 4 | ffffffffffffffffffffffffffffffff 5 | 7fffffff7fffffffffffffffffffffff 6 | ffffffff7fffffffffffffff7fffffff 7 | ffffffff800007ff8000000180000000 8 | 0000001d0000000dfffff80080000000 9 | 000001fd000000fd0000007d0000003d 10 | 000000010000000000000000fffff9fd 11 | 36925814369258143692581436925814 12 | -------------------------------------------------------------------------------- /verilator/references/I-PI-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 80000001800000000000000000000002 4 | fffffffe00000000ffffffffffffffff 5 | 7fffffff7fffffff7fffffff7ffffffe 6 | fffffffffffffffe7ffffffe80000000 7 | 7fffffff800000018000000080000000 8 | 0000abcd0000000100000000ffffffff 9 | 0000abd10000abd00000abcf0000abce 10 | 00000000000000000000abd30000abd2 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-RF_size-01.reference_output: -------------------------------------------------------------------------------- 1 | 526973632d5620525633324900000000 2 | 4d696c616e204e6f73746572736b7920 3 | 286e6f73746572736b7940636f646173 4 | 69702e636f6d292c20526164656b2048 5 | 616a656b202868616a656b40636f6461 6 | 7369702e636f6d292e204c6561766520 7 | 7573206d65737361676520696620796f 8 | 7520726561642074686973203a290d0a 9 | 526973632d5620525633324900000000 10 | -------------------------------------------------------------------------------- /verilator/references/I-RF_width-01.reference_output: -------------------------------------------------------------------------------- 1 | 80000000800000008000000000000000 2 | 80000000800000008000000080000000 3 | 80000000800000008000000080000000 4 | 80000000800000008000000080000000 5 | 80000000800000008000000080000000 6 | 80000000800000008000000080000000 7 | 80000000800000008000000080000000 8 | 80000000800000008000000080000000 9 | -------------------------------------------------------------------------------- /verilator/references/I-RF_x0-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | -------------------------------------------------------------------------------- /verilator/references/I-SB-01.reference_output: -------------------------------------------------------------------------------- 1 | 000000f800000066000000f4aaaabb22 2 | 0fff00f0dd0d0eee0bbbcc0c000000aa 3 | 00000010000000f00000004487654300 4 | 000000630000003600000036000000ef 5 | -------------------------------------------------------------------------------- /verilator/references/I-SH-01.reference_output: -------------------------------------------------------------------------------- 1 | 000088f80000f666000044f4aaaaf222 2 | 0fff00f0dd0d0eee0bbbcc0c00000aaa 3 | 000032100000def00000334487650000 4 | 0000496300005836000058360000cdef 5 | -------------------------------------------------------------------------------- /verilator/references/I-SLL-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000002000000010000000000000000 3 | 00010000000000018000000000008000 4 | 80000000ffff8000fffffffeffffffff 5 | fffffffe7fffffffffff0000ffffffff 6 | ffff00007fffffff80000000ffff8000 7 | 00000000000000000000000080000000 8 | 579bde20abcdef100000000080000000 9 | 79bde200bcdef1005e6f7880af37bc40 10 | 000000000000000000000000f37bc400 11 | 80000000a19080000eca864287654321 12 | -------------------------------------------------------------------------------- /verilator/references/I-SLLI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000002000000010000000000000000 3 | 00010000000000018000000000008000 4 | 80000000ffff8000fffffffeffffffff 5 | fffffffe7fffffffffff0000ffffffff 6 | ffff00007fffffff80000000ffff8000 7 | 00000000000000000000000080000000 8 | 579bde20abcdef100000000080000000 9 | 79bde200bcdef1005e6f7880af37bc40 10 | 000000000000000000000000f37bc400 11 | -------------------------------------------------------------------------------- /verilator/references/I-SLT-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000010000000100000000 2 | 00000000000000010000000000000000 3 | 00000000000000000000000000000001 4 | 000000000000000100000001ffffffff 5 | 000000007fffffff0000000000000001 6 | 00000000000000000000000000000000 7 | 00000001000000010000000180000000 8 | ffffffff000000000000000000000001 9 | 00000000000000010000000100000001 10 | 00000000000000000000000000000000 11 | 00000001000000010000000000000001 12 | 00000001000000000000000100000000 13 | -------------------------------------------------------------------------------- /verilator/references/I-SLTI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000010000000100000000 2 | 00000000000000010000000000000000 3 | 00000000000000000000000000000001 4 | 000000000000000100000001ffffffff 5 | 000000007fffffff0000000000000001 6 | 00000000000000000000000000000000 7 | 00000001000000010000000180000000 8 | 00000000ffffffff0000000100000001 9 | 00000000000000010000000100000000 10 | 00000001000000000000000000000000 11 | 00000001000000000000000100000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-SLTIU-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000001000000010000000100000000 2 | 00000000000000010000000100000000 3 | 00000001000000000000000100000001 4 | 000000000000000000000000ffffffff 5 | 000000007fffffff0000000000000000 6 | 00000001000000000000000100000000 7 | 00000001000000000000000080000000 8 | 00000000000000010000000100000000 9 | 00000001000000010000000100000000 10 | 00000001000000000000000100000000 11 | 00000001000000000000000100000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-SLTU-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000001000000010000000100000000 2 | 00000000000000010000000100000000 3 | 00000001000000000000000100000001 4 | 000000000000000000000000ffffffff 5 | 000000007fffffff0000000000000000 6 | 00000001000000000000000100000000 7 | 00000001000000000000000080000000 8 | 00000001000000000000000000000000 9 | 000000010000000100000001ffffffff 10 | 00000000000000000000000100000000 11 | 00000001000000000000000000000000 12 | 00000001000000000000000100000000 13 | -------------------------------------------------------------------------------- /verilator/references/I-SRA-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000010000000000000000 3 | 00000000000000010000000000000000 4 | ffffffffffffffffffffffffffffffff 5 | 3fffffff7fffffffffffffffffffffff 6 | 00007fff7fffffff000000000000ffff 7 | ffffffffffff0000c000000080000000 8 | d5e6f788abcdef10ffff800080000000 9 | fd5e6f78fabcdef1f579bde2eaf37bc4 10 | 000000000000000000000000feaf37bc 11 | ffffffffffff0ecac3b2a19087654321 12 | -------------------------------------------------------------------------------- /verilator/references/I-SRAI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000010000000000000000 3 | 00000000000000010000000000000000 4 | ffffffffffffffffffffffffffffffff 5 | 3fffffff7fffffffffffffffffffffff 6 | 00007fff7fffffff000000000000ffff 7 | ffffffffffff0000c000000080000000 8 | d5e6f788abcdef10ffff800080000000 9 | fd5e6f78fabcdef1f579bde2eaf37bc4 10 | 000000000000000000000000feaf37bc 11 | -------------------------------------------------------------------------------- /verilator/references/I-SRL-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000010000000000000000 3 | 00000000000000010000000000000000 4 | 000000010001ffff7fffffffffffffff 5 | 3fffffff7fffffff0000ffffffffffff 6 | 00007fff7fffffff000000000000ffff 7 | 00000001000100004000000080000000 8 | 55e6f788abcdef100000800080000000 9 | 055e6f780abcdef11579bde22af37bc4 10 | 00000000000000000000000002af37bc 11 | 0000000100010eca43b2a19087654321 12 | -------------------------------------------------------------------------------- /verilator/references/I-SRLI-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000010000000000000000 3 | 00000000000000010000000000000000 4 | 000000010001ffff7fffffffffffffff 5 | 3fffffff7fffffff0000ffffffffffff 6 | 00007fff7fffffff000000000000ffff 7 | 00000001000100004000000080000000 8 | 55e6f788abcdef100000800080000000 9 | 055e6f780abcdef11579bde22af37bc4 10 | 00000000000000000000000002af37bc 11 | -------------------------------------------------------------------------------- /verilator/references/I-SUB-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000001ffffffff0000000000000000 2 | 00000001000000018000000080000001 3 | 80000001800000020000000200000000 4 | 00000000fffffffeffffffffffffffff 5 | 7fffffff7fffffff7fffffff80000000 6 | ffffffff00000000800000007ffffffe 7 | 800000017fffffff8000000080000000 8 | 0000abcd000000010000000000000001 9 | 0000abc90000abca0000abcb0000abcc 10 | 00000000000000000000abc70000abc8 11 | c96da7ecc96da7ec3692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-SW-01.reference_output: -------------------------------------------------------------------------------- 1 | f77788f855f5f666f33344f411f1f222 2 | 0fff00f0dd0d0eee0bbbcc0c99090aaa 3 | 765432109abcdef01122334400000000 4 | 25814963147258361472583689abcdef 5 | -------------------------------------------------------------------------------- /verilator/references/I-TEST-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 80000001800000000000000000000002 4 | fffffffe00000000ffffffffffffffff 5 | 7fffffff7fffffff7fffffff7ffffffe 6 | fffffffffffffffe7ffffffe80000000 7 | 7fffffff800000018000000080000000 8 | 0000abcd0000000100000000ffffffff 9 | 0000abd10000abd00000abcf0000abce 10 | 00000000000000000000abd30000abd2 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-UART-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 80000001800000000000000000000002 4 | fffffffe00000000ffffffffffffffff 5 | 7fffffff7fffffff7fffffff7ffffffe 6 | fffffffffffffffe7ffffffe80000000 7 | 7fffffff800000018000000080000000 8 | 0000abcd0000000100000000ffffffff 9 | 0000abd10000abd00000abcf0000abce 10 | 00000000000000000000abd30000abd2 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-XOR-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 800000017ffffffefffffffe00000000 4 | 00000000fffffffeffffffffffffffff 5 | 7fffffff7fffffff7fffffff80000000 6 | ffffffff00000000800000007ffffffe 7 | 7fffffff800000018000000080000000 8 | abcdffff0000007f00000000ffffffff 9 | abcdffafabcdffa0abcdffbfabcdff80 10 | 0000000000000000abcdffababcdffa8 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/references/I-XORI-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000007ff0000000100000000 2 | 0000000000000001fffff80000000000 3 | fffff80100000001fffffffe000007fe 4 | 00000000fffff800fffffffeffffffff 5 | 7ffffffe7fffffff000007ffffffffff 6 | 800007ff7fffffff800000007ffff800 7 | 7fffffff800007ff8000000180000000 8 | abcdff80abcdffff7ffff80080000000 9 | abcdffa8abcdffafabcdffa0abcdffbf 10 | 000000010000000000000000abcdffab 11 | 36925814369258143692581436925814 12 | -------------------------------------------------------------------------------- /verilator/references/I-dr-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 80000001800000000000000000000002 4 | fffffffe00000000ffffffffffffffff 5 | 7fffffff7fffffff7fffffff7ffffffe 6 | fffffffffffffffe7ffffffe80000000 7 | 7fffffff800000018000000080000000 8 | 0000abcd0000000100000000ffffffff 9 | 0000abd10000abd00000abcf0000abce 10 | 00000000000000000000abd30000abd2 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /verilator/run/RV32I_Compliance.txt: -------------------------------------------------------------------------------- 1 | Vergleichen der Dateien ..\SIGNATURES\I-ADD-01.signature und ..\REFERENCES\I-ADD-01.REFERENCE_OUTPUT 2 | FC: Keine Unterschiede gefunden 3 | 4 | -------------------------------------------------------------------------------- /verilator/run/run_philo.bat: -------------------------------------------------------------------------------- 1 | set PATH=..\dll;%PATH% 2 | copy ..\images\zephyr-philo.bin ..\build\riscv.bin 3 | cd ..\build 4 | 5 | python ..\scripts\concat_up5k.py 6 | python ..\scripts\bin2hex.py > ..\build\spiflash.hex 7 | 8 | start engine-v.exe 9 | 10 | -------------------------------------------------------------------------------- /verilator/run/run_rv32i_add.bat: -------------------------------------------------------------------------------- 1 | cd ..\signatures 2 | rem del * /q 3 | cd ..\run 4 | del RV32I_Compliance.txt 5 | 6 | call runverilator.bat I-ADD-01 7 | 8 | exit 0 -------------------------------------------------------------------------------- /verilator/run/run_rv32i_all.bat: -------------------------------------------------------------------------------- 1 | cd ..\signatures 2 | del * /q 3 | cd ..\run 4 | del RV32I_Compliance.txt 5 | 6 | call runverilator.bat I-IO-01 7 | 8 | call runverilator.bat I-RF_size-01 9 | call runverilator.bat I-RF_width-01 10 | call runverilator.bat I-RF_x0-01 11 | 12 | call runverilator.bat I-ECALL-01 13 | call runverilator.bat I-EBREAK-01 14 | 15 | call runverilator.bat I-MISALIGN_JMP-01 16 | call runverilator.bat I-MISALIGN_LDST-01 17 | 18 | call runverilator.bat I-CSRRW-01 19 | call runverilator.bat I-CSRRS-01 20 | call runverilator.bat I-CSRRC-01 21 | 22 | call runverilator.bat I-CSRRWI-01 23 | call runverilator.bat I-CSRRSI-01 24 | call runverilator.bat I-CSRRCI-01 25 | 26 | 27 | call runverilator.bat I-ADD-01 28 | call runverilator.bat I-ADDI-01 29 | call runverilator.bat I-AND-01 30 | call runverilator.bat I-ANDI-01 31 | 32 | call runverilator.bat I-SUB-01 33 | 34 | call runverilator.bat I-SLT-01 35 | call runverilator.bat I-SLTU-01 36 | call runverilator.bat I-SLTI-01 37 | call runverilator.bat I-SLTIU-01 38 | 39 | 40 | call runverilator.bat I-OR-01 41 | call runverilator.bat I-ORI-01 42 | call runverilator.bat I-XOR-01 43 | call runverilator.bat I-XORI-01 44 | 45 | 46 | call runverilator.bat I-AUIPC-01 47 | call runverilator.bat I-LUI-01 48 | 49 | call runverilator.bat I-BEQ-01 50 | call runverilator.bat I-BNE-01 51 | 52 | call runverilator.bat I-BLT-01 53 | call runverilator.bat I-BGE-01 54 | call runverilator.bat I-BLTU-01 55 | call runverilator.bat I-BGEU-01 56 | 57 | 58 | call runverilator.bat I-LB-01 59 | call runverilator.bat I-LH-01 60 | call runverilator.bat I-LW-01 61 | call runverilator.bat I-LBU-01 62 | call runverilator.bat I-LHU-01 63 | 64 | call runverilator.bat I-SB-01 65 | call runverilator.bat I-SH-01 66 | call runverilator.bat I-SW-01 67 | 68 | call runverilator.bat I-JAL-01 69 | call runverilator.bat I-JALR-01 70 | 71 | call runverilator.bat I-NOP-01 72 | call runverilator.bat I-FENCE.I-01 73 | call runverilator.bat I-DELAY_SLOTS-01 74 | call runverilator.bat I-ENDIANESS-01 75 | 76 | call runverilator.bat I-SLTI-01 77 | call runverilator.bat I-SLTIU-01 78 | 79 | call runverilator.bat I-SLLI-01 80 | call runverilator.bat I-SRLI-01 81 | call runverilator.bat I-SRAI-01 82 | 83 | call runverilator.bat I-SLL-01 84 | call runverilator.bat I-SLT-01 85 | call runverilator.bat I-SLTU-01 86 | call runverilator.bat I-SRL-01 87 | call runverilator.bat I-SRA-01 88 | 89 | exit 0 90 | -------------------------------------------------------------------------------- /verilator/run/run_synch.bat: -------------------------------------------------------------------------------- 1 | set PATH=..\dll;%PATH% 2 | copy ..\images\zephyr-synch.bin ..\build\riscv.bin 3 | 4 | cd ..\build 5 | 6 | python ..\scripts\concat_up5k.py 7 | 8 | python ..\scripts\bin2hex.py > ..\build\spiflash.hex 9 | 10 | start engine-v.exe 11 | 12 | 13 | -------------------------------------------------------------------------------- /verilator/run/runverilator.bat: -------------------------------------------------------------------------------- 1 | echo Running verilator for RV32I compliance test case: %1 2 | @echo off 3 | copy ..\images\%1.bin ..\build\riscv.bin 4 | cd ..\build 5 | 6 | python ..\scripts\concat_up5k.py 7 | python ..\scripts\bin2hex.py > ..\build\spiflash.hex 8 | 9 | set PATH=..\dll;%PATH% 10 | engine-v.exe >output.sig_listing 11 | python ..\scripts\extract_sig.py output.sig_listing >output.sig 12 | 13 | @copy output.sig ..\signatures\%1.signature 14 | cd .. 15 | cd run 16 | fc ..\signatures\%1.signature ..\references\%1.reference_output >> RV32I_Compliance.txt 17 | -------------------------------------------------------------------------------- /verilator/run_mss/RV32I_Compliance.txt: -------------------------------------------------------------------------------- 1 | Vergleichen der Dateien ..\SIGNATURES\I-ADD-01.signature und ..\REFERENCES\I-ADD-01.REFERENCE_OUTPUT 2 | FC: Keine Unterschiede gefunden 3 | 4 | -------------------------------------------------------------------------------- /verilator/run_mss/run_philo.bat: -------------------------------------------------------------------------------- 1 | set PATH=..\dll;%PATH% 2 | copy ..\images\zephyr-philo.mem ..\build_mss\riscv.mem 3 | cd ..\build_mss 4 | start engine-v.exe 5 | 6 | -------------------------------------------------------------------------------- /verilator/run_mss/run_rv32i_add.bat: -------------------------------------------------------------------------------- 1 | cd ..\signatures 2 | rem del * /q 3 | cd ..\run_mss 4 | del RV32I_Compliance.txt 5 | 6 | call runverilator.bat I-ADD-01 7 | 8 | exit 0 -------------------------------------------------------------------------------- /verilator/run_mss/run_rv32i_all.bat: -------------------------------------------------------------------------------- 1 | cd ..\signatures 2 | del * /q 3 | cd ..\run_mss 4 | del RV32I_Compliance.txt 5 | 6 | call runverilator.bat I-IO-01 7 | 8 | call runverilator.bat I-RF_size-01 9 | call runverilator.bat I-RF_width-01 10 | call runverilator.bat I-RF_x0-01 11 | 12 | call runverilator.bat I-ECALL-01 13 | call runverilator.bat I-EBREAK-01 14 | 15 | call runverilator.bat I-MISALIGN_JMP-01 16 | call runverilator.bat I-MISALIGN_LDST-01 17 | 18 | call runverilator.bat I-CSRRW-01 19 | call runverilator.bat I-CSRRS-01 20 | call runverilator.bat I-CSRRC-01 21 | 22 | call runverilator.bat I-CSRRWI-01 23 | call runverilator.bat I-CSRRSI-01 24 | call runverilator.bat I-CSRRCI-01 25 | 26 | 27 | call runverilator.bat I-ADD-01 28 | call runverilator.bat I-ADDI-01 29 | call runverilator.bat I-AND-01 30 | call runverilator.bat I-ANDI-01 31 | 32 | call runverilator.bat I-SUB-01 33 | 34 | call runverilator.bat I-SLT-01 35 | call runverilator.bat I-SLTU-01 36 | call runverilator.bat I-SLTI-01 37 | call runverilator.bat I-SLTIU-01 38 | 39 | 40 | call runverilator.bat I-OR-01 41 | call runverilator.bat I-ORI-01 42 | call runverilator.bat I-XOR-01 43 | call runverilator.bat I-XORI-01 44 | 45 | 46 | call runverilator.bat I-AUIPC-01 47 | call runverilator.bat I-LUI-01 48 | 49 | call runverilator.bat I-BEQ-01 50 | call runverilator.bat I-BNE-01 51 | 52 | call runverilator.bat I-BLT-01 53 | call runverilator.bat I-BGE-01 54 | call runverilator.bat I-BLTU-01 55 | call runverilator.bat I-BGEU-01 56 | 57 | 58 | call runverilator.bat I-LB-01 59 | call runverilator.bat I-LH-01 60 | call runverilator.bat I-LW-01 61 | call runverilator.bat I-LBU-01 62 | call runverilator.bat I-LHU-01 63 | 64 | call runverilator.bat I-SB-01 65 | call runverilator.bat I-SH-01 66 | call runverilator.bat I-SW-01 67 | 68 | call runverilator.bat I-JAL-01 69 | call runverilator.bat I-JALR-01 70 | 71 | call runverilator.bat I-NOP-01 72 | call runverilator.bat I-FENCE.I-01 73 | call runverilator.bat I-DELAY_SLOTS-01 74 | call runverilator.bat I-ENDIANESS-01 75 | 76 | call runverilator.bat I-SLTI-01 77 | call runverilator.bat I-SLTIU-01 78 | 79 | call runverilator.bat I-SLLI-01 80 | call runverilator.bat I-SRLI-01 81 | call runverilator.bat I-SRAI-01 82 | 83 | call runverilator.bat I-SLL-01 84 | call runverilator.bat I-SLT-01 85 | call runverilator.bat I-SLTU-01 86 | call runverilator.bat I-SRL-01 87 | call runverilator.bat I-SRA-01 88 | 89 | exit 0 90 | -------------------------------------------------------------------------------- /verilator/run_mss/run_synch.bat: -------------------------------------------------------------------------------- 1 | set PATH=..\dll;%PATH% 2 | copy ..\images\zephyr-synch.mem ..\build_mss\riscv.mem 3 | cd ..\build_mss 4 | start engine-v.exe 5 | 6 | 7 | -------------------------------------------------------------------------------- /verilator/run_mss/runverilator.bat: -------------------------------------------------------------------------------- 1 | echo Running verilator for RV32I compliance test case: %1 2 | @echo off 3 | copy ..\images\%1.mem ..\build_mss\riscv.mem 4 | 5 | cd ..\build_mss 6 | set PATH=..\dll;%PATH% 7 | engine-v.exe >output.sig_listing 8 | python ..\scripts\extract_sig.py output.sig_listing >output.sig 9 | 10 | @copy output.sig ..\signatures\%1.signature 11 | cd .. 12 | cd run_mss 13 | fc ..\signatures\%1.signature ..\references\%1.reference_output >> RV32I_Compliance.txt 14 | -------------------------------------------------------------------------------- /verilator/scripts/bin2hex.py: -------------------------------------------------------------------------------- 1 | 2 | binFile = open('spiflash.bin','rb') 3 | binaryData = binFile.read(163840) 4 | for i in range(0,163839): 5 | print ("%02x" %binaryData[i]) 6 | binFile.close -------------------------------------------------------------------------------- /verilator/scripts/concat_up5k.py: -------------------------------------------------------------------------------- 1 | 2 | spiFile = open('spiflash.bin','wb') 3 | 4 | # 128KB is reserved for bitstream 5 | bitFile = open('../bitstream/mf8a18_rv32i.bin','rb') 6 | bitData = bitFile.read(0x20000) 7 | 8 | riscvFile = open('riscv.bin','rb') 9 | riscvData = riscvFile.read(32768) 10 | 11 | spiFile.write(bitData) 12 | 13 | spiFile.seek(0x20000) 14 | spiFile.write(riscvData) 15 | 16 | nullData = bytearray([0]) 17 | spiFile.seek(0x27fff) 18 | spiFile.write(nullData) 19 | 20 | spiFile.close 21 | bitFile.close 22 | 23 | -------------------------------------------------------------------------------- /verilator/scripts/extract_sig.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import fileinput 4 | 5 | in_sig = 0 6 | 7 | for line in fileinput.input(): 8 | if line.startswith("[TESTBENCH_END]"): 9 | in_sig = 0 10 | if in_sig: 11 | print(line.strip()) 12 | if line.startswith("[TESTBENCH_BEGIN]"): 13 | in_sig = 1 14 | 15 | -------------------------------------------------------------------------------- /verilator/signatures/README.md: -------------------------------------------------------------------------------- 1 | Folder where signatures are written by the testbench --------------------------------------------------------------------------------