-- )
165 | ?exec Method ?class-def ?unsealed
166 | Tcreate Last-class @ ,
167 | Current c.size @ here 3 cells - !
168 | Last-class c.size @ Current c.size +!
169 | \ | offset | Varlink | class |
170 | DOES> ( object1 -- object2 ) >object
171 | comp? IF ?dup 0= ?EXIT lit, T + H EXIT THEN
172 | dbg? IF t> + >t EXIT THEN
173 | +
174 | ;
175 |
176 | ' [ Alias [ immediate \ for debugging
177 | ' ] Alias ] \ for debugging
178 |
179 | \ -------------------------------------------------------------------------
180 | \ Target definitions
181 | \ -------------------------------------------------------------------------
182 | Target definitions Forth
183 |
184 | ' Class Alias Class
185 | ' ClassRoot Alias ClassRoot
186 | ' Method Alias Method
187 |
188 | Forth definitions
189 |
190 | \ ****************************************************************
191 | \ Examples for basic Objects: Cell and Point
192 | \ These can not be compiled here, because first the cross-compiler
193 | \ must have been completely loaded.
194 | \ ****************************************************************
195 | \ Target
196 | \
197 | \ Class Cell Cell definitions
198 | \ 1 Cell allot Cell seal
199 | \ Macro: @ ( obj -- n ) T @ H ;
200 | \ Macro: ! ( n obj -- ) T ! H ;
201 | \ : +! ( n obj -- ) +! ;
202 | \ : on ( obj -- ) on ;
203 | \ : off ( obj -- ) off ;
204 | \ : ? ( obj -- ) @ . ;
205 | \ Target
206 | \
207 | \ Class Point Point definitions
208 | \ Cell Attribute X
209 | \ Cell Attribute Y
210 | \ Point seal
211 | \ : set ( X Y obj -- ) swap over Self Y ! Self X ! ;
212 | \ : ? ( obj -- ) dup Point X ? Point Y ? ;
213 | \ Target
214 | \
215 | \ Point Object Punkt init: init-Punkt ( -- ) 1 2 Punkt set ;
216 | \
217 | \ ****************************************************************
218 | \ int16 with sign extension
219 | \ ****************************************************************
220 | \
221 | \ Class int16 int16 definitions
222 | \ 1 int16 allot int16 seal
223 | \ : @ ( addr -- n ) @ $FFFF and dup $8000 and IF $FFFF not or THEN ;
224 | \ Macro: ! ( n addr -- ) T ! H ;
225 | \ Target
226 | \
227 | \ int16 Object Dies \ an int16 variable in the data memory
228 | \ $200 int16 Constant Das \ an int16 variable at address $200
229 |
--------------------------------------------------------------------------------
/software/prolog.vhd:
--------------------------------------------------------------------------------
1 | --
2 | -- Program memory ROM implemented using a case statement.
3 | -- It is generated by the microCore cross compiler.
4 |
5 | LIBRARY IEEE;
6 | USE IEEE.STD_LOGIC_1164.ALL;
7 | USE IEEE.NUMERIC_STD.ALL;
8 | USE work.architecture_pkg.ALL;
9 |
10 | ENTITY program_rom IS PORT (
11 | addr : IN program_addr;
12 | data : OUT inst_bus
13 | ); END program_rom;
14 |
15 | ARCHITECTURE sim_model OF program_rom IS
16 |
17 | SUBTYPE rom_address IS NATURAL RANGE 0 TO 2**prog_addr_width-1;
18 |
19 | FUNCTION program(addr : rom_address) RETURN UNSIGNED IS
20 | BEGIN
21 | CASE addr IS
22 |
--------------------------------------------------------------------------------
/software/prolog_boot.vhd:
--------------------------------------------------------------------------------
1 | --
2 | -- Program memory ROM implemented using a case statement.
3 | -- Its content was generated by the microCore cross compiler.
4 | -- It will be statically synthesized into the design as cold bootrom.
5 |
6 | LIBRARY IEEE;
7 | USE IEEE.STD_LOGIC_1164.ALL;
8 | USE IEEE.NUMERIC_STD.ALL;
9 | USE work.architecture_pkg.ALL;
10 |
11 | ENTITY boot_rom IS PORT (
12 | addr : IN boot_addr_bus;
13 | data : OUT inst_bus
14 | ); END boot_rom;
15 |
16 | ARCHITECTURE sim_model OF boot_rom IS
17 |
18 | SUBTYPE rom_address IS NATURAL RANGE 0 TO 2**boot_addr_width-1;
19 |
20 | FUNCTION program(addr : rom_address) RETURN UNSIGNED IS
21 | BEGIN
22 | CASE addr IS
23 |
--------------------------------------------------------------------------------
/software/prolog_internal.vhd:
--------------------------------------------------------------------------------
1 | --
2 | -- Internal program memory RAM implemented using an array type.
3 | -- It is generated by the cross compiler.
4 |
5 | LIBRARY IEEE;
6 | USE IEEE.STD_LOGIC_1164.ALL;
7 | USE IEEE.NUMERIC_STD.ALL;
8 | USE work.architecture_pkg.ALL;
9 |
10 | ENTITY internal_program IS PORT (
11 | clk : IN STD_LOGIC;
12 | en : IN STD_LOGIC;
13 | we : IN STD_LOGIC;
14 | addr : IN program_addr;
15 | di : IN inst_bus;
16 | do : OUT inst_bus
17 | );
18 | ATTRIBUTE ram_style : STRING;
19 | ATTRIBUTE ram_style OF internal_program : ENTITY IS "block";
20 |
21 | END internal_program;
22 |
23 | ARCHITECTURE inference_model OF internal_program IS
24 |
25 | ATTRIBUTE syn_ramstyle : STRING;
26 |
27 | TYPE inst_ram IS ARRAY (0 TO 2**prog_addr_width-1) OF inst_bus;
28 |
29 | SIGNAL program : inst_ram
30 | := (
31 |
--------------------------------------------------------------------------------
/software/rs232_linux.fs:
--------------------------------------------------------------------------------
1 | \ ----------------------------------------------------------------------
2 | \ @file : rs232_linux.fs
3 | \ ----------------------------------------------------------------------
4 | \
5 | \ Last change: KS 27.03.2021 22:14:11
6 | \ @project: microForth/microCore
7 | \ @language: gforth_0.6.2
8 | \ @copyright (c): Free Software Foundation
9 | \ @original author: uho - Ulrich Hoffmann
10 | \ @contributor: ks - Klaus Schleisiek
11 | \
12 | \ @license: This file is part of microForth.
13 | \ microForth is free software for microCore that loads on top of Gforth;
14 | \ you can redistribute it and/or modify it under the terms of the
15 | \ GNU General Public License as published by the Free Software Foundation,
16 | \ either version 3 of the License, or (at your option) any later version.
17 | \ This program is distributed in the hope that it will be useful,
18 | \ but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | \ GNU General Public License for more details.
21 | \ You should have received a copy of the GNU General Public License
22 | \ along with this program. If not, see http://www.gnu.org/licenses/.
23 | \
24 | \ @brief : Terminal for gforth/R8C hacked by uho to run as an rs232
25 | \ interface under linux.
26 | \
27 | \ Version Author Date Changes
28 | \ uho 15-Feb-2009 initial version
29 | \ ks 10-Apr-2020 addition of the gforth_07x version.
30 | \ ----------------------------------------------------------------------
31 | Only Forth also definitions
32 |
33 | gforth_062 [IF] cr .( UART for gforth_062, 32 bit)
34 |
35 | require lib.fs
36 |
37 | [IFUNDEF] libc library libc libc.so.6 [THEN]
38 |
39 | libc tcgetattr int ptr (int) tcgetattr ( port termios -- r )
40 | libc tcsetattr int int ptr (int) tcsetattr ( port opt termios -- r )
41 | libc tcflow int int (int) tcflow ( port action -- r )
42 | libc ioctl int int ptr (int) ioctl ( d request ptr -- r )
43 | libc fileno ptr (int) fileno ( file* -- port )
44 |
45 | 4 4 2Constant int%
46 | $20 Constant NCCS
47 |
48 | struct
49 | int% field c_iflag
50 | int% field c_oflag
51 | int% field c_cflag
52 | int% field c_lflag
53 | char% NCCS * field c_line
54 | int% field c_ispeed
55 | int% field c_ospeed
56 | end-struct termios
57 |
58 | Create t_old termios %allot drop
59 | Create t_buf termios %allot drop
60 |
61 | 1 Constant B50
62 | 2 Constant B75
63 | 3 Constant B110
64 | 4 Constant B134
65 | 5 Constant B150
66 | 6 Constant B200
67 | 7 Constant B300
68 | 8 Constant B600
69 | 9 Constant B1200
70 | $A Constant B1800
71 | $B Constant B2400
72 | $C Constant B4800
73 | $D Constant B9600
74 | $E Constant B19200
75 | $F Constant B38400
76 | $1001 Constant B57600
77 | $1002 Constant B115200
78 | $30 Constant CS8 \ 8 bits/character
79 | $80 Constant CREAD \ input enable
80 | $400 Constant CSTOPB \ 2 stop bits
81 | $800 Constant CLOCAL \ don't check RS232 status lines
82 | 1 Constant IGNBRK \ ignore break
83 | 4 Constant IGNPAR \ ignore parity/framing errors
84 | 6 Constant VTIME
85 | 7 Constant VMIN
86 |
87 | : set-baud ( baud handle -- )
88 | fileno >r r@ t_old tcgetattr drop
89 | t_old t_buf termios %size move
90 | [ IGNBRK IGNPAR or ] Literal t_buf c_iflag !
91 | 0 t_buf c_oflag !
92 | [ CS8 CSTOPB or CREAD or CLOCAL or ] Literal or t_buf c_cflag !
93 | 0 t_buf c_lflag !
94 | 0 t_buf c_line 2dup VMIN + c! VTIME + c! \ return after every read, even if no char available
95 | &28800 t_buf c_cflag @ $F and lshift
96 | dup t_buf c_ispeed ! t_buf c_ospeed !
97 | r> 1 t_buf tcsetattr drop
98 | ;
99 | : reset-baud ( handle -- ) fileno 1 t_old tcsetattr drop ;
100 |
101 | [THEN] gforth_079 gforth_072 or [IF] cr .( UART for gforth_07x, 32/64 bit)
102 |
103 | require libcc.fs
104 |
105 | c-library serial
106 | \c #include
107 | \c #include
108 | \c #include
109 | \c #include
110 | \c #include
111 | \c #include
112 | \c #include
113 |
114 | c-function tcgetattr tcgetattr n a -- n ( port termios -- r )
115 | c-function tcsetattr tcsetattr n n a -- n ( port opt termios -- r )
116 | c-function cfmakeraw cfmakeraw a -- void ( termios -- )
117 | c-function cfsetispeed cfsetispeed a n -- n ( termios speed -- r )
118 | c-function cfsetospeed cfsetospeed a n -- n ( termios speed -- r )
119 | c-function tcflow tcflow n n -- n ( port action -- n )
120 | c-function ioctl ioctl n n a -- n ( port cmd ptr -- n )
121 | c-function setvbuf setvbuf a a n n -- n ( file* buf mode size -- r )
122 | end-c-library
123 |
124 | [IFDEF] android
125 | ' wfield: alias flagfield: ( offset -- offset' )
126 | ' w@ alias flag@
127 | ' w! alias flag!
128 | [ELSE]
129 | ' lfield: alias flagfield: ( offset -- offset' )
130 | ' l@ alias flag@
131 | ' l! alias flag!
132 | [THEN]
133 |
134 | begin-structure termios
135 | flagfield: c_iflag \ input mode flags
136 | flagfield: c_oflag \ output mode flags
137 | flagfield: c_cflag \ control mode flags
138 | flagfield: c_lflag \ local mode flags
139 | cfield: c_line
140 | 32 +field c_cc \ line discipline
141 | flagfield: c_ispeed \ input speed
142 | flagfield: c_ospeed \ output speed
143 | end-structure
144 |
145 | Create t_old termios allot
146 | Create t_buf termios allot
147 |
148 | 1 Constant B50
149 | 2 Constant B75
150 | 3 Constant B110
151 | 4 Constant B134
152 | 5 Constant B150
153 | 6 Constant B200
154 | 7 Constant B300
155 | 8 Constant B600
156 | 9 Constant B1200
157 | $A Constant B1800
158 | $B Constant B2400
159 | $C Constant B4800
160 | $D Constant B9600
161 | $E Constant B19200
162 | $F Constant B38400
163 | $1001 Constant B57600
164 | $1002 Constant B115200
165 | $1003 Constant B230400
166 | $1004 Constant B460800
167 | $1005 Constant B500000
168 | $1006 Constant B576000
169 | $1007 Constant B921600
170 | $1008 Constant B1000000
171 | $1009 Constant B1152000
172 | $100A Constant B1500000
173 | $100B Constant B2000000
174 | $100C Constant B2500000
175 | $100D Constant B3000000
176 | $100E Constant B3500000
177 | $100F Constant B4000000
178 | $30 Constant CS8
179 | $80 Constant CREAD
180 | $40 Constant CSTOPB
181 | $800 Constant CLOCAL
182 | $800 Constant IXANY
183 | 1 Constant IGNBRK
184 | 4 Constant IGNPAR
185 | $100 Constant NOCTTY
186 | $800 Constant NODELAY
187 | 5 Constant VTIME
188 | 6 Constant VMIN
189 |
190 | : set-baud ( baud handle -- )
191 | fileno >r r@ t_old tcgetattr ?ior
192 | t_old t_buf termios move
193 | t_buf cfmakeraw
194 | t_buf c_iflag dup flag@ CLOCAL or swap flag!
195 | t_buf over cfsetispeed ?ior
196 | t_buf swap cfsetospeed ?ior
197 | 0 t_buf c_line 2dup VMIN + c! VTIME + c! \ return after every read, even if no char available
198 | r> 0 t_buf tcsetattr ?ior
199 | ;
200 | : reset-baud ( handle -- ) fileno 0 t_old tcsetattr ?ior ;
201 |
202 | [THEN]
203 |
204 | 0 Value handle
205 |
206 | : open-port ( addr u -- ) r/w open-file throw to handle ;
207 |
208 | : close-port ( -- ) handle ?dup 0= ?EXIT close-file throw 0 TO handle ;
209 |
210 | &120 Constant #buf-length
211 | Create read-buf #buf-length chars allot
212 |
213 | : term-read ( -- u ) read-buf #buf-length handle read-file throw ;
214 |
215 | : term-flush ( -- ) handle flush-file throw ;
216 |
217 | : term-emit ( char -- ) handle emit-file throw ;
218 |
219 | : (term-type) ( addr u -- ) handle write-file throw term-flush ;
220 |
221 | Variable read-len 0 read-len !
222 |
223 | : term-key? ( -- flag ) read-len @ IF true EXIT THEN term-read dup read-len ! 0<> ;
224 |
225 | : term-key ( -- char )
226 | BEGIN term-key? UNTIL
227 | read-buf c@ -1 read-len +!
228 | read-buf char+ read-buf read-len @ cmove
229 | ;
230 | : Umbilical: ( baud -- ) \ e.g. B115200 Umbilical: /dev/ttyUSB0
231 | name open-port handle set-baud
232 | ;
233 |
--------------------------------------------------------------------------------
/software/rs232_macosx.fs:
--------------------------------------------------------------------------------
1 | \ ----------------------------------------------------------------------
2 | \ @file : rs232_macosx.fs
3 | \ ----------------------------------------------------------------------
4 | \
5 | \ Last change: KS 24.03.2021 17:53:45
6 | \ @project: microForth/microCore
7 | \ @language: gforth_0.6.2
8 | \ @copyright (c): Free Software Foundation
9 | \ @original author: uho - Ulrich Hoffmann
10 | \ @contributor:
11 | \
12 | \ @license: This file is part of microForth.
13 | \ microForth is free software for microCore that loads on top of Gforth;
14 | \ you can redistribute it and/or modify it under the terms of the
15 | \ GNU General Public License as published by the Free Software Foundation,
16 | \ either version 3 of the License, or (at your option) any later version.
17 | \ This program is distributed in the hope that it will be useful,
18 | \ but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | \ GNU General Public License for more details.
21 | \ You should have received a copy of the GNU General Public License
22 | \ along with this program. If not, see http://www.gnu.org/licenses/.
23 | \
24 | \ @brief : Terminal for gforth/R8C hacked by uho to run as an rs232
25 | \ interface under MAC-OS.
26 | \
27 | \ Version Author Date Changes
28 | \ uho 15-Feb-2009 initial version
29 | \ ----------------------------------------------------------------------
30 | Only Forth also definitions
31 |
32 | require lib.fs
33 |
34 | [IFUNDEF] libc library libc libc.dylib [THEN]
35 |
36 | libc tcgetattr int ptr (int) tcgetattr ( port termios -- r )
37 | libc tcsetattr int int ptr (int) tcsetattr ( port opt termios -- r )
38 | libc tcflow int int (int) tcflow ( port action -- r )
39 | libc ioctl int int ptr (int) ioctl ( d request ptr -- r )
40 | libc fileno ptr (int) fileno ( handle -- port )
41 |
42 | cell dup 2Constant int%
43 | 20 Constant NCCS
44 |
45 | struct
46 | int% field c_iflag
47 | int% field c_oflag
48 | int% field c_cflag
49 | int% field c_lflag
50 | char% NCCS * field c_line
51 | int% field c_ispeed
52 | int% field c_ospeed
53 | end-struct termios
54 |
55 | Create t_old termios %allot drop
56 | Create t_buf termios %allot drop
57 |
58 | $300 Constant CS8
59 | $800 Constant CREAD
60 | $8000 Constant CLOCAL
61 | 0 Constant CBAUD
62 | 1 Constant IGNBRK
63 | 4 Constant IGNPAR
64 | &17 Constant VTIME
65 | &16 Constant VMIN
66 | $4004667F Constant FIONREAD
67 |
68 | &19200 Constant B19200
69 | &38400 Constant B38400
70 | &57600 Constant B57600
71 | &115200 Constant B115200
72 |
73 | : set-baud ( baud handle -- )
74 | fileno >r r@ t_old tcgetattr drop
75 | t_old t_buf termios %size move
76 | [ IGNBRK IGNPAR or ] Literal t_buf c_iflag !
77 | 0 t_buf c_oflag !
78 | [ CS8 CREAD or CLOCAL or ] Literal t_buf c_cflag !
79 | 0 t_buf c_lflag !
80 | dup t_buf c_ispeed !
81 | t_buf c_ospeed !
82 | 0 t_buf c_line VMIN + c!
83 | 0 t_buf c_line VTIME + c!
84 | r> 1 t_buf tcsetattr drop
85 | ;
86 | : reset-baud ( handle -- ) fileno 1 t_old tcsetattr drop ;
87 |
88 | : check-read ( handle -- n ) fileno >r 0 sp@ r> FIONREAD rot ioctl
drop ;
89 |
90 | 0 Value handle
91 |
92 | : open-port ( addr u -- ) r/w open-file throw TO handle ;
93 |
94 | : term-read ( -- addr u ) pad handle check-read handle read-file throw pad swap ;
95 |
96 | : term-emit ( char -- ) handle emit-file throw ;
97 |
98 | : (term-type) ( addr u -- ) handle write-file throw ;
99 |
100 | : term-flush ( -- ) handle flush-file throw ;
101 |
102 | Create read-buf $400 chars allot
103 | Variable read-len 0 read-len !
104 |
105 | : term-key? ( -- flag )
106 | read-len @ IF true EXIT THEN
107 | term-read dup read-len ! read-buf swap chars cmove
108 | read-len @ 0<> ;
109 |
110 | : term-key ( -- char )
111 | BEGIN term-key? UNTIL
112 | read-buf c@ -1 read-len +!
113 | read-buf char+ read-buf read-len @ cmove
114 | ;
115 | : Umbilical: ( baud -- ) \ e.g. B115200 Umbilical: /dev/cu.usbserial
116 | name open-port handle set-baud
117 | ;
118 |
--------------------------------------------------------------------------------
/software/rs232_windows.fs:
--------------------------------------------------------------------------------
1 | \ ----------------------------------------------------------------------
2 | \ @file : rs232_windows.fs
3 | \ ----------------------------------------------------------------------
4 | \
5 | \ Last change: KS 24.03.2021 17:54:31
6 | \ @project: microForth/microCore
7 | \ @language: gforth_0.6.2
8 | \ @copyright (c): Free Software Foundation
9 | \ @original author: uho - Ulrich Hoffmann
10 | \ @contributor: ks - Klaus Schleisiek
11 | \
12 | \ @license: This file is part of microForth.
13 | \ microForth is free software for microCore that loads on top of Gforth;
14 | \ you can redistribute it and/or modify it under the terms of the
15 | \ GNU General Public License as published by the Free Software Foundation,
16 | \ either version 3 of the License, or (at your option) any later version.
17 | \ This program is distributed in the hope that it will be useful,
18 | \ but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | \ GNU General Public License for more details.
21 | \ You should have received a copy of the GNU General Public License
22 | \ along with this program. If not, see http://www.gnu.org/licenses/.
23 | \
24 | \ @brief : Terminal for gforth/R8C hacked by uho to run as an rs232
25 | \ cygwin interface under windows.
26 | \ This rs232-interface is unreliable and blocks infrequently
27 | \ due to Microsoft's infamous device drivers.
28 | \
29 | \ Version Author Date Changes
30 | \ uho 15-Feb-2009 initial version
31 | \ ks 10-Apr-2020 some code simplifications. Didn't help thou.
32 | \ ----------------------------------------------------------------------
33 | Only Forth also definitions
34 |
35 | require lib.fs
36 |
37 | library kernel32 kernel32
38 |
39 | kernel32 GetCommState int ptr (int) GetCommState ( handle addr -- r )
40 | kernel32 SetCommState int ptr (int) SetCommState ( handle addr -- r )
41 | kernel32 CreateFile ptr int int ptr int int ptr (int) CreateFileA ( name access share security disp attr temp -- handle )
42 | kernel32 WriteFile int ptr int ptr ptr (int) WriteFile ( handle data size &len &data -- flag )
43 | kernel32 ReadFile int ptr int ptr ptr (int) ReadFile ( handle data size &len &data -- flag )
44 | kernel32 SetCommTimeouts int ptr (int) SetCommTimeouts ( handle addr -- flag )
45 | kernel32 GetCommTimeouts int ptr (int) GetCommTimeouts ( handle addr -- flag )
46 | kernel32 CloseHandle int (int) CloseHandle ( handle -- flag )
47 | kernel32 SetupComm int int int (int) SetupComm ( handle #inq #outq -- flag )
48 |
49 | 4 4 2Constant int%
50 | 2 2 2Constant word%
51 |
52 | struct
53 | int% field DCBlength
54 | int% field BaudRate
55 | int% field flags
56 | word% field wReserved
57 | word% field XonLim
58 | word% field XoffLim
59 | char% field ByteSize
60 | char% field Parity
61 | char% field StopBits
62 | char% field XonChar
63 | char% field XoffChar
64 | char% field ErrorChar
65 | char% field EofChar
66 | char% field EvtChar
67 | word% field wReserved1
68 | end-struct DCB
69 |
70 | struct
71 | int% field ReadIntervalTimeout
72 | int% field ReadTotalTimeoutMultiplier
73 | int% field ReadTotalTimeoutConstant
74 | int% field WriteTotalTimeoutMultiplier
75 | int% field WriteTotalTimeoutConstant
76 | end-struct COMMTIMEOUTS
77 |
78 | Create t_buf DCB %allot drop
79 | Create timeouts COMMTIMEOUTS %allot drop
80 | &128 Constant #buf-size
81 |
82 | 0 Value handle
83 |
84 | $80000000 Constant GENERIC_READ
85 | $40000000 Constant GENERIC_WRITE
86 | 3 Constant OPEN_EXISTING
87 |
88 | : open-port ( addr u -- )
89 | tuck pad swap move 0 swap pad + c! \ 0 terminated string
90 | pad GENERIC_READ GENERIC_WRITE or 0 0 OPEN_EXISTING 0 0 CreateFile
91 | dup -1 = abort" serial port not available" TO handle
92 | handle #buf-size dup SetupComm drop
93 | ;
94 | : close-port ( -- )
95 | handle ?dup 0= ?EXIT
96 | CloseHandle 0= abort" can not close serial port"
97 | 0 TO handle
98 | ;
99 | &19200 Constant B19200
100 | &38400 Constant B38400
101 | &57600 Constant B57600
102 | &115200 Constant B115200
103 |
104 | : set-baud ( baud handle -- ) >r
105 | r@ timeouts GetCommTimeouts drop
106 | -1 timeouts ReadIntervalTimeout !
107 | 0 timeouts ReadTotalTimeoutMultiplier !
108 | 0 timeouts ReadTotalTimeoutConstant !
109 | 0 timeouts WriteTotalTimeoutMultiplier !
110 | 0 timeouts WriteTotalTimeoutConstant !
111 | r@ timeouts SetCommTimeouts drop
112 | t_buf DCB %size erase
113 | DCB %size t_buf DCBlength !
114 | $1011 t_buf flags !
115 | t_buf BaudRate !
116 | 8 t_buf ByteSize c!
117 | 2 t_buf StopBits c! \ 2 stop bits
118 | 0 t_buf Parity c! \ no parity
119 | r> t_buf SetCommState drop
120 | ;
121 | : reset-baud ( handle -- ) drop ;
122 |
123 | Create read-buf #buf-size 1+ chars allot \ 0-terminated string, therfore 1+
124 | Variable read-len
125 |
126 | : term-read ( -- addr u )
127 | handle read-buf #buf-size read-len 0 ReadFile drop
128 | read-buf read-len @
129 | ;
130 | : term-key? ( -- flag )
131 | read-len @ IF true EXIT THEN
132 | term-read dup read-len ! nip 0<>
133 | ;
134 | : term-key ( -- char )
135 | BEGIN term-key? 0= WHILE $80000 FOR NEXT REPEAT \ some waiting on 0, it does not work reliably otherwise
136 | read-buf c@ -1 read-len +!
137 | read-buf char+ read-buf read-len @ cmove
138 | ;
139 | Variable write-buf
140 | Variable write-len
141 |
142 | : (term-type) ( addr u -- ) handle -rot write-len 0 WriteFile drop ;
143 |
144 | : term-emit ( char -- ) write-buf c! write-buf 1 (term-type) ;
145 |
146 | : term-flush ( -- ) ;
147 |
148 | : Umbilical: ( baud -- ) \ e.g. B115200 Umbilical: COM3
149 | name open-port handle set-baud
150 | ;
151 |
--------------------------------------------------------------------------------
/software/sim.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 30.07.2022 23:00:10
3 | \
4 | \ microCore load screen for simulation.
5 | \ It produces program.mem for initialization of the program memory during simulation.
6 | \
7 | Only Forth also definitions hex
8 |
9 | [IFDEF] unpatch unpatch [ENDIF]
10 | [IFDEF] close-port close-port [ENDIF]
11 | [IFDEF] microcore microcore [ENDIF] Marker microcore
12 |
13 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
14 | include ../vhdl/architecture_pkg_sim.vhd
15 | include microcross.fs \ the cross-compiler
16 |
17 | Target new initialized \ go into target compilation mode and initialize target compiler
18 |
19 | 6 trap-addr code-origin
20 | 0 data-origin
21 |
22 | include constants.fs \ MicroCore Register addresses and bits
23 | library forth_lib.fs
24 |
25 | \ ----------------------------------------------------------------------
26 | \ Booting and TRAPs
27 | \ ----------------------------------------------------------------------
28 |
29 | : boot ( -- )
30 | $332211 #extern st @
31 | BEGIN REPEAT
32 | ;
33 |
34 | #reset TRAP: rst ( -- ) boot ; \ compile branch to boot at reset vector location
35 | #isr TRAP: isr ( -- ) di IRET ;
36 | #psr TRAP: psr ( -- ) pause ; \ reexecute the previous instruction
37 |
38 | end
39 |
40 | MEM-file program.mem cr .( sim.fs written to program.mem )
41 |
--------------------------------------------------------------------------------
/software/sim_break.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 04.08.2022 18:36:56
3 | \
4 | \ MicroCore load screen for simulating the umbilical's break function.
5 | \ Constant break has to be set to '1' in bench.vhd.
6 | \ Use wave signal script break.do in the simulator directory.
7 | \
8 | Only Forth also definitions
9 |
10 | [IFDEF] unpatch unpatch [ENDIF]
11 | [IFDEF] close-port close-port [ENDIF]
12 | [IFDEF] microcore microcore [ENDIF] Marker microcore
13 |
14 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
15 | include ../vhdl/architecture_pkg_sim.vhd
16 | include microcross.fs \ the cross-compiler
17 |
18 | \ Verbose on
19 |
20 | Target new initialized \ go into target compilation mode and initialize target compiler
21 |
22 | 8 trap-addr code-origin
23 | 0 data-origin
24 |
25 | include constants.fs \ microCore Register addresses and bits
26 | include debugger.fs
27 | library forth_lib.fs
28 | include multitask.fs
29 |
30 | Task Background
31 |
32 | Variable Counter
33 | Variable Rerun
34 |
35 | : bg_task ( -- ) 0 Counter ! 0 Rerun !
36 | BEGIN pause 1 Counter +! Dsu @ Rerun @
37 | 2dup or 0= IF Rerun on THEN
38 | and IF #c-bitout Ctrl ! THEN
39 | REPEAT
40 | ;
41 | : boot ( -- )
42 | 0 Rerun cell+ erase CALL INITIALIZATION
43 | Terminal Background ['] bg_task spawn
44 | BEGIN pause REPEAT
45 | ;
46 | #reset TRAP: rst ( -- ) boot ; \ compile branch to boot at reset vector location
47 | #psr TRAP: psr ( -- ) pause ; \ reexecute the previous instruction
48 | #break TRAP: break ( -- ) debugger ;
49 | #data! TRAP: data! ( dp n -- dp+1 ) swap st cell+ ; \ Data memory initialization
50 |
51 | end
52 |
53 | MEM-file program.mem cr .( sim_break.fs written to program.mem )
54 |
--------------------------------------------------------------------------------
/software/sim_core.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 02.04.2022 19:08:42
3 | \
4 | \ MicroCore load screen for coretest simulation.
5 | \ It produces program.mem for initialization of the program memory during simulation.
6 | \ Use wave signal script core.do in the simulator directory.
7 | \
8 | Only Forth also definitions
9 |
10 | [IFDEF] unpatch unpatch [ENDIF]
11 | [IFDEF] close-port close-port [ENDIF]
12 | [IFDEF] microcore microcore [ENDIF] Marker microcore
13 |
14 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
15 | include ../vhdl/architecture_pkg_sim.vhd
16 | include microcross.fs \ the cross-compiler
17 |
18 | \ Verbose on
19 |
20 | Target new initialized \ go into target compilation mode and initialize target compiler
21 |
22 | 9 trap-addr code-origin
23 | 0 data-origin
24 |
25 | include constants.fs \ MicroCore Register addresses and bits
26 | library forth_lib.fs
27 | include coretest.fs
28 |
29 | : boot ( -- ) CALL INITIALIZATION coretest BEGIN REPEAT ;
30 |
31 | \ ----------------------------------------------------------------------
32 | \ Booting and TRAPs
33 | \ ----------------------------------------------------------------------
34 |
35 | #reset TRAP: rst ( -- ) boot ; \ compile branch to coretest at reset vector location
36 | #isr TRAP: isr ( -- ) interrupt IRET ;
37 | #psr TRAP: psr ( -- ) #f-sema release ; \ matches coretest's test_sema
38 | #data! TRAP: data! ( dp n -- dp+ ) swap st cell+ ; \ Data memory initialization operator
39 |
40 | end
41 |
42 | MEM-file program.mem cr .( sim_core.fs written to program.mem )
43 |
--------------------------------------------------------------------------------
/software/sim_debug.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 02.10.2022 16:34:23
3 | \
4 | \ MicroCore load screen for simulating the debug umbilical.
5 | \ It produces program.mem for initialization of the program memory during simulation.
6 | \ Constant debug has to be set to '1' in bench.vhd.
7 | \ Use wave signal script debug.do in the simulator directory.
8 | \
9 | Only Forth also definitions
10 |
11 | [IFDEF] unpatch unpatch [ENDIF]
12 | [IFDEF] close-port close-port [ENDIF]
13 | [IFDEF] microcore microcore [ENDIF] Marker microcore
14 |
15 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
16 | include ../vhdl/architecture_pkg_sim.vhd
17 | include microcross.fs \ the cross-compiler
18 |
19 | Target new \ go into target compilation mode and initialize target compiler
20 |
21 | 3 trap-addr code-origin
22 | 0 data-origin
23 |
24 | include constants.fs \ microCore Register addresses and bits
25 |
26 | : boot ( -- )
27 | $6699 $1155 1 st cell+ !
28 | Debug-reg ld st ld over swap !
29 | BEGIN REPEAT
30 | ;
31 |
32 | #reset TRAP: rst ( -- ) boot ; \ compile branch to boot at reset vector location
33 | #isr TRAP: isr ( -- ) di IRET ;
34 | #psr TRAP: psr ( -- ) pause ; \ reexecute the previous instruction
35 |
36 | end
37 |
38 | MEM-file program.mem cr .( sim_debug.fs written to program.mem )
39 |
--------------------------------------------------------------------------------
/software/sim_download.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 02.10.2022 18:31:25
3 | \
4 | \ MicroCore load screen to simulate the umbilical download function.
5 | \ Either constant download or upload has to be set to '1' in bench.vhd.
6 | \ Use wave signal script download.do and upload.do in the simulator directory.
7 | \
8 | Only Forth also definitions
9 |
10 | [IFDEF] unpatch unpatch [ENDIF]
11 | [IFDEF] close-port close-port [ENDIF]
12 | [IFDEF] microcore microcore [ENDIF] Marker microcore
13 |
14 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
15 | include ../vhdl/architecture_pkg_sim.vhd
16 | include microcross.fs \ the cross-compiler
17 |
18 | Target new \ go into target compilation mode and initialize target compiler
19 |
20 | 3 trap-addr code-origin
21 | 0 data-origin
22 |
23 | include constants.fs \ microCore Register addresses and bits
24 |
25 | : boot ( -- )
26 | $2211 1 cells $20 FOR over swap st cell+ NEXT !
27 | [ H data_addr_width cache_addr_width u> T ] [IF]
28 | $8877 $6655 #extern st cell+ !
29 | [THEN]
30 | host@
31 | #c-bitout Ctrl !
32 | BEGIN REPEAT
33 | ;
34 |
35 | #reset TRAP: rst ( -- ) boot ; \ compile branch to boot at reset vector location
36 | #isr TRAP: isr ( -- ) di IRET ;
37 | #psr TRAP: psr ( -- ) pause ; \ reexecute the previous instruction
38 |
39 | end
40 |
41 | MEM-file program.mem cr .( sim_download.fs written to program.mem )
42 |
--------------------------------------------------------------------------------
/software/sim_handshake.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 10.05.2023 21:41:20
3 | \
4 | \ MicroCore load screen for simulating the host <-> target synchronization.
5 | \ Constant handshake has to be set to '1' in bench.vhd.
6 | \ Use wave signal script handshake.do in the simulator directory.
7 | \
8 | Only Forth also definitions
9 |
10 | [IFDEF] unpatch unpatch [ENDIF]
11 | [IFDEF] close-port close-port [ENDIF]
12 | [IFDEF] microcore microcore [ENDIF] Marker microcore
13 |
14 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
15 | include ../vhdl/architecture_pkg_sim.vhd
16 | include microcross.fs \ the cross-compiler
17 |
18 | Target new \ go into target compilation mode and initialize target compiler
19 |
20 | 8 trap-addr code-origin
21 | 0 data-origin
22 |
23 | include constants.fs \ microCore Register addresses and bits
24 | library forth_lib.fs
25 |
26 | Variable extern
27 |
28 | : boot ( -- ) \ handshake protocol from monitor.fs
29 | 0 extern ! #i-ext int-enable ei
30 | host@ drop
31 | BEGIN #warmboot host! host@ $3F5 = UNTIL
32 | BEGIN $305 host! host@ 0= UNTIL \ synchronise Host <-> Target communication
33 | BEGIN 0 host! host@ execute REPEAT \ the "monitor" loop
34 | ;
35 | : interrupt ( -- ) 1 extern +! ;
36 |
37 | #reset TRAP: rst ( -- ) boot ; \ compile branch to boot at reset vector location
38 | #isr TRAP: isr ( -- ) interrupt IRET ;
39 | #psr TRAP: psr ( -- ) pause ; \ reexecute the previous instruction
40 |
41 | end
42 |
43 | MEM-file program.mem cr .( sim_handshake.fs written to program.mem )
44 |
--------------------------------------------------------------------------------
/software/sim_progload.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 21.03.2021 18:57:11
3 | \
4 | \ MicroCore load screen to simulate program loading via the umbilical.
5 | \
6 | \ Constant progload has to be set to '1' in bench.vhd.
7 | \ CONSTANT MEM_file has to be set to "" in architecture_pkg_sim.vhd
8 | \ Use wave signal script progload.do in the simulator directory.
9 | \
10 | Only Forth also definitions
11 |
12 | [IFDEF] unpatch unpatch [ENDIF]
13 | [IFDEF] close-port close-port [ENDIF]
14 | [IFDEF] microcore microcore [ENDIF] Marker microcore
15 |
16 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
17 | include ../vhdl/architecture_pkg_sim.vhd
18 | include microcross.fs \ the cross-compiler
19 |
20 | Target new \ go into target compilation mode and initialize target compiler
21 |
22 | 0 code-origin
23 | 0 data-origin
24 |
25 | include constants.fs \ microCore Register addresses and bits
26 |
27 | ] $5555 4 BEGIN st ld REPEAT [
28 |
29 | end
30 |
31 | VHDL-file ../vhdl/program.vhd cr .( sim_progload.fs written to ../vhdl/program.vhd )
32 |
--------------------------------------------------------------------------------
/software/sim_template.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 02.10.2022 16:34:45
3 | \
4 | \ MicroCore load screen for simulation.
5 | \ It produces program.mem for initialization of the program memory during simulation.
6 | \ Use wave signal script xxxxxxxxx.do in the simulator directory.
7 | \
8 | Only Forth also definitions
9 |
10 | [IFDEF] unpatch unpatch [ENDIF]
11 | [IFDEF] close-port close-port [ENDIF]
12 | [IFDEF] microcore microcore [ENDIF] Marker microcore
13 |
14 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
15 | include ../vhdl/architecture_pkg_sim.vhd
16 | include microcross.fs \ the cross-compiler
17 |
18 | Target new initialized \ go into target compilation mode and initialize target compiler
19 |
20 | 8 trap-addr code-origin
21 | 0 data-origin
22 |
23 | include constants.fs \ microCore Register addresses and bits
24 | library forth_lib.fs
25 |
26 | \ ----------------------------------------------------------------------
27 | \ Interrupt
28 | \ ----------------------------------------------------------------------
29 |
30 | : interrupt ( -- ) Intflags @ drop ;
31 |
32 | \ ----------------------------------------------------------------------
33 | \ Booting and TRAPs
34 | \ ----------------------------------------------------------------------
35 |
36 | : boot ( -- )
37 | BEGIN REPEAT
38 | ;
39 |
40 | #reset TRAP: rst ( -- ) boot ; \ compile branch to boot at reset vector location
41 | #isr TRAP: isr ( -- ) interrupt IRET ;
42 | #psr TRAP: psr ( -- ) pause ; \ reexecute the previous instruction
43 | #does> TRAP: dodoes ( addr -- addr' ) ld cell+ swap BRANCH ; \ the DOES> runtime primitive
44 | #data! TRAP: data! ( dp n -- dp+1 ) swap st cell+ ; \ Data memory initialization
45 |
46 | end
47 |
48 | MEM-file program.mem cr .( written to program.mem )
49 |
--------------------------------------------------------------------------------
/software/sim_upload.fs:
--------------------------------------------------------------------------------
1 | \
2 | \ Last change: KS 04.10.2022 22:34:44
3 | \
4 | \ MicroCore load screen to simulate the umbilical upload function.
5 | \ Either constant download or upload has to be set to '1' in bench.vhd.
6 | \ Use wave signal script download.do and upload.do in the simulator directory.
7 | \
8 | Only Forth also definitions
9 |
10 | [IFDEF] unpatch unpatch [ENDIF]
11 | [IFDEF] close-port close-port [ENDIF]
12 | [IFDEF] microcore microcore [ENDIF] Marker microcore
13 |
14 | include extensions.fs \ Some System word (re)definitions for a more sympathetic environment
15 | include ../vhdl/architecture_pkg_sim.vhd
16 | include microcross.fs \ the cross-compiler
17 |
18 | Target new \ go into target compilation mode and initialize target compiler
19 |
20 | 3 trap-addr code-origin
21 | 0 data-origin
22 |
23 | include constants.fs \ microCore Register addresses and bits
24 |
25 | WITH_BYTES [IF]
26 |
27 | : boot ( -- ) 8 cells \ mem-addr on uCore
28 | BEGIN cld swap $11 = UNTIL 1+
29 | BEGIN cld swap $12 = UNTIL 1+
30 | BEGIN cld swap $13 = UNTIL 1+
31 | BEGIN cld swap $14 = UNTIL 1+
32 | BEGIN cld swap $15 = UNTIL 1+
33 | BEGIN cld swap $16 = UNTIL drop
34 | [ H data_addr_width cache_addr_width u> T ] [IF]
35 | #extern
36 | BEGIN cld swap $25 = UNTIL 1+
37 | BEGIN cld swap $26 = UNTIL 1+
38 | BEGIN cld swap $27 = UNTIL 1+
39 | BEGIN cld swap $28 = UNTIL drop
40 | [THEN]
41 | #c-bitout Ctrl !
42 | BEGIN REPEAT
43 | ;
44 | [ELSE] \ cell addressed
45 |
46 | : boot ( -- ) 8 cells \ mem-addr on uCore
47 | BEGIN ld swap $11 = UNTIL 1+
48 | BEGIN ld swap $12 = UNTIL 1+
49 | BEGIN ld swap $13 = UNTIL 1+
50 | BEGIN ld swap $14 = UNTIL drop
51 | [ H data_addr_width cache_addr_width u> T ] [IF]
52 | #extern
53 | BEGIN ld swap $25 = UNTIL 1+
54 | BEGIN ld swap $26 = UNTIL 1+
55 | BEGIN ld swap $27 = UNTIL 1+
56 | BEGIN ld swap $28 = UNTIL drop
57 | [THEN]
58 | #c-bitout Ctrl !
59 | BEGIN REPEAT
60 | ;
61 | [THEN]
62 |
63 | #reset TRAP: rst ( -- ) boot ; \ compile branch to boot at reset vector location
64 | #isr TRAP: isr ( -- ) di IRET ;
65 | #psr TRAP: psr ( -- ) pause ; \ reexecute the previous instruction
66 |
67 | end
68 |
69 | MEM-file program.mem cr .( sim_upload.fs written to program.mem )
70 |
--------------------------------------------------------------------------------
/software/task_lib.fs:
--------------------------------------------------------------------------------
1 | \ ----------------------------------------------------------------------
2 | \ @file : task_lib.fs
3 | \ ----------------------------------------------------------------------
4 | \
5 | \ Last change: KS 16.07.2022 17:46:29
6 | \ @project: microForth/microCore
7 | \ @language: gforth_0.6.2
8 | \ @copyright (c): Free Software Foundation
9 | \ @original author: ks - Klaus Schleisiek
10 | \ @contributor:
11 | \
12 | \ @license: This file is part of microForth.
13 | \ microForth is free software for microCore that loads on top of Gforth;
14 | \ you can redistribute it and/or modify it under the terms of the
15 | \ GNU General Public License as published by the Free Software Foundation,
16 | \ either version 3 of the License, or (at your option) any later version.
17 | \ This program is distributed in the hope that it will be useful,
18 | \ but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | \ GNU General Public License for more details.
21 | \ You should have received a copy of the GNU General Public License
22 | \ along with this program. If not, see http://www.gnu.org/licenses/.
23 | \
24 | \ @brief : A co-operative multitasker for microCore.
25 | \ It has been split up into two parts: multitask.fs and task_lib.fs
26 | \ To use the multitasker, tasks_addr_width must be > 0 in
27 | \ architecture_pkg.vhd
28 | \
29 | \ Version Author Date Changes
30 | \ 210 ks 02-May-2020 initial version
31 | \ 2200 ks 19-Oct-2020 library version, some simplifications
32 | \ 2400 ks 06-Jul-2022 Split up into multitask.fs and task_lib.fs
33 | \ ----------------------------------------------------------------------
34 | \ Semaphore methods
35 | \ ----------------------------------------------------------------------
36 | Target
37 |
38 | ~ : lock ( sema -- )
39 | BEGIN ld swap dup IF TCB - THEN
40 | WHILE dup #t-sema tcb! halt
41 | REPEAT
42 | TCB swap #s-task + st
43 | [ #s-count #s-task - ] Literal + inc
44 | ;
45 | ~ : stopped ( lfa -- lfa' ) [ H there 'stopped ! T ] go-next ;
46 |
47 | : message ( n -- ) \ redefine message
48 | TCB Terminal = IF message EXIT THEN
49 | #t-poll tcb! ['] stopped TCB ! halt \ msg# -> t-poll, stopped -> t-exec
50 | ;
51 | ~ : semaphore-available ( sema -- )
52 | >r Priority
53 | BEGIN next-task?
54 | WHILE dup RoundRobin = IF #t-link + @ THEN
55 | dup #t-sema + @ r@ =
56 | IF dup wake 0 over #t-sema + ! THEN
57 | REPEAT drop
58 | 0 r> #s-task + !
59 | ;
60 | ~ : force-unlock ( sema -- )
61 | dup cell+ dup dec @ IF drop EXIT THEN
62 | semaphore-available pause
63 | ;
64 | ~ : unlock ( sema -- ) dup @ TCB - IF #not-my-semaphore message THEN force-unlock ;
65 |
66 | ~ : wait ( sema -- ) \ can be used with SIGNAL executed inside interrupt servers
67 | TCB over st #s-count + \ lock semaphor
68 | BEGIN ld swap \ count > 0?
69 | IF dec 0 swap ! EXIT THEN \ decrement count and release semaphor
70 | halt \ wait for signal event
71 | REPEAT
72 | ;
73 | : signal ( sema -- ) dup #s-count + inc @ ?dup IF wake THEN ;
74 |
75 | \ ----------------------------------------------------------------------
76 | \ Task management
77 | \ ----------------------------------------------------------------------
78 |
79 | ~ : task-used? ( task-number -- f )
80 | >r Priority #t-link + @
81 | BEGIN dup RoundRobin = IF #t-link + @ THEN
82 | #t-dsp + ld swap dsp>task r@ = IF rdrop EXIT THEN
83 | [ #t-link #t-dsp - ] Literal + @ dup RRLink @ =
84 | UNTIL drop rdrop False
85 | ;
86 | : get-task-number ( -- task-number )
87 | #tasks BEGIN 1- dup task-used? 0= ?EXIT dup 0= UNTIL
88 | #all-tasks-busy message
89 | ;
90 | : schedule ( task newtask -- ) \ link newtask into task list after task
91 | ['] go-next over ! >r
92 | get-task-number task>dsp r@ #t-dsp + !
93 | dup #t-link + @ r@ #t-link + ! r@ swap #t-link + !
94 | 0 r> #t-sema + !
95 | ;
96 | ~ : spawn ( task newtask xt -- ) >r tuck schedule r> activate ;
97 |
98 | ~ : unlock-semaphores ( task -- ) \ used by deactive to free semaphores owned by task
99 | >r Sema-link @
100 | BEGIN ?dup
101 | WHILE dup #s-task + @ r@ =
102 | IF 1 over #s-count + ! dup force-unlock THEN
103 | #s-link + @
104 | REPEAT rdrop
105 | ;
106 | : deactivate ( task -- )
107 | ['] go-next over !
108 | dup unlock-semaphores
109 | 0 over #t-sema + !
110 | TCB - ?EXIT
111 | TCB #t-link +
112 | GOTO go-next
113 | ;
114 | ~ : previous-task ( task -- task-1 )
115 | >r Priority
116 | BEGIN dup RRLink @ = IF drop rdrop #task-not-linked message EXIT THEN
117 | dup #t-link + @
118 | over RoundRobin = IF nip dup #t-link + @ THEN
119 | r@ = IF rdrop EXIT THEN #t-link + @
120 | REPEAT
121 | ;
122 | : cancel ( task -- )
123 | dup previous-task
124 | over #t-link + @ swap #t-link + ! \ link task out of task list
125 | dup RRLink @ = IF dup #t-link + @ RRLink ! THEN \ Move RoundRobin Pointer as well
126 | deactivate
127 | ;
128 | \ ----------------------------------------------------------------------
129 | \ Polling services without and with time limit.
130 | \
131 | \ Polling services have been added for performance reasons, because
132 | \ a task does not need to be woken up in order to check for an event.
133 | \
134 | \ xt ist the execution token of a word, that checks some condition
135 | \ returning True when the condition is met.
136 | \ ----------------------------------------------------------------------
137 |
138 | ~ : poll-exec ( xt t-exec -- ) TCB st #t-poll + ! halt ;
139 |
140 | ~ : do-poll ( lfa -- lfa' ) [ H there 'do-poll ! T ]
141 | dup [ #t-poll #t-link - ] Literal + @ execute
142 | 0= ?GOTO go-next GOTO do-wake
143 | ;
144 | : poll ( xt -- ) ['] do-poll poll-exec ;
145 |
146 | ~ : do-time ( lfa -- lfa' ) [ H there 'do-time ! T ]
147 | dup [ #t-time #t-link - ] Literal + @
148 | time? 0= ?GOTO go-next
149 | 0 over [ #t-time #t-link - ] Literal + ! \ reset #t-time field
150 | GOTO do-wake
151 | ;
152 | ~ : do-poll-tmax ( lfa -- lfa' ) [ H there 'do-poll-tmax ! T ]
153 | dup [ #t-poll #t-link - ] Literal + @ execute
154 | ?GOTO do-wake do-time
155 | ;
156 | : poll-tmax ( xt ticks -- f ) \ true when condition met, false when timeout
157 | time + #t-time tcb! ['] do-poll-tmax poll-exec #t-time tcb@ 0<>
158 | ;
159 | \ ----------------------------------------------------------------------
160 | \ Redefining forth_lib.fs' Time-reg based delays for the multitasker
161 | \ ----------------------------------------------------------------------
162 |
163 | : continue ( time -- ) #t-time tcb! ['] do-time TCB ! halt ;
164 |
165 | : sleep ( ticks -- ) ahead continue ;
166 |
167 | \ ----------------------------------------------------------------------
168 | \ Catch and throw for a multitasking environment
169 | \ ----------------------------------------------------------------------
170 |
171 | ~ : rstack> ( -- rsp ) Rsp @ ; \ A call in order to push TOR into the return stack memory
172 |
173 | ~ : catch ( xt -- error# | 0 ) \ Return address is already on rstack
174 | Dsp @ >r ( xt ) \ Save data stack pointer, xt fills NOS slot
175 | #t-catch tcb@ >r ( xt ) \ Save previous #t-catch
176 | rstack> #t-catch tcb! ( xt ) \ Fill TOR and set #t-catch to RSP
177 | execute ( ) \ Execute the word passed on the stack
178 | r> #t-catch tcb! ( ) \ Restore previous #t-catch
179 | rdrop ( ) \ Discard saved stack pointer
180 | 0 ( 0 ) \ Signify normal completion
181 | ;
182 | : throw ( error# -- ) \ Returns to context saved by CATCH
183 | ?dup 0= ?EXIT \ Don't throw 0
184 | #t-catch tcb@ ?dup 0= IF #catch-not-initialized message THEN
185 | >rstack ( err# ) \ Return to saved return stack context
186 | r> #t-catch tcb! ( err# ) \ Restore previous #t-catch
187 | r> swap >r ( saved-dsp ) \ save err# temporarily on rstack
188 | >dstack r> ( err# ) \ Change stack pointer
189 | ; \ The final EXIT will return to the caller of CATCH, because the return stack has
190 | \ been restored to the state that existed when CATCH was executed.
191 |
192 |
--------------------------------------------------------------------------------
/software/umbilical.fs:
--------------------------------------------------------------------------------
1 | \ ----------------------------------------------------------------------
2 | \ @file : umbilical.fs
3 | \ ----------------------------------------------------------------------
4 | \
5 | \ Last change: KS 10.04.2021 19:43:21
6 | \ @project: microForth/microCore
7 | \ @language: gforth_0.6.2
8 | \ @copyright (c): Free Software Foundation
9 | \ @original author: ks - Klaus Schleisiek
10 | \ @contributor:
11 | \
12 | \ @license: This file is part of microForth.
13 | \ microForth is free software for microCore that loads on top of Gforth;
14 | \ you can redistribute it and/or modify it under the terms of the
15 | \ GNU General Public License as published by the Free Software Foundation,
16 | \ either version 3 of the License, or (at your option) any later version.
17 | \ This program is distributed in the hope that it will be useful,
18 | \ but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | \ GNU General Public License for more details.
21 | \ You should have received a copy of the GNU General Public License
22 | \ along with this program. If not, see http://www.gnu.org/licenses/.
23 | \
24 | \ @brief : This is the top level configuration file for the rs232 interface.
25 | \ Depending on your host's OS you have to comment-in the
26 | \ appropriate driver and fill in the name of the actual
27 | \ rs232 interface used.
28 | \
29 | \ Version Author Date Changes
30 | \ 210 ks 14-Jun-2020 initial version
31 | \ ----------------------------------------------------------------------
32 | SIMULATION [NOTIF]
33 |
34 | include rs232_linux.fs B115200 Umbilical: /dev/ttyUSB0
35 | \ include rs232_windows.fs B115200 Umbilical: COM3
36 | \ include rs232_macosx.fs B115200 Umbilical: /dev/cu.usbserial
37 |
38 | [THEN]
39 |
--------------------------------------------------------------------------------
/software/vhdl.fs:
--------------------------------------------------------------------------------
1 | \ ----------------------------------------------------------------------
2 | \ @file : vhdl.fs
3 | \ ----------------------------------------------------------------------
4 | \
5 | \ Last change: KS 01.03.2022 18:48:14
6 | \ @project: microForth/microCore
7 | \ @language: gforth_0.6.2
8 | \ @copyright (c): Free Software Foundation
9 | \ @original author: ks - Klaus Schleisiek
10 | \ @contributor:
11 | \
12 | \ @license: This file is part of microForth.
13 | \ microForth is free software for microCore that loads on top of Gforth;
14 | \ you can redistribute it and/or modify it under the terms of the
15 | \ GNU General Public License as published by the Free Software Foundation,
16 | \ either version 3 of the License, or (at your option) any later version.
17 | \ This program is distributed in the hope that it will be useful,
18 | \ but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | \ GNU General Public License for more details.
21 | \ You should have received a copy of the GNU General Public License
22 | \ along with this program. If not, see http://www.gnu.org/licenses/.
23 | \
24 | \ @brief : A simplistic VHDL interpreter for importing microCore
25 | \ architecture parameters into the cross compiler environment
26 | \ including e.g. bus widths and opcodes. To this end
27 | \ architecture_pkg.vhd will be loaded during cross compilation.
28 | \ Architecture_pkg has been written in a peculiar way so that
29 | \ it can be interpreted by the VHDL simulator, the
30 | \ VHDL synthesizer as well as the Forth cross compiler.
31 | \ When loaded by the cross compiler, code between --~ up to
32 | \ --~-- will be skipped.
33 | \
34 | \ Version Author Date Changes
35 | \ 210 ks 14-Jun-2020 initial version
36 | \ 2200 ks 15-Dec-2020 more literal number formats
37 | \ ----------------------------------------------------------------------
38 | \ E.g. the following VHDL expressions will be interpreted by Forth:
39 | \
40 | \ CONSTANT WITH_MULT : BOOLEAN := false;
41 | \ CONSTANT data_width : NATURAL := 16;
42 | \ CONSTANT addr_rstack : NATURAL := 16#C00#;
43 | \ CONSTANT flag_reg : INTEGER := -2;
44 | \ CONSTANT op_NOOP : byte := "00000000";
45 | \ CONSTANT op_NOOP : byte := X"00";
46 | \ CONSTANT video_rate : REAL := 55.0;
47 | \ ----------------------------------------------------------------------
48 | Forth definitions
49 |
50 | ' \ Alias -- immediate
51 |
52 | : base>number ( addr len -- n ) over c@
53 | [char] ' case? IF 1 /string drop c@ [char] 1 = EXIT THEN
54 | [char] " case? IF 1 /string [char] " token binary s>number drop EXIT THEN
55 | [char] O case? IF 1 /string [char] " token octal s>number drop EXIT THEN
56 | [char] X = IF 1 /string [char] " token hex s>number drop EXIT THEN
57 | 2dup [char] # scan dup \ is it a NATURAL with base prefix?
58 | IF 2>r [char] # token decimal s>number drop Base !
59 | 2r> [char] # token s>number drop
60 | EXIT THEN 2drop \ its a decimal number
61 | BL token decimal s>number drop
62 | ;
63 | : VHDL-number ( -- n ) Base save BL skip-input [char] ; parse base>number ;
64 |
65 | : dec_parameter ( -- n ) Base save BL skip-input [char] ; parse decimal s>number drop ;
66 |
67 | Vocabulary --VHDL --VHDL definitions
68 |
69 | 1 Constant STD_LOGIC
70 | 1 Constant byte
71 | 1 Constant NATURAL
72 | 1 Constant INTEGER
73 | 2 Constant BOOLEAN
74 | 3 Constant REAL
75 |
76 | : STD_LOGIC_VECTOR ( -- type ) postpone ( byte ; \ )
77 | : UNSIGNED ( -- type ) postpone ( byte ; \ )
78 |
79 | : CONSTANT ( -- ) 0 Constant ;
80 |
81 | : vhdl-types ( type -- n )
82 | 1 case? IF VHDL-number EXIT THEN
83 | 2 case? IF [char] ; word count evaluate EXIT THEN \ for conditional compilation
84 | 3 case? IF dec_parameter &10 / EXIT THEN
85 | abort" unknown type"
86 | ;
87 | : := ( type -- ) Base save vhdl-types here cell- ! ; \ patch constant created before
88 |
89 | : --~ ( ccc~ -- ) [char] ~ scan-input ; \ ~
90 |
91 | : --Forth ( ccc~ -- ) Forth --~ ;
92 |
93 | ' \ Alias --
94 | ' noop Alias ;
95 | ' noop Alias :
96 |
97 | Forth definitions
98 |
--------------------------------------------------------------------------------
/synplify/get_version.tcl:
--------------------------------------------------------------------------------
1 |
2 |
--------------------------------------------------------------------------------
/synplify/microCore.fdc:
--------------------------------------------------------------------------------
1 |
2 | ###==== BEGIN Header
3 |
4 | # Synopsys, Inc. constraint file
5 | # by Synplify Pro (R), M-2017.03L-SP1-1 FDC Constraint Editor
6 |
7 | # Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
8 | # These sections are generated from SCOPE spreadsheet tabs.
9 |
10 | ###==== END Header
11 |
12 | ###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
13 | ###==== END Collections
14 |
15 | ###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
16 | create_clock -name {clk} {p:clock} -period {100}
17 |
18 | ###==== END Clocks
19 |
20 | ###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
21 | ###==== END "Generated Clocks"
22 |
23 | ###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
24 | ###==== END Inputs/Outputs
25 |
26 | ###==== BEGIN Registers - (Populated from tab in SCOPE, do not edit)
27 | ###==== END Registers
28 |
29 | ###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
30 | ###==== END "Delay Paths"
31 |
32 | ###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
33 | ###==== END Attributes
34 |
35 | ###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
36 | ###==== END "I/O Standards"
37 |
38 | ###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
39 | ###==== END "Compile Points"
40 |
41 |
--------------------------------------------------------------------------------
/synplify/microCore.prj:
--------------------------------------------------------------------------------
1 | #-- Synopsys, Inc.
2 | #-- Version N-2018.03L-SP1-1
3 | #-- Project file D:\technik\microcore\microCore\synplify\microCore.prj
4 | #-- Written on Tue Mar 30 23:39:08 2021
5 |
6 |
7 | #project files
8 | add_file -vhdl -lib work "../vhdl/functions_pkg.vhd"
9 | add_file -vhdl -lib work "../vhdl/architecture_pkg.vhd"
10 | add_file -vhdl -lib work "../vhdl/uArithmetic.vhd"
11 | add_file -vhdl -lib work "../vhdl/uCntrl.vhd"
12 | add_file -vhdl -lib work "../vhdl/uart.vhd"
13 | add_file -vhdl -lib work "../vhdl/debugger.vhd"
14 | add_file -vhdl -lib work "../vhdl/bootload.vhd"
15 | add_file -vhdl -lib work "../vhdl/uProgmem.vhd"
16 | add_file -vhdl -lib work "../vhdl/uCore.vhd"
17 | add_file -vhdl -lib work "../vhdl/uDatacache.vhd"
18 | add_file -vhdl -lib work "../vhdl/external_SRAM.vhd"
19 | add_file -vhdl -lib work "../vhdl/fpga.vhd"
20 | add_file -fpga_constraint "microCore.fdc"
21 |
22 | #implementation: "synplify"
23 | impl -add synplify -type fpga
24 |
25 | #implementation attributes
26 | set_option -vlog_std sysv
27 | set_option -project_relative_includes 1
28 |
29 | #device options
30 | set_option -technology LATTICE-XP2
31 | set_option -part LFXP2_8E
32 | set_option -package QN208C
33 | set_option -speed_grade -5
34 | set_option -part_companion ""
35 |
36 | #compilation/mapping options
37 | set_option -top_module "fpga"
38 |
39 | # hdl_compiler_options
40 | set_option -distributed_compile 0
41 |
42 | # mapper_without_write_options
43 | set_option -frequency 25
44 | set_option -auto_constrain_io 1
45 | set_option -default_enum_encoding onehot
46 | set_option -srs_instrumentation 1
47 |
48 | # mapper_options
49 | set_option -write_verilog 0
50 | set_option -write_vhdl 0
51 |
52 | # Lattice XP
53 | set_option -maxfan 1000
54 | set_option -disable_io_insertion 0
55 | set_option -retiming 0
56 | set_option -pipe 0
57 | set_option -forcegsr auto
58 | set_option -fix_gated_and_generated_clocks 1
59 | set_option -rw_check_on_ram 1
60 | set_option -update_models_cp 0
61 | set_option -syn_edif_array_rename 1
62 | set_option -Write_declared_clocks_only 1
63 |
64 | # NFilter
65 | set_option -no_sequential_opt 0
66 |
67 | # sequential_optimization_options
68 | set_option -symbolic_fsm_compiler 0
69 |
70 | # Compiler Options
71 | set_option -compiler_compatible 0
72 | set_option -resource_sharing 0
73 | set_option -multi_file_compilation_unit 1
74 |
75 | # Compiler Options
76 | set_option -auto_infer_blackbox 1
77 |
78 | #automatic place and route (vendor) options
79 | set_option -write_apr_constraint 1
80 |
81 | #set result format/file last
82 | project -result_file "./microCore.edn"
83 | impl -active "synplify"
84 |
--------------------------------------------------------------------------------
/vhdl/architectures/12/uDatacache.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_cell.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 01.11.2022 19:01:28
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 17-Jun-2022 byte addressing using byte_addr_width
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | make_sim_mem: IF SIMULATION GENERATE
70 |
71 | internal_data_mem: internal_dpram
72 | GENERIC MAP (data_width, cache_size, "no_rw_check", DMEM_file)
73 | PORT MAP (
74 | clk => clk,
75 | ena => enable,
76 | wea => write,
77 | addra => addr(cache_addr_width-1 DOWNTO 0),
78 | dia => wdata,
79 | doa => rdata,
80 | -- dma port
81 | enb => dma_enable,
82 | web => dma_write,
83 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
84 | dib => dma_wdata,
85 | dob => dma_rdata
86 | );
87 |
88 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
89 | -- instantiate FPGA specific IP for cell addressed memory here:
90 |
91 | internal_data_mem: internal_dpram
92 | GENERIC MAP (data_width, cache_size, "no_rw_check")
93 | PORT MAP (
94 | clk => clk,
95 | ena => enable,
96 | wea => write,
97 | addra => addr(cache_addr_width-1 DOWNTO 0),
98 | dia => wdata,
99 | doa => rdata,
100 | -- dma port
101 | enb => dma_enable,
102 | web => dma_write,
103 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
104 | dib => dma_wdata,
105 | dob => dma_rdata
106 | );
107 |
108 | END GENERATE make_syn_mem;
109 |
110 | END rtl;
111 |
112 | -- append FPGA specific IP for byte or cell addressed memory here
113 |
--------------------------------------------------------------------------------
/vhdl/architectures/16/uDatacache.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_cell.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 12.06.2023 23:37:58
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 17-Jun-2022 byte addressing using byte_addr_width
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | make_sim_mem: IF SIMULATION GENERATE
70 |
71 | internal_data_mem: internal_dpram
72 | GENERIC MAP (data_width, cache_size, "no_rw_check", DMEM_file)
73 | PORT MAP (
74 | clk => clk,
75 | ena => enable,
76 | wea => write,
77 | addra => addr(cache_addr_width-1 DOWNTO 0),
78 | dia => wdata,
79 | doa => rdata,
80 | -- dma port
81 | enb => dma_enable,
82 | web => dma_write,
83 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
84 | dib => dma_wdata,
85 | dob => dma_rdata
86 | );
87 |
88 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
89 | -- instantiate FPGA specific IP for cell addressed memory here:
90 |
91 | internal_data_mem: internal_dpram
92 | GENERIC MAP (data_width, cache_size, "no_rw_check")
93 | PORT MAP (
94 | clk => clk,
95 | ena => enable,
96 | wea => write,
97 | addra => addr(cache_addr_width-1 DOWNTO 0),
98 | dia => wdata,
99 | doa => rdata,
100 | -- dma port
101 | enb => dma_enable,
102 | web => dma_write,
103 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
104 | dib => dma_wdata,
105 | dob => dma_rdata
106 | );
107 |
108 | END GENERATE make_syn_mem;
109 |
110 | END rtl;
111 |
112 | -- append FPGA specific IP for byte or cell addressed memory here
113 |
--------------------------------------------------------------------------------
/vhdl/architectures/16b/uDatacache.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_16b.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 06.07.2023 17:35:15
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 03-Nov-2022 byte addressing using byte_addr_width > 0
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | byte_access_proc : PROCESS(uBus, mem_rdata, dma_mem, dma_mem_rdata)
70 | BEGIN
71 |
72 | mem_wdata <= wdata;
73 | rdata <= mem_rdata;
74 | bytes_en <= (OTHERS => '1');
75 |
76 | dma_mem_wdata <= dma_wdata;
77 | dma_rdata <= dma_mem_rdata;
78 | dma_bytes_en <= (OTHERS => '1');
79 |
80 | -- 16 bit system
81 | IF byte_addr_width = 1 THEN
82 | IF bytes = 1 THEN -- byte access
83 | mem_wdata <= wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0);
84 | bytes_en <= "01";
85 | rdata <= resize(mem_rdata(07 DOWNTO 0), data_width);
86 | IF addr(0) = '1' THEN
87 | bytes_en <= "10";
88 | rdata <= resize(mem_rdata(15 DOWNTO 8), data_width);
89 | END IF;
90 | dma_mem_wdata <= dma_wdata(7 DOWNTO 0) & dma_wdata(7 DOWNTO 0);
91 | dma_bytes_en <= "01";
92 | dma_rdata <= resize(dma_mem_rdata(07 DOWNTO 0), data_width);
93 | IF dma_addr(0) = '1' THEN
94 | dma_bytes_en <= "10";
95 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 8), data_width);
96 | END IF;
97 | END IF;
98 | END IF;
99 |
100 | -- 32 bit system
101 | IF byte_addr_width = 2 THEN
102 | IF bytes = 1 THEN -- byte access
103 | mem_wdata <= wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0);
104 | CASE addr(1 DOWNTO 0) IS
105 | WHEN "00" => bytes_en <= "0001";
106 | rdata <= resize(mem_rdata(07 DOWNTO 00), data_width);
107 | WHEN "01" => bytes_en <= "0010";
108 | rdata <= resize(mem_rdata(15 DOWNTO 08), data_width);
109 | WHEN "10" => bytes_en <= "0100";
110 | rdata <= resize(mem_rdata(23 DOWNTO 16), data_width);
111 | WHEN "11" => bytes_en <= "1000";
112 | rdata <= resize(mem_rdata(31 DOWNTO 24), data_width);
113 | WHEN OTHERS => NULL;
114 | END CASE;
115 | dma_mem_wdata <= dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0);
116 | CASE dma_addr(1 DOWNTO 0) IS
117 | WHEN "00" => dma_bytes_en <= "0001";
118 | dma_rdata <= resize(dma_mem_rdata(07 DOWNTO 00), data_width);
119 | WHEN "01" => dma_bytes_en <= "0010";
120 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 08), data_width);
121 | WHEN "10" => dma_bytes_en <= "0100";
122 | dma_rdata <= resize(dma_mem_rdata(23 DOWNTO 16), data_width);
123 | WHEN "11" => dma_bytes_en <= "1000";
124 | dma_rdata <= resize(dma_mem_rdata(31 DOWNTO 24), data_width);
125 | WHEN OTHERS => NULL;
126 | END CASE;
127 | ELSIF bytes = 2 THEN -- word access
128 | mem_wdata <= wdata(15 DOWNTO 0) & wdata(15 DOWNTO 0);
129 | bytes_en <= "0011";
130 | rdata <= resize(mem_rdata(15 DOWNTO 0), data_width);
131 | IF addr(1) = '1' THEN
132 | bytes_en <= "1100";
133 | rdata <= resize(mem_rdata(31 DOWNTO 16), data_width);
134 | END IF;
135 | dma_mem_wdata <= dma_wdata(15 DOWNTO 0) & dma_wdata(15 DOWNTO 0);
136 | dma_bytes_en <= "0011";
137 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 0), data_width);
138 | IF dma_addr(1) = '1' THEN
139 | dma_bytes_en <= "1100";
140 | dma_rdata <= resize(dma_mem_rdata(31 DOWNTO 16), data_width);
141 | END IF;
142 | END IF;
143 | END IF;
144 |
145 | END PROCESS byte_access_proc;
146 |
147 | make_sim_mem: IF SIMULATION GENERATE
148 |
149 | internal_data_mem: internal_dpbram
150 | GENERIC MAP (data_width, cache_size, byte_addr_width, "no_rw_check", DMEM_file)
151 | PORT MAP (
152 | clk => clk,
153 | ena => enable,
154 | wea => write,
155 | bytea => bytes_en,
156 | addra => addr(cache_addr_width-1 DOWNTO byte_addr_width),
157 | dia => mem_wdata,
158 | doa => mem_rdata,
159 | -- dma port
160 | enb => dma_enable,
161 | web => dma_write,
162 | byteb => dma_bytes_en,
163 | addrb => dma_addr(cache_addr_width-1 DOWNTO byte_addr_width),
164 | dib => dma_mem_wdata,
165 | dob => dma_mem_rdata
166 | );
167 |
168 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
169 | -- instantiate FPGA specific IP for byte addressed memory here:
170 |
171 | internal_data_mem: internal_dpbram
172 | GENERIC MAP (data_width, cache_size, byte_addr_width, "rw_check")
173 | PORT MAP (
174 | clk => clk,
175 | ena => enable,
176 | wea => write,
177 | bytea => bytes_en,
178 | addra => addr(cache_addr_width-1 DOWNTO byte_addr_width),
179 | dia => mem_wdata,
180 | doa => mem_rdata,
181 | -- dma port
182 | enb => dma_enable,
183 | web => dma_write,
184 | byteb => dma_bytes_en,
185 | addrb => dma_addr(cache_addr_width-1 DOWNTO byte_addr_width),
186 | dib => dma_mem_wdata,
187 | dob => dma_mem_rdata
188 | );
189 |
190 | END GENERATE make_syn_mem;
191 |
192 | END rtl;
193 |
194 | -- append FPGA specific IP for byte or cell addressed memory here
195 |
--------------------------------------------------------------------------------
/vhdl/architectures/27/uDatacache.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_cell.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 15.07.2023 12:03:14
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 17-Jun-2022 byte addressing using byte_addr_width
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | make_sim_mem: IF SIMULATION GENERATE
70 |
71 | internal_data_mem: internal_dpram
72 | GENERIC MAP (data_width, cache_size, "no_rw_check", DMEM_file)
73 | PORT MAP (
74 | clk => clk,
75 | ena => enable,
76 | wea => write,
77 | addra => addr(cache_addr_width-1 DOWNTO 0),
78 | dia => wdata,
79 | doa => rdata,
80 | -- dma port
81 | enb => dma_enable,
82 | web => dma_write,
83 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
84 | dib => dma_wdata,
85 | dob => dma_rdata
86 | );
87 |
88 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
89 | -- instantiate FPGA specific IP for cell addressed memory here:
90 |
91 | internal_data_mem: internal_dpram
92 | GENERIC MAP (data_width, cache_size, "no_rw_check")
93 | PORT MAP (
94 | clk => clk,
95 | ena => enable,
96 | wea => write,
97 | addra => addr(cache_addr_width-1 DOWNTO 0),
98 | dia => wdata,
99 | doa => rdata,
100 | -- dma port
101 | enb => dma_enable,
102 | web => dma_write,
103 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
104 | dib => dma_wdata,
105 | dob => dma_rdata
106 | );
107 |
108 | END GENERATE make_syn_mem;
109 |
110 | END rtl;
111 |
112 | -- append FPGA specific IP for byte or cell addressed memory here
113 |
--------------------------------------------------------------------------------
/vhdl/architectures/32/uDatacache.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_cell.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 12.06.2023 23:37:58
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 17-Jun-2022 byte addressing using byte_addr_width
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | make_sim_mem: IF SIMULATION GENERATE
70 |
71 | internal_data_mem: internal_dpram
72 | GENERIC MAP (data_width, cache_size, "no_rw_check", DMEM_file)
73 | PORT MAP (
74 | clk => clk,
75 | ena => enable,
76 | wea => write,
77 | addra => addr(cache_addr_width-1 DOWNTO 0),
78 | dia => wdata,
79 | doa => rdata,
80 | -- dma port
81 | enb => dma_enable,
82 | web => dma_write,
83 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
84 | dib => dma_wdata,
85 | dob => dma_rdata
86 | );
87 |
88 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
89 | -- instantiate FPGA specific IP for cell addressed memory here:
90 |
91 | internal_data_mem: internal_dpram
92 | GENERIC MAP (data_width, cache_size, "no_rw_check")
93 | PORT MAP (
94 | clk => clk,
95 | ena => enable,
96 | wea => write,
97 | addra => addr(cache_addr_width-1 DOWNTO 0),
98 | dia => wdata,
99 | doa => rdata,
100 | -- dma port
101 | enb => dma_enable,
102 | web => dma_write,
103 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
104 | dib => dma_wdata,
105 | dob => dma_rdata
106 | );
107 |
108 | END GENERATE make_syn_mem;
109 |
110 | END rtl;
111 |
112 | -- append FPGA specific IP for byte or cell addressed memory here
113 |
--------------------------------------------------------------------------------
/vhdl/architectures/32b/uDatacache.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_byte.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 02.11.2022 23:17:05
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 03-Nov-2022 byte addressing using byte_addr_width > 0
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | byte_access_proc : PROCESS(uBus, mem_rdata, dma_mem, dma_mem_rdata)
70 | BEGIN
71 |
72 | mem_wdata <= wdata;
73 | rdata <= mem_rdata;
74 | bytes_en <= (OTHERS => '1');
75 |
76 | dma_mem_wdata <= dma_wdata;
77 | dma_rdata <= dma_mem_rdata;
78 | dma_bytes_en <= (OTHERS => '1');
79 |
80 | -- 16 bit system
81 | IF byte_addr_width = 1 THEN
82 | IF bytes = 1 THEN -- byte access
83 | mem_wdata <= wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0);
84 | bytes_en <= "01";
85 | rdata <= resize(mem_rdata(07 DOWNTO 0), data_width);
86 | IF addr(0) = '1' THEN
87 | bytes_en <= "10";
88 | rdata <= resize(mem_rdata(15 DOWNTO 8), data_width);
89 | END IF;
90 | dma_mem_wdata <= dma_wdata(7 DOWNTO 0) & dma_wdata(7 DOWNTO 0);
91 | dma_bytes_en <= "01";
92 | dma_rdata <= resize(dma_mem_rdata(07 DOWNTO 0), data_width);
93 | IF dma_addr(0) = '1' THEN
94 | dma_bytes_en <= "10";
95 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 8), data_width);
96 | END IF;
97 | END IF;
98 | END IF;
99 |
100 | -- 32 bit system
101 | IF byte_addr_width = 2 THEN
102 | IF bytes = 1 THEN -- byte access
103 | mem_wdata <= wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0);
104 | CASE addr(1 DOWNTO 0) IS
105 | WHEN "00" => bytes_en <= "0001";
106 | rdata <= resize(mem_rdata(07 DOWNTO 00), data_width);
107 | WHEN "01" => bytes_en <= "0010";
108 | rdata <= resize(mem_rdata(15 DOWNTO 08), data_width);
109 | WHEN "10" => bytes_en <= "0100";
110 | rdata <= resize(mem_rdata(23 DOWNTO 16), data_width);
111 | WHEN "11" => bytes_en <= "1000";
112 | rdata <= resize(mem_rdata(31 DOWNTO 24), data_width);
113 | WHEN OTHERS => NULL;
114 | END CASE;
115 | dma_mem_wdata <= dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0);
116 | CASE dma_addr(1 DOWNTO 0) IS
117 | WHEN "00" => dma_bytes_en <= "0001";
118 | dma_rdata <= resize(dma_mem_rdata(07 DOWNTO 00), data_width);
119 | WHEN "01" => dma_bytes_en <= "0010";
120 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 08), data_width);
121 | WHEN "10" => dma_bytes_en <= "0100";
122 | dma_rdata <= resize(dma_mem_rdata(23 DOWNTO 16), data_width);
123 | WHEN "11" => dma_bytes_en <= "1000";
124 | dma_rdata <= resize(dma_mem_rdata(31 DOWNTO 24), data_width);
125 | WHEN OTHERS => NULL;
126 | END CASE;
127 | ELSIF bytes = 2 THEN -- word access
128 | mem_wdata <= wdata(15 DOWNTO 0) & wdata(15 DOWNTO 0);
129 | bytes_en <= "0011";
130 | rdata <= resize(mem_rdata(15 DOWNTO 0), data_width);
131 | IF addr(1) = '1' THEN
132 | bytes_en <= "1100";
133 | rdata <= resize(mem_rdata(31 DOWNTO 16), data_width);
134 | END IF;
135 | dma_mem_wdata <= dma_wdata(15 DOWNTO 0) & dma_wdata(15 DOWNTO 0);
136 | dma_bytes_en <= "0011";
137 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 0), data_width);
138 | IF dma_addr(1) = '1' THEN
139 | dma_bytes_en <= "1100";
140 | dma_rdata <= resize(dma_mem_rdata(31 DOWNTO 16), data_width);
141 | END IF;
142 | END IF;
143 | END IF;
144 |
145 | END PROCESS byte_access_proc;
146 |
147 | make_sim_mem: IF SIMULATION GENERATE
148 |
149 | internal_data_mem: internal_dpbram
150 | GENERIC MAP (data_width, cache_size, byte_addr_width, "no_rw_check", DMEM_file)
151 | PORT MAP (
152 | clk => clk,
153 | ena => enable,
154 | wea => write,
155 | bytea => bytes_en,
156 | addra => addr(cache_addr_width-1 DOWNTO byte_addr_width),
157 | dia => mem_wdata,
158 | doa => mem_rdata,
159 | -- dma port
160 | enb => dma_enable,
161 | web => dma_write,
162 | byteb => dma_bytes_en,
163 | addrb => dma_addr(cache_addr_width-1 DOWNTO byte_addr_width),
164 | dib => dma_mem_wdata,
165 | dob => dma_mem_rdata
166 | );
167 |
168 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
169 | -- instantiate FPGA specific IP for byte addressed memory here:
170 |
171 | internal_data_mem: internal_dpbram
172 | GENERIC MAP (data_width, cache_size, byte_addr_width, "no_rw_check")
173 | PORT MAP (
174 | clk => clk,
175 | ena => enable,
176 | wea => write,
177 | bytea => bytes_en,
178 | addra => addr(cache_addr_width-1 DOWNTO byte_addr_width),
179 | dia => mem_wdata,
180 | doa => mem_rdata,
181 | -- dma port
182 | enb => dma_enable,
183 | web => dma_write,
184 | byteb => dma_bytes_en,
185 | addrb => dma_addr(cache_addr_width-1 DOWNTO byte_addr_width),
186 | dib => dma_mem_wdata,
187 | dob => dma_mem_rdata
188 | );
189 |
190 | END GENERATE make_syn_mem;
191 |
192 | END rtl;
193 |
194 | -- append FPGA specific IP for byte or cell addressed memory here
195 |
--------------------------------------------------------------------------------
/vhdl/architectures/uDatacache_byte.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_byte.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 02.11.2022 23:17:05
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 03-Nov-2022 byte addressing using byte_addr_width > 0
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | byte_access_proc : PROCESS(uBus, mem_rdata, dma_mem, dma_mem_rdata)
70 | BEGIN
71 |
72 | mem_wdata <= wdata;
73 | rdata <= mem_rdata;
74 | bytes_en <= (OTHERS => '1');
75 |
76 | dma_mem_wdata <= dma_wdata;
77 | dma_rdata <= dma_mem_rdata;
78 | dma_bytes_en <= (OTHERS => '1');
79 |
80 | -- 16 bit system
81 | IF byte_addr_width = 1 THEN
82 | IF bytes = 1 THEN -- byte access
83 | mem_wdata <= wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0);
84 | bytes_en <= "01";
85 | rdata <= resize(mem_rdata(07 DOWNTO 0), data_width);
86 | IF addr(0) = '1' THEN
87 | bytes_en <= "10";
88 | rdata <= resize(mem_rdata(15 DOWNTO 8), data_width);
89 | END IF;
90 | dma_mem_wdata <= dma_wdata(7 DOWNTO 0) & dma_wdata(7 DOWNTO 0);
91 | dma_bytes_en <= "01";
92 | dma_rdata <= resize(dma_mem_rdata(07 DOWNTO 0), data_width);
93 | IF dma_addr(0) = '1' THEN
94 | dma_bytes_en <= "10";
95 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 8), data_width);
96 | END IF;
97 | END IF;
98 | END IF;
99 |
100 | -- 32 bit system
101 | IF byte_addr_width = 2 THEN
102 | IF bytes = 1 THEN -- byte access
103 | mem_wdata <= wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0);
104 | CASE addr(1 DOWNTO 0) IS
105 | WHEN "00" => bytes_en <= "0001";
106 | rdata <= resize(mem_rdata(07 DOWNTO 00), data_width);
107 | WHEN "01" => bytes_en <= "0010";
108 | rdata <= resize(mem_rdata(15 DOWNTO 08), data_width);
109 | WHEN "10" => bytes_en <= "0100";
110 | rdata <= resize(mem_rdata(23 DOWNTO 16), data_width);
111 | WHEN "11" => bytes_en <= "1000";
112 | rdata <= resize(mem_rdata(31 DOWNTO 24), data_width);
113 | WHEN OTHERS => NULL;
114 | END CASE;
115 | dma_mem_wdata <= dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0);
116 | CASE dma_addr(1 DOWNTO 0) IS
117 | WHEN "00" => dma_bytes_en <= "0001";
118 | dma_rdata <= resize(dma_mem_rdata(07 DOWNTO 00), data_width);
119 | WHEN "01" => dma_bytes_en <= "0010";
120 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 08), data_width);
121 | WHEN "10" => dma_bytes_en <= "0100";
122 | dma_rdata <= resize(dma_mem_rdata(23 DOWNTO 16), data_width);
123 | WHEN "11" => dma_bytes_en <= "1000";
124 | dma_rdata <= resize(dma_mem_rdata(31 DOWNTO 24), data_width);
125 | WHEN OTHERS => NULL;
126 | END CASE;
127 | ELSIF bytes = 2 THEN -- word access
128 | mem_wdata <= wdata(15 DOWNTO 0) & wdata(15 DOWNTO 0);
129 | bytes_en <= "0011";
130 | rdata <= resize(mem_rdata(15 DOWNTO 0), data_width);
131 | IF addr(1) = '1' THEN
132 | bytes_en <= "1100";
133 | rdata <= resize(mem_rdata(31 DOWNTO 16), data_width);
134 | END IF;
135 | dma_mem_wdata <= dma_wdata(15 DOWNTO 0) & dma_wdata(15 DOWNTO 0);
136 | dma_bytes_en <= "0011";
137 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 0), data_width);
138 | IF dma_addr(1) = '1' THEN
139 | dma_bytes_en <= "1100";
140 | dma_rdata <= resize(dma_mem_rdata(31 DOWNTO 16), data_width);
141 | END IF;
142 | END IF;
143 | END IF;
144 |
145 | END PROCESS byte_access_proc;
146 |
147 | make_sim_mem: IF SIMULATION GENERATE
148 |
149 | internal_data_mem: internal_dpbram
150 | GENERIC MAP (data_width, cache_size, byte_addr_width, "no_rw_check", DMEM_file)
151 | PORT MAP (
152 | clk => clk,
153 | ena => enable,
154 | wea => write,
155 | bytea => bytes_en,
156 | addra => addr(cache_addr_width-1 DOWNTO byte_addr_width),
157 | dia => mem_wdata,
158 | doa => mem_rdata,
159 | -- dma port
160 | enb => dma_enable,
161 | web => dma_write,
162 | byteb => dma_bytes_en,
163 | addrb => dma_addr(cache_addr_width-1 DOWNTO byte_addr_width),
164 | dib => dma_mem_wdata,
165 | dob => dma_mem_rdata
166 | );
167 |
168 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
169 | -- instantiate FPGA specific IP for byte addressed memory here:
170 |
171 | internal_data_mem: internal_dpbram
172 | GENERIC MAP (data_width, cache_size, byte_addr_width, "no_rw_check")
173 | PORT MAP (
174 | clk => clk,
175 | ena => enable,
176 | wea => write,
177 | bytea => bytes_en,
178 | addra => addr(cache_addr_width-1 DOWNTO byte_addr_width),
179 | dia => mem_wdata,
180 | doa => mem_rdata,
181 | -- dma port
182 | enb => dma_enable,
183 | web => dma_write,
184 | byteb => dma_bytes_en,
185 | addrb => dma_addr(cache_addr_width-1 DOWNTO byte_addr_width),
186 | dib => dma_mem_wdata,
187 | dob => dma_mem_rdata
188 | );
189 |
190 | END GENERATE make_syn_mem;
191 |
192 | END rtl;
193 |
194 | -- append FPGA specific IP for byte or cell addressed memory here
195 |
--------------------------------------------------------------------------------
/vhdl/architectures/uDatacache_cell.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_cell.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 12.06.2023 23:37:58
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 17-Jun-2022 byte addressing using byte_addr_width
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | make_sim_mem: IF SIMULATION GENERATE
70 |
71 | internal_data_mem: internal_dpram
72 | GENERIC MAP (data_width, cache_size, "no_rw_check", DMEM_file)
73 | PORT MAP (
74 | clk => clk,
75 | ena => enable,
76 | wea => write,
77 | addra => addr(cache_addr_width-1 DOWNTO 0),
78 | dia => wdata,
79 | doa => rdata,
80 | -- dma port
81 | enb => dma_enable,
82 | web => dma_write,
83 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
84 | dib => dma_wdata,
85 | dob => dma_rdata
86 | );
87 |
88 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
89 | -- instantiate FPGA specific IP for cell addressed memory here:
90 |
91 | internal_data_mem: internal_dpram
92 | GENERIC MAP (data_width, cache_size, "no_rw_check")
93 | PORT MAP (
94 | clk => clk,
95 | ena => enable,
96 | wea => write,
97 | addra => addr(cache_addr_width-1 DOWNTO 0),
98 | dia => wdata,
99 | doa => rdata,
100 | -- dma port
101 | enb => dma_enable,
102 | web => dma_write,
103 | addrb => dma_addr(cache_addr_width-1 DOWNTO 0),
104 | dib => dma_wdata,
105 | dob => dma_rdata
106 | );
107 |
108 | END GENERATE make_syn_mem;
109 |
110 | END rtl;
111 |
112 | -- append FPGA specific IP for byte or cell addressed memory here
113 |
--------------------------------------------------------------------------------
/vhdl/bootload.vhd:
--------------------------------------------------------------------------------
1 | --
2 | -- Program memory ROM implemented using a case statement.
3 | -- Its content was generated by the microCore cross compiler.
4 | -- It will be statically synthesized into the design as cold bootrom.
5 |
6 | LIBRARY IEEE;
7 | USE IEEE.STD_LOGIC_1164.ALL;
8 | USE IEEE.NUMERIC_STD.ALL;
9 | USE work.architecture_pkg.ALL;
10 |
11 | ENTITY boot_rom IS PORT (
12 | addr : IN boot_addr_bus;
13 | data : OUT inst_bus
14 | ); END boot_rom;
15 |
16 | ARCHITECTURE sim_model OF boot_rom IS
17 |
18 | SUBTYPE rom_address IS NATURAL RANGE 0 TO 2**boot_addr_width-1;
19 |
20 | FUNCTION program(addr : rom_address) RETURN UNSIGNED IS
21 | BEGIN
22 | CASE addr IS
23 | WHEN 16#0000# => RETURN "10000000";
24 | WHEN 16#0001# => RETURN "00000000";
25 | WHEN 16#0002# => RETURN "11111110";
26 | WHEN 16#0003# => RETURN "00001001";
27 | WHEN 16#0004# => RETURN "01011101";
28 | WHEN OTHERS => RETURN "--------";
29 | END CASE;
30 | END program;
31 |
32 | BEGIN
33 |
34 | data <= program(to_integer(addr));
35 |
36 | END sim_model;
--------------------------------------------------------------------------------
/vhdl/bootload_sim.vhd:
--------------------------------------------------------------------------------
1 | --
2 | -- Program memory ROM implemented using a case statement.
3 | -- Its content was generated by the microCore cross compiler.
4 | -- It will be statically synthesized into the design as cold bootrom.
5 |
6 | LIBRARY IEEE;
7 | USE IEEE.STD_LOGIC_1164.ALL;
8 | USE IEEE.NUMERIC_STD.ALL;
9 | USE work.architecture_pkg.ALL;
10 |
11 | ENTITY boot_rom IS PORT (
12 | addr : IN boot_addr_bus;
13 | data : OUT inst_bus
14 | ); END boot_rom;
15 |
16 | ARCHITECTURE sim_model OF boot_rom IS
17 |
18 | SUBTYPE rom_address IS NATURAL RANGE 0 TO 2**boot_addr_width-1;
19 |
20 | FUNCTION program(addr : rom_address) RETURN UNSIGNED IS
21 | BEGIN
22 | CASE addr IS
23 | WHEN 16#0000# => RETURN "10000000";
24 | WHEN 16#0001# => RETURN "00000000";
25 | WHEN 16#0002# => RETURN "00001001";
26 | WHEN 16#0003# => RETURN "01011101";
27 | WHEN OTHERS => RETURN "--------";
28 | END CASE;
29 | END program;
30 |
31 | BEGIN
32 |
33 | data <= program(to_integer(addr));
34 |
35 | END sim_model;
--------------------------------------------------------------------------------
/vhdl/external_SRAM.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : external_SRAM.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 15.07.2023 19:35:08
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Connecting external SRAM memories to microCore. Scaled
20 | -- by the ram_... constants in architecture_pkg.vhd
21 | -- This version can only be used if byte_addr_width = 0.
22 | --
23 | -- Version Author Date Changes
24 | -- 210 ks 8-Jun-2020 initial version
25 | -- 2300 ks 4-Mar-2021 converted to NUMERIC_STD
26 | -- 2310 ks 22-Mar-2021 Bugfix in data_mux_proc
27 | -- ---------------------------------------------------------------------
28 | LIBRARY IEEE;
29 | USE IEEE.STD_LOGIC_1164.ALL;
30 | USE IEEE.NUMERIC_STD.ALL;
31 | USE work.functions_pkg.ALL;
32 | USE work.architecture_pkg.ALL;
33 |
34 | ENTITY external_SRAM IS GENERIC (
35 | ram_addr_width : NATURAL; -- addr width of the external SRAM
36 | ram_data_width : NATURAL; -- data width of the external SRAM
37 | delay_cnt : NATURAL -- delay_cnt+1 extra clock cycles for each memory access
38 | ); PORT (
39 | uBus : IN uBus_port;
40 | ext_rdata : OUT data_bus;
41 | delay : OUT STD_LOGIC;
42 | -- external SRAM
43 | ce_n : OUT STD_LOGIC;
44 | oe_n : OUT STD_LOGIC;
45 | we_n : OUT STD_LOGIC;
46 | addr : OUT UNSIGNED(ram_addr_width-1 DOWNTO 0);
47 | data : INOUT UNSIGNED(ram_data_width-1 DOWNTO 0)
48 | ); END external_SRAM;
49 |
50 | ARCHITECTURE rtl OF external_SRAM IS
51 |
52 | ALIAS reset : STD_LOGIC IS uBus.reset;
53 | ALIAS clk : STD_LOGIC IS uBus.clk;
54 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
55 | ALIAS ext_en : STD_LOGIC IS uBus.ext_en;
56 | ALIAS write : STD_LOGIC IS uBus.write;
57 | ALIAS wdata : data_bus IS uBus.wdata;
58 |
59 | CONSTANT residue : NATURAL := data_width MOD ram_data_width;
60 | CONSTANT leader : NATURAL := (ram_data_width - residue) MOD ram_data_width;
61 |
62 | SIGNAL delay_ctr : NATURAL RANGE 0 TO umax(delay_cnt, cycles-1);
63 | SIGNAL ext_ce : STD_LOGIC;
64 | SIGNAL sub_addr : UNSIGNED(ram_subbits-1 DOWNTO 0);
65 | SIGNAL LSword : UNSIGNED((ram_data_width * (ram_chunks-1))-1 DOWNTO 0);
66 |
67 | -- defined in architecture_pkg.vhd
68 | -- CONSTANT ram_data_width : NATURAL := 8; -- external memory word width
69 | -- CONSTANT ram_chunks : NATURAL := ceiling(data_width, ram_data_width);
70 | -- CONSTANT ram_subbits : NATURAL := log2(ram_chunks);
71 |
72 | BEGIN
73 |
74 | -- ---------------------------------------------------------------------
75 | -- ram_data_width < data_width
76 | -- ---------------------------------------------------------------------
77 |
78 | if_wide_data: IF ram_data_width < data_width GENERATE
79 |
80 | delay <= '1' WHEN ext_en = '1' AND (ext_ce = '0' OR delay_ctr /= 0 OR sub_addr /= ram_chunks-1) ELSE '0';
81 |
82 | rdata_proc : PROCESS (data, LSword)
83 | BEGIN
84 | IF residue = 0 THEN
85 | ext_rdata <= data & LSword;
86 | ELSE
87 | ext_rdata <= data(residue-1 DOWNTO 0) & LSword;
88 | END IF;
89 | END PROCESS rdata_proc;
90 |
91 | ce_n <= NOT ext_ce;
92 | addr <= resize(uBus.addr & sub_addr, addr'length);
93 |
94 | data_mux_proc: PROCESS (uBus, sub_addr, wdata, ext_ce)
95 | VARIABLE subaddr : NATURAL;
96 | VARIABLE maxdata : UNSIGNED((ram_data_width * ram_chunks)-1 DOWNTO 0);
97 | VARIABLE subdata : UNSIGNED(data'range);
98 | BEGIN
99 | subaddr := to_integer(sub_addr);
100 | maxdata := slice('0', leader) & wdata;
101 | subdata := maxdata((ram_data_width * (subaddr + 1))-1 DOWNTO ram_data_width * subaddr);
102 | data <= (OTHERS => 'Z');
103 | IF uBus.write = '1' AND ext_ce = '1' THEN
104 | data <= subdata;
105 | END IF;
106 | END PROCESS data_mux_proc;
107 |
108 | SRAM_proc: PROCESS (clk)
109 | BEGIN
110 | IF reset = '1' AND ASYNC_RESET THEN
111 | delay_ctr <= cycles - 1;
112 | ext_ce <= '0';
113 | we_n <= '1';
114 | oe_n <= '1';
115 | ELSIF rising_edge(clk) THEN
116 | IF delay_ctr = 0 THEN
117 | IF ext_ce = '0' AND ext_en = '1' THEN
118 | delay_ctr <= delay_cnt;
119 | sub_addr <= (OTHERS => '0');
120 | ext_ce <= '1';
121 | END IF;
122 | IF ext_ce = '1' AND sub_addr /= ram_chunks-1 THEN
123 | sub_addr <= sub_addr + 1;
124 | delay_ctr <= delay_cnt;
125 | LSword <= data & LSword(LSword'high DOWNTO ram_data_width);
126 | we_n <= '1';
127 | END IF;
128 | IF clk_en = '1' AND sub_addr = ram_chunks-1 THEN
129 | sub_addr <= (OTHERS => '0');
130 | delay_ctr <= cycles - 1;
131 | ext_ce <= '0';
132 | we_n <= '1';
133 | oe_n <= '1';
134 | END IF;
135 | ELSIF ext_en = '1' THEN
136 | delay_ctr <= delay_ctr - 1;
137 | IF delay_ctr = delay_cnt AND ext_ce = '1' THEN
138 | IF uBus.write = '1' THEN
139 | we_n <= '0';
140 | ELSE
141 | oe_n <= '0';
142 | END IF;
143 | END IF;
144 | END IF;
145 | IF reset = '1' AND NOT ASYNC_RESET THEN
146 | delay_ctr <= cycles - 1;
147 | ext_ce <= '0';
148 | we_n <= '1';
149 | oe_n <= '1';
150 | END IF;
151 | END IF;
152 | END PROCESS SRAM_proc;
153 |
154 | END GENERATE if_wide_data;
155 |
156 | -- ---------------------------------------------------------------------
157 | -- ram_data_width >= data_width
158 | -- ---------------------------------------------------------------------
159 |
160 | else_wide_data: IF ram_data_width >= data_width GENERATE
161 |
162 | delay <= '1' WHEN ext_en = '1' AND (ext_ce = '0' OR delay_ctr /= 0) ELSE '0';
163 |
164 | ce_n <= NOT ext_ce;
165 | addr <= resize(uBus.addr, addr'length);
166 |
167 | data_mux_proc: PROCESS (uBus, ext_ce, wdata)
168 | BEGIN
169 | data <= (OTHERS => 'Z');
170 | IF uBus.write = '1' AND ext_ce = '1' THEN
171 | data(data_width-1 DOWNTO 0) <= wdata;
172 | IF residue /= 0 THEN
173 | data(ram_data_width-1 DOWNTO data_width) <= (OTHERS => '0');
174 | END IF;
175 | END IF;
176 | END PROCESS data_mux_proc;
177 |
178 | ext_rdata <= data(data_width-1 DOWNTO 0);
179 |
180 | SRAM_proc: PROCESS (clk)
181 | BEGIN
182 | IF reset = '1' AND ASYNC_RESET THEN
183 | delay_ctr <= 0;
184 | ext_ce <= '0';
185 | we_n <= '1';
186 | oe_n <= '1';
187 | ELSIF rising_edge(clk) THEN
188 | IF delay_ctr = 0 THEN
189 | IF ext_ce = '0' AND ext_en = '1' THEN
190 | delay_ctr <= delay_cnt;
191 | ext_ce <= '1';
192 | END IF;
193 | IF ext_ce = '1' THEN
194 | delay_ctr <= delay_cnt;
195 | we_n <= '1';
196 | END IF;
197 | IF clk_en = '1' THEN
198 | delay_ctr <= cycles - 1;
199 | ext_ce <= '0';
200 | we_n <= '1';
201 | oe_n <= '1';
202 | END IF;
203 | ELSIF ext_en = '1' THEN
204 | delay_ctr <= delay_ctr - 1;
205 | IF delay_ctr = delay_cnt AND ext_ce = '1' THEN
206 | IF uBus.write = '1' THEN
207 | we_n <= '0';
208 | ELSE
209 | oe_n <= '0';
210 | END IF;
211 | END IF;
212 | END IF;
213 | IF reset = '1' AND NOT ASYNC_RESET THEN
214 | delay_ctr <= 0;
215 | ext_ce <= '0';
216 | we_n <= '1';
217 | oe_n <= '1';
218 | END IF;
219 | END IF;
220 | END PROCESS SRAM_proc;
221 |
222 | END GENERATE else_wide_data;
223 |
224 | END rtl;
225 |
--------------------------------------------------------------------------------
/vhdl/header.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : .vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 05.04.2021 16:53:00
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief:
20 | --
21 | -- Version Author Date Changes
22 | -- ks 8-Jun-2020 initial version
23 | -- ---------------------------------------------------------------------
24 |
25 |
--------------------------------------------------------------------------------
/vhdl/program.vhd:
--------------------------------------------------------------------------------
1 | --
2 | -- Program memory ROM implemented using a case statement.
3 | -- It is generated by the microCore cross compiler.
4 |
5 | LIBRARY IEEE;
6 | USE IEEE.STD_LOGIC_1164.ALL;
7 | USE IEEE.NUMERIC_STD.ALL;
8 | USE work.architecture_pkg.ALL;
9 |
10 | ENTITY program_rom IS PORT (
11 | addr : IN program_addr;
12 | data : OUT inst_bus
13 | ); END program_rom;
14 |
15 | ARCHITECTURE sim_model OF program_rom IS
16 |
17 | SUBTYPE rom_address IS NATURAL RANGE 0 TO 2**prog_addr_width-1;
18 |
19 | FUNCTION program(addr : rom_address) RETURN UNSIGNED IS
20 | BEGIN
21 | CASE addr IS
22 | WHEN 16#0000# => RETURN "10000001";
23 | WHEN 16#0001# => RETURN "10101010";
24 | WHEN 16#0002# => RETURN "11010101";
25 | WHEN 16#0003# => RETURN "00000000";
26 | WHEN 16#0004# => RETURN "10000100";
27 | WHEN 16#0005# => RETURN "00000000";
28 | WHEN 16#0006# => RETURN "01001000";
29 | WHEN 16#0007# => RETURN "01010000";
30 | WHEN 16#0008# => RETURN "11111100";
31 | WHEN 16#0009# => RETURN "00001001";
32 | WHEN 16#000A# => RETURN "01011101";
33 | WHEN OTHERS => RETURN "--------";
34 | END CASE;
35 | END program;
36 |
37 | BEGIN
38 |
39 | data <= program(to_integer(addr));
40 |
41 | END sim_model;
--------------------------------------------------------------------------------
/vhdl/uArithmetic.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uArithmetic.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 02.04.2021 11:59:11
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Application specific adder and multiplier should the
20 | -- inferred one be too slow.
21 | --
22 | -- Version Author Date Changes
23 | -- 2300 ks 8-Mar-2021 Converted to NUMERIC_STD
24 | -- Former uAdd.vhd and uMult.vhd merged.
25 | -- ---------------------------------------------------------------------
26 | LIBRARY IEEE;
27 | USE IEEE.STD_LOGIC_1164.ALL;
28 | USE IEEE.NUMERIC_STD.ALL;
29 | USE work.architecture_pkg.ALL;
30 | USE work.functions_pkg.ALL;
31 |
32 | ENTITY uArithmetic IS PORT (
33 | -- add
34 | cin : IN STD_LOGIC;
35 | ladd_x : IN UNSIGNED(data_width DOWNTO 0);
36 | ladd_y : IN UNSIGNED(data_width DOWNTO 0);
37 | ladd_out : OUT UNSIGNED(data_width+1 DOWNTO 0);
38 | -- multiply
39 | multiplicand : IN UNSIGNED(data_width DOWNTO 0);
40 | multiplier : IN UNSIGNED(data_width DOWNTO 0);
41 | product : OUT UNSIGNED(data_width*2+1 DOWNTO 0)
42 | ); END uArithmetic;
43 |
44 | ARCHITECTURE inference OF uArithmetic IS
45 |
46 | BEGIN
47 |
48 | sim_arith: IF SIMULATION GENERATE
49 |
50 | ladd_out <= ('0' & ladd_x) + ('0' & ladd_y) + ("" & cin);
51 |
52 | product <= unsigned(signed(multiplicand) * signed(multiplier));
53 |
54 | END GENERATE sim_arith; syn_arith: IF NOT SIMULATION GENERATE
55 |
56 | ladd_out <= ('0' & ladd_x) + ('0' & ladd_y) + ("" & cin);
57 |
58 | product <= unsigned(signed(multiplicand) * signed(multiplier));
59 |
60 | END GENERATE syn_arith;
61 |
62 | END inference;
63 |
--------------------------------------------------------------------------------
/vhdl/uCore.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uCore.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 12.07.2023 23:58:06
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: The microCore processor kernel.
20 | --
21 | -- Version Author Date Changes
22 | -- 210 ks 8-Jun-2020 initial version
23 | -- 2300 ks 8-Mar-2021 compiler switch WITH_PROG_RW eliminated
24 | -- Conversion to NUMERIC_STD
25 | -- 2332 ks 13-Apr-2022 enable_proc moved to fpga.vhd
26 | -- 2400 ks 03-Nov-2022 bugfix of deb_denable
27 | -- ---------------------------------------------------------------------
28 | LIBRARY IEEE;
29 | USE IEEE.STD_LOGIC_1164.ALL;
30 | USE IEEE.NUMERIC_STD.ALL;
31 | USE work.functions_pkg.ALL;
32 | USE work.architecture_pkg.ALL;
33 |
34 | ENTITY microcore IS PORT (
35 | uBus : IN uBus_port;
36 | core : OUT core_signals;
37 | memory : OUT datamem_port;
38 | -- umbilical uart interface
39 | rxd : IN STD_LOGIC;
40 | break : OUT STD_LOGIC;
41 | txd : OUT STD_LOGIC
42 | ); END microcore;
43 |
44 | ARCHITECTURE rtl OF microcore IS
45 |
46 | ATTRIBUTE syn_keep : BOOLEAN;
47 |
48 | ALIAS reset : STD_LOGIC IS uBus.reset;
49 | ALIAS clk : STD_LOGIC IS uBus.clk;
50 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
51 | ALIAS pause : STD_LOGIC IS uBus.pause;
52 | ALIAS mem_rdata : data_bus IS uBus.rdata;
53 |
54 | COMPONENT microcontrol PORT (
55 | uBus : IN uBus_port;
56 | deb_reset : IN STD_LOGIC; -- reset issued by debugger
57 | deb_pause : IN STD_LOGIC; -- pause issued by debugger
58 | deb_penable : IN STD_LOGIC; -- program memory ready for write by debugger
59 | uCtrl : OUT core_signals;
60 | progmem : OUT progmem_port;
61 | prog_rdata : IN inst_bus;
62 | datamem : OUT datamem_port;
63 | mem_rdata : IN data_bus -- data memory read data
64 | ); END COMPONENT microcontrol;
65 |
66 | SIGNAL uCtrl : core_signals;
67 | SIGNAL progmem : progmem_port;
68 | SIGNAL prog_rdata : inst_bus;
69 | SIGNAL datamem : datamem_port;
70 |
71 | COMPONENT debugger PORT (
72 | uBus : IN uBus_port;
73 | deb_reset : OUT STD_LOGIC; -- reset generated by debugger
74 | deb_pause : OUT STD_LOGIC;
75 | deb_prequest : OUT STD_LOGIC; -- request program memory write cycle
76 | deb_penable : IN STD_LOGIC; -- execute program memory write
77 | deb_drequest : OUT STD_LOGIC; -- request data memory for a read/write cycle
78 | deb_denable : IN STD_LOGIC; -- execute data memory read/write
79 | umbilical : OUT progmem_port; -- interface to the program memory
80 | debugmem : OUT datamem_port; -- interface to the data memory
81 | debugmem_rdata : IN data_bus;
82 | -- umbilical uart
83 | rxd : IN STD_LOGIC;
84 | break : OUT STD_LOGIC;
85 | txd : OUT STD_LOGIC
86 | ); END COMPONENT debugger;
87 |
88 | SIGNAL umbilical : progmem_port;
89 | SIGNAL debugmem : datamem_port;
90 | SIGNAL deb_pause : STD_LOGIC;
91 | SIGNAL deb_reset : STD_LOGIC;
92 | SIGNAL deb_prequest : STD_LOGIC;
93 | SIGNAL deb_drequest : STD_LOGIC;
94 | SIGNAL deb_penable : STD_LOGIC;
95 | SIGNAL deb_denable : STD_LOGIC;
96 | SIGNAL deb_ext_en : STD_LOGIC;
97 | SIGNAL deb_mem_en : STD_LOGIC;
98 |
99 | SIGNAL warmboot : STD_LOGIC := '0'; ATTRIBUTE syn_keep OF warmboot : SIGNAL IS true;
100 |
101 | -- cold boot loader
102 | COMPONENT boot_rom PORT (
103 | addr : IN boot_addr_bus;
104 | data : OUT inst_bus
105 | ); END COMPONENT boot_rom;
106 |
107 | SIGNAL boot_addr : boot_addr_bus;
108 | SIGNAL boot_rdata : inst_bus;
109 |
110 | -- program memory
111 | COMPONENT uProgmem PORT (
112 | clk : IN STD_LOGIC;
113 | penable : IN STD_LOGIC;
114 | pwrite : IN STD_LOGIC;
115 | paddr : IN program_addr;
116 | pwdata : IN inst_bus;
117 | prdata : OUT inst_bus
118 | ); END COMPONENT uProgmem;
119 |
120 | SIGNAL pcache_rdata : inst_bus;
121 | SIGNAL pcache_wdata : inst_bus;
122 | SIGNAL pwrite : STD_LOGIC;
123 | SIGNAL paddr : program_addr;
124 |
125 | BEGIN
126 |
127 | -- make sure reg_addr_width is large enough for all registers
128 | ASSERT (abs(min_registers) <= (2 ** reg_addr_width))
129 | REPORT "reg_addr_width too small"
130 | SEVERITY error;
131 |
132 | -- ---------------------------------------------------------------------
133 | -- internal program memory
134 | -- ---------------------------------------------------------------------
135 |
136 | paddr <= umbilical.addr WHEN deb_penable = '1' ELSE progmem.addr;
137 |
138 | pwrite <= umbilical.write WHEN deb_penable = '1' ELSE
139 | progmem.write WHEN warmboot = '0' OR SIMULATION ELSE '0'; -- only during boot phase
140 |
141 | pcache_wdata <= umbilical.wdata WHEN deb_penable = '1' ELSE progmem.wdata;
142 |
143 | internal_prog_mem: uProgmem PORT MAP (
144 | clk => clk,
145 | penable => clk_en,
146 | pwrite => pwrite,
147 | paddr => paddr,
148 | pwdata => pcache_wdata,
149 | prdata => pcache_rdata
150 | );
151 |
152 | prog_rdata <= pcache_rdata WHEN warmboot = '1' ELSE boot_rdata;
153 |
154 | -- ---------------------------------------------------------------------
155 | -- boot loader, reads from program memory after branch to zero (reboot)
156 | -- ---------------------------------------------------------------------
157 |
158 | cold_boot_proc: PROCESS (reset, clk)
159 | BEGIN
160 | IF reset = '1' AND ASYNC_RESET THEN
161 | IF COLDBOOT THEN warmboot <= '0'; END IF; -- go into boot loading on reset?
162 | boot_addr <= (OTHERS => '0');
163 | ELSIF rising_edge(clk) THEN
164 | IF clk_en = '1' AND warmboot = '0' THEN
165 | boot_addr <= progmem.addr(boot_addr_width-1 DOWNTO 0);
166 | IF (prog_rdata = op_BRANCH AND progmem.addr = 0 AND progmem.write = '0') OR deb_penable = '1' THEN
167 | warmboot <= '1';
168 | END IF;
169 | END IF;
170 | IF reset = '1' AND NOT ASYNC_RESET THEN
171 | IF COLDBOOT THEN warmboot <= '0'; END IF; -- go into boot loading on reset?
172 | boot_addr <= (OTHERS => '0');
173 | END IF;
174 | END IF;
175 | END PROCESS cold_boot_proc;
176 |
177 | boot_loader: boot_rom PORT MAP(boot_addr, boot_rdata);
178 |
179 | -- ---------------------------------------------------------------------
180 | -- instruction execution engine
181 | -- ---------------------------------------------------------------------
182 |
183 | uCntrl: microcontrol PORT MAP (
184 | uBus => uBus,
185 | deb_reset => deb_reset, -- reset issued by debugger
186 | deb_pause => deb_pause, -- pause issued by debugger
187 | deb_penable => deb_penable, -- program memory ready for write by debugger
188 | uCtrl => uCtrl,
189 | progmem => progmem,
190 | prog_rdata => prog_rdata,
191 | datamem => datamem,
192 | mem_rdata => mem_rdata
193 | );
194 |
195 | core.reg_en <= uCtrl.reg_en;
196 | core.mem_en <= uCtrl.mem_en OR deb_mem_en;
197 | core.ext_en <= uCtrl.ext_en OR deb_ext_en;
198 | core.tick <= uCtrl.tick;
199 | core.chain <= uCtrl.chain;
200 | core.status <= uCtrl.status;
201 | core.dsp <= uCtrl.dsp;
202 | core.rsp <= uCtrl.rsp;
203 | core.int <= uCtrl.int;
204 | core.time <= uCtrl.time;
205 | core.debug <= debugmem.wdata;
206 | memory <= debugmem WHEN deb_denable = '1' ELSE datamem;
207 |
208 | -- ---------------------------------------------------------------------
209 | -- umbilical uart debug interface
210 | -- ---------------------------------------------------------------------
211 |
212 | deb_penable <= deb_prequest AND (NOT uCtrl.chain OR deb_reset);
213 |
214 | deb_denable_proc : PROCESS(deb_drequest, deb_denable, debugmem, uCtrl)
215 | BEGIN
216 | deb_mem_en <= '0';
217 | deb_ext_en <= '0';
218 | deb_denable <= deb_drequest AND NOT (uCtrl.chain OR uCtrl.mem_en OR uCtrl.ext_en OR uCtrl.reg_en);
219 | IF deb_denable = '1' THEN
220 | deb_mem_en <= '1';
221 | IF WITH_EXTMEM AND debugmem.addr(data_addr_width-1 DOWNTO cache_addr_width) /= 0 THEN
222 | deb_mem_en <= '0';
223 | deb_ext_en <= '1';
224 | END IF;
225 | END IF;
226 | END PROCESS deb_denable_proc;
227 |
228 | debug_unit: debugger PORT MAP (
229 | uBus => uBus,
230 | deb_reset => deb_reset,
231 | deb_pause => deb_pause,
232 | deb_prequest => deb_prequest,
233 | deb_penable => deb_penable,
234 | deb_drequest => deb_drequest,
235 | deb_denable => deb_denable,
236 | umbilical => umbilical,
237 | debugmem => debugmem,
238 | debugmem_rdata => mem_rdata,
239 | -- umbilical
240 | rxd => rxd,
241 | break => break,
242 | txd => txd
243 | );
244 |
245 | END rtl;
--------------------------------------------------------------------------------
/vhdl/uDatacache.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uDatacache_byte.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 02.11.2022 23:17:05
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal data memory.
20 | -- Here fpga specific dual port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- 2300 ks 8-Mar-2021 Conversion to NUMERIC_STD
25 | -- 2400 ks 03-Nov-2022 byte addressing using byte_addr_width > 0
26 | -- ---------------------------------------------------------------------
27 | LIBRARY IEEE;
28 | USE IEEE.STD_LOGIC_1164.ALL;
29 | USE IEEE.NUMERIC_STD.ALL;
30 | USE work.functions_pkg.ALL;
31 | USE work.architecture_pkg.ALL;
32 |
33 | ENTITY uDatacache IS PORT (
34 | uBus : IN uBus_port;
35 | rdata : OUT data_bus;
36 | dma_mem : IN datamem_port;
37 | dma_rdata : OUT data_bus
38 | ); END uDatacache;
39 |
40 | ARCHITECTURE rtl OF uDatacache IS
41 |
42 | ALIAS clk : STD_LOGIC IS uBus.clk;
43 | ALIAS clk_en : STD_LOGIC IS uBus.clk_en;
44 | ALIAS mem_en : STD_LOGIC IS uBus.mem_en;
45 | ALIAS bytes : byte_type IS uBus.bytes;
46 | ALIAS write : STD_LOGIC IS uBus.write;
47 | ALIAS addr : data_addr IS uBus.addr;
48 | ALIAS wdata : data_bus IS uBus.wdata;
49 | ALIAS dma_enable : STD_LOGIC IS dma_mem.enable;
50 | ALIAS dma_bytes : byte_type IS dma_mem.bytes;
51 | ALIAS dma_write : STD_LOGIC IS dma_mem.write;
52 | ALIAS dma_addr : data_addr IS dma_mem.addr;
53 | ALIAS dma_wdata : data_bus IS dma_mem.wdata;
54 |
55 | SIGNAL enable : STD_LOGIC;
56 |
57 | SIGNAL bytes_en : byte_addr;
58 | SIGNAL mem_wdata : data_bus;
59 | SIGNAL mem_rdata : data_bus;
60 |
61 | SIGNAL dma_bytes_en : byte_addr;
62 | SIGNAL dma_mem_wdata : data_bus;
63 | SIGNAL dma_mem_rdata : data_bus;
64 |
65 | BEGIN
66 |
67 | enable <= clk_en AND mem_en;
68 |
69 | byte_access_proc : PROCESS(uBus, mem_rdata, dma_mem, dma_mem_rdata)
70 | BEGIN
71 |
72 | mem_wdata <= wdata;
73 | rdata <= mem_rdata;
74 | bytes_en <= (OTHERS => '1');
75 |
76 | dma_mem_wdata <= dma_wdata;
77 | dma_rdata <= dma_mem_rdata;
78 | dma_bytes_en <= (OTHERS => '1');
79 |
80 | -- 16 bit system
81 | IF byte_addr_width = 1 THEN
82 | IF bytes = 1 THEN -- byte access
83 | mem_wdata <= wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0);
84 | bytes_en <= "01";
85 | rdata <= resize(mem_rdata(07 DOWNTO 0), data_width);
86 | IF addr(0) = '1' THEN
87 | bytes_en <= "10";
88 | rdata <= resize(mem_rdata(15 DOWNTO 8), data_width);
89 | END IF;
90 | dma_mem_wdata <= dma_wdata(7 DOWNTO 0) & dma_wdata(7 DOWNTO 0);
91 | dma_bytes_en <= "01";
92 | dma_rdata <= resize(dma_mem_rdata(07 DOWNTO 0), data_width);
93 | IF dma_addr(0) = '1' THEN
94 | dma_bytes_en <= "10";
95 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 8), data_width);
96 | END IF;
97 | END IF;
98 | END IF;
99 |
100 | -- 32 bit system
101 | IF byte_addr_width = 2 THEN
102 | IF bytes = 1 THEN -- byte access
103 | mem_wdata <= wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0) & wdata(7 DOWNTO 0);
104 | CASE addr(1 DOWNTO 0) IS
105 | WHEN "00" => bytes_en <= "0001";
106 | rdata <= resize(mem_rdata(07 DOWNTO 00), data_width);
107 | WHEN "01" => bytes_en <= "0010";
108 | rdata <= resize(mem_rdata(15 DOWNTO 08), data_width);
109 | WHEN "10" => bytes_en <= "0100";
110 | rdata <= resize(mem_rdata(23 DOWNTO 16), data_width);
111 | WHEN "11" => bytes_en <= "1000";
112 | rdata <= resize(mem_rdata(31 DOWNTO 24), data_width);
113 | WHEN OTHERS => NULL;
114 | END CASE;
115 | dma_mem_wdata <= dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0) & dma_wdata( 7 DOWNTO 0);
116 | CASE dma_addr(1 DOWNTO 0) IS
117 | WHEN "00" => dma_bytes_en <= "0001";
118 | dma_rdata <= resize(dma_mem_rdata(07 DOWNTO 00), data_width);
119 | WHEN "01" => dma_bytes_en <= "0010";
120 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 08), data_width);
121 | WHEN "10" => dma_bytes_en <= "0100";
122 | dma_rdata <= resize(dma_mem_rdata(23 DOWNTO 16), data_width);
123 | WHEN "11" => dma_bytes_en <= "1000";
124 | dma_rdata <= resize(dma_mem_rdata(31 DOWNTO 24), data_width);
125 | WHEN OTHERS => NULL;
126 | END CASE;
127 | ELSIF bytes = 2 THEN -- word access
128 | mem_wdata <= wdata(15 DOWNTO 0) & wdata(15 DOWNTO 0);
129 | bytes_en <= "0011";
130 | rdata <= resize(mem_rdata(15 DOWNTO 0), data_width);
131 | IF addr(1) = '1' THEN
132 | bytes_en <= "1100";
133 | rdata <= resize(mem_rdata(31 DOWNTO 16), data_width);
134 | END IF;
135 | dma_mem_wdata <= dma_wdata(15 DOWNTO 0) & dma_wdata(15 DOWNTO 0);
136 | dma_bytes_en <= "0011";
137 | dma_rdata <= resize(dma_mem_rdata(15 DOWNTO 0), data_width);
138 | IF dma_addr(1) = '1' THEN
139 | dma_bytes_en <= "1100";
140 | dma_rdata <= resize(dma_mem_rdata(31 DOWNTO 16), data_width);
141 | END IF;
142 | END IF;
143 | END IF;
144 |
145 | END PROCESS byte_access_proc;
146 |
147 | make_sim_mem: IF SIMULATION GENERATE
148 |
149 | internal_data_mem: internal_dpbram
150 | GENERIC MAP (data_width, cache_size, byte_addr_width, "no_rw_check", DMEM_file)
151 | PORT MAP (
152 | clk => clk,
153 | ena => enable,
154 | wea => write,
155 | bytea => bytes_en,
156 | addra => addr(cache_addr_width-1 DOWNTO byte_addr_width),
157 | dia => mem_wdata,
158 | doa => mem_rdata,
159 | -- dma port
160 | enb => dma_enable,
161 | web => dma_write,
162 | byteb => dma_bytes_en,
163 | addrb => dma_addr(cache_addr_width-1 DOWNTO byte_addr_width),
164 | dib => dma_mem_wdata,
165 | dob => dma_mem_rdata
166 | );
167 |
168 | END GENERATE make_sim_mem; make_syn_mem: IF NOT SIMULATION GENERATE
169 | -- instantiate FPGA specific IP for byte addressed memory here:
170 |
171 | internal_data_mem: internal_dpbram
172 | GENERIC MAP (data_width, cache_size, byte_addr_width, "no_rw_check")
173 | PORT MAP (
174 | clk => clk,
175 | ena => enable,
176 | wea => write,
177 | bytea => bytes_en,
178 | addra => addr(cache_addr_width-1 DOWNTO byte_addr_width),
179 | dia => mem_wdata,
180 | doa => mem_rdata,
181 | -- dma port
182 | enb => dma_enable,
183 | web => dma_write,
184 | byteb => dma_bytes_en,
185 | addrb => dma_addr(cache_addr_width-1 DOWNTO byte_addr_width),
186 | dib => dma_mem_wdata,
187 | dob => dma_mem_rdata
188 | );
189 |
190 | END GENERATE make_syn_mem;
191 |
192 | END rtl;
193 |
194 | -- append FPGA specific IP for byte or cell addressed memory here
195 |
--------------------------------------------------------------------------------
/vhdl/uProgmem.vhd:
--------------------------------------------------------------------------------
1 | -- ---------------------------------------------------------------------
2 | -- @file : uProgmem.vhd
3 | -- ---------------------------------------------------------------------
4 | --
5 | -- Last change: KS 10.04.2021 17:24:58
6 | -- @project: microCore
7 | -- @language: VHDL-93
8 | -- @copyright (c): Klaus Schleisiek, All Rights Reserved.
9 | -- @contributors:
10 | --
11 | -- @license: Do not use this file except in compliance with the License.
12 | -- You may obtain a copy of the Public License at
13 | -- https://github.com/microCore-VHDL/microCore/tree/master/documents
14 | -- Software distributed under the License is distributed on an "AS IS"
15 | -- basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
16 | -- See the License for the specific language governing rights and
17 | -- limitations under the License.
18 | --
19 | -- @brief: Definition of the internal program memory.
20 | -- Here fpga specific single port memory IP can be included.
21 | --
22 | -- Version Author Date Changes
23 | -- 210 ks 8-Jun-2020 initial version
24 | -- ---------------------------------------------------------------------
25 | LIBRARY IEEE;
26 | USE IEEE.STD_LOGIC_1164.ALL;
27 | USE work.functions_pkg.ALL;
28 | USE work.architecture_pkg.ALL;
29 |
30 | ENTITY uProgmem IS PORT (
31 | clk : IN STD_LOGIC;
32 | penable : IN STD_LOGIC;
33 | pwrite : IN STD_LOGIC;
34 | paddr : IN program_addr;
35 | pwdata : IN inst_bus;
36 | prdata : OUT inst_bus
37 | ); END uProgmem;
38 |
39 | ARCHITECTURE rtl OF uProgmem IS
40 |
41 | BEGIN
42 |
43 | internal_prog_mem: internal_ram
44 | GENERIC MAP (inst_width, prog_size, "no_rw_check", MEM_file)
45 | PORT MAP (
46 | clk => clk,
47 | en => penable,
48 | we => pwrite,
49 | addr => paddr,
50 | di => pwdata,
51 | do => prdata
52 | );
53 |
54 | END rtl;
55 |
--------------------------------------------------------------------------------
20 |