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4 | Verilog/SystemVerilog Guide
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13 | #### A guide covering Verilog & SystemVerilog including the applications, libraries and tools that will make you a better and more efficient developer by having a better understanding of how hardware works on the lowest level.
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15 | **Note: You can easily convert this markdown file to a PDF in [VSCode](https://code.visualstudio.com/) using this handy extension [Markdown PDF](https://marketplace.visualstudio.com/items?itemName=yzane.markdown-pdf).**
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22 | # Verilog/SystemVerilog Learning Resources
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24 | [Verilog](https://verilog.com/) is a Hardware Description Language(HDL) used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction.
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26 | [SystemVerilog](https://www.systemverilog.io/) is an extension of Verilog with many of the verification features that allow engineers to verify the design using complex testbench structures and random stimuli in simulation.
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28 | [Verilog Book Shelf](https://verilog.com/v-books.html)
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30 | [Verilog HDL Basics training from Intel](https://www.intel.com/content/www/us/en/programmable/support/training/course/ohdl1120.html)
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32 | [SystemVerilog for Design and Verification](https://www.cadence.com/en_US/home/training/all-courses/82143.html)
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34 | [Verilog HDL Programming Courses on Udemy](https://www.udemy.com/topic/verilog-hdl-programming/)
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36 | [Top Verilog Programming Courses on Coursera](https://www.coursera.org/courses?query=verilog)
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38 | [Verilog course for Engineers on Technobyte](https://technobyte.org/verilog-course-tutorials/)
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40 | [Verilog Tutorials and Courses on hackr.io](https://hackr.io/tutorials/learn-verilog)
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42 | [Designing With Verilog Certification from the Xilinx Learning Center](https://xilinxprod-catalog.netexam.com/Certification/35916/designing-with-verilog)
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44 | [Learning Verilog for FPGA Development on LinkedIn Learning](https://www.linkedin.com/learning/learning-verilog-for-fpga-development)
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46 | [SystemVerilog tutorial on ChipVerify](https://www.chipverify.com/systemverilog/systemverilog-tutorial)
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48 | # Verilog/SystemVerilog Tools & Frameworks
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50 | [Apio](https://github.com/FPGAwars/apio) is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your verilog designs.
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52 | [IceStorm](https://github.com/YosysHQ/icestorm) is a project that aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
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54 | [Icestudio](https://icestudio.io/) is a visual editor for open FPGA boards. Built on top of the Icestorm project using Apio.
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56 | [EDA Playground](https://www.edaplayground.com) is a online code for programming your Verilog projects.
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58 | [PlatformIO](https://platformio.org/) is a professional collaborative platform for embedded development with no vendor lock-in. It provides support for multiplatforms and frameworks such as IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbed OS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V.
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60 | [PlatformIO for VSCode](https://marketplace.visualstudio.com/items?itemName=platformio.platformio-ide) is a plugin that provides support for the PlatformIO IDE on VSCode.
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62 | [LLVM](https://llvm.org/) is a collection of modular and reusable compiler and toolchain technologies. It can be used to develop a front end for any programming language and a back end for any instruction set architecture(ISA). LLVM code representation is designed to be used in three different forms: as an in-memory compiler IR, as an on-disk bitcode representation (suitable for fast loading by a Just-In-Time compiler), and as a human readable assembly language representation.
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64 | [Chisel](https://www.chisel-lang.org/) is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the [Scala](https://www.scala-lang.org/) programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
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66 | [Clash compiler](https://www.clash-lang.org/) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
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68 | [Verilator](https://verilator.org/) is an open-source SystemVerilog simulator and lint system.
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70 | [Verilog to Routing(VTR)](https://verilogtorouting.org/) is a collaborative project to provide a open-source framework for conducting FPGA architecture and CAD Research & Development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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72 | [Cascade](https://github.com/vmware/cascade) is a Just-In-Time Compiler for Verilog from VMware Research. Cascade executes code immediately in a software simulator, and performs compilation in the background. When compilation is finished, the code is moved into hardware, and from the user’s perspective it simply gets faster over time.
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74 | [OpenTimer](https://github.com/OpenTimer/OpenTimer) is a High-Performance Timing Analysis Tool for VLSI Systems.
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77 | ## Contribute
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79 | - [x] If would you like to contribute to this guide simply make a [Pull Request](https://github.com/mikeroyal/Verilog-SystemVerilog-Guide/pulls).
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82 | ## License
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84 | Distributed under the [Creative Commons Attribution 4.0 International (CC BY 4.0) Public License](https://creativecommons.org/licenses/by/4.0/).
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