├── Basic ├── libraries │ ├── new_lib.gds │ └── ICPS2023_5_Basic.gds ├── doc │ └── readme.html └── grain.xml ├── Technology ├── tech │ ├── models │ │ ├── SOI_CMOS~ │ │ ├── MF_CMOS20240109.txt │ │ ├── MF_CMOS20230922.txt │ │ └── SOI_CMOS │ ├── OR_to_ICPS.txt │ ├── symbols │ │ ├── Xschem │ │ │ ├── lab_pin.sym │ │ │ ├── netlist.sym │ │ │ ├── code_shown.sym │ │ │ ├── opin.sym │ │ │ ├── gnd.sym │ │ │ ├── ipin.sym │ │ │ ├── iopin.sym │ │ │ ├── NDIO_MIN.sym │ │ │ ├── PDIO_MIN.sym │ │ │ ├── vac.sym │ │ │ ├── voltage.sym │ │ │ ├── vpulse.sym │ │ │ ├── vsin.sym │ │ │ ├── code.sym │ │ │ ├── NMOS_ESD_MIN.sym │ │ │ ├── PMOS_ESD_MIN.sym │ │ │ ├── cap.sym │ │ │ ├── CAP_MIN.sym │ │ │ ├── res.sym │ │ │ ├── RES_MIN.sym │ │ │ ├── HR_POLY_MIN.sym │ │ │ ├── HVNMOS_MIN.sym │ │ │ ├── R_POLY_MIN.sym │ │ │ ├── NMOS_MIN.sym │ │ │ ├── PMOS_MIN.sym │ │ │ └── HVPMOS_MIN.sym │ │ ├── LTspice │ │ │ └── MinedaLIB │ │ │ │ ├── NDIO_MIN.asy │ │ │ │ ├── PDIO_MIN.asy │ │ │ │ ├── CAP_MIN.asy │ │ │ │ ├── RES_MIN.asy │ │ │ │ ├── NMOS_ESD_MIN.asy │ │ │ │ ├── PMOS_ESD_MIN.asy │ │ │ │ ├── HR_POLY_MIN.asy │ │ │ │ ├── R_POLY_MIN.asy │ │ │ │ ├── NMOS_MIN.asy │ │ │ │ └── PMOS_MIN.asy │ │ └── EEschema │ │ │ ├── MinedaSymbols.lib~ │ │ │ └── MinedaSymbols.lib │ ├── macros │ │ ├── metalize_bridges.lym │ │ ├── revert_from_metals.lym │ │ ├── change PCell defaults.lym │ │ ├── force_ongrid.lym │ │ ├── Backannotate device parasitics.lym │ │ ├── autoplace.lym │ │ ├── Documents │ │ │ ├── PDK user manual.lym │ │ │ ├── PDK reference manual.lym │ │ │ └── minimall Fab SOI CMOS PDK document.lym │ │ ├── convert library cells.lym │ │ ├── get_reference.lym │ │ ├── SOI_TEG_to_Mineda2022_6.lym │ │ └── XsectionUI.lym │ ├── drc │ │ ├── area_cut.lydrc │ │ ├── ICPS2023_5_to_SOI.lydrc │ │ └── drc.lydrc │ ├── AIST-SOI-CMOS.xs │ ├── YSS-SOI-CMOS.xs │ ├── tech.lyt │ ├── YSS-SOI-CMOS_Xsection.lyp │ ├── ICPS_SOI.lyp │ └── ICPS2023_5.lyp ├── doc │ ├── PDK_minimalFabSOICMOS.pdf │ └── PDK_reference_manual.pdf └── grain.xml ├── Samples └── Semicon2023 │ ├── NAND │ ├── nand_min_tb.raw │ ├── nand_sample.GDS │ ├── nand_min_tb.op.raw │ ├── floating_devices.asy │ ├── nand_sample.yaml │ ├── nand_min.asy │ ├── nand_min_tb.asc │ ├── lvs_work │ │ ├── nand_sample_lvs_settings.rb │ │ ├── nand_chip.net.txt │ │ ├── nand_sample_reference.cir.txt │ │ └── nand_sample_output.cir.txt │ ├── nand_min.asc │ ├── nand_min_tb.plt │ ├── nand_min_and_floating_devices.asc │ ├── floating_devices.asc │ ├── nand_chip.asc │ ├── nand_min_tb.log │ ├── nand_sample_output.cir │ └── nand_sample_ba.yaml │ └── base_contest2023.GDS ├── README.md └── LICENSE /Basic/libraries/new_lib.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mineda-support/ICPS2023_5/HEAD/Basic/libraries/new_lib.gds -------------------------------------------------------------------------------- /Technology/tech/models/SOI_CMOS~: -------------------------------------------------------------------------------- 1 | .include ./mosfet_model_YSS_SOI_PMOS.txt 2 | .include ./mosfet_model_YSS_SOI_NMOS.txt -------------------------------------------------------------------------------- /Basic/libraries/ICPS2023_5_Basic.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mineda-support/ICPS2023_5/HEAD/Basic/libraries/ICPS2023_5_Basic.gds -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_min_tb.raw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mineda-support/ICPS2023_5/HEAD/Samples/Semicon2023/NAND/nand_min_tb.raw -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_sample.GDS: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mineda-support/ICPS2023_5/HEAD/Samples/Semicon2023/NAND/nand_sample.GDS -------------------------------------------------------------------------------- /Samples/Semicon2023/base_contest2023.GDS: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mineda-support/ICPS2023_5/HEAD/Samples/Semicon2023/base_contest2023.GDS -------------------------------------------------------------------------------- /Technology/doc/PDK_minimalFabSOICMOS.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mineda-support/ICPS2023_5/HEAD/Technology/doc/PDK_minimalFabSOICMOS.pdf -------------------------------------------------------------------------------- /Technology/doc/PDK_reference_manual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mineda-support/ICPS2023_5/HEAD/Technology/doc/PDK_reference_manual.pdf -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_min_tb.op.raw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mineda-support/ICPS2023_5/HEAD/Samples/Semicon2023/NAND/nand_min_tb.op.raw -------------------------------------------------------------------------------- /Technology/tech/OR_to_ICPS.txt: -------------------------------------------------------------------------------- 1 | 3/0:3/0 2 | 5/0:5/0 3 | 7/0:7/0 4 | 8/0:8/0 5 | 13/0:13/0 6 | 14/0:14/0 7 | 15/0:15/0 8 | 16/0:16/0 9 | 18/0:18/0 10 | 19/0:19/0 11 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/floating_devices.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal -17 1 269 215 4 | WINDOW 0 8 -24 Bottom 2 5 | PIN -16 0 LEFT 8 6 | PINATTR PinName x 7 | PINATTR SpiceOrder 1 8 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_sample.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | target: nand_sample 3 | reference: lvs_work/nand_sample_reference.cir.txt 4 | netlist: C:/Users/seiji/KLayout/salt/ICPS2023_5/Samples/Semicon2023/NAND/nand_chip.net 5 | schematic: C:/Users/seiji/KLayout/salt/ICPS2023_5/Samples/Semicon2023/NAND/nand_chip.asc 6 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/lab_pin.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.8 file_version=1.2} 2 | G {} 3 | K {type=label 4 | format="*.alias @lab" 5 | template="name=l1 sig_type=std_logic lab=xxx"} 6 | V {} 7 | S {} 8 | E {} 9 | B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in} 10 | T {@lab} -7.5 -8.125 0 1 0.33 0.33 {} 11 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/netlist.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.5_RC5 file_version=1.1} 2 | G {type=netlist_commands 3 | template="name=s1 value=blabla" 4 | format=" 5 | @value 6 | "} 7 | V {} 8 | S {} 9 | E {} 10 | L 4 0 -10 70 -10 {} 11 | L 4 0 -10 0 10 {} 12 | T {NETLIST} 5 -25 0 0 0.3 0.3 {} 13 | T {@value} 15 -5 0 0 0.3 0.3 {} 14 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/code_shown.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.9 file_version=1.2 } 2 | G {} 3 | K {type=netlist_commands 4 | template="name=s1 only_toplevel=false value=blabla" 5 | format=" 6 | @value 7 | "} 8 | V {} 9 | S {} 10 | E {} 11 | L 4 0 -10 70 -10 {} 12 | L 4 0 -10 0 10 {} 13 | T {@name} 5 -30 0 0 0.3 0.3 {} 14 | T {@value} 15 -5 0 0 0.3 0.3 {} 15 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/opin.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.8 file_version=1.2} 2 | G {} 3 | K {type=opin 4 | format="*.opin @lab" 5 | template="name=p1 lab=xxx" 6 | } 7 | V {} 8 | S {} 9 | E {} 10 | B 5 -0.009765619999999999 -0.009765619999999999 0.009765619999999999 0.009765619999999999 {name=p dir=in} 11 | P 5 6 -0 -5 0 5 8.125 5 14.375 0 8.125 -5 -0 -5 {fill=true} 12 | T {@lab} 20 -8.75 0 0 0.33 0.33 {} 13 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/gnd.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.2 } 2 | G {} 3 | K {type=label 4 | function0="L" 5 | global=true 6 | format="*.alias @lab" 7 | template="name=l1 lab=GND"} 8 | V {} 9 | S {} 10 | E {} 11 | L 4 0 0 0 12.5 {} 12 | L 4 -5 12.5 5 12.5 {} 13 | L 4 0 17.5 5 12.5 {} 14 | L 4 -5 12.5 0 17.5 {} 15 | B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout goto=0} 16 | T {@lab} 7.5 5 0 0 0.2 0.2 {} 17 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/ipin.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.8 file_version=1.2} 2 | G {} 3 | K {type=ipin 4 | format="*.ipin @lab" 5 | template="name=p1 lab=xxx" 6 | } 7 | V {} 8 | S {} 9 | E {} 10 | B 5 -0.009765619999999999 -0.009765619999999999 0.009765619999999999 0.009765619999999999 {name=p dir=out} 11 | P 5 6 -0 -0 -6.25 -5 -14.375 -5 -14.375 5 -6.25 5 0 0 {fill=true} 12 | T {@lab} -18.75 -8.75 0 1 0.33 0.33 {} 13 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/iopin.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.5_RC5 file_version=1.1} 2 | G {type=iopin 3 | format="*.iopin @lab" 4 | template="name=p1 lab=xxx" 5 | } 6 | V {} 7 | S {} 8 | E {} 9 | B 5 -0.0098 -0.009765619999999999 0.0098 0.009765619999999999 {name=p dir=inout} 10 | P 5 7 0 0 5.625 -4.84375 10.7812 -4.84375 16.4062 -0 10.7812 4.84375 5.625 4.84375 -0 0 {fill=true} 11 | T {@lab} 19.8438 -8.75 0 0 0.33 0.33 {} 12 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/NDIO_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType CELL 3 | LINE Normal 0 96 0 56 4 | LINE Normal -16 56 16 56 5 | LINE Normal 0 32 0 0 6 | LINE Normal -16 32 16 32 7 | LINE Normal 16 32 0 56 8 | LINE Normal 0 56 -16 32 9 | WINDOW 0 48 32 Left 2 10 | WINDOW 3 48 64 Left 2 11 | SYMATTR Value NDIO 12 | SYMATTR Prefix D 13 | PIN 0 0 NONE 0 14 | PINATTR PinName PLUS 15 | PINATTR SpiceOrder 1 16 | PIN 0 96 NONE 0 17 | PINATTR PinName MINUS 18 | PINATTR SpiceOrder 2 19 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/PDIO_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType CELL 3 | LINE Normal 0 96 0 56 4 | LINE Normal -16 56 16 56 5 | LINE Normal 0 32 0 0 6 | LINE Normal -16 32 16 32 7 | LINE Normal 16 32 0 56 8 | LINE Normal 0 56 -16 32 9 | WINDOW 0 48 32 Left 2 10 | WINDOW 3 48 64 Left 2 11 | SYMATTR Value PDIO 12 | SYMATTR Prefix D 13 | PIN 0 0 NONE 0 14 | PINATTR PinName PLUS 15 | PINATTR SpiceOrder 1 16 | PIN 0 96 NONE 0 17 | PINATTR PinName MINUS 18 | PINATTR SpiceOrder 2 19 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/NDIO_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type= 3 | 4 | } 5 | V {} 6 | S {} 7 | E {} 8 | L 4 0 60 0 35 {} 9 | L 4 -10 35 10 35 {} 10 | L 4 0 20 0 0 {} 11 | L 4 -10 20 10 20 {} 12 | L 4 10 20 0 35 {} 13 | L 4 0 35 -10 20 {} 14 | B 5 -2 -2 2 2 {name=PLUS dir=in} 15 | T {PLUS} 0 0 0 0.2 0.2 {layer=13} 16 | B 5 -2 58 2 62 {name=MINUS dir=in} 17 | T {MINUS} 0 60 0 0.2 0.2 {layer=13} 18 | T {@value} 30 40 0 0 0.20 0.2 {} 19 | T {@name} 30 20 0 0 0.2 0.2 {} 20 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/PDIO_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type= 3 | 4 | } 5 | V {} 6 | S {} 7 | E {} 8 | L 4 0 60 0 35 {} 9 | L 4 -10 35 10 35 {} 10 | L 4 0 20 0 0 {} 11 | L 4 -10 20 10 20 {} 12 | L 4 10 20 0 35 {} 13 | L 4 0 35 -10 20 {} 14 | B 5 -2 -2 2 2 {name=PLUS dir=in} 15 | T {PLUS} 0 0 0 0.2 0.2 {layer=13} 16 | B 5 -2 58 2 62 {name=MINUS dir=in} 17 | T {MINUS} 0 60 0 0.2 0.2 {layer=13} 18 | T {@value} 30 40 0 0 0.20 0.2 {} 19 | T {@name} 30 20 0 0 0.2 0.2 {} 20 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/CAP_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType CELL 3 | LINE Normal 16 35 -16 35 4 | LINE Normal 0 0 0 35 5 | LINE Normal 0 48 0 96 6 | LINE Normal -22 48 -22 41 7 | LINE Normal 22 48 -22 48 8 | LINE Normal 22 41 22 48 9 | LINE Normal 22 41 22 41 10 | WINDOW 0 32 0 Left 2 11 | WINDOW 3 32 64 Left 2 12 | SYMATTR Value CAP 13 | SYMATTR Prefix C 14 | PIN 0 0 NONE 0 15 | PINATTR PinName PLUS 16 | PINATTR SpiceOrder 1 17 | PIN 0 96 NONE 0 18 | PINATTR PinName MINUS 19 | PINATTR SpiceOrder 2 20 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/RES_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType CELL 3 | LINE Normal 0 96 0 77 4 | LINE Normal 0 77 -16 72 5 | LINE Normal -16 72 16 62 6 | LINE Normal 16 62 -16 53 7 | LINE Normal -16 53 16 43 8 | LINE Normal 16 43 -16 34 9 | LINE Normal -16 34 16 24 10 | LINE Normal 16 24 0 19 11 | LINE Normal 0 19 0 0 12 | WINDOW 0 32 0 Left 2 13 | WINDOW 3 32 48 Left 2 14 | SYMATTR Value RES 15 | SYMATTR Prefix R 16 | PIN 0 0 NONE 0 17 | PINATTR PinName PLUS 18 | PINATTR SpiceOrder 1 19 | PIN 0 96 NONE 0 20 | PINATTR PinName MINUS 21 | PINATTR SpiceOrder 2 22 | -------------------------------------------------------------------------------- /Technology/tech/macros/metalize_bridges.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | Metalize bridges 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | ruby 17 | 18 | mb = MinedaBridge.new 19 | mb.metalize_bridges(true) 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/NMOS_ESD_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal 32 64 96 64 4 | LINE Normal 0 192 0 0 5 | LINE Normal 0 0 128 0 6 | LINE Normal 128 0 128 192 7 | LINE Normal 128 192 0 192 8 | LINE Normal 64 64 32 128 9 | LINE Normal 32 128 96 128 10 | LINE Normal 96 128 64 64 11 | LINE Normal 64 0 64 64 12 | LINE Normal 64 192 64 128 13 | WINDOW 0 48 32 Left 0 14 | WINDOW 3 48 64 Left 0 15 | WINDOW 123 48 96 Left 0 16 | PIN 64 0 BOTTOM 0 17 | PINATTR PinName PAD 18 | PINATTR SpiceOrder 1 19 | PIN 64 192 BOTTOM 0 20 | PINATTR PinName VSS 21 | PINATTR SpiceOrder 2 22 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/PMOS_ESD_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal 32 64 96 64 4 | LINE Normal 0 192 0 0 5 | LINE Normal 0 0 128 0 6 | LINE Normal 128 0 128 192 7 | LINE Normal 128 192 0 192 8 | LINE Normal 64 64 32 128 9 | LINE Normal 32 128 96 128 10 | LINE Normal 96 128 64 64 11 | LINE Normal 64 0 64 64 12 | LINE Normal 64 192 64 128 13 | WINDOW 0 48 32 Left 0 14 | WINDOW 3 48 64 Left 0 15 | WINDOW 123 48 96 Left 0 16 | PIN 64 0 BOTTOM 0 17 | PINATTR PinName VDD 18 | PINATTR SpiceOrder 2 19 | PIN 64 192 BOTTOM 0 20 | PINATTR PinName PAD 21 | PINATTR SpiceOrder 1 22 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/vac.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.7 file_version=1.1} 2 | G {type=vsource 3 | format="@name @pinlist @value" 4 | template="name=V1 value=3" 5 | 6 | } 7 | V {} 8 | S {} 9 | E {} 10 | L 4 -5 22 5 22 {} 11 | L 4 -5 47 5 47 {} 12 | L 4 0 17 0 27 {} 13 | L 4 0 60 0 55 {} 14 | L 4 0 10 0 15 {} 15 | A 3 0 35 20 0 360 {} 16 | B 5 -2 8 2 12 {name=+ dir=in pinnumber=1} 17 | T {@#0:pinnumber} -3 4 0 1 0.2 0.2 {layer=13} 18 | B 5 -2 58 2 62 {name=- dir=in pinnumber=2} 19 | T {@#1:pinnumber} -3 54 0 1 0.2 0.2 {layer=13} 20 | T {@value} 15 60 0 0 0.20 0.2 {} 21 | T {@name} 15 10 0 0 0.2 0.2 {} 22 | -------------------------------------------------------------------------------- /Technology/tech/macros/revert_from_metals.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | Non-metalize bridges (revert from metals) 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | ruby 17 | 18 | mb = MinedaBridge.new 19 | mb.metalize_bridges(nil) 20 | 21 | 22 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/HR_POLY_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType CELL 3 | LINE Normal 0 96 0 77 4 | LINE Normal 0 77 -16 72 5 | LINE Normal -16 72 16 62 6 | LINE Normal 16 62 -16 53 7 | LINE Normal -16 53 16 43 8 | LINE Normal 16 43 -16 34 9 | LINE Normal -16 34 16 24 10 | LINE Normal 16 24 0 19 11 | LINE Normal 0 19 0 0 12 | LINE Normal 0 67 0 29 13 | WINDOW 0 32 0 Left 2 14 | WINDOW 3 32 48 Left 2 15 | SYMATTR Value HR_POLY 16 | SYMATTR Prefix R 17 | PIN 0 0 NONE 0 18 | PINATTR PinName PLUS 19 | PINATTR SpiceOrder 1 20 | PIN 0 96 NONE 0 21 | PINATTR PinName MINUS 22 | PINATTR SpiceOrder 2 23 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/voltage.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.7 file_version=1.1} 2 | G {type=vsource 3 | format="@name @pinlist @value" 4 | template="name=V1 value=3" 5 | 6 | } 7 | V {} 8 | S {} 9 | E {} 10 | L 4 -5 22 5 22 {} 11 | L 4 -5 47 5 47 {} 12 | L 4 0 17 0 27 {} 13 | L 4 0 60 0 55 {} 14 | L 4 0 10 0 15 {} 15 | A 3 0 35 20 0 360 {} 16 | B 5 -2 8 2 12 {name=+ dir=in pinnumber=1} 17 | T {@#0:pinnumber} -3 4 0 1 0.2 0.2 {layer=13} 18 | B 5 -2 58 2 62 {name=- dir=in pinnumber=2} 19 | T {@#1:pinnumber} -3 54 0 1 0.2 0.2 {layer=13} 20 | T {@value} 15 60 0 0 0.20 0.2 {} 21 | T {@name} 15 10 0 0 0.2 0.2 {} 22 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/vpulse.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.7 file_version=1.1} 2 | G {type=vsource 3 | format="@name @pinlist @value" 4 | template="name=V1 value=3" 5 | 6 | } 7 | V {} 8 | S {} 9 | E {} 10 | L 4 -5 22 5 22 {} 11 | L 4 -5 47 5 47 {} 12 | L 4 0 17 0 27 {} 13 | L 4 0 60 0 55 {} 14 | L 4 0 10 0 15 {} 15 | A 3 0 35 20 0 360 {} 16 | B 5 -2 8 2 12 {name=+ dir=in pinnumber=1} 17 | T {@#0:pinnumber} -3 4 0 1 0.2 0.2 {layer=13} 18 | B 5 -2 58 2 62 {name=- dir=in pinnumber=2} 19 | T {@#1:pinnumber} -3 54 0 1 0.2 0.2 {layer=13} 20 | T {@value} 15 60 0 0 0.20 0.2 {} 21 | T {@name} 15 10 0 0 0.2 0.2 {} 22 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/vsin.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.7 file_version=1.1} 2 | G {type=vsource 3 | format="@name @pinlist @value" 4 | template="name=V1 value=3" 5 | 6 | } 7 | V {} 8 | S {} 9 | E {} 10 | L 4 -5 22 5 22 {} 11 | L 4 -5 47 5 47 {} 12 | L 4 0 17 0 27 {} 13 | L 4 0 60 0 55 {} 14 | L 4 0 10 0 15 {} 15 | A 3 0 35 20 0 360 {} 16 | B 5 -2 8 2 12 {name=+ dir=in pinnumber=1} 17 | T {@#0:pinnumber} -3 4 0 1 0.2 0.2 {layer=13} 18 | B 5 -2 58 2 62 {name=- dir=in pinnumber=2} 19 | T {@#1:pinnumber} -3 54 0 1 0.2 0.2 {layer=13} 20 | T {@value} 15 60 0 0 0.20 0.2 {} 21 | T {@name} 15 10 0 0 0.2 0.2 {} 22 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/R_POLY_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType CELL 3 | LINE Normal 0 96 0 77 4 | LINE Normal 0 77 -16 72 5 | LINE Normal -16 72 16 62 6 | LINE Normal 16 62 -16 53 7 | LINE Normal -16 53 16 43 8 | LINE Normal 16 43 -16 34 9 | LINE Normal -16 34 16 24 10 | LINE Normal 16 24 0 19 11 | LINE Normal 0 19 0 0 12 | LINE Normal 0 29 0 19 13 | LINE Normal 0 67 0 77 14 | WINDOW 0 32 0 Left 2 15 | WINDOW 3 32 48 Left 2 16 | SYMATTR Value R_POLY 17 | SYMATTR Prefix R 18 | PIN 0 0 NONE 0 19 | PINATTR PinName PLUS 20 | PINATTR SpiceOrder 1 21 | PIN 0 96 NONE 0 22 | PINATTR PinName MINUS 23 | PINATTR SpiceOrder 2 24 | -------------------------------------------------------------------------------- /Technology/tech/macros/change PCell defaults.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | Change PCell defauts for Mineda2022_6 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 12 | true 13 | 14 | 15 | ruby 16 | 17 | module MyMacro 18 | include MinedaCommon 19 | pd = PCellDefaults.new 20 | pd.change_pcell_defaults 21 | end 22 | 23 | 24 | -------------------------------------------------------------------------------- /Technology/tech/macros/force_ongrid.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | Non-metalize bridges(revert from metals) 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | ruby 17 | 18 | module MyMacro 19 | ogc = MinedaGridCheck.new ($ICPS_grid || 1.0.um) 20 | ogc.do_check 21 | end 22 | 23 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/code.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.5_RC5 file_version=1.1} 2 | G {type=netlist_commands 3 | template="name=s1 only_toplevel=false value=blabla" 4 | format=" 5 | @value 6 | "} 7 | V {} 8 | S {} 9 | E {} 10 | L 4 20 30 60 30 {} 11 | L 4 20 40 40 40 {} 12 | L 4 20 50 60 50 {} 13 | L 4 20 60 50 60 {} 14 | L 4 20 70 50 70 {} 15 | L 4 20 80 90 80 {} 16 | L 4 20 90 40 90 {} 17 | L 4 20 20 70 20 {} 18 | L 4 20 10 40 10 {} 19 | L 4 100 10 110 10 {} 20 | L 4 110 10 110 110 {} 21 | L 4 20 110 110 110 {} 22 | L 4 20 100 20 110 {} 23 | L 4 100 0 100 100 {} 24 | L 4 10 100 100 100 {} 25 | L 4 10 0 10 100 {} 26 | L 4 10 0 100 0 {} 27 | T {@name} 15 -25 0 0 0.3 0.3 {} 28 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/NMOS_ESD_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | 6 | } 7 | V {} 8 | S {} 9 | E {} 10 | L 4 20 40 60 40 {} 11 | L 4 0 120 0 0 {} 12 | L 4 0 0 80 0 {} 13 | L 4 80 0 80 120 {} 14 | L 4 80 120 0 120 {} 15 | L 4 40 40 20 80 {} 16 | L 4 20 80 60 80 {} 17 | L 4 60 80 40 40 {} 18 | L 4 40 0 40 40 {} 19 | L 4 40 120 40 80 {} 20 | B 5 38 -2 42 2 {name=PAD dir=in} 21 | T {PAD} 40 0 3 0 0.2 0.2 {layer=13} 22 | B 5 38 118 42 122 {name=VSS dir=in} 23 | T {VSS} 40 120 3 0 0.2 0.2 {layer=13} 24 | T {@value} 30 40 0 0 0.20 0.2 {} 25 | T {@name} 30 20 0 0 0.2 0.2 {} 26 | T {@symname} 30 60 0 0 0.20 0.2 {} 27 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/PMOS_ESD_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | 6 | } 7 | V {} 8 | S {} 9 | E {} 10 | L 4 20 40 60 40 {} 11 | L 4 0 120 0 0 {} 12 | L 4 0 0 80 0 {} 13 | L 4 80 0 80 120 {} 14 | L 4 80 120 0 120 {} 15 | L 4 40 40 20 80 {} 16 | L 4 20 80 60 80 {} 17 | L 4 60 80 40 40 {} 18 | L 4 40 0 40 40 {} 19 | L 4 40 120 40 80 {} 20 | B 5 38 118 42 122 {name=PAD dir=in} 21 | T {PAD} 40 120 3 0 0.2 0.2 {layer=13} 22 | B 5 38 -2 42 2 {name=VDD dir=in} 23 | T {VDD} 40 0 3 0 0.2 0.2 {layer=13} 24 | T {@value} 30 40 0 0 0.20 0.2 {} 25 | T {@name} 30 20 0 0 0.2 0.2 {} 26 | T {@symname} 30 60 0 0 0.20 0.2 {} 27 | -------------------------------------------------------------------------------- /Technology/tech/macros/Backannotate device parasitics.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | Backannotate device parasitics 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | ruby 17 | 18 | module MyMacro 19 | 20 | include BackannotateModule 21 | ba = Backannotate.new NCH: 'NMOS', PCH: 'PMOS' 22 | ba.do_backannotate 23 | 24 | end 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_min.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 -79 -16 -79 4 | LINE Normal -31 -80 -16 -80 5 | LINE Normal -32 -16 -32 -80 6 | LINE Normal -33 -16 -16 -16 7 | LINE Normal -32 -64 -48 -64 8 | LINE Normal -32 -32 -48 -32 9 | LINE Normal -16 -16 -32 -32 10 | CIRCLE Normal 32 -40 16 -56 11 | ARC Normal -48 -80 16 -16 -15 -16 -16 -79 12 | WINDOW 0 32 -80 Bottom 2 13 | PIN -48 -64 NONE 8 14 | PINATTR PinName A 15 | PINATTR SpiceOrder 1 16 | PIN -48 -32 NONE 8 17 | PINATTR PinName B 18 | PINATTR SpiceOrder 2 19 | PIN -16 -80 NONE 8 20 | PINATTR PinName VDD 21 | PINATTR SpiceOrder 3 22 | PIN 0 -16 NONE 8 23 | PINATTR PinName VSS 24 | PINATTR SpiceOrder 4 25 | PIN 32 -48 NONE 8 26 | PINATTR PinName Y 27 | PINATTR SpiceOrder 5 28 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/NMOS_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType CELL 3 | LINE Normal 32 -22 64 -22 4 | LINE Normal 64 -22 64 -48 5 | LINE Normal 32 32 32 -32 6 | LINE Normal 50 16 64 22 7 | LINE Normal 64 22 50 28 8 | LINE Normal 0 0 24 0 9 | LINE Normal 24 -24 24 24 10 | LINE Normal 32 0 64 0 11 | LINE Normal 32 22 50 22 12 | LINE Normal 64 22 64 48 13 | LINE Normal 50 28 50 16 14 | WINDOW 0 80 -48 Left 2 15 | WINDOW 3 81 16 Left 2 16 | SYMATTR Value nch 17 | SYMATTR Prefix M 18 | PIN 64 -48 NONE 0 19 | PINATTR PinName D 20 | PINATTR SpiceOrder 1 21 | PIN 0 0 NONE 0 22 | PINATTR PinName G 23 | PINATTR SpiceOrder 2 24 | PIN 64 48 NONE 0 25 | PINATTR PinName S 26 | PINATTR SpiceOrder 3 27 | PIN 64 0 NONE 0 28 | PINATTR PinName B 29 | PINATTR SpiceOrder 4 30 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/cap.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.7 file_version=1.1} 2 | G {type=capacitor 3 | format="@name @pinlist @value m=@m" 4 | tedax_format="footprint @name @footprint 5 | value @name @value 6 | device @name @device 7 | @comptag" 8 | verilog_ignore=true 9 | template="name=C1 10 | m=1 11 | value=1p 12 | footprint=1206 13 | device=\"ceramic capacitor\"" 14 | 15 | } 16 | V {} 17 | S {} 18 | E {} 19 | L 4 10 22 10 40 {} 20 | L 4 10 17 10 0 {} 21 | L 4 0 17 20 17 {} 22 | L 4 0 22 20 22 {} 23 | B 5 8 -2 12 2 {name=A dir=in pinnumber=1} 24 | T {@#0:pinnumber} 7 -6 0 1 0.2 0.2 {layer=13} 25 | B 5 8 38 12 42 {name=B dir=in pinnumber=2} 26 | T {@#1:pinnumber} 7 34 0 1 0.2 0.2 {layer=13} 27 | T {@value} 15 35 0 0 0.20 0.2 {} 28 | T {@name} 15 5 0 0 0.2 0.2 {} 29 | -------------------------------------------------------------------------------- /Technology/tech/symbols/LTspice/MinedaLIB/PMOS_MIN.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType CELL 3 | LINE Normal 24 -24 24 24 4 | LINE Normal 32 22 64 22 5 | LINE Normal 64 22 64 48 6 | LINE Normal 47 -22 64 -22 7 | LINE Normal 64 -22 64 -48 8 | LINE Normal 0 0 24 0 9 | LINE Normal 32 0 64 0 10 | LINE Normal 32 32 32 -32 11 | LINE Normal 32 -22 47 -28 12 | LINE Normal 47 -17 32 -22 13 | LINE Normal 47 -17 47 -28 14 | WINDOW 0 80 -48 Left 2 15 | WINDOW 3 80 16 Left 2 16 | SYMATTR Value pch 17 | SYMATTR Prefix M 18 | PIN 64 48 NONE 0 19 | PINATTR PinName D 20 | PINATTR SpiceOrder 1 21 | PIN 0 0 NONE 0 22 | PINATTR PinName G 23 | PINATTR SpiceOrder 2 24 | PIN 64 -48 NONE 0 25 | PINATTR PinName S 26 | PINATTR SpiceOrder 3 27 | PIN 64 0 NONE 0 28 | PINATTR PinName B 29 | PINATTR SpiceOrder 4 30 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/CAP_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type=capacitor 3 | format="@name @pinlist @value m=@m" 4 | tedax_format="footprint @name @footprint 5 | value @name @value 6 | device @name @device 7 | @comptag" 8 | verilog_ignore=true 9 | template="name=C1 10 | m=1 11 | value=1p 12 | footprint=1206 13 | device=\"ceramic capacitor\"" 14 | 15 | } 16 | V {} 17 | S {} 18 | E {} 19 | L 4 10 21 -10 21 {} 20 | L 4 0 0 0 21 {} 21 | L 4 0 30 0 60 {} 22 | L 4 -14 30 -14 25 {} 23 | L 4 13 30 -14 30 {} 24 | L 4 13 25 13 30 {} 25 | L 4 13 25 13 25 {} 26 | B 5 -2 -2 2 2 {name=PLUS dir=in} 27 | T {PLUS} 0 0 0 0.2 0.2 {layer=13} 28 | B 5 -2 58 2 62 {name=MINUS dir=in} 29 | T {MINUS} 0 60 0 0.2 0.2 {layer=13} 30 | T {@value} 20 40 0 0 0.20 0.2 {} 31 | T {@name} 20 0 0 0 0.2 0.2 {} 32 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/res.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=2.9.7 file_version=1.1} 2 | G {type=resistor 3 | format="@name @pinlist @value m=@m" 4 | verilog_format="tran @name (@@P\\, @@M\\);" 5 | tedax_format="footprint @name @footprint 6 | value @name @value 7 | device @name @device 8 | @comptag" 9 | template="name=R1 10 | value=1k 11 | footprint=1206 12 | device=resistor 13 | m=1" 14 | 15 | } 16 | V {} 17 | S {} 18 | E {} 19 | L 4 10 55 10 60 {} 20 | L 4 0 50 10 55 {} 21 | L 4 20 40 0 50 {} 22 | L 4 0 30 20 40 {} 23 | L 4 20 20 0 30 {} 24 | L 4 10 10 10 15 {} 25 | L 4 10 15 20 20 {} 26 | B 5 8 8 12 12 {name=A dir=in pinnumber=1} 27 | T {@#0:pinnumber} 7 4 0 1 0.2 0.2 {layer=13} 28 | B 5 8 58 12 62 {name=B dir=in pinnumber=2} 29 | T {@#1:pinnumber} 7 54 0 1 0.2 0.2 {layer=13} 30 | T {@value} 22 47 0 0 0.20 0.2 {} 31 | T {@name} 22 25 0 0 0.2 0.2 {} 32 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/RES_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type=resistor 3 | format="@name @pinlist @value m=@m" 4 | verilog_format="tran @name (@@P\\, @@M\\);" 5 | tedax_format="footprint @name @footprint 6 | value @name @value 7 | device @name @device 8 | @comptag" 9 | template="name=R1 10 | value=1k 11 | footprint=1206 12 | device=resistor 13 | m=1" 14 | 15 | } 16 | V {} 17 | S {} 18 | E {} 19 | L 4 0 60 0 48 {} 20 | L 4 0 48 -10 45 {} 21 | L 4 -10 45 10 38 {} 22 | L 4 10 38 -10 33 {} 23 | L 4 -10 33 10 26 {} 24 | L 4 10 26 -10 21 {} 25 | L 4 -10 21 10 15 {} 26 | L 4 10 15 0 11 {} 27 | L 4 0 11 0 0 {} 28 | B 5 -2 -2 2 2 {name=PLUS dir=in} 29 | T {PLUS} 0 0 0 0.2 0.2 {layer=13} 30 | B 5 -2 58 2 62 {name=MINUS dir=in} 31 | T {MINUS} 0 60 0 0.2 0.2 {layer=13} 32 | T {@value} 20 30 0 0 0.20 0.2 {} 33 | T {@name} 20 0 0 0 0.2 0.2 {} 34 | -------------------------------------------------------------------------------- /Technology/tech/macros/autoplace.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | autoplace for ICPS2023_5 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | false 14 | 15 | 16 | ruby 17 | 18 | module MyMacro 19 | 20 | include RBA 21 | 22 | layout = MinedaAutoPlace.new(res: $res || 'R_ndiff', cap: $cap || 'Pdiff_cap', 23 | grid: $grid || 5, xscale: $xscale || 1000, yscale: $yscale || 1500, 24 | wmax: $wmax || 100 ) 25 | layout.autoplace 26 | 27 | end 28 | 29 | 30 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/HR_POLY_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type=resistor 3 | format="@name @pinlist @value m=@m" 4 | verilog_format="tran @name (@@P\\, @@M\\);" 5 | tedax_format="footprint @name @footprint 6 | value @name @value 7 | device @name @device 8 | @comptag" 9 | template="name=R1 10 | value=1k 11 | footprint=1206 12 | device=resistor 13 | m=1" 14 | 15 | } 16 | V {} 17 | S {} 18 | E {} 19 | L 4 0 60 0 48 {} 20 | L 4 0 48 -10 45 {} 21 | L 4 -10 45 10 38 {} 22 | L 4 10 38 -10 33 {} 23 | L 4 -10 33 10 26 {} 24 | L 4 10 26 -10 21 {} 25 | L 4 -10 21 10 15 {} 26 | L 4 10 15 0 11 {} 27 | L 4 0 11 0 0 {} 28 | L 4 0 41 0 18 {} 29 | B 5 -2 -2 2 2 {name=PLUS dir=in} 30 | T {PLUS} 0 0 0 0.2 0.2 {layer=13} 31 | B 5 -2 58 2 62 {name=MINUS dir=in} 32 | T {MINUS} 0 60 0 0.2 0.2 {layer=13} 33 | T {@value} 20 30 0 0 0.20 0.2 {} 34 | T {@name} 20 0 0 0 0.2 0.2 {} 35 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/HVNMOS_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type=nmos 3 | format="@name @pinlist @model w=@w l=@l m=@m" 4 | template="name=m1 model=n6.0 w=1u l=0.8u m=1"} 5 | } 6 | V {} 7 | S {} 8 | E {} 9 | L 4 20 -14 40 -14 {} 10 | L 4 40 -14 40 -30 {} 11 | L 4 31 10 40 13 {} 12 | L 4 40 13 31 17 {} 13 | L 4 0 0 15 0 {} 14 | L 4 15 -15 15 15 {} 15 | L 4 20 0 40 0 {} 16 | L 4 20 13 31 13 {} 17 | L 4 40 13 40 30 {} 18 | L 4 31 17 31 10 {} 19 | L 4 20 -11 20 -20 {} 20 | L 4 20 10 20 20 {} 21 | L 4 20 5 20 -6 {} 22 | B 5 38 -32 42 -28 {name=D dir=in} 23 | T {D} 40 -30 0 0.2 0.2 {layer=13} 24 | B 5 -2 -2 2 2 {name=G dir=in} 25 | T {G} 0 0 0 0.2 0.2 {layer=13} 26 | B 5 38 28 42 32 {name=S dir=in} 27 | T {S} 40 30 0 0.2 0.2 {layer=13} 28 | B 5 38 -2 42 2 {name=B dir=in} 29 | T {B} 40 0 0 0.2 0.2 {layer=13} 30 | T {@value} 50 10 0 0 0.20 0.2 {} 31 | T {@name} 50 -30 0 0 0.2 0.2 {} 32 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/R_POLY_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type=resistor 3 | format="@name @pinlist @value m=@m" 4 | verilog_format="tran @name (@@P\\, @@M\\);" 5 | tedax_format="footprint @name @footprint 6 | value @name @value 7 | device @name @device 8 | @comptag" 9 | template="name=R1 10 | value=1k 11 | footprint=1206 12 | device=resistor 13 | m=1" 14 | 15 | } 16 | V {} 17 | S {} 18 | E {} 19 | L 4 0 60 0 48 {} 20 | L 4 0 48 -10 45 {} 21 | L 4 -10 45 10 38 {} 22 | L 4 10 38 -10 33 {} 23 | L 4 -10 33 10 26 {} 24 | L 4 10 26 -10 21 {} 25 | L 4 -10 21 10 15 {} 26 | L 4 10 15 0 11 {} 27 | L 4 0 11 0 0 {} 28 | L 4 0 18 0 11 {} 29 | L 4 0 41 0 48 {} 30 | B 5 -2 -2 2 2 {name=PLUS dir=in} 31 | T {PLUS} 0 0 0 0.2 0.2 {layer=13} 32 | B 5 -2 58 2 62 {name=MINUS dir=in} 33 | T {MINUS} 0 60 0 0.2 0.2 {layer=13} 34 | T {@value} 20 30 0 0 0.20 0.2 {} 35 | T {@name} 20 0 0 0 0.2 0.2 {} 36 | -------------------------------------------------------------------------------- /Technology/tech/macros/Documents/PDK user manual.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | ICPS2023_5 PDK User Manual 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | ruby 17 | 18 | module MyMacro 19 | 20 | cmd = case RbConfig::CONFIG['host_os'] 21 | when /mswin|mingw|cygwin/ then "start " 22 | when /darwin/ then "open " 23 | when /linux|bsd/ then "xdg-open " 24 | else raise "No OS detected" 25 | end 26 | 27 | b = system cmd + "https://www.dropbox.com/scl/fi/84uzdzux0urhsd05mfxmb/ICPS2023_5-PDKv1.03.paper?rlkey=04jeibh2hrzlrlx4x9h5ghp4s&dl=0" 28 | 29 | end 30 | 31 | 32 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/NMOS_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.2 } 2 | G {} 3 | K {type=nmos4 4 | format="@spiceprefix@name @pinlist @model w=@w l=@l @extra as=@as ps=@ps ad=@ad pd=@pd m=@m" 5 | template="name=M1 model=nch w=5u l=0.18u as=0 ps=0 ad=0 pd=0 m=1" 6 | 7 | } 8 | V {} 9 | S {} 10 | E {} 11 | L 4 20 -14 40 -14 {} 12 | L 4 40 -30 40 -14 {} 13 | L 4 20 -20 20 20 {} 14 | L 4 31 10 40 13 {} 15 | L 4 31 17 40 13 {} 16 | L 4 0 0 15 0 {} 17 | L 4 15 -15 15 15 {} 18 | L 4 20 0 40 0 {} 19 | L 4 20 13 31 13 {} 20 | L 4 40 13 40 30 {} 21 | L 4 31 10 31 17 {} 22 | B 5 38 -32 42 -28 {name=D dir=in} 23 | B 5 -2 -2 2 2 {name=G dir=in} 24 | B 5 38 28 42 32 {name=S dir=in} 25 | B 5 38 -2 42 2 {name=B dir=in} 26 | T {D} 40 -30 0 0 0.2 0.2 {layer=13} 27 | T {G} 0 0 0 0 0.2 0.2 {layer=13} 28 | T {S} 40 30 0 0 0.2 0.2 {layer=13} 29 | T {B} 40 0 0 0 0.2 0.2 {layer=13} 30 | T {@value} 50 10 0 0 0.2 0.2 {} 31 | T {@name} 50 -30 0 0 0.2 0.2 {} 32 | T {@w\\/@l\\/@m} 20 0 0 0 0.2 0.2 {} 33 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/PMOS_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.2 } 2 | G {} 3 | K {type=pmos4 4 | format="@spiceprefix@name @pinlist @model w=@w l=@l @extra as=@as ps=@ps ad=@ad pd=@pd m=@m" 5 | template="name=M1 model=pch w=5u l=0.18u as=0 ps=0 ad=0 pd=0 m=1" 6 | 7 | } 8 | V {} 9 | S {} 10 | E {} 11 | L 4 15 -15 15 15 {} 12 | L 4 20 13 40 13 {} 13 | L 4 40 13 40 30 {} 14 | L 4 29 -14 40 -14 {} 15 | L 4 40 -30 40 -14 {} 16 | L 4 0 0 15 0 {} 17 | L 4 20 0 40 0 {} 18 | L 4 20 -20 20 20 {} 19 | L 4 20 -14 29 -18 {} 20 | L 4 20 -14 29 -11 {} 21 | L 4 29 -18 29 -11 {} 22 | B 5 38 28 42 32 {name=D dir=in} 23 | B 5 -2 -2 2 2 {name=G dir=in} 24 | B 5 38 -32 42 -28 {name=S dir=in} 25 | B 5 38 -2 42 2 {name=B dir=in} 26 | T {D} 40 30 0 0 0.2 0.2 {layer=13} 27 | T {G} 0 0 0 0 0.2 0.2 {layer=13} 28 | T {S} 40 -30 0 0 0.2 0.2 {layer=13} 29 | T {B} 40 0 0 0 0.2 0.2 {layer=13} 30 | T {@value} 50 10 0 0 0.2 0.2 {} 31 | T {@name} 50 -30 0 0 0.2 0.2 {} 32 | T {@w\\/@l\\/@m} 20 20 0 0 0.2 0.2 {} 33 | -------------------------------------------------------------------------------- /Technology/tech/symbols/Xschem/HVPMOS_MIN.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.0.0 file_version=1.1} 2 | G {type=pmos 3 | format="@name @pinlist @model w=@w l=@l m=@m" 4 | template="name=m1 model=p6.0 w=1u l=0.5u m=1"} 5 | } 6 | V {} 7 | S {} 8 | E {} 9 | L 4 15 -15 15 15 {} 10 | L 4 20 13 40 13 {} 11 | L 4 40 13 40 30 {} 12 | L 4 29 -14 40 -14 {} 13 | L 4 40 -14 40 -30 {} 14 | L 4 0 0 15 0 {} 15 | L 4 20 0 40 0 {} 16 | L 4 20 -14 29 -18 {} 17 | L 4 29 -11 20 -14 {} 18 | L 4 29 -11 29 -18 {} 19 | L 4 20 -11 20 -20 {} 20 | L 4 20 -11 20 -11 {} 21 | L 4 20 -11 20 -11 {} 22 | L 4 20 -11 20 -11 {} 23 | L 4 20 -11 20 -11 {} 24 | L 4 20 5 20 -6 {} 25 | L 4 20 20 20 10 {} 26 | B 5 38 28 42 32 {name=D dir=in} 27 | T {D} 40 30 0 0.2 0.2 {layer=13} 28 | B 5 -2 -2 2 2 {name=G dir=in} 29 | T {G} 0 0 0 0.2 0.2 {layer=13} 30 | B 5 38 -32 42 -28 {name=S dir=in} 31 | T {S} 40 -30 0 0.2 0.2 {layer=13} 32 | B 5 38 -2 42 2 {name=B dir=in} 33 | T {B} 40 0 0 0.2 0.2 {layer=13} 34 | T {@value} 50 10 0 0 0.20 0.2 {} 35 | T {@name} 50 -30 0 0 0.2 0.2 {} 36 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_min_tb.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 944 680 3 | WIRE 160 0 -128 0 4 | WIRE 160 32 160 0 5 | WIRE 128 48 16 48 6 | WIRE -128 64 -128 0 7 | WIRE 16 64 16 48 8 | WIRE 240 64 208 64 9 | WIRE 128 80 96 80 10 | WIRE 96 96 96 80 11 | WIRE -128 208 -128 144 12 | WIRE 16 208 16 144 13 | WIRE 16 208 -128 208 14 | WIRE 96 208 96 176 15 | WIRE 96 208 16 208 16 | WIRE 176 208 176 96 17 | WIRE 176 208 96 208 18 | WIRE 176 224 176 208 19 | FLAG 176 224 0 20 | FLAG 240 64 out 21 | IOPIN 240 64 Out 22 | FLAG 96 80 A 23 | FLAG 16 48 B 24 | SYMBOL nand_min 176 112 R0 25 | SYMATTR InstName X1 26 | SYMBOL voltage 16 48 R0 27 | SYMATTR InstName V1 28 | SYMATTR Value PULSE(0 3 0 0 0 2m 4m) 29 | SYMBOL voltage 96 80 R0 30 | WINDOW 123 0 0 Left 0 31 | WINDOW 39 0 0 Left 0 32 | SYMATTR InstName V2 33 | SYMATTR Value PULSE(0 3 0 0 0 1m 2m) 34 | SYMBOL voltage -128 48 R0 35 | SYMATTR InstName V3 36 | SYMATTR Value 3 37 | TEXT -72 264 Left 2 !.include %HOMEPATH%\\KLayout\\salt\\ICPS2023_5\\Technology\\tech\\models\\SOI_CMOS 38 | TEXT -74 284 Left 2 !.tran 10m 39 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/lvs_work/nand_sample_lvs_settings.rb: -------------------------------------------------------------------------------- 1 | def lvs_settings 2 | same_circuits 'nand', '.TOP' 3 | netlist.make_top_level_pins 4 | netlist.flatten_circuit 'Nch*' 5 | netlist.flatten_circuit 'Pch*' 6 | align 7 | same_device_classes 'NMOS', 'NCH' 8 | same_device_classes 'PMOS', 'PCH' 9 | same_device_classes 'MIMCAP', 'CAP' 10 | same_device_classes 'TINCAP', 'CAP' 11 | same_device_classes 'PDIFFCAP', 'CAP' 12 | same_device_classes 'NDIFFCAP', 'CAP' 13 | same_device_classes 'NRES', 'RES' 14 | same_device_classes 'PRES', 'RES' 15 | same_device_classes 'R_SOI', 'RES' 16 | tolerance 'RES', 'R', :relative => 0.03 17 | tolerance 'NRES', 'R', :relative => 0.03 18 | tolerance 'PRES', 'R', :relative => 0.03 19 | tolerance 'R_SOI', 'R', :relative => 0.03 20 | tolerance 'MIMCAP', 'C', :relative => 0.03 21 | tolerance 'TINCAP', 'C', :relative => 0.03 22 | tolerance 'PDIFFCAP', 'C', :relative => 0.03 23 | tolerance 'NDIFFCAP', 'C', :relative => 0.03 24 | netlist.combine_devices 25 | schematic.combine_devices 26 | end 27 | -------------------------------------------------------------------------------- /Technology/tech/macros/Documents/PDK reference manual.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | ICPS2023_5 PDK Reference Manual 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | ruby 17 | 18 | module MyMacro 19 | home = ENV['USERPROFILE'] || ENV['HOME'] 20 | klayout = '.klayout' 21 | ampasand = '&' 22 | case RbConfig::CONFIG['host_os'] 23 | when /mswin|mingw|cygwin/ 24 | cmd = "start " 25 | klayout = 'KLayout' 26 | ampasand = '' 27 | when /darwin/ 28 | cmd = "open " 29 | when /linux|bsd/ 30 | cmd = "xdg-open " 31 | else raise "No OS detected" 32 | end 33 | 34 | b = system cmd + "file:///#{home}/#{klayout}/salt/ICPS2023_5/Technology/doc/PDK_reference_manual.pdf" + ampasand 35 | 36 | end 37 | 38 | 39 | -------------------------------------------------------------------------------- /Technology/tech/macros/convert library cells.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | false 14 | 15 | 16 | ruby 17 | 18 | module MyMacro 19 | include MinedaCommon 20 | go = ConvertPCells.new 'ICPS2023_5' 21 | go.do_convert_library_cells({ 22 | layer_map: $layer_map, # = 'c:/Users/seijirom/Klayout/salt/ICPS2023_5/Technology/tech/OR_to_ICPS.txt', 23 | routing_scale_factor: $rsf || 1, pcell_scale_factor: $psf || 1, 24 | path: {'ML1' => {path_width_scale: $ml1_pws, path_width_min: $ml1_pwm, path_width_max: $ml1_pwx}, 25 | 'TIN' => {path_width_scale: $tin_pws, path_width_min: $tin_pwm, path_width_max: $tin_pwx}}, 26 | force_defaults: [:dg, :use_nwell, :with_nsubcont, :with_psubcont] 27 | }) 28 | end 29 | 30 | -------------------------------------------------------------------------------- /Technology/tech/macros/Documents/minimall Fab SOI CMOS PDK document.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | minimal Fab SOI CMOS PDK document 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | ruby 17 | 18 | module MyMacro 19 | home = ENV['USERPROFILE'] || ENV['HOME'] 20 | klayout = '.klayout' 21 | ampasand = '&' 22 | case RbConfig::CONFIG['host_os'] 23 | when /mswin|mingw|cygwin/ 24 | cmd = "start " 25 | klayout = 'KLayout' 26 | ampasand = '' 27 | when /darwin/ 28 | cmd = "open " 29 | when /linux|bsd/ 30 | cmd = "xdg-open " 31 | else raise "No OS detected" 32 | end 33 | 34 | b = system cmd + "file:///#{home}/#{klayout}/salt/ICPS2023_5/Technology/doc/PDK_minimalFabSOICMOS.pdf" + ampasand 35 | 36 | end 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- /Basic/doc/readme.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |

Your new Package

5 | 6 |

7 | Your new package is there! You can edit the package properties in the package manager. 8 | Use the edit button in the upper right corner of the package details panel to 9 | open the package editor. 10 |

11 | 12 |

13 | Here is what you should do: 14 |

15 | 16 | 21 | 22 |

23 | Of course, the most interesting thing is how to add, edit and develop libraries within 24 | your library package. When the package was initialized, a "libraries" folder with a single 25 | sample library has been created. 26 | In the package details you will find the local path to your package and the library 27 | layout file under "Installation". 28 | You can use any versioning system to manage your files there. 29 |

30 | 31 |

32 | Once you have finished your package, don't forget to specify the package version 33 | so users of you package will be informed of updates. Finally you can publish the 34 | package files to a place of your choice and submit the download URL to the 35 | Salt Mine server. 36 |

37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /Technology/tech/drc/area_cut.lydrc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | drc 6 | 7 | 8 | 9 | false 10 | false 11 | 12 | false 13 | drc_scripts 14 | tools_menu.drc.end 15 | dsl 16 | drc-dsl-xml 17 | target(source.path.sub(/\.(gds|GDS)/,"_converted\.\\1")) 18 | diff = input(3, 0) 19 | tin = input(5, 0) 20 | cnt = input(7, 0) 21 | ml1 = input(8, 0) 22 | via1 = input(9, 0) 23 | ml2 = input(10, 0) 24 | text = input(13, 0) 25 | frame = input(14, 0) 26 | res = input(15, 0) 27 | cap = input(16, 0) 28 | dio = input(17, 0) 29 | parea = input(18, 0) 30 | narea = input(19, 0) 31 | pad = input(20, 0) 32 | 33 | new_parea = parea - tin.sized(-2.um) 34 | new_narea = narea - tin.sized(-2.um) 35 | 36 | diff.output(3, 0) 37 | tin.output(5, 0) 38 | cnt.output(7, 0) 39 | ml1.output(8, 0) 40 | via1.output(9, 0) 41 | ml2.output(10, 0) 42 | frame.output(14, 0) 43 | res.output(15, 0) 44 | cap.output(16, 0) 45 | dio.output(17, 0) 46 | new_parea.output(18, 0) 47 | new_narea.output(19, 0) 48 | pad.output(20, 0) 49 | 50 | puts source.path.sub('.gds', '_converted.gds') + ' created' 51 | 52 | -------------------------------------------------------------------------------- /Technology/tech/macros/get_reference.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | Get reference for ICPS2023_5 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | ruby 17 | 18 | # get_reference v0.2, July 24 2023 copy right Seijiro Moriyama (Anagix Corp.) 19 | module MyMacro 20 | include RBA 21 | #include MinedaLVSpreprop 22 | 23 | MinedaLVS.new.lvs_go 'ICPS2023_5', { 24 | device: {NMOS: 'NCH', PMOS: 'PCH', 25 | MIMCAP: 'CAP', TINCAP: 'CAP', 26 | PDIFFCAP: 'CAP', NDIFFCAP: 'CAP', 27 | NRES: 'RES', PRES: 'RES', 28 | R_SOI: 'RES'}, 29 | tolerance: {RES: {R: {relative: 0.03}}, 30 | NRES: {R: {relative: 0.03}}, 31 | PRES: {R: {relative: 0.03}}, 32 | R_SOI: {R: {relative: 0.03}}, 33 | MIMCAP: {C: {relative: 0.03}}, 34 | TINCAP: {C: {relative: 0.03}}, 35 | PDIFFCAP: {C: {relative: 0.03}}, 36 | NDIFFCAP: {C: {relative: 0.03}}}, 37 | flatten_circuit: ['Nch*', 'Pch*'] 38 | } 39 | end 40 | 41 | 42 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_min.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE -144 -16 -176 -16 4 | WIRE -48 -16 -144 -16 5 | WIRE -16 -16 -48 -16 6 | WIRE 64 -16 -16 -16 7 | WIRE -176 16 -176 -16 8 | WIRE -48 16 -48 -16 9 | WIRE -240 64 -288 64 10 | WIRE -144 64 -144 -16 11 | WIRE -144 64 -176 64 12 | WIRE -16 64 -16 -16 13 | WIRE -16 64 -48 64 14 | WIRE -176 144 -176 112 15 | WIRE -48 144 -48 112 16 | WIRE -48 144 -176 144 17 | WIRE 80 144 -48 144 18 | WIRE -112 160 -112 64 19 | WIRE -112 160 -256 160 20 | WIRE -176 176 -176 144 21 | WIRE -256 224 -256 160 22 | WIRE -256 224 -368 224 23 | WIRE -240 224 -256 224 24 | WIRE -144 224 -176 224 25 | WIRE -176 304 -176 272 26 | WIRE -288 352 -288 64 27 | WIRE -288 352 -368 352 28 | WIRE -240 352 -288 352 29 | WIRE -144 352 -144 224 30 | WIRE -144 352 -176 352 31 | WIRE -176 416 -176 400 32 | WIRE -144 416 -144 352 33 | WIRE -144 416 -176 416 34 | WIRE -176 448 -176 416 35 | FLAG -368 224 A 36 | IOPIN -368 224 In 37 | FLAG -368 352 B 38 | IOPIN -368 352 In 39 | FLAG 80 144 Y 40 | IOPIN 80 144 Out 41 | FLAG 64 -16 VDD 42 | IOPIN 64 -16 In 43 | FLAG -176 448 VSS 44 | IOPIN -176 448 In 45 | SYMBOL MinedaLIB\\PMOS_MIN -240 64 R0 46 | SYMATTR InstName M1 47 | SYMATTR Value2 l=10.0U w=40.0U 48 | SYMBOL MinedaLIB\\PMOS_MIN -112 64 R0 49 | SYMATTR InstName M2 50 | SYMATTR Value2 l=10.0U w=40.0U 51 | SYMBOL MinedaLIB\\NMOS_MIN -240 224 R0 52 | SYMATTR InstName M3 53 | SYMATTR Value2 l=10.0U w=10.0U 54 | SYMBOL MinedaLIB\\NMOS_MIN -240 352 R0 55 | SYMATTR InstName M4 56 | SYMATTR Value2 l=10.0U w=10.0U 57 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_min_tb.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 3 4 | Active Pane: 1 5 | { 6 | traces: 1 {524290,0,"V(a)"} 7 | X: ('m',0,0,0.001,0.01) 8 | Y[0]: (' ',1,0,0.3,3) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,1,0,0.3,3) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 1 {524291,0,"V(b)"} 16 | X: ('m',0,0,0.001,0.01) 17 | Y[0]: (' ',1,0,0.3,3) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,1,0,0.3,3) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | }, 23 | { 24 | traces: 1 {524292,0,"V(out)"} 25 | X: ('m',0,0,0.001,0.01) 26 | Y[0]: (' ',1,-0.3,0.3,3.3) 27 | Y[1]: ('_',0,1e+308,0,-1e+308) 28 | Volts: (' ',0,0,1,-0.3,0.3,3.3) 29 | Log: 0 0 0 30 | GridStyle: 1 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_min_and_floating_devices.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 708 3 | WIRE -144 -16 -176 -16 4 | WIRE -48 -16 -144 -16 5 | WIRE -16 -16 -48 -16 6 | WIRE 64 -16 -16 -16 7 | WIRE -176 16 -176 -16 8 | WIRE -48 16 -48 -16 9 | WIRE -240 64 -288 64 10 | WIRE -144 64 -144 -16 11 | WIRE -144 64 -176 64 12 | WIRE -16 64 -16 -16 13 | WIRE -16 64 -48 64 14 | WIRE -176 144 -176 112 15 | WIRE -48 144 -48 112 16 | WIRE -48 144 -176 144 17 | WIRE 80 144 -48 144 18 | WIRE -112 160 -112 64 19 | WIRE -112 160 -256 160 20 | WIRE -176 176 -176 144 21 | WIRE -256 224 -256 160 22 | WIRE -256 224 -368 224 23 | WIRE -240 224 -256 224 24 | WIRE -144 224 -176 224 25 | WIRE -176 304 -176 272 26 | WIRE -288 352 -288 64 27 | WIRE -288 352 -368 352 28 | WIRE -240 352 -288 352 29 | WIRE -144 352 -144 224 30 | WIRE -144 352 -176 352 31 | WIRE -176 416 -176 400 32 | WIRE -144 416 -144 352 33 | WIRE -144 416 -176 416 34 | WIRE -176 448 -176 416 35 | FLAG -368 224 A 36 | IOPIN -368 224 In 37 | FLAG -368 352 B 38 | IOPIN -368 352 In 39 | FLAG 80 144 Y 40 | IOPIN 80 144 Out 41 | FLAG 64 -16 VDD 42 | IOPIN 64 -16 In 43 | FLAG -176 448 VSS 44 | IOPIN -176 448 In 45 | FLAG -144 416 0 46 | SYMBOL MinedaLIB\\PMOS_MIN -240 64 R0 47 | SYMATTR InstName M1 48 | SYMATTR Value2 l=10.0U w=40.0U 49 | SYMBOL MinedaLIB\\PMOS_MIN -112 64 R0 50 | SYMATTR InstName M2 51 | SYMATTR Value2 l=10.0U w=40.0U 52 | SYMBOL MinedaLIB\\NMOS_MIN -240 224 R0 53 | SYMATTR InstName M3 54 | SYMATTR Value2 l=10.0U w=10.0U 55 | SYMBOL MinedaLIB\\NMOS_MIN -240 352 R0 56 | SYMATTR InstName M4 57 | SYMATTR Value2 l=10.0U w=10.0U 58 | SYMBOL floating_devices -32 208 R0 59 | SYMATTR InstName X1 60 | TEXT -442 556 Left 2 !.tran 1m 61 | TEXT -440 592 Left 2 !.include %HOMEPATH%\\KLayout\\salt\\ICPS2023_5\\Technology\\tech\\models\\SOI_CMOS 62 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/lvs_work/nand_chip.net.txt: -------------------------------------------------------------------------------- 1 | * C:\Users\seiji\KLayout\salt\ICPS2023_5\Samples\Semicon2023\NAND\nand_chip.asc 2 | XX1 NC_01 NC_02 N001 0 NC_03 nand_min 3 | M1 NC_04 NC_05 NC_06 NC_07 nch l=10.0U w=10.0U 4 | M2 NC_08 NC_09 NC_10 NC_11 nch l=10.0U w=10.0U 5 | M3 NC_12 NC_13 NC_14 NC_15 nch l=10.0U w=10.0U 6 | M4 NC_16 NC_17 NC_18 NC_19 nch l=10.0U w=10.0U 7 | M5 NC_20 NC_21 NC_22 NC_23 nch l=10.0U w=10.0U 8 | M6 NC_24 NC_25 NC_26 NC_27 nch l=10.0U w=10.0U 9 | M7 NC_28 NC_29 NC_30 NC_31 nch l=10.0U w=10.0U 10 | M8 NC_32 NC_33 NC_34 NC_35 nch l=10.0U w=10.0U 11 | M9 NC_36 NC_37 NC_38 NC_39 nch l=10.0U w=10.0U 12 | M10 NC_40 NC_41 NC_42 NC_43 nch l=10.0U w=10.0U 13 | M11 NC_44 NC_45 NC_46 NC_47 nch l=10.0U w=10.0U 14 | M12 NC_48 NC_49 NC_50 NC_51 nch l=10.0U w=10.0U 15 | M14 NC_52 NC_53 NC_54 NC_55 pch l=10u w=40u 16 | M15 NC_56 NC_57 NC_58 NC_59 pch l=10u w=40u 17 | M16 NC_60 NC_61 NC_62 NC_63 pch l=10u w=40u 18 | M17 NC_64 NC_65 NC_66 NC_67 pch l=10u w=40u 19 | M18 NC_68 NC_69 NC_70 NC_71 pch l=10u w=40u 20 | M19 NC_72 NC_73 NC_74 NC_75 pch l=10u w=40u 21 | M20 NC_76 NC_77 NC_78 NC_79 pch l=10u w=40u 22 | M21 NC_80 NC_81 NC_82 NC_83 pch l=10u w=40u 23 | M22 NC_84 NC_85 NC_86 NC_87 pch l=10u w=40u 24 | M23 NC_88 NC_89 NC_90 NC_91 pch l=10u w=40u 25 | M24 NC_92 NC_93 NC_94 NC_95 pch l=10u w=40u 26 | M25 NC_96 NC_97 NC_98 NC_99 pch l=10u w=40u 27 | M13 NC_100 NC_101 NC_102 NC_103 nch l=10.0U w=10.0U 28 | M26 NC_104 NC_105 NC_106 NC_107 nch l=10.0U w=10.0U 29 | M27 NC_108 NC_109 NC_110 NC_111 pch l=10u w=40u 30 | M28 NC_112 NC_113 NC_114 NC_115 pch l=10u w=40u 31 | 32 | * block symbol definitions 33 | .subckt nand_min A B VDD VSS Y 34 | M1 Y B VDD VDD pch l=10.0U w=40.0U 35 | M2 Y A VDD VDD pch l=10.0U w=40.0U 36 | M3 Y A N001 VSS nch l=10.0U w=10.0U 37 | M4 N001 B VSS VSS nch l=10.0U w=10.0U 38 | .ends nand_min 39 | 40 | .model NMOS NMOS 41 | .model PMOS PMOS 42 | .lib C:\Users\seiji\AppData\Local\LTspice\lib\cmp\standard.mos 43 | .backanno 44 | .end 45 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/lvs_work/nand_sample_reference.cir.txt: -------------------------------------------------------------------------------- 1 | ** C:\USERS\SEIJI\KLAYOUT\SALT\ICPS2023_5\SAMPLES\SEMICON2023\NAND\NAND_CHIP.ASC 2 | XX1 NC_01 NC_02 N001 0 NC_03 NAND_MIN 3 | M1 NC_04 NC_05 NC_06 NC_07 NCH L=10.0U W=10.0U 4 | M2 NC_08 NC_09 NC_10 NC_11 NCH L=10.0U W=10.0U 5 | M3 NC_12 NC_13 NC_14 NC_15 NCH L=10.0U W=10.0U 6 | M4 NC_16 NC_17 NC_18 NC_19 NCH L=10.0U W=10.0U 7 | M5 NC_20 NC_21 NC_22 NC_23 NCH L=10.0U W=10.0U 8 | M6 NC_24 NC_25 NC_26 NC_27 NCH L=10.0U W=10.0U 9 | M7 NC_28 NC_29 NC_30 NC_31 NCH L=10.0U W=10.0U 10 | M8 NC_32 NC_33 NC_34 NC_35 NCH L=10.0U W=10.0U 11 | M9 NC_36 NC_37 NC_38 NC_39 NCH L=10.0U W=10.0U 12 | M10 NC_40 NC_41 NC_42 NC_43 NCH L=10.0U W=10.0U 13 | M11 NC_44 NC_45 NC_46 NC_47 NCH L=10.0U W=10.0U 14 | M12 NC_48 NC_49 NC_50 NC_51 NCH L=10.0U W=10.0U 15 | M14 NC_52 NC_53 NC_54 NC_55 PCH L=10U W=40U 16 | M15 NC_56 NC_57 NC_58 NC_59 PCH L=10U W=40U 17 | M16 NC_60 NC_61 NC_62 NC_63 PCH L=10U W=40U 18 | M17 NC_64 NC_65 NC_66 NC_67 PCH L=10U W=40U 19 | M18 NC_68 NC_69 NC_70 NC_71 PCH L=10U W=40U 20 | M19 NC_72 NC_73 NC_74 NC_75 PCH L=10U W=40U 21 | M20 NC_76 NC_77 NC_78 NC_79 PCH L=10U W=40U 22 | M21 NC_80 NC_81 NC_82 NC_83 PCH L=10U W=40U 23 | M22 NC_84 NC_85 NC_86 NC_87 PCH L=10U W=40U 24 | M23 NC_88 NC_89 NC_90 NC_91 PCH L=10U W=40U 25 | M24 NC_92 NC_93 NC_94 NC_95 PCH L=10U W=40U 26 | M25 NC_96 NC_97 NC_98 NC_99 PCH L=10U W=40U 27 | M13 NC_100 NC_101 NC_102 NC_103 NCH L=10.0U W=10.0U 28 | M26 NC_104 NC_105 NC_106 NC_107 NCH L=10.0U W=10.0U 29 | M27 NC_108 NC_109 NC_110 NC_111 PCH L=10U W=40U 30 | M28 NC_112 NC_113 NC_114 NC_115 PCH L=10U W=40U 31 | * 32 | ** BLOCK SYMBOL DEFINITIONS 33 | .SUBCKT NAND_MIN A B VDD VSS Y 34 | M1 Y B VDD VDD PCH L=10.0U W=40.0U 35 | M2 Y A VDD VDD PCH L=10.0U W=40.0U 36 | M3 Y A N001 VSS NCH L=10.0U W=10.0U 37 | M4 N001 B VSS VSS NCH L=10.0U W=10.0U 38 | .ENDS NAND_MIN 39 | * 40 | *.MODEL NMOS NMOS 41 | *.MODEL PMOS PMOS 42 | *.LIB C:\USERS\SEIJI\APPDATA\LOCAL\LTSPICE\LIB\CMP\STANDARD.MOS 43 | *.BACKANNO 44 | *.END 45 | .GLOBAL 0 46 | .END 47 | -------------------------------------------------------------------------------- /Technology/tech/macros/SOI_TEG_to_Mineda2022_6.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | false 14 | 15 | 16 | ruby 17 | 18 | module MyMacro 19 | 20 | include RBA 21 | 22 | app = Application.instance 23 | mw = app.main_window 24 | unless lv = mw.current_view 25 | raise "Shape Statistics: No view selected" 26 | end 27 | cell = lv.active_cellview.cell 28 | layout = cell.layout 29 | 30 | parea_src = layout.layer(2, 0) 31 | narea_src = layout.layer(3, 0) 32 | diff_src = layout.layer(4, 0) 33 | cnt_src = layout.layer(6, 0) 34 | ml1_src = layout.layer(7, 0) 35 | via1_src = layout.layer(8, 0) 36 | ml2_src = layout.layer(9, 0) 37 | pad_src = layout.layer(10, 0) 38 | #frame_src = layout.layer(14, 0) 39 | 40 | unless layout.layer_indices.include? 18 41 | puts 'conversion start' 42 | # YSS source layout definitions 43 | 44 | # OpenRule destination layout definitions 45 | parea_dst = layout.layer(18, 0) 46 | layout.move_layer(parea_src, parea_dst) # 2 -> 18 47 | narea_dst = layout.layer(19, 0) 48 | layout.move_layer(narea_src, narea_dst) # 3 -> 19 49 | diff_dst = layout.layer(3, 0) 50 | layout.move_layer(diff_src, diff_dst) # 4 -> 3 51 | 52 | pad_dst = layout.layer(50, 0) 53 | layout.move_layer(pad_src, pad_dst) # 10 -> 50 54 | ml2_dst= layout.layer(10, 0) 55 | layout.move_layer(ml2_src, ml2_dst) # 9 -> 10 56 | via1_dst = layout.layer(9, 0) 57 | layout.move_layer(via1_src, via1_dst) # 8 -> 9 58 | ml1_dst = layout.layer(8,0) 59 | layout.move_layer(ml1_src, ml1_dst) # 7 -> 8 60 | cnt_dst = layout.layer(7, 0) 61 | layout.move_layer(cnt_src, cnt_dst) # 6 -> 7 62 | 63 | 64 | #frame_dst = layout.layer(14, 0) 65 | #layout.move_layer(frame_src, frame_dst) 66 | 67 | puts 'conversion end' 68 | else 69 | # derived layers 70 | end 71 | # text = input(13, 0) 72 | # res = input(15, 0) 73 | # cap = input(16, 0) 74 | # dio = input(17, 0) 75 | 76 | 77 | # lv.remove_unused_layers 78 | 79 | end 80 | 81 | 82 | 83 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ICPS2023_5 2 | 3 | PDK for minimal Fab LSI fabricaition at AIST ACPS supporting 1st metal only 4 | SOI CMOS process. Made public since Nov.1, 2023. 5 | 6 | Following contents are documented in Technology/doc/PDK_minimalFabSOICMOS.pdf 7 | 8 | - Documentation 9 | * Device/Process Explanation 10 | * Device Characteristics 11 | * Design Manual 12 | - Electrical Data 13 | * SPICE Model 14 | * PCELL 15 | * DRC/LVS Rule 16 | 17 | PDK_reference_manual.pdf (in Japanese) is available under Technology/doc. 18 | 19 | PDK User Manual is: 20 | https://www.dropbox.com/scl/fi/84uzdzux0urhsd05mfxmb/ICPS2023_5-PDK-Users-Manual-v1.05.paper?rlkey=04jeibh2hrzlrlx4x9h5ghp4s&dl=0 21 | 22 | https://www.dropbox.com/scl/fi/xpbs2515cgc8ptyq67hix/ICPS2023_5-PDKv1.05.paper?rlkey=twak2s8lfh915b38o76o038q5&dl=0 (日本語版 in Japanese) 23 | 24 | PDK installation is just git clone following two packages 25 | under \~/KLayout/salt (\~/.klayout/salt under Linux and MacOS). 26 | 1. https://github.com/mineda-support/AnagixLoader.git 27 | 2. https://github.com/mineda-support/ICPS2023_5.git 28 | 29 | Tutorial for Semicon 2023 Minimaf Fab design contest is available: 30 | https://github.com/mineda-support/Semicon2023-MinimalFab-Design-Contest 31 | 32 | Design contest reception period is until Nov. 30, 2023, but you can use 33 | the document as a tutorial for using the open source minimal fab PDK with open source EDA. 34 | 35 | Leo Moser-san has kindly written an excellent tutorial titled 'Design of a NAND gate using the ICPS PDK' on his blog page: 36 | 37 | https://mole99.uber.space/2024/NAND_tutorial/Design%20of%20a%20NAND%20gate%20using%20the%20ICPS%20PDK.html 38 | 39 | His interview with Matt Ven-san is also worth viewing: 40 | 41 | https://discordapp.com/channels/1107477879891181639/1162283404008640533/1207705636591374336 42 | 43 | \***************************************************************************
44 | \* Copyright 2023 minimalFab Promoting Organization
45 | \*
46 | \* Licensed under the Apache License, Version 2.0 (the "License");
47 | \* you may not use this file except in compliance with the License.
48 | \* You may obtain a copy of the License at
49 | \*
50 | \* http://www.apache.org/licenses/LICENSE-2.0
51 | \*
52 | \* Unless required by applicable law or agreed to in writing, software
53 | \* distributed under the License is distributed on an "AS IS" BASIS,
54 | \* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
55 | \* See the License for the specific language governing permissions and
56 | \* limitations under the License
57 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/floating_devices.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 900 1096 3 | FLAG -352 224 x 4 | IOPIN -352 224 In 5 | SYMBOL MinedaLIB\\NMOS_MIN -352 224 R0 6 | SYMATTR InstName M1 7 | SYMATTR Value2 l=10.0U w=10.0U 8 | SYMBOL MinedaLIB\\NMOS_MIN -240 224 R0 9 | SYMATTR InstName M2 10 | SYMATTR Value2 l=10.0U w=10.0U 11 | SYMBOL MinedaLIB\\NMOS_MIN -112 224 R0 12 | SYMATTR InstName M3 13 | SYMATTR Value2 l=10.0U w=10.0U 14 | SYMBOL MinedaLIB\\NMOS_MIN 0 224 R0 15 | SYMATTR InstName M4 16 | SYMATTR Value2 l=10.0U w=10.0U 17 | SYMBOL MinedaLIB\\NMOS_MIN -352 368 R0 18 | SYMATTR InstName M5 19 | SYMATTR Value2 l=10.0U w=10.0U 20 | SYMBOL MinedaLIB\\NMOS_MIN -240 368 R0 21 | SYMATTR InstName M6 22 | SYMATTR Value2 l=10.0U w=10.0U 23 | SYMBOL MinedaLIB\\NMOS_MIN -112 368 R0 24 | SYMATTR InstName M7 25 | SYMATTR Value2 l=10.0U w=10.0U 26 | SYMBOL MinedaLIB\\NMOS_MIN 0 368 R0 27 | SYMATTR InstName M8 28 | SYMATTR Value2 l=10.0U w=10.0U 29 | SYMBOL MinedaLIB\\NMOS_MIN -352 512 R0 30 | SYMATTR InstName M9 31 | SYMATTR Value2 l=10.0U w=10.0U 32 | SYMBOL MinedaLIB\\NMOS_MIN -240 512 R0 33 | SYMATTR InstName M10 34 | SYMATTR Value2 l=10.0U w=10.0U 35 | SYMBOL MinedaLIB\\NMOS_MIN -112 512 R0 36 | SYMATTR InstName M11 37 | SYMATTR Value2 l=10.0U w=10.0U 38 | SYMBOL MinedaLIB\\NMOS_MIN 0 512 R0 39 | SYMATTR InstName M12 40 | SYMATTR Value2 l=10.0U w=10.0U 41 | SYMBOL MinedaLIB\\PMOS_MIN 432 224 R0 42 | SYMATTR InstName M14 43 | SYMATTR Value2 l=10u w=40u 44 | SYMBOL MinedaLIB\\PMOS_MIN 544 224 R0 45 | SYMATTR InstName M15 46 | SYMATTR Value2 l=10u w=40u 47 | SYMBOL MinedaLIB\\PMOS_MIN 656 224 R0 48 | SYMATTR InstName M16 49 | SYMATTR Value2 l=10u w=40u 50 | SYMBOL MinedaLIB\\PMOS_MIN 768 224 R0 51 | SYMATTR InstName M17 52 | SYMATTR Value2 l=10u w=40u 53 | SYMBOL MinedaLIB\\PMOS_MIN 432 368 R0 54 | SYMATTR InstName M18 55 | SYMATTR Value2 l=10u w=40u 56 | SYMBOL MinedaLIB\\PMOS_MIN 544 368 R0 57 | SYMATTR InstName M19 58 | SYMATTR Value2 l=10u w=40u 59 | SYMBOL MinedaLIB\\PMOS_MIN 656 368 R0 60 | SYMATTR InstName M20 61 | SYMATTR Value2 l=10u w=40u 62 | SYMBOL MinedaLIB\\PMOS_MIN 768 368 R0 63 | SYMATTR InstName M21 64 | SYMATTR Value2 l=10u w=40u 65 | SYMBOL MinedaLIB\\PMOS_MIN 432 496 R0 66 | SYMATTR InstName M22 67 | SYMATTR Value2 l=10u w=40u 68 | SYMBOL MinedaLIB\\PMOS_MIN 544 496 R0 69 | SYMATTR InstName M23 70 | SYMATTR Value2 l=10u w=40u 71 | SYMBOL MinedaLIB\\PMOS_MIN 656 496 R0 72 | SYMATTR InstName M24 73 | SYMATTR Value2 l=10u w=40u 74 | SYMBOL MinedaLIB\\PMOS_MIN 768 496 R0 75 | SYMATTR InstName M25 76 | SYMATTR Value2 l=10u w=40u 77 | SYMBOL MinedaLIB\\NMOS_MIN -352 672 R0 78 | SYMATTR InstName M13 79 | SYMATTR Value2 l=10.0U w=10.0U 80 | SYMBOL MinedaLIB\\NMOS_MIN -240 672 R0 81 | SYMATTR InstName M26 82 | SYMATTR Value2 l=10.0U w=10.0U 83 | SYMBOL MinedaLIB\\PMOS_MIN 432 640 R0 84 | SYMATTR InstName M27 85 | SYMATTR Value2 l=10u w=40u 86 | SYMBOL MinedaLIB\\PMOS_MIN 544 640 R0 87 | SYMATTR InstName M28 88 | SYMATTR Value2 l=10u w=40u 89 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_chip.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 900 1096 3 | WIRE 320 80 -96 80 4 | WIRE 496 80 320 80 5 | WIRE 320 176 320 80 6 | WIRE 336 320 336 240 7 | FLAG 336 320 0 8 | SYMBOL nand_min 336 256 R0 9 | SYMATTR InstName X1 10 | SYMBOL MinedaLIB\\NMOS_MIN -352 224 R0 11 | SYMATTR InstName M1 12 | SYMATTR Value2 l=10.0U w=10.0U 13 | SYMBOL MinedaLIB\\NMOS_MIN -240 224 R0 14 | SYMATTR InstName M2 15 | SYMATTR Value2 l=10.0U w=10.0U 16 | SYMBOL MinedaLIB\\NMOS_MIN -112 224 R0 17 | SYMATTR InstName M3 18 | SYMATTR Value2 l=10.0U w=10.0U 19 | SYMBOL MinedaLIB\\NMOS_MIN 0 224 R0 20 | SYMATTR InstName M4 21 | SYMATTR Value2 l=10.0U w=10.0U 22 | SYMBOL MinedaLIB\\NMOS_MIN -352 368 R0 23 | SYMATTR InstName M5 24 | SYMATTR Value2 l=10.0U w=10.0U 25 | SYMBOL MinedaLIB\\NMOS_MIN -240 368 R0 26 | SYMATTR InstName M6 27 | SYMATTR Value2 l=10.0U w=10.0U 28 | SYMBOL MinedaLIB\\NMOS_MIN -112 368 R0 29 | SYMATTR InstName M7 30 | SYMATTR Value2 l=10.0U w=10.0U 31 | SYMBOL MinedaLIB\\NMOS_MIN 0 368 R0 32 | SYMATTR InstName M8 33 | SYMATTR Value2 l=10.0U w=10.0U 34 | SYMBOL MinedaLIB\\NMOS_MIN -352 512 R0 35 | SYMATTR InstName M9 36 | SYMATTR Value2 l=10.0U w=10.0U 37 | SYMBOL MinedaLIB\\NMOS_MIN -240 512 R0 38 | SYMATTR InstName M10 39 | SYMATTR Value2 l=10.0U w=10.0U 40 | SYMBOL MinedaLIB\\NMOS_MIN -112 512 R0 41 | SYMATTR InstName M11 42 | SYMATTR Value2 l=10.0U w=10.0U 43 | SYMBOL MinedaLIB\\NMOS_MIN 0 512 R0 44 | SYMATTR InstName M12 45 | SYMATTR Value2 l=10.0U w=10.0U 46 | SYMBOL MinedaLIB\\PMOS_MIN 432 224 R0 47 | SYMATTR InstName M14 48 | SYMATTR Value2 l=10u w=40u 49 | SYMBOL MinedaLIB\\PMOS_MIN 544 224 R0 50 | SYMATTR InstName M15 51 | SYMATTR Value2 l=10u w=40u 52 | SYMBOL MinedaLIB\\PMOS_MIN 656 224 R0 53 | SYMATTR InstName M16 54 | SYMATTR Value2 l=10u w=40u 55 | SYMBOL MinedaLIB\\PMOS_MIN 768 224 R0 56 | SYMATTR InstName M17 57 | SYMATTR Value2 l=10u w=40u 58 | SYMBOL MinedaLIB\\PMOS_MIN 432 368 R0 59 | SYMATTR InstName M18 60 | SYMATTR Value2 l=10u w=40u 61 | SYMBOL MinedaLIB\\PMOS_MIN 544 368 R0 62 | SYMATTR InstName M19 63 | SYMATTR Value2 l=10u w=40u 64 | SYMBOL MinedaLIB\\PMOS_MIN 656 368 R0 65 | SYMATTR InstName M20 66 | SYMATTR Value2 l=10u w=40u 67 | SYMBOL MinedaLIB\\PMOS_MIN 768 368 R0 68 | SYMATTR InstName M21 69 | SYMATTR Value2 l=10u w=40u 70 | SYMBOL MinedaLIB\\PMOS_MIN 432 496 R0 71 | SYMATTR InstName M22 72 | SYMATTR Value2 l=10u w=40u 73 | SYMBOL MinedaLIB\\PMOS_MIN 544 496 R0 74 | SYMATTR InstName M23 75 | SYMATTR Value2 l=10u w=40u 76 | SYMBOL MinedaLIB\\PMOS_MIN 656 496 R0 77 | SYMATTR InstName M24 78 | SYMATTR Value2 l=10u w=40u 79 | SYMBOL MinedaLIB\\PMOS_MIN 768 496 R0 80 | SYMATTR InstName M25 81 | SYMATTR Value2 l=10u w=40u 82 | SYMBOL MinedaLIB\\NMOS_MIN -352 656 R0 83 | SYMATTR InstName M13 84 | SYMATTR Value2 l=10.0U w=10.0U 85 | SYMBOL MinedaLIB\\NMOS_MIN -240 656 R0 86 | SYMATTR InstName M26 87 | SYMATTR Value2 l=10.0U w=10.0U 88 | SYMBOL MinedaLIB\\PMOS_MIN 432 640 R0 89 | SYMATTR InstName M27 90 | SYMATTR Value2 l=10u w=40u 91 | SYMBOL MinedaLIB\\PMOS_MIN 544 640 R0 92 | SYMATTR InstName M28 93 | SYMATTR Value2 l=10u w=40u 94 | -------------------------------------------------------------------------------- /Technology/tech/macros/XsectionUI.lym: -------------------------------------------------------------------------------- 1 | 2 | 3 | Display Xsection for Mineda2021_2 4 | 5 | 6 | 7 | 8 | 9 | false 10 | false 11 | 12 | true 13 | 14 | 15 | ruby 16 | 17 | # XsectionUI for Mineda2021_2 v0.16 by S. Moriyama June 18th, 2021 18 | # v0.13 fixed DIFF-CUT by Chikau Takahashi June 7th, 2021 19 | module MyMacro 20 | include RBA 21 | $soi_check = nil 22 | eng = DRC::DRCEngine::new 23 | eng.instance_eval do 24 | soi = input(4,0) 25 | $soi_check = soi.area 26 | if $soi_check == 0 # for designers 27 | diff = input(3, 0) 28 | tin = input(5, 0).raw 29 | cap = input(16,0) 30 | parea = input(18, 0) 31 | narea = input(19, 0) 32 | # new_parea = parea - tin 33 | # new_narea = narea - tin 34 | new_parea = (parea & diff ).sized(2.0) - (tin - cap) 35 | new_narea = (narea & diff ).sized(2.0) - (tin - cap) 36 | tin_gate = tin.interacting(diff) - cap 37 | tin_rest = tin - tin_gate 38 | bb = (diff + tin_gate ).extents 39 | tin_gate_enlarged = tin_gate.sized(2.0.um) & bb 40 | (tin +tin_gate_enlarged).output(21, 0) # tin 41 | end 42 | end 43 | eng._finish(false) 44 | 45 | mw = Application.instance.main_window 46 | view_index = mw.current_view_index 47 | layout_view = mw.current_view 48 | 49 | load File.join(File.dirname(__FILE__), "../../../xsection/ruby/xsection.rb") 50 | include XS 51 | xs = XSectionScriptEnvironment.new 52 | xs_view_index = mw.views 53 | xs.run_script File.join(File.dirname(__FILE__), "../YSS-SOI-CMOS.xs") 54 | if $soi_check == 0 55 | mw.select_view view_index 56 | layout = mw.current_view.active_cellview.cell.layout 57 | # puts "layout=#{layout.inspect}" 58 | # layout_view.each_layer{|l| puts "ind=#{ind=l.layer_index}"} 59 | layout_view.each_layer{|l| 60 | ind = l.layer_index 61 | if ind > 0 && (info = layout.get_info(ind)) && [4,21].include?(info.layer) 62 | puts "@#{ind} info.layer=#{info.layer}" 63 | layout.delete_layer(ind) 64 | end 65 | } 66 | end 67 | if mw.views-1 >= xs_view_index 68 | xs_view_index.upto(mw.views-1){|xv_index| 69 | xv = mw.view(xv_index).cellview(0) 70 | top_cell = xv.layout.top_cell 71 | xs = xv.layout.create_cell 'xs' 72 | xs.insert CellInstArray.new top_cell.cell_index, ICplxTrans.new 73 | lv = mw.view(view_index) 74 | cv_created = lv.show_layout(xs.layout, true) 75 | layer_props_file = File.join(File.dirname(__FILE__), "../YSS-SOI-CMOS_Xsection.lyp") 76 | layout_view.load_layer_props layer_props_file, cv_created, false 77 | } 78 | mw.select_view view_index 79 | end 80 | end 81 | 82 | 83 | 84 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_min_tb.log: -------------------------------------------------------------------------------- 1 | Circuit: * C:\Users\seijirom\KLayout\salt\ICPS2023_5\Samples\Semicon2023\NAND\nand_min_tb.asc 2 | 3 | Error on line 1226 : .model nch nmos tnom = 25 level = 8 paramchk = 1 mobmod = 1 capmod = 3 fnoimod = 1 soimod = 3 tox = 1.5e-08 xj = 1.5e-007 nch = 1.7e+017 vth0 = 0.20809 k1 = 0.5 k2 = 0 k3 = 80 k3b = 0 w0 = 2.5e-006 nlx = 1.74e-007 vbm = -3.0 dvt0 = 2.2 dvt1 = 0.53 dvt2 = -0.032 dvt0w = 0 dvt1w = 5.3e+006 dvt2w = -0.032 u0 = 670 ua = 2.25e-09 ub = 5.87e-19 uc = -4.65e-11 vsat = 800755.2814 a0 = 1.1164 ags = 0.2656 b0 = 0 b1 = 0 keta = -0.047 a1 = 0 a2 = 0.20782 rdsw = 0 prwb = 0 prwg = 58.7371 wr = 1 wint = 0 lint = 0 dwg = 0 dwb = 0 voff = -0.17284 nfactor = 0.99099 eta0 = 0.08 etab = -0.07 dsub = 0.56 cit = 0 cdsc = 0.00021654 cdscb = 0 cdscd = 0.38995 pclm = 2.9694 pdiblc1 = 0.39 pdiblc2 = 0.0021218 pdiblcb = 0 drout = 0.56 pvag = 0 delta = 0.045152 ngate = 0 alpha0 = 0 beta0 = 30 rsh = 0 xpart = 1 cgso = 5.3e-9 cgdo = 5.3e-9 cgsl = 0 cgdl = 0 cjswg = 5.0e-010 mjswg = 0.33 pbswg = 1 ckappa = 0.6 cf = 0 clc = 1.0e-007 cle = 0.6 dlc = 0 dwc = 0 noff = 1 acde = 1 moin = 15 ute = -1.5 kt1 = -0.11 kt1l = 0 kt2 = 0.022 ua1 = 4.31e-009 ub1 = -7.61e-018 uc1 = -5.6e-011 at = 3.3e+004 prt = 0 tcjswg = 0 af = 1 ef = 1 kf = 0 4 | * Unrecognized parameter "fnoimod" -- ignored 5 | Error on line 1226 : .model nch nmos tnom = 25 level = 8 paramchk = 1 mobmod = 1 capmod = 3 fnoimod = 1 soimod = 3 tox = 1.5e-08 xj = 1.5e-007 nch = 1.7e+017 vth0 = 0.20809 k1 = 0.5 k2 = 0 k3 = 80 k3b = 0 w0 = 2.5e-006 nlx = 1.74e-007 vbm = -3.0 dvt0 = 2.2 dvt1 = 0.53 dvt2 = -0.032 dvt0w = 0 dvt1w = 5.3e+006 dvt2w = -0.032 u0 = 670 ua = 2.25e-09 ub = 5.87e-19 uc = -4.65e-11 vsat = 800755.2814 a0 = 1.1164 ags = 0.2656 b0 = 0 b1 = 0 keta = -0.047 a1 = 0 a2 = 0.20782 rdsw = 0 prwb = 0 prwg = 58.7371 wr = 1 wint = 0 lint = 0 dwg = 0 dwb = 0 voff = -0.17284 nfactor = 0.99099 eta0 = 0.08 etab = -0.07 dsub = 0.56 cit = 0 cdsc = 0.00021654 cdscb = 0 cdscd = 0.38995 pclm = 2.9694 pdiblc1 = 0.39 pdiblc2 = 0.0021218 pdiblcb = 0 drout = 0.56 pvag = 0 delta = 0.045152 ngate = 0 alpha0 = 0 beta0 = 30 rsh = 0 xpart = 1 cgso = 5.3e-9 cgdo = 5.3e-9 cgsl = 0 cgdl = 0 cjswg = 5.0e-010 mjswg = 0.33 pbswg = 1 ckappa = 0.6 cf = 0 clc = 1.0e-007 cle = 0.6 dlc = 0 dwc = 0 noff = 1 acde = 1 moin = 15 ute = -1.5 kt1 = -0.11 kt1l = 0 kt2 = 0.022 ua1 = 4.31e-009 ub1 = -7.61e-018 uc1 = -5.6e-011 at = 3.3e+004 prt = 0 tcjswg = 0 af = 1 ef = 1 kf = 0 6 | * Unrecognized parameter "soimod" -- ignored 7 | Limiting rise time of source v1 to 0.0002 8 | Limiting fall time of source v1 to 0.0002 9 | Limiting rise time of source v2 to 0.0001 10 | Limiting fall time of source v2 to 0.0001 11 | Warning: Pd = 0 is less than W. 12 | Warning: Ps = 0 is less than W. 13 | Warning: Pd = 0 is less than W. 14 | Warning: Ps = 0 is less than W. 15 | Direct Newton iteration for .op point succeeded. 16 | 17 | Date: Fri Nov 3 09:46:14 2023 18 | Total elapsed time: 0.271 seconds. 19 | 20 | tnom = 27 21 | temp = 27 22 | method = modified trap 23 | totiter = 4389 24 | traniter = 4364 25 | tranpoints = 1813 26 | accept = 1565 27 | rejected = 248 28 | matrix size = 8 29 | fillins = 0 30 | solver = Normal 31 | Avg thread counts: 1.1/1.2/1.2/1.1 32 | Matrix Compiler1: 18 opcodes 0.4/[0.4]/0.5 33 | Matrix Compiler2: 636 bytes object code size 0.4/0.5/[0.4] 34 | 35 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_sample_output.cir: -------------------------------------------------------------------------------- 1 | * Created by KLayout 2 | 3 | * cell nand 4 | * pin B 5 | * pin A 6 | * pin Z 7 | * pin VSS 8 | * pin VDD 9 | .SUBCKT nand 1 3 4 5 6 10 | * net 1 B 11 | * net 3 A 12 | * net 4 Z 13 | * net 5 VSS 14 | * net 6 VDD 15 | * device instance $1 r0 *1 1067,-222.5 NMOS 16 | M$1 43 47 45 43 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 17 | * device instance $2 r0 *1 1067,-382.5 NMOS 18 | M$2 44 48 46 44 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 19 | * device instance $3 r0 *1 907,-222.5 NMOS 20 | M$3 16 22 34 16 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 21 | * device instance $4 r0 *1 907,-382.5 NMOS 22 | M$4 19 37 13 19 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 23 | * device instance $5 r0 *1 1067,-862.5 NMOS 24 | M$5 49 53 51 49 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 25 | * device instance $6 r0 *1 1067,-1022.5 NMOS 26 | M$6 50 54 52 50 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 27 | * device instance $7 r0 *1 907,-862.5 NMOS 28 | M$7 17 23 35 17 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 29 | * device instance $8 r0 *1 907,-1022.5 NMOS 30 | M$8 20 38 14 20 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 31 | * device instance $9 r0 *1 427,-222.5 NMOS 32 | M$9 55 59 57 55 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 33 | * device instance $10 r0 *1 427,-382.5 NMOS 34 | M$10 56 60 58 56 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 35 | * device instance $11 r0 *1 267,-222.5 NMOS 36 | M$11 4 3 2 4 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 37 | * device instance $12 r0 *1 267,-382.5 NMOS 38 | M$12 4 1 5 4 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 39 | * device instance $13 r0 *1 427,-862.5 NMOS 40 | M$13 61 65 63 61 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 41 | * device instance $14 r0 *1 427,-1022.5 NMOS 42 | M$14 62 66 64 62 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 43 | * device instance $15 r0 *1 267,-862.5 NMOS 44 | M$15 18 24 36 18 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 45 | * device instance $16 r0 *1 267,-1022.5 NMOS 46 | M$16 21 39 15 21 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 47 | * device instance $17 r0 *1 1070,114 PMOS 48 | M$17 69 71 67 69 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 49 | * device instance $18 r0 *1 1070,-46 PMOS 50 | M$18 70 72 68 70 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 51 | * device instance $19 r0 *1 910,114 PMOS 52 | M$19 28 40 10 28 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 53 | * device instance $20 r0 *1 910,-46 PMOS 54 | M$20 31 25 7 31 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 55 | * device instance $21 r0 *1 1070,-526 PMOS 56 | M$21 75 77 73 75 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 57 | * device instance $22 r0 *1 1070,-686 PMOS 58 | M$22 76 78 74 76 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 59 | * device instance $23 r0 *1 910,-526 PMOS 60 | M$23 29 41 11 29 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 61 | * device instance $24 r0 *1 910,-686 PMOS 62 | M$24 32 26 8 32 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 63 | * device instance $25 r0 *1 430,114 PMOS 64 | M$25 81 83 79 81 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 65 | * device instance $26 r0 *1 430,-46 PMOS 66 | M$26 82 84 80 82 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 67 | * device instance $27 r0 *1 270,114 PMOS 68 | M$27 2 1 6 2 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 69 | * device instance $28 r0 *1 270,-46 PMOS 70 | M$28 2 3 6 2 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 71 | * device instance $29 r0 *1 430,-526 PMOS 72 | M$29 87 89 85 87 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 73 | * device instance $30 r0 *1 430,-686 PMOS 74 | M$30 88 90 86 88 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 75 | * device instance $31 r0 *1 270,-526 PMOS 76 | M$31 30 42 12 30 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 77 | * device instance $32 r0 *1 270,-686 PMOS 78 | M$32 33 27 9 33 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 79 | .ENDS nand 80 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/lvs_work/nand_sample_output.cir.txt: -------------------------------------------------------------------------------- 1 | * Created by KLayout 2 | 3 | * cell nand 4 | * pin B 5 | * pin A 6 | * pin Z 7 | * pin VSS 8 | * pin VDD 9 | .SUBCKT nand 1 3 4 5 6 10 | * net 1 B 11 | * net 3 A 12 | * net 4 Z 13 | * net 5 VSS 14 | * net 6 VDD 15 | * device instance $1 r0 *1 1067,-222.5 NMOS 16 | M$1 43 47 45 43 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 17 | * device instance $2 r0 *1 1067,-382.5 NMOS 18 | M$2 44 48 46 44 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 19 | * device instance $3 r0 *1 907,-222.5 NMOS 20 | M$3 16 22 34 16 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 21 | * device instance $4 r0 *1 907,-382.5 NMOS 22 | M$4 19 37 13 19 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 23 | * device instance $5 r0 *1 1067,-862.5 NMOS 24 | M$5 49 53 51 49 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 25 | * device instance $6 r0 *1 1067,-1022.5 NMOS 26 | M$6 50 54 52 50 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 27 | * device instance $7 r0 *1 907,-862.5 NMOS 28 | M$7 17 23 35 17 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 29 | * device instance $8 r0 *1 907,-1022.5 NMOS 30 | M$8 20 38 14 20 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 31 | * device instance $9 r0 *1 427,-222.5 NMOS 32 | M$9 55 59 57 55 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 33 | * device instance $10 r0 *1 427,-382.5 NMOS 34 | M$10 56 60 58 56 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 35 | * device instance $11 r0 *1 267,-222.5 NMOS 36 | M$11 4 3 2 4 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 37 | * device instance $12 r0 *1 267,-382.5 NMOS 38 | M$12 4 1 5 4 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 39 | * device instance $13 r0 *1 427,-862.5 NMOS 40 | M$13 61 65 63 61 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 41 | * device instance $14 r0 *1 427,-1022.5 NMOS 42 | M$14 62 66 64 62 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 43 | * device instance $15 r0 *1 267,-862.5 NMOS 44 | M$15 18 24 36 18 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 45 | * device instance $16 r0 *1 267,-1022.5 NMOS 46 | M$16 21 39 15 21 NMOS L=10U W=10U AS=229P AD=229P PS=64U PD=64U 47 | * device instance $17 r0 *1 1070,114 PMOS 48 | M$17 69 71 67 69 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 49 | * device instance $18 r0 *1 1070,-46 PMOS 50 | M$18 70 72 68 70 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 51 | * device instance $19 r0 *1 910,114 PMOS 52 | M$19 28 40 10 28 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 53 | * device instance $20 r0 *1 910,-46 PMOS 54 | M$20 31 25 7 31 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 55 | * device instance $21 r0 *1 1070,-526 PMOS 56 | M$21 75 77 73 75 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 57 | * device instance $22 r0 *1 1070,-686 PMOS 58 | M$22 76 78 74 76 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 59 | * device instance $23 r0 *1 910,-526 PMOS 60 | M$23 29 41 11 29 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 61 | * device instance $24 r0 *1 910,-686 PMOS 62 | M$24 32 26 8 32 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 63 | * device instance $25 r0 *1 430,114 PMOS 64 | M$25 81 83 79 81 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 65 | * device instance $26 r0 *1 430,-46 PMOS 66 | M$26 82 84 80 82 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 67 | * device instance $27 r0 *1 270,114 PMOS 68 | M$27 2 1 6 2 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 69 | * device instance $28 r0 *1 270,-46 PMOS 70 | M$28 2 3 6 2 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 71 | * device instance $29 r0 *1 430,-526 PMOS 72 | M$29 87 89 85 87 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 73 | * device instance $30 r0 *1 430,-686 PMOS 74 | M$30 88 90 86 88 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 75 | * device instance $31 r0 *1 270,-526 PMOS 76 | M$31 30 42 12 30 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 77 | * device instance $32 r0 *1 270,-686 PMOS 78 | M$32 33 27 9 33 PMOS L=10U W=40U AS=760P AD=760P PS=118U PD=118U 79 | .ENDS nand 80 | -------------------------------------------------------------------------------- /Samples/Semicon2023/NAND/nand_sample_ba.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | ".TOP": 3 | M1: 4 | L: 10.0 5 | W: 10.0 6 | AS: 229.0 7 | AD: 229.0 8 | PS: 64.0 9 | PD: 64.0 10 | M2: 11 | L: 10.0 12 | W: 10.0 13 | AS: 229.0 14 | AD: 229.0 15 | PS: 64.0 16 | PD: 64.0 17 | M3: 18 | L: 10.0 19 | W: 10.0 20 | AS: 229.0 21 | AD: 229.0 22 | PS: 64.0 23 | PD: 64.0 24 | M4: 25 | L: 10.0 26 | W: 10.0 27 | AS: 229.0 28 | AD: 229.0 29 | PS: 64.0 30 | PD: 64.0 31 | M5: 32 | L: 10.0 33 | W: 10.0 34 | AS: 229.0 35 | AD: 229.0 36 | PS: 64.0 37 | PD: 64.0 38 | M6: 39 | L: 10.0 40 | W: 10.0 41 | AS: 229.0 42 | AD: 229.0 43 | PS: 64.0 44 | PD: 64.0 45 | M7: 46 | L: 10.0 47 | W: 10.0 48 | AS: 229.0 49 | AD: 229.0 50 | PS: 64.0 51 | PD: 64.0 52 | M8: 53 | L: 10.0 54 | W: 10.0 55 | AS: 229.0 56 | AD: 229.0 57 | PS: 64.0 58 | PD: 64.0 59 | M9: 60 | L: 10.0 61 | W: 10.0 62 | AS: 229.0 63 | AD: 229.0 64 | PS: 64.0 65 | PD: 64.0 66 | M10: 67 | L: 10.0 68 | W: 10.0 69 | AS: 229.0 70 | AD: 229.0 71 | PS: 64.0 72 | PD: 64.0 73 | M11: 74 | L: 10.0 75 | W: 10.0 76 | AS: 229.0 77 | AD: 229.0 78 | PS: 64.0 79 | PD: 64.0 80 | M12: 81 | L: 10.0 82 | W: 10.0 83 | AS: 229.0 84 | AD: 229.0 85 | PS: 64.0 86 | PD: 64.0 87 | M13: 88 | L: 10.0 89 | W: 10.0 90 | AS: 229.0 91 | AD: 229.0 92 | PS: 64.0 93 | PD: 64.0 94 | M26: 95 | L: 10.0 96 | W: 10.0 97 | AS: 229.0 98 | AD: 229.0 99 | PS: 64.0 100 | PD: 64.0 101 | X1: 102 | M3: 103 | L: 10.0 104 | W: 10.0 105 | AS: 229.0 106 | AD: 229.0 107 | PS: 64.0 108 | PD: 64.0 109 | M4: 110 | L: 10.0 111 | W: 10.0 112 | AS: 229.0 113 | AD: 229.0 114 | PS: 64.0 115 | PD: 64.0 116 | M1: 117 | L: 10.0 118 | W: 40.0 119 | AS: 760.0 120 | AD: 760.0 121 | PS: 118.0 122 | PD: 118.0 123 | M2: 124 | L: 10.0 125 | W: 40.0 126 | AS: 760.0 127 | AD: 760.0 128 | PS: 118.0 129 | PD: 118.0 130 | M14: 131 | L: 10.0 132 | W: 40.0 133 | AS: 760.0 134 | AD: 760.0 135 | PS: 118.0 136 | PD: 118.0 137 | M15: 138 | L: 10.0 139 | W: 40.0 140 | AS: 760.0 141 | AD: 760.0 142 | PS: 118.0 143 | PD: 118.0 144 | M16: 145 | L: 10.0 146 | W: 40.0 147 | AS: 760.0 148 | AD: 760.0 149 | PS: 118.0 150 | PD: 118.0 151 | M17: 152 | L: 10.0 153 | W: 40.0 154 | AS: 760.0 155 | AD: 760.0 156 | PS: 118.0 157 | PD: 118.0 158 | M18: 159 | L: 10.0 160 | W: 40.0 161 | AS: 760.0 162 | AD: 760.0 163 | PS: 118.0 164 | PD: 118.0 165 | M19: 166 | L: 10.0 167 | W: 40.0 168 | AS: 760.0 169 | AD: 760.0 170 | PS: 118.0 171 | PD: 118.0 172 | M20: 173 | L: 10.0 174 | W: 40.0 175 | AS: 760.0 176 | AD: 760.0 177 | PS: 118.0 178 | PD: 118.0 179 | M21: 180 | L: 10.0 181 | W: 40.0 182 | AS: 760.0 183 | AD: 760.0 184 | PS: 118.0 185 | PD: 118.0 186 | M22: 187 | L: 10.0 188 | W: 40.0 189 | AS: 760.0 190 | AD: 760.0 191 | PS: 118.0 192 | PD: 118.0 193 | M23: 194 | L: 10.0 195 | W: 40.0 196 | AS: 760.0 197 | AD: 760.0 198 | PS: 118.0 199 | PD: 118.0 200 | M24: 201 | L: 10.0 202 | W: 40.0 203 | AS: 760.0 204 | AD: 760.0 205 | PS: 118.0 206 | PD: 118.0 207 | M25: 208 | L: 10.0 209 | W: 40.0 210 | AS: 760.0 211 | AD: 760.0 212 | PS: 118.0 213 | PD: 118.0 214 | M27: 215 | L: 10.0 216 | W: 40.0 217 | AS: 760.0 218 | AD: 760.0 219 | PS: 118.0 220 | PD: 118.0 221 | M28: 222 | L: 10.0 223 | W: 40.0 224 | AS: 760.0 225 | AD: 760.0 226 | PS: 118.0 227 | PD: 118.0 228 | -------------------------------------------------------------------------------- /Technology/tech/drc/ICPS2023_5_to_SOI.lydrc: -------------------------------------------------------------------------------- 1 | 2 | 3 | ICPS2023_5 (SOI mixed) to SOI conversion 4 | 5 | drc 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | 15 | 16 | dsl 17 | drc-dsl-xml 18 | =begin 19 | * Copyright 2023 minimalFab Promoting Organization 20 | * 21 | * Licensed under the Apache License, Version 2.0 (the "License"); 22 | * you may not use this file except in compliance with the License. 23 | * You may obtain a copy of the License at 24 | * 25 | * http://www.apache.org/licenses/LICENSE-2.0 26 | * 27 | * Unless required by applicable law or agreed to in writing, software 28 | * distributed under the License is distributed on an "AS IS" BASIS, 29 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | * See the License for the specific language governing permissions and 31 | * limitations under the License 32 | =end 33 | target(source.path.sub(/\.(gds|GDS)/,"_converted\.\\1")) 34 | # 2021/6/6 initial version by Seijiro Moriyama 35 | # v0.9 added diode conversion by Swear Takahashi on July 12th, 2021 36 | # v0.91 convert cnt to g_cnt (L21) if inside TIN, and sd_cnt (L22) otherwise 37 | # v0.92 g_cnt tiny fix suggested by Swear Takahashi 38 | # v0.93 allowed to mix YSS SOI layers (w/o conversion) surrounded by NWell 39 | # v0.94 renamed diff_keep to soi_keep 40 | # v0.95 bug fix: keep all SOI layers 41 | # v0.97 TIN & PWell correction by Swear Takahashi on March 6th, 2022 42 | # v0.98 set deep mode to process hierarchically 43 | # v0.99 gate contact and s/d contact use same layer (6) 44 | 45 | deep 46 | dont_touch = input(63, 63) 47 | diff = input(3, 0).outside(dont_touch) 48 | tin = input(5, 0).outside(dont_touch).raw 49 | cnt = input(7, 0).outside(dont_touch) 50 | ml1 = input(8, 0) .outside(dont_touch) 51 | via1 = input(9, 0) .outside(dont_touch) 52 | ml2 = input(10, 0).outside(dont_touch) 53 | # text = input(13, 0) 54 | frame = input(14, 0).outside(dont_touch) 55 | res = input(15, 0).outside(dont_touch) 56 | cap = input(16, 0).outside(dont_touch) 57 | #cap = cap.sized(2.0) if cap.area > 0.0 58 | # cap = cap..outside(dont_touch) 59 | dio = input(17, 0).outside(dont_touch) 60 | parea = input(18, 0).outside(dont_touch) 61 | narea = input(19, 0).outside(dont_touch) 62 | pad = input(50, 0).outside(dont_touch) 63 | 64 | pwell1 = input(21,0) 65 | pwell = narea.interacting(tin).sized(2.0) + pwell1 66 | tin_t = input(5,1) 67 | 68 | dio2 = dio.sized(2.0) - (parea + narea) 69 | 70 | new_parea = (parea & diff ).sized(2.0) - (tin - cap + dio2) 71 | new_narea = (narea & diff ).sized(2.0) - (tin - cap + dio2) 72 | 73 | tin_gate = tin.interacting(diff) - tin.overlapping(cap) 74 | tin_rest = tin - tin_gate 75 | bb = (diff + tin_gate ).extents 76 | tin_gate_enlarged = tin_gate.sized(2.0.um) & bb 77 | 78 | bg_keep = input(0, 0).inside(dont_touch) 79 | parea_keep = input(2, 0).inside(dont_touch) 80 | narea_keep = input(3,0).inside(dont_touch) 81 | soi_keep = input(4, 0).inside(dont_touch) 82 | tin_keep = input(5, 0).inside(dont_touch) 83 | cnt_keep = input(6,0).inside(dont_touch) 84 | ml1_keep = input(7, 0).inside(dont_touch) 85 | via1_keep = input(8, 0).inside(dont_touch) 86 | ml2_keep = input(9, 0).inside(dont_touch) 87 | 88 | pad_keep = input(10, 0).inside(dont_touch) 89 | pwell_keep = input(13, 0).inside(dont_touch) 90 | g_cnt_keep = input(21, 0).inside(dont_touch) 91 | sd_cnt_keep = input(22, 0).inside(dont_touch) 92 | 93 | bg_keep.output(0, 0) 94 | (parea_keep+new_parea).output(2, 0) 95 | (narea_keep+new_narea).output(3, 0) 96 | (soi_keep+diff).output(4, 0) 97 | (tin_keep+tin +tin_gate_enlarged+ tin_t).output(5, 0) 98 | cnt_keep.output(6, 0) 99 | (ml1_keep+ml1).output(7, 0) 100 | (via1_keep+via1).output(8, 0) 101 | (ml2_keep+ml2).output(9, 0) 102 | (pad_keep+pad).output(10, 0) 103 | (pwell_keep+pwell).output(13, 0) 104 | g_cnt = cnt.inside(tin & ml1) 105 | sd_cnt = cnt - g_cnt 106 | #(g_cnt_keep+g_cnt).output(21, 0) 107 | #(sd_cnt_keep+sd_cnt).output(22, 0) 108 | (g_cnt_keep+g_cnt).output(6, 0) 109 | (sd_cnt_keep+sd_cnt).output(6, 0) 110 | 111 | #frame.output(14, 0) 112 | # for LVS for Product 113 | res.output(15, 0) 114 | cap.output(16, 0) 115 | dio.output(17, 0) 116 | 117 | 118 | 119 | 120 | 121 | 122 | puts source.path.sub(/\.gds|\.GDS/, '_converted.gds') + ' created' 123 | 124 | -------------------------------------------------------------------------------- /Technology/tech/symbols/EEschema/MinedaSymbols.lib~: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | EELAYER 30 0 3 | EELAYER END 4 | $Descr A4 11693 8268 5 | encoding utf-8 6 | Sheet 1 1 7 | Title "" 8 | Date "" 9 | Rev "" 10 | Comp "" 11 | Comment1 "" 12 | Comment2 "" 13 | Comment3 "" 14 | Comment4 "" 15 | $EndDescr 16 | $Comp 17 | L MinedaSymbols:0_MIN #GND? 18 | U 1 1 5FC49A38 19 | P 2400 2450 20 | F 0 "#GND?" H 2400 2350 50 0001 C CNN 21 | F 1 "0_MIN" H 2400 2539 50 0000 C CNN 22 | F 2 "" H 2550 2450 50 0001 C CNN 23 | F 3 "" H 2550 2450 50 0001 C CNN 24 | 1 2400 2450 25 | 1 0 0 -1 26 | $EndComp 27 | $Comp 28 | L MinedaSymbols:CAP_MIN C? 29 | U 1 1 5FC4A542 30 | P 2850 2300 31 | F 0 "C?" H 2928 2241 50 0000 L CNN 32 | F 1 "CAP" H 2928 2150 50 0000 L CNN 33 | F 2 "" H 2800 2370 50 0001 C CNN 34 | F 3 "" H 2800 2370 50 0001 C CNN 35 | F 4 "C" H 2950 1900 50 0001 L CNN "Spice_Primitive" 36 | F 5 "C" H 2928 2059 50 0000 L CNN "Spice_Model" 37 | F 6 "Y" H 2950 2000 50 0001 L CNN "Spice_Netlist_Enabled" 38 | 1 2850 2300 39 | 1 0 0 -1 40 | $EndComp 41 | $Comp 42 | L MinedaSymbols:HR_POLY_MIN R? 43 | U 1 1 5FC4AEB1 44 | P 3300 2300 45 | F 0 "R?" H 3378 2241 50 0000 L CNN 46 | F 1 "HR_POLY" H 3378 2150 50 0000 L CNN 47 | F 2 "" H 3300 2300 50 0001 C CNN 48 | F 3 "" H 3300 2300 50 0001 C CNN 49 | F 4 "R" H 3425 1950 50 0001 L CNN "Spice_Primitive" 50 | F 5 "R" H 3378 2059 50 0000 L CNN "Spice_Model" 51 | F 6 "Y" H 3425 2050 50 0001 L CNN "Spice_Netlist_Enabled" 52 | 1 3300 2300 53 | 1 0 0 -1 54 | $EndComp 55 | $Comp 56 | L MinedaSymbols:NMOS_MIN M? 57 | U 1 1 5FC4B8F1 58 | P 3900 2450 59 | F 0 "M?" H 4144 2496 50 0000 L CNN 60 | F 1 "NMOS_MIN" H 4250 2550 50 0001 L CNN 61 | F 2 "" H 3900 2450 50 0001 C CNN 62 | F 3 "" H 3900 2450 50 0001 C CNN 63 | F 4 "M" H 4250 2250 50 0001 L CNN "Spice_Primitive" 64 | F 5 "nchOR1ex l=1u w=2u" H 4144 2405 50 0000 L CNN "Spice_Model" 65 | F 6 "Y" H 4250 2350 50 0001 L CNN "Spice_Netlist_Enabled" 66 | 1 3900 2450 67 | 1 0 0 -1 68 | $EndComp 69 | $Comp 70 | L MinedaSymbols:NDIO_MIN D? 71 | U 1 1 5FC4CE9B 72 | P 5350 2300 73 | F 0 "D?" H 5428 2196 50 0000 L CNN 74 | F 1 "NDIO_MIN" H 5428 2105 50 0000 L CNN 75 | F 2 "" H 5350 2300 50 0001 C CNN 76 | F 3 "" H 5350 2300 50 0001 C CNN 77 | F 4 "D" H 5500 1950 50 0001 L CNN "Spice_Primitive" 78 | F 5 "NDIO" H 5500 2150 50 0001 L CNN "Spice_Model" 79 | F 6 "Y" H 5500 2050 50 0001 L CNN "Spice_Netlist_Enabled" 80 | 1 5350 2300 81 | 1 0 0 -1 82 | $EndComp 83 | $Comp 84 | L MinedaSymbols:NMOS_ESD_MIN U? 85 | U 1 1 5FC4DA8D 86 | P 5950 2300 87 | F 0 "U?" H 6378 2046 50 0000 L CNN 88 | F 1 "NMOS_ESD_MIN" H 6378 1955 50 0000 L CNN 89 | F 2 "" H 5950 2300 50 0001 C CNN 90 | F 3 "" H 5950 2300 50 0001 C CNN 91 | 1 5950 2300 92 | 1 0 0 -1 93 | $EndComp 94 | $Comp 95 | L MinedaSymbols:PMOS_MIN M? 96 | U 1 1 5FC4E5C6 97 | P 2400 3200 98 | F 0 "M?" H 2644 3246 50 0000 L CNN 99 | F 1 "PMOS_MIN" H 2750 3300 50 0001 L CNN 100 | F 2 "" H 2400 3200 50 0001 C CNN 101 | F 3 "" H 2400 3200 50 0001 C CNN 102 | F 4 "M" H 2750 3000 50 0001 L CNN "Spice_Primitive" 103 | F 5 "pchOR1ex l=1u w=6u" H 2644 3155 50 0000 L CNN "Spice_Model" 104 | F 6 "Y" H 2750 3100 50 0001 L CNN "Spice_Netlist_Enabled" 105 | 1 2400 3200 106 | 1 0 0 -1 107 | $EndComp 108 | $Comp 109 | L MinedaSymbols:PDIO_MIN D? 110 | U 1 1 5FC4EEFC 111 | P 3850 3050 112 | F 0 "D?" H 3928 2946 50 0000 L CNN 113 | F 1 "PDIO_MIN" H 3928 2855 50 0000 L CNN 114 | F 2 "" H 3850 3050 50 0001 C CNN 115 | F 3 "" H 3850 3050 50 0001 C CNN 116 | F 4 "D" H 4000 2700 50 0001 L CNN "Spice_Primitive" 117 | F 5 "PDIO" H 4000 2900 50 0001 L CNN "Spice_Model" 118 | F 6 "Y" H 4000 2800 50 0001 L CNN "Spice_Netlist_Enabled" 119 | 1 3850 3050 120 | 1 0 0 -1 121 | $EndComp 122 | $Comp 123 | L MinedaSymbols:PMOS_ESD_MIN U? 124 | U 1 1 5FC4FEC4 125 | P 4400 3050 126 | F 0 "U?" H 4828 2796 50 0000 L CNN 127 | F 1 "PMOS_ESD_MIN" H 4828 2705 50 0000 L CNN 128 | F 2 "" H 4400 3050 50 0001 C CNN 129 | F 3 "" H 4400 3050 50 0001 C CNN 130 | 1 4400 3050 131 | 1 0 0 -1 132 | $EndComp 133 | $Comp 134 | L MinedaSymbols:RES_MIN R? 135 | U 1 1 5FC50D34 136 | P 5450 3050 137 | F 0 "R?" H 5528 2991 50 0000 L CNN 138 | F 1 "RES_MIN" H 5528 2900 50 0000 L CNN 139 | F 2 "" H 5500 3050 50 0001 C CNN 140 | F 3 "" H 5500 3050 50 0001 C CNN 141 | F 4 "R" H 5600 2700 50 0001 L CNN "Spice_Primitive" 142 | F 5 "R" H 5528 2809 50 0000 L CNN "Spice_Model" 143 | F 6 "Y" H 5600 2800 50 0001 L CNN "Spice_Netlist_Enabled" 144 | 1 5450 3050 145 | 1 0 0 -1 146 | $EndComp 147 | $Comp 148 | L MinedaSymbols:R_POLY_MIN R? 149 | U 1 1 5FC51496 150 | P 5950 3050 151 | F 0 "R?" H 6028 2991 50 0000 L CNN 152 | F 1 "R_POLY_MIN" H 6028 2900 50 0000 L CNN 153 | F 2 "" H 5950 3050 50 0001 C CNN 154 | F 3 "" H 5950 3050 50 0001 C CNN 155 | F 4 "R" H 6100 2700 50 0001 L CNN "Spice_Primitive" 156 | F 5 "R" H 6028 2809 50 0000 L CNN "Spice_Model" 157 | F 6 "Y" H 6100 2800 50 0001 L CNN "Spice_Netlist_Enabled" 158 | 1 5950 3050 159 | 1 0 0 -1 160 | $EndComp 161 | $Comp 162 | L MinedaSymbols:NDIO_MIN D? 163 | U 1 1 601A81A1 164 | P 5100 1700 165 | F 0 "D?" H 5178 1596 50 0000 L CNN 166 | F 1 "NDIO_MIN" H 5178 1505 50 0000 L CNN 167 | F 2 "" H 5100 1700 50 0001 C CNN 168 | F 3 "" H 5100 1700 50 0001 C CNN 169 | F 4 "D" H 5250 1350 50 0001 L CNN "Spice_Primitive" 170 | F 5 "NDIO" H 5250 1550 50 0001 L CNN "Spice_Model" 171 | F 6 "Y" H 5250 1450 50 0001 L CNN "Spice_Netlist_Enabled" 172 | 1 5100 1700 173 | 1 0 0 -1 174 | $EndComp 175 | $EndSCHEMATC 176 | -------------------------------------------------------------------------------- /Technology/tech/AIST-SOI-CMOS.xs: -------------------------------------------------------------------------------- 1 | # AIST-SOI-CMOS.xs v0.2 based on YSS-SOI-CMOS v0.31 by Swear Takahashi July 3rd, 2021 2 | # SOI CMOS process description demonstrating: 3 | # - Source/Drain diffusion 4 | # - TIN Gate formation 5 | # - Contact to Source/Drain and Al gate 6 | # - 2nd metal layer formation 7 | 8 | # Pick a 10x finer database unit for enhanced accuracy: 9 | dbu(dbu * 0.1) 10 | 11 | # Basic options: declare the depth of the simulation and the height. 12 | # These are the defaults: 13 | # depth(10.0) 14 | # height(10.0) 15 | # Declare the basic accuracy used to remove artefacts for example: 16 | delta(5 * dbu) 17 | height(200.0) 18 | # Declaration the layout layers. 19 | # Possible operations are (l1 = layer(..); l2 = layer(..)) 20 | # "or" l1.or(l2) 21 | # "and" l1.and(l2) 22 | # "xor" l1.xor(l2) 23 | # "not" l1.not(l2) 24 | # "size" l1.sized(s) (s in micron units) 25 | # or l1.sized(x, y) (x, y in micron units) 26 | # "invert" l1.inverted 27 | #Layers Definition 28 | 29 | soi = layer("4/0") 30 | if soi.data.size > 0 # for production 31 | pdiff = layer("2/0") 32 | ndiff = layer("3/0") 33 | tin = layer("5/0").inverted 34 | cnt = layer("6/0") 35 | ml1 = layer("7/0").inverted 36 | via1 = layer("8/0") 37 | ml2 = layer("9/0").inverted 38 | soi = soi.inverted 39 | else # for designers 40 | diff = layer("3/0") 41 | diffa = diff.sized(2.0) 42 | tin = layer("21/0") 43 | if tin.data.size == 0 44 | tin = layer("5/0") 45 | end 46 | tin = tin.inverted 47 | cnt = layer("7/0") 48 | ml1 = layer("8/0").inverted 49 | via1 = layer("9/0") 50 | ml2 = layer("10/0").inverted 51 | cap = layer("16/0") 52 | parea = layer("18/0") 53 | narea = layer("19/0") 54 | pdiff = diffa.and(parea).and(tin.or(cap)) 55 | ndiff = diffa.and(narea).and(tin.or(cap)) 56 | soi = diff.inverted 57 | end 58 | 59 | #### layer Thichness 60 | yfactor = 10.0 # zoom Y-direction by factor of 10 61 | tsub = 0.8 * yfactor 62 | tbox = 0.4 * yfactor 63 | tsoi = 0.095 * yfactor # AIST: 0.2 -> 0.095 64 | tox = 0.015 * yfactor # AIST: 0.02 -> 0.015 65 | ttin = 0.05 * yfactor # AIST: 0.1 -> 0.05 66 | tteos1 = 0.25 * yfactor # AIST: 0.3 -> 0.25 67 | tcnt = 0.27 * yfactor # AIST: 0.32 -> ttes1+0.2=0.27 68 | tml1a = 0.3 * yfactor # AIST: same 69 | tvia1 = 0.3 * yfactor 70 | tteos2 = 0.3 * yfactor # AIST: same 71 | tml2a = 0.3 * yfactor # AIST: 0.55 -> 0.3 72 | 73 | # Process steps: 74 | # Now we move to cross section view: from the layout geometry we create 75 | # a material stack by simulating the process step by step. 76 | # The basic idea is that all activity happens at the surface. We can 77 | # deposit material (over existing or at a mask), etch material and 78 | # planarize. 79 | # A material is a 2D geometry as seen in the cross section along the 80 | # measurement line. 81 | 82 | # Start with the n doped bulk and assign that to material "nbulk" 83 | # "bulk" delivers the wafer's cross section. 84 | 85 | nbulk = bulk 86 | # SUB.BOX/SOI deposit 87 | sub = deposit(tsub) 88 | box = deposit(tbox) 89 | soia = deposit(tsoi) 90 | 91 | mask(soi).etch(tsoi*2,:into => soia,:taper =>30) 92 | 93 | # N/P doping 94 | 95 | nplus = mask(ndiff).grow(1.0*yfactor, 1.0, :mode => :round, :into => soia) 96 | pplus = mask(pdiff).grow(0.5*yfactor, 0.5, :mode => :round, :into => soia) 97 | 98 | 99 | # SOI etching (taper = 70) 100 | 101 | mask(soi).etch(tsoi*2,:into => pplus,:taper =>30) 102 | mask(soi).etch(tsoi*2,:into => nplus,:taper =>30) 103 | 104 | # 20nm gate oxide.deposit 105 | gox = deposit(tox) 106 | 107 | # 100nm TiN deposit 108 | tina = deposit(ttin) 109 | 110 | # TiN etching 111 | mask(tin).etch(ttin*2.0,:into => tina, :taper =>5) 112 | 113 | # deposit first TEOS 300nm 114 | 115 | iso1 = deposit(tteos1,:mode => :round) 116 | 117 | # etch the gate and source/drain contacts 118 | 119 | mask(cnt).etch(tteos1, :into => iso1, :taper => 4) 120 | mask(cnt).etch(tcnt, :into => gox, :taper => 4) 121 | 122 | 123 | ## Metal1 deposit alu1:metal1 deposit 124 | 125 | alu1 = deposit(tml1a,1.0, :mode => :round) 126 | 127 | ##alu1 etcing by ml1-MASK 128 | mask(ml1).etch(tml1a*2, :into => alu1, :taper => 8) 129 | 130 | # isolation TEOS2 layer deposit 131 | 132 | iso2 = deposit(tteos2,tteos1/2.0, :mode => :round) 133 | 134 | # tungsten CMP: take off 0.45 micron measured from the top level of the 135 | # w, iso materials from w and iso. 136 | # Alternative specifications are: 137 | # :downto => {material(s)} planarize down to these materials 138 | # :to => z planarize to the given z position measured from 0 (the initial wafer surface) 139 | #planarize(:into => [w, iso], :less => 0.65) 140 | 141 | ### iso1 etching for M1-M2 contact## 142 | 143 | mask(via1).etch(tvia1*2,0.3, :into => iso2,:taper =>5) 144 | 145 | ### metal2 deposit all region ## 146 | 147 | alu2 = deposit(tml2a,0.1,:mode => :round) 148 | 149 | ## metal2 Layer eching By ml2 150 | 151 | mask(ml2).etch(tml2a,0.5, :into => alu2, :taper => 5) 152 | 153 | #planarize(:into => [alu1], :less => 0.3) 154 | # finally output all result material. 155 | # output specification can be scattered throughout the script but it is 156 | # easier to read when put at the end. 157 | 158 | output("sub (280/0)", sub) 159 | output("box (282/0)", box) 160 | output("soi (284/0)", soia) 161 | 162 | output("pdiff (290/0)", pplus) 163 | output("ndiff (292/0)", nplus) 164 | 165 | output("gox (300/0)", gox) 166 | output("tina (301/0)",tina) 167 | output("iso1 (302/0)",iso1) 168 | output("alu1 (305/0)", alu1) 169 | 170 | output("iso1 (310/0)", iso2) 171 | 172 | output("alu2 (400/0)", alu2) 173 | 174 | layers_file("YSS-SOI-CMOS_Xsection.lyp") 175 | 176 | 177 | -------------------------------------------------------------------------------- /Technology/tech/YSS-SOI-CMOS.xs: -------------------------------------------------------------------------------- 1 | # YSS-SOI-CMOS.xs v0.1 by Swear Takahashi May 31st, 2021 2 | # v0.2 by S. Moriyama June 2nd, 2021 3 | # - added diff_cut check 4 | # v0.3 fixed by Swear Takahashi, June 6th, 2021 5 | # v0.31 diff related bug fix by Swear Takahashi, July 3rd, 2021 6 | # SOI CMOS process description demonstrating: 7 | # - Source/Drain diffusion 8 | # - TIN Gate formation 9 | # - Contact to Source/Drain and Al gate 10 | # - 2nd metal layer formation 11 | 12 | # Pick a 10x finer database unit for enhanced accuracy: 13 | dbu(dbu * 0.1) 14 | 15 | # Basic options: declare the depth of the simulation and the height. 16 | # These are the defaults: 17 | # depth(10.0) 18 | # height(10.0) 19 | # Declare the basic accuracy used to remove artefacts for example: 20 | delta(5 * dbu) 21 | height(200.0) 22 | # Declaration the layout layers. 23 | # Possible operations are (l1 = layer(..); l2 = layer(..)) 24 | # "or" l1.or(l2) 25 | # "and" l1.and(l2) 26 | # "xor" l1.xor(l2) 27 | # "not" l1.not(l2) 28 | # "size" l1.sized(s) (s in micron units) 29 | # or l1.sized(x, y) (x, y in micron units) 30 | # "invert" l1.inverted 31 | #Layers Definition 32 | 33 | soi = layer("4/0") 34 | if soi.data.size > 0 # for production 35 | pdiff = layer("2/0") 36 | ndiff = layer("3/0") 37 | tin = layer("5/0").inverted 38 | cnt = layer("6/0") 39 | ml1 = layer("7/0").inverted 40 | via1 = layer("8/0") 41 | ml2 = layer("9/0").inverted 42 | soi = soi.inverted 43 | else # for designers 44 | diff = layer("3/0") 45 | diffa = diff.sized(2.0) 46 | tin = layer("21/0") 47 | if tin.data.size == 0 48 | tin = layer("5/0") 49 | end 50 | tin = tin.inverted 51 | cnt = layer("7/0") 52 | ml1 = layer("8/0").inverted 53 | via1 = layer("9/0") 54 | ml2 = layer("10/0").inverted 55 | cap = layer("16/0") 56 | parea = layer("18/0") 57 | narea = layer("19/0") 58 | pdiff = diffa.and(parea).and(tin.or(cap)) 59 | ndiff = diffa.and(narea).and(tin.or(cap)) 60 | soi = diff.inverted 61 | end 62 | 63 | #### layer Thichness 64 | yfactor = 10.0 # zoom Y-direction by factor of 10 65 | tsub = 0.8 * yfactor 66 | tbox = 0.4 * yfactor 67 | tsoi = 0.2 * yfactor 68 | tox = 0.02 * yfactor 69 | ttin = 0.1 * yfactor 70 | tteos1 = 0.3 * yfactor 71 | tcnt = 0.32 * yfactor 72 | tml1a = 0.3 * yfactor 73 | tvia1 = 0.3 * yfactor 74 | tteos2 = 0.3 * yfactor 75 | tml2a = 0.55 * yfactor 76 | 77 | # Process steps: 78 | # Now we move to cross section view: from the layout geometry we create 79 | # a material stack by simulating the process step by step. 80 | # The basic idea is that all activity happens at the surface. We can 81 | # deposit material (over existing or at a mask), etch material and 82 | # planarize. 83 | # A material is a 2D geometry as seen in the cross section along the 84 | # measurement line. 85 | 86 | # Start with the n doped bulk and assign that to material "nbulk" 87 | # "bulk" delivers the wafer's cross section. 88 | 89 | nbulk = bulk 90 | # SUB.BOX/SOI deposit 91 | sub = deposit(tsub) 92 | box = deposit(tbox) 93 | soia = deposit(tsoi) 94 | 95 | mask(soi).etch(tsoi*2,:into => soia,:taper =>30) 96 | 97 | # N/P doping 98 | 99 | nplus = mask(ndiff).grow(1.0*yfactor, 1.0, :mode => :round, :into => soia) 100 | pplus = mask(pdiff).grow(0.5*yfactor, 0.5, :mode => :round, :into => soia) 101 | 102 | 103 | # SOI etching (taper = 70) 104 | 105 | mask(soi).etch(tsoi*2,:into => pplus,:taper =>30) 106 | mask(soi).etch(tsoi*2,:into => nplus,:taper =>30) 107 | 108 | # 20nm gate oxide.deposit 109 | gox = deposit(tox) 110 | 111 | # 100nm TiN deposit 112 | tina = deposit(ttin) 113 | 114 | # TiN etching 115 | mask(tin).etch(ttin*2.0,:into => tina, :taper =>5) 116 | 117 | # deposit first TEOS 300nm 118 | 119 | iso1 = deposit(tteos1,:mode => :round) 120 | 121 | # etch the gate and source/drain contacts 122 | 123 | mask(cnt).etch(tteos1, :into => iso1, :taper => 4) 124 | mask(cnt).etch(tcnt, :into => gox, :taper => 4) 125 | 126 | 127 | ## Metal1 deposit alu1:metal1 deposit 128 | 129 | alu1 = deposit(tml1a,1.0, :mode => :round) 130 | 131 | ##alu1 etcing by ml1-MASK 132 | mask(ml1).etch(tml1a*2, :into => alu1, :taper => 8) 133 | 134 | # isolation TEOS2 layer deposit 135 | 136 | iso2 = deposit(tteos2,tteos1/2.0, :mode => :round) 137 | 138 | # tungsten CMP: take off 0.45 micron measured from the top level of the 139 | # w, iso materials from w and iso. 140 | # Alternative specifications are: 141 | # :downto => {material(s)} planarize down to these materials 142 | # :to => z planarize to the given z position measured from 0 (the initial wafer surface) 143 | #planarize(:into => [w, iso], :less => 0.65) 144 | 145 | ### iso1 etching for M1-M2 contact## 146 | 147 | mask(via1).etch(tvia1*2,0.3, :into => iso2,:taper =>5) 148 | 149 | ### metal2 deposit all region ## 150 | 151 | alu2 = deposit(tml2a,0.1,:mode => :round) 152 | 153 | ## metal2 Layer eching By ml2 154 | 155 | mask(ml2).etch(tml2a,0.5, :into => alu2, :taper => 5) 156 | 157 | #planarize(:into => [alu1], :less => 0.3) 158 | # finally output all result material. 159 | # output specification can be scattered throughout the script but it is 160 | # easier to read when put at the end. 161 | 162 | output("sub (280/0)", sub) 163 | output("box (282/0)", box) 164 | output("soi (284/0)", soia) 165 | 166 | output("pdiff (290/0)", pplus) 167 | output("ndiff (292/0)", nplus) 168 | 169 | output("gox (300/0)", gox) 170 | output("tina (301/0)",tina) 171 | output("iso1 (302/0)",iso1) 172 | output("alu1 (305/0)", alu1) 173 | 174 | output("iso1 (310/0)", iso2) 175 | 176 | output("alu2 (400/0)", alu2) 177 | 178 | layers_file("YSS-SOI-CMOS_Xsection.lyp") 179 | 180 | 181 | -------------------------------------------------------------------------------- /Basic/grain.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | ICPS2023_5/Basic 4 | 5 | false 6 | 0.0 7 | 8 | Static Library 9 | This template provides a static library 10 | doc/readme.html 11 | 12 | Apache 2.0 13 | 14 | 15 | 16 | 2023-05-12T15:55:25 17 | iVBORw0KGgoAAAANSUhEUgAAAEAAAABACAYAAACqaXHeAAAACXBIWXMAAAX/AAAF/wHJdq1WAAAAGXRFWHRTb2Z0d2FyZQB3d3cuaW5rc2NhcGUub3Jnm+48GgAAEPRJREFUeJzlW3tsXUV6/83Med1z7svXvrGd2LHjxE5THCICRUBDuywkLQEhtSUr/tiyEkUqK9EVUlsEqF1FtLvbqmwVadWVStFmtU27UtJNoUlBEBRCILAhmJC3SZoXxI/YsWP7+j7OY2b6hz0n5x5fZ0u4zv7RkY7OvefOzP2+33zf7/vmcYD/54Xc7D/csmVLczabbbNtu0XX9bQQokgpHa5UKkM7d+4c3LFjB7+Z8iw4AM8880xrT0/P021tbb9vmuZK0zQdxhiEELBtG8ViEaZpQggB3/fdSqVy1nXdd4aGhn781FNPnVxo+RYMgE2bNrFVq1b9aMWKFX+Sz+cN27ZhGAamp6eRTqdx9OhRPPjgg9i/fz+6u7sxODgI0zSRy+VQLpdRKpXEyMjI7vPnz//x5s2bpxZKTm2hOs7lcj/MZDLfzmaz0HUdhmFASonLly9j1apVWLlyJWzbxqOPPopSqQTLssA5ByEEnHP4vk8bGhoeuXLlyn8A2LBQci4YAJ7n3VsoFDA1NQXDMOB5HizLwsWLFzE6OgohBEqlEgAgCAJcvXoVfX19WLduHTzPQxAEmJqawsTExB0LJSOwgABks1mSyWTQ0dGBoaEh+L4Pz/Owbt06lMtl7Ny5Ex0dHchkMnjvvffwwAMPYO3atZiYmABjDGNjY+jv74dpmnKhZAQWEIBSqeR1dXVh7969sG0bAwMDWLRoEXK5HNLpNDo7O8EYQ7FYxJo1azAwMIDW1lYkk0mcPHkS/f396OrqQrFYdBdKRmABAUin0/qxY8fwyCOPoFwuY+/evRgbG8PAwACCIIAQIqxLCAFjDIlEAl1dXVi9ejXa29tx+PBh2LZtLJSMwAJFgaeffnoxY+zoxo0bG0dGRrB37144joPu7m60tbXBdd0QBKW8ZVlobm5Gf38/Dh8+jEwmgzVr1uDcuXOyra1t5/vvv/9nL7/88lC9Za07AM8///xv9/b27j516lQ2nU7DsiysW7cOR48exfDwMC5evIjLly+jXC6jXC7DsiwYhoF8Po+7774bt99+OyilOH78OM6ePYtUKgXP89DV1XX14MGDD7300ksf1lPeurtAe3v71kKhkJ2cnERLSwvWr1+P3bt34+DBg6CUorGxEbfeeiuy2SwMwwDnHKVSCePj4zh+/Dj27duHnp4erF69Gvl8Hu+++y6WLVuGycnJhiVLlvwUwMp6ylt3AHzfX9Tc3IzW1lb09fVh165duO2227BhwwYkk0mUSiUUi0UUi0WMjY3Btm1YloXu7m7ccsstSKfT2L9/P7Zu3QpCCFpbW5HNZpHJZPDZZ5811lveugNw7NixA4lEYmNPTw+y2SwuXbqEwcFBfPrppxgZGYHv+2FiRCmFlBK+78P3fQBALpdDLpdDU1MTlixZgqVLl8IwDLz99tsol8t1NX9gATjg1KlTe/fs2bPu0KFDWnd3N1m6dCkymQyuXLmCiYkJTE1NoVgshkQIAJqmwbIsOI6DdDqNlpYWtLW14fPPP8eBAwfQ19cnn3jiCf/+++9/d+XKlXXNCusKwKZNm9iLL7441NTUZE1PT6e2bduGd955B2NjY1IIQdLpNPL5PDKZDBzHga7rAADP8+D7PiilIIRgamoKe/bsQXt7OzZs2IDHHnsMzc3NhWKxWHnhhRda6zljrCsAu3bt+s5dd931/aamJgcApqenMTk5Cd/3SwcPHrRPnDiBgYEBXL58GdPT0/A8DwBgGAZSqRSam5uxePFi9Pb2ore3VxqGQRRgAHDlypXCoUOHvrtx48Yt9ZK5rhwghPiN8fFxP5fLgVKKZDIJx3E8z/OC9evX47777gPnHEEQhHfXvZboaZqGRCIBwzCQTqfLtm2bANhs35iamhLJZPIeKeWrAMoAJgG4hJAbTpfrCkAqlepobGzMDgwMXGpra2sjhHiEkIppmmnTNOfUD4IAExMTMAwjJEVCCPzSGRSHdthT7rAMghIAF4IHMmF1ZlZ33/eIEGKllLIPwC8YY31SylFCyA25RV1d4IMPPujr7u5eO6vskJTSdhwnwxibt43neSCEQPIirl78MUpTg3BdwPMYKsURFMbPQgqOdNMqJBvaYBoBmLwgdafbX9Tz3DlCnZ9rmvZPhJCxG5G5rhZgmmaTlBKEEJTLZUsIkS4UChVCyDSltEwpFbqu65TSVDKZTClgvOJnuPw/P8FUZQW4vhZSY5AoQOiAlfIArwhppVGAhmmfQtM3ElM6RqnvWz0t3X/xNc25fSuAXz8Auq6nhBCglEIIERBCYJqmyRgzKaVgjIWxf3p6usI590Rxnz0+8KE24a1Cpvl3VFsIIcA5hxACjDEQMmOsUkroug4pJdD0d3T4wo575eSffhPAD25E5nq6ADlx4kSpqanJSqVSKBQKQwBalNLqTimFpmmgVGLkzBYyMnwFWu5h2Kl2SCkhpQRjDFJKCCHgeV4YLgkh4SXlNd4Tbn+5cvYPfyFN76k1v4filxGa1kv7zZs3L7dt21ACBkHA1ahF74QQcO8K+fzT58jZM18gueRbSDcsC0HSdR2EEGiaFhIjYwyGYUDXdWiaFtZTl+H0JpKrDn5Dp6uPHH0Vq38tAOTz+XuSySRVTA5AxJVnjMGdPEguHPk+zg9qWLb2L2Enc6FCmqaFSql+CCHhZ03Tqi7GGBhjM2Al8kZ61a5lVst33j3yKnvypgPgOE6npmmh0GquDyA0+8Lgv5MLp3dhdLoTt9z55zCMRKgEpTRcODUMI3ym+tA0DVLKUHkAIVDX3MqgmWUvNCR7/vMfj76m/+uRN+HcNABSqVQLgHDEOOeh4Iy4ZOT0ZvLZmTOQ5r3oWfPNUPGo36v6UdCklCEQUS6IAhJ1G84FUk13pdK9v/wjTXYfPrITvTcFgEQi0a6EmwWB6roO+BfJF8e+i8PHrqJl2TewZNk9UJaiZoBRZaN3FTFUv9EoojZX1HdldYZhQAiBRLItkb7lzS6z9cl913OJugGQTCYXK7OfHS2DT39Azp/8KY6cJrjjd59HpqEtHE3OeWi+jDEEQRBaQVRJFQ10XQ/dSoVKXdcRBEFYP95O0xIst/xvG53l//YPR16l//LBdiQWDADTNJvUiMyCwIYG+7Hr9TfxtQf/GobpgNKZv1P1AISCA9esRz03DCP8DMy4hwIh6jbxXEEIEZIkIQyZ5q9nRf4HD6QS7IcLBoCu65moBTDGmFspQDccaJpRxegxoMI+1GfOeZVyQoiquF8LMNV3/DcpJQiluDgw1UBg5xcEgGeffTZlmqatfHGW2DTfd2GYqSrlVFF147lC9LMiyOgSeryP6D3aXvUf9ieFBi2VjPdRFwCamprWZrNZPZqpUUoZ5wF0I1EVEmsJWEsJoHr0o2So6tdqE+9P3TnnGpfOwgDQ0NBwm2VZVTkAY4wJ4YNpc6fB1xM8Xk+BoL7XGu24ddUCmAupSzhz8oK6AOA4zuKoj8/u8rIg4NB1Y14LiAsNVIMTN/3ob7Xq16ob3iFpIOcCUJfZoG3bLVHz55wLSimbsQRzzgj9KsEjPAJgLhC/qqhwGLUCCgpfWvacul+q53kKY2wRcM0cPc/zZydE0HWrZpta5BctSoEoCcbNOto+mjRF+wjrUwLBrYXJAyzLWhRNWYUQ/owrCDCtem9zPuKLmmxU8TgJ1irzuVS0HSUUnFhzCKkuANi2nY/mAJxzTghBwAU07ZoFxJk8+ryWErVIEEBVMhRVuBZnhJZGdUhhzlmbqwcAJJoEzSYiwYxAEppuVhFW3AKuB8Z8o3+93CBULOYSum4ikExu344qEL4yAJs3b16eyWScaGIjhJi1gJk/jo5cdPJSi+Siz+JXHAj1LJoCx61C/a7pCXBO/dGT1fOBrwxAPp+/J51O01jmxQV3wQMOxq65XRSkOEvHlY9zQZwj4i4Qt5Q4ELqegJAkSBh1BiCZTHaoeXp0siNEBZ7nQtOqXeB64S/6e9wF4peqc738IQq4biTBBeWlIqpC4VcCQEpJWlpaHi0Wi1WrNwAkD1y4XikMg0ootVBSa7TjQKg2UQuIg6nqcc5rWo26DD0BISgXonqV6KtagJ1KpZZ7nlcFgJQSnLtwvQrYLABKkCgAtUw7Ck7cGpSStdrVcouq6bFhgUvKi14dXeD111/vamxstCmlcF03dAFKKUTgwvfK0DT7ur4KVFtFHKBa4MxnNbVcRhEo00xwASFFHV0gCIJv53I5MrMWx1GpVAAAQgjmuSV4bhmaZoWKRe9RwePCRhVXUWM+5eKgRO8qN+CcQ2cWACYrfh0BaGhoWEcICVdxi8Wi2utjnl+G71egzbpANLbPghTe40JHFUwkEuESl1I2eo+6xnygcs5BNB0SRHpuHQFIpVJLxsbGqtbpJycnQQhJ+l4FvlcGY/ocAaMKx2N5vJ7jOOFKcZQDonWjiscBVSBRokMIyEDUkQNKpdKbw8PD4WaGWu1ljFmc+wgCF5QZcxg66ue1BI+CpM4L1CI+9Szefy03YZoOCRCvni6wdevWv3FdV3DOQxCklGLmcLQLITgo1cIRjipRK2+vJbxlWbAsqyqM1pokxcGLcwYlGggYPK+OALzyyiunzp49e/zcuXPh3h0hJKCUwvPKM3/A9CpiUz6pPsdjeBQcKSVs24bjOPOOdLRvBZBqW8UtlEEQkIDXEQAAeOutt35eKBREoVBQjC0ppfDcmYigLCAqfC1Tj14KBEWw0eW2KF/M108QBHPCJKMaNKIx36P1TYWLxeKPPvnkkzNnzpwBAJCZgiBwQQgFgVYzdseJrFYoVPsC6nhN1A3m83lV5jwnFJSZzA/qbwHFjz766J993xdXr14FpZSQ2W0vppkg9NpoqXutUFYLJKV49HzRfBYTV76WdWh6QqsrCaqyffv2LadPnz56+vRpYPZUl+970LQECGFzprNxToj7siJVZQGRzZYqxRQh1gqt0WvmRJoPEKrXnQNmi9y3b99faZrGpZQEAPzAhZXIwPPKcwSLghDN2JSiKqeIjrzaOle7P0IIaJomI0B4syAIKaUrpRwUQlQIITwIiufHr5yF4CJhWFbV3kDdtsa2bdv236Ojox8PDw+T0dFRBL6P5d1fh2mY4QkPQggcx5lj6tFTZFJe2xm2rGvLaSrZUpupswQpCSGSUioYY8eklF9wzt8JguCclPKE53mvViqVfimNraaG3W5lXEskklUAzH9+7QaKlPJQPp/f1NHRwdvau43O5b9FmluWQtO08GisGr3omSF1qRFXCZU6IQoAlUoluikqOOe+pmlXPc+bkFJOUUp3u647KqX8ryAIfum67p7x8fEtyWTyJ5lM5sDK37zjZ9/73t+vYIbz0mu7DlxS/db9sPTjjz/+3J133vnk2rVrl7W3t9NMJiMNwxB0lh2jfl4sFsM3yhQ46i0zTdOQSqXCficnJxEEgfQ8L2CMnZJSfuh53nHf9y8JIZZ7nnfYtu0DANDd3f1/fs+o7gDMcoB98uTJxtdee+0hwzAe6ujouKOzs3NRa2sryWazQtd1SQihKmRG2sbzfS6l9KSURULIBcbY20KI/bZtHwcwAaBEbvCEqCoL+ursLBg6APONN95Y9PHHHz/kOM7Gzs7OtUuXLs0vXrwYDQ0NAAAhhBRCeL7vTwohPrcs6yPbtk9JKS8IIb7Qdf0qgOnZyydf4XxwtNzUl6dnAWGjo6PWjh07Vly6dOkPHn744YampqYLXV1dhzVNuwygCMArFAp+KpXyAHiYUXhBXqq+6W+PR4sCBDN7lAIz+wlfbiPwK5b/BZAWA2467TX9AAAAAElFTkSuQmCC 18 | 19 | 20 | -------------------------------------------------------------------------------- /Technology/tech/tech.lyt: -------------------------------------------------------------------------------- 1 | 2 | 3 | ICPS2023_5 4 | 5 | 6 | 0.001 7 | 8 | C:\Users\seiji\KLayout\salt\ICPS2023_5\Technology\tech 9 | ICPS2023_5.lyp 10 | true 11 | 12 | 13 | 1 14 | true 15 | true 16 | 17 | 18 | true 19 | layer_map() 20 | true 21 | true 22 | 23 | 24 | true 25 | layer_map() 26 | 0.001 27 | true 28 | #1 29 | true 30 | #1 31 | false 32 | #1 33 | true 34 | OUTLINE 35 | true 36 | PLACEMENT_BLK 37 | true 38 | REGIONS 39 | true 40 | 41 | 0 42 | true 43 | .PIN 44 | 2 45 | true 46 | .PIN 47 | 2 48 | true 49 | .FILL 50 | 5 51 | true 52 | .OBS 53 | 3 54 | true 55 | .BLK 56 | 4 57 | true 58 | .LABEL 59 | 1 60 | true 61 | .LABEL 62 | 1 63 | true 64 | 65 | 0 66 | true 67 | 68 | 0 69 | VIA_ 70 | true 71 | default 72 | false 73 | false 74 | 75 | 76 | 77 | false 78 | true 79 | true 80 | 64 81 | 0 82 | 1 83 | 0 84 | DATA 85 | 0 86 | 0 87 | BORDER 88 | layer_map() 89 | true 90 | 91 | 92 | 0.001 93 | 1 94 | 100 95 | 100 96 | 0 97 | 0 98 | 0 99 | false 100 | false 101 | false 102 | true 103 | layer_map() 104 | 105 | 106 | 0 107 | 0.001 108 | layer_map() 109 | true 110 | false 111 | 112 | 113 | 1 114 | 0.001 115 | layer_map() 116 | true 117 | false 118 | true 119 | 120 | 121 | 122 | 123 | 124 | GDS2 125 | 126 | true 127 | false 128 | false 129 | false 130 | false 131 | false 132 | 8000 133 | 32000 134 | LIB 135 | 136 | 137 | 2 138 | true 139 | true 140 | 1 141 | * 142 | false 143 | 144 | 145 | 0 146 | 147 | 148 | false 149 | false 150 | 151 | 152 | 0 153 | 154 | true 155 | 156 | 157 | 158 | 159 | 160 | -------------------------------------------------------------------------------- /Technology/grain.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | ICPS2023_5/Technology 4 | 5 | false 6 | 0.0 7 | 8 | Technology 9 | This template provides a technology 10 | doc/readme.html 11 | 12 | Apache 2.0 13 | 14 | 15 | 16 | 2023-05-12T15:54:56 17 | iVBORw0KGgoAAAANSUhEUgAAAEAAAABACAYAAACqaXHeAAAACXBIWXMAAAX/AAAF/wHJdq1WAAAAGXRFWHRTb2Z0d2FyZQB3d3cuaW5rc2NhcGUub3Jnm+48GgAAE9NJREFUeJzlW3lsXMd5/83Mu/a9PR734HKXh06SlhVRZ2zZkQ+5kl0XkREDFpwUcQIURYvW/iNCgqBoG5QG2hhFkaZIUhRJk6aNk6ZFmqO2UytWLNlyEkeOZckURUqWxZC0SInioT3fvnOmf+zhlUzKkrW0gXaAwb59O/vm9/3m+7755pt5wP/zQt7vDr/85S+bpmmmQqFQQpblMICKEGK+UCjMT05Ozg8ODvL3E8+yE7Bv37742rVrP97d3f1RVVVvVVU1zhgD5xy6rqNcLkNVVXDO4XleyXGco67r7p+YmPj+Y489NrHc+JaNgMHBQRoEwZ/19vb+eSqVMnRdh6IoKJVKiEajGBoawv3334/Dhw+jt7cX09PTUFUV8XgclUoFlmX5s7Oz/zw2Nva5wcFBa7lwSsv14Onp6c/29/f/jWmakGUZiqJACIGZmRmsW7cO/f390HUdDz30ECzLgqZpCIIAhBAEQQDP8yTTNP8kEokYAD69XDiXjQDf9+8pFosoFApQFAWu60LTNExMTGB2dhacc1iWVW+LS5cu4ejRo9ixYwdc14Xv+ygUCsjn8/csF0ZgGQmIRqMkFothxYoVOH/+PDzPg+u62LFjByqVCn70ox9hxYoViMVieOmll7Br1y5s2bIFuVwOjDHMz8/j1KlT0DRNLBdGYBkJqFQq9urVq3Hw4EHouo6pqSm0t7cjHo8jGo1i5cqVYIyhXC5j48aNmJqaQiaTQTgcxsjICE6dOoXVq1ejVCotm/0Dy6sB6okTJ/DAAw+gUqng4MGDmJ+fx9TUFHzfB+dvz3aEEDDGEAqFsHr1amzYsAHd3d04duwYQqFQaLkwAss0Czz66KMJWZaP3n///SsuXryIgwcPwjAM9Pb2oqurC47jNEioC69pGtLpNE6dOoVjx44hFoth48aNGBsb411dXV978cUXH//Wt7610GqsLSfgC1/4wvp169Y9NzIyko1Go9A0DTt27MDQ0BAuXLiAiYkJzMzMoFKpoFKpQNM0KIqCVCqF2267DVu3bgWlFMPDwzh79iwikQhc18WqVaumjhw5cu+XvvSlkVbibbkJZDKZbxYKhWw+n0dHRwd2796NZ555BkeOHAGlFIlEAgMDAzBNE4qiIAgCWJaFhYUFDA8P44UXXkBfXx82bNiAVCqFF198EatWrUKhUOjs6ur6JoDbW4m35QS4rruio6MDmUwGR48exdNPP43Nmzfj3nvvRTgchmVZKJfLKJfLmJ+fh67r0DQNvb29WL9+PaLRKA4fPoxvf/vbIIQgk8nANE3EYjGcPn26s9V4W07A8PDwT3Vd/8O+vj6Ypolz585henoax48fx8WLF+F5XiMwopRCCAHP8+B5HgAgHo8jkUigvb0dnZ2d6OnpgaIoOHToEBzH+ZkQQq51VTdfTgjx3yvelvuA0dHR7x04cODBV199VV27di3t6elBLBbD3NwccrkcCoUCyuVywxECgCRJ0DQNhmHANE1s2rQJa9asQaVSwdzcHCzLEitXrgw6OzvfCoVCQwDCAAwAqhDiBUrp4OOPP156LwuplhIwODhIH3744TOJRCJSLpdT3/3ud3Ho0CHMz88LzjmJRqNIpVKIxWIwDAOyXB1M13XheR4kScLAwAD27NmDaDSKubk5FAoFOI4DIQQYYwKAL0kSwuEwj8ViPJlMukKIY0KIv3j99dd/s23bNu8DI+CZZ57Zu3379n9KJBIJACiVSsjn83BdN/fKK6+YJ0+exNTUFGZmZlAqleC6LgBAURTEYjHs2LEDjzzyCCYnJ1EoFAAAjDEEQYAgCCCEgKqqCIVCkCQJhBDMzMwISZK8Xbt2nQHwX5TSLxJC3GvF3FIfwDnvnZubc9ra2kApRTgchmEYluu6zu7du7Fz504EQQDf9xufjuMAADRNQzabxYULF1AsFnHixAlwzhGPx5FMJqGqKhhjsG27YUK1/xLf95XXXnttzdatWx8E8HcAPhgCDMNYlUwms+fOnTvZ3d29nhBiEUKKqqqmVVV9R3vf95HL5aAoSmNUFUXBxMQENmzYAMuyUKlUGprCGIPv+6CUwjRNhMNh2LaNQ4cOYcOGDSCEVABclwm0lABd1zuFEGhra1tfLBZPE0Jiuq53MMYW71ySEI1GG9+FEOjs7MQtt9yC559/HowxdHR0NGIGIUQjdiiVShgfH8fCwgLuvPNOb/PmzYEQokQIua7FU0sJUFU1K4QAIQS2bRuc83SxWCwAWGCMFQkhgSzLKmMsYRhGe52Y2lRYkCSJKIqir1+/nhSLRdrR0QHLsmDbdmM16XkeVFVFV1cXBgYG4DiOME3TByAAlK8Xc0sJkCQpwTkHpRScc5cQAkVRIoyxCKUUjLHG3F8sFvO2bS/4vg9FUeKMsRgARKPRhoMLh8NIpVIIhULwfR+WZTWmTkIIJElCEASN/gkhpevG3CrhARDGWJQQAkIIhBBe/boG7u1Oq7YelWU5Wi6XiSzL4JzX84KQpPcGi3NeppRelwnQ99TTImVwcDCj67pRF5pz7i8m/GL3mstS96+hfLAmkEqlBsLhMGvSgAC4uvDNGlIvlN7QmFx38qRlGhAOh7vqtlsjQLyb8M2/1esNEmCjqgnXXFpGgGEYaQANIYSo4ljMDyyl5pIk3QgBglL6wZmArus9wOICN18vpf71lFidgDqBQoh31HqpXZN6eo1zXrleAltGQCQS6eacgzFWN4FG9PNu6q+qKmRZboS6IyMj7xD2Kv3i5Zdf1tLptJxOp6PZbPa6cLfMBBRFydZjgJqAFLi68JRSRCKRxqbI8ePHMTo6CsMwkE6noSjKZf7hStOp7y2oqkrC4bB09uzZv3z22Wdffuqpp1ZdK+6WESDLcns9yVkDKr/byNciP0xMTGB4eBgrV65Ef38/uru7kc/n8dZbbzWCH8YYVFWFruuQZRmu62JsbAyjo6NIJBLgnKOrqyvc19f3YcbYr3/wgx/8/bXgbokJ7Nu3L6RpWls9DAYAIYSylPA1OyWMMQwNDSEUCmHdunWXtVu3bh045ygUCjhz5gxs2wbnHEIIyLKMaDSK9vZ2mKZ5WT5hxYoVSCQS7SMjI3/85JNP3vLJT37yTkLIkomSlhCQTqf7YrGYdoUDVJYaeSEEoZTi2LFjSCaTSCQSixLFGINpmjBN8zKn6Pt+Y21Q9xWu68JxHJw/fx5dXV249dZbddM0t3/9618/LoTYtBQJLSEgkUjc1Ly5WfMFarNATfN8Y+STySSSySSubPdupR4q14VvDqMty8LU1BSy2Sxuuukm5jjOzV/5yldeAvCRxZ7VEh8QiUQ6mgOZIAhAKQ1dKVTdQY6Pj0NVVSSTyXc4uWutkiRdVuuzTxAEcBwHMzMzIITg5ptvZn19fZueeOKJry4bAZqmdTSDC4IgkCRJu1J4xhjxfR+zs7Po6elZTDuuKnRz2zoJjLHLal0bXNfFzMwMFEXBli1bdF3XP75v3761y0IAY6wRBRJC4DhOuWk6rG9/EUopRkdHsWbNmsZ/rybgUiQ0wNeW2PVaW4Y3quM4uHjxIhRFwX333ZfUdf17y0KApmlZIURjBIMgsJuzQPWR8n0fvu8jFApdl7ovRUydhHq/9ev6bAEAtm0jn89D0zQkEok1jz322GUxQksICIVCXc0xAOe8kZSsOz5CCM6ePYurRWrXOvJXPPsd5rNUFLlz586EEOIfmu+1ggCiqmojCGrOBl3pBMvlMmKx2Ls/8CpCL9W++XOp0tbWBlmW+5vv3TABg4ODmUgk0giCahrQyMw2g7qW2P69lOYY4d2KpmmJu+++W6t/v+E4IJVKDcRiMak5CgTgA5erqG3b75rqCuDDRhkl5FFADjksoEgLKIoCbFTgw4MQAhJkKEKFLgyEWQQhGNCIDkkoEB4BhbykNnR1dRmKotwB4EBLCIhEIp2yLDfy9QAghOB1AHXvXCgUIMtyY5Q4AuTpHM7RcZyhozhOXsWr5AjyQQ6KJ0MJZEiBBCmQQDkFFRRE1MJsIiAIR0A5fBrAZz68iAe3zYNCVGxyt2LA34w13k3Iut0w3DZQXnXKmUwmxBjb0hIChBDkwIEDnyiXyw3PXicAaKg/AaremBCCS2wGZ9gIjrBf4Fn6FCpeGSErhJCrwfTC6HATUD0Vqq9AIjIYYaCEgYKC1HbyBASmi9MoVApIqkmoIRlQAUd2YMsOxpU3MKoMoWJUIEyC3c79+LBzO9Y4NyESjYBz3lGX4UY1QA2Hw5td14VhGO+I+YG3c3yMMbypDOM16Vf4ofR9hG0DYdtA3MnAsHUYjg6VagCnIKAwlTYoVIVEZUhEAgUDIdVnHX7rIF45/zJWGmvxR92fx1+PfB73rL0HwuNwHBsut1FWrWrVLLygPodnoj/Gfe5H0RPuRSCCfEsIePrppzP9/f0mpRSO4yASiVz2ezMhmqbhV/OHsJ/+BDErikgljIhtIGyHoQsdmhTCsenjOD1/Cp9e9ad4Y/4UNmU2oUPrqhJR0wYA2JEGeABccubxtbEvYmN6M3xP4Pnx53B7cifOe7PoSXZB9VQoftWUGGf4eeh/kC33IG9VGkdwb4gAzvnvx+NxalkWgiCAbdtQFAWcc9ZkDgCARCKBYFRACiTI9erLkAMZEpMhEQVr2/oQVUwMW68iE+5EUuuAIUWgUR0hqkNjOggIzHgC/eaHYHMLlcCCzS2UgwLu6r4H5aCE1ZFVIATwuVztw6/2J/ky5n67IJyC9tOWEBCPx+8hhNSFRrlchqZpoJRKQGPpKzjnhFKKZCkNV/Jq1YUju1ACByyo2nnCiKMz0gWVatBoCB4cFP0cbGKhRGTQmgZwEcAXPjzhwOUOHG7D5Q7awynYPAybV2AHFlzqwJFduJLb6NP4reENDQ1dbAkB4XC4d35+HvF4vHHuL5/PA0CqOSqra8PKoA8fGuvFmz2TWAjn4UoeHNmBYdswHBt2oEGlZShUhUwUyLTuCKs+gDZpVYAAgQjgCw8ed+EJF26NCIfYKGvWZX7AkR2sGe/E9Bn7fLMMN0SAZVn/WSwWP5dOpxvxd20pnHAc57JFiizL2HnLbhx/9gXIMwJ+B3C+fQHn4ucRcrVq9TSorgrNV6F4MmS3KjwjDOSKWUCAg4sqCR7z4EguHNWFLTuwFRuVWo3YOnrOpaFMC0zvXxDzI+5nW0bAd77zna/u3bv3M0EQSPXta9/3fU3TJM45giBoHIaUJKmaALHX4MWh/wA9SZFKdKAnuRI0rqFiurgUK+Bc4jwopw27ZVwCWyQO4LU4IKjHAaxqWh3FFBL5KLSFOPicg8LFOYzPHgP3fTivdS6cOTn5w5YR8I1vfGNy69atL5imuWtgYACcc9i27TLGJKB6AEIIAcdxoKoqJEnCx3btxen/fgVD6n7MzE5jdmEGlDFQRkEpQ6dmIBqOQQ3pkDQFVGGARAAGgNS2fQRAfAHhcXA3gFdxYVtlFEs5lK1pTAVvgdeO1fDAB/cD+G/EROmC/1dXynDDkeD+/fuf7O3tvbtYLEqRSARCCF5fkjZvUtR9xKpVq7DN3I3x/FHk2IWq8JSCMgpCGXzPQ7mcByEUhBKAkIbqV4uAEPV0GIfgAoJziEYeIAAPOHgQgAcBBOcIygSV1/Uzvz0+9Y9X4l/86MZ1lI6OjtORSGSXYRjdmUwGlUrFU1VVaV4c1VNVtcQINg1swfDBcYyTowi4VwUfcIga6Eb1AwR+dRQDv1Y9H4HvgfvVz/p3v/F79TceBIAQEAFQfC5RevOXM31Y5OzQDRMwPj7uR6NRa9u2bR8zDINSSrmqqo1p8EoSgGpU+OGB2/DGoQuY1oYRcL+hsiIIEDSNYOD7NSKuIMGrC98keO0kWb0IDhSfS9gLI5Xtdtk7txj+GyYAAEZGRk7ecccdHwGwpr29nciy3NgVWowEzjkMw8AtA7fj5IFzWAiNIaDVFbQQTSp9pUY011obUbWHd2AKygS5n5nl/Cn/7oWZ0rGlsLeEAACIRCJvbt++/dNtbW1MVVWyVKKzvnMshICu67jvro/izZ/Pww7KKCmzLcHivRUSCwf0yclf51ZWSs5V3zxrGQEnTpw498ADD2yTJOmmyclJVCqVxnsAS6W56ltev7vr9yDNtuH88SJcrQhPfm8vifg5huIh07p0lP3r+eHcLlzDkbmWEQAAlNJXIpHInkQiMRUOh51CoaCOjY1JU1NTsCwLhJB6qNyIEh3HgSRJWH/zh/Cx3Q+jeEJGbjQAKhLcUAFgVz/+y10C/40Y/NcT7sIvlKcmX52/rTxv//haMbf8sPSePXs+EYvFHslkMndms1mjs7Nzvr+/fyIWi5nFYjGTz+dDnHO0tbUhmUyKCxcukGKxCEopkskkMpmMMAzDHx4epv/27/9C35wZgcVzxA4s+MRGwAPAkwTlEhQRQtroEY/+wWfsu+66628PHz78xZ07d17XyfFle3Fy7969imVZt8qy/DuZTGZXNpu9JZvNyp2dnfOrV68+ZxiGadu2KUlSkE6n52zbvrSwsJDI5/OrLcuiqVSKJxKJiq7rQpZlSinlAJqP3RAAEEJUAJzmnD/BGNtPrrIRulh5394d3rNnj04pvT0Wi+3KZDK7MpnM5mw2Szdu3IhcLodcLpfP5XK/yeVyv6xUKq+1tbX98lOf+pQDoNP3/XZCyApCSCeAFKrH5XUAnhDiJ4yxnwNwrld44AN4ebpeHnzwwXYA9zz00ENyLpd7+dFHH31zsXZCCIK3cV55LVB9YeJ9feH6/1T5X6ovmGNWfu3DAAAAAElFTkSuQmCC 18 | 19 | 20 | -------------------------------------------------------------------------------- /Technology/tech/symbols/EEschema/MinedaSymbols.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # 0 5 | # 6 | DEF 0_MIN #GND 0 0 Y Y 1 F P 7 | F0 "#GND" 0 -100 50 H I C CNN 8 | F1 "0_MIN" 0 -50 50 H V C CNN 9 | F2 "" 150 0 50 H I C CNN 10 | F3 "" 150 0 50 H I C CNN 11 | DRAW 12 | P 4 0 1 0 -50 0 50 0 0 -50 -50 0 N 13 | X 0 1 0 0 0 L 35 35 1 1 W N 14 | ENDDRAW 15 | ENDDEF 16 | # 17 | # CAP 18 | # 19 | DEF CAP_MIN C 0 40 N Y 1 F N 20 | F0 "C" 100 0 50 H V L CNN 21 | F1 "CAP_MIN" 100 -100 50 H V L CNN 22 | F2 "" -50 70 50 H I C CNN 23 | F3 "" -50 70 50 H I C CNN 24 | F4 "C" 100 -400 50 H I L CNN "Spice_Primitive" 25 | F5 "C" 100 -200 50 H V L CNN "Spice_Model" 26 | F6 "Y" 100 -300 50 H I L CNN "Spice_Netlist_Enabled" 27 | DRAW 28 | P 2 0 1 0 -45 -100 40 -100 N 29 | P 2 0 1 0 0 -200 0 -135 N 30 | P 4 0 1 0 50 -120 50 -135 -55 -135 -55 -120 N 31 | X ~ 1 0 0 100 D 35 35 1 1 P 32 | X ~ 2 0 -300 100 U 35 35 1 1 P 33 | ENDDRAW 34 | ENDDEF 35 | # 36 | # HR_POLY 37 | # 38 | DEF HR_POLY_MIN R 0 0 N Y 1 F N 39 | F0 "R" 125 50 50 H V L CNN 40 | F1 "HR_POLY_MIN" 125 -50 50 H V L CNN 41 | F2 "" 0 0 50 H I C CNN 42 | F3 "" 0 0 50 H I C CNN 43 | F4 "R" 125 -350 50 H I L CNN "Spice_Primitive" 44 | F5 "R" 125 -150 50 H V L CNN "Spice_Model" 45 | F6 "Y" 125 -250 50 H I L CNN "Spice_Netlist_Enabled" 46 | DRAW 47 | P 2 0 1 0 -50 -225 50 -190 N 48 | P 2 0 1 0 -50 -165 50 -130 N 49 | P 2 0 1 0 -50 -105 50 -75 N 50 | P 2 0 1 0 0 -250 0 -240 N 51 | P 2 0 1 0 0 -240 -50 -225 N 52 | P 2 0 1 0 0 -205 0 -90 N 53 | P 2 0 1 0 0 -55 0 -50 N 54 | P 2 0 1 0 50 -190 -50 -165 N 55 | P 2 0 1 0 50 -130 -50 -105 N 56 | P 2 0 1 0 50 -75 0 -55 N 57 | X ~ 1 0 0 50 D 35 35 1 1 P 58 | X ~ 2 0 -300 50 U 35 35 1 1 P 59 | ENDDRAW 60 | ENDDEF 61 | # 62 | # NDIO 63 | # 64 | DEF NDIO_MIN D 0 0 N Y 1 F N 65 | F0 "D" 150 50 50 H V L CNN 66 | F1 "NDIO_MIN" 150 -50 50 H V L CNN 67 | F2 "" 0 0 50 H I C CNN 68 | F3 "" 0 0 50 H I C CNN 69 | F4 "D" 150 -350 50 H I L CNN "Spice_Primitive" 70 | F5 "NDIO" 150 -150 50 H I L CNN "Spice_Model" 71 | F6 "Y" 150 -250 50 H I L CNN "Spice_Netlist_Enabled" 72 | DRAW 73 | P 2 0 1 0 -50 -175 50 -175 N 74 | P 2 0 1 0 -50 -100 50 -100 N 75 | P 2 0 1 0 0 -175 -50 -100 N 76 | P 2 0 1 0 0 -175 0 -200 N 77 | P 2 0 1 0 50 -100 0 -175 N 78 | X A 1 0 0 100 D 35 35 1 1 P 79 | X K 2 0 -300 100 U 35 35 1 1 P 80 | ENDDRAW 81 | ENDDEF 82 | # 83 | # NMOS_ESD 84 | # 85 | DEF NMOS_ESD_MIN U 0 0 N Y 1 F N 86 | F0 "U" 450 -50 50 H V L CNN 87 | F1 "NMOS_ESD_MIN" 650 -150 50 H V C CNN 88 | F2 "" 0 0 50 H I C CNN 89 | F3 "" 0 0 50 H I C CNN 90 | DRAW 91 | P 2 0 1 0 0 -600 0 0 N 92 | P 2 0 1 0 0 0 400 0 N 93 | P 2 0 1 0 100 -400 300 -400 N 94 | P 2 0 1 0 100 -200 300 -200 N 95 | P 2 0 1 0 200 -400 200 -500 N 96 | P 2 0 1 0 200 -200 100 -400 N 97 | P 2 0 1 0 200 -100 200 -200 N 98 | P 2 0 1 0 300 -400 200 -200 N 99 | P 2 0 1 0 400 -600 0 -600 N 100 | P 2 0 1 0 400 0 400 -600 N 101 | X VSS 1 200 -600 100 U 35 35 1 1 P 102 | X PAD 2 200 0 100 D 35 35 1 1 P 103 | ENDDRAW 104 | ENDDEF 105 | # 106 | # PDIO 107 | # 108 | DEF PDIO_MIN D 0 0 N Y 1 F N 109 | F0 "D" 150 50 50 H V L CNN 110 | F1 "PDIO_MIN" 150 -50 50 H V L CNN 111 | F2 "" 0 0 50 H I C CNN 112 | F3 "" 0 0 50 H I C CNN 113 | F4 "D" 150 -350 50 H I L CNN "Spice_Primitive" 114 | F5 "PDIO" 150 -150 50 H I L CNN "Spice_Model" 115 | F6 "Y" 150 -250 50 H I L CNN "Spice_Netlist_Enabled" 116 | DRAW 117 | P 2 0 1 0 -50 -175 50 -175 N 118 | P 2 0 1 0 -50 -100 50 -100 N 119 | P 2 0 1 0 0 -200 0 -175 N 120 | P 2 0 1 0 0 -175 -50 -100 N 121 | P 2 0 1 0 50 -100 0 -175 N 122 | X A 1 0 0 100 D 35 35 1 1 P 123 | X K 2 0 -300 100 U 35 35 1 1 P 124 | ENDDRAW 125 | ENDDEF 126 | # 127 | # PMOS_MIN 128 | # 129 | DEF PMOS_MIN M 0 0 N Y 1 F N 130 | F0 "M" 350 200 50 H V L CNN 131 | F1 "PMOS_MIN" 350 100 50 H I L CNN 132 | F2 "" 0 0 50 H I C CNN 133 | F3 "" 0 0 50 H I C CNN 134 | F4 "M" 350 -200 50 H I L CNN "Spice_Primitive" 135 | F5 "Pch l=10u w=40u" 350 0 50 H V L CNN "Spice_Model" 136 | F6 "Y" 350 -100 50 H I L CNN "Spice_Netlist_Enabled" 137 | DRAW 138 | P 2 0 1 0 0 0 75 0 N 139 | P 2 0 1 0 75 75 75 -75 N 140 | P 2 0 1 0 100 -100 100 100 N 141 | P 2 0 1 0 100 -65 200 -65 N 142 | P 2 0 1 0 100 0 200 0 N 143 | P 2 0 1 0 100 70 145 90 N 144 | P 2 0 1 0 145 55 100 70 N 145 | P 2 0 1 0 145 55 145 90 N 146 | P 2 0 1 0 145 70 200 70 N 147 | P 2 0 1 0 200 -65 200 -150 N 148 | P 2 0 1 0 200 70 200 150 N 149 | X D 1 200 -150 50 U 35 35 1 1 P N 150 | X G 2 0 0 50 R 35 35 1 1 P N 151 | X S 3 200 150 50 D 35 35 1 1 P N 152 | X B 4 200 0 100 L 35 35 1 1 P N 153 | ENDDRAW 154 | ENDDEF 155 | # 156 | # PMOS_ESD 157 | # 158 | DEF PMOS_ESD_MIN U 0 0 N Y 1 F N 159 | F0 "U" 450 -50 50 H V L CNN 160 | F1 "PMOS_ESD_MIN" 450 -150 50 H V L CNN 161 | F2 "" 0 0 50 H I C CNN 162 | F3 "" 0 0 50 H I C CNN 163 | DRAW 164 | P 2 0 1 0 0 -600 0 0 N 165 | P 2 0 1 0 0 0 400 0 N 166 | P 2 0 1 0 100 -400 300 -400 N 167 | P 2 0 1 0 100 -200 300 -200 N 168 | P 2 0 1 0 200 -400 200 -500 N 169 | P 2 0 1 0 200 -200 100 -400 N 170 | P 2 0 1 0 200 -100 200 -200 N 171 | P 2 0 1 0 300 -400 200 -200 N 172 | P 2 0 1 0 400 -600 0 -600 N 173 | P 2 0 1 0 400 0 400 -600 N 174 | X PAD 1 200 -600 100 U 35 35 1 1 P 175 | X VDD 2 200 0 100 D 35 35 1 1 P 176 | ENDDRAW 177 | ENDDEF 178 | # 179 | # RES 180 | # 181 | DEF RES_MIN R 0 0 N Y 1 F N 182 | F0 "R" 150 50 50 H V L CNN 183 | F1 "RES_MIN" 150 -50 50 H V L CNN 184 | F2 "" 50 0 50 H I C CNN 185 | F3 "" 50 0 50 H I C CNN 186 | F4 "R" 150 -350 50 H I L CNN "Spice_Primitive" 187 | F5 "R" 150 -150 50 H V L CNN "Spice_Model" 188 | F6 "Y" 150 -250 50 H I L CNN "Spice_Netlist_Enabled" 189 | DRAW 190 | P 2 0 1 0 -50 -225 50 -190 N 191 | P 2 0 1 0 -50 -165 50 -130 N 192 | P 2 0 1 0 -50 -105 50 -75 N 193 | P 2 0 1 0 0 -250 0 -240 N 194 | P 2 0 1 0 0 -240 -50 -225 N 195 | P 2 0 1 0 0 -55 0 -50 N 196 | P 2 0 1 0 50 -190 -50 -165 N 197 | P 2 0 1 0 50 -130 -50 -105 N 198 | P 2 0 1 0 50 -75 0 -55 N 199 | X ~ 1 0 0 50 D 35 35 1 1 P 200 | X ~ 2 0 -300 50 U 35 35 1 1 P 201 | ENDDRAW 202 | ENDDEF 203 | # 204 | # R_POLY 205 | # 206 | DEF R_POLY_MIN R 0 0 N Y 1 F N 207 | F0 "R" 150 50 50 H V L CNN 208 | F1 "R_POLY_MIN" 150 -50 50 H V L CNN 209 | F2 "" 0 0 50 H I C CNN 210 | F3 "" 0 0 50 H I C CNN 211 | F4 "R" 150 -350 50 H I L CNN "Spice_Primitive" 212 | F5 "R" 150 -150 50 H V L CNN "Spice_Model" 213 | F6 "Y" 150 -250 50 H I L CNN "Spice_Netlist_Enabled" 214 | DRAW 215 | P 2 0 1 0 -50 -225 50 -190 N 216 | P 2 0 1 0 -50 -165 50 -130 N 217 | P 2 0 1 0 -50 -105 50 -75 N 218 | P 2 0 1 0 0 -300 0 -240 N 219 | P 2 0 1 0 0 -240 -50 -225 N 220 | P 2 0 1 0 0 -240 0 -210 N 221 | P 2 0 1 0 0 -55 0 -90 N 222 | P 2 0 1 0 0 -55 0 0 N 223 | P 2 0 1 0 50 -190 -50 -165 N 224 | P 2 0 1 0 50 -130 -50 -105 N 225 | P 2 0 1 0 50 -75 0 -55 N 226 | X ~ 1 0 0 50 D 35 35 1 1 P 227 | X ~ 2 0 -300 50 U 35 35 1 1 P 228 | ENDDRAW 229 | ENDDEF 230 | # 231 | # NMOS_MIN 232 | # 233 | DEF NMOS_MIN M 0 0 N Y 1 F N 234 | F0 "M" 350 200 50 H V L CNN 235 | F1 "NMOS_MIN" 350 100 50 H I L CNN 236 | F2 "" 0 0 50 H I C CNN 237 | F3 "" 0 0 50 H I C CNN 238 | F4 "M" 350 -200 50 H I L CNN "Spice_Primitive" 239 | F5 "Nch l=10u w=20u" 350 0 50 H V L CNN "Spice_Model" 240 | F6 "Y" 350 -100 50 H I L CNN "Spice_Netlist_Enabled" 241 | DRAW 242 | P 2 0 1 0 0 0 75 0 N 243 | P 2 0 1 0 75 75 75 -75 N 244 | P 2 0 1 0 100 -100 100 100 N 245 | P 2 0 1 0 100 -65 155 -65 N 246 | P 2 0 1 0 100 0 200 0 N 247 | P 2 0 1 0 100 70 200 70 N 248 | P 2 0 1 0 155 -85 155 -50 N 249 | P 2 0 1 0 155 -50 200 -65 N 250 | P 2 0 1 0 200 -65 155 -85 N 251 | P 2 0 1 0 200 -65 200 -150 N 252 | P 2 0 1 0 200 70 200 150 N 253 | X D 1 200 150 50 D 35 35 1 1 P 254 | X G 2 0 0 50 R 35 35 1 1 P 255 | X S 3 200 -150 50 U 35 35 1 1 P 256 | X B 4 200 0 100 L 35 35 1 1 P 257 | ENDDRAW 258 | ENDDEF 259 | # 260 | #End Library 261 | -------------------------------------------------------------------------------- /Technology/tech/drc/drc.lydrc: -------------------------------------------------------------------------------- 1 | 2 | 3 | DRC for ICPS2023_5 4 | 5 | drc 6 | 7 | 8 | 9 | false 10 | false 11 | 0 12 | 13 | true 14 | drc_scripts 15 | tools_menu.drc.end 16 | dsl 17 | drc-dsl-xml 18 | =begin 19 | * Copyright 2023 minimalFab Promoting Organization 20 | * 21 | * Licensed under the Apache License, Version 2.0 (the "License"); 22 | * you may not use this file except in compliance with the License. 23 | * You may obtain a copy of the License at 24 | * 25 | * http://www.apache.org/licenses/LICENSE-2.0 26 | * 27 | * Unless required by applicable law or agreed to in writing, software 28 | * distributed under the License is distributed on an "AS IS" BASIS, 29 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | * See the License for the specific language governing permissions and 31 | * limitations under the License 32 | =end 33 | # Mineda2022_6 Rule for ICPS SOI CMOS process 34 | ## v0.1: based on Mineda2022_2 ver 0.55 35 | ## v0.32 Nov. 7 2024 by S. Moriyama 36 | report("Output database") 37 | 38 | ### layout/Production Check input(4,0) SOI for Production 39 | 40 | soi = input(4, 0) 41 | exclude = input(63, 63) 42 | # Get raw layers 43 | ## layout data input 44 | if soi.area == 0 then 45 | product = false 46 | puts 'Layout DRC Start' 47 | mask = input(20,0) 48 | diff = input(3, 0).not(exclude) - mask 49 | tin = input(5, 0).not(exclude).raw - mask 50 | cnt1 = input(7, 0).not(exclude) - mask 51 | ml1 = input(8, 0).not(exclude) - mask 52 | via1 = input(9, 0).not(exclude) - mask 53 | ml2 = input(10, 0).not(exclude) - mask 54 | text = input(13, 0).not(exclude) - mask 55 | frame = input(14, 0).not(exclude) - mask 56 | res = input(15, 0).not(exclude) - mask 57 | cap = input(16, 0).not(exclude) - mask 58 | dio = input(17, 0).not(exclude) - mask 59 | parea = input(18, 0).not(exclude) - mask 60 | narea = input(19, 0).not(exclude) - mask 61 | pad = input(50, 0).not(exclude) - mask 62 | cnt = cnt1 - pad 63 | 64 | pdiff = diff & parea - res 65 | ndiff = diff & narea - res 66 | 67 | nmos = ndiff & tin 68 | pmos = pdiff & tin 69 | str = 'Diff' 70 | # tin_gate = tin.interacting(diff) - cap 71 | tin_gate = tin.interacting(pdiff) + tin.interacting(ndiff) - cap # for Mineda2022_2 72 | tin_rest = tin - tin_gate 73 | bb = (diff + tin_gate ).extents 74 | tin_gate_enlarged = tin_gate.sized(2.0.um) & bb 75 | tinA = tin+ tin_gate_enlarged 76 | # tin_gate_enlarged.output("enlarged TiN") 77 | 78 | else # for Product Data input 79 | product = true 80 | puts 'PRODUCT DRC Start' 81 | mask = input(20,0) 82 | diff = input(4,0).not(exclude) - mask ## = SOI 83 | parea = input(2,0).not(exclude) - mask ## = P_plus 84 | narea = input(3,0).not(exclude) - mask ## = N_plus 85 | tin = input(5,0).not(exclude) - mask 86 | cnt = input(6,0).not(exclude) - mask 87 | ml1 = input(7,0).not(exclude) - mask 88 | via1 = input(8,0).not(exclude) - mask 89 | ml2 = input(9,0).not(exclude) - mask 90 | 91 | pdiff = diff & parea 92 | ndiff = diff & narea 93 | 94 | pmos = diff - parea & tin 95 | # pmos_a = pmos.edge 96 | # pmos_b = pmos.edge 97 | nmos = diff - narea & tin 98 | str = 'SOI' 99 | end 100 | 101 | puts 'Check Diffusion' # both layout and product 102 | #layout str='Diff' // process str = 'SOI' 103 | r_diff_w = diff.width(6.0.um) ;r_diff_w.output("(#{str}-A)#{str} width <6") 104 | r_diff_s = diff.space(4.0.um) ;r_diff_s.output("(#{str}-B)#{str} space <4") 105 | r_parea_diff_en = parea.enclosing(diff,2.0.um);r_parea_diff_en.output("(#{str}-C)Parea enclosing #{str} <2") 106 | r_narea_diff_en = narea.enclosing(diff,2.0.um);r_narea_diff_en.output("(#{str}-D)Narea enclosing #{str} <2") 107 | r_pdiff_ndiff_s = pdiff.separation(ndiff,4.0.um);r_pdiff_ndiff_s.output("(#{str}-E)Pdiff Ndiff space<4") 108 | r_parea_narea_and = parea & narea;r_parea_narea_and.output("(#{str}-F)Parea Narea butting") 109 | r_parea_ndiff_s = parea.separation(ndiff,5.0.um);r_parea_ndiff_s.output("(#{str}-G)Parea Ndiff space<5") 110 | r_narea_pdiff_s = narea.separation(pdiff,5.0.um);r_narea_pdiff_s.output("(#{str}-H)Narea Pdiff space<5") 111 | 112 | cnt_via = cnt & tin & ml1 - diff 113 | 114 | puts 'Check TiN & Cnt' # both layout and product 115 | unless product 116 | r_tin_w = tinA.width(6.0.um);r_tin_w.output("(TiN-A)TiN width < 6") 117 | r_tin_s = tinA.space(4.0.um);r_tin_s.output("(TiN-B)TiN space <4") 118 | r_tin_cnt_en = tinA.enclosing(cnt,2.0.um);r_tin_cnt_en.output("(TiN-C)TiN enclosing Cnt < 2") 119 | r_pdiff_tin_ext = tinA.enclosing((pdiff ),4.0.um);r_pdiff_tin_ext.output("(TiN-D)TIN extension Pdiff <4") 120 | r_ndiff_tin_ext = tinA.enclosing((ndiff ),4.0.um);r_ndiff_tin_ext.output("(TiN-E)TIN extension Ndiff <4") 121 | end 122 | r_cnt_w = cnt.width(4.0.um);r_cnt_w.output("(CNT-G)Cnt width <4") 123 | r_cnt_s = cnt.space(4.0.um);r_cnt_s.output("(CNT-H)Cnt space <4") 124 | r_diff_cnt_en = diff.enclosing(cnt,2.0.um);r_diff_cnt_en.output("(CNT-I)Diff enclosing Cnt <2") 125 | r_cnt_fix = cnt_via.without_perimeter(20.0.um);r_cnt_fix.output("(CNT-J)CNT-Via 5um Fixed size") 126 | 127 | m1_via = via1 & ml1 & ml2 128 | 129 | puts 'Check Metal/Metal2 & Cont & Via1' #both layout and product 130 | r_ml1_w = ml1.width(6.0.um);r_ml1_w.output("(ML1-A)Ml1 width <6") 131 | r_ml1_s = ml1.space(4.0.um); r_ml1_s.output("(ML1-B)Ml1 space < 4") 132 | r_ml1_cnt_en = ml1.enclosing(cnt,2.0.um);r_ml1_cnt_en.output("(ML1-C)Ml1 enclosing Cnt <2") 133 | r_via1_w = via1.width(4.0.um);r_via1_w.output("(VIA1-D)Via1 width < 4") 134 | r_via1_s = via1.space(4.0.um);r_via1_w.output("(VIA1-E)Via1 space < 4") 135 | r_ml1_via1_en = ml1.enclosing(via1,2.0.um);r_ml1_via1_en.output("(VIA1-F)Ml1 enclosing Via1 < 2") 136 | r_via_fix = m1_via.without_perimeter(20.0.um);r_via_fix.output("(VIA1-G)M1Via 5um Fixed Size") 137 | r_ml2_w = ml2.width(6.0.um);r_ml2_w.output("(ML2-H)Ml2 width < 6") 138 | r_ml2_s = ml2.space(6.um); r_ml2_s.output("(ML2-I)Ml2 space < 6") 139 | r_ml2_via1_en = ml2.enclosing(via1,2.0.um);r_ml2_via1_en.output("(ML2-J)Ml2 enclosing Via1 < 2") 140 | 141 | r_pdiff_s = pdiff.space(5.0.um);r_pdiff_s.output('(PMOS-A)Pdiff space <5') 142 | r_ndiff_s = ndiff.space(5.0.um);r_ndiff_s.output('(NMOS-D)Ndiff space <5') 143 | 144 | if product == true then ## for product 145 | puts 'Check MOS Structure' 146 | # r_parea_pdiff_en =parea.enclosing(pdiff,2.0.um);r_parea_pdiff_en.output("(PMOS)Parea enclosing Pdiff <2") 147 | r_tin_pdiff_en = (tin & pdiff).width(2.0.um);r_tin_pdiff_en.output('(PMOS-B) TiN overlapping Pdiff <2') 148 | # r_tin_pmos_en = tin.enclosing(pmos,6.0.um);r_tin_pmos_en.output('(PMOS-C)TiN extend PMOS <6') 149 | # r_narea_ndiff_en =narea.enclosing(ndiff,2.0.um);r_narea_ndiff_en.output("(NMOS)Narea enclosing Ndiff <2") 150 | r_tin_ndiff_en = (tin & ndiff).width(2.0.um);r_tin_ndiff_en.output('(NMOS-E) TiN overlapping Ndiff <2') 151 | # r_tin_nmos_en = tin.enclosing(nmos,6.0.um);r_tin_nmos_en.output('(NMOS-F)TiN extend NMOS <6') 152 | end 153 | 154 | puts "DRC Finished" 155 | 156 | #puts 'Check stand-alone Cont/Via' 157 | #sacnt = cnt.outside(dmcnt) 158 | #sacnt.output("Stand alone Cont") 159 | # SAvia1 = geomAnd(VIA1, geomNot(DM_via1)) => 160 | 161 | 162 | -------------------------------------------------------------------------------- /Technology/tech/YSS-SOI-CMOS_Xsection.lyp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | #ff00ff 5 | #ff00ff 6 | 0 7 | 0 8 | I1 9 | 10 | true 11 | true 12 | false 13 | 14 | false 15 | false 16 | 0 17 | SUB 18 | 280/0@1 19 | 20 | 21 | #8000ff 22 | #8000ff 23 | 0 24 | 0 25 | I0 26 | 27 | true 28 | true 29 | false 30 | 1 31 | false 32 | false 33 | 0 34 | BOX 35 | 282/0@1 36 | 37 | 38 | #80a8ff 39 | #80a8ff 40 | 0 41 | 0 42 | I0 43 | 44 | true 45 | true 46 | false 47 | 1 48 | false 49 | false 50 | 0 51 | SOI 52 | 284/0@1 53 | 54 | 55 | #c080ff 56 | #c080ff 57 | 0 58 | 0 59 | I9 60 | 61 | true 62 | true 63 | false 64 | 1 65 | false 66 | false 67 | 0 68 | 69 | 'pdiff ' 290/0@1 70 | 71 | 72 | #8086ff 73 | #8086ff 74 | 0 75 | 0 76 | I5 77 | 78 | true 79 | true 80 | false 81 | 1 82 | false 83 | false 84 | 0 85 | 86 | 'ndiff ' 292/0@1 87 | 88 | 89 | #ffffff 90 | #ffffff 91 | 0 92 | 0 93 | I0 94 | 95 | true 96 | true 97 | false 98 | 1 99 | false 100 | false 101 | 0 102 | gox 103 | 300/0@1 104 | 105 | 106 | #ddff00 107 | #ddff00 108 | 0 109 | 0 110 | I0 111 | 112 | true 113 | true 114 | false 115 | 1 116 | false 117 | false 118 | 0 119 | TiN 120 | 301/0@1 121 | 122 | 123 | #ddff00 124 | #f3ff80 125 | 0 126 | 0 127 | I9 128 | 129 | true 130 | true 131 | false 132 | 1 133 | false 134 | false 135 | 0 136 | TEOS1 137 | 302/0@1 138 | 139 | 140 | #0000ff 141 | #0000ff 142 | 0 143 | 0 144 | I0 145 | 146 | true 147 | true 148 | false 149 | 1 150 | false 151 | false 152 | 0 153 | Metal1 154 | 305/0@1 155 | 156 | 157 | #91ff00 158 | #91ff00 159 | 0 160 | 0 161 | I5 162 | 163 | true 164 | true 165 | false 166 | 1 167 | false 168 | false 169 | 0 170 | TEOS 171 | 310/0@1 172 | 173 | 174 | #ff00ff 175 | #ff00ff 176 | 0 177 | 0 178 | I0 179 | 180 | true 181 | true 182 | false 183 | 1 184 | false 185 | false 186 | 0 187 | Metal2 188 | 400/0@1 189 | 190 | 191 | 192 | 193 | .................... 194 | .................... 195 | .................... 196 | .................... 197 | .................... 198 | .................... 199 | .................... 200 | .................... 201 | .................... 202 | .................... 203 | .................... 204 | .................... 205 | .................... 206 | .................... 207 | ...**............... 208 | ...**............... 209 | .................... 210 | .................... 211 | .................... 212 | .................... 213 | 214 | 1 215 | dots 4 216 | 217 | 218 | 219 | *..............................* 220 | .*............................*. 221 | ..*..........................*.. 222 | ...*........................*... 223 | ....*......................*.... 224 | .....*....................*..... 225 | ......*..................*...... 226 | .......*................*....... 227 | ........*..............*........ 228 | .........*............*......... 229 | ..........*..........*.......... 230 | ...........*........*........... 231 | ............*......*............ 232 | .............*....*............. 233 | ..............*..*.............. 234 | ...............**............... 235 | ...............**............... 236 | ..............*..*.............. 237 | .............*....*............. 238 | ............*......*............ 239 | ...........*........*........... 240 | ..........*..........*.......... 241 | .........*............*......... 242 | ........*..............*........ 243 | .......*................*....... 244 | ......*..................*...... 245 | .....*....................*..... 246 | ....*......................*.... 247 | ...*........................*... 248 | ..*..........................*.. 249 | .*............................*. 250 | *..............................* 251 | 252 | 2 253 | cross 254 | 255 | 256 | -------------------------------------------------------------------------------- /Technology/tech/models/MF_CMOS20240109.txt: -------------------------------------------------------------------------------- 1 | * Copyright 2023 minimalFab Promoting Organization 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License 14 | 15 | * SPICE file 16 | * ICPS2023Ver1.01 17 | * Revised 2024.1.9 18 | 19 | * 20 | .MODEL mf_nmos NMOS 21 | + TNOM = 25 22 | + VERSION = 3.3.0 23 | + LEVEL = 8 24 | + PARAMCHK = 1 25 | + MOBMOD = 1 26 | + CAPMOD = 3 27 | *+ FNOIMOD = 1 28 | *+ SOIMOD = 3 29 | * XVERIFIER_OPTIMIZE TOX 1e-09 3 1.5e-08 + TOX = XVERIFIER_VALUE 30 | + TOX = 1.5e-08 31 | + XJ = 1.5E-007 32 | + NCH = 1.7E+017 33 | * XVERIFIER_OPTIMIZE VTH0 0 3 0.20809 + VTH0 = XVERIFIER_VALUE 34 | + VTH0 = 0.20809 35 | * XVERIFIER_OPTIMIZE K1 0 1 0.5 + K1 = XVERIFIER_VALUE 36 | + K1 = 0.5 37 | * XVERIFIER_OPTIMIZE K2 0 1 0 + K2 = XVERIFIER_VALUE 38 | + K2 = 0 39 | + K3 = 80 40 | + K3B = 0 41 | + W0 = 2.5E-006 42 | + NLX = 1.74E-007 43 | + VBM = -3.0 44 | + DVT0 = 2.2 45 | + DVT1 = 0.53 46 | + DVT2 = -0.032 47 | + DVT0W = 0 48 | + DVT1W = 5.3E+006 49 | + DVT2W = -0.032 50 | * XVERIFIER_OPTIMIZE U0 100 2000 670 + U0 = XVERIFIER_VALUE 51 | + U0 = 670 52 | * XVERIFIER_OPTIMIZE UA -3e-08 1e-08 2.25e-09 + UA = XVERIFIER_VALUE 53 | + UA = 2.25e-09 54 | * XVERIFIER_OPTIMIZE UB -3e-20 1e-16 5.87e-19 + UB = XVERIFIER_VALUE 55 | + UB = 5.87e-19 56 | * XVERIFIER_OPTIMIZE UC -1e-10 -1e-12 -4.65e-11 + UC = XVERIFIER_VALUE 57 | + UC = -4.65e-11 58 | * XVERIFIER_OPTIMIZE VSAT 10000 1000000 800755.2814 + VSAT = XVERIFIER_VALUE 59 | + VSAT = 800755.2814 60 | * XVERIFIER_OPTIMIZE A0 0 3 1.1164 + A0 = XVERIFIER_VALUE 61 | + A0 = 1.1164 62 | * XVERIFIER_OPTIMIZE AGS -0.1 3 0.2656 + AGS = XVERIFIER_VALUE 63 | + AGS = 0.2656 64 | + B0 = 0 65 | + B1 = 0 66 | + KETA = -0.047 67 | + A1 = 0 68 | * XVERIFIER_OPTIMIZE A2 0.2 1 0.20782 + A2 = XVERIFIER_VALUE 69 | + A2 = 0.20782 70 | * XVERIFIER_OPTIMIZE RDSW 0 1000000 0 + RDSW = XVERIFIER_VALUE 71 | + RDSW = 0 72 | + PRWB = 0 73 | * XVERIFIER_OPTIMIZE PRWG 0 100 58.7371 + PRWG = XVERIFIER_VALUE 74 | + PRWG = 58.7371 75 | + WR = 1 76 | + WINT = 0 77 | + LINT = 0 78 | + DWG = 0 79 | + DWB = 0 80 | * XVERIFIER_OPTIMIZE VOFF -0.5 0.5 -0.17284 + VOFF = XVERIFIER_VALUE 81 | + VOFF = -0.17284 82 | * XVERIFIER_OPTIMIZE NFACTOR 0.5 10 0.99099 + NFACTOR = XVERIFIER_VALUE 83 | + NFACTOR = 0.99099 84 | + ETA0 = 0.08 85 | + ETAB = -0.07 86 | + DSUB = 0.56 87 | + CIT = 0 88 | * XVERIFIER_OPTIMIZE CDSC 1e-05 0.01 0.00021654 + CDSC = XVERIFIER_VALUE 89 | + CDSC = 0.00021654 90 | + CDSCB = 0 91 | * XVERIFIER_OPTIMIZE CDSCD 0 1 0.38995 + CDSCD = XVERIFIER_VALUE 92 | + CDSCD = 0.38995 93 | * XVERIFIER_OPTIMIZE PCLM 0.1 3 2.9694 + PCLM = XVERIFIER_VALUE 94 | + PCLM = 2.9694 95 | + PDIBLC1 = 0.39 96 | * XVERIFIER_OPTIMIZE PDIBLC2 1e-06 0.1 0.0021218 + PDIBLC2 = XVERIFIER_VALUE 97 | + PDIBLC2 = 0.0021218 98 | + PDIBLCB = 0 99 | + DROUT = 0.56 100 | *****+ PSCBE1 = 4.24E+008 101 | *****+ PSCBE2 = 1.0E-005 102 | + PVAG = 0 103 | * XVERIFIER_OPTIMIZE DELTA 0.001 10 0.045152 + DELTA = XVERIFIER_VALUE 104 | + DELTA = 0.045152 105 | + NGATE = 0 106 | + ALPHA0 = 0 107 | *****+ ALPHA1 = 0 108 | + BETA0 = 30 109 | + RSH = 0 110 | *****+ JSSW = 0 111 | *****+ JS = 1.0E-004 112 | *****+ IJTH = 0.1 113 | + XPART = 1 114 | + CGSO = 5.3E-9 115 | *****+ CGSO = 8.8E-9 116 | + CGDO = 5.3E-9 117 | *****+ CGDO = 8.8E-9 118 | + CGSL = 0 119 | + CGDL = 0 120 | *****+ CGBO = 0 121 | *****+ CJ = 5.0E-004 122 | *****+ MJ = 0.5 123 | *****+ MJSW = 0.33 124 | *****+ CJSW = 5.0E-010 125 | + CJSWG = 5.0E-010 126 | + MJSWG = 0.33 127 | *****+ PBSW = 1 128 | *****+ PB = 1 129 | + PBSWG = 1 130 | + CKAPPA = 0.6 131 | + CF = 0 132 | + CLC = 1.0E-007 133 | + CLE = 0.6 134 | + DLC = 0 135 | + DWC = 0 136 | *****+ VFBCV = -1 137 | + NOFF = 1 138 | *****+ VOFFCV = 0 139 | + ACDE = 1 140 | + MOIN = 15 141 | + UTE = -1.5 142 | + KT1 = -0.11 143 | + KT1L = 0 144 | + KT2 = 0.022 145 | + UA1 = 4.31E-009 146 | + UB1 = -7.61E-018 147 | + UC1 = -5.6E-011 148 | + AT = 3.3E+004 149 | + PRT = 0 150 | *****+ NJ = 1 151 | *****+ XTI = 3 152 | *****+ TPB = 0 153 | *****+ TPBSW = 0 154 | *****+ TPBSWG = 0 155 | *****+ TCJ = 0 156 | *****+ TCJSW = 0 157 | + TCJSWG = 0 158 | + AF = 1 159 | + EF = 1 160 | + KF = 0 161 | 162 | * 163 | .MODEL mf_pmos PMOS 164 | + TNOM = 25 165 | + LEVEL = 8 166 | ******************+ LEVEL = 9 167 | + VERSION = 3.3.0 168 | + PARAMCHK = 1 169 | + MOBMOD = 1 170 | + CAPMOD = 3 171 | * XVERIFIER_OPTIMIZE TOX 1e-09 3 1.5e-08 + TOX = XVERIFIER_VALUE 172 | + TOX = 1.5e-08 173 | + XJ = 1.5E-007 174 | + NCH = 1.7E+017 175 | * XVERIFIER_OPTIMIZE VTH0 -3 0 -0.4348 + VTH0 = XVERIFIER_VALUE 176 | + VTH0 = -0.4348 177 | * XVERIFIER_OPTIMIZE K1 0 1 0.5 + K1 = XVERIFIER_VALUE 178 | + K1 = 0.5 179 | * XVERIFIER_OPTIMIZE K2 0 1 0 + K2 = XVERIFIER_VALUE 180 | + K2 = 0 181 | + K3 = 80 182 | + K3B = 0 183 | + W0 = 2.5E-006 184 | + NLX = 1.74E-007 185 | + VBM = -3.0 186 | + DVT0 = 2.2 187 | + DVT1 = 0.53 188 | + DVT2 = -0.032 189 | + DVT0W = 0 190 | + DVT1W = 5.3E+006 191 | + DVT2W = -0.032 192 | * XVERIFIER_OPTIMIZE U0 10 2000 80.6055 + U0 = XVERIFIER_VALUE 193 | + U0 = 80.6055 194 | * XVERIFIER_OPTIMIZE UA -3e-08 1e-08 -5.7647e-10 + UA = XVERIFIER_VALUE 195 | + UA = -5.7647e-10 196 | * XVERIFIER_OPTIMIZE UB -3e-20 1e-16 5.0269e-19 + UB = XVERIFIER_VALUE 197 | + UB = 5.0269e-19 198 | * XVERIFIER_OPTIMIZE UC -1e-10 -1e-12 -4.65e-11 + UC = XVERIFIER_VALUE 199 | + UC = -4.65e-11 200 | * XVERIFIER_OPTIMIZE VSAT 10000 1000000 999949 + VSAT = XVERIFIER_VALUE 201 | + VSAT = 999949 202 | * XVERIFIER_OPTIMIZE A0 0 3 0.52732 + A0 = XVERIFIER_VALUE 203 | + A0 = 0.52732 204 | * XVERIFIER_OPTIMIZE AGS -0.1 3 0.1971 + AGS = XVERIFIER_VALUE 205 | + AGS = 0.1971 206 | * XVERIFIER_OPTIMIZE B0 0 0.001 3.8867e-07 + B0 = XVERIFIER_VALUE 207 | + B0 = 3.8867e-07 208 | * XVERIFIER_OPTIMIZE B1 0 0.001 0.00054728 + B1 = XVERIFIER_VALUE 209 | + B1 = 0.00054728 210 | + KETA = -0.047 211 | * XVERIFIER_OPTIMIZE A1 0 3 0.00012153 + A1 = XVERIFIER_VALUE 212 | + A1 = 0.00012153 213 | * XVERIFIER_OPTIMIZE A2 0.2 3 0.9886 + A2 = XVERIFIER_VALUE 214 | + A2 = 0.9886 215 | * XVERIFIER_OPTIMIZE RDSW 0 1000000 218.151 + RDSW = XVERIFIER_VALUE 216 | + RDSW = 218.151 217 | + PRWB = 0 218 | * XVERIFIER_OPTIMIZE PRWG 0 100 39.5405 + PRWG = XVERIFIER_VALUE 219 | + PRWG = 39.5405 220 | + WR = 1 221 | *+ WINT = 0 222 | *+ LINT = 0 223 | + DWG = 0 224 | + DWB = 0 225 | * XVERIFIER_OPTIMIZE VOFF -0.5 0.5 -0.11293 + VOFF = XVERIFIER_VALUE 226 | + VOFF = -0.11293 227 | * XVERIFIER_OPTIMIZE NFACTOR 0.5 10 0.50037 + NFACTOR = XVERIFIER_VALUE 228 | + NFACTOR = 0.50037 229 | + ETA0 = 0.08 230 | + ETAB = -0.07 231 | + DSUB = 0.56 232 | + CIT = 0 233 | * XVERIFIER_OPTIMIZE CDSC 1e-05 0.01 1.2564e-05 + CDSC = XVERIFIER_VALUE 234 | + CDSC = 1.2564e-05 235 | + CDSCB = 0 236 | * XVERIFIER_OPTIMIZE CDSCD 0 1 0.49236 + CDSCD = XVERIFIER_VALUE 237 | + CDSCD = 0.49236 238 | * XVERIFIER_OPTIMIZE PCLM 0.1 10 8.9189 + PCLM = XVERIFIER_VALUE 239 | + PCLM = 8.9189 240 | + PDIBLC1 = 0.39 241 | * XVERIFIER_OPTIMIZE PDIBLC2 1e-06 1 1.0757e-06 + PDIBLC2 = XVERIFIER_VALUE 242 | + PDIBLC2 = 1.0757e-06 243 | + PDIBLCB = 0 244 | + DROUT = 0.56 245 | *****+ PSCBE1 = 4.24E+008 246 | *****+ PSCBE2 = 1.0E-005 247 | + PVAG = 0 248 | * XVERIFIER_OPTIMIZE DELTA 0.001 10 0.0015861 + DELTA = XVERIFIER_VALUE 249 | + DELTA = 0.0015861 250 | + NGATE = 0 251 | + ALPHA0 = 0 252 | *****+ ALPHA1 = 0 253 | + BETA0 = 30 254 | + RSH = 0 255 | *****+ JSSW = 0 256 | *****+ JS = 1.0E-004 257 | *****+ IJTH = 0.1 258 | + XPART = 1 259 | + CGSO = 6.4E-9 260 | *****+ CGSO = 10.5E-9 261 | + CGDO = 6.4E-9 262 | *****+ CGDO = 10.5E-9 263 | + CGSL = 0 264 | + CGDL = 0 265 | *****+ CGBO = 0 266 | *****+ CJ = 5.0E-004 267 | *****+ MJ = 0.5 268 | *****+ MJSW = 0.33 269 | *****+ CJSW = 5.0E-010 270 | + CJSWG = 5.0E-010 271 | + MJSWG = 0.33 272 | *****+ PBSW = 1 273 | *****+ PB = 1 274 | + PBSWG = 1 275 | + CKAPPA = 0.6 276 | + CF = 0 277 | + CLC = 1.0E-007 278 | + CLE = 0.6 279 | + DLC = 0 280 | + DWC = 0 281 | *****+ VFBCV = -1 282 | + NOFF = 1 283 | *****+ VOFFCV = 0 284 | + ACDE = 1 285 | + MOIN = 15 286 | + UTE = -1.5 287 | + KT1 = -0.11 288 | + KT1L = 0 289 | + KT2 = 0.022 290 | + UA1 = 4.31E-009 291 | + UB1 = -7.61E-018 292 | + UC1 = -5.6E-011 293 | + AT = 3.3E+004 294 | + PRT = 0 295 | *****+ NJ = 1 296 | *****+ XTI = 3 297 | *****+ TPB = 0 298 | *****+ TPBSW = 0 299 | *****+ TPBSWG = 0 300 | *****+ TCJ = 0 301 | *****+ TCJSW = 0 302 | + TCJSWG = 0 303 | + AF = 1 304 | + EF = 1 305 | + KF = 0 306 | * XVERIFIER_OPTIMIZE WINT 0 2.9e-06 0 + WINT = XVERIFIER_VALUE 307 | + WINT = 0 308 | * XVERIFIER_OPTIMIZE LINT 0 2.9e-06 7.5e-07 + LINT = XVERIFIER_VALUE 309 | + LINT = 7.5e-07 310 | 311 | -------------------------------------------------------------------------------- /Technology/tech/models/MF_CMOS20230922.txt: -------------------------------------------------------------------------------- 1 | * Copyright 2023 minimalFab Promoting Organization 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License 14 | 15 | * SPICE file 16 | * ICPS2023Ver1.0 17 | 18 | 19 | * 20 | .MODEL mf_nmos NMOS 21 | + TNOM = 25 22 | ************************+ LEVEL = 8 23 | *+ VERSION = 3.3.0 24 | + LEVEL = 8 25 | + PARAMCHK = 1 26 | + MOBMOD = 1 27 | + CAPMOD = 3 28 | + FNOIMOD = 1 29 | + SOIMOD = 3 30 | * XVERIFIER_OPTIMIZE TOX 1e-09 3 1.5e-08 + TOX = XVERIFIER_VALUE 31 | + TOX = 1.5e-08 32 | + XJ = 1.5E-007 33 | + NCH = 1.7E+017 34 | * XVERIFIER_OPTIMIZE VTH0 0 3 0.20809 + VTH0 = XVERIFIER_VALUE 35 | + VTH0 = 0.20809 36 | * XVERIFIER_OPTIMIZE K1 0 1 0.5 + K1 = XVERIFIER_VALUE 37 | + K1 = 0.5 38 | * XVERIFIER_OPTIMIZE K2 0 1 0 + K2 = XVERIFIER_VALUE 39 | + K2 = 0 40 | + K3 = 80 41 | + K3B = 0 42 | + W0 = 2.5E-006 43 | + NLX = 1.74E-007 44 | + VBM = -3.0 45 | + DVT0 = 2.2 46 | + DVT1 = 0.53 47 | + DVT2 = -0.032 48 | + DVT0W = 0 49 | + DVT1W = 5.3E+006 50 | + DVT2W = -0.032 51 | * XVERIFIER_OPTIMIZE U0 100 2000 670 + U0 = XVERIFIER_VALUE 52 | + U0 = 670 53 | * XVERIFIER_OPTIMIZE UA -3e-08 1e-08 2.25e-09 + UA = XVERIFIER_VALUE 54 | + UA = 2.25e-09 55 | * XVERIFIER_OPTIMIZE UB -3e-20 1e-16 5.87e-19 + UB = XVERIFIER_VALUE 56 | + UB = 5.87e-19 57 | * XVERIFIER_OPTIMIZE UC -1e-10 -1e-12 -4.65e-11 + UC = XVERIFIER_VALUE 58 | + UC = -4.65e-11 59 | * XVERIFIER_OPTIMIZE VSAT 10000 1000000 800755.2814 + VSAT = XVERIFIER_VALUE 60 | + VSAT = 800755.2814 61 | * XVERIFIER_OPTIMIZE A0 0 3 1.1164 + A0 = XVERIFIER_VALUE 62 | + A0 = 1.1164 63 | * XVERIFIER_OPTIMIZE AGS -0.1 3 0.2656 + AGS = XVERIFIER_VALUE 64 | + AGS = 0.2656 65 | + B0 = 0 66 | + B1 = 0 67 | + KETA = -0.047 68 | + A1 = 0 69 | * XVERIFIER_OPTIMIZE A2 0.2 1 0.20782 + A2 = XVERIFIER_VALUE 70 | + A2 = 0.20782 71 | * XVERIFIER_OPTIMIZE RDSW 0 1000000 0 + RDSW = XVERIFIER_VALUE 72 | + RDSW = 0 73 | + PRWB = 0 74 | * XVERIFIER_OPTIMIZE PRWG 0 100 58.7371 + PRWG = XVERIFIER_VALUE 75 | + PRWG = 58.7371 76 | + WR = 1 77 | + WINT = 0 78 | + LINT = 0 79 | + DWG = 0 80 | + DWB = 0 81 | * XVERIFIER_OPTIMIZE VOFF -0.5 0.5 -0.17284 + VOFF = XVERIFIER_VALUE 82 | + VOFF = -0.17284 83 | * XVERIFIER_OPTIMIZE NFACTOR 0.5 10 0.99099 + NFACTOR = XVERIFIER_VALUE 84 | + NFACTOR = 0.99099 85 | + ETA0 = 0.08 86 | + ETAB = -0.07 87 | + DSUB = 0.56 88 | + CIT = 0 89 | * XVERIFIER_OPTIMIZE CDSC 1e-05 0.01 0.00021654 + CDSC = XVERIFIER_VALUE 90 | + CDSC = 0.00021654 91 | + CDSCB = 0 92 | * XVERIFIER_OPTIMIZE CDSCD 0 1 0.38995 + CDSCD = XVERIFIER_VALUE 93 | + CDSCD = 0.38995 94 | * XVERIFIER_OPTIMIZE PCLM 0.1 3 2.9694 + PCLM = XVERIFIER_VALUE 95 | + PCLM = 2.9694 96 | + PDIBLC1 = 0.39 97 | * XVERIFIER_OPTIMIZE PDIBLC2 1e-06 0.1 0.0021218 + PDIBLC2 = XVERIFIER_VALUE 98 | + PDIBLC2 = 0.0021218 99 | + PDIBLCB = 0 100 | + DROUT = 0.56 101 | *****+ PSCBE1 = 4.24E+008 102 | *****+ PSCBE2 = 1.0E-005 103 | + PVAG = 0 104 | * XVERIFIER_OPTIMIZE DELTA 0.001 10 0.045152 + DELTA = XVERIFIER_VALUE 105 | + DELTA = 0.045152 106 | + NGATE = 0 107 | + ALPHA0 = 0 108 | *****+ ALPHA1 = 0 109 | + BETA0 = 30 110 | + RSH = 0 111 | *****+ JSSW = 0 112 | *****+ JS = 1.0E-004 113 | *****+ IJTH = 0.1 114 | + XPART = 1 115 | + CGSO = 5.3E-9 116 | *****+ CGSO = 8.8E-9 117 | + CGDO = 5.3E-9 118 | *****+ CGDO = 8.8E-9 119 | + CGSL = 0 120 | + CGDL = 0 121 | *****+ CGBO = 0 122 | *****+ CJ = 5.0E-004 123 | *****+ MJ = 0.5 124 | *****+ MJSW = 0.33 125 | *****+ CJSW = 5.0E-010 126 | + CJSWG = 5.0E-010 127 | + MJSWG = 0.33 128 | *****+ PBSW = 1 129 | *****+ PB = 1 130 | + PBSWG = 1 131 | + CKAPPA = 0.6 132 | + CF = 0 133 | + CLC = 1.0E-007 134 | + CLE = 0.6 135 | + DLC = 0 136 | + DWC = 0 137 | *****+ VFBCV = -1 138 | + NOFF = 1 139 | *****+ VOFFCV = 0 140 | + ACDE = 1 141 | + MOIN = 15 142 | + UTE = -1.5 143 | + KT1 = -0.11 144 | + KT1L = 0 145 | + KT2 = 0.022 146 | + UA1 = 4.31E-009 147 | + UB1 = -7.61E-018 148 | + UC1 = -5.6E-011 149 | + AT = 3.3E+004 150 | + PRT = 0 151 | *****+ NJ = 1 152 | *****+ XTI = 3 153 | *****+ TPB = 0 154 | *****+ TPBSW = 0 155 | *****+ TPBSWG = 0 156 | *****+ TCJ = 0 157 | *****+ TCJSW = 0 158 | + TCJSWG = 0 159 | + AF = 1 160 | + EF = 1 161 | + KF = 0 162 | 163 | * 164 | .MODEL mf_pmos PMOS 165 | + TNOM = 25 166 | + LEVEL = 8 167 | ******************+ LEVEL = 9 168 | + VERSION = 3.3.0 169 | + PARAMCHK = 1 170 | + MOBMOD = 1 171 | + CAPMOD = 3 172 | * XVERIFIER_OPTIMIZE TOX 1e-09 3 1.5e-08 + TOX = XVERIFIER_VALUE 173 | + TOX = 1.5e-08 174 | + XJ = 1.5E-007 175 | + NCH = 1.7E+017 176 | * XVERIFIER_OPTIMIZE VTH0 -3 0 -0.4348 + VTH0 = XVERIFIER_VALUE 177 | + VTH0 = -0.4348 178 | * XVERIFIER_OPTIMIZE K1 0 1 0.5 + K1 = XVERIFIER_VALUE 179 | + K1 = 0.5 180 | * XVERIFIER_OPTIMIZE K2 0 1 0 + K2 = XVERIFIER_VALUE 181 | + K2 = 0 182 | + K3 = 80 183 | + K3B = 0 184 | + W0 = 2.5E-006 185 | + NLX = 1.74E-007 186 | + VBM = -3.0 187 | + DVT0 = 2.2 188 | + DVT1 = 0.53 189 | + DVT2 = -0.032 190 | + DVT0W = 0 191 | + DVT1W = 5.3E+006 192 | + DVT2W = -0.032 193 | * XVERIFIER_OPTIMIZE U0 10 2000 80.6055 + U0 = XVERIFIER_VALUE 194 | + U0 = 80.6055 195 | * XVERIFIER_OPTIMIZE UA -3e-08 1e-08 -5.7647e-10 + UA = XVERIFIER_VALUE 196 | + UA = -5.7647e-10 197 | * XVERIFIER_OPTIMIZE UB -3e-20 1e-16 5.0269e-19 + UB = XVERIFIER_VALUE 198 | + UB = 5.0269e-19 199 | * XVERIFIER_OPTIMIZE UC -1e-10 -1e-12 -4.65e-11 + UC = XVERIFIER_VALUE 200 | + UC = -4.65e-11 201 | * XVERIFIER_OPTIMIZE VSAT 10000 1000000 999949 + VSAT = XVERIFIER_VALUE 202 | + VSAT = 999949 203 | * XVERIFIER_OPTIMIZE A0 0 3 0.52732 + A0 = XVERIFIER_VALUE 204 | + A0 = 0.52732 205 | * XVERIFIER_OPTIMIZE AGS -0.1 3 0.1971 + AGS = XVERIFIER_VALUE 206 | + AGS = 0.1971 207 | * XVERIFIER_OPTIMIZE B0 0 0.001 3.8867e-07 + B0 = XVERIFIER_VALUE 208 | + B0 = 3.8867e-07 209 | * XVERIFIER_OPTIMIZE B1 0 0.001 0.00054728 + B1 = XVERIFIER_VALUE 210 | + B1 = 0.00054728 211 | + KETA = -0.047 212 | * XVERIFIER_OPTIMIZE A1 0 3 0.00012153 + A1 = XVERIFIER_VALUE 213 | + A1 = 0.00012153 214 | * XVERIFIER_OPTIMIZE A2 0.2 3 0.9886 + A2 = XVERIFIER_VALUE 215 | + A2 = 0.9886 216 | * XVERIFIER_OPTIMIZE RDSW 0 1000000 218.151 + RDSW = XVERIFIER_VALUE 217 | + RDSW = 218.151 218 | + PRWB = 0 219 | * XVERIFIER_OPTIMIZE PRWG 0 100 39.5405 + PRWG = XVERIFIER_VALUE 220 | + PRWG = 39.5405 221 | + WR = 1 222 | *+ WINT = 0 223 | *+ LINT = 0 224 | + DWG = 0 225 | + DWB = 0 226 | * XVERIFIER_OPTIMIZE VOFF -0.5 0.5 -0.11293 + VOFF = XVERIFIER_VALUE 227 | + VOFF = -0.11293 228 | * XVERIFIER_OPTIMIZE NFACTOR 0.5 10 0.50037 + NFACTOR = XVERIFIER_VALUE 229 | + NFACTOR = 0.50037 230 | + ETA0 = 0.08 231 | + ETAB = -0.07 232 | + DSUB = 0.56 233 | + CIT = 0 234 | * XVERIFIER_OPTIMIZE CDSC 1e-05 0.01 1.2564e-05 + CDSC = XVERIFIER_VALUE 235 | + CDSC = 1.2564e-05 236 | + CDSCB = 0 237 | * XVERIFIER_OPTIMIZE CDSCD 0 1 0.49236 + CDSCD = XVERIFIER_VALUE 238 | + CDSCD = 0.49236 239 | * XVERIFIER_OPTIMIZE PCLM 0.1 10 8.9189 + PCLM = XVERIFIER_VALUE 240 | + PCLM = 8.9189 241 | + PDIBLC1 = 0.39 242 | * XVERIFIER_OPTIMIZE PDIBLC2 1e-06 1 1.0757e-06 + PDIBLC2 = XVERIFIER_VALUE 243 | + PDIBLC2 = 1.0757e-06 244 | + PDIBLCB = 0 245 | + DROUT = 0.56 246 | *****+ PSCBE1 = 4.24E+008 247 | *****+ PSCBE2 = 1.0E-005 248 | + PVAG = 0 249 | * XVERIFIER_OPTIMIZE DELTA 0.001 10 0.0015861 + DELTA = XVERIFIER_VALUE 250 | + DELTA = 0.0015861 251 | + NGATE = 0 252 | + ALPHA0 = 0 253 | *****+ ALPHA1 = 0 254 | + BETA0 = 30 255 | + RSH = 0 256 | *****+ JSSW = 0 257 | *****+ JS = 1.0E-004 258 | *****+ IJTH = 0.1 259 | + XPART = 1 260 | + CGSO = 6.4E-9 261 | *****+ CGSO = 10.5E-9 262 | + CGDO = 6.4E-9 263 | *****+ CGDO = 10.5E-9 264 | + CGSL = 0 265 | + CGDL = 0 266 | *****+ CGBO = 0 267 | *****+ CJ = 5.0E-004 268 | *****+ MJ = 0.5 269 | *****+ MJSW = 0.33 270 | *****+ CJSW = 5.0E-010 271 | + CJSWG = 5.0E-010 272 | + MJSWG = 0.33 273 | *****+ PBSW = 1 274 | *****+ PB = 1 275 | + PBSWG = 1 276 | + CKAPPA = 0.6 277 | + CF = 0 278 | + CLC = 1.0E-007 279 | + CLE = 0.6 280 | + DLC = 0 281 | + DWC = 0 282 | *****+ VFBCV = -1 283 | + NOFF = 1 284 | *****+ VOFFCV = 0 285 | + ACDE = 1 286 | + MOIN = 15 287 | + UTE = -1.5 288 | + KT1 = -0.11 289 | + KT1L = 0 290 | + KT2 = 0.022 291 | + UA1 = 4.31E-009 292 | + UB1 = -7.61E-018 293 | + UC1 = -5.6E-011 294 | + AT = 3.3E+004 295 | + PRT = 0 296 | *****+ NJ = 1 297 | *****+ XTI = 3 298 | *****+ TPB = 0 299 | *****+ TPBSW = 0 300 | *****+ TPBSWG = 0 301 | *****+ TCJ = 0 302 | *****+ TCJSW = 0 303 | + TCJSWG = 0 304 | + AF = 1 305 | + EF = 1 306 | + KF = 0 307 | * XVERIFIER_OPTIMIZE WINT 0 2.9e-06 0 + WINT = XVERIFIER_VALUE 308 | + WINT = 0 309 | * XVERIFIER_OPTIMIZE LINT 0 2.9e-06 7.5e-07 + LINT = XVERIFIER_VALUE 310 | + LINT = 7.5e-07 311 | 312 | -------------------------------------------------------------------------------- /Technology/tech/models/SOI_CMOS: -------------------------------------------------------------------------------- 1 | * Copyright 2023 minimalFab Promoting Organization 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License 14 | 15 | *.include ./MF_CMOS20240109.txt 16 | * SPICE file 17 | * ICPS2023Ver1.01 18 | * Revised 2024.1.9 19 | 20 | * 21 | .MODEL nch NMOS 22 | + TNOM = 25 23 | + VERSION = 3.3.0 24 | + LEVEL = 8 25 | + PARAMCHK = 1 26 | + MOBMOD = 1 27 | + CAPMOD = 3 28 | *+ FNOIMOD = 1 29 | *+ SOIMOD = 3 30 | * XVERIFIER_OPTIMIZE TOX 1e-09 3 1.5e-08 + TOX = XVERIFIER_VALUE 31 | + TOX = 1.5e-08 32 | + XJ = 1.5E-007 33 | + NCH = 1.7E+017 34 | * XVERIFIER_OPTIMIZE VTH0 0 3 0.20809 + VTH0 = XVERIFIER_VALUE 35 | + VTH0 = 0.20809 36 | * XVERIFIER_OPTIMIZE K1 0 1 0.5 + K1 = XVERIFIER_VALUE 37 | + K1 = 0.5 38 | * XVERIFIER_OPTIMIZE K2 0 1 0 + K2 = XVERIFIER_VALUE 39 | + K2 = 0 40 | + K3 = 80 41 | + K3B = 0 42 | + W0 = 2.5E-006 43 | + NLX = 1.74E-007 44 | + VBM = -3.0 45 | + DVT0 = 2.2 46 | + DVT1 = 0.53 47 | + DVT2 = -0.032 48 | + DVT0W = 0 49 | + DVT1W = 5.3E+006 50 | + DVT2W = -0.032 51 | * XVERIFIER_OPTIMIZE U0 100 2000 670 + U0 = XVERIFIER_VALUE 52 | + U0 = 670 53 | * XVERIFIER_OPTIMIZE UA -3e-08 1e-08 2.25e-09 + UA = XVERIFIER_VALUE 54 | + UA = 2.25e-09 55 | * XVERIFIER_OPTIMIZE UB -3e-20 1e-16 5.87e-19 + UB = XVERIFIER_VALUE 56 | + UB = 5.87e-19 57 | * XVERIFIER_OPTIMIZE UC -1e-10 -1e-12 -4.65e-11 + UC = XVERIFIER_VALUE 58 | + UC = -4.65e-11 59 | * XVERIFIER_OPTIMIZE VSAT 10000 1000000 800755.2814 + VSAT = XVERIFIER_VALUE 60 | + VSAT = 800755.2814 61 | * XVERIFIER_OPTIMIZE A0 0 3 1.1164 + A0 = XVERIFIER_VALUE 62 | + A0 = 1.1164 63 | * XVERIFIER_OPTIMIZE AGS -0.1 3 0.2656 + AGS = XVERIFIER_VALUE 64 | + AGS = 0.2656 65 | + B0 = 0 66 | + B1 = 0 67 | + KETA = -0.047 68 | + A1 = 0 69 | * XVERIFIER_OPTIMIZE A2 0.2 1 0.20782 + A2 = XVERIFIER_VALUE 70 | + A2 = 0.20782 71 | * XVERIFIER_OPTIMIZE RDSW 0 1000000 0 + RDSW = XVERIFIER_VALUE 72 | + RDSW = 0 73 | + PRWB = 0 74 | * XVERIFIER_OPTIMIZE PRWG 0 100 58.7371 + PRWG = XVERIFIER_VALUE 75 | + PRWG = 58.7371 76 | + WR = 1 77 | + WINT = 0 78 | + LINT = 0 79 | + DWG = 0 80 | + DWB = 0 81 | * XVERIFIER_OPTIMIZE VOFF -0.5 0.5 -0.17284 + VOFF = XVERIFIER_VALUE 82 | + VOFF = -0.17284 83 | * XVERIFIER_OPTIMIZE NFACTOR 0.5 10 0.99099 + NFACTOR = XVERIFIER_VALUE 84 | + NFACTOR = 0.99099 85 | + ETA0 = 0.08 86 | + ETAB = -0.07 87 | + DSUB = 0.56 88 | + CIT = 0 89 | * XVERIFIER_OPTIMIZE CDSC 1e-05 0.01 0.00021654 + CDSC = XVERIFIER_VALUE 90 | + CDSC = 0.00021654 91 | + CDSCB = 0 92 | * XVERIFIER_OPTIMIZE CDSCD 0 1 0.38995 + CDSCD = XVERIFIER_VALUE 93 | + CDSCD = 0.38995 94 | * XVERIFIER_OPTIMIZE PCLM 0.1 3 2.9694 + PCLM = XVERIFIER_VALUE 95 | + PCLM = 2.9694 96 | + PDIBLC1 = 0.39 97 | * XVERIFIER_OPTIMIZE PDIBLC2 1e-06 0.1 0.0021218 + PDIBLC2 = XVERIFIER_VALUE 98 | + PDIBLC2 = 0.0021218 99 | + PDIBLCB = 0 100 | + DROUT = 0.56 101 | *****+ PSCBE1 = 4.24E+008 102 | *****+ PSCBE2 = 1.0E-005 103 | + PVAG = 0 104 | * XVERIFIER_OPTIMIZE DELTA 0.001 10 0.045152 + DELTA = XVERIFIER_VALUE 105 | + DELTA = 0.045152 106 | + NGATE = 0 107 | + ALPHA0 = 0 108 | *****+ ALPHA1 = 0 109 | + BETA0 = 30 110 | + RSH = 0 111 | *****+ JSSW = 0 112 | *****+ JS = 1.0E-004 113 | *****+ IJTH = 0.1 114 | + XPART = 1 115 | + CGSO = 5.3E-9 116 | *****+ CGSO = 8.8E-9 117 | + CGDO = 5.3E-9 118 | *****+ CGDO = 8.8E-9 119 | + CGSL = 0 120 | + CGDL = 0 121 | *****+ CGBO = 0 122 | *****+ CJ = 5.0E-004 123 | *****+ MJ = 0.5 124 | *****+ MJSW = 0.33 125 | *****+ CJSW = 5.0E-010 126 | + CJSWG = 5.0E-010 127 | + MJSWG = 0.33 128 | *****+ PBSW = 1 129 | *****+ PB = 1 130 | + PBSWG = 1 131 | + CKAPPA = 0.6 132 | + CF = 0 133 | + CLC = 1.0E-007 134 | + CLE = 0.6 135 | + DLC = 0 136 | + DWC = 0 137 | *****+ VFBCV = -1 138 | + NOFF = 1 139 | *****+ VOFFCV = 0 140 | + ACDE = 1 141 | + MOIN = 15 142 | + UTE = -1.5 143 | + KT1 = -0.11 144 | + KT1L = 0 145 | + KT2 = 0.022 146 | + UA1 = 4.31E-009 147 | + UB1 = -7.61E-018 148 | + UC1 = -5.6E-011 149 | + AT = 3.3E+004 150 | + PRT = 0 151 | *****+ NJ = 1 152 | *****+ XTI = 3 153 | *****+ TPB = 0 154 | *****+ TPBSW = 0 155 | *****+ TPBSWG = 0 156 | *****+ TCJ = 0 157 | *****+ TCJSW = 0 158 | + TCJSWG = 0 159 | + AF = 1 160 | + EF = 1 161 | + KF = 0 162 | 163 | * 164 | .MODEL pch PMOS 165 | + TNOM = 25 166 | + LEVEL = 8 167 | ******************+ LEVEL = 9 168 | + VERSION = 3.3.0 169 | + PARAMCHK = 1 170 | + MOBMOD = 1 171 | + CAPMOD = 3 172 | * XVERIFIER_OPTIMIZE TOX 1e-09 3 1.5e-08 + TOX = XVERIFIER_VALUE 173 | + TOX = 1.5e-08 174 | + XJ = 1.5E-007 175 | + NCH = 1.7E+017 176 | * XVERIFIER_OPTIMIZE VTH0 -3 0 -0.4348 + VTH0 = XVERIFIER_VALUE 177 | + VTH0 = -0.4348 178 | * XVERIFIER_OPTIMIZE K1 0 1 0.5 + K1 = XVERIFIER_VALUE 179 | + K1 = 0.5 180 | * XVERIFIER_OPTIMIZE K2 0 1 0 + K2 = XVERIFIER_VALUE 181 | + K2 = 0 182 | + K3 = 80 183 | + K3B = 0 184 | + W0 = 2.5E-006 185 | + NLX = 1.74E-007 186 | + VBM = -3.0 187 | + DVT0 = 2.2 188 | + DVT1 = 0.53 189 | + DVT2 = -0.032 190 | + DVT0W = 0 191 | + DVT1W = 5.3E+006 192 | + DVT2W = -0.032 193 | * XVERIFIER_OPTIMIZE U0 10 2000 80.6055 + U0 = XVERIFIER_VALUE 194 | + U0 = 80.6055 195 | * XVERIFIER_OPTIMIZE UA -3e-08 1e-08 -5.7647e-10 + UA = XVERIFIER_VALUE 196 | + UA = -5.7647e-10 197 | * XVERIFIER_OPTIMIZE UB -3e-20 1e-16 5.0269e-19 + UB = XVERIFIER_VALUE 198 | + UB = 5.0269e-19 199 | * XVERIFIER_OPTIMIZE UC -1e-10 -1e-12 -4.65e-11 + UC = XVERIFIER_VALUE 200 | + UC = -4.65e-11 201 | * XVERIFIER_OPTIMIZE VSAT 10000 1000000 999949 + VSAT = XVERIFIER_VALUE 202 | + VSAT = 999949 203 | * XVERIFIER_OPTIMIZE A0 0 3 0.52732 + A0 = XVERIFIER_VALUE 204 | + A0 = 0.52732 205 | * XVERIFIER_OPTIMIZE AGS -0.1 3 0.1971 + AGS = XVERIFIER_VALUE 206 | + AGS = 0.1971 207 | * XVERIFIER_OPTIMIZE B0 0 0.001 3.8867e-07 + B0 = XVERIFIER_VALUE 208 | + B0 = 3.8867e-07 209 | * XVERIFIER_OPTIMIZE B1 0 0.001 0.00054728 + B1 = XVERIFIER_VALUE 210 | + B1 = 0.00054728 211 | + KETA = -0.047 212 | * XVERIFIER_OPTIMIZE A1 0 3 0.00012153 + A1 = XVERIFIER_VALUE 213 | + A1 = 0.00012153 214 | * XVERIFIER_OPTIMIZE A2 0.2 3 0.9886 + A2 = XVERIFIER_VALUE 215 | + A2 = 0.9886 216 | * XVERIFIER_OPTIMIZE RDSW 0 1000000 218.151 + RDSW = XVERIFIER_VALUE 217 | + RDSW = 218.151 218 | + PRWB = 0 219 | * XVERIFIER_OPTIMIZE PRWG 0 100 39.5405 + PRWG = XVERIFIER_VALUE 220 | + PRWG = 39.5405 221 | + WR = 1 222 | *+ WINT = 0 223 | *+ LINT = 0 224 | + DWG = 0 225 | + DWB = 0 226 | * XVERIFIER_OPTIMIZE VOFF -0.5 0.5 -0.11293 + VOFF = XVERIFIER_VALUE 227 | + VOFF = -0.11293 228 | * XVERIFIER_OPTIMIZE NFACTOR 0.5 10 0.50037 + NFACTOR = XVERIFIER_VALUE 229 | + NFACTOR = 0.50037 230 | + ETA0 = 0.08 231 | + ETAB = -0.07 232 | + DSUB = 0.56 233 | + CIT = 0 234 | * XVERIFIER_OPTIMIZE CDSC 1e-05 0.01 1.2564e-05 + CDSC = XVERIFIER_VALUE 235 | + CDSC = 1.2564e-05 236 | + CDSCB = 0 237 | * XVERIFIER_OPTIMIZE CDSCD 0 1 0.49236 + CDSCD = XVERIFIER_VALUE 238 | + CDSCD = 0.49236 239 | * XVERIFIER_OPTIMIZE PCLM 0.1 10 8.9189 + PCLM = XVERIFIER_VALUE 240 | + PCLM = 8.9189 241 | + PDIBLC1 = 0.39 242 | * XVERIFIER_OPTIMIZE PDIBLC2 1e-06 1 1.0757e-06 + PDIBLC2 = XVERIFIER_VALUE 243 | + PDIBLC2 = 1.0757e-06 244 | + PDIBLCB = 0 245 | + DROUT = 0.56 246 | *****+ PSCBE1 = 4.24E+008 247 | *****+ PSCBE2 = 1.0E-005 248 | + PVAG = 0 249 | * XVERIFIER_OPTIMIZE DELTA 0.001 10 0.0015861 + DELTA = XVERIFIER_VALUE 250 | + DELTA = 0.0015861 251 | + NGATE = 0 252 | + ALPHA0 = 0 253 | *****+ ALPHA1 = 0 254 | + BETA0 = 30 255 | + RSH = 0 256 | *****+ JSSW = 0 257 | *****+ JS = 1.0E-004 258 | *****+ IJTH = 0.1 259 | + XPART = 1 260 | + CGSO = 6.4E-9 261 | *****+ CGSO = 10.5E-9 262 | + CGDO = 6.4E-9 263 | *****+ CGDO = 10.5E-9 264 | + CGSL = 0 265 | + CGDL = 0 266 | *****+ CGBO = 0 267 | *****+ CJ = 5.0E-004 268 | *****+ MJ = 0.5 269 | *****+ MJSW = 0.33 270 | *****+ CJSW = 5.0E-010 271 | + CJSWG = 5.0E-010 272 | + MJSWG = 0.33 273 | *****+ PBSW = 1 274 | *****+ PB = 1 275 | + PBSWG = 1 276 | + CKAPPA = 0.6 277 | + CF = 0 278 | + CLC = 1.0E-007 279 | + CLE = 0.6 280 | + DLC = 0 281 | + DWC = 0 282 | *****+ VFBCV = -1 283 | + NOFF = 1 284 | *****+ VOFFCV = 0 285 | + ACDE = 1 286 | + MOIN = 15 287 | + UTE = -1.5 288 | + KT1 = -0.11 289 | + KT1L = 0 290 | + KT2 = 0.022 291 | + UA1 = 4.31E-009 292 | + UB1 = -7.61E-018 293 | + UC1 = -5.6E-011 294 | + AT = 3.3E+004 295 | + PRT = 0 296 | *****+ NJ = 1 297 | *****+ XTI = 3 298 | *****+ TPB = 0 299 | *****+ TPBSW = 0 300 | *****+ TPBSWG = 0 301 | *****+ TCJ = 0 302 | *****+ TCJSW = 0 303 | + TCJSWG = 0 304 | + AF = 1 305 | + EF = 1 306 | + KF = 0 307 | * XVERIFIER_OPTIMIZE WINT 0 2.9e-06 0 + WINT = XVERIFIER_VALUE 308 | + WINT = 0 309 | * XVERIFIER_OPTIMIZE LINT 0 2.9e-06 7.5e-07 + LINT = XVERIFIER_VALUE 310 | + LINT = 7.5e-07 311 | 312 | -------------------------------------------------------------------------------- /Technology/tech/ICPS_SOI.lyp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | #ff00ff 5 | #ff00ff 6 | 0 7 | 0 8 | I12 9 | 10 | false 11 | true 12 | false 13 | 14 | false 15 | false 16 | 0 17 | P_plus 18 | 2/0@1 19 | 20 | 21 | #008000 22 | #008000 23 | 0 24 | 0 25 | I12 26 | 27 | true 28 | true 29 | false 30 | 31 | false 32 | false 33 | 0 34 | N_plus 35 | 3/0@1 36 | 37 | 38 | #afff80 39 | #afff80 40 | 0 41 | 0 42 | I1 43 | 44 | true 45 | true 46 | false 47 | 1 48 | false 49 | false 50 | 0 51 | SOI 52 | 4/0@1 53 | 54 | 55 | #ff7c25 56 | #ff7c25 57 | 0 58 | 0 59 | I3 60 | 61 | true 62 | true 63 | false 64 | 65 | false 66 | false 67 | 0 68 | TIN 69 | 5/0@1 70 | 71 | 72 | #80a8ff 73 | #80a8ff 74 | 0 75 | 0 76 | I7 77 | 78 | true 79 | true 80 | false 81 | 82 | false 83 | false 84 | 0 85 | ML1 86 | 7/0@1 87 | 88 | 89 | #ffffff 90 | #ffffff 91 | 0 92 | 0 93 | I43 94 | 95 | true 96 | true 97 | false 98 | 99 | false 100 | false 101 | 0 102 | VIA1 103 | 8/0@1 104 | 105 | 106 | #ffffff 107 | #ffffff 108 | 0 109 | 0 110 | I13 111 | 112 | true 113 | true 114 | false 115 | 1 116 | false 117 | false 118 | 0 119 | CNT 120 | 6/0@1 121 | 122 | 123 | #ffffff 124 | #ffffff 125 | 0 126 | 0 127 | I8 128 | 129 | true 130 | true 131 | false 132 | 133 | false 134 | false 135 | 0 136 | ML2 137 | 9/0@1 138 | 139 | 140 | #cccccc 141 | #cccccc 142 | 0 143 | 0 144 | I13 145 | 146 | true 147 | true 148 | false 149 | 150 | false 151 | false 152 | 0 153 | PAD 154 | 10/0@1 155 | 156 | 157 | #ff0000 158 | #ff0000 159 | 0 160 | 0 161 | I1 162 | 163 | true 164 | true 165 | false 166 | 1 167 | false 168 | false 169 | 0 170 | PWell 171 | 13/0@1 172 | 173 | 174 | #500080 175 | #500080 176 | 0 177 | 0 178 | I5 179 | 180 | true 181 | true 182 | false 183 | 1 184 | false 185 | false 186 | 0 187 | RES 188 | 15/0@1 189 | 190 | 191 | #f3ff80 192 | #f3ff80 193 | 0 194 | 0 195 | I9 196 | 197 | true 198 | true 199 | false 200 | 201 | false 202 | false 203 | 0 204 | CAP 205 | 16/0@1 206 | 207 | 208 | #f3ff80 209 | #f3ff80 210 | 0 211 | 0 212 | I5 213 | 214 | true 215 | true 216 | false 217 | 218 | false 219 | false 220 | 0 221 | diode 222 | 17/0@1 223 | 224 | 225 | 226 | 227 | .................... 228 | .................... 229 | .................... 230 | .................... 231 | .................... 232 | .................... 233 | .................... 234 | .................... 235 | .................... 236 | .................... 237 | .................... 238 | .................... 239 | .................... 240 | .................... 241 | ...**............... 242 | ...**............... 243 | .................... 244 | .................... 245 | .................... 246 | .................... 247 | 248 | 1 249 | dots 4 250 | 251 | 252 | 253 | *..............................* 254 | .*............................*. 255 | ..*..........................*.. 256 | ...*........................*... 257 | ....*......................*.... 258 | .....*....................*..... 259 | ......*..................*...... 260 | .......*................*....... 261 | ........*..............*........ 262 | .........*............*......... 263 | ..........*..........*.......... 264 | ...........*........*........... 265 | ............*......*............ 266 | .............*....*............. 267 | ..............*..*.............. 268 | ...............**............... 269 | ...............**............... 270 | ..............*..*.............. 271 | .............*....*............. 272 | ............*......*............ 273 | ...........*........*........... 274 | ..........*..........*.......... 275 | .........*............*......... 276 | ........*..............*........ 277 | .......*................*....... 278 | ......*..................*...... 279 | .....*....................*..... 280 | ....*......................*.... 281 | ...*........................*... 282 | ..*..........................*.. 283 | .*............................*. 284 | *..............................* 285 | 286 | 2 287 | cross 288 | 289 | 290 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. Definitions. 8 | 9 | "License" shall mean the terms and conditions for use, reproduction, 10 | and distribution as defined by Sections 1 through 9 of this document. 11 | 12 | "Licensor" shall mean the copyright owner or entity authorized by 13 | the copyright owner that is granting the License. 14 | 15 | "Legal Entity" shall mean the union of the acting entity and all 16 | other entities that control, are controlled by, or are under common 17 | control with that entity. For the purposes of this definition, 18 | "control" means (i) the power, direct or indirect, to cause the 19 | direction or management of such entity, whether by contract or 20 | otherwise, or (ii) ownership of fifty percent (50%) or more of the 21 | outstanding shares, or (iii) beneficial ownership of such entity. 22 | 23 | "You" (or "Your") shall mean an individual or Legal Entity 24 | exercising permissions granted by this License. 25 | 26 | "Source" form shall mean the preferred form for making modifications, 27 | including but not limited to software source code, documentation 28 | source, and configuration files. 29 | 30 | "Object" form shall mean any form resulting from mechanical 31 | transformation or translation of a Source form, including but 32 | not limited to compiled object code, generated documentation, 33 | and conversions to other media types. 34 | 35 | "Work" shall mean the work of authorship, whether in Source or 36 | Object form, made available under the License, as indicated by a 37 | copyright notice that is included in or attached to the work 38 | (an example is provided in the Appendix below). 39 | 40 | "Derivative Works" shall mean any work, whether in Source or Object 41 | form, that is based on (or derived from) the Work and for which the 42 | editorial revisions, annotations, elaborations, or other modifications 43 | represent, as a whole, an original work of authorship. For the purposes 44 | of this License, Derivative Works shall not include works that remain 45 | separable from, or merely link (or bind by name) to the interfaces of, 46 | the Work and Derivative Works thereof. 47 | 48 | "Contribution" shall mean any work of authorship, including 49 | the original version of the Work and any modifications or additions 50 | to that Work or Derivative Works thereof, that is intentionally 51 | submitted to Licensor for inclusion in the Work by the copyright owner 52 | or by an individual or Legal Entity authorized to submit on behalf of 53 | the copyright owner. For the purposes of this definition, "submitted" 54 | means any form of electronic, verbal, or written communication sent 55 | to the Licensor or its representatives, including but not limited to 56 | communication on electronic mailing lists, source code control systems, 57 | and issue tracking systems that are managed by, or on behalf of, the 58 | Licensor for the purpose of discussing and improving the Work, but 59 | excluding communication that is conspicuously marked or otherwise 60 | designated in writing by the copyright owner as "Not a Contribution." 61 | 62 | "Contributor" shall mean Licensor and any individual or Legal Entity 63 | on behalf of whom a Contribution has been received by Licensor and 64 | subsequently incorporated within the Work. 65 | 66 | 2. Grant of Copyright License. Subject to the terms and conditions of 67 | this License, each Contributor hereby grants to You a perpetual, 68 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 69 | copyright license to reproduce, prepare Derivative Works of, 70 | publicly display, publicly perform, sublicense, and distribute the 71 | Work and such Derivative Works in Source or Object form. 72 | 73 | 3. Grant of Patent License. Subject to the terms and conditions of 74 | this License, each Contributor hereby grants to You a perpetual, 75 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 76 | (except as stated in this section) patent license to make, have made, 77 | use, offer to sell, sell, import, and otherwise transfer the Work, 78 | where such license applies only to those patent claims licensable 79 | by such Contributor that are necessarily infringed by their 80 | Contribution(s) alone or by combination of their Contribution(s) 81 | with the Work to which such Contribution(s) was submitted. If You 82 | institute patent litigation against any entity (including a 83 | cross-claim or counterclaim in a lawsuit) alleging that the Work 84 | or a Contribution incorporated within the Work constitutes direct 85 | or contributory patent infringement, then any patent licenses 86 | granted to You under this License for that Work shall terminate 87 | as of the date such litigation is filed. 88 | 89 | 4. Redistribution. You may reproduce and distribute copies of the 90 | Work or Derivative Works thereof in any medium, with or without 91 | modifications, and in Source or Object form, provided that You 92 | meet the following conditions: 93 | 94 | (a) You must give any other recipients of the Work or 95 | Derivative Works a copy of this License; and 96 | 97 | (b) You must cause any modified files to carry prominent notices 98 | stating that You changed the files; and 99 | 100 | (c) You must retain, in the Source form of any Derivative Works 101 | that You distribute, all copyright, patent, trademark, and 102 | attribution notices from the Source form of the Work, 103 | excluding those notices that do not pertain to any part of 104 | the Derivative Works; and 105 | 106 | (d) If the Work includes a "NOTICE" text file as part of its 107 | distribution, then any Derivative Works that You distribute must 108 | include a readable copy of the attribution notices contained 109 | within such NOTICE file, excluding those notices that do not 110 | pertain to any part of the Derivative Works, in at least one 111 | of the following places: within a NOTICE text file distributed 112 | as part of the Derivative Works; within the Source form or 113 | documentation, if provided along with the Derivative Works; or, 114 | within a display generated by the Derivative Works, if and 115 | wherever such third-party notices normally appear. The contents 116 | of the NOTICE file are for informational purposes only and 117 | do not modify the License. You may add Your own attribution 118 | notices within Derivative Works that You distribute, alongside 119 | or as an addendum to the NOTICE text from the Work, provided 120 | that such additional attribution notices cannot be construed 121 | as modifying the License. 122 | 123 | You may add Your own copyright statement to Your modifications and 124 | may provide additional or different license terms and conditions 125 | for use, reproduction, or distribution of Your modifications, or 126 | for any such Derivative Works as a whole, provided Your use, 127 | reproduction, and distribution of the Work otherwise complies with 128 | the conditions stated in this License. 129 | 130 | 5. Submission of Contributions. Unless You explicitly state otherwise, 131 | any Contribution intentionally submitted for inclusion in the Work 132 | by You to the Licensor shall be under the terms and conditions of 133 | this License, without any additional terms or conditions. 134 | Notwithstanding the above, nothing herein shall supersede or modify 135 | the terms of any separate license agreement you may have executed 136 | with Licensor regarding such Contributions. 137 | 138 | 6. Trademarks. This License does not grant permission to use the trade 139 | names, trademarks, service marks, or product names of the Licensor, 140 | except as required for reasonable and customary use in describing the 141 | origin of the Work and reproducing the content of the NOTICE file. 142 | 143 | 7. Disclaimer of Warranty. Unless required by applicable law or 144 | agreed to in writing, Licensor provides the Work (and each 145 | Contributor provides its Contributions) on an "AS IS" BASIS, 146 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 147 | implied, including, without limitation, any warranties or conditions 148 | of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A 149 | PARTICULAR PURPOSE. You are solely responsible for determining the 150 | appropriateness of using or redistributing the Work and assume any 151 | risks associated with Your exercise of permissions under this License. 152 | 153 | 8. Limitation of Liability. In no event and under no legal theory, 154 | whether in tort (including negligence), contract, or otherwise, 155 | unless required by applicable law (such as deliberate and grossly 156 | negligent acts) or agreed to in writing, shall any Contributor be 157 | liable to You for damages, including any direct, indirect, special, 158 | incidental, or consequential damages of any character arising as a 159 | result of this License or out of the use or inability to use the 160 | Work (including but not limited to damages for loss of goodwill, 161 | work stoppage, computer failure or malfunction, or any and all 162 | other commercial damages or losses), even if such Contributor 163 | has been advised of the possibility of such damages. 164 | 165 | 9. Accepting Warranty or Additional Liability. While redistributing 166 | the Work or Derivative Works thereof, You may choose to offer, 167 | and charge a fee for, acceptance of support, warranty, indemnity, 168 | or other liability obligations and/or rights consistent with this 169 | License. However, in accepting such obligations, You may act only 170 | on Your own behalf and on Your sole responsibility, not on behalf 171 | of any other Contributor, and only if You agree to indemnify, 172 | defend, and hold each Contributor harmless for any liability 173 | incurred by, or claims asserted against, such Contributor by reason 174 | of your accepting any such warranty or additional liability. 175 | 176 | END OF TERMS AND CONDITIONS -------------------------------------------------------------------------------- /Technology/tech/ICPS2023_5.lyp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | #00aa00 5 | #00aa00 6 | 0 7 | 0 8 | C0 9 | 10 | false 11 | true 12 | false 13 | 14 | false 15 | false 16 | 0 17 | NWL 18 | 1/0@1 19 | 20 | 21 | #00aa00 22 | #00aa00 23 | 0 24 | 0 25 | C0 26 | 27 | false 28 | true 29 | false 30 | 31 | false 32 | false 33 | 0 34 | NWL_dp 35 | 2/0@1 36 | 37 | 38 | #ffffff 39 | #9580ff 40 | 0 41 | 0 42 | I3 43 | 44 | true 45 | true 46 | false 47 | 48 | false 49 | false 50 | 0 51 | DIFF 52 | 3/0@1 53 | 54 | 55 | #ff7c25 56 | #ff7c25 57 | 0 58 | 0 59 | I3 60 | 61 | false 62 | false 63 | false 64 | 65 | false 66 | false 67 | 0 68 | POL 69 | 5/0@1 70 | 71 | 72 | #ff7c25 73 | #ff7c25 74 | 0 75 | 0 76 | I3 77 | 78 | true 79 | true 80 | false 81 | 82 | false 83 | false 84 | 0 85 | TIN 86 | 5/0@1 87 | 88 | 89 | #ff0000 90 | #ff0000 91 | 0 92 | 0 93 | I3 94 | 95 | false 96 | false 97 | false 98 | 99 | false 100 | false 101 | 0 102 | HPOL 103 | 6/0@1 104 | 105 | 106 | #ffffff 107 | #ffffff 108 | 0 109 | 0 110 | I13 111 | 112 | true 113 | true 114 | false 115 | 116 | false 117 | false 118 | 0 119 | CNT 120 | 7/0@1 121 | 122 | 123 | #00aaff 124 | #00aaff 125 | 0 126 | 0 127 | I7 128 | 129 | true 130 | true 131 | false 132 | 133 | false 134 | false 135 | 0 136 | ML1 137 | 8/0@1 138 | 139 | 140 | #ffffff 141 | #ffffff 142 | 0 143 | 0 144 | I43 145 | 146 | false 147 | false 148 | false 149 | 150 | false 151 | false 152 | 0 153 | VIA1 154 | 9/0@1 155 | 156 | 157 | #cccccc 158 | #cccccc 159 | 0 160 | 0 161 | I8 162 | 163 | false 164 | false 165 | false 166 | 167 | false 168 | false 169 | 0 170 | ML2 171 | 10/0@1 172 | 173 | 174 | #808080 175 | #808080 176 | 0 177 | 0 178 | I46 179 | 180 | false 181 | false 182 | false 183 | 1 184 | false 185 | false 186 | 0 187 | VIA2 188 | 11/0@1 189 | 190 | 191 | #0000ff 192 | #0000ff 193 | 0 194 | 0 195 | I11 196 | 197 | false 198 | false 199 | false 200 | 1 201 | false 202 | false 203 | 0 204 | ML3 205 | ML3 12/0@1 206 | 207 | 208 | #ffffff 209 | #ffffff 210 | 0 211 | 0 212 | I1 213 | 214 | true 215 | true 216 | false 217 | 218 | false 219 | false 220 | 0 221 | TEXT 222 | 13/0@1 223 | 224 | 225 | #ffffff 226 | #ffffff 227 | 0 228 | 0 229 | I1 230 | 231 | true 232 | true 233 | true 234 | 235 | false 236 | false 237 | 0 238 | FRAME 239 | 14/0@1 240 | 241 | 242 | #500080 243 | #500080 244 | 0 245 | 0 246 | I5 247 | 248 | true 249 | true 250 | false 251 | 1 252 | false 253 | false 254 | 0 255 | RES 256 | 15/0@1 257 | 258 | 259 | #f3ff80 260 | #f3ff80 261 | 0 262 | 0 263 | I9 264 | 265 | true 266 | true 267 | false 268 | 269 | false 270 | false 271 | 0 272 | CAP 273 | 16/0@1 274 | 275 | 276 | #f3ff80 277 | #f3ff80 278 | 0 279 | 0 280 | I5 281 | 282 | true 283 | true 284 | false 285 | 286 | false 287 | false 288 | 0 289 | diode 290 | 17/0@1 291 | 292 | 293 | #ff00ff 294 | #ff00ff 295 | 0 296 | 0 297 | I1 298 | 299 | true 300 | true 301 | false 302 | 303 | false 304 | false 305 | 0 306 | Parea 307 | 18/0@1 308 | 309 | 310 | #00aa00 311 | #00aa00 312 | 0 313 | 0 314 | I1 315 | 316 | true 317 | true 318 | false 319 | 320 | false 321 | false 322 | 0 323 | Narea 324 | 19/0@1 325 | 326 | 327 | #80fffb 328 | #80fffb 329 | 0 330 | 0 331 | I15 332 | 333 | true 334 | false 335 | false 336 | 1 337 | false 338 | false 339 | 0 340 | PAD 341 | 50/0@1 342 | 343 | 344 | #96c8ff 345 | #96c8ff 346 | 0 347 | 0 348 | I21 349 | 350 | true 351 | true 352 | false 353 | 354 | false 355 | false 356 | 0 357 | DM_dcn 358 | 101/0@1 359 | 360 | 361 | #ffaaff 362 | #ffaaff 363 | 0 364 | 0 365 | I21 366 | 367 | false 368 | false 369 | false 370 | 371 | false 372 | false 373 | 0 374 | DM_pcn 375 | 102/0@1 376 | 377 | 378 | #ffaaff 379 | #ffaaff 380 | 0 381 | 0 382 | I21 383 | 384 | true 385 | true 386 | false 387 | 388 | false 389 | false 390 | 0 391 | DM_tcn 392 | 102/0@1 393 | 394 | 395 | #00ffff 396 | #00ffff 397 | 0 398 | 0 399 | I21 400 | 401 | false 402 | true 403 | false 404 | 405 | false 406 | false 407 | 0 408 | DM_nscn 409 | 103/0@1 410 | 411 | 412 | #00aaff 413 | #00aaff 414 | 0 415 | 0 416 | I21 417 | 418 | false 419 | false 420 | false 421 | 422 | false 423 | false 424 | 0 425 | DM_pscn 426 | 104/0@1 427 | 428 | 429 | #688caa 430 | #688caa 431 | 0 432 | 0 433 | I21 434 | 435 | true 436 | true 437 | false 438 | 439 | false 440 | false 441 | 0 442 | DM_via1 443 | 105/0@1 444 | 445 | 446 | #80a8ff 447 | #80a8ff 448 | 0 449 | 0 450 | I9 451 | 452 | true 453 | true 454 | false 455 | 456 | false 457 | false 458 | 0 459 | 460 | 5/1@1 461 | 462 | 463 | #afff80 464 | #afff80 465 | 0 466 | 0 467 | I5 468 | 469 | true 470 | true 471 | false 472 | 473 | false 474 | false 475 | 0 476 | 477 | 20/0@1 478 | 479 | 480 | #ff0000 481 | #ff0000 482 | 0 483 | 0 484 | I3 485 | 486 | true 487 | true 488 | false 489 | 490 | false 491 | false 492 | 0 493 | P-Welll 494 | 21/0@1 495 | 496 | 497 | 498 | 499 | .................... 500 | .................... 501 | .................... 502 | .................... 503 | .................... 504 | .................... 505 | .................... 506 | .................... 507 | .................... 508 | .................... 509 | .................... 510 | .................... 511 | .................... 512 | .................... 513 | ...**............... 514 | ...**............... 515 | .................... 516 | .................... 517 | .................... 518 | .................... 519 | 520 | 1 521 | dots 4 522 | 523 | 524 | 525 | *..............................* 526 | .*............................*. 527 | ..*..........................*.. 528 | ...*........................*... 529 | ....*......................*.... 530 | .....*....................*..... 531 | ......*..................*...... 532 | .......*................*....... 533 | ........*..............*........ 534 | .........*............*......... 535 | ..........*..........*.......... 536 | ...........*........*........... 537 | ............*......*............ 538 | .............*....*............. 539 | ..............*..*.............. 540 | ...............**............... 541 | ...............**............... 542 | ..............*..*.............. 543 | .............*....*............. 544 | ............*......*............ 545 | ...........*........*........... 546 | ..........*..........*.......... 547 | .........*............*......... 548 | ........*..............*........ 549 | .......*................*....... 550 | ......*..................*...... 551 | .....*....................*..... 552 | ....*......................*.... 553 | ...*........................*... 554 | ..*..........................*.. 555 | .*............................*. 556 | *..............................* 557 | 558 | 2 559 | cross 560 | 561 | 562 | --------------------------------------------------------------------------------