├── LICENSE ├── README.md ├── classes └── dtc-145.bbclass ├── conf ├── layer.conf └── machine │ └── coral-dev.conf ├── recipes-bsp ├── coral-boot-script │ ├── coral-boot-script.bb │ └── files │ │ └── boot.txt ├── libedgetpu │ └── libedgetpu_1.0.bb └── u-boot │ ├── files │ └── 0001-Remove-redundant-YYLOC-global-declaration.patch │ └── u-boot-coral_2019.04.bb ├── recipes-kernel ├── dtc │ ├── dtc-145_git.bb │ └── files │ │ ├── 0001-Fix-compiler-warnings-seen-with-musl.patch │ │ ├── 0001-Remove-redundant-YYLOC-global-declaration.patch │ │ └── make_install.patch ├── kernel-modules │ ├── kernel-module-qca6174 │ │ └── 0001-MLK-18491-02-qcacld-2.0-fix-the-overflow-of-bounce-b.patch │ ├── kernel-module-qca6174_2.1.bb │ └── kernel-module-qcacld-lea.inc ├── linux-firmware │ └── linux-firmware_%.bbappend └── linux │ ├── files │ ├── defconfig │ ├── extra.cfg │ ├── mendel.cfg │ ├── werror.cfg │ └── wifi.cfg │ ├── linux-coral-5.4 │ ├── 0001-regulator-bd718x7-Add-MODULE_ALIAS.patch │ ├── 0002-regulator-bd718x7-Simplify-the-code-by-removing-stru.patch │ ├── 0003-mfd-Rohm-PMICs-Use-platform_device_id-to-match-MFD-s.patch │ ├── 0004-regulator-bd718x7-Split-driver-to-common-and-bd718x7.patch │ ├── 0005-regulator-bd718x7-remove-voltage-change-restriction-.patch │ ├── 0006-arm64-dts-freescale-add-initial-support-for-Google-i.patch │ ├── 0007-arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch │ ├── 0008-arm64-dts-imx8mq-phanbell-Add-gpio-fan-thermal-suppo.patch │ ├── 0009-arm64-dts-imx8mq-phanbell-Fix-Ethernet-PHY-post-rese.patch │ ├── 0010-arm64-dts-imx8mq-phanbell-Replace-deprecated-phy-res.patch │ ├── 0011-arm64-dts-imx8mq-phanbell-Align-pin-configuration-gr.patch │ ├── 0012-arm64-dts-imx8mq-phanbell-Disable-busfreq-to-avoid-s.patch │ ├── 0013-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch │ ├── 0014-arm64-dts-imx8mq-Set-ext_osc-to-1-as-default.patch │ ├── 0015-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch │ ├── 0016-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch │ ├── 0017-arm64-dts-imx8mq-phanbell-Enable-PCIe.patch │ ├── 0018-spi-spi-imx-Revive-cs-gpios-property-for-DT.patch │ ├── 0019-arm64-dts-imx8mq-phanbell-Enable-ECSPI1.patch │ ├── 0020-arm64-dts-imx8mq-phanbell-Add-gpio-pinmux-for-40-pin.patch │ └── 0021-arm64-dts-imx8mq-phanbell-Enable-I2C-2-I2C-3.patch │ ├── linux-coral │ ├── 0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch │ ├── 0002-include-linux-module.h-copy-__init-__exit-attrs-to-i.patch │ ├── 0003-Compiler-Attributes-add-support-for-__copy-gcc-9.patch │ └── 0004-Add-an-alias-for-imx8mq-phanbell.dts.patch │ ├── linux-coral_4.14.bb │ ├── linux-coral_5.4.bb │ ├── linux-fslc%.bbappend │ ├── linux-imx-5.15 │ ├── 0001-imx8mq-phanbell.dts-Enable-Coral-specifics-e.g.-PCIE.patch │ ├── 0002-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch │ ├── 0003-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch │ └── 0004-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch │ └── linux-imx_%.bbappend ├── recipes-security └── optee-imx │ └── optee-os_%.bbappend ├── recipes-support ├── common │ └── edgetpu-common.inc └── python │ └── python3-edgetpu.bb └── wic └── coral-bootpart.wks.in /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Mirza Krak 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | OpenEmbedded/Yocto BSP layer for Google Coral Dev Board 2 | ======================================================= 3 | 4 | This layer provides support for Coral Dev Board for use with OpenEmbedded 5 | and/or Yocto. 6 | 7 | This layer depends on: 8 | 9 | URI: git://git.openembedded.org/openembedded-core 10 | branch: master 11 | revision: HEAD 12 | 13 | URI: https://github.com/Freescale/meta-freescale.git 14 | branch: master 15 | revision: HEAD 16 | 17 | URL: https://github.com/kraj/meta-clang 18 | branch: master 19 | revision: HEAD 20 | 21 | Quick start 22 | ----------- 23 | 24 | Please visit the the [Quick start guide](https://github.com/mirzak/meta-coral/wiki/Quick-start-guide) 25 | for instructions on how to setup and build the project. 26 | 27 | Contributing 28 | ------------ 29 | 30 | Please submit any patches against the `meta-coral` using the GitHub 31 | pull-request feature. Fork the repo, make a branch, do the work, rebase 32 | from upstream, create the pull request. 33 | 34 | For some useful guidelines to be followed when submitting patches, 35 | please refer to: 36 | 37 | - http://openembedded.org/wiki/Commit_Patch_Message_Guidelines 38 | 39 | Pull requests will be discussed within the GitHub pull-request 40 | infrastructure. If you want to get informed on new PRs and the 41 | follow-up discussions please use the GitHub's notification system. 42 | 43 | Source code: 44 | 45 | - https://github.com/mirzak/meta-coral.git 46 | -------------------------------------------------------------------------------- /classes/dtc-145.bbclass: -------------------------------------------------------------------------------- 1 | # Use this class for U-Boot 2017.03 or older. 2 | 3 | DEPENDS:append = " dtc-145-native" 4 | 5 | do_configure:prepend () { 6 | sed -i -e 's/^DTC[[:space:]]*=[[:space:]]*dtc[[:space:]]*$/DTC = dtc-145/' ${S}/Makefile 7 | } 8 | -------------------------------------------------------------------------------- /conf/layer.conf: -------------------------------------------------------------------------------- 1 | # We have a conf and classes directory, add to BBPATH 2 | BBPATH .= ":${LAYERDIR}" 3 | 4 | # We have a packages directory, add to BBFILES 5 | BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ 6 | ${LAYERDIR}/recipes-*/*/*.bbappend" 7 | 8 | BBFILE_COLLECTIONS += "coral-bsp" 9 | BBFILE_PATTERN_coral-bsp := "^${LAYERDIR}/" 10 | BBFILE_PRIORITY_coral-bsp = "6" 11 | LAYERSERIES_COMPAT_coral-bsp = "nanbield scarthgap" 12 | 13 | LAYERDEPENDS_coral-bsp = "core freescale-layer clang-layer" 14 | -------------------------------------------------------------------------------- /conf/machine/coral-dev.conf: -------------------------------------------------------------------------------- 1 | #@TYPE: Machine 2 | #@NAME: Google Coral Dev Board 3 | #@SOC: i.MX8MQ 4 | #@DESCRIPTION: Machine configuration for Google Coral Dev Board 5 | #@MAINTAINER: Mirza Krak 6 | 7 | MACHINEOVERRIDES =. "mx8mq:use-nxp-bsp:" 8 | 9 | require conf/machine/include/imx-base.inc 10 | require conf/machine/include/arm/armv8a/tune-cortexa53.inc 11 | 12 | # Mainline BSP defaults to "generic" cortexa53 configuration, 13 | # adjust it here to include crypto extension which enables 14 | # inline NEON and FPU code generation 15 | DEFAULTTUNE:use-mainline-bsp = "cortexa53-crypto" 16 | 17 | PREFERRED_PROVIDER_virtual/kernel:use-mainline-bsp = "linux-fslc" 18 | PREFERRED_PROVIDER_virtual/kernel:use-nxp-bsp = "linux-coral" 19 | KBUILD_DEFCONFIG = "imx_v8_defconfig" 20 | 21 | MACHINE_FEATURES += "pci wifi bluetooth bcm43455 bcm4356" 22 | MACHINE_FEATURES:append:use-nxp-bsp = " optee bcm4359" 23 | 24 | MACHINE_EXTRA_RDEPENDS += "\ 25 | kernel-modules \ 26 | libedgetpu \ 27 | linux-firmware-ath10k \ 28 | " 29 | 30 | MACHINE_SOCARCH_FILTER:append:mx8mq = " virtual/libopenvg virtual/libgles1 virtual/libgles2 virtual/egl virtual/mesa virtual/libgl virtual/libg2d" 31 | 32 | KERNEL_DEVICETREE:use-nxp-bsp = "freescale/imx8mq-phanbell.dtb" 33 | KERNEL_DEVICETREE:use-mainline-bsp = "freescale/imx8mq-phanbell.dtb" 34 | 35 | IMX_DEFAULT_BOOTLOADER = "u-boot-coral" 36 | 37 | UBOOT_SUFFIX = "bin" 38 | 39 | UBOOT_CONFIG ??= "sd" 40 | UBOOT_CONFIG[sd] = "imx8mq_phanbell_defconfig,sdcard" 41 | UBOOT_CONFIG[mfgtool] = "imx8mq_phanbell_defconfig" 42 | 43 | UBOOT_PROVIDES_BOOT_CONTAINER:mx8m-generic-bsp = "0" 44 | 45 | SPL_BINARY = "spl/u-boot-spl.bin" 46 | 47 | # Set DDR FIRMWARE 48 | DDR_FIRMWARE_NAME = "\ 49 | lpddr4_pmu_train_1d_imem.bin \ 50 | lpddr4_pmu_train_1d_dmem.bin \ 51 | lpddr4_pmu_train_2d_imem.bin \ 52 | lpddr4_pmu_train_2d_dmem.bin \ 53 | " 54 | 55 | # Set u-boot DTB 56 | UBOOT_DTB_NAME = "fsl-imx8mq-phanbell.dtb" 57 | 58 | # Set ATF platform name 59 | ATF_PLATFORM = "imx8mq" 60 | 61 | # Set imx-mkimage boot target 62 | IMXBOOT_TARGETS = "flash_evk flash_evk_no_hdmi flash_dp_evk" 63 | IMX_BOOT_SOC_TARGET = "iMX8M" 64 | 65 | # Set Serial console 66 | SERIAL_CONSOLE = "115200 ttymxc0" 67 | 68 | LOADADDR = "" 69 | UBOOT_MAKE_TARGET = "" 70 | IMX_BOOT_SEEK = "33" 71 | 72 | OPTEE_BIN_EXT = "8mq" 73 | 74 | IMAGE_BOOT_FILES += "boot.scr" 75 | 76 | WKS_FILE = "coral-bootpart.wks.in" 77 | -------------------------------------------------------------------------------- /recipes-bsp/coral-boot-script/coral-boot-script.bb: -------------------------------------------------------------------------------- 1 | SUMMARY = "U-boot boot scripts for Coral Dev Board" 2 | LICENSE = "MIT" 3 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" 4 | 5 | DEPENDS = "u-boot-mkimage-native" 6 | 7 | INHIBIT_DEFAULT_DEPS = "1" 8 | 9 | SRC_URI = "file://boot.txt" 10 | 11 | do_compile() { 12 | mkimage -A arm -T script -C none -n "Boot script" -d "${WORKDIR}/boot.txt" boot.scr 13 | } 14 | 15 | inherit deploy nopackages 16 | 17 | do_deploy() { 18 | install -d ${DEPLOYDIR} 19 | install -m 0644 boot.scr ${DEPLOYDIR} 20 | } 21 | 22 | addtask do_deploy after do_compile before do_build 23 | 24 | COMPATIBLE_MACHINE = "coral-dev" 25 | -------------------------------------------------------------------------------- /recipes-bsp/coral-boot-script/files/boot.txt: -------------------------------------------------------------------------------- 1 | fdt_addr=0x44000000 2 | image=Image 3 | script=boot.scr 4 | mmc_root="PARTUUID=70672ec3-5eee-49ff-b3b1-eb1fbd406bf5" 5 | sd_root="/dev/mmcblk1p2" 6 | 7 | # Check boot device to decide which root partition to use 8 | if test ${bootdev} = 1; then 9 | setenv root ${sd_root} 10 | else 11 | setenv root ${mmc_root} 12 | fi 13 | 14 | if test ${baseboardid} = 1; then 15 | setenv fdt_file imx8mq-phanbell.dtb 16 | else 17 | # EVT Boards have quirky baseboard ID resistors, so fall back 18 | # to phanbell if we're unsure what the board is. 19 | echo "Unknown baseboard revision, selecting phanbell dtb." 20 | setenv fdt_file imx8mq-phanbell.dtb 21 | fi 22 | 23 | cmdline="root=${root} rootfstype=ext4 rw rootwait net.ifnames=0 pci=pcie_bus_perf" 24 | 25 | ext2load mmc ${bootdev}:1 ${loadaddr} ${image} 26 | setenv bootargs ${cmdline} ${extra_bootargs} 27 | 28 | #Load base device tree. 29 | ext2load mmc ${bootdev}:1 ${fdt_addr} ${fdt_file} 30 | fdt addr ${fdt_addr} 31 | fdt resize 32 | 33 | # Load overlays to arbitrary address beyond fdt location (will apply them later). 34 | setexpr fdtovaddr ${fdt_addr} + F000 35 | 36 | # Parse overlays.txt and apply individual overlays. 37 | if ext2load mmc ${bootdev}:1 ${fdtovaddr} overlays.txt && env import -t ${fdtovaddr} ${filesize} && test -n ${overlay}; then 38 | echo loaded overlay.txt: ${overlay} 39 | for ov in ${overlay}; do 40 | if ext2load mmc ${bootdev}:1 ${fdtovaddr} ${ov}.dtbo && fdt apply ${fdtovaddr}; then 41 | echo overlay of ${ov} successful 42 | else 43 | echo overlay failed, reverting to original device tree 44 | ext2load mmc ${bootdev}:1 ${fdt_addr} ${fdt_file} 45 | booti ${loadaddr} - ${fdt_addr} 46 | fi 47 | done 48 | fi 49 | 50 | booti ${loadaddr} - ${fdt_addr} 51 | -------------------------------------------------------------------------------- /recipes-bsp/libedgetpu/libedgetpu_1.0.bb: -------------------------------------------------------------------------------- 1 | SUMMARY = "Edge TPU library" 2 | LICENSE = "Proprietary" 3 | LIC_FILES_CHKSUM = "file://libedgetpu/LICENSE.txt;md5=3b9bc721e87e6fe1ca09f3c923502627" 4 | 5 | require recipes-support/common/edgetpu-common.inc 6 | 7 | S = "${WORKDIR}/git" 8 | 9 | RDEPENDS:${PN} = "libusb1 libcxx" 10 | 11 | EDGETPU_THROTTLED = "1" 12 | 13 | python __anonymous() { 14 | tunes = d.getVar("TUNE_FEATURES", True) 15 | if not tunes: 16 | return 17 | 18 | if "aarch64" in tunes: 19 | d.setVar("LIBEDGETPU_SUFFIX", "arm64") 20 | elif "x86_64" in tunes: 21 | d.setVar("LIBEDGETPU_SUFFIX", "x86_64") 22 | elif "callconvention-hard" in tunes: 23 | d.setVar("LIBEDGETPU_SUFFIX", "arm32") 24 | else: 25 | pkgn = d.getVar("PN", True) 26 | pkgv = d.getVar("PV", True) 27 | raise bb.parse.SkipRecipe("%s-%s: unsupported ARCH: %s" % (pkgn, pkgv, tunes)) 28 | 29 | 30 | throttled = d.getVar("EDGETPU_THROTTLED", True) 31 | if throttled: 32 | d.setVar("LIBEDGETPU_SUFFIX", d.getVar("LIBEDGETPU_SUFFIX", True) + "_throttled") 33 | } 34 | 35 | do_install() { 36 | install -d ${D}${sysconfdir}/udev/rules.d 37 | install -m 0644 ${S}/99-edgetpu-accelerator.rules \ 38 | ${D}${sysconfdir}/udev/rules.d/99-edgetpu-accelerator.rules 39 | 40 | install -d ${D}/${libdir} 41 | install -m 755 ${S}/libedgetpu/libedgetpu_${LIBEDGETPU_SUFFIX}.so \ 42 | ${D}/${libdir}/libedgetpu.so.1.0 43 | ln -sf ${libdir}/libedgetpu.so.1.0 ${D}/${libdir}/libedgetpu.so.1 44 | ln -sf ${libdir}/libedgetpu.so.1.0 ${D}/${libdir}/libedgetpu.so 45 | 46 | install -d ${D}/${includedir} 47 | install -m 755 ${S}/libedgetpu/edgetpu.h ${D}/${includedir} 48 | } 49 | 50 | TOOLCHAIN = "clang" 51 | 52 | INSANE_SKIP:${PN} += "already-stripped" 53 | -------------------------------------------------------------------------------- /recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch: -------------------------------------------------------------------------------- 1 | From 018921ee79d3f30893614b3b2b63b588d8544f73 Mon Sep 17 00:00:00 2001 2 | From: Peter Robinson 3 | Date: Thu, 30 Jan 2020 09:37:15 +0000 4 | Subject: [PATCH] Remove redundant YYLOC global declaration 5 | 6 | Same as the upstream fix for building dtc with gcc 10. 7 | 8 | Upstream-Status: Backport [https://github.com/u-boot/u-boot/commit/018921ee79d3f30893614b3b2b63b588d8544f73] 9 | Signed-off-by: Peter Robinson 10 | --- 11 | scripts/dtc/dtc-lexer.l | 1 - 12 | 1 file changed, 1 deletion(-) 13 | 14 | diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l 15 | index fd825ebba6..24af549977 100644 16 | --- a/scripts/dtc/dtc-lexer.l 17 | +++ b/scripts/dtc/dtc-lexer.l 18 | @@ -38,7 +38,6 @@ LINECOMMENT "//".*\n 19 | #include "srcpos.h" 20 | #include "dtc-parser.tab.h" 21 | 22 | -YYLTYPE yylloc; 23 | extern bool treesource_error; 24 | 25 | /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ 26 | -- 27 | 2.39.0 28 | 29 | -------------------------------------------------------------------------------- /recipes-bsp/u-boot/u-boot-coral_2019.04.bb: -------------------------------------------------------------------------------- 1 | DESCRIPTION = "Coral U-Boot suppporting the Google Coral Dev board/SOM" 2 | require recipes-bsp/u-boot/u-boot-common.inc 3 | require recipes-bsp/u-boot/u-boot.inc 4 | 5 | DEPENDS += " \ 6 | flex-native \ 7 | bison-native \ 8 | ${@oe.utils.conditional('UBOOT_ENV', '', 'coral-boot-script', '', d)} \ 9 | " 10 | 11 | PROVIDES += "u-boot" 12 | 13 | LICENSE = "GPL-2.0-or-later" 14 | LIC_FILES_CHKSUM = "file://Licenses/gpl-2.0.txt;md5=b234ee4d69f5fce4486a80fdaf4a4263" 15 | 16 | SRC_URI = "git://coral.googlesource.com/uboot-imx;protocol=https;branch=master \ 17 | file://0001-Remove-redundant-YYLOC-global-declaration.patch" 18 | SRCREV = "0353addb5507bb259c9232c8b23e3d604eebd878" 19 | 20 | S = "${WORKDIR}/git" 21 | 22 | inherit fsl-u-boot-localversion 23 | 24 | LOCALVERSION ?= "-${SRCBRANCH}" 25 | 26 | BOOT_TOOLS = "imx-boot-tools" 27 | 28 | UBOOT_INITIAL_ENV = "" 29 | 30 | do_deploy:append() { 31 | # Deploy u-boot-nodtb.bin and fsl-imx8m*-XX.dtb for mkimage to generate boot binary 32 | if [ -n "${UBOOT_CONFIG}" ] 33 | then 34 | for config in ${UBOOT_MACHINE}; do 35 | i=$(expr $i + 1); 36 | for type in ${UBOOT_CONFIG}; do 37 | j=$(expr $j + 1); 38 | if [ $j -eq $i ] 39 | then 40 | install -d ${DEPLOYDIR}/${BOOT_TOOLS} 41 | install -m 0777 ${B}/${config}/arch/arm/dts/${UBOOT_DTB_NAME} ${DEPLOYDIR}/${BOOT_TOOLS} 42 | install -m 0777 ${B}/${config}/u-boot-nodtb.bin ${DEPLOYDIR}/${BOOT_TOOLS}/u-boot-nodtb.bin-${MACHINE}-${type} 43 | fi 44 | done 45 | unset j 46 | done 47 | unset i 48 | fi 49 | } 50 | 51 | PACKAGE_ARCH = "${MACHINE_ARCH}" 52 | 53 | COMPATIBLE_MACHINE = "coral-dev" 54 | -------------------------------------------------------------------------------- /recipes-kernel/dtc/dtc-145_git.bb: -------------------------------------------------------------------------------- 1 | SUMMARY = "Device Tree Compiler" 2 | HOMEPAGE = "https://devicetree.org/" 3 | DESCRIPTION = "The Device Tree Compiler is a tool used to manipulate the Open-Firmware-like device tree used by PowerPC kernels." 4 | SECTION = "bootloader" 5 | LICENSE = "GPLv2 | BSD-2-Clause" 6 | DEPENDS = "flex-native bison-native" 7 | 8 | LIC_FILES_CHKSUM = " \ 9 | file://GPL;md5=94d55d512a9ba36caa9b7df079bae19f \ 10 | file://libfdt/libfdt.h;beginline=3;endline=52;md5=fb360963151f8ec2d6c06b055bcbb68c \ 11 | " 12 | 13 | SRC_URI = "git://git.kernel.org/pub/scm/utils/dtc/dtc.git;branch=master \ 14 | file://make_install.patch \ 15 | file://0001-Remove-redundant-YYLOC-global-declaration.patch \ 16 | file://0001-Fix-compiler-warnings-seen-with-musl.patch \ 17 | " 18 | SRCREV = "22a65c5331c22979d416738eb756b9541672e00d" 19 | 20 | UPSTREAM_CHECK_GITTAGREGEX = "v(?P\d+(\.\d+)+)" 21 | 22 | EXTRA_OEMAKE='NO_PYTHON=1 PREFIX="${prefix}" LIBDIR="${libdir}" DESTDIR="${D}"' 23 | 24 | inherit pkgconfig 25 | 26 | S = "${WORKDIR}/git" 27 | 28 | # only install the dtc binary renamed to dtc-145 29 | do_install () { 30 | install -d ${D}/${bindir} 31 | install -m 755 dtc ${D}/${bindir}/dtc-145 32 | } 33 | 34 | PACKAGES =+ "${PN}-misc" 35 | FILES:${PN}-misc = "${bindir}/convert-dtsv0 ${bindir}/ftdump ${bindir}/dtdiff" 36 | 37 | RDEPENDS:${PN}-misc += "bash diffutils" 38 | 39 | BBCLASSEXTEND = "native nativesdk" 40 | -------------------------------------------------------------------------------- /recipes-kernel/dtc/files/0001-Fix-compiler-warnings-seen-with-musl.patch: -------------------------------------------------------------------------------- 1 | From 50034ca2600ae07203f397af6d78e2e9ff16bc02 Mon Sep 17 00:00:00 2001 2 | From: Khem Raj 3 | Date: Sat, 6 Oct 2018 18:12:23 -0700 4 | Subject: [PATCH] Fix compiler warnings seen with musl 5 | 6 | Fixes 7 | 8 | checks.c:975:16: error: format '%ld' expects argument of type 'long 9 | int', but argument 6 has type 'unsigned int' [-Werror=format=] 10 | FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple 11 | of %ld in node %s", 12 | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 | prop->name, prop->val.len, sizeof(cell_t), node->fullpath); 14 | ~~~~~~~~~~~~~~ 15 | checks.c:96:23: note: in definition of macro 'FAIL' 16 | check_msg((c), dti, __VA_ARGS__); \ 17 | ^~~~~~~~~~~ 18 | checks.c: In function 'check_interrupts_property': 19 | checks.c:1166:16: error: format '%ld' expects argument of type 'long 20 | int', but argument 6 has type 'unsigned int' [-Werror=format=] 21 | FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple 22 | of %ld in node %s", 23 | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 24 | irq_prop->name, irq_prop->val.len, sizeof(cell_t), 25 | ~~~~~~~~~~~~~~ 26 | 27 | Upstream-Status: Backport [adapted from an upstream fix] 28 | 29 | Signed-off-by: Khem Raj 30 | --- 31 | checks.c | 4 ++-- 32 | 1 file changed, 2 insertions(+), 2 deletions(-) 33 | 34 | diff --git a/checks.c b/checks.c 35 | index 902f2e3..08a3a29 100644 36 | --- a/checks.c 37 | +++ b/checks.c 38 | @@ -972,7 +972,7 @@ static void check_property_phandle_args(struct check *c, 39 | int cell, cellsize = 0; 40 | 41 | if (prop->val.len % sizeof(cell_t)) { 42 | - FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple of %ld in node %s", 43 | + FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple of %zu in node %s", 44 | prop->name, prop->val.len, sizeof(cell_t), node->fullpath); 45 | return; 46 | } 47 | @@ -1163,7 +1163,7 @@ static void check_interrupts_property(struct check *c, 48 | return; 49 | 50 | if (irq_prop->val.len % sizeof(cell_t)) 51 | - FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple of %ld in node %s", 52 | + FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple of %zu in node %s", 53 | irq_prop->name, irq_prop->val.len, sizeof(cell_t), 54 | node->fullpath); 55 | 56 | -------------------------------------------------------------------------------- /recipes-kernel/dtc/files/0001-Remove-redundant-YYLOC-global-declaration.patch: -------------------------------------------------------------------------------- 1 | From 0e9225eb0dfec51def612b928d2f1836b092bc7e Mon Sep 17 00:00:00 2001 2 | From: Dirk Mueller 3 | Date: Tue, 14 Jan 2020 18:53:41 +0100 4 | Subject: [PATCH] Remove redundant YYLOC global declaration 5 | 6 | gcc 10 will default to -fno-common, which causes this error at link 7 | time: 8 | 9 | (.text+0x0): multiple definition of `yylloc'; dtc-lexer.lex.o (symbol from plugin):(.text+0x0): first defined here 10 | 11 | This is because both dtc-lexer as well as dtc-parser define the same 12 | global symbol yyloc. Before with -fcommon those were merged into one 13 | defintion. The proper solution would be to to mark this as "extern", 14 | however that leads to: 15 | 16 | dtc-lexer.l:26:16: error: redundant redeclaration of 'yylloc' [-Werror=redundant-decls] 17 | 26 | extern YYLTYPE yylloc; 18 | | ^~~~~~ 19 | In file included from dtc-lexer.l:24: 20 | dtc-parser.tab.h:127:16: note: previous declaration of 'yylloc' was here 21 | 127 | extern YYLTYPE yylloc; 22 | | ^~~~~~ 23 | cc1: all warnings being treated as errors 24 | 25 | which means the declaration is completely redundant and can just be 26 | dropped. 27 | 28 | Signed-off-by: Dirk Mueller 29 | Message-Id: <20200114175341.2994-1-dmueller@suse.com> 30 | Signed-off-by: David Gibson 31 | --- 32 | dtc-lexer.l | 1 - 33 | 1 file changed, 1 deletion(-) 34 | 35 | --- a/dtc-lexer.l 36 | +++ b/dtc-lexer.l 37 | @@ -38,7 +38,6 @@ LINECOMMENT "//".*\n 38 | #include "srcpos.h" 39 | #include "dtc-parser.tab.h" 40 | 41 | -YYLTYPE yylloc; 42 | extern bool treesource_error; 43 | 44 | /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ 45 | -------------------------------------------------------------------------------- /recipes-kernel/dtc/files/make_install.patch: -------------------------------------------------------------------------------- 1 | Upstream-Status: Inappropriate [configuration] 2 | 3 | --- a/Makefile 4 | +++ b/Makefile 5 | @@ -18,7 +18,7 @@ CONFIG_LOCALVERSION = 6 | CPPFLAGS = -I libfdt -I . 7 | WARNINGS = -Wall -Wpointer-arith -Wcast-qual -Wnested-externs \ 8 | -Wstrict-prototypes -Wmissing-prototypes -Wredundant-decls -Wshadow 9 | -CFLAGS = -g -Os $(SHAREDLIB_CFLAGS) -Werror $(WARNINGS) 10 | +CFLAGS = -g -Os $(SHAREDLIB_CFLAGS) $(WARNINGS) 11 | 12 | BISON = bison 13 | LEX = flex 14 | @@ -196,8 +196,8 @@ install-bin: all $(SCRIPTS) 15 | install-lib: all 16 | @$(VECHO) INSTALL-LIB 17 | $(INSTALL) -d $(DESTDIR)$(LIBDIR) 18 | - $(INSTALL) $(LIBFDT_lib) $(DESTDIR)$(LIBDIR) 19 | - ln -sf $(notdir $(LIBFDT_lib)) $(DESTDIR)$(LIBDIR)/$(LIBFDT_soname) 20 | + $(INSTALL) $(LIBFDT_lib) $(DESTDIR)$(LIBDIR)/$(LIBFDT_soname) 21 | + ln -sf $(LIBFDT_soname) $(DESTDIR)$(LIBDIR)/$(notdir $(LIBFDT_lib)) 22 | ln -sf $(LIBFDT_soname) $(DESTDIR)$(LIBDIR)/libfdt.$(SHAREDLIB_EXT) 23 | $(INSTALL) -m 644 $(LIBFDT_archive) $(DESTDIR)$(LIBDIR) 24 | 25 | -------------------------------------------------------------------------------- /recipes-kernel/kernel-modules/kernel-module-qca6174/0001-MLK-18491-02-qcacld-2.0-fix-the-overflow-of-bounce-b.patch: -------------------------------------------------------------------------------- 1 | From 16573cbb9c82218f93741a9bc873242c012ac061 Mon Sep 17 00:00:00 2001 2 | From: Hangtian Zhu 3 | Date: Thu, 14 Jun 2018 11:10:05 +0800 4 | Subject: [PATCH 22/23] MLK-18491-02 qcacld-2.0: fix the overflow of bounce 5 | buffer 6 | 7 | Patch a41baa51cbc5("MLK-18491 qcacld-2.0: avoid overflow of bounce buffer") 8 | is not reasonable to fix overflow of bounce buffer issue. 9 | 10 | The patch is released by Qualcomm to fix the issue. 11 | (Case Number:03515221) 12 | 13 | Signed-off-by: Hangtian Zhu 14 | --- 15 | CORE/SERVICES/HTC/htc.c | 2 +- 16 | CORE/SERVICES/HTC/htc_send.c | 28 ++++++++++++++-------------- 17 | 2 files changed, 15 insertions(+), 15 deletions(-) 18 | 19 | diff --git a/CORE/SERVICES/HTC/htc.c b/CORE/SERVICES/HTC/htc.c 20 | index 1e2450d..09936a0 100644 21 | --- a/CORE/SERVICES/HTC/htc.c 22 | +++ b/CORE/SERVICES/HTC/htc.c 23 | @@ -657,7 +657,7 @@ static void ResetEndpointStates(HTC_TARGET *target) 24 | INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBufferHoldQueue); 25 | pEndpoint->target = target; 26 | //pEndpoint->TxCreditFlowEnabled = (A_BOOL)htc_credit_flow; 27 | - pEndpoint->TxCreditFlowEnabled = (A_BOOL)0; 28 | + pEndpoint->TxCreditFlowEnabled = (A_BOOL)1; 29 | adf_os_atomic_init(&pEndpoint->TxProcessCount); 30 | } 31 | } 32 | diff --git a/CORE/SERVICES/HTC/htc_send.c b/CORE/SERVICES/HTC/htc_send.c 33 | index 1a3dd28..19d8065 100644 34 | --- a/CORE/SERVICES/HTC/htc_send.c 35 | +++ b/CORE/SERVICES/HTC/htc_send.c 36 | @@ -105,12 +105,12 @@ void HTCGetControlEndpointTxHostCredits(HTC_HANDLE HTCHandle, int *credits) 37 | 38 | static INLINE void RestoreTxPacket(HTC_TARGET *target, HTC_PACKET *pPacket) 39 | { 40 | + adf_nbuf_t netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket); 41 | if (pPacket->PktInfo.AsTx.Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) { 42 | - adf_nbuf_t netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket); 43 | adf_nbuf_unmap(target->osdev, netbuf, ADF_OS_DMA_TO_DEVICE); 44 | - adf_nbuf_pull_head(netbuf, sizeof(HTC_FRAME_HDR)); 45 | pPacket->PktInfo.AsTx.Flags &= ~HTC_TX_PACKET_FLAG_FIXUP_NETBUF; 46 | } 47 | + adf_nbuf_pull_head(netbuf, sizeof(HTC_FRAME_HDR)); 48 | 49 | } 50 | 51 | @@ -641,12 +641,11 @@ static A_STATUS HTCIssuePackets(HTC_TARGET *target, 52 | * that is already mapped, or a non-data netbuf that needs to be 53 | * mapped. 54 | */ 55 | - if (pPacket->PktInfo.AsTx.Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) { 56 | - adf_nbuf_map( 57 | - target->osdev, 58 | - GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket), 59 | - ADF_OS_DMA_TO_DEVICE); 60 | - } 61 | + pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF; 62 | + adf_nbuf_map( 63 | + target->osdev, 64 | + GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket), 65 | + ADF_OS_DMA_TO_DEVICE); 66 | } 67 | LOCK_HTC_TX(target); 68 | /* store in look up queue to match completions */ 69 | @@ -1261,12 +1260,13 @@ A_STATUS HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue) 70 | * mapped. This only applies to non-data frames, since data frames 71 | * were already mapped as they entered into the driver. 72 | */ 73 | - adf_nbuf_map( 74 | - target->osdev, 75 | - GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket), 76 | - ADF_OS_DMA_TO_DEVICE); 77 | - 78 | - pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF; 79 | + if(!IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) { 80 | + pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF; 81 | + adf_nbuf_map( 82 | + target->osdev, 83 | + GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket), 84 | + ADF_OS_DMA_TO_DEVICE); 85 | + } 86 | } HTC_PACKET_QUEUE_ITERATE_END; 87 | 88 | HTCTrySend(target,pEndpoint,pPktQueue); 89 | -- 90 | 1.9.1 91 | 92 | -------------------------------------------------------------------------------- /recipes-kernel/kernel-modules/kernel-module-qca6174_2.1.bb: -------------------------------------------------------------------------------- 1 | require kernel-module-qcacld-lea.inc 2 | 3 | SUMMARY = "Qualcomm WiFi driver for QCA module 6174" 4 | 5 | SRC_URI += "file://0001-MLK-18491-02-qcacld-2.0-fix-the-overflow-of-bounce-b.patch" 6 | 7 | EXTRA_OEMAKE += " \ 8 | CONFIG_ROME_IF=pci \ 9 | CONFIG_WLAN_FEATURE_11W=y \ 10 | CONFIG_WLAN_FEATURE_FILS=y \ 11 | CONFIG_WLAN_WAPI_MODE_11AC_DISABLE=y \ 12 | MODNAME=qca6174 \ 13 | " 14 | 15 | RDEPENDS_${PN} += "firmware-qca6174" 16 | -------------------------------------------------------------------------------- /recipes-kernel/kernel-modules/kernel-module-qcacld-lea.inc: -------------------------------------------------------------------------------- 1 | SUMMARY = "Qualcomm WiFi driver for QCA module 9377 and 6174" 2 | LICENSE = "BSD & GPLv2" 3 | LIC_FILES_CHKSUM = "file://CORE/HDD/src/wlan_hdd_main.c;beginline=1;endline=20;md5=ec8d62116b13db773825ebf7cf91be1d;" 4 | 5 | QCACLD_SRC ?= "git://source.codeaurora.org/external/imx/qcacld-2.0-imx.git;protocol=https" 6 | SRC_URI = "${QCACLD_SRC};branch=IMX_CNSS.LEA.NRT_2.0" 7 | SRCREV = "e008d2578b09f1f593f65ede48529a52312e3957" 8 | 9 | S = "${WORKDIR}/git" 10 | 11 | inherit module 12 | 13 | EXTRA_OEMAKE += " \ 14 | CONFIG_CFG80211_INTERNAL_REGDB=y \ 15 | CONFIG_HDD_WLAN_WAIT_TIME=10000 \ 16 | CONFIG_LINUX_QCMBR=y \ 17 | CONFIG_NON_QC_PLATFORM=y \ 18 | CONFIG_PMF_SUPPORT=y \ 19 | TARGET_BUILD_VARIANT=user \ 20 | " 21 | 22 | COMPATIBLE_MACHINE = "(imx)" 23 | COMPATIBLE_HOST_libc-musl = 'null' 24 | -------------------------------------------------------------------------------- /recipes-kernel/linux-firmware/linux-firmware_%.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" 2 | 3 | INSANE_SKIP:linux-firmware-ath10k = "ldflags" 4 | -------------------------------------------------------------------------------- /recipes-kernel/linux/files/defconfig: -------------------------------------------------------------------------------- 1 | CONFIG_SYSVIPC=y 2 | CONFIG_POSIX_MQUEUE=y 3 | CONFIG_AUDIT=y 4 | CONFIG_NO_HZ_IDLE=y 5 | CONFIG_HIGH_RES_TIMERS=y 6 | CONFIG_IRQ_TIME_ACCOUNTING=y 7 | CONFIG_BSD_PROCESS_ACCT=y 8 | CONFIG_BSD_PROCESS_ACCT_V3=y 9 | CONFIG_TASKSTATS=y 10 | CONFIG_TASK_DELAY_ACCT=y 11 | CONFIG_TASK_XACCT=y 12 | CONFIG_TASK_IO_ACCOUNTING=y 13 | CONFIG_IKCONFIG=y 14 | CONFIG_IKCONFIG_PROC=y 15 | CONFIG_NUMA_BALANCING=y 16 | CONFIG_MEMCG=y 17 | CONFIG_MEMCG_SWAP=y 18 | CONFIG_BLK_CGROUP=y 19 | CONFIG_CGROUP_PIDS=y 20 | CONFIG_CGROUP_HUGETLB=y 21 | CONFIG_CPUSETS=y 22 | CONFIG_CGROUP_DEVICE=y 23 | CONFIG_CGROUP_CPUACCT=y 24 | CONFIG_CGROUP_PERF=y 25 | CONFIG_NAMESPACES=y 26 | CONFIG_USER_NS=y 27 | CONFIG_SCHED_AUTOGROUP=y 28 | CONFIG_RELAY=y 29 | CONFIG_BLK_DEV_INITRD=y 30 | CONFIG_EXPERT=y 31 | CONFIG_KALLSYMS_ALL=y 32 | # CONFIG_COMPAT_BRK is not set 33 | CONFIG_PROFILING=y 34 | CONFIG_JUMP_LABEL=y 35 | CONFIG_MODULES=y 36 | CONFIG_MODULE_UNLOAD=y 37 | # CONFIG_IOSCHED_DEADLINE is not set 38 | CONFIG_ARCH_SUNXI=y 39 | CONFIG_ARCH_ALPINE=y 40 | CONFIG_ARCH_BCM2835=y 41 | CONFIG_ARCH_BCM_IPROC=y 42 | CONFIG_ARCH_BERLIN=y 43 | CONFIG_ARCH_BRCMSTB=y 44 | CONFIG_ARCH_EXYNOS=y 45 | CONFIG_ARCH_LAYERSCAPE=y 46 | CONFIG_ARCH_LG1K=y 47 | CONFIG_ARCH_HISI=y 48 | CONFIG_ARCH_MEDIATEK=y 49 | CONFIG_ARCH_MESON=y 50 | CONFIG_ARCH_MVEBU=y 51 | CONFIG_ARCH_QCOM=y 52 | CONFIG_ARCH_ROCKCHIP=y 53 | CONFIG_ARCH_SEATTLE=y 54 | CONFIG_ARCH_RENESAS=y 55 | CONFIG_ARCH_R8A7795=y 56 | CONFIG_ARCH_R8A7796=y 57 | CONFIG_ARCH_STRATIX10=y 58 | CONFIG_ARCH_TEGRA=y 59 | CONFIG_ARCH_SPRD=y 60 | CONFIG_ARCH_THUNDER=y 61 | CONFIG_ARCH_THUNDER2=y 62 | CONFIG_ARCH_UNIPHIER=y 63 | CONFIG_ARCH_VEXPRESS=y 64 | CONFIG_ARCH_XGENE=y 65 | CONFIG_ARCH_ZX=y 66 | CONFIG_ARCH_ZYNQMP=y 67 | CONFIG_ARCH_FSL_IMX8QM=y 68 | CONFIG_ARCH_FSL_IMX8QP=y 69 | CONFIG_ARCH_FSL_IMX8QXP=y 70 | CONFIG_ARCH_FSL_IMX8MQ=y 71 | CONFIG_ARCH_FSL_IMX8MM=y 72 | CONFIG_PCI=y 73 | CONFIG_HOTPLUG_PCI_PCIE=y 74 | CONFIG_PCI_IOV=y 75 | CONFIG_HOTPLUG_PCI=y 76 | CONFIG_HOTPLUG_PCI_ACPI=y 77 | CONFIG_PCI_IMX6=y 78 | CONFIG_PCI_HISI=y 79 | CONFIG_PCIE_KIRIN=y 80 | CONFIG_PCI_AARDVARK=y 81 | CONFIG_PCIE_RCAR=y 82 | CONFIG_PCI_HOST_GENERIC=y 83 | CONFIG_PCI_XGENE=y 84 | CONFIG_PCIE_ROCKCHIP=m 85 | CONFIG_ARM64_VA_BITS_48=y 86 | CONFIG_SCHED_MC=y 87 | CONFIG_NUMA=y 88 | CONFIG_PREEMPT=y 89 | CONFIG_KSM=y 90 | CONFIG_TRANSPARENT_HUGEPAGE=y 91 | CONFIG_CMA=y 92 | CONFIG_SECCOMP=y 93 | CONFIG_KEXEC=y 94 | CONFIG_CRASH_DUMP=y 95 | CONFIG_XEN=y 96 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 97 | CONFIG_COMPAT=y 98 | CONFIG_PM_DEBUG=y 99 | CONFIG_PM_TEST_SUSPEND=y 100 | CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y 101 | CONFIG_ARM_CPUIDLE=y 102 | CONFIG_CPU_FREQ=y 103 | CONFIG_CPU_FREQ_STAT=y 104 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 105 | CONFIG_CPU_FREQ_GOV_POWERSAVE=y 106 | CONFIG_CPU_FREQ_GOV_USERSPACE=y 107 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y 108 | CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y 109 | CONFIG_CPU_FREQ_GOV_INTERACTIVE=y 110 | CONFIG_CPUFREQ_DT=y 111 | CONFIG_ARM_BIG_LITTLE_CPUFREQ=y 112 | CONFIG_ARM_IMX8_CPUFREQ=y 113 | CONFIG_ARM_IMX8MQ_CPUFREQ=y 114 | CONFIG_ARM_SCPI_CPUFREQ=y 115 | CONFIG_ACPI_CPPC_CPUFREQ=m 116 | CONFIG_NET=y 117 | CONFIG_PACKET=y 118 | CONFIG_UNIX=y 119 | CONFIG_INET=y 120 | CONFIG_IP_MULTICAST=y 121 | CONFIG_IP_PNP=y 122 | CONFIG_IP_PNP_DHCP=y 123 | CONFIG_IP_PNP_BOOTP=y 124 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m 125 | CONFIG_INET6_XFRM_MODE_TUNNEL=m 126 | CONFIG_INET6_XFRM_MODE_BEET=m 127 | CONFIG_IPV6_SIT=m 128 | CONFIG_NETFILTER=y 129 | CONFIG_NF_CONNTRACK=m 130 | CONFIG_NF_CONNTRACK_EVENTS=y 131 | CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m 132 | CONFIG_NETFILTER_XT_TARGET_LOG=m 133 | CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m 134 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m 135 | CONFIG_NF_CONNTRACK_IPV4=m 136 | CONFIG_IP_NF_IPTABLES=m 137 | CONFIG_IP_NF_FILTER=m 138 | CONFIG_IP_NF_TARGET_REJECT=m 139 | CONFIG_IP_NF_NAT=m 140 | CONFIG_IP_NF_TARGET_MASQUERADE=m 141 | CONFIG_IP_NF_MANGLE=m 142 | CONFIG_NF_CONNTRACK_IPV6=m 143 | CONFIG_IP6_NF_IPTABLES=m 144 | CONFIG_IP6_NF_FILTER=m 145 | CONFIG_IP6_NF_TARGET_REJECT=m 146 | CONFIG_IP6_NF_MANGLE=m 147 | CONFIG_IP6_NF_NAT=m 148 | CONFIG_IP6_NF_TARGET_MASQUERADE=m 149 | CONFIG_BRIDGE=m 150 | CONFIG_BRIDGE_VLAN_FILTERING=y 151 | CONFIG_VLAN_8021Q=m 152 | CONFIG_VLAN_8021Q_GVRP=y 153 | CONFIG_VLAN_8021Q_MVRP=y 154 | CONFIG_LLC2=y 155 | CONFIG_BPF_JIT=y 156 | CONFIG_CAN=y 157 | CONFIG_CAN_FLEXCAN=y 158 | CONFIG_BT=y 159 | CONFIG_BT_RFCOMM=y 160 | CONFIG_BT_RFCOMM_TTY=y 161 | CONFIG_BT_BNEP=y 162 | CONFIG_BT_BNEP_MC_FILTER=y 163 | CONFIG_BT_BNEP_PROTO_FILTER=y 164 | CONFIG_BT_HIDP=y 165 | # CONFIG_BT_HS is not set 166 | # CONFIG_BT_LE is not set 167 | CONFIG_BT_LEDS=y 168 | CONFIG_BT_HCIUART=y 169 | CONFIG_BT_HCIUART_BCSP=y 170 | CONFIG_BT_HCIUART_ATH3K=y 171 | CONFIG_BT_HCIUART_3WIRE=y 172 | CONFIG_BT_HCIUART_BCM=y 173 | CONFIG_BT_HCIUART_QCA=y 174 | CONFIG_BT_HCIVHCI=y 175 | CONFIG_CFG80211=y 176 | CONFIG_NL80211_TESTMODE=y 177 | CONFIG_CFG80211_INTERNAL_REGDB=y 178 | CONFIG_CFG80211_WEXT=y 179 | CONFIG_MAC80211=y 180 | CONFIG_MAC80211_LEDS=y 181 | CONFIG_NET_9P=y 182 | CONFIG_NET_9P_VIRTIO=y 183 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 184 | CONFIG_DEVTMPFS=y 185 | CONFIG_DEVTMPFS_MOUNT=y 186 | CONFIG_DMA_CMA=y 187 | CONFIG_CMA_SIZE_MBYTES=320 188 | CONFIG_ARM_CCI400_PMU=y 189 | CONFIG_ARM_CCI5xx_PMU=y 190 | CONFIG_MTD=y 191 | CONFIG_MTD_CMDLINE_PARTS=y 192 | CONFIG_MTD_BLOCK=y 193 | CONFIG_MTD_RAM=y 194 | CONFIG_MTD_DATAFLASH=y 195 | CONFIG_MTD_M25P80=y 196 | CONFIG_MTD_SLRAM=y 197 | CONFIG_MTD_NAND=y 198 | CONFIG_MTD_NAND_DENALI_DT=y 199 | CONFIG_MTD_NAND_GPMI_NAND=y 200 | CONFIG_MTD_SPI_NOR=y 201 | # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set 202 | CONFIG_SPI_FSL_QUADSPI=y 203 | CONFIG_SPI_FSL_FLEXSPI=y 204 | CONFIG_MTD_UBI=y 205 | CONFIG_OF_OVERLAY=y 206 | CONFIG_BLK_DEV_LOOP=y 207 | CONFIG_BLK_DEV_NBD=m 208 | CONFIG_XEN_BLKDEV_BACKEND=y 209 | CONFIG_VIRTIO_BLK=y 210 | CONFIG_BLK_DEV_NVME=m 211 | CONFIG_SENSORS_FXOS8700=y 212 | CONFIG_SENSORS_FXAS2100X=y 213 | CONFIG_SRAM=y 214 | CONFIG_EEPROM_AT25=m 215 | # CONFIG_SCSI_PROC_FS is not set 216 | CONFIG_BLK_DEV_SD=y 217 | CONFIG_SCSI_SAS_ATA=y 218 | CONFIG_SCSI_HISI_SAS=y 219 | CONFIG_SCSI_HISI_SAS_PCI=y 220 | CONFIG_ATA=y 221 | CONFIG_SATA_AHCI=y 222 | CONFIG_SATA_AHCI_PLATFORM=y 223 | CONFIG_AHCI_IMX=y 224 | CONFIG_AHCI_CEVA=y 225 | CONFIG_AHCI_MVEBU=y 226 | CONFIG_AHCI_XGENE=y 227 | CONFIG_AHCI_QORIQ=y 228 | CONFIG_SATA_SIL24=y 229 | CONFIG_SATA_RCAR=y 230 | CONFIG_PATA_PLATFORM=y 231 | CONFIG_PATA_OF_PLATFORM=y 232 | CONFIG_NETDEVICES=y 233 | CONFIG_MACVLAN=m 234 | CONFIG_MACVTAP=m 235 | CONFIG_TUN=y 236 | CONFIG_VETH=m 237 | CONFIG_VIRTIO_NET=y 238 | CONFIG_AMD_XGBE=y 239 | CONFIG_NET_XGENE=y 240 | CONFIG_MACB=y 241 | CONFIG_HNS_DSAF=y 242 | CONFIG_HNS_ENET=y 243 | CONFIG_E1000E=y 244 | CONFIG_IGB=y 245 | CONFIG_IGBVF=y 246 | CONFIG_MVNETA=y 247 | CONFIG_MVPP2=y 248 | CONFIG_SKY2=y 249 | CONFIG_QCOM_EMAC=m 250 | CONFIG_RAVB=y 251 | CONFIG_SMC91X=y 252 | CONFIG_SMSC911X=y 253 | CONFIG_STMMAC_ETH=m 254 | CONFIG_MDIO_BUS_MUX_MMIOREG=y 255 | CONFIG_AT803X_PHY=y 256 | CONFIG_MARVELL_PHY=m 257 | CONFIG_MESON_GXL_PHY=m 258 | CONFIG_MICREL_PHY=y 259 | CONFIG_NXP_TJA110X_PHY=y 260 | CONFIG_REALTEK_PHY=m 261 | CONFIG_ROCKCHIP_PHY=y 262 | CONFIG_USB_PEGASUS=m 263 | CONFIG_USB_RTL8150=m 264 | CONFIG_USB_RTL8152=m 265 | CONFIG_USB_USBNET=m 266 | CONFIG_USB_NET_DM9601=m 267 | CONFIG_USB_NET_SR9800=m 268 | CONFIG_USB_NET_SMSC75XX=m 269 | CONFIG_USB_NET_SMSC95XX=m 270 | CONFIG_USB_NET_PLUSB=m 271 | CONFIG_USB_NET_MCS7830=m 272 | # CONFIG_WLAN_VENDOR_ATH is not set 273 | CONFIG_BRCMFMAC=m 274 | CONFIG_BRCMFMAC_PCIE=y 275 | CONFIG_HOSTAP=y 276 | CONFIG_RTL_CARDS=m 277 | # CONFIG_WLAN_VENDOR_TI is not set 278 | CONFIG_XEN_NETDEV_BACKEND=m 279 | CONFIG_IVSHMEM_NET=y 280 | CONFIG_INPUT_POLLDEV=y 281 | CONFIG_INPUT_EVDEV=y 282 | CONFIG_KEYBOARD_ADC=m 283 | CONFIG_KEYBOARD_GPIO=y 284 | CONFIG_KEYBOARD_IMX_SC_PWRKEY=y 285 | CONFIG_KEYBOARD_CROS_EC=y 286 | CONFIG_INPUT_TOUCHSCREEN=y 287 | CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=y 288 | CONFIG_INPUT_MISC=y 289 | CONFIG_INPUT_PM8941_PWRKEY=y 290 | CONFIG_INPUT_HISI_POWERKEY=y 291 | CONFIG_INPUT_MPL3115=y 292 | CONFIG_INPUT_ISL29023=y 293 | # CONFIG_SERIO_SERPORT is not set 294 | CONFIG_SERIO_AMBAKMI=y 295 | CONFIG_LEGACY_PTY_COUNT=16 296 | CONFIG_SERIAL_8250=y 297 | CONFIG_SERIAL_8250_CONSOLE=y 298 | CONFIG_SERIAL_8250_EXTENDED=y 299 | CONFIG_SERIAL_8250_SHARE_IRQ=y 300 | CONFIG_SERIAL_8250_BCM2835AUX=y 301 | CONFIG_SERIAL_8250_DW=y 302 | CONFIG_SERIAL_8250_MT6577=y 303 | CONFIG_SERIAL_8250_UNIPHIER=y 304 | CONFIG_SERIAL_OF_PLATFORM=y 305 | CONFIG_SERIAL_AMBA_PL011=y 306 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 307 | CONFIG_SERIAL_MESON=y 308 | CONFIG_SERIAL_MESON_CONSOLE=y 309 | CONFIG_SERIAL_SAMSUNG=y 310 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y 311 | CONFIG_SERIAL_TEGRA=y 312 | CONFIG_SERIAL_IMX_CONSOLE=y 313 | CONFIG_SERIAL_SH_SCI=y 314 | CONFIG_SERIAL_SH_SCI_NR_UARTS=11 315 | CONFIG_SERIAL_SH_SCI_CONSOLE=y 316 | CONFIG_SERIAL_MSM=y 317 | CONFIG_SERIAL_MSM_CONSOLE=y 318 | CONFIG_SERIAL_XILINX_PS_UART=y 319 | CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y 320 | CONFIG_SERIAL_FSL_LPUART=y 321 | CONFIG_SERIAL_FSL_LPUART_CONSOLE=y 322 | CONFIG_SERIAL_MVEBU_UART=y 323 | CONFIG_SERIAL_DEV_BUS=y 324 | CONFIG_SERIAL_DEV_CTRL_TTYPORT=y 325 | CONFIG_VIRTIO_CONSOLE=y 326 | CONFIG_I2C_CHARDEV=y 327 | CONFIG_I2C_MUX_PCA954x=y 328 | CONFIG_I2C_BCM2835=m 329 | CONFIG_I2C_DESIGNWARE_PLATFORM=y 330 | CONFIG_I2C_IMX=y 331 | CONFIG_I2C_IMX_LPI2C=y 332 | CONFIG_I2C_MESON=y 333 | CONFIG_I2C_MV64XXX=y 334 | CONFIG_I2C_PXA=y 335 | CONFIG_I2C_QUP=y 336 | CONFIG_I2C_RK3X=y 337 | CONFIG_I2C_SH_MOBILE=y 338 | CONFIG_I2C_TEGRA=y 339 | CONFIG_I2C_UNIPHIER_F=y 340 | CONFIG_I2C_RCAR=y 341 | CONFIG_I2C_CROS_EC_TUNNEL=y 342 | CONFIG_XEN_I2C_BACKEND=y 343 | CONFIG_I2C_RPBUS=y 344 | CONFIG_SPI=y 345 | CONFIG_SPI_BCM2835=m 346 | CONFIG_SPI_BCM2835AUX=m 347 | CONFIG_SPI_FSL_LPSPI=y 348 | CONFIG_SPI_IMX=y 349 | CONFIG_SPI_MESON_SPICC=m 350 | CONFIG_SPI_MESON_SPIFC=m 351 | CONFIG_SPI_ORION=y 352 | CONFIG_SPI_PL022=y 353 | CONFIG_SPI_ROCKCHIP=y 354 | CONFIG_SPI_QUP=y 355 | CONFIG_SPI_S3C64XX=y 356 | CONFIG_SPI_SPIDEV=y 357 | CONFIG_SPI_SLAVE=y 358 | CONFIG_SPI_SLAVE_TIME=y 359 | CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y 360 | CONFIG_SPMI=y 361 | CONFIG_PINCTRL_SINGLE=y 362 | CONFIG_PINCTRL_MAX77620=y 363 | CONFIG_PINCTRL_IPQ8074=y 364 | CONFIG_PINCTRL_MSM8916=y 365 | CONFIG_PINCTRL_MSM8994=y 366 | CONFIG_PINCTRL_MSM8996=y 367 | CONFIG_PINCTRL_QDF2XXX=y 368 | CONFIG_PINCTRL_QCOM_SPMI_PMIC=y 369 | CONFIG_GPIO_SYSFS=y 370 | CONFIG_GPIO_DWAPB=y 371 | CONFIG_GPIO_PL061=y 372 | CONFIG_GPIO_RCAR=y 373 | CONFIG_GPIO_XGENE=y 374 | CONFIG_GPIO_XGENE_SB=y 375 | CONFIG_GPIO_MAX732X=y 376 | CONFIG_GPIO_PCA953X=y 377 | CONFIG_GPIO_PCA953X_IRQ=y 378 | CONFIG_GPIO_MAX77620=y 379 | CONFIG_POWER_AVS=y 380 | CONFIG_ROCKCHIP_IODOMAIN=y 381 | CONFIG_POWER_RESET_MSM=y 382 | CONFIG_POWER_RESET_XGENE=y 383 | CONFIG_POWER_RESET_SYSCON=y 384 | CONFIG_SYSCON_REBOOT_MODE=y 385 | CONFIG_BATTERY_BQ27XXX=y 386 | CONFIG_SENSORS_ARM_SCPI=y 387 | CONFIG_SENSORS_LM90=m 388 | CONFIG_SENSORS_INA2XX=m 389 | # CONFIG_MXC_MMA8451 is not set 390 | CONFIG_THERMAL_WRITABLE_TRIPS=y 391 | CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y 392 | CONFIG_CPU_THERMAL=y 393 | CONFIG_THERMAL_EMULATION=y 394 | CONFIG_IMX8M_THERMAL=y 395 | CONFIG_IMX8MM_THERMAL=y 396 | CONFIG_IMX_SC_THERMAL=y 397 | CONFIG_DEVICE_THERMAL=y 398 | CONFIG_ROCKCHIP_THERMAL=m 399 | CONFIG_EXYNOS_THERMAL=y 400 | CONFIG_WATCHDOG=y 401 | CONFIG_S3C2410_WATCHDOG=y 402 | CONFIG_IMX2_WDT=y 403 | CONFIG_IMX8_WDT=y 404 | CONFIG_MESON_GXBB_WATCHDOG=m 405 | CONFIG_MESON_WATCHDOG=m 406 | CONFIG_RENESAS_WDT=y 407 | CONFIG_UNIPHIER_WATCHDOG=y 408 | CONFIG_BCM2835_WDT=y 409 | CONFIG_MFD_AXP20X_RSB=y 410 | CONFIG_MFD_CROS_EC=y 411 | CONFIG_MFD_CROS_EC_I2C=y 412 | CONFIG_MFD_CROS_EC_SPI=y 413 | CONFIG_MFD_EXYNOS_LPASS=m 414 | CONFIG_MFD_HI6421_PMIC=y 415 | CONFIG_MFD_HI655X_PMIC=y 416 | CONFIG_MFD_MAX77620=y 417 | CONFIG_MFD_SPMI_PMIC=y 418 | CONFIG_MFD_RK808=y 419 | CONFIG_MFD_SEC_CORE=y 420 | CONFIG_MFD_BD71837=y 421 | CONFIG_REGULATOR_FIXED_VOLTAGE=y 422 | CONFIG_REGULATOR_AXP20X=y 423 | CONFIG_REGULATOR_FAN53555=y 424 | CONFIG_REGULATOR_GPIO=y 425 | CONFIG_REGULATOR_HI6421V530=y 426 | CONFIG_REGULATOR_HI655X=y 427 | CONFIG_REGULATOR_MAX77620=y 428 | CONFIG_REGULATOR_PFUZE100=y 429 | CONFIG_REGULATOR_PWM=y 430 | CONFIG_REGULATOR_QCOM_SMD_RPM=y 431 | CONFIG_REGULATOR_QCOM_SPMI=y 432 | CONFIG_REGULATOR_RK808=y 433 | CONFIG_REGULATOR_S2MPS11=y 434 | CONFIG_REGULATOR_BD71837=y 435 | CONFIG_RC_CORE=y 436 | CONFIG_RC_DEVICES=y 437 | CONFIG_IR_GPIO_CIR=y 438 | CONFIG_MEDIA_SUPPORT=y 439 | CONFIG_MEDIA_CAMERA_SUPPORT=y 440 | CONFIG_MEDIA_ANALOG_TV_SUPPORT=y 441 | CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y 442 | CONFIG_MEDIA_CEC_SUPPORT=y 443 | CONFIG_MEDIA_CONTROLLER=y 444 | CONFIG_VIDEO_V4L2_SUBDEV_API=y 445 | # CONFIG_DVB_NET is not set 446 | CONFIG_MEDIA_USB_SUPPORT=y 447 | CONFIG_USB_VIDEO_CLASS=m 448 | CONFIG_V4L_PLATFORM_DRIVERS=y 449 | CONFIG_VIDEO_MXC_CAPTURE=y 450 | CONFIG_VIDEO_MX8_CAPTURE=y 451 | CONFIG_GMSL_MAX9286=y 452 | CONFIG_VIDEO_MXC_CSI_CAMERA=y 453 | CONFIG_MXC_MIPI_CSI=y 454 | CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y 455 | CONFIG_V4L_MEM2MEM_DRIVERS=y 456 | CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m 457 | CONFIG_VIDEO_SAMSUNG_S5P_MFC=m 458 | CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m 459 | CONFIG_VIDEO_RENESAS_FCP=m 460 | CONFIG_VIDEO_RENESAS_VSP1=m 461 | CONFIG_IMX_DPU_CORE=y 462 | CONFIG_IMX_DCSS_CORE=y 463 | CONFIG_IMX_LCDIF_CORE=y 464 | CONFIG_DRM=y 465 | CONFIG_DRM_NOUVEAU=m 466 | CONFIG_DRM_EXYNOS=m 467 | CONFIG_DRM_EXYNOS5433_DECON=y 468 | CONFIG_DRM_EXYNOS7_DECON=y 469 | CONFIG_DRM_EXYNOS_DSI=y 470 | # CONFIG_DRM_EXYNOS_DP is not set 471 | CONFIG_DRM_EXYNOS_HDMI=y 472 | CONFIG_DRM_EXYNOS_MIC=y 473 | CONFIG_DRM_ROCKCHIP=m 474 | CONFIG_ROCKCHIP_ANALOGIX_DP=y 475 | CONFIG_ROCKCHIP_CDN_DP=y 476 | CONFIG_ROCKCHIP_DW_HDMI=y 477 | CONFIG_ROCKCHIP_DW_MIPI_DSI=y 478 | CONFIG_ROCKCHIP_INNO_HDMI=y 479 | CONFIG_DRM_RCAR_DU=m 480 | CONFIG_DRM_RCAR_LVDS=y 481 | CONFIG_DRM_RCAR_VSP=y 482 | CONFIG_DRM_MSM=m 483 | CONFIG_DRM_TEGRA=m 484 | CONFIG_DRM_PANEL_SIMPLE=y 485 | CONFIG_DRM_PANEL_SEIKO_43WVF1G=y 486 | CONFIG_DRM_PANEL_RAYDIUM_RM67191=y 487 | CONFIG_DRM_NXP_SEIKO_43WVFIG=y 488 | CONFIG_DRM_I2C_ADV7511=y 489 | CONFIG_DRM_ITE_IT6263=y 490 | CONFIG_DRM_IMX_PARALLEL_DISPLAY=y 491 | CONFIG_DRM_IMX_TVE=y 492 | CONFIG_DRM_IMX_LDB=y 493 | CONFIG_DRM_IMX_HDMI=y 494 | CONFIG_DRM_IMX_NWL_DSI=y 495 | CONFIG_DRM_IMX_SEC_DSIM=y 496 | CONFIG_DRM_IMX_HDP=y 497 | CONFIG_IMX_HDP_CEC=y 498 | CONFIG_DRM_VC4=m 499 | CONFIG_DRM_HISI_KIRIN=m 500 | CONFIG_DRM_MXSFB=y 501 | CONFIG_DRM_MESON=m 502 | CONFIG_FB_IMX64=y 503 | CONFIG_FB_IMX64_DEBUG=y 504 | CONFIG_FB_ARMCLCD=y 505 | CONFIG_FB_MXC_DISP_FRAMEWORK=y 506 | CONFIG_BACKLIGHT_GENERIC=m 507 | CONFIG_BACKLIGHT_PWM=y 508 | CONFIG_BACKLIGHT_LP855X=m 509 | CONFIG_FRAMEBUFFER_CONSOLE=y 510 | CONFIG_LOGO=y 511 | # CONFIG_LOGO_LINUX_MONO is not set 512 | # CONFIG_LOGO_LINUX_VGA16 is not set 513 | CONFIG_SOUND=y 514 | CONFIG_SND=y 515 | CONFIG_SND_USB_AUDIO=m 516 | CONFIG_SND_SOC=y 517 | CONFIG_SND_BCM2835_SOC_I2S=m 518 | CONFIG_SND_SOC_FSL_ACM=y 519 | CONFIG_SND_IMX_SOC=y 520 | CONFIG_SND_SOC_IMX_AK4458=y 521 | CONFIG_SND_SOC_IMX_AK5558=y 522 | CONFIG_SND_SOC_IMX_AK4497=y 523 | CONFIG_SND_SOC_IMX_WM8960=y 524 | CONFIG_SND_SOC_IMX_WM8524=y 525 | CONFIG_SND_SOC_IMX_CS42888=y 526 | CONFIG_SND_SOC_IMX_WM8962=y 527 | CONFIG_SND_SOC_IMX_MICFIL=y 528 | CONFIG_SND_SOC_IMX_RPMSG=y 529 | CONFIG_SND_SOC_IMX_MQS=y 530 | CONFIG_SND_SOC_IMX_SPDIF=y 531 | CONFIG_SND_SOC_IMX_AMIX=y 532 | CONFIG_SND_SOC_IMX_CDNHDMI=y 533 | CONFIG_SND_SOC_IMX_DSP=y 534 | CONFIG_SND_SOC_SAMSUNG=y 535 | CONFIG_SND_SOC_RCAR=y 536 | CONFIG_SND_SOC_AK4613=y 537 | CONFIG_SND_SIMPLE_CARD=y 538 | CONFIG_HID_A4TECH=y 539 | CONFIG_HID_APPLE=y 540 | CONFIG_HID_BELKIN=y 541 | CONFIG_HID_CHERRY=y 542 | CONFIG_HID_CHICONY=y 543 | CONFIG_HID_CYPRESS=y 544 | CONFIG_HID_EZKEY=y 545 | CONFIG_HID_KENSINGTON=y 546 | CONFIG_HID_LOGITECH=y 547 | CONFIG_HID_MICROSOFT=y 548 | CONFIG_HID_MONTEREY=y 549 | CONFIG_HID_MULTITOUCH=y 550 | CONFIG_USB=y 551 | CONFIG_USB_OTG=y 552 | CONFIG_USB_OTG_WHITELIST=y 553 | CONFIG_USB_XHCI_HCD=y 554 | CONFIG_USB_XHCI_TEGRA=y 555 | CONFIG_USB_EHCI_HCD=y 556 | CONFIG_USB_EHCI_MSM=y 557 | CONFIG_USB_EHCI_EXYNOS=y 558 | CONFIG_USB_EHCI_HCD_PLATFORM=y 559 | CONFIG_USB_OHCI_HCD=y 560 | CONFIG_USB_OHCI_EXYNOS=y 561 | CONFIG_USB_OHCI_HCD_PLATFORM=y 562 | CONFIG_USB_HCD_TEST_MODE=y 563 | CONFIG_USB_RENESAS_USBHS=m 564 | CONFIG_USB_ACM=m 565 | CONFIG_USB_STORAGE=y 566 | CONFIG_USB_DWC3=y 567 | CONFIG_USB_DWC2=y 568 | CONFIG_USB_CHIPIDEA=y 569 | CONFIG_USB_CHIPIDEA_UDC=y 570 | CONFIG_USB_CHIPIDEA_HOST=y 571 | CONFIG_USB_ISP1760=y 572 | CONFIG_USB_ISP1760_HOST_ROLE=y 573 | CONFIG_USB_CDNS3=y 574 | CONFIG_USB_CDNS3_GADGET=y 575 | CONFIG_USB_CDNS3_HOST=y 576 | CONFIG_USB_TEST=m 577 | CONFIG_USB_EHSET_TEST_FIXTURE=y 578 | CONFIG_USB_HSIC_USB3503=y 579 | CONFIG_NOP_USB_XCEIV=y 580 | CONFIG_USB_GPIO_VBUS=y 581 | CONFIG_USB_QCOM_8X16_PHY=y 582 | CONFIG_USB_MXS_PHY=y 583 | CONFIG_USB_ULPI=y 584 | CONFIG_USB_GADGET=y 585 | CONFIG_USB_RENESAS_USBHS_UDC=m 586 | CONFIG_USB_CONFIGFS=y 587 | CONFIG_USB_CONFIGFS_SERIAL=y 588 | CONFIG_USB_CONFIGFS_ACM=y 589 | CONFIG_USB_CONFIGFS_OBEX=y 590 | CONFIG_USB_CONFIGFS_NCM=y 591 | CONFIG_USB_CONFIGFS_ECM=y 592 | CONFIG_USB_CONFIGFS_ECM_SUBSET=y 593 | CONFIG_USB_CONFIGFS_RNDIS=y 594 | CONFIG_USB_CONFIGFS_EEM=y 595 | CONFIG_USB_CONFIGFS_MASS_STORAGE=y 596 | CONFIG_FSL_UTP=y 597 | CONFIG_USB_CONFIGFS_F_LB_SS=y 598 | CONFIG_USB_CONFIGFS_F_FS=y 599 | CONFIG_USB_CONFIGFS_F_UAC1=y 600 | CONFIG_USB_CONFIGFS_F_UAC2=y 601 | CONFIG_USB_CONFIGFS_F_MIDI=y 602 | CONFIG_USB_CONFIGFS_F_HID=y 603 | CONFIG_USB_ZERO=m 604 | CONFIG_USB_AUDIO=m 605 | CONFIG_GADGET_UAC1=y 606 | CONFIG_USB_ETH=m 607 | CONFIG_USB_ETH_EEM=y 608 | CONFIG_USB_G_NCM=m 609 | CONFIG_USB_MASS_STORAGE=m 610 | CONFIG_USB_G_SERIAL=m 611 | CONFIG_USB_CDC_COMPOSITE=m 612 | CONFIG_MMC=y 613 | CONFIG_MMC_BLOCK_MINORS=32 614 | CONFIG_MMC_ARMMMCI=y 615 | CONFIG_MMC_SDHCI=y 616 | CONFIG_MMC_SDHCI_ACPI=y 617 | CONFIG_MMC_SDHCI_PLTFM=y 618 | CONFIG_MMC_SDHCI_OF_ARASAN=y 619 | CONFIG_MMC_SDHCI_OF_ESDHC=y 620 | CONFIG_MMC_SDHCI_CADENCE=y 621 | CONFIG_MMC_SDHCI_ESDHC_IMX=y 622 | CONFIG_MMC_SDHCI_TEGRA=y 623 | CONFIG_MMC_MESON_GX=y 624 | CONFIG_MMC_SDHCI_MSM=y 625 | CONFIG_MMC_SPI=y 626 | CONFIG_MMC_SDHI=y 627 | CONFIG_MMC_DW=y 628 | CONFIG_MMC_DW_EXYNOS=y 629 | CONFIG_MMC_DW_K3=y 630 | CONFIG_MMC_DW_ROCKCHIP=y 631 | CONFIG_MMC_SUNXI=y 632 | CONFIG_MMC_BCM2835=y 633 | CONFIG_MMC_SDHCI_XENON=y 634 | CONFIG_MXC_MLB150=y 635 | CONFIG_MXC_SIM=y 636 | CONFIG_MXC_EMVSIM=y 637 | CONFIG_NEW_LEDS=y 638 | CONFIG_LEDS_CLASS=y 639 | CONFIG_LEDS_GPIO=y 640 | CONFIG_LEDS_PWM=y 641 | CONFIG_LEDS_SYSCON=y 642 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y 643 | CONFIG_LEDS_TRIGGER_CPU=y 644 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 645 | CONFIG_EDAC=y 646 | CONFIG_RTC_CLASS=y 647 | CONFIG_RTC_DRV_MAX77686=y 648 | CONFIG_RTC_DRV_RK808=m 649 | CONFIG_RTC_DRV_S5M=y 650 | CONFIG_RTC_DRV_DS3232=y 651 | CONFIG_RTC_DRV_EFI=y 652 | CONFIG_RTC_DRV_S3C=y 653 | CONFIG_RTC_DRV_PL031=y 654 | CONFIG_RTC_DRV_TEGRA=y 655 | CONFIG_RTC_DRV_SNVS=y 656 | CONFIG_RTC_DRV_IMX_SC=y 657 | CONFIG_RTC_DRV_XGENE=y 658 | CONFIG_DMADEVICES=y 659 | CONFIG_DMA_BCM2835=m 660 | CONFIG_FSL_EDMA_V3=y 661 | CONFIG_IMX_SDMA=y 662 | CONFIG_K3_DMA=y 663 | CONFIG_MV_XOR_V2=y 664 | CONFIG_MXS_DMA=y 665 | CONFIG_PL330_DMA=y 666 | CONFIG_TEGRA20_APB_DMA=y 667 | CONFIG_QCOM_BAM_DMA=y 668 | CONFIG_QCOM_HIDMA_MGMT=y 669 | CONFIG_QCOM_HIDMA=y 670 | CONFIG_RCAR_DMAC=y 671 | CONFIG_UIO=y 672 | CONFIG_UIO_PCI_GENERIC=y 673 | CONFIG_VIRTIO_PCI=y 674 | CONFIG_VIRTIO_BALLOON=y 675 | CONFIG_VIRTIO_MMIO=y 676 | CONFIG_XEN_GNTDEV=y 677 | CONFIG_XEN_GRANT_DEV_ALLOC=y 678 | CONFIG_STAGING=y 679 | CONFIG_ION=y 680 | CONFIG_ION_SYSTEM_HEAP=y 681 | CONFIG_ION_CMA_HEAP=y 682 | CONFIG_TYPEC_TCPM=y 683 | CONFIG_TYPEC_TCPCI=y 684 | CONFIG_COMMON_CLK_RK808=y 685 | CONFIG_COMMON_CLK_SCPI=y 686 | CONFIG_COMMON_CLK_CS2000_CP=y 687 | CONFIG_COMMON_CLK_S2MPS11=y 688 | CONFIG_CLK_QORIQ=y 689 | CONFIG_COMMON_CLK_PWM=y 690 | CONFIG_COMMON_CLK_QCOM=y 691 | CONFIG_QCOM_CLK_SMD_RPM=y 692 | CONFIG_IPQ_GCC_8074=y 693 | CONFIG_MSM_GCC_8916=y 694 | CONFIG_MSM_GCC_8994=y 695 | CONFIG_MSM_MMCC_8996=y 696 | CONFIG_HWSPINLOCK=y 697 | CONFIG_HWSPINLOCK_QCOM=y 698 | CONFIG_CLKSRC_IMX_SYS_CNT=y 699 | CONFIG_ARM_MHU=y 700 | CONFIG_PLATFORM_MHU=y 701 | CONFIG_BCM2835_MBOX=y 702 | CONFIG_HI6220_MBOX=y 703 | CONFIG_ROCKCHIP_IOMMU=y 704 | CONFIG_ARM_SMMU=y 705 | CONFIG_ARM_SMMU_V3=y 706 | CONFIG_RPMSG=y 707 | CONFIG_RPMSG_QCOM_SMD=y 708 | CONFIG_RASPBERRYPI_POWER=y 709 | CONFIG_ARCH_MXC_ARM64=y 710 | CONFIG_QCOM_SMEM=y 711 | CONFIG_QCOM_SMD_RPM=y 712 | CONFIG_QCOM_SMP2P=y 713 | CONFIG_QCOM_SMSM=y 714 | CONFIG_ROCKCHIP_PM_DOMAINS=y 715 | CONFIG_ARCH_TEGRA_132_SOC=y 716 | CONFIG_ARCH_TEGRA_210_SOC=y 717 | CONFIG_ARCH_TEGRA_186_SOC=y 718 | CONFIG_EXTCON_PTN5150=y 719 | CONFIG_IIO=y 720 | CONFIG_EXYNOS_ADC=y 721 | CONFIG_IMX8QXP_ADC=y 722 | CONFIG_ROCKCHIP_SARADC=m 723 | CONFIG_PWM=y 724 | CONFIG_PWM_BCM2835=m 725 | CONFIG_PWM_CROS_EC=m 726 | CONFIG_PWM_FSL_FTM=y 727 | CONFIG_PWM_IMX=y 728 | CONFIG_PWM_MESON=m 729 | CONFIG_PWM_ROCKCHIP=y 730 | CONFIG_PWM_SAMSUNG=y 731 | CONFIG_PWM_TEGRA=m 732 | CONFIG_PHY_XGENE=y 733 | CONFIG_PHY_SUN4I_USB=y 734 | CONFIG_PHY_HI6220_USB=y 735 | CONFIG_PHY_RCAR_GEN3_USB2=y 736 | CONFIG_PHY_ROCKCHIP_EMMC=y 737 | CONFIG_PHY_ROCKCHIP_INNO_USB2=y 738 | CONFIG_PHY_ROCKCHIP_PCIE=m 739 | CONFIG_PHY_TEGRA_XUSB=y 740 | CONFIG_QCOM_L2_PMU=y 741 | CONFIG_QCOM_L3_PMU=y 742 | CONFIG_IMX8_DDR_PERF=y 743 | CONFIG_NVMEM_IMX_OCOTP=y 744 | CONFIG_NVMEM_IMX_SCU_OCOTP=y 745 | CONFIG_TEE=y 746 | CONFIG_OPTEE=y 747 | CONFIG_ARM_SCPI_PROTOCOL=y 748 | CONFIG_RASPBERRYPI_FIRMWARE=y 749 | CONFIG_EFI_CAPSULE_LOADER=y 750 | CONFIG_ACPI=y 751 | CONFIG_ACPI_APEI=y 752 | CONFIG_ACPI_APEI_GHES=y 753 | CONFIG_ACPI_APEI_PCIEAER=y 754 | CONFIG_EXT2_FS=y 755 | CONFIG_EXT3_FS=y 756 | CONFIG_EXT4_FS_POSIX_ACL=y 757 | CONFIG_BTRFS_FS=m 758 | CONFIG_BTRFS_FS_POSIX_ACL=y 759 | CONFIG_FANOTIFY=y 760 | CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y 761 | CONFIG_QUOTA=y 762 | CONFIG_AUTOFS4_FS=y 763 | CONFIG_FUSE_FS=m 764 | CONFIG_CUSE=m 765 | CONFIG_OVERLAY_FS=m 766 | CONFIG_VFAT_FS=y 767 | CONFIG_HUGETLBFS=y 768 | CONFIG_EFIVAR_FS=y 769 | CONFIG_JFFS2_FS=y 770 | CONFIG_UBIFS_FS=y 771 | CONFIG_SQUASHFS=y 772 | CONFIG_NFS_FS=y 773 | CONFIG_NFS_V4=y 774 | CONFIG_NFS_V4_1=y 775 | CONFIG_NFS_V4_2=y 776 | CONFIG_ROOT_NFS=y 777 | CONFIG_9P_FS=y 778 | CONFIG_NLS_CODEPAGE_437=y 779 | CONFIG_NLS_ISO8859_1=y 780 | CONFIG_VIRTUALIZATION=y 781 | CONFIG_KVM=y 782 | CONFIG_PRINTK_TIME=y 783 | CONFIG_DEBUG_FS=y 784 | CONFIG_MAGIC_SYSRQ=y 785 | # CONFIG_SCHED_DEBUG is not set 786 | # CONFIG_DEBUG_PREEMPT is not set 787 | # CONFIG_FTRACE is not set 788 | CONFIG_MEMTEST=y 789 | CONFIG_SECURITY=y 790 | CONFIG_CRYPTO_TEST=m 791 | CONFIG_CRYPTO_CHACHA20POLY1305=y 792 | CONFIG_CRYPTO_ECHAINIV=y 793 | CONFIG_CRYPTO_CBC=y 794 | CONFIG_CRYPTO_CTS=y 795 | CONFIG_CRYPTO_LRW=y 796 | CONFIG_CRYPTO_XTS=y 797 | CONFIG_CRYPTO_MD4=y 798 | CONFIG_CRYPTO_MD5=y 799 | CONFIG_CRYPTO_RMD128=y 800 | CONFIG_CRYPTO_RMD160=y 801 | CONFIG_CRYPTO_RMD256=y 802 | CONFIG_CRYPTO_RMD320=y 803 | CONFIG_CRYPTO_SHA512=y 804 | CONFIG_CRYPTO_SHA3=y 805 | CONFIG_CRYPTO_TGR192=y 806 | CONFIG_CRYPTO_WP512=y 807 | CONFIG_CRYPTO_BLOWFISH=y 808 | CONFIG_CRYPTO_CAMELLIA=y 809 | CONFIG_CRYPTO_CAST5=y 810 | CONFIG_CRYPTO_CAST6=y 811 | CONFIG_CRYPTO_SERPENT=y 812 | CONFIG_CRYPTO_TWOFISH=y 813 | CONFIG_CRYPTO_ANSI_CPRNG=y 814 | CONFIG_CRYPTO_DEV_FSL_CAAM=y 815 | CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y 816 | CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y 817 | CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y 818 | CONFIG_ARM64_CRYPTO=y 819 | CONFIG_CRYPTO_SHA512_ARM64=m 820 | CONFIG_CRYPTO_SHA1_ARM64_CE=y 821 | CONFIG_CRYPTO_SHA2_ARM64_CE=y 822 | CONFIG_CRYPTO_GHASH_ARM64_CE=y 823 | CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m 824 | CONFIG_CRYPTO_CRC32_ARM64_CE=m 825 | CONFIG_CRYPTO_AES_ARM64_CE_CCM=y 826 | CONFIG_CRYPTO_AES_ARM64_CE_BLK=y 827 | CONFIG_CRYPTO_CHACHA20_NEON=m 828 | CONFIG_CRYPTO_AES_ARM64_BS=m 829 | -------------------------------------------------------------------------------- /recipes-kernel/linux/files/extra.cfg: -------------------------------------------------------------------------------- 1 | CONFIG_OVERLAY_FS=y 2 | -------------------------------------------------------------------------------- /recipes-kernel/linux/files/mendel.cfg: -------------------------------------------------------------------------------- 1 | CONFIG_IKCONFIG=y 2 | CONFIG_ANDROID_PARANOID_NETWORK=n 3 | CONFIG_BRCMFMAC=m 4 | CONFIG_BRCMFMAC_SDIO=m 5 | CONFIG_BRCMUTIL=n 6 | CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=n 7 | CONFIG_KERNEL_GZIP=y 8 | CONFIG_KERNEL_LZO=n 9 | CONFIG_REGULATOR_BD71837=y 10 | CONFIG_MFD_BD71837=y 11 | CONFIG_LOG_BUF_SHIFT=17 12 | CONFIG_WLAN=y 13 | CONFIG_ATH10K=n 14 | 15 | CONFIG_I2C=y 16 | CONFIG_I2C_CHARDEV=y 17 | CONFIG_SND_SOC_FSL_ASOC_CARD=n 18 | CONFIG_SND_GOOGLE_EDGETPU_CARD=y 19 | CONFIG_SND_SOC_IMX_MAX98357A=y 20 | CONFIG_SND_SOC_MAX98357A=y 21 | CONFIG_SND_SOC_RT5645=y 22 | CONFIG_SND_SOC_RT5631=y 23 | CONFIG_SND_SOC_RL6231=y 24 | CONFIG_MFD_BD71837=y 25 | CONFIG_REGULATOR_BD71837=y 26 | CONFIG_MXC_CAMERA_OV5645_MIPI_V2=y 27 | CONFIG_SPI_IMX=y 28 | CONFIG_PCIEASPM_POWERSAVE=n 29 | CONFIG_PCIEASPM_POWER_SUPERSAVE=y 30 | CONFIG_LOCALVERSION_AUTO=n 31 | CONFIG_IMX8MQ_PHANBELL_POWERSAVE=n 32 | CONFIG_DRM_PANEL_TIANMA_S6D6FP0A2=y 33 | CONFIG_STAGING_GASKET_FRAMEWORK=m 34 | CONFIG_STAGING_APEX_DRIVER=m 35 | CONFIG_USB_GADGET=y 36 | CONFIG_USB_GADGETFS=y 37 | CONFIG_USB_FUNCTIONFS=y 38 | CONFIG_USB_FUNCTIONFS_GENERIC=y 39 | CONFIG_USB_LIBCOMPOSITE=y 40 | CONFIG_CONFIGFS_FS=y 41 | CONFIG_CONFIGFS_F_FS=y 42 | CONFIG_CONFIGFS_F_MTP=y 43 | CONFIG_CONFIGFS_F_PTP=y 44 | CONFIG_CONFIGFS_F_UEVENT=y 45 | CONFIG_TMPFS=y 46 | CONFIG_TMPFS_POSIX_ACL=y 47 | CONFIG_USB_F_FS=y 48 | CONFIG_USB_F_ACM=y 49 | CONFIG_USB_GADGETFS=y 50 | CONFIG_GOOGLE_APEX_POWER=n 51 | CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=n 52 | CONFIG_TOUCHSCREEN_FTS=y 53 | 54 | CONFIG_USB_G_HID=y 55 | CONFIG_USB_SERIAL=y 56 | CONFIG_USB_SERIAL_CP210X=y 57 | CONFIG_MXC_GPU_VIV=n 58 | 59 | CONFIG_USB_SERIAL_FTDI_SIO=y 60 | CONFIG_USB_FTDI_ELAN=y 61 | 62 | CONFIG_HWMON=y 63 | CONFIG_SENSORS_GPIO_FAN=y 64 | CONFIG_PMBUS=y 65 | CONFIG_SENSORS_INA233=m 66 | CONFIG_LEDS_KTD202X=y 67 | CONFIG_USB_USB5744=m 68 | CONFIG_USB_HUB_USB251XB=m 69 | CONFIG_I2C_MUX=y 70 | CONFIG_I2C_MUX_PCA954x=m 71 | CONFIG_INPUT_TOUCHSCREEN=y 72 | CONFIG_TOUCHSCREEN_SEC_TS_1223=m 73 | 74 | CONFIG_MD=y 75 | CONFIG_BLK_DEV_DM=m 76 | CONFIG_BLK_DEV_THROTTLING=y 77 | CONFIG_DM_CRYPT=m 78 | 79 | CONFIG_IP_NF_ARPTABLES=m 80 | CONFIG_IP_NF_FILTER=m 81 | CONFIG_IP_NF_IPTABLES=m 82 | CONFIG_IP_NF_MANGLE=m 83 | CONFIG_IP_NF_MATCH_AH=m 84 | CONFIG_IP_NF_MATCH_ECN=m 85 | CONFIG_IP_NF_MATCH_RPFILTER=m 86 | CONFIG_IP_NF_MATCH_TTL=m 87 | CONFIG_IP_NF_NAT=m 88 | CONFIG_IP_NF_RAW=m 89 | CONFIG_IP_NF_SECURITY=m 90 | CONFIG_IP_NF_TARGET_CLUSTERIP=m 91 | CONFIG_IP_NF_TARGET_ECN=m 92 | CONFIG_IP_NF_TARGET_MASQUERADE=m 93 | CONFIG_IP_NF_TARGET_NETMAP=m 94 | CONFIG_IP_NF_TARGET_REDIRECT=m 95 | CONFIG_IP_NF_TARGET_REJECT=m 96 | CONFIG_IP_NF_TARGET_SYNPROXY=m 97 | CONFIG_IP_NF_TARGET_TTL=m 98 | CONFIG_IP6_NF_IPTABLES=m 99 | CONFIG_IP6_NF_MATCH_AH=m 100 | CONFIG_IP6_NF_MATCH_EUI64=m 101 | CONFIG_IP6_NF_MATCH_FRAG=m 102 | CONFIG_IP6_NF_MATCH_OPTS=m 103 | CONFIG_IP6_NF_MATCH_HL=m 104 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m 105 | CONFIG_IP6_NF_MATCH_MH=m 106 | CONFIG_IP6_NF_MATCH_RPFILTER=m 107 | CONFIG_IP6_NF_MATCH_RT=m 108 | CONFIG_IP6_NF_TARGET_HL=m 109 | CONFIG_IP6_NF_FILTER=m 110 | CONFIG_IP6_NF_TARGET_REJECT=m 111 | CONFIG_IP6_NF_TARGET_SYNPROXY=m 112 | CONFIG_IP6_NF_MANGLE=m 113 | CONFIG_IP6_NF_RAW=m 114 | CONFIG_IP6_NF_SECURITY=m 115 | CONFIG_IP6_NF_NAT=m 116 | CONFIG_IP6_NF_TARGET_MASQUERADE=m 117 | CONFIG_IP6_NF_TARGET_NPT=m 118 | CONFIG_NF_CONNTRACK=m 119 | CONFIG_NF_CONNTRACK_AMANDA=m 120 | CONFIG_NF_CONNTRACK_EVENTS=m 121 | CONFIG_NF_CONNTRACK_FTP=m 122 | CONFIG_NF_CONNTRACK_H323=m 123 | CONFIG_NF_CONNTRACK_IPV4=m 124 | CONFIG_NF_CONNTRACK_IPV6=m 125 | CONFIG_NF_CONNTRACK_IRC=m 126 | CONFIG_NF_CONNTRACK_MARK=m 127 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m 128 | CONFIG_NF_CONNTRACK_PPTP=m 129 | CONFIG_NF_CONNTRACK_PROCFS=m 130 | CONFIG_NF_CONNTRACK_SANE=m 131 | CONFIG_NF_CONNTRACK_SIP=m 132 | CONFIG_NF_CONNTRACK_SNMP=m 133 | CONFIG_NF_CONNTRACK_TFTP=m 134 | CONFIG_NF_CONNTRACK_TIMEOUT=m 135 | CONFIG_NF_CONNTRACK_TIMESTAMP=m 136 | CONFIG_NF_TABLES=m 137 | CONFIG_NF_TABLES_INET=y 138 | CONFIG_NF_TABLES_NETDEV=y 139 | CONFIG_NF_TABLES_BRIDGE=y 140 | CONFIG_NF_TABLES_IPV4=y 141 | CONFIG_NF_TABLES_IPV6=y 142 | CONFIG_NF_TABLES_ARP=y 143 | CONFIG_IP_VS=m 144 | CONFIG_NETFILTER_XT_MATCH_IPVS=m 145 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m 146 | CONFIG_EXT4_FS_SECURITY=y 147 | 148 | CONFIG_IIO=m 149 | CONFIG_IIO_BUFFER=y 150 | CONFIG_IIO_TRIGGER=y 151 | CONFIG_TI_ADS1015=m 152 | 153 | CONFIG_GPIO_PI4IOE5V6408=m 154 | CONFIG_TPU_AKIRA=m 155 | CONFIG_YORKTOWN_TPU=m 156 | 157 | CONFIG_IMX_SDMA=m 158 | CONFIG_CMA_DEBUGFS=y 159 | CONFIG_CGROUP_FREEZER=y 160 | CONFIG_CGROUP_NET_PRIO=y 161 | CONFIG_CFS_BANDWIDTH=y 162 | CONFIG_IP_VS_PROTO_TCP=y 163 | CONFIG_IP_VS_PROTO_UDP=y 164 | CONFIG_IP_VS_RR=m 165 | CONFIG_VXLAN=m 166 | CONFIG_XFRM_USER=m 167 | CONFIG_INET_ESP=m 168 | CONFIG_DUMMY=m 169 | CONFIG_DM_THIN_PROVISIONING=m 170 | 171 | CONFIG_SQUASHFS_XZ=y 172 | CONFIG_NETFILTER_XT_MARK=m 173 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m 174 | CONFIG_IP_SET=m 175 | CONFIG_IP_VS_NFCT=m 176 | CONFIG_IP_NF_ARP_MANGLE=m 177 | CONFIG_IP_VS_SH=m 178 | CONFIG_NET_SCHED=m 179 | CONFIG_NET_CLS_CGROUP=m 180 | CONFIG_NETFILTER_XT_SET=m 181 | -------------------------------------------------------------------------------- /recipes-kernel/linux/files/werror.cfg: -------------------------------------------------------------------------------- 1 | # Needed for 5.4 to compile with gcc13+ 2 | CONFIG_DRM_NWL_MIPI_DSI=n 3 | CONFIG_USB_CDNS3=n 4 | CONFIG_USB_MUSB_HDRC=n 5 | CONFIG_USB_MUSB_DUAL_ROLE=n 6 | -------------------------------------------------------------------------------- /recipes-kernel/linux/files/wifi.cfg: -------------------------------------------------------------------------------- 1 | CONFIG_ATH10K=m 2 | CONFIG_ATH10K_PCI=y 3 | CONFIG_ATH_CARDS=y 4 | CONFIG_WLAN=y 5 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0001-regulator-bd718x7-Add-MODULE_ALIAS.patch: -------------------------------------------------------------------------------- 1 | From 754c063fa38f0d4535e8d022f895e385728ca846 Mon Sep 17 00:00:00 2001 2 | From: =?UTF-8?q?Guido=20G=C3=BCnther?= 3 | Date: Mon, 30 Sep 2019 22:26:00 +0200 4 | Subject: [PATCH 01/21] regulator: bd718x7: Add MODULE_ALIAS() 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | This fixes device probing when built as a module 10 | 11 | Signed-off-by: Guido Günther 12 | Link: https://lore.kernel.org/r/46ce3400e227dd88d51486c02a6152c9ec52acbb.1569875042.git.agx@sigxcpu.org 13 | Signed-off-by: Mark Brown 14 | --- 15 | drivers/regulator/bd718x7-regulator.c | 1 + 16 | 1 file changed, 1 insertion(+) 17 | 18 | diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c 19 | index bdab46a5c461..13a43eee2e46 100644 20 | --- a/drivers/regulator/bd718x7-regulator.c 21 | +++ b/drivers/regulator/bd718x7-regulator.c 22 | @@ -1293,3 +1293,4 @@ module_platform_driver(bd718xx_regulator); 23 | MODULE_AUTHOR("Matti Vaittinen "); 24 | MODULE_DESCRIPTION("BD71837/BD71847 voltage regulator driver"); 25 | MODULE_LICENSE("GPL"); 26 | +MODULE_ALIAS("platform:bd718xx-pmic"); 27 | -- 28 | 2.39.2 29 | 30 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0002-regulator-bd718x7-Simplify-the-code-by-removing-stru.patch: -------------------------------------------------------------------------------- 1 | From 28e6442b240279af714dbfd0144b2f5e8cbc2b6a Mon Sep 17 00:00:00 2001 2 | From: Axel Lin 3 | Date: Wed, 8 Jan 2020 09:42:55 +0800 4 | Subject: [PATCH 02/21] regulator: bd718x7: Simplify the code by removing 5 | struct bd718xx_pmic_inits 6 | 7 | Nowdays ROHM_CHIP_TYPE_AMOUNT includes not only BD71837/BD71847 but also 8 | BD70528/BD71828 which are not supported by this driver. So it seems not 9 | necessay to have pmic_regulators[ROHM_CHIP_TYPE_AMOUNT] as mapping table. 10 | Simplify the code by removing struct bd718xx_pmic_inits and 11 | pmic_regulators[ROHM_CHIP_TYPE_AMOUNT]. 12 | 13 | Signed-off-by: Axel Lin 14 | Link: https://lore.kernel.org/r/20200108014256.11282-1-axel.lin@ingics.com 15 | Signed-off-by: Mark Brown 16 | --- 17 | drivers/regulator/bd718x7-regulator.c | 34 +++++++++++---------------- 18 | 1 file changed, 14 insertions(+), 20 deletions(-) 19 | 20 | diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c 21 | index 13a43eee2e46..8f9b2d8eaf10 100644 22 | --- a/drivers/regulator/bd718x7-regulator.c 23 | +++ b/drivers/regulator/bd718x7-regulator.c 24 | @@ -1142,28 +1142,14 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 25 | }, 26 | }; 27 | 28 | -struct bd718xx_pmic_inits { 29 | - const struct bd718xx_regulator_data *r_datas; 30 | - unsigned int r_amount; 31 | -}; 32 | - 33 | static int bd718xx_probe(struct platform_device *pdev) 34 | { 35 | struct bd718xx *mfd; 36 | struct regulator_config config = { 0 }; 37 | - struct bd718xx_pmic_inits pmic_regulators[ROHM_CHIP_TYPE_AMOUNT] = { 38 | - [ROHM_CHIP_TYPE_BD71837] = { 39 | - .r_datas = bd71837_regulators, 40 | - .r_amount = ARRAY_SIZE(bd71837_regulators), 41 | - }, 42 | - [ROHM_CHIP_TYPE_BD71847] = { 43 | - .r_datas = bd71847_regulators, 44 | - .r_amount = ARRAY_SIZE(bd71847_regulators), 45 | - }, 46 | - }; 47 | - 48 | int i, j, err; 49 | bool use_snvs; 50 | + const struct bd718xx_regulator_data *reg_data; 51 | + unsigned int num_reg_data; 52 | 53 | mfd = dev_get_drvdata(pdev->dev.parent); 54 | if (!mfd) { 55 | @@ -1172,8 +1158,16 @@ static int bd718xx_probe(struct platform_device *pdev) 56 | goto err; 57 | } 58 | 59 | - if (mfd->chip.chip_type >= ROHM_CHIP_TYPE_AMOUNT || 60 | - !pmic_regulators[mfd->chip.chip_type].r_datas) { 61 | + switch (mfd->chip.chip_type) { 62 | + case ROHM_CHIP_TYPE_BD71837: 63 | + reg_data = bd71837_regulators; 64 | + num_reg_data = ARRAY_SIZE(bd71837_regulators); 65 | + break; 66 | + case ROHM_CHIP_TYPE_BD71847: 67 | + reg_data = bd71847_regulators; 68 | + num_reg_data = ARRAY_SIZE(bd71847_regulators); 69 | + break; 70 | + default: 71 | dev_err(&pdev->dev, "Unsupported chip type\n"); 72 | err = -EINVAL; 73 | goto err; 74 | @@ -1215,13 +1209,13 @@ static int bd718xx_probe(struct platform_device *pdev) 75 | } 76 | } 77 | 78 | - for (i = 0; i < pmic_regulators[mfd->chip.chip_type].r_amount; i++) { 79 | + for (i = 0; i < num_reg_data; i++) { 80 | 81 | const struct regulator_desc *desc; 82 | struct regulator_dev *rdev; 83 | const struct bd718xx_regulator_data *r; 84 | 85 | - r = &pmic_regulators[mfd->chip.chip_type].r_datas[i]; 86 | + r = ®_data[i]; 87 | desc = &r->desc; 88 | 89 | config.dev = pdev->dev.parent; 90 | -- 91 | 2.39.2 92 | 93 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0003-mfd-Rohm-PMICs-Use-platform_device_id-to-match-MFD-s.patch: -------------------------------------------------------------------------------- 1 | From 998dc427dbb50c81f2a588667bff4a1328460c24 Mon Sep 17 00:00:00 2001 2 | From: Matti Vaittinen 3 | Date: Mon, 20 Jan 2020 15:42:38 +0200 4 | Subject: [PATCH 03/21] mfd: Rohm PMICs: Use platform_device_id to match MFD 5 | sub-devices 6 | 7 | Thanks to Stephen Boyd I today learned we can use platform_device_id 8 | to do device and module matching for MFD sub-devices! 9 | 10 | Do device matching using the platform_device_id instead of using 11 | explicit module_aliases to load modules and custom parent-data field 12 | to do module loading and sub-device matching. 13 | 14 | Cc: Stephen Boyd 15 | Signed-off-by: Matti Vaittinen 16 | Acked-by: Mark Brown 17 | Signed-off-by: Lee Jones 18 | --- 19 | drivers/clk/clk-bd718x7.c | 12 ++++++++- 20 | drivers/mfd/rohm-bd70528.c | 3 +-- 21 | drivers/mfd/rohm-bd718x7.c | 39 ++++++++++++++++++++++----- 22 | drivers/regulator/bd718x7-regulator.c | 11 +++++++- 23 | include/linux/mfd/rohm-generic.h | 3 +-- 24 | 5 files changed, 55 insertions(+), 13 deletions(-) 25 | 26 | diff --git a/drivers/clk/clk-bd718x7.c b/drivers/clk/clk-bd718x7.c 27 | index ae6e5baee330..1c1764f74d0a 100644 28 | --- a/drivers/clk/clk-bd718x7.c 29 | +++ b/drivers/clk/clk-bd718x7.c 30 | @@ -74,6 +74,7 @@ static int bd71837_clk_probe(struct platform_device *pdev) 31 | .name = "bd718xx-32k-out", 32 | .ops = &bd71837_clk_ops, 33 | }; 34 | + enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data; 35 | 36 | c = devm_kzalloc(&pdev->dev, sizeof(*c), GFP_KERNEL); 37 | if (!c) 38 | @@ -87,7 +88,7 @@ static int bd71837_clk_probe(struct platform_device *pdev) 39 | dev_err(&pdev->dev, "No parent clk found\n"); 40 | return -EINVAL; 41 | } 42 | - switch (mfd->chip_type) { 43 | + switch (chip) { 44 | case ROHM_CHIP_TYPE_BD71837: 45 | case ROHM_CHIP_TYPE_BD71847: 46 | c->reg = BD718XX_REG_OUT32K; 47 | @@ -121,11 +122,20 @@ static int bd71837_clk_probe(struct platform_device *pdev) 48 | return rval; 49 | } 50 | 51 | +static const struct platform_device_id bd718x7_clk_id[] = { 52 | + { "bd71837-clk", ROHM_CHIP_TYPE_BD71837 }, 53 | + { "bd71847-clk", ROHM_CHIP_TYPE_BD71847 }, 54 | + { "bd70528-clk", ROHM_CHIP_TYPE_BD70528 }, 55 | + { }, 56 | +}; 57 | +MODULE_DEVICE_TABLE(platform, bd718x7_clk_id); 58 | + 59 | static struct platform_driver bd71837_clk = { 60 | .driver = { 61 | .name = "bd718xx-clk", 62 | }, 63 | .probe = bd71837_clk_probe, 64 | + .id_table = bd718x7_clk_id, 65 | }; 66 | 67 | module_platform_driver(bd71837_clk); 68 | diff --git a/drivers/mfd/rohm-bd70528.c b/drivers/mfd/rohm-bd70528.c 69 | index 55599d5c5c86..e66a4a1c3731 100644 70 | --- a/drivers/mfd/rohm-bd70528.c 71 | +++ b/drivers/mfd/rohm-bd70528.c 72 | @@ -48,7 +48,7 @@ static struct mfd_cell bd70528_mfd_cells[] = { 73 | * We use BD71837 driver to drive the clock block. Only differences to 74 | * BD70528 clock gate are the register address and mask. 75 | */ 76 | - { .name = "bd718xx-clk", }, 77 | + { .name = "bd70528-clk", }, 78 | { .name = "bd70528-wdt", }, 79 | { 80 | .name = "bd70528-power", 81 | @@ -237,7 +237,6 @@ static int bd70528_i2c_probe(struct i2c_client *i2c, 82 | 83 | dev_set_drvdata(&i2c->dev, &bd70528->chip); 84 | 85 | - bd70528->chip.chip_type = ROHM_CHIP_TYPE_BD70528; 86 | bd70528->chip.regmap = devm_regmap_init_i2c(i2c, &bd70528_regmap); 87 | if (IS_ERR(bd70528->chip.regmap)) { 88 | dev_err(&i2c->dev, "Failed to initialize Regmap\n"); 89 | diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c 90 | index 85e7f5133365..bb86ec829079 100644 91 | --- a/drivers/mfd/rohm-bd718x7.c 92 | +++ b/drivers/mfd/rohm-bd718x7.c 93 | @@ -30,14 +30,24 @@ static struct gpio_keys_platform_data bd718xx_powerkey_data = { 94 | .name = "bd718xx-pwrkey", 95 | }; 96 | 97 | -static struct mfd_cell bd718xx_mfd_cells[] = { 98 | +static struct mfd_cell bd71837_mfd_cells[] = { 99 | { 100 | .name = "gpio-keys", 101 | .platform_data = &bd718xx_powerkey_data, 102 | .pdata_size = sizeof(bd718xx_powerkey_data), 103 | }, 104 | - { .name = "bd718xx-clk", }, 105 | - { .name = "bd718xx-pmic", }, 106 | + { .name = "bd71837-clk", }, 107 | + { .name = "bd71837-pmic", }, 108 | +}; 109 | + 110 | +static struct mfd_cell bd71847_mfd_cells[] = { 111 | + { 112 | + .name = "gpio-keys", 113 | + .platform_data = &bd718xx_powerkey_data, 114 | + .pdata_size = sizeof(bd718xx_powerkey_data), 115 | + }, 116 | + { .name = "bd71847-clk", }, 117 | + { .name = "bd71847-pmic", }, 118 | }; 119 | 120 | static const struct regmap_irq bd718xx_irqs[] = { 121 | @@ -124,6 +134,9 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, 122 | { 123 | struct bd718xx *bd718xx; 124 | int ret; 125 | + unsigned int chip_type; 126 | + struct mfd_cell *mfd; 127 | + int cells; 128 | 129 | if (!i2c->irq) { 130 | dev_err(&i2c->dev, "No IRQ configured\n"); 131 | @@ -136,8 +149,21 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, 132 | return -ENOMEM; 133 | 134 | bd718xx->chip_irq = i2c->irq; 135 | - bd718xx->chip.chip_type = (unsigned int)(uintptr_t) 136 | - of_device_get_match_data(&i2c->dev); 137 | + chip_type = (unsigned int)(uintptr_t) 138 | + of_device_get_match_data(&i2c->dev); 139 | + switch (chip_type) { 140 | + case ROHM_CHIP_TYPE_BD71837: 141 | + mfd = bd71837_mfd_cells; 142 | + cells = ARRAY_SIZE(bd71837_mfd_cells); 143 | + break; 144 | + case ROHM_CHIP_TYPE_BD71847: 145 | + mfd = bd71847_mfd_cells; 146 | + cells = ARRAY_SIZE(bd71847_mfd_cells); 147 | + break; 148 | + default: 149 | + dev_err(&i2c->dev, "Unknown device type"); 150 | + return -EINVAL; 151 | + } 152 | bd718xx->chip.dev = &i2c->dev; 153 | dev_set_drvdata(&i2c->dev, bd718xx); 154 | 155 | @@ -170,8 +196,7 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, 156 | button.irq = ret; 157 | 158 | ret = devm_mfd_add_devices(bd718xx->chip.dev, PLATFORM_DEVID_AUTO, 159 | - bd718xx_mfd_cells, 160 | - ARRAY_SIZE(bd718xx_mfd_cells), NULL, 0, 161 | + mfd, cells, NULL, 0, 162 | regmap_irq_get_domain(bd718xx->irq_data)); 163 | if (ret) 164 | dev_err(&i2c->dev, "Failed to create subdevices\n"); 165 | diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c 166 | index 8f9b2d8eaf10..1ad69f7b6d9f 100644 167 | --- a/drivers/regulator/bd718x7-regulator.c 168 | +++ b/drivers/regulator/bd718x7-regulator.c 169 | @@ -1150,6 +1150,7 @@ static int bd718xx_probe(struct platform_device *pdev) 170 | bool use_snvs; 171 | const struct bd718xx_regulator_data *reg_data; 172 | unsigned int num_reg_data; 173 | + enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data; 174 | 175 | mfd = dev_get_drvdata(pdev->dev.parent); 176 | if (!mfd) { 177 | @@ -1158,7 +1159,7 @@ static int bd718xx_probe(struct platform_device *pdev) 178 | goto err; 179 | } 180 | 181 | - switch (mfd->chip.chip_type) { 182 | + switch (chip) { 183 | case ROHM_CHIP_TYPE_BD71837: 184 | reg_data = bd71837_regulators; 185 | num_reg_data = ARRAY_SIZE(bd71837_regulators); 186 | @@ -1275,11 +1276,19 @@ static int bd718xx_probe(struct platform_device *pdev) 187 | return err; 188 | } 189 | 190 | +static const struct platform_device_id bd718x7_pmic_id[] = { 191 | + { "bd71837-pmic", ROHM_CHIP_TYPE_BD71837 }, 192 | + { "bd71847-pmic", ROHM_CHIP_TYPE_BD71847 }, 193 | + { }, 194 | +}; 195 | +MODULE_DEVICE_TABLE(platform, bd718x7_pmic_id); 196 | + 197 | static struct platform_driver bd718xx_regulator = { 198 | .driver = { 199 | .name = "bd718xx-pmic", 200 | }, 201 | .probe = bd718xx_probe, 202 | + .id_table = bd718x7_pmic_id, 203 | }; 204 | 205 | module_platform_driver(bd718xx_regulator); 206 | diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h 207 | index bff15ac26f2c..922f88008232 100644 208 | --- a/include/linux/mfd/rohm-generic.h 209 | +++ b/include/linux/mfd/rohm-generic.h 210 | @@ -4,7 +4,7 @@ 211 | #ifndef __LINUX_MFD_ROHM_H__ 212 | #define __LINUX_MFD_ROHM_H__ 213 | 214 | -enum { 215 | +enum rohm_chip_type { 216 | ROHM_CHIP_TYPE_BD71837 = 0, 217 | ROHM_CHIP_TYPE_BD71847, 218 | ROHM_CHIP_TYPE_BD70528, 219 | @@ -12,7 +12,6 @@ enum { 220 | }; 221 | 222 | struct rohm_regmap_dev { 223 | - unsigned int chip_type; 224 | struct device *dev; 225 | struct regmap *regmap; 226 | }; 227 | -- 228 | 2.39.2 229 | 230 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0004-regulator-bd718x7-Split-driver-to-common-and-bd718x7.patch: -------------------------------------------------------------------------------- 1 | From 46e726b6717847da205dccaf883d73fa1565f7d1 Mon Sep 17 00:00:00 2001 2 | From: Matti Vaittinen 3 | Date: Mon, 20 Jan 2020 15:44:45 +0200 4 | Subject: [PATCH 04/21] regulator: bd718x7: Split driver to common and bd718x7 5 | specific parts 6 | 7 | Few ROHM PMICs allow setting the voltage states for different system states 8 | like RUN, IDLE, SUSPEND and LPSR. States are then changed via SoC specific 9 | mechanisms. bd718x7 driver implemented device-tree parsing functions for 10 | these state specific voltages. The parsing functions can be re-used by 11 | other ROHM chip drivers like bd71828. Split the generic functions from 12 | bd718x7-regulator.c to rohm-regulator.c and export them for other modules 13 | to use. 14 | 15 | Signed-off-by: Matti Vaittinen 16 | Acked-by: Mark Brown 17 | Signed-off-by: Lee Jones 18 | --- 19 | drivers/regulator/Kconfig | 4 + 20 | drivers/regulator/Makefile | 1 + 21 | drivers/regulator/bd718x7-regulator.c | 183 ++++++++------------------ 22 | drivers/regulator/rohm-regulator.c | 95 +++++++++++++ 23 | include/linux/mfd/rohm-generic.h | 66 ++++++++++ 24 | 5 files changed, 221 insertions(+), 128 deletions(-) 25 | create mode 100644 drivers/regulator/rohm-regulator.c 26 | 27 | diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig 28 | index 96cdc0e1f7e8..af0ba71a5df6 100644 29 | --- a/drivers/regulator/Kconfig 30 | +++ b/drivers/regulator/Kconfig 31 | @@ -197,6 +197,7 @@ config REGULATOR_BD70528 32 | config REGULATOR_BD718XX 33 | tristate "ROHM BD71837 Power Regulator" 34 | depends on MFD_ROHM_BD718XX 35 | + select REGULATOR_ROHM 36 | help 37 | This driver supports voltage regulators on ROHM BD71837 PMIC. 38 | This will enable support for the software controllable buck 39 | @@ -808,6 +809,9 @@ config REGULATOR_RN5T618 40 | Say y here to support the regulators found on Ricoh RN5T567, 41 | RN5T618 or RC5T619 PMIC. 42 | 43 | +config REGULATOR_ROHM 44 | + tristate 45 | + 46 | config REGULATOR_RT5033 47 | tristate "Richtek RT5033 Regulators" 48 | depends on MFD_RT5033 49 | diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile 50 | index c58c41a3260c..4ab1fe2af3b3 100644 51 | --- a/drivers/regulator/Makefile 52 | +++ b/drivers/regulator/Makefile 53 | @@ -102,6 +102,7 @@ obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o 54 | obj-$(CONFIG_REGULATOR_RC5T583) += rc5t583-regulator.o 55 | obj-$(CONFIG_REGULATOR_RK808) += rk808-regulator.o 56 | obj-$(CONFIG_REGULATOR_RN5T618) += rn5t618-regulator.o 57 | +obj-$(CONFIG_REGULATOR_ROHM) += rohm-regulator.o 58 | obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o 59 | obj-$(CONFIG_REGULATOR_S2MPA01) += s2mpa01.o 60 | obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o 61 | diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c 62 | index 1ad69f7b6d9f..cf3872837abc 100644 63 | --- a/drivers/regulator/bd718x7-regulator.c 64 | +++ b/drivers/regulator/bd718x7-regulator.c 65 | @@ -318,6 +318,7 @@ struct reg_init { 66 | }; 67 | struct bd718xx_regulator_data { 68 | struct regulator_desc desc; 69 | + const struct rohm_dvs_config dvs; 70 | const struct reg_init init; 71 | const struct reg_init *additional_inits; 72 | int additional_init_amnt; 73 | @@ -349,133 +350,15 @@ static const struct reg_init bd71837_ldo6_inits[] = { 74 | }, 75 | }; 76 | 77 | -#define NUM_DVS_BUCKS 4 78 | - 79 | -struct of_dvs_setting { 80 | - const char *prop; 81 | - unsigned int reg; 82 | -}; 83 | - 84 | -static int set_dvs_levels(const struct of_dvs_setting *dvs, 85 | - struct device_node *np, 86 | - const struct regulator_desc *desc, 87 | - struct regmap *regmap) 88 | -{ 89 | - int ret, i; 90 | - unsigned int uv; 91 | - 92 | - ret = of_property_read_u32(np, dvs->prop, &uv); 93 | - if (ret) { 94 | - if (ret != -EINVAL) 95 | - return ret; 96 | - return 0; 97 | - } 98 | - 99 | - for (i = 0; i < desc->n_voltages; i++) { 100 | - ret = regulator_desc_list_voltage_linear_range(desc, i); 101 | - if (ret < 0) 102 | - continue; 103 | - if (ret == uv) { 104 | - i <<= ffs(desc->vsel_mask) - 1; 105 | - ret = regmap_update_bits(regmap, dvs->reg, 106 | - DVS_BUCK_RUN_MASK, i); 107 | - break; 108 | - } 109 | - } 110 | - return ret; 111 | -} 112 | - 113 | -static int buck4_set_hw_dvs_levels(struct device_node *np, 114 | +static int buck_set_hw_dvs_levels(struct device_node *np, 115 | const struct regulator_desc *desc, 116 | struct regulator_config *cfg) 117 | { 118 | - int ret, i; 119 | - const struct of_dvs_setting dvs[] = { 120 | - { 121 | - .prop = "rohm,dvs-run-voltage", 122 | - .reg = BD71837_REG_BUCK4_VOLT_RUN, 123 | - }, 124 | - }; 125 | + struct bd718xx_regulator_data *data; 126 | 127 | - for (i = 0; i < ARRAY_SIZE(dvs); i++) { 128 | - ret = set_dvs_levels(&dvs[i], np, desc, cfg->regmap); 129 | - if (ret) 130 | - break; 131 | - } 132 | - return ret; 133 | -} 134 | -static int buck3_set_hw_dvs_levels(struct device_node *np, 135 | - const struct regulator_desc *desc, 136 | - struct regulator_config *cfg) 137 | -{ 138 | - int ret, i; 139 | - const struct of_dvs_setting dvs[] = { 140 | - { 141 | - .prop = "rohm,dvs-run-voltage", 142 | - .reg = BD71837_REG_BUCK3_VOLT_RUN, 143 | - }, 144 | - }; 145 | + data = container_of(desc, struct bd718xx_regulator_data, desc); 146 | 147 | - for (i = 0; i < ARRAY_SIZE(dvs); i++) { 148 | - ret = set_dvs_levels(&dvs[i], np, desc, cfg->regmap); 149 | - if (ret) 150 | - break; 151 | - } 152 | - return ret; 153 | -} 154 | - 155 | -static int buck2_set_hw_dvs_levels(struct device_node *np, 156 | - const struct regulator_desc *desc, 157 | - struct regulator_config *cfg) 158 | -{ 159 | - int ret, i; 160 | - const struct of_dvs_setting dvs[] = { 161 | - { 162 | - .prop = "rohm,dvs-run-voltage", 163 | - .reg = BD718XX_REG_BUCK2_VOLT_RUN, 164 | - }, 165 | - { 166 | - .prop = "rohm,dvs-idle-voltage", 167 | - .reg = BD718XX_REG_BUCK2_VOLT_IDLE, 168 | - }, 169 | - }; 170 | - 171 | - 172 | - 173 | - for (i = 0; i < ARRAY_SIZE(dvs); i++) { 174 | - ret = set_dvs_levels(&dvs[i], np, desc, cfg->regmap); 175 | - if (ret) 176 | - break; 177 | - } 178 | - return ret; 179 | -} 180 | - 181 | -static int buck1_set_hw_dvs_levels(struct device_node *np, 182 | - const struct regulator_desc *desc, 183 | - struct regulator_config *cfg) 184 | -{ 185 | - int ret, i; 186 | - const struct of_dvs_setting dvs[] = { 187 | - { 188 | - .prop = "rohm,dvs-run-voltage", 189 | - .reg = BD718XX_REG_BUCK1_VOLT_RUN, 190 | - }, 191 | - { 192 | - .prop = "rohm,dvs-idle-voltage", 193 | - .reg = BD718XX_REG_BUCK1_VOLT_IDLE, 194 | - }, 195 | - { 196 | - .prop = "rohm,dvs-suspend-voltage", 197 | - .reg = BD718XX_REG_BUCK1_VOLT_SUSP, 198 | - }, 199 | - }; 200 | - 201 | - for (i = 0; i < ARRAY_SIZE(dvs); i++) { 202 | - ret = set_dvs_levels(&dvs[i], np, desc, cfg->regmap); 203 | - if (ret) 204 | - break; 205 | - } 206 | - return ret; 207 | + return rohm_regulator_set_dvs_levels(&data->dvs, np, desc, cfg->regmap); 208 | } 209 | 210 | static const struct bd718xx_regulator_data bd71847_regulators[] = { 211 | @@ -496,7 +379,17 @@ static const struct bd718xx_regulator_data bd71847_regulators[] = { 212 | .enable_reg = BD718XX_REG_BUCK1_CTRL, 213 | .enable_mask = BD718XX_BUCK_EN, 214 | .owner = THIS_MODULE, 215 | - .of_parse_cb = buck1_set_hw_dvs_levels, 216 | + .of_parse_cb = buck_set_hw_dvs_levels, 217 | + }, 218 | + .dvs = { 219 | + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 220 | + ROHM_DVS_LEVEL_SUSPEND, 221 | + .run_reg = BD718XX_REG_BUCK1_VOLT_RUN, 222 | + .run_mask = DVS_BUCK_RUN_MASK, 223 | + .idle_reg = BD718XX_REG_BUCK1_VOLT_IDLE, 224 | + .idle_mask = DVS_BUCK_RUN_MASK, 225 | + .suspend_reg = BD718XX_REG_BUCK1_VOLT_SUSP, 226 | + .suspend_mask = DVS_BUCK_RUN_MASK, 227 | }, 228 | .init = { 229 | .reg = BD718XX_REG_BUCK1_CTRL, 230 | @@ -520,7 +413,14 @@ static const struct bd718xx_regulator_data bd71847_regulators[] = { 231 | .enable_reg = BD718XX_REG_BUCK2_CTRL, 232 | .enable_mask = BD718XX_BUCK_EN, 233 | .owner = THIS_MODULE, 234 | - .of_parse_cb = buck2_set_hw_dvs_levels, 235 | + .of_parse_cb = buck_set_hw_dvs_levels, 236 | + }, 237 | + .dvs = { 238 | + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE, 239 | + .run_reg = BD718XX_REG_BUCK2_VOLT_RUN, 240 | + .run_mask = DVS_BUCK_RUN_MASK, 241 | + .idle_reg = BD718XX_REG_BUCK2_VOLT_IDLE, 242 | + .idle_mask = DVS_BUCK_RUN_MASK, 243 | }, 244 | .init = { 245 | .reg = BD718XX_REG_BUCK2_CTRL, 246 | @@ -792,7 +692,17 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 247 | .enable_reg = BD718XX_REG_BUCK1_CTRL, 248 | .enable_mask = BD718XX_BUCK_EN, 249 | .owner = THIS_MODULE, 250 | - .of_parse_cb = buck1_set_hw_dvs_levels, 251 | + .of_parse_cb = buck_set_hw_dvs_levels, 252 | + }, 253 | + .dvs = { 254 | + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 255 | + ROHM_DVS_LEVEL_SUSPEND, 256 | + .run_reg = BD718XX_REG_BUCK1_VOLT_RUN, 257 | + .run_mask = DVS_BUCK_RUN_MASK, 258 | + .idle_reg = BD718XX_REG_BUCK1_VOLT_IDLE, 259 | + .idle_mask = DVS_BUCK_RUN_MASK, 260 | + .suspend_reg = BD718XX_REG_BUCK1_VOLT_SUSP, 261 | + .suspend_mask = DVS_BUCK_RUN_MASK, 262 | }, 263 | .init = { 264 | .reg = BD718XX_REG_BUCK1_CTRL, 265 | @@ -816,7 +726,14 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 266 | .enable_reg = BD718XX_REG_BUCK2_CTRL, 267 | .enable_mask = BD718XX_BUCK_EN, 268 | .owner = THIS_MODULE, 269 | - .of_parse_cb = buck2_set_hw_dvs_levels, 270 | + .of_parse_cb = buck_set_hw_dvs_levels, 271 | + }, 272 | + .dvs = { 273 | + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE, 274 | + .run_reg = BD718XX_REG_BUCK2_VOLT_RUN, 275 | + .run_mask = DVS_BUCK_RUN_MASK, 276 | + .idle_reg = BD718XX_REG_BUCK2_VOLT_IDLE, 277 | + .idle_mask = DVS_BUCK_RUN_MASK, 278 | }, 279 | .init = { 280 | .reg = BD718XX_REG_BUCK2_CTRL, 281 | @@ -840,7 +757,12 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 282 | .enable_reg = BD71837_REG_BUCK3_CTRL, 283 | .enable_mask = BD718XX_BUCK_EN, 284 | .owner = THIS_MODULE, 285 | - .of_parse_cb = buck3_set_hw_dvs_levels, 286 | + .of_parse_cb = buck_set_hw_dvs_levels, 287 | + }, 288 | + .dvs = { 289 | + .level_map = ROHM_DVS_LEVEL_RUN, 290 | + .run_reg = BD71837_REG_BUCK3_VOLT_RUN, 291 | + .run_mask = DVS_BUCK_RUN_MASK, 292 | }, 293 | .init = { 294 | .reg = BD71837_REG_BUCK3_CTRL, 295 | @@ -864,7 +786,12 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 296 | .enable_reg = BD71837_REG_BUCK4_CTRL, 297 | .enable_mask = BD718XX_BUCK_EN, 298 | .owner = THIS_MODULE, 299 | - .of_parse_cb = buck4_set_hw_dvs_levels, 300 | + .of_parse_cb = buck_set_hw_dvs_levels, 301 | + }, 302 | + .dvs = { 303 | + .level_map = ROHM_DVS_LEVEL_RUN, 304 | + .run_reg = BD71837_REG_BUCK4_VOLT_RUN, 305 | + .run_mask = DVS_BUCK_RUN_MASK, 306 | }, 307 | .init = { 308 | .reg = BD71837_REG_BUCK4_CTRL, 309 | diff --git a/drivers/regulator/rohm-regulator.c b/drivers/regulator/rohm-regulator.c 310 | new file mode 100644 311 | index 000000000000..399002383b28 312 | --- /dev/null 313 | +++ b/drivers/regulator/rohm-regulator.c 314 | @@ -0,0 +1,95 @@ 315 | +// SPDX-License-Identifier: GPL-2.0 316 | +// Copyright (C) 2020 ROHM Semiconductors 317 | + 318 | +#include 319 | +#include 320 | +#include 321 | +#include 322 | +#include 323 | +#include 324 | + 325 | +static int set_dvs_level(const struct regulator_desc *desc, 326 | + struct device_node *np, struct regmap *regmap, 327 | + char *prop, unsigned int reg, unsigned int mask, 328 | + unsigned int omask, unsigned int oreg) 329 | +{ 330 | + int ret, i; 331 | + uint32_t uv; 332 | + 333 | + ret = of_property_read_u32(np, prop, &uv); 334 | + if (ret) { 335 | + if (ret != -EINVAL) 336 | + return ret; 337 | + return 0; 338 | + } 339 | + 340 | + if (uv == 0) { 341 | + if (omask) 342 | + return regmap_update_bits(regmap, oreg, omask, 0); 343 | + } 344 | + for (i = 0; i < desc->n_voltages; i++) { 345 | + ret = regulator_desc_list_voltage_linear_range(desc, i); 346 | + if (ret < 0) 347 | + continue; 348 | + if (ret == uv) { 349 | + i <<= ffs(desc->vsel_mask) - 1; 350 | + ret = regmap_update_bits(regmap, reg, mask, i); 351 | + if (omask && !ret) 352 | + ret = regmap_update_bits(regmap, oreg, omask, 353 | + omask); 354 | + break; 355 | + } 356 | + } 357 | + return ret; 358 | +} 359 | + 360 | +int rohm_regulator_set_dvs_levels(const struct rohm_dvs_config *dvs, 361 | + struct device_node *np, 362 | + const struct regulator_desc *desc, 363 | + struct regmap *regmap) 364 | +{ 365 | + int i, ret = 0; 366 | + char *prop; 367 | + unsigned int reg, mask, omask, oreg = desc->enable_reg; 368 | + 369 | + for (i = 0; i < ROHM_DVS_LEVEL_MAX && !ret; i++) { 370 | + if (dvs->level_map & (1 << i)) { 371 | + switch (i + 1) { 372 | + case ROHM_DVS_LEVEL_RUN: 373 | + prop = "rohm,dvs-run-voltage"; 374 | + reg = dvs->run_reg; 375 | + mask = dvs->run_mask; 376 | + omask = dvs->run_on_mask; 377 | + break; 378 | + case ROHM_DVS_LEVEL_IDLE: 379 | + prop = "rohm,dvs-idle-voltage"; 380 | + reg = dvs->idle_reg; 381 | + mask = dvs->idle_mask; 382 | + omask = dvs->idle_on_mask; 383 | + break; 384 | + case ROHM_DVS_LEVEL_SUSPEND: 385 | + prop = "rohm,dvs-suspend-voltage"; 386 | + reg = dvs->suspend_reg; 387 | + mask = dvs->suspend_mask; 388 | + omask = dvs->suspend_on_mask; 389 | + break; 390 | + case ROHM_DVS_LEVEL_LPSR: 391 | + prop = "rohm,dvs-lpsr-voltage"; 392 | + reg = dvs->lpsr_reg; 393 | + mask = dvs->lpsr_mask; 394 | + omask = dvs->lpsr_on_mask; 395 | + break; 396 | + default: 397 | + return -EINVAL; 398 | + } 399 | + ret = set_dvs_level(desc, np, regmap, prop, reg, mask, 400 | + omask, oreg); 401 | + } 402 | + } 403 | + return ret; 404 | +} 405 | +EXPORT_SYMBOL(rohm_regulator_set_dvs_levels); 406 | + 407 | +MODULE_LICENSE("GPL v2"); 408 | +MODULE_AUTHOR("Matti Vaittinen "); 409 | +MODULE_DESCRIPTION("Generic helpers for ROHM PMIC regulator drivers"); 410 | diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h 411 | index 922f88008232..800cc923fec8 100644 412 | --- a/include/linux/mfd/rohm-generic.h 413 | +++ b/include/linux/mfd/rohm-generic.h 414 | @@ -4,6 +4,9 @@ 415 | #ifndef __LINUX_MFD_ROHM_H__ 416 | #define __LINUX_MFD_ROHM_H__ 417 | 418 | +#include 419 | +#include 420 | + 421 | enum rohm_chip_type { 422 | ROHM_CHIP_TYPE_BD71837 = 0, 423 | ROHM_CHIP_TYPE_BD71847, 424 | @@ -16,4 +19,67 @@ struct rohm_regmap_dev { 425 | struct regmap *regmap; 426 | }; 427 | 428 | +enum { 429 | + ROHM_DVS_LEVEL_UNKNOWN, 430 | + ROHM_DVS_LEVEL_RUN, 431 | + ROHM_DVS_LEVEL_IDLE, 432 | + ROHM_DVS_LEVEL_SUSPEND, 433 | + ROHM_DVS_LEVEL_LPSR, 434 | + ROHM_DVS_LEVEL_MAX = ROHM_DVS_LEVEL_LPSR, 435 | +}; 436 | + 437 | +/** 438 | + * struct rohm_dvs_config - dynamic voltage scaling register descriptions 439 | + * 440 | + * @level_map: bitmap representing supported run-levels for this 441 | + * regulator 442 | + * @run_reg: register address for regulator config at 'run' state 443 | + * @run_mask: value mask for regulator voltages at 'run' state 444 | + * @run_on_mask: enable mask for regulator at 'run' state 445 | + * @idle_reg: register address for regulator config at 'idle' state 446 | + * @idle_mask: value mask for regulator voltages at 'idle' state 447 | + * @idle_on_mask: enable mask for regulator at 'idle' state 448 | + * @suspend_reg: register address for regulator config at 'suspend' state 449 | + * @suspend_mask: value mask for regulator voltages at 'suspend' state 450 | + * @suspend_on_mask: enable mask for regulator at 'suspend' state 451 | + * @lpsr_reg: register address for regulator config at 'lpsr' state 452 | + * @lpsr_mask: value mask for regulator voltages at 'lpsr' state 453 | + * @lpsr_on_mask: enable mask for regulator at 'lpsr' state 454 | + * 455 | + * Description of ROHM PMICs voltage configuration registers for different 456 | + * system states. This is used to correctly configure the PMIC at startup 457 | + * based on values read from DT. 458 | + */ 459 | +struct rohm_dvs_config { 460 | + uint64_t level_map; 461 | + unsigned int run_reg; 462 | + unsigned int run_mask; 463 | + unsigned int run_on_mask; 464 | + unsigned int idle_reg; 465 | + unsigned int idle_mask; 466 | + unsigned int idle_on_mask; 467 | + unsigned int suspend_reg; 468 | + unsigned int suspend_mask; 469 | + unsigned int suspend_on_mask; 470 | + unsigned int lpsr_reg; 471 | + unsigned int lpsr_mask; 472 | + unsigned int lpsr_on_mask; 473 | +}; 474 | + 475 | +#if IS_ENABLED(CONFIG_REGULATOR_ROHM) 476 | +int rohm_regulator_set_dvs_levels(const struct rohm_dvs_config *dvs, 477 | + struct device_node *np, 478 | + const struct regulator_desc *desc, 479 | + struct regmap *regmap); 480 | + 481 | +#else 482 | +static inline int rohm_regulator_set_dvs_levels(const struct rohm_dvs_config *dvs, 483 | + struct device_node *np, 484 | + const struct regulator_desc *desc, 485 | + struct regmap *regmap) 486 | +{ 487 | + return 0; 488 | +} 489 | +#endif 490 | + 491 | #endif 492 | -- 493 | 2.39.2 494 | 495 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0005-regulator-bd718x7-remove-voltage-change-restriction-.patch: -------------------------------------------------------------------------------- 1 | From f46b9d18f4fb8588c6048b8024523e012424d914 Mon Sep 17 00:00:00 2001 2 | From: Matti Vaittinen 3 | Date: Wed, 13 May 2020 17:39:21 +0300 4 | Subject: [PATCH 05/21] regulator: bd718x7: remove voltage change restriction 5 | from BD71847 LDOs 6 | 7 | The BD71837 had a HW "feature" where changing the regulator output 8 | voltages of other regulators but bucks 1-4 might cause spikes if 9 | regulators were enabled. Thus SW prohibit voltage changes for other 10 | regulators except for bucks 1-4 when regulator is enabled. 11 | 12 | The HW colleagues did inadvertly fix this issue for BD71847 and 13 | BD71850. 14 | 15 | The power-good detection for LDOs can still cause false alarms if 16 | LDO voltage is changed upwards when LDO is enabled. 17 | 18 | Allow LDO voltage changes and disabe the power-good monioring for 19 | the duration of the LDO voltage change and enable it after LDO 20 | voltage has stabilized. ROHM HW colleagues measured the safety 21 | limit of 1000uS for guaranteeing the voltage has stabilized. Let's 22 | use that for starters and add confiurable stabilization wait-time 23 | later if needed. 24 | 25 | Signed-off-by: Matti Vaittinen 26 | Link: https://lore.kernel.org/r/20200513143921.GA22143@localhost.localdomain 27 | Signed-off-by: Mark Brown 28 | --- 29 | drivers/regulator/bd718x7-regulator.c | 189 ++++++++++++++++++++++++-- 30 | 1 file changed, 179 insertions(+), 10 deletions(-) 31 | 32 | diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c 33 | index cf3872837abc..003706cf6970 100644 34 | --- a/drivers/regulator/bd718x7-regulator.c 35 | +++ b/drivers/regulator/bd718x7-regulator.c 36 | @@ -59,8 +59,14 @@ static int bd718xx_buck1234_set_ramp_delay(struct regulator_dev *rdev, 37 | * Bucks 5 to 8 and LDOs can use PFM and must be disabled when voltage 38 | * is changed. Hence we return -EBUSY for these if voltage is changed 39 | * when BUCK/LDO is enabled. 40 | + * 41 | + * On BD71847, BD71850, ... The LDO voltage can be changed when LDO is 42 | + * enabled. But if voltage is increased the LDO power-good monitoring 43 | + * must be disabled for the duration of changing + 1mS to ensure voltage 44 | + * has reached the higher level before HW does next under voltage detection 45 | + * cycle. 46 | */ 47 | -static int bd718xx_set_voltage_sel_restricted(struct regulator_dev *rdev, 48 | +static int bd71837_set_voltage_sel_restricted(struct regulator_dev *rdev, 49 | unsigned int sel) 50 | { 51 | if (regulator_is_enabled_regmap(rdev)) 52 | @@ -69,8 +75,123 @@ static int bd718xx_set_voltage_sel_restricted(struct regulator_dev *rdev, 53 | return regulator_set_voltage_sel_regmap(rdev, sel); 54 | } 55 | 56 | +static void voltage_change_done(struct regulator_dev *rdev, unsigned int sel, 57 | + unsigned int *mask) 58 | +{ 59 | + int ret; 60 | + 61 | + if (*mask) { 62 | + /* 63 | + * Let's allow scheduling as we use I2C anyways. We just need to 64 | + * guarantee minimum of 1ms sleep - it shouldn't matter if we 65 | + * exceed it due to the scheduling. 66 | + */ 67 | + msleep(1); 68 | + /* 69 | + * Note for next hacker. The PWRGOOD should not be masked on 70 | + * BD71847 so we will just unconditionally enable detection 71 | + * when voltage is set. 72 | + * If someone want's to disable PWRGOOD he must implement 73 | + * caching and restoring the old value here. I am not 74 | + * aware of such use-cases so for the sake of the simplicity 75 | + * we just always enable PWRGOOD here. 76 | + */ 77 | + ret = regmap_update_bits(rdev->regmap, BD718XX_REG_MVRFLTMASK2, 78 | + *mask, 0); 79 | + if (ret) 80 | + dev_err(&rdev->dev, 81 | + "Failed to re-enable voltage monitoring (%d)\n", 82 | + ret); 83 | + } 84 | +} 85 | + 86 | +static int voltage_change_prepare(struct regulator_dev *rdev, unsigned int sel, 87 | + unsigned int *mask) 88 | +{ 89 | + int ret; 90 | + 91 | + *mask = 0; 92 | + if (regulator_is_enabled_regmap(rdev)) { 93 | + int now, new; 94 | + 95 | + now = rdev->desc->ops->get_voltage_sel(rdev); 96 | + if (now < 0) 97 | + return now; 98 | + 99 | + now = rdev->desc->ops->list_voltage(rdev, now); 100 | + if (now < 0) 101 | + return now; 102 | + 103 | + new = rdev->desc->ops->list_voltage(rdev, sel); 104 | + if (new < 0) 105 | + return new; 106 | + 107 | + /* 108 | + * If we increase LDO voltage when LDO is enabled we need to 109 | + * disable the power-good detection until voltage has reached 110 | + * the new level. According to HW colleagues the maximum time 111 | + * it takes is 1000us. I assume that on systems with light load 112 | + * this might be less - and we could probably use DT to give 113 | + * system specific delay value if performance matters. 114 | + * 115 | + * Well, knowing we use I2C here and can add scheduling delays 116 | + * I don't think it is worth the hassle and I just add fixed 117 | + * 1ms sleep here (and allow scheduling). If this turns out to 118 | + * be a problem we can change it to delay and make the delay 119 | + * time configurable. 120 | + */ 121 | + if (new > now) { 122 | + int ldo_offset = rdev->desc->id - BD718XX_LDO1; 123 | + 124 | + *mask = BD718XX_LDO1_VRMON80 << ldo_offset; 125 | + ret = regmap_update_bits(rdev->regmap, 126 | + BD718XX_REG_MVRFLTMASK2, 127 | + *mask, *mask); 128 | + if (ret) { 129 | + dev_err(&rdev->dev, 130 | + "Failed to stop voltage monitoring\n"); 131 | + return ret; 132 | + } 133 | + } 134 | + } 135 | + 136 | + return 0; 137 | +} 138 | + 139 | +static int bd718xx_set_voltage_sel_restricted(struct regulator_dev *rdev, 140 | + unsigned int sel) 141 | +{ 142 | + int ret; 143 | + int mask; 144 | + 145 | + ret = voltage_change_prepare(rdev, sel, &mask); 146 | + if (ret) 147 | + return ret; 148 | + 149 | + ret = regulator_set_voltage_sel_regmap(rdev, sel); 150 | + voltage_change_done(rdev, sel, &mask); 151 | + 152 | + return ret; 153 | +} 154 | + 155 | static int bd718xx_set_voltage_sel_pickable_restricted( 156 | struct regulator_dev *rdev, unsigned int sel) 157 | +{ 158 | + int ret; 159 | + int mask; 160 | + 161 | + ret = voltage_change_prepare(rdev, sel, &mask); 162 | + if (ret) 163 | + return ret; 164 | + 165 | + ret = regulator_set_voltage_sel_pickable_regmap(rdev, sel); 166 | + voltage_change_done(rdev, sel, &mask); 167 | + 168 | + return ret; 169 | +} 170 | + 171 | +static int bd71837_set_voltage_sel_pickable_restricted( 172 | + struct regulator_dev *rdev, unsigned int sel) 173 | { 174 | if (regulator_is_enabled_regmap(rdev)) 175 | return -EBUSY; 176 | @@ -85,6 +206,16 @@ static const struct regulator_ops bd718xx_pickable_range_ldo_ops = { 177 | .list_voltage = regulator_list_voltage_pickable_linear_range, 178 | .set_voltage_sel = bd718xx_set_voltage_sel_pickable_restricted, 179 | .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, 180 | + 181 | +}; 182 | + 183 | +static const struct regulator_ops bd71837_pickable_range_ldo_ops = { 184 | + .enable = regulator_enable_regmap, 185 | + .disable = regulator_disable_regmap, 186 | + .is_enabled = regulator_is_enabled_regmap, 187 | + .list_voltage = regulator_list_voltage_pickable_linear_range, 188 | + .set_voltage_sel = bd71837_set_voltage_sel_pickable_restricted, 189 | + .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, 190 | }; 191 | 192 | static const struct regulator_ops bd718xx_pickable_range_buck_ops = { 193 | @@ -92,11 +223,30 @@ static const struct regulator_ops bd718xx_pickable_range_buck_ops = { 194 | .disable = regulator_disable_regmap, 195 | .is_enabled = regulator_is_enabled_regmap, 196 | .list_voltage = regulator_list_voltage_pickable_linear_range, 197 | - .set_voltage_sel = bd718xx_set_voltage_sel_pickable_restricted, 198 | + .set_voltage_sel = regulator_set_voltage_sel_pickable_regmap, 199 | + .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, 200 | + .set_voltage_time_sel = regulator_set_voltage_time_sel, 201 | +}; 202 | + 203 | +static const struct regulator_ops bd71837_pickable_range_buck_ops = { 204 | + .enable = regulator_enable_regmap, 205 | + .disable = regulator_disable_regmap, 206 | + .is_enabled = regulator_is_enabled_regmap, 207 | + .list_voltage = regulator_list_voltage_pickable_linear_range, 208 | + .set_voltage_sel = bd71837_set_voltage_sel_pickable_restricted, 209 | .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, 210 | .set_voltage_time_sel = regulator_set_voltage_time_sel, 211 | }; 212 | 213 | +static const struct regulator_ops bd71837_ldo_regulator_ops = { 214 | + .enable = regulator_enable_regmap, 215 | + .disable = regulator_disable_regmap, 216 | + .is_enabled = regulator_is_enabled_regmap, 217 | + .list_voltage = regulator_list_voltage_linear_range, 218 | + .set_voltage_sel = bd71837_set_voltage_sel_restricted, 219 | + .get_voltage_sel = regulator_get_voltage_sel_regmap, 220 | +}; 221 | + 222 | static const struct regulator_ops bd718xx_ldo_regulator_ops = { 223 | .enable = regulator_enable_regmap, 224 | .disable = regulator_disable_regmap, 225 | @@ -106,6 +256,15 @@ static const struct regulator_ops bd718xx_ldo_regulator_ops = { 226 | .get_voltage_sel = regulator_get_voltage_sel_regmap, 227 | }; 228 | 229 | +static const struct regulator_ops bd71837_ldo_regulator_nolinear_ops = { 230 | + .enable = regulator_enable_regmap, 231 | + .disable = regulator_disable_regmap, 232 | + .is_enabled = regulator_is_enabled_regmap, 233 | + .list_voltage = regulator_list_voltage_table, 234 | + .set_voltage_sel = bd71837_set_voltage_sel_restricted, 235 | + .get_voltage_sel = regulator_get_voltage_sel_regmap, 236 | +}; 237 | + 238 | static const struct regulator_ops bd718xx_ldo_regulator_nolinear_ops = { 239 | .enable = regulator_enable_regmap, 240 | .disable = regulator_disable_regmap, 241 | @@ -120,7 +279,17 @@ static const struct regulator_ops bd718xx_buck_regulator_ops = { 242 | .disable = regulator_disable_regmap, 243 | .is_enabled = regulator_is_enabled_regmap, 244 | .list_voltage = regulator_list_voltage_linear_range, 245 | - .set_voltage_sel = bd718xx_set_voltage_sel_restricted, 246 | + .set_voltage_sel = regulator_set_voltage_sel_regmap, 247 | + .get_voltage_sel = regulator_get_voltage_sel_regmap, 248 | + .set_voltage_time_sel = regulator_set_voltage_time_sel, 249 | +}; 250 | + 251 | +static const struct regulator_ops bd71837_buck_regulator_ops = { 252 | + .enable = regulator_enable_regmap, 253 | + .disable = regulator_disable_regmap, 254 | + .is_enabled = regulator_is_enabled_regmap, 255 | + .list_voltage = regulator_list_voltage_linear_range, 256 | + .set_voltage_sel = bd71837_set_voltage_sel_restricted, 257 | .get_voltage_sel = regulator_get_voltage_sel_regmap, 258 | .set_voltage_time_sel = regulator_set_voltage_time_sel, 259 | }; 260 | @@ -902,7 +1071,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 261 | .of_match = of_match_ptr("LDO1"), 262 | .regulators_node = of_match_ptr("regulators"), 263 | .id = BD718XX_LDO1, 264 | - .ops = &bd718xx_pickable_range_ldo_ops, 265 | + .ops = &bd71837_pickable_range_ldo_ops, 266 | .type = REGULATOR_VOLTAGE, 267 | .n_voltages = BD718XX_LDO1_VOLTAGE_NUM, 268 | .linear_ranges = bd718xx_ldo1_volts, 269 | @@ -928,7 +1097,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 270 | .of_match = of_match_ptr("LDO2"), 271 | .regulators_node = of_match_ptr("regulators"), 272 | .id = BD718XX_LDO2, 273 | - .ops = &bd718xx_ldo_regulator_nolinear_ops, 274 | + .ops = &bd71837_ldo_regulator_nolinear_ops, 275 | .type = REGULATOR_VOLTAGE, 276 | .volt_table = &ldo_2_volts[0], 277 | .vsel_reg = BD718XX_REG_LDO2_VOLT, 278 | @@ -950,7 +1119,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 279 | .of_match = of_match_ptr("LDO3"), 280 | .regulators_node = of_match_ptr("regulators"), 281 | .id = BD718XX_LDO3, 282 | - .ops = &bd718xx_ldo_regulator_ops, 283 | + .ops = &bd71837_ldo_regulator_ops, 284 | .type = REGULATOR_VOLTAGE, 285 | .n_voltages = BD718XX_LDO3_VOLTAGE_NUM, 286 | .linear_ranges = bd718xx_ldo3_volts, 287 | @@ -973,7 +1142,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 288 | .of_match = of_match_ptr("LDO4"), 289 | .regulators_node = of_match_ptr("regulators"), 290 | .id = BD718XX_LDO4, 291 | - .ops = &bd718xx_ldo_regulator_ops, 292 | + .ops = &bd71837_ldo_regulator_ops, 293 | .type = REGULATOR_VOLTAGE, 294 | .n_voltages = BD718XX_LDO4_VOLTAGE_NUM, 295 | .linear_ranges = bd718xx_ldo4_volts, 296 | @@ -996,7 +1165,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 297 | .of_match = of_match_ptr("LDO5"), 298 | .regulators_node = of_match_ptr("regulators"), 299 | .id = BD718XX_LDO5, 300 | - .ops = &bd718xx_ldo_regulator_ops, 301 | + .ops = &bd71837_ldo_regulator_ops, 302 | .type = REGULATOR_VOLTAGE, 303 | .n_voltages = BD71837_LDO5_VOLTAGE_NUM, 304 | .linear_ranges = bd71837_ldo5_volts, 305 | @@ -1023,7 +1192,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 306 | .of_match = of_match_ptr("LDO6"), 307 | .regulators_node = of_match_ptr("regulators"), 308 | .id = BD718XX_LDO6, 309 | - .ops = &bd718xx_ldo_regulator_ops, 310 | + .ops = &bd71837_ldo_regulator_ops, 311 | .type = REGULATOR_VOLTAGE, 312 | .n_voltages = BD718XX_LDO6_VOLTAGE_NUM, 313 | .linear_ranges = bd718xx_ldo6_volts, 314 | @@ -1050,7 +1219,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { 315 | .of_match = of_match_ptr("LDO7"), 316 | .regulators_node = of_match_ptr("regulators"), 317 | .id = BD718XX_LDO7, 318 | - .ops = &bd718xx_ldo_regulator_ops, 319 | + .ops = &bd71837_ldo_regulator_ops, 320 | .type = REGULATOR_VOLTAGE, 321 | .n_voltages = BD71837_LDO7_VOLTAGE_NUM, 322 | .linear_ranges = bd71837_ldo7_volts, 323 | -- 324 | 2.39.2 325 | 326 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0006-arm64-dts-freescale-add-initial-support-for-Google-i.patch: -------------------------------------------------------------------------------- 1 | From ca22043e293c06fb9ec120304e963047c49c7ece Mon Sep 17 00:00:00 2001 2 | From: Marco Antonio Franchi 3 | Date: Tue, 17 Dec 2019 13:36:17 +0000 4 | Subject: [PATCH 06/21] arm64: dts: freescale: add initial support for Google 5 | i.MX 8MQ Phanbell 6 | 7 | This patch adds the device tree to support Google Coral Edge TPU, 8 | historicaly named as fsl-imx8mq-phanbell, a computer on module 9 | which can be used for AI/ML propose. 10 | 11 | It introduces a minimal enablement support for this module and 12 | was totally based on the NXP i.MX 8MQ EVK board and i.MX 8MQ Phanbell 13 | Google Source Code for Coral Edge TPU Mendel release: 14 | https://coral.googlesource.com/linux-imx/ 15 | 16 | Tested components: 17 | - PMIC; 18 | - USB-C OTG; 19 | - USB-C PWR; 20 | - micro-USB; 21 | - USB. 22 | 23 | Signed-off-by: Marco Franchi 24 | Reviewed-by: Fabio Estevam 25 | Signed-off-by: Shawn Guo 26 | --- 27 | arch/arm64/boot/dts/freescale/Makefile | 1 + 28 | .../boot/dts/freescale/imx8mq-phanbell.dts | 376 ++++++++++++++++++ 29 | 2 files changed, 377 insertions(+) 30 | create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 31 | 32 | diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile 33 | index d5eb439fe4a6..fafdad5368ff 100644 34 | --- a/arch/arm64/boot/dts/freescale/Makefile 35 | +++ b/arch/arm64/boot/dts/freescale/Makefile 36 | @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb 37 | dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb 38 | dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb 39 | dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dp.dtb 40 | +dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb 41 | dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb 42 | dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb 43 | dtb-$(CONFIG_ARCH_MXC) += imx8mq-ddr3l-val.dtb imx8mq-ddr4-val.dtb imx8mq-ddr4-val-gpmi-nand.dtb 44 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 45 | new file mode 100644 46 | index 000000000000..3f2a489a4ad8 47 | --- /dev/null 48 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 49 | @@ -0,0 +1,376 @@ 50 | +// SPDX-License-Identifier: (GPL-2.0 OR MIT) 51 | +/* 52 | + * Copyright 2017-2019 NXP 53 | + */ 54 | + 55 | +/dts-v1/; 56 | + 57 | +#include "imx8mq.dtsi" 58 | + 59 | +/ { 60 | + model = "Google i.MX8MQ Phanbell"; 61 | + compatible = "google,imx8mq-phanbell", "fsl,imx8mq"; 62 | + 63 | + chosen { 64 | + stdout-path = &uart1; 65 | + }; 66 | + 67 | + memory@40000000 { 68 | + device_type = "memory"; 69 | + reg = <0x00000000 0x40000000 0 0x40000000>; 70 | + }; 71 | + 72 | + pmic_osc: clock-pmic { 73 | + compatible = "fixed-clock"; 74 | + #clock-cells = <0>; 75 | + clock-frequency = <32768>; 76 | + clock-output-names = "pmic_osc"; 77 | + }; 78 | + 79 | + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 80 | + compatible = "regulator-fixed"; 81 | + regulator-name = "VSD_3V3"; 82 | + regulator-min-microvolt = <3300000>; 83 | + regulator-max-microvolt = <3300000>; 84 | + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 85 | + enable-active-high; 86 | + }; 87 | +}; 88 | + 89 | +&A53_0 { 90 | + cpu-supply = <&buck2>; 91 | +}; 92 | + 93 | +&A53_1 { 94 | + cpu-supply = <&buck2>; 95 | +}; 96 | + 97 | +&A53_2 { 98 | + cpu-supply = <&buck2>; 99 | +}; 100 | + 101 | +&A53_3 { 102 | + cpu-supply = <&buck2>; 103 | +}; 104 | + 105 | +&i2c1 { 106 | + clock-frequency = <400000>; 107 | + pinctrl-names = "default"; 108 | + pinctrl-0 = <&pinctrl_i2c1>; 109 | + status = "okay"; 110 | + 111 | + pmic: pmic@4b { 112 | + compatible = "rohm,bd71837"; 113 | + reg = <0x4b>; 114 | + pinctrl-names = "default"; 115 | + pinctrl-0 = <&pinctrl_pmic>; 116 | + #clock-cells = <0>; 117 | + clocks = <&pmic_osc>; 118 | + clock-output-names = "pmic_clk"; 119 | + interrupt-parent = <&gpio1>; 120 | + interrupts = <3 GPIO_ACTIVE_LOW>; 121 | + 122 | + regulators { 123 | + buck1: BUCK1 { 124 | + regulator-name = "buck1"; 125 | + regulator-min-microvolt = <700000>; 126 | + regulator-max-microvolt = <1300000>; 127 | + regulator-boot-on; 128 | + regulator-always-on; 129 | + regulator-ramp-delay = <1250>; 130 | + rohm,dvs-run-voltage = <900000>; 131 | + rohm,dvs-idle-voltage = <900000>; 132 | + rohm,dvs-suspend-voltage = <800000>; 133 | + }; 134 | + 135 | + buck2: BUCK2 { 136 | + regulator-name = "buck2"; 137 | + regulator-min-microvolt = <850000>; 138 | + regulator-max-microvolt = <1000000>; 139 | + regulator-boot-on; 140 | + regulator-always-on; 141 | + rohm,dvs-run-voltage = <1000000>; 142 | + rohm,dvs-idle-voltage = <900000>; 143 | + }; 144 | + 145 | + buck3: BUCK3 { 146 | + regulator-name = "buck3"; 147 | + regulator-min-microvolt = <700000>; 148 | + regulator-max-microvolt = <1300000>; 149 | + regulator-boot-on; 150 | + rohm,dvs-run-voltage = <900000>; 151 | + }; 152 | + 153 | + buck4: BUCK4 { 154 | + regulator-name = "buck4"; 155 | + regulator-min-microvolt = <700000>; 156 | + regulator-max-microvolt = <1300000>; 157 | + regulator-boot-on; 158 | + regulator-always-on; 159 | + rohm,dvs-run-voltage = <900000>; 160 | + }; 161 | + 162 | + buck5: BUCK5 { 163 | + regulator-name = "buck5"; 164 | + regulator-min-microvolt = <700000>; 165 | + regulator-max-microvolt = <1350000>; 166 | + regulator-boot-on; 167 | + regulator-always-on; 168 | + }; 169 | + 170 | + buck6: BUCK6 { 171 | + regulator-name = "buck6"; 172 | + regulator-min-microvolt = <3000000>; 173 | + regulator-max-microvolt = <3300000>; 174 | + regulator-boot-on; 175 | + regulator-always-on; 176 | + }; 177 | + 178 | + buck7: BUCK7 { 179 | + regulator-name = "buck7"; 180 | + regulator-min-microvolt = <1605000>; 181 | + regulator-max-microvolt = <1995000>; 182 | + regulator-boot-on; 183 | + regulator-always-on; 184 | + }; 185 | + 186 | + buck8: BUCK8 { 187 | + regulator-name = "buck8"; 188 | + regulator-min-microvolt = <800000>; 189 | + regulator-max-microvolt = <1400000>; 190 | + regulator-boot-on; 191 | + regulator-always-on; 192 | + }; 193 | + 194 | + ldo1: LDO1 { 195 | + regulator-name = "ldo1"; 196 | + regulator-min-microvolt = <3000000>; 197 | + regulator-max-microvolt = <3300000>; 198 | + regulator-boot-on; 199 | + regulator-always-on; 200 | + }; 201 | + 202 | + ldo2: LDO2 { 203 | + regulator-name = "ldo2"; 204 | + regulator-min-microvolt = <900000>; 205 | + regulator-max-microvolt = <900000>; 206 | + regulator-boot-on; 207 | + regulator-always-on; 208 | + }; 209 | + 210 | + ldo3: LDO3 { 211 | + regulator-name = "ldo3"; 212 | + regulator-min-microvolt = <1800000>; 213 | + regulator-max-microvolt = <3300000>; 214 | + regulator-boot-on; 215 | + regulator-always-on; 216 | + }; 217 | + 218 | + ldo4: LDO4 { 219 | + regulator-name = "ldo4"; 220 | + regulator-min-microvolt = <900000>; 221 | + regulator-max-microvolt = <1800000>; 222 | + regulator-boot-on; 223 | + regulator-always-on; 224 | + }; 225 | + 226 | + ldo5: LDO5 { 227 | + regulator-name = "ldo5"; 228 | + regulator-min-microvolt = <1800000>; 229 | + regulator-max-microvolt = <3300000>; 230 | + regulator-boot-on; 231 | + regulator-always-on; 232 | + }; 233 | + 234 | + ldo6: LDO6 { 235 | + regulator-name = "ldo6"; 236 | + regulator-min-microvolt = <900000>; 237 | + regulator-max-microvolt = <1800000>; 238 | + regulator-boot-on; 239 | + regulator-always-on; 240 | + }; 241 | + 242 | + ldo7: LDO7 { 243 | + regulator-name = "ldo7"; 244 | + regulator-min-microvolt = <1800000>; 245 | + regulator-max-microvolt = <3300000>; 246 | + regulator-boot-on; 247 | + regulator-always-on; 248 | + }; 249 | + }; 250 | + }; 251 | +}; 252 | + 253 | +&uart1 { 254 | + pinctrl-names = "default"; 255 | + pinctrl-0 = <&pinctrl_uart1>; 256 | + status = "okay"; 257 | +}; 258 | + 259 | +&usdhc1 { 260 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 261 | + pinctrl-0 = <&pinctrl_usdhc1>; 262 | + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 263 | + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 264 | + bus-width = <8>; 265 | + non-removable; 266 | + status = "okay"; 267 | +}; 268 | + 269 | +&usdhc2 { 270 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 271 | + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 272 | + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 273 | + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 274 | + bus-width = <4>; 275 | + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 276 | + vmmc-supply = <®_usdhc2_vmmc>; 277 | + status = "okay"; 278 | +}; 279 | + 280 | +&usb3_phy0 { 281 | + status = "okay"; 282 | +}; 283 | + 284 | +&usb_dwc3_0 { 285 | + dr_mode = "otg"; 286 | + status = "okay"; 287 | +}; 288 | + 289 | +&usb3_phy1 { 290 | + status = "okay"; 291 | +}; 292 | + 293 | +&usb_dwc3_1 { 294 | + dr_mode = "host"; 295 | + status = "okay"; 296 | +}; 297 | + 298 | +&wdog1 { 299 | + pinctrl-names = "default"; 300 | + pinctrl-0 = <&pinctrl_wdog>; 301 | + fsl,ext-reset-output; 302 | + status = "okay"; 303 | +}; 304 | + 305 | +&iomuxc { 306 | + pinctrl_i2c1: i2c1grp { 307 | + fsl,pins = < 308 | + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 309 | + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 310 | + >; 311 | + }; 312 | + 313 | + pinctrl_pmic: pmicirq { 314 | + fsl,pins = < 315 | + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 316 | + >; 317 | + }; 318 | + 319 | + pinctrl_uart1: uart1grp { 320 | + fsl,pins = < 321 | + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 322 | + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 323 | + >; 324 | + }; 325 | + 326 | + pinctrl_usdhc1: usdhc1grp { 327 | + fsl,pins = < 328 | + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 329 | + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 330 | + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 331 | + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 332 | + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 333 | + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 334 | + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 335 | + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 336 | + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 337 | + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 338 | + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 339 | + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 340 | + >; 341 | + }; 342 | + 343 | + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 344 | + fsl,pins = < 345 | + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 346 | + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 347 | + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 348 | + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 349 | + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 350 | + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 351 | + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 352 | + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 353 | + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 354 | + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 355 | + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 356 | + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 357 | + >; 358 | + }; 359 | + 360 | + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 361 | + fsl,pins = < 362 | + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 363 | + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 364 | + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 365 | + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 366 | + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 367 | + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 368 | + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 369 | + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 370 | + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 371 | + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 372 | + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 373 | + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 374 | + >; 375 | + }; 376 | + 377 | + pinctrl_usdhc2_gpio: usdhc2grpgpio { 378 | + fsl,pins = < 379 | + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 380 | + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 381 | + >; 382 | + }; 383 | + 384 | + pinctrl_usdhc2: usdhc2grp { 385 | + fsl,pins = < 386 | + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 387 | + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 388 | + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 389 | + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 390 | + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 391 | + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 392 | + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 393 | + >; 394 | + }; 395 | + 396 | + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 397 | + fsl,pins = < 398 | + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 399 | + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 400 | + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 401 | + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 402 | + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 403 | + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 404 | + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 405 | + >; 406 | + }; 407 | + 408 | + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 409 | + fsl,pins = < 410 | + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 411 | + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 412 | + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 413 | + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 414 | + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 415 | + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 416 | + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 417 | + >; 418 | + }; 419 | + 420 | + pinctrl_wdog: wdoggrp { 421 | + fsl,pins = < 422 | + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 423 | + >; 424 | + }; 425 | +}; 426 | -- 427 | 2.39.2 428 | 429 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0007-arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch: -------------------------------------------------------------------------------- 1 | From 9cf62eac95c7392a0075722c1bf5cdbfdd4393e4 Mon Sep 17 00:00:00 2001 2 | From: Alifer Moraes 3 | Date: Tue, 11 Feb 2020 10:48:28 -0300 4 | Subject: [PATCH 07/21] arm64: dts: imx8mq-phanbell: Add support for ethernet 5 | 6 | Add support for ethernet on Google's i.MX 8MQ Phanbell 7 | 8 | Signed-off-by: Alifer Moraes 9 | Tested-by: Vitor Massaru Iha 10 | Signed-off-by: Shawn Guo 11 | --- 12 | .../boot/dts/freescale/imx8mq-phanbell.dts | 41 +++++++++++++++++++ 13 | 1 file changed, 41 insertions(+) 14 | 15 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 16 | index 3f2a489a4ad8..16ed13c44a47 100644 17 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 18 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 19 | @@ -201,6 +201,27 @@ 20 | }; 21 | }; 22 | 23 | +&fec1 { 24 | + pinctrl-names = "default"; 25 | + pinctrl-0 = <&pinctrl_fec1>; 26 | + phy-mode = "rgmii-id"; 27 | + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 28 | + phy-reset-duration = <10>; 29 | + phy-reset-post-delay = <30>; 30 | + phy-handle = <ðphy0>; 31 | + fsl,magic-packet; 32 | + status = "okay"; 33 | + 34 | + mdio { 35 | + #address-cells = <1>; 36 | + #size-cells = <0>; 37 | + ethphy0: ethernet-phy@0 { 38 | + compatible = "ethernet-phy-ieee802.3-c22"; 39 | + reg = <0>; 40 | + }; 41 | + }; 42 | +}; 43 | + 44 | &uart1 { 45 | pinctrl-names = "default"; 46 | pinctrl-0 = <&pinctrl_uart1>; 47 | @@ -254,6 +275,26 @@ 48 | }; 49 | 50 | &iomuxc { 51 | + pinctrl_fec1: fec1grp { 52 | + fsl,pins = < 53 | + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 54 | + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 55 | + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 56 | + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 57 | + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 58 | + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 59 | + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 60 | + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 61 | + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 62 | + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 63 | + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 64 | + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 65 | + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 66 | + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 67 | + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 68 | + >; 69 | + }; 70 | + 71 | pinctrl_i2c1: i2c1grp { 72 | fsl,pins = < 73 | MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 74 | -- 75 | 2.39.2 76 | 77 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0008-arm64-dts-imx8mq-phanbell-Add-gpio-fan-thermal-suppo.patch: -------------------------------------------------------------------------------- 1 | From ee0824e83cf33f393a716fb5d93e877b9e430dd2 Mon Sep 17 00:00:00 2001 2 | From: Vitor Massaru Iha 3 | Date: Mon, 2 Mar 2020 22:15:16 -0300 4 | Subject: [PATCH 08/21] arm64: dts: imx8mq-phanbell: Add gpio-fan/thermal 5 | support 6 | 7 | It was based on Google Source Code for Coral Edge TPU Mendel release: 8 | https://coral.googlesource.com/linux-imx/ 9 | 10 | It was tested on Coral Dev Board using this command: 11 | sudo stress --cpu 4 --timeout 3600 12 | 13 | Signed-off-by: Vitor Massaru Iha 14 | Reviewed-by: Fabio Estevam 15 | Signed-off-by: Shawn Guo 16 | --- 17 | .../boot/dts/freescale/imx8mq-phanbell.dts | 63 +++++++++++++++++++ 18 | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- 19 | 2 files changed, 64 insertions(+), 1 deletion(-) 20 | 21 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 22 | index 16ed13c44a47..1a04d01acc18 100644 23 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 24 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 25 | @@ -35,6 +35,16 @@ 26 | gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 27 | enable-active-high; 28 | }; 29 | + 30 | + fan: gpio-fan { 31 | + compatible = "gpio-fan"; 32 | + gpio-fan,speed-map = <0 0 8600 1>; 33 | + gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; 34 | + #cooling-cells = <2>; 35 | + pinctrl-names = "default"; 36 | + pinctrl-0 = <&pinctrl_gpio_fan>; 37 | + status = "okay"; 38 | + }; 39 | }; 40 | 41 | &A53_0 { 42 | @@ -53,6 +63,53 @@ 43 | cpu-supply = <&buck2>; 44 | }; 45 | 46 | +&cpu_thermal { 47 | + trips { 48 | + cpu_alert0: trip0 { 49 | + temperature = <75000>; 50 | + hysteresis = <2000>; 51 | + type = "passive"; 52 | + }; 53 | + 54 | + cpu_alert1: trip1 { 55 | + temperature = <80000>; 56 | + hysteresis = <2000>; 57 | + type = "passive"; 58 | + }; 59 | + 60 | + cpu_crit0: trip3 { 61 | + temperature = <90000>; 62 | + hysteresis = <2000>; 63 | + type = "critical"; 64 | + }; 65 | + 66 | + fan_toggle0: trip4 { 67 | + temperature = <65000>; 68 | + hysteresis = <10000>; 69 | + type = "active"; 70 | + }; 71 | + }; 72 | + 73 | + cooling-maps { 74 | + map0 { 75 | + trip = <&cpu_alert0>; 76 | + cooling-device = 77 | + <&A53_0 0 1>; /* Exclude highest OPP */ 78 | + }; 79 | + 80 | + map1 { 81 | + trip = <&cpu_alert1>; 82 | + cooling-device = 83 | + <&A53_0 0 2>; /* Exclude two highest OPPs */ 84 | + }; 85 | + 86 | + map4 { 87 | + trip = <&fan_toggle0>; 88 | + cooling-device = <&fan 0 1>; 89 | + }; 90 | + }; 91 | +}; 92 | + 93 | &i2c1 { 94 | clock-frequency = <400000>; 95 | pinctrl-names = "default"; 96 | @@ -295,6 +352,12 @@ 97 | >; 98 | }; 99 | 100 | + pinctrl_gpio_fan: gpiofangrp { 101 | + fsl,pins = < 102 | + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16 103 | + >; 104 | + }; 105 | + 106 | pinctrl_i2c1: i2c1grp { 107 | fsl,pins = < 108 | MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 109 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi 110 | index b628a5369653..041ead56beea 100755 111 | --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi 112 | +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi 113 | @@ -222,7 +222,7 @@ 114 | }; 115 | 116 | thermal-zones { 117 | - cpu-thermal { 118 | + cpu_thermal: cpu-thermal { 119 | polling-delay-passive = <250>; 120 | polling-delay = <2000>; 121 | thermal-sensors = <&tmu 0>; 122 | -- 123 | 2.39.2 124 | 125 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0009-arm64-dts-imx8mq-phanbell-Fix-Ethernet-PHY-post-rese.patch: -------------------------------------------------------------------------------- 1 | From f1eacbecb579c548724704c740848da19dffc5b6 Mon Sep 17 00:00:00 2001 2 | From: Alifer Moraes 3 | Date: Fri, 6 Mar 2020 07:42:19 -0300 4 | Subject: [PATCH 09/21] arm64: dts: imx8mq-phanbell: Fix Ethernet PHY 5 | post-reset duration 6 | 7 | i.MX8MQ Phanbell board uses Realtek RTL8211FD as Ethernet PHY. 8 | Its datasheet states that the proper post reset duration should be at least 50 ms. 9 | 10 | Fixes: f34d4bfab354 ("arm64: dts: imx8mq-phanbell: Add support for ethernet") 11 | Signed-off-by: Alifer Moraes 12 | Signed-off-by: Shawn Guo 13 | --- 14 | arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 2 +- 15 | 1 file changed, 1 insertion(+), 1 deletion(-) 16 | 17 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 18 | index 1a04d01acc18..77ab568fae67 100644 19 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 20 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 21 | @@ -264,7 +264,7 @@ 22 | phy-mode = "rgmii-id"; 23 | phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 24 | phy-reset-duration = <10>; 25 | - phy-reset-post-delay = <30>; 26 | + phy-reset-post-delay = <50>; 27 | phy-handle = <ðphy0>; 28 | fsl,magic-packet; 29 | status = "okay"; 30 | -- 31 | 2.39.2 32 | 33 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0010-arm64-dts-imx8mq-phanbell-Replace-deprecated-phy-res.patch: -------------------------------------------------------------------------------- 1 | From 5df89084e49729eafa4eb8b7833674668086cf15 Mon Sep 17 00:00:00 2001 2 | From: Krzysztof Kozlowski 3 | Date: Sun, 23 Aug 2020 13:15:06 +0200 4 | Subject: [PATCH 10/21] arm64: dts: imx8mq-phanbell: Replace deprecated phy 5 | reset properties 6 | 7 | Use preferred properties of phy node instead of deprecated 8 | phy-reset-gpios (and others). This avoids copying deprecated code into 9 | future DTSes. 10 | 11 | Signed-off-by: Krzysztof Kozlowski 12 | Signed-off-by: Shawn Guo 13 | --- 14 | arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 6 +++--- 15 | 1 file changed, 3 insertions(+), 3 deletions(-) 16 | 17 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 18 | index 77ab568fae67..3f541ddf0768 100644 19 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 20 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 21 | @@ -262,9 +262,6 @@ 22 | pinctrl-names = "default"; 23 | pinctrl-0 = <&pinctrl_fec1>; 24 | phy-mode = "rgmii-id"; 25 | - phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 26 | - phy-reset-duration = <10>; 27 | - phy-reset-post-delay = <50>; 28 | phy-handle = <ðphy0>; 29 | fsl,magic-packet; 30 | status = "okay"; 31 | @@ -275,6 +272,9 @@ 32 | ethphy0: ethernet-phy@0 { 33 | compatible = "ethernet-phy-ieee802.3-c22"; 34 | reg = <0>; 35 | + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 36 | + reset-assert-us = <10000>; 37 | + reset-deassert-us = <50000>; 38 | }; 39 | }; 40 | }; 41 | -- 42 | 2.39.2 43 | 44 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0011-arm64-dts-imx8mq-phanbell-Align-pin-configuration-gr.patch: -------------------------------------------------------------------------------- 1 | From d7cc3d71a65a2f611efb98ed0c39f85b3d5263f6 Mon Sep 17 00:00:00 2001 2 | From: Krzysztof Kozlowski 3 | Date: Fri, 28 Aug 2020 18:47:46 +0200 4 | Subject: [PATCH 11/21] arm64: dts: imx8mq-phanbell: Align pin configuration 5 | group names with schema 6 | 7 | Device tree schema expects pin configuration groups to end with 'grp' 8 | suffix, otherwise dtbs_check complain with a warning like: 9 | 10 | ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' 11 | 12 | Signed-off-by: Krzysztof Kozlowski 13 | Signed-off-by: Shawn Guo 14 | --- 15 | arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++++++------ 16 | 1 file changed, 6 insertions(+), 6 deletions(-) 17 | 18 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 19 | index 3f541ddf0768..d6d3a3d5abc3 100644 20 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 21 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 22 | @@ -365,7 +365,7 @@ 23 | >; 24 | }; 25 | 26 | - pinctrl_pmic: pmicirq { 27 | + pinctrl_pmic: pmicirqgrp { 28 | fsl,pins = < 29 | MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 30 | >; 31 | @@ -395,7 +395,7 @@ 32 | >; 33 | }; 34 | 35 | - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 36 | + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 37 | fsl,pins = < 38 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 39 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 40 | @@ -412,7 +412,7 @@ 41 | >; 42 | }; 43 | 44 | - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 45 | + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 46 | fsl,pins = < 47 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 48 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 49 | @@ -429,7 +429,7 @@ 50 | >; 51 | }; 52 | 53 | - pinctrl_usdhc2_gpio: usdhc2grpgpio { 54 | + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 55 | fsl,pins = < 56 | MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 57 | MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 58 | @@ -448,7 +448,7 @@ 59 | >; 60 | }; 61 | 62 | - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 63 | + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 64 | fsl,pins = < 65 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 66 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 67 | @@ -460,7 +460,7 @@ 68 | >; 69 | }; 70 | 71 | - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 72 | + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 73 | fsl,pins = < 74 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 75 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 76 | -- 77 | 2.39.2 78 | 79 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0012-arm64-dts-imx8mq-phanbell-Disable-busfreq-to-avoid-s.patch: -------------------------------------------------------------------------------- 1 | From 8d652338e1944cafff83e1470b64ebd6232b577c Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Thu, 22 Oct 2020 21:44:02 +0900 4 | Subject: [PATCH 12/21] arm64: dts: imx8mq-phanbell: Disable busfreq to avoid 5 | system hang 6 | 7 | Avoid system hang on boot by disabling busfreq driver for i.MX8MQ 8 | Phanbell board. 9 | 10 | Signed-off-by: Ryosuke Saito 11 | --- 12 | arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 4 ++++ 13 | 1 file changed, 4 insertions(+) 14 | 15 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 16 | index d6d3a3d5abc3..dc0270787f7b 100644 17 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 18 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 19 | @@ -20,6 +20,10 @@ 20 | reg = <0x00000000 0x40000000 0 0x40000000>; 21 | }; 22 | 23 | + busfreq { 24 | + status = "disabled"; 25 | + }; 26 | + 27 | pmic_osc: clock-pmic { 28 | compatible = "fixed-clock"; 29 | #clock-cells = <0>; 30 | -- 31 | 2.39.2 32 | 33 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0013-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch: -------------------------------------------------------------------------------- 1 | From e645d6b386a83843a36608ba3be7f864dfc06a91 Mon Sep 17 00:00:00 2001 2 | From: Richard Zhu 3 | Date: Wed, 21 Jun 2017 10:23:00 +0800 4 | Subject: [PATCH 13/21] MLK-15307-2 clk: imx8mq: set the parent clocks of PCIE 5 | 6 | Configure the parent clocks of PCIE. 7 | 8 | Signed-off-by: Richard Zhu 9 | Signed-off-by: Ryosuke Saito 10 | --- 11 | drivers/clk/imx/clk-imx8mq.c | 6 ++++++ 12 | 1 file changed, 6 insertions(+) 13 | 14 | diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c 15 | index f8aaed0712f2..7f7faa6cd9f9 100644 16 | --- a/drivers/clk/imx/clk-imx8mq.c 17 | +++ b/drivers/clk/imx/clk-imx8mq.c 18 | @@ -612,6 +612,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 19 | /* enable all the clocks just for bringup */ 20 | imx_clk_init_on(np, clks); 21 | 22 | + /* set pcie root's parent clk source */ 23 | + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_CTRL], clks[IMX8MQ_SYS2_PLL_250M]); 24 | + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_PHY], clks[IMX8MQ_SYS2_PLL_100M]); 25 | + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_CTRL], clks[IMX8MQ_SYS2_PLL_250M]); 26 | + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_PHY], clks[IMX8MQ_SYS2_PLL_100M]); 27 | + 28 | clk_set_parent(clks[IMX8MQ_CLK_CSI1_CORE], clks[IMX8MQ_SYS1_PLL_266M]); 29 | clk_set_parent(clks[IMX8MQ_CLK_CSI1_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]); 30 | clk_set_parent(clks[IMX8MQ_CLK_CSI1_ESC], clks[IMX8MQ_SYS1_PLL_800M]); 31 | -- 32 | 2.39.2 33 | 34 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0014-arm64-dts-imx8mq-Set-ext_osc-to-1-as-default.patch: -------------------------------------------------------------------------------- 1 | From 02b389837fff9bee4a0221513e7185277fa4ca92 Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Mon, 9 Nov 2020 21:18:54 +0900 4 | Subject: [PATCH] arm64: dts: imx8mq: Set ext_osc to 1 as default 5 | 6 | Currently, imx8mq PCIe driver codes assume that the external clock 7 | generator is always used but e.g. imx8mq-phanbell board is an exception. 8 | Such boards have to be configured with the internal PLL as PCIe REF 9 | clock. 10 | 11 | Since there are many dts files which include imx8mq.dtsi without ext_osc 12 | set properly and use the external clock implicitly, instead of modifying 13 | all such dts files, set the default value of ext_osc to 1 to change the 14 | driver's behavior and be able for such exceptional boards to override it 15 | easily. 16 | 17 | This is not ideal though, makes fewer future conflicts for now. 18 | 19 | Signed-off-by: Ryosuke Saito 20 | --- 21 | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 +++ 22 | 1 file changed, 3 insertions(+) 23 | 24 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi 25 | index d53b658c736e..31d6dddbf50b 100755 26 | --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi 27 | +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi 28 | @@ -1454,6 +1454,7 @@ 29 | <&clk IMX8MQ_SYS1_PLL_80M>; 30 | assigned-clock-rates = <250000000>, <100000000>, 31 | <10000000>; 32 | + ext_osc = <1>; 33 | status = "disabled"; 34 | }; 35 | 36 | @@ -1485,6 +1486,7 @@ 37 | <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ>, 38 | <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 39 | reset-names = "pciephy", "apps", "clkreq", "turnoff"; 40 | + ext_osc = <1>; 41 | status = "disabled"; 42 | }; 43 | 44 | @@ -1512,6 +1514,7 @@ 45 | <10000000>; 46 | num-ib-windows = <4>; 47 | num-ob-windows = <4>; 48 | + ext_osc = <1>; 49 | status = "disabled"; 50 | }; 51 | 52 | -- 53 | 2.39.2 54 | 55 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0015-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch: -------------------------------------------------------------------------------- 1 | From f933537c63c6140707b96463f0573bd75f9a3b23 Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Sun, 15 Nov 2020 22:39:01 +0900 4 | Subject: [PATCH] PCI: imx: Use the external clock as REF_CLK when needed for 5 | i.MX8MQ 6 | 7 | Do not use the external clock when the internal PLL is used as PCIe 8 | REF_CLK. 9 | 10 | Signed-off-by: Ryosuke Saito 11 | --- 12 | drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++-------- 13 | 1 file changed, 7 insertions(+), 8 deletions(-) 14 | 15 | diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c 16 | index 1eed334db638..16844df2dfab 100644 17 | --- a/drivers/pci/controller/dwc/pci-imx6.c 18 | +++ b/drivers/pci/controller/dwc/pci-imx6.c 19 | @@ -1595,14 +1595,13 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 20 | break; 21 | case IMX8MQ: 22 | case IMX8MQ_EP: 23 | - /* 24 | - * TODO: Currently this code assumes external 25 | - * oscillator is being used 26 | - */ 27 | - regmap_update_bits(imx6_pcie->iomuxc_gpr, 28 | - imx6_pcie_grp_offset(imx6_pcie), 29 | - IMX8MQ_GPR_PCIE_REF_USE_PAD, 30 | - IMX8MQ_GPR_PCIE_REF_USE_PAD); 31 | + if (imx6_pcie->ext_osc) { 32 | + /* Use the external oscillator as REF clock */ 33 | + regmap_update_bits(imx6_pcie->iomuxc_gpr, 34 | + imx6_pcie_grp_offset(imx6_pcie), 35 | + IMX8MQ_GPR_PCIE_REF_USE_PAD, 36 | + IMX8MQ_GPR_PCIE_REF_USE_PAD); 37 | + } 38 | /* 39 | * Regarding to the datasheet, the PCIE_VPH is suggested 40 | * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the 41 | -- 42 | 2.39.2 43 | 44 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0016-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch: -------------------------------------------------------------------------------- 1 | From a38acdc9ca4548e7d6afad9bde51a6cd6d2de619 Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Sun, 15 Nov 2020 22:45:53 +0900 4 | Subject: [PATCH] PCI: imx: Provide a clock to the device for i.MX8MQ 5 | 6 | When the internal PLL is configured as PCIe REF_CLK, we also have to 7 | output a clock via CLK2_P/N pin to the connector/device to provide it. 8 | Configure 100 MHz clock as its output. 9 | 10 | Signed-off-by: Ryosuke Saito 11 | --- 12 | drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++ 13 | 1 file changed, 35 insertions(+) 14 | 15 | diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c 16 | index 16844df2dfab..650f54b97929 100644 17 | --- a/drivers/pci/controller/dwc/pci-imx6.c 18 | +++ b/drivers/pci/controller/dwc/pci-imx6.c 19 | @@ -290,6 +290,12 @@ struct imx6_pcie { 20 | #define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) 21 | #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) 22 | 23 | +#define IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG 0x74 24 | +#define IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK GENMASK(3, 0) 25 | +#define IMX8MQ_ANA_PLLOUT_MONITOR_CKE BIT(4) 26 | +#define IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG 0x7C 27 | +#define IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK GENMASK(2, 0) 28 | + 29 | static void imx6_pcie_ltssm_disable(struct device *dev); 30 | 31 | static bool imx6_pcie_readable_reg(struct device *dev, unsigned int reg) 32 | @@ -1601,6 +1607,35 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 33 | imx6_pcie_grp_offset(imx6_pcie), 34 | IMX8MQ_GPR_PCIE_REF_USE_PAD, 35 | IMX8MQ_GPR_PCIE_REF_USE_PAD); 36 | + } else { 37 | + /* 38 | + * Use the internal PLL as REF clock and also 39 | + * provide a clock to the device. 40 | + */ 41 | + struct regmap *anatop = 42 | + syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop"); 43 | + 44 | + if (IS_ERR(anatop)) { 45 | + dev_err(imx6_pcie->pci->dev, 46 | + "Couldn't configure the internal PLL as REF clock\n"); 47 | + break; 48 | + } 49 | + 50 | + /* Select SYSTEM_PLL1_CLK as the clock source */ 51 | + regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, 52 | + IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK, 0xb); 53 | + 54 | + /* 55 | + * SYSTEM_PLL1_CLK is 800 MHz, so divided by 8 56 | + * for generating 100 MHz as output. 57 | + */ 58 | + regmap_update_bits(anatop, IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG, 59 | + IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK, 0x7); 60 | + 61 | + /* Enable CLK2_P/N clock to provide it to the device */ 62 | + regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, 63 | + IMX8MQ_ANA_PLLOUT_MONITOR_CKE, 64 | + IMX8MQ_ANA_PLLOUT_MONITOR_CKE); 65 | } 66 | /* 67 | * Regarding to the datasheet, the PCIE_VPH is suggested 68 | -- 69 | 2.39.2 70 | 71 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0017-arm64-dts-imx8mq-phanbell-Enable-PCIe.patch: -------------------------------------------------------------------------------- 1 | From 300fb8ccf767c216e262cfc8e6efab2cce7e9b13 Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Thu, 5 Nov 2020 22:55:47 +0900 4 | Subject: [PATCH 17/21] arm64: dts: imx8mq-phanbell: Enable PCIe 5 | 6 | Add suport for PCIe. 7 | 8 | Signed-off-by: Ryosuke Saito 9 | --- 10 | .../boot/dts/freescale/imx8mq-phanbell.dts | 75 +++++++++++++++++++ 11 | 1 file changed, 75 insertions(+) 12 | 13 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 14 | index dc0270787f7b..d2a261ebb8e2 100644 15 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 16 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 17 | @@ -49,6 +49,12 @@ 18 | pinctrl-0 = <&pinctrl_gpio_fan>; 19 | status = "okay"; 20 | }; 21 | + 22 | + pcie1_refclk: pcie1-refclk { 23 | + compatible = "fixed-clock"; 24 | + #clock-cells = <0>; 25 | + clock-frequency = <100000000>; 26 | + }; 27 | }; 28 | 29 | &A53_0 { 30 | @@ -114,6 +120,17 @@ 31 | }; 32 | }; 33 | 34 | +&gpio3 { 35 | + pinctrl-names = "default"; 36 | + pinctrl-0 = <&pinctrl_wifi_reset>; 37 | + 38 | + wl-reg-on { 39 | + gpio-hog; 40 | + gpios = <11 GPIO_ACTIVE_HIGH>; 41 | + output-high; 42 | + }; 43 | +}; 44 | + 45 | &i2c1 { 46 | clock-frequency = <400000>; 47 | pinctrl-names = "default"; 48 | @@ -262,6 +279,35 @@ 49 | }; 50 | }; 51 | 52 | +&pcie0 { 53 | + pinctrl-names = "default"; 54 | + pinctrl-0 = <&pinctrl_pcie0>; 55 | + reset-gpio = <&gpio3 10 GPIO_ACTIVE_LOW>; 56 | + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 57 | + <&clk IMX8MQ_CLK_PCIE1_AUX>, 58 | + <&clk IMX8MQ_CLK_PCIE1_PHY>, 59 | + <&clk IMX8MQ_CLK_DUMMY>; 60 | + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 61 | + fsl,max-link-speed = <1>; 62 | + ext_osc = <0>; 63 | + hard-wired = <1>; 64 | + status = "okay"; 65 | +}; 66 | + 67 | +&pcie1 { 68 | + pinctrl-names = "default"; 69 | + pinctrl-0 = <&pinctrl_pcie1>; 70 | + reset-gpio = <&gpio3 18 GPIO_ACTIVE_LOW>; 71 | + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 72 | + <&clk IMX8MQ_CLK_PCIE2_AUX>, 73 | + <&clk IMX8MQ_CLK_PCIE2_PHY>, 74 | + <&pcie1_refclk>; 75 | + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 76 | + ext_osc = <1>; 77 | + hard-wired = <1>; 78 | + status = "okay"; 79 | +}; 80 | + 81 | &fec1 { 82 | pinctrl-names = "default"; 83 | pinctrl-0 = <&pinctrl_fec1>; 84 | @@ -336,6 +382,29 @@ 85 | }; 86 | 87 | &iomuxc { 88 | + pinctrl-names = "default"; 89 | + pinctrl-0 = <&pinctrl_hog>; 90 | + 91 | + pinctrl_hog: hoggrp { 92 | + fsl,pins = < 93 | + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x05 94 | + >; 95 | + }; 96 | + 97 | + pinctrl_pcie0: pcie0grp { 98 | + fsl,pins = < 99 | + MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 100 | + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16 101 | + >; 102 | + }; 103 | + 104 | + pinctrl_pcie1: pcie1grp { 105 | + fsl,pins = < 106 | + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 107 | + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 108 | + >; 109 | + }; 110 | + 111 | pinctrl_fec1: fec1grp { 112 | fsl,pins = < 113 | MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 114 | @@ -481,4 +550,10 @@ 115 | MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 116 | >; 117 | }; 118 | + 119 | + pinctrl_wifi_reset: wifiresetgrp { 120 | + fsl,pins = < 121 | + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 122 | + >; 123 | + }; 124 | }; 125 | -- 126 | 2.39.2 127 | 128 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0018-spi-spi-imx-Revive-cs-gpios-property-for-DT.patch: -------------------------------------------------------------------------------- 1 | From 62ac8479d1a70e2c0ef04a06936e47987f04b180 Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Sat, 2 Jan 2021 19:49:34 +0900 4 | Subject: [PATCH 18/21] spi: spi-imx: Revive cs-gpios property for DT 5 | 6 | The commit 881a0b993e9f ("spi: imx: GPIO based chip selects should not 7 | be required") completely removed the 'cs-gpios' property from DT, but 8 | still, one might require SS/CS lines to be configured as GPIO for some 9 | good reason (e.g., restriction of board I/O pin assignment). 10 | For that, let's revive the property again. 11 | 12 | Signed-off-by: Ryosuke Saito 13 | --- 14 | drivers/spi/spi-imx.c | 16 ++++++++++++++++ 15 | 1 file changed, 16 insertions(+) 16 | 17 | diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c 18 | index 91e32291c44e..4b0492bd0e00 100644 19 | --- a/drivers/spi/spi-imx.c 20 | +++ b/drivers/spi/spi-imx.c 21 | @@ -1685,6 +1685,22 @@ static int spi_imx_probe(struct platform_device *pdev) 22 | if (!of_property_read_u32(np, "num-cs", &num_cs)) 23 | master->num_chipselect = num_cs; 24 | /* If not preset, default value of 1 is used */ 25 | + 26 | + if (of_find_property(np, "cs-gpios", NULL)) { 27 | + master->cs_gpios = devm_kcalloc(&master->dev, 28 | + master->num_chipselect, 29 | + sizeof(int), GFP_KERNEL); 30 | + if (!master->cs_gpios) 31 | + return -ENOMEM; 32 | + 33 | + for (i = 0; i < master->num_chipselect; i++) { 34 | + ret = of_get_named_gpio(np, "cs-gpios", i); 35 | + if (ret < 0) 36 | + goto out_master_put; 37 | + 38 | + master->cs_gpios[i] = ret; 39 | + } 40 | + } 41 | } 42 | 43 | spi_imx->bitbang.chipselect = spi_imx_chipselect; 44 | -- 45 | 2.39.2 46 | 47 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0019-arm64-dts-imx8mq-phanbell-Enable-ECSPI1.patch: -------------------------------------------------------------------------------- 1 | From 40a8007cb59fefd4fc83c003742cf12cfae607ba Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Sat, 2 Jan 2021 19:55:05 +0900 4 | Subject: [PATCH 19/21] arm64: dts: imx8mq-phanbell: Enable ECSPI1 5 | 6 | Add ecspi1 enabled with two spidev devices. 7 | 8 | Signed-off-by: Ryosuke Saito 9 | --- 10 | .../boot/dts/freescale/imx8mq-phanbell.dts | 36 +++++++++++++++++++ 11 | 1 file changed, 36 insertions(+) 12 | 13 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 14 | index d2a261ebb8e2..386ef06d698d 100644 15 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 16 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 17 | @@ -308,6 +308,27 @@ 18 | status = "okay"; 19 | }; 20 | 21 | +&ecspi1 { 22 | + pinctrl-names = "default"; 23 | + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 24 | + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>, 25 | + <&gpio3 2 GPIO_ACTIVE_HIGH>; 26 | + num-cs = <2>; 27 | + status = "okay"; 28 | + 29 | + spidev@0 { 30 | + compatible = "rohm,dh2228fv"; 31 | + spi-max-frequency = <20000000>; 32 | + reg = <0>; 33 | + }; 34 | + 35 | + spidev@1 { 36 | + compatible = "rohm,dh2228fv"; 37 | + spi-max-frequency = <20000000>; 38 | + reg = <1>; 39 | + }; 40 | +}; 41 | + 42 | &fec1 { 43 | pinctrl-names = "default"; 44 | pinctrl-0 = <&pinctrl_fec1>; 45 | @@ -405,6 +426,21 @@ 46 | >; 47 | }; 48 | 49 | + pinctrl_ecspi1: ecspi1grp { 50 | + fsl,pins = < 51 | + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 52 | + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 53 | + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 54 | + >; 55 | + }; 56 | + 57 | + pinctrl_ecspi1_cs: ecspi1_cs_grp { 58 | + fsl,pins = < 59 | + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x82 60 | + MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x82 61 | + >; 62 | + }; 63 | + 64 | pinctrl_fec1: fec1grp { 65 | fsl,pins = < 66 | MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 67 | -- 68 | 2.39.2 69 | 70 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0020-arm64-dts-imx8mq-phanbell-Add-gpio-pinmux-for-40-pin.patch: -------------------------------------------------------------------------------- 1 | From 71e58a267131a7ca719c647c7ec2be002010d5c6 Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Sat, 2 Jan 2021 19:56:43 +0900 4 | Subject: [PATCH 20/21] arm64: dts: imx8mq-phanbell: Add gpio pinmux for 40-pin 5 | header 6 | 7 | Add gpio pinmux for the 40-pin expansion header on the board. 8 | 9 | Signed-off-by: Ryosuke Saito 10 | --- 11 | arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 10 ++++++++++ 12 | 1 file changed, 10 insertions(+) 13 | 14 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 15 | index 386ef06d698d..47c55e986da0 100644 16 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 17 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 18 | @@ -409,6 +409,16 @@ 19 | pinctrl_hog: hoggrp { 20 | fsl,pins = < 21 | MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x05 22 | + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 23 | + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 24 | + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 25 | + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 26 | + MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x19 27 | + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 28 | + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 29 | + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 30 | + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x19 31 | + MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 32 | >; 33 | }; 34 | 35 | -- 36 | 2.39.2 37 | 38 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral-5.4/0021-arm64-dts-imx8mq-phanbell-Enable-I2C-2-I2C-3.patch: -------------------------------------------------------------------------------- 1 | From 324a26744442949fab8aa9aeafe2bae25e9d5707 Mon Sep 17 00:00:00 2001 2 | From: Ryosuke Saito 3 | Date: Fri, 23 Apr 2021 19:20:57 +0900 4 | Subject: [PATCH 21/21] arm64: dts: imx8mq-phanbell: Enable I2C-2/I2C-3 5 | 6 | Enable I2C-2/I2C-3 which can be used through Dev Board 40-pin header. 7 | 8 | Signed-off-by: Ryosuke Saito 9 | --- 10 | .../boot/dts/freescale/imx8mq-phanbell.dts | 28 +++++++++++++++++++ 11 | 1 file changed, 28 insertions(+) 12 | 13 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 14 | index 47c55e986da0..b50431ff5f33 100644 15 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 16 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 17 | @@ -279,6 +279,20 @@ 18 | }; 19 | }; 20 | 21 | +&i2c2 { 22 | + clock-frequency = <100000>; 23 | + pinctrl-names = "default"; 24 | + pinctrl-0 = <&pinctrl_i2c2>; 25 | + status = "okay"; 26 | +}; 27 | + 28 | +&i2c3 { 29 | + clock-frequency = <100000>; 30 | + pinctrl-names = "default"; 31 | + pinctrl-0 = <&pinctrl_i2c3>; 32 | + status = "okay"; 33 | +}; 34 | + 35 | &pcie0 { 36 | pinctrl-names = "default"; 37 | pinctrl-0 = <&pinctrl_pcie0>; 38 | @@ -484,6 +498,20 @@ 39 | >; 40 | }; 41 | 42 | + pinctrl_i2c2: i2c2grp { 43 | + fsl,pins = < 44 | + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 45 | + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 46 | + >; 47 | + }; 48 | + 49 | + pinctrl_i2c3: i2c3grp { 50 | + fsl,pins = < 51 | + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f 52 | + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f 53 | + >; 54 | + }; 55 | + 56 | pinctrl_pmic: pmicirqgrp { 57 | fsl,pins = < 58 | MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 59 | -- 60 | 2.39.2 61 | 62 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch: -------------------------------------------------------------------------------- 1 | From 2c97c163df3d1572582858eded96ae3fad852eb0 Mon Sep 17 00:00:00 2001 2 | From: Dirk Mueller 3 | Date: Tue, 14 Jan 2020 18:53:41 +0100 4 | Subject: [PATCH 1/4] scripts/dtc: Remove redundant YYLOC global declaration 5 | 6 | gcc 10 will default to -fno-common, which causes this error at link 7 | time: 8 | 9 | (.text+0x0): multiple definition of `yylloc'; dtc-lexer.lex.o (symbol from plugin):(.text+0x0): first defined here 10 | 11 | This is because both dtc-lexer as well as dtc-parser define the same 12 | global symbol yyloc. Before with -fcommon those were merged into one 13 | defintion. The proper solution would be to to mark this as "extern", 14 | however that leads to: 15 | 16 | dtc-lexer.l:26:16: error: redundant redeclaration of 'yylloc' [-Werror=redundant-decls] 17 | 26 | extern YYLTYPE yylloc; 18 | | ^~~~~~ 19 | In file included from dtc-lexer.l:24: 20 | dtc-parser.tab.h:127:16: note: previous declaration of 'yylloc' was here 21 | 127 | extern YYLTYPE yylloc; 22 | | ^~~~~~ 23 | cc1: all warnings being treated as errors 24 | 25 | which means the declaration is completely redundant and can just be 26 | dropped. 27 | 28 | Signed-off-by: Dirk Mueller 29 | Signed-off-by: David Gibson 30 | [robh: cherry-pick from upstream] 31 | Cc: stable@vger.kernel.org 32 | Signed-off-by: Rob Herring 33 | --- 34 | scripts/dtc/dtc-lexer.l | 1 - 35 | scripts/dtc/dtc-lexer.lex.c_shipped | 1 - 36 | 2 files changed, 2 deletions(-) 37 | 38 | diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l 39 | index fd825ebba69c..24af54997758 100644 40 | --- a/scripts/dtc/dtc-lexer.l 41 | +++ b/scripts/dtc/dtc-lexer.l 42 | @@ -38,7 +38,6 @@ LINECOMMENT "//".*\n 43 | #include "srcpos.h" 44 | #include "dtc-parser.tab.h" 45 | 46 | -YYLTYPE yylloc; 47 | extern bool treesource_error; 48 | 49 | /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ 50 | diff --git a/scripts/dtc/dtc-lexer.lex.c_shipped b/scripts/dtc/dtc-lexer.lex.c_shipped 51 | index 64c243772398..9db3a409c507 100644 52 | --- a/scripts/dtc/dtc-lexer.lex.c_shipped 53 | +++ b/scripts/dtc/dtc-lexer.lex.c_shipped 54 | @@ -631,7 +631,6 @@ char *yytext; 55 | #include "srcpos.h" 56 | #include "dtc-parser.tab.h" 57 | 58 | -YYLTYPE yylloc; 59 | extern bool treesource_error; 60 | 61 | /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ 62 | -- 63 | 2.39.2 64 | 65 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral/0002-include-linux-module.h-copy-__init-__exit-attrs-to-i.patch: -------------------------------------------------------------------------------- 1 | From 50ee39f6075dafd2f7291bba249003e9e5c8b292 Mon Sep 17 00:00:00 2001 2 | From: Miguel Ojeda 3 | Date: Sat, 19 Jan 2019 20:59:34 +0100 4 | Subject: [PATCH 2/4] include/linux/module.h: copy __init/__exit attrs to 5 | init/cleanup_module 6 | 7 | The upcoming GCC 9 release extends the -Wmissing-attributes warnings 8 | (enabled by -Wall) to C and aliases: it warns when particular function 9 | attributes are missing in the aliases but not in their target. 10 | 11 | In particular, it triggers for all the init/cleanup_module 12 | aliases in the kernel (defined by the module_init/exit macros), 13 | ending up being very noisy. 14 | 15 | These aliases point to the __init/__exit functions of a module, 16 | which are defined as __cold (among other attributes). However, 17 | the aliases themselves do not have the __cold attribute. 18 | 19 | Since the compiler behaves differently when compiling a __cold 20 | function as well as when compiling paths leading to calls 21 | to __cold functions, the warning is trying to point out 22 | the possibly-forgotten attribute in the alias. 23 | 24 | In order to keep the warning enabled, we decided to silence 25 | this case. Ideally, we would mark the aliases directly 26 | as __init/__exit. However, there are currently around 132 modules 27 | in the kernel which are missing __init/__exit in their init/cleanup 28 | functions (either because they are missing, or for other reasons, 29 | e.g. the functions being called from somewhere else); and 30 | a section mismatch is a hard error. 31 | 32 | A conservative alternative was to mark the aliases as __cold only. 33 | However, since we would like to eventually enforce __init/__exit 34 | to be always marked, we chose to use the new __copy function 35 | attribute (introduced by GCC 9 as well to deal with this). 36 | With it, we copy the attributes used by the target functions 37 | into the aliases. This way, functions that were not marked 38 | as __init/__exit won't have their aliases marked either, 39 | and therefore there won't be a section mismatch. 40 | 41 | Note that the warning would go away marking either the extern 42 | declaration, the definition, or both. However, we only mark 43 | the definition of the alias, since we do not want callers 44 | (which only see the declaration) to be compiled as if the function 45 | was __cold (and therefore the paths leading to those calls 46 | would be assumed to be unlikely). 47 | 48 | Link: https://lore.kernel.org/lkml/20190123173707.GA16603@gmail.com/ 49 | Link: https://lore.kernel.org/lkml/20190206175627.GA20399@gmail.com/ 50 | Suggested-by: Martin Sebor 51 | Acked-by: Jessica Yu 52 | Signed-off-by: Miguel Ojeda 53 | --- 54 | include/linux/module.h | 4 ++-- 55 | 1 file changed, 2 insertions(+), 2 deletions(-) 56 | 57 | diff --git a/include/linux/module.h b/include/linux/module.h 58 | index a9d546c5b9aa..c290de08c830 100644 59 | --- a/include/linux/module.h 60 | +++ b/include/linux/module.h 61 | @@ -128,13 +128,13 @@ extern void cleanup_module(void); 62 | #define module_init(initfn) \ 63 | static inline initcall_t __maybe_unused __inittest(void) \ 64 | { return initfn; } \ 65 | - int init_module(void) __attribute__((alias(#initfn))); 66 | + int init_module(void) __copy(initfn) __attribute__((alias(#initfn))); 67 | 68 | /* This is only required if you want to be unloadable. */ 69 | #define module_exit(exitfn) \ 70 | static inline exitcall_t __maybe_unused __exittest(void) \ 71 | { return exitfn; } \ 72 | - void cleanup_module(void) __attribute__((alias(#exitfn))); 73 | + void cleanup_module(void) __copy(exitfn) __attribute__((alias(#exitfn))); 74 | 75 | #endif 76 | 77 | -- 78 | 2.39.2 79 | 80 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral/0003-Compiler-Attributes-add-support-for-__copy-gcc-9.patch: -------------------------------------------------------------------------------- 1 | From 34707a2b114814f5974188eef79a725ccd8198bc Mon Sep 17 00:00:00 2001 2 | From: Miguel Ojeda 3 | Date: Fri, 8 Feb 2019 23:51:05 +0100 4 | Subject: [PATCH 3/4] Compiler Attributes: add support for __copy (gcc >= 9) 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | commit c0d9782f5b6d7157635ae2fd782a4b27d55a6013 upstream. 10 | 11 | From the GCC manual: 12 | 13 | copy 14 | copy(function) 15 | 16 | The copy attribute applies the set of attributes with which function 17 | has been declared to the declaration of the function to which 18 | the attribute is applied. The attribute is designed for libraries 19 | that define aliases or function resolvers that are expected 20 | to specify the same set of attributes as their targets. The copy 21 | attribute can be used with functions, variables, or types. However, 22 | the kind of symbol to which the attribute is applied (either 23 | function or variable) must match the kind of symbol to which 24 | the argument refers. The copy attribute copies only syntactic and 25 | semantic attributes but not attributes that affect a symbol’s 26 | linkage or visibility such as alias, visibility, or weak. 27 | The deprecated attribute is also not copied. 28 | 29 | https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html 30 | 31 | The upcoming GCC 9 release extends the -Wmissing-attributes warnings 32 | (enabled by -Wall) to C and aliases: it warns when particular function 33 | attributes are missing in the aliases but not in their target, e.g.: 34 | 35 | void __cold f(void) {} 36 | void __alias("f") g(void); 37 | 38 | diagnoses: 39 | 40 | warning: 'g' specifies less restrictive attribute than 41 | its target 'f': 'cold' [-Wmissing-attributes] 42 | 43 | Using __copy(f) we can copy the __cold attribute from f to g: 44 | 45 | void __cold f(void) {} 46 | void __copy(f) __alias("f") g(void); 47 | 48 | This attribute is most useful to deal with situations where an alias 49 | is declared but we don't know the exact attributes the target has. 50 | 51 | For instance, in the kernel, the widely used module_init/exit macros 52 | define the init/cleanup_module aliases, but those cannot be marked 53 | always as __init/__exit since some modules do not have their 54 | functions marked as such. 55 | 56 | Suggested-by: Martin Sebor 57 | Reviewed-by: Nick Desaulniers 58 | Signed-off-by: Miguel Ojeda 59 | Signed-off-by: Stefan Agner 60 | Signed-off-by: Greg Kroah-Hartman 61 | --- 62 | include/linux/compiler-gcc.h | 4 ++++ 63 | include/linux/compiler_types.h | 4 ++++ 64 | 2 files changed, 8 insertions(+) 65 | 66 | diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h 67 | index 4816355b9875..6d7ead22c1b4 100644 68 | --- a/include/linux/compiler-gcc.h 69 | +++ b/include/linux/compiler-gcc.h 70 | @@ -343,6 +343,10 @@ 71 | #define __designated_init __attribute__((designated_init)) 72 | #endif 73 | 74 | +#if GCC_VERSION >= 90100 75 | +#define __copy(symbol) __attribute__((__copy__(symbol))) 76 | +#endif 77 | + 78 | #endif /* gcc version >= 40000 specific checks */ 79 | 80 | #if !defined(__noclone) 81 | diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h 82 | index 4be464a07612..222fcefaa6a7 100644 83 | --- a/include/linux/compiler_types.h 84 | +++ b/include/linux/compiler_types.h 85 | @@ -230,6 +230,10 @@ struct ftrace_likely_data { 86 | # define __latent_entropy 87 | #endif 88 | 89 | +#ifndef __copy 90 | +# define __copy(symbol) 91 | +#endif 92 | + 93 | #ifndef __randomize_layout 94 | # define __randomize_layout __designated_init 95 | #endif 96 | -- 97 | 2.39.2 98 | 99 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral/0004-Add-an-alias-for-imx8mq-phanbell.dts.patch: -------------------------------------------------------------------------------- 1 | From 262aed6a1fbe0e1bcad71e6572bebe54a64b21de Mon Sep 17 00:00:00 2001 2 | From: Khem Raj 3 | Date: Tue, 14 Feb 2023 12:54:50 -0800 4 | Subject: [PATCH 4/4] Add an alias for imx8mq-phanbell.dts 5 | 6 | Latest fsl kernel has renamed it so. This keeps this kernel working with 7 | newer yocto layers 8 | 9 | Upstream-Status: Inappropriate [OE-specific] 10 | Signed-off-by: Khem Raj 11 | --- 12 | arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 1 + 13 | 1 file changed, 1 insertion(+) 14 | create mode 120000 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 15 | 16 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 17 | new file mode 120000 18 | index 000000000000..2f3aa51ba095 19 | --- /dev/null 20 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 21 | @@ -0,0 +1 @@ 22 | +fsl-imx8mq-phanbell.dts 23 | \ No newline at end of file 24 | -- 25 | 2.39.2 26 | 27 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral_4.14.bb: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2020 Mirza Krak 2 | require recipes-kernel/linux/linux-imx.inc 3 | SUMMARY = "Linux Kernel provided and supported by Google for Coral Dev Board" 4 | 5 | DEPENDS += "lzop-native bc-native" 6 | 7 | LINUX_VERSION = "4.14.98" 8 | 9 | SRCREV = "c13f50afd3920f718f9becc9f47c31fccba00bf7" 10 | SRC_URI = "\ 11 | git://coral.googlesource.com/linux-imx;protocol=https;branch=master \ 12 | file://0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch \ 13 | file://0002-include-linux-module.h-copy-__init-__exit-attrs-to-i.patch \ 14 | file://0003-Compiler-Attributes-add-support-for-__copy-gcc-9.patch \ 15 | file://0004-Add-an-alias-for-imx8mq-phanbell.dts.patch \ 16 | file://defconfig \ 17 | file://mendel.cfg \ 18 | file://extra.cfg \ 19 | " 20 | KERNEL_EXTRA_ARGS += "LOADADDR=${UBOOT_ENTRYPOINT}" 21 | 22 | COMPATIBLE_MACHINE = "coral-dev" 23 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-coral_5.4.bb: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2023 Khem Raj 2 | require recipes-kernel/linux/linux-imx.inc 3 | 4 | LIC_FILES_CHKSUM = "file://COPYING;md5=bbea815ee2795b2f4230826c0c6b8814" 5 | 6 | SUMMARY = "Linux Kernel provided and supported by Google for Coral Dev Board" 7 | 8 | DEPENDS += "lzop-native bc-native" 9 | 10 | LINUX_VERSION = "5.4.237" 11 | 12 | FILESPATH =. "${FILE_DIRNAME}/${BPN}-5.4:" 13 | 14 | SRCREV = "33630781929731d93d24c944689add3da38c8e93" 15 | SRC_URI = "\ 16 | git://github.com/Freescale/linux-fslc;protocol=https;branch=5.4-2.3.x-imx \ 17 | file://extra.cfg \ 18 | file://wifi.cfg \ 19 | file://werror.cfg \ 20 | file://0001-regulator-bd718x7-Add-MODULE_ALIAS.patch \ 21 | file://0002-regulator-bd718x7-Simplify-the-code-by-removing-stru.patch \ 22 | file://0003-mfd-Rohm-PMICs-Use-platform_device_id-to-match-MFD-s.patch \ 23 | file://0004-regulator-bd718x7-Split-driver-to-common-and-bd718x7.patch \ 24 | file://0005-regulator-bd718x7-remove-voltage-change-restriction-.patch \ 25 | file://0006-arm64-dts-freescale-add-initial-support-for-Google-i.patch \ 26 | file://0007-arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch \ 27 | file://0008-arm64-dts-imx8mq-phanbell-Add-gpio-fan-thermal-suppo.patch \ 28 | file://0009-arm64-dts-imx8mq-phanbell-Fix-Ethernet-PHY-post-rese.patch \ 29 | file://0010-arm64-dts-imx8mq-phanbell-Replace-deprecated-phy-res.patch \ 30 | file://0011-arm64-dts-imx8mq-phanbell-Align-pin-configuration-gr.patch \ 31 | file://0012-arm64-dts-imx8mq-phanbell-Disable-busfreq-to-avoid-s.patch \ 32 | file://0013-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch \ 33 | file://0014-arm64-dts-imx8mq-Set-ext_osc-to-1-as-default.patch \ 34 | file://0015-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch \ 35 | file://0016-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch \ 36 | file://0017-arm64-dts-imx8mq-phanbell-Enable-PCIe.patch \ 37 | file://0018-spi-spi-imx-Revive-cs-gpios-property-for-DT.patch \ 38 | file://0019-arm64-dts-imx8mq-phanbell-Enable-ECSPI1.patch \ 39 | file://0020-arm64-dts-imx8mq-phanbell-Add-gpio-pinmux-for-40-pin.patch \ 40 | file://0021-arm64-dts-imx8mq-phanbell-Enable-I2C-2-I2C-3.patch \ 41 | " 42 | KERNEL_EXTRA_ARGS += "LOADADDR=${UBOOT_ENTRYPOINT}" 43 | 44 | OBJCOPY:toolchain-clang = "${HOST_PREFIX}objcopy" 45 | 46 | COMPATIBLE_MACHINE = "coral-dev" 47 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-fslc%.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS:prepend := "${THISDIR}/files:" 2 | 3 | SRC_URI:append:coral-dev = " file://extra.cfg" 4 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-imx-5.15/0001-imx8mq-phanbell.dts-Enable-Coral-specifics-e.g.-PCIE.patch: -------------------------------------------------------------------------------- 1 | From 2806bcdfbe52eeba6d09d3a952e270bdba4b8f19 Mon Sep 17 00:00:00 2001 2 | From: Khem Raj 3 | Date: Tue, 7 Mar 2023 21:02:46 -0800 4 | Subject: [PATCH] imx8mq-phanbell.dts: Enable Coral specifics e.g. PCIE 5 | 6 | Signed-off-by: Khem Raj 7 | --- 8 | .../boot/dts/freescale/imx8mq-phanbell.dts | 155 +++++++++++++++++- 9 | 1 file changed, 154 insertions(+), 1 deletion(-) 10 | 11 | diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 12 | index a3b9d615a3b4..5ce4fc21443e 100644 13 | --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 14 | +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts 15 | @@ -21,6 +21,10 @@ memory@40000000 { 16 | reg = <0x00000000 0x40000000 0 0x40000000>; 17 | }; 18 | 19 | + busfreq { 20 | + status = "disabled"; 21 | + }; 22 | + 23 | pmic_osc: clock-pmic { 24 | compatible = "fixed-clock"; 25 | #clock-cells = <0>; 26 | @@ -46,6 +50,12 @@ fan: gpio-fan { 27 | pinctrl-0 = <&pinctrl_gpio_fan>; 28 | status = "okay"; 29 | }; 30 | + 31 | + pcie1_refclk: pcie1-refclk { 32 | + compatible = "fixed-clock"; 33 | + #clock-cells = <0>; 34 | + clock-frequency = <100000000>; 35 | + }; 36 | }; 37 | 38 | &A53_0 { 39 | @@ -111,6 +121,17 @@ map4 { 40 | }; 41 | }; 42 | 43 | +&gpio3 { 44 | + pinctrl-names = "default"; 45 | + pinctrl-0 = <&pinctrl_wifi_reset>; 46 | + 47 | + wl-reg-on { 48 | + gpio-hog; 49 | + gpios = <11 GPIO_ACTIVE_HIGH>; 50 | + output-high; 51 | + }; 52 | +}; 53 | + 54 | &i2c1 { 55 | clock-frequency = <400000>; 56 | pinctrl-names = "default"; 57 | @@ -126,7 +147,7 @@ pmic: pmic@4b { 58 | clocks = <&pmic_osc>; 59 | clock-output-names = "pmic_clk"; 60 | interrupt-parent = <&gpio1>; 61 | - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 62 | + interrupts = <3 GPIO_ACTIVE_LOW>; 63 | 64 | regulators { 65 | buck1: BUCK1 { 66 | @@ -259,6 +280,70 @@ ldo7: LDO7 { 67 | }; 68 | }; 69 | 70 | +&i2c2 { 71 | + clock-frequency = <100000>; 72 | + pinctrl-names = "default"; 73 | + pinctrl-0 = <&pinctrl_i2c2>; 74 | + status = "okay"; 75 | +}; 76 | + 77 | +&i2c3 { 78 | + clock-frequency = <100000>; 79 | + pinctrl-names = "default"; 80 | + pinctrl-0 = <&pinctrl_i2c3>; 81 | + status = "okay"; 82 | +}; 83 | + 84 | +&pcie0 { 85 | + pinctrl-names = "default"; 86 | + pinctrl-0 = <&pinctrl_pcie0>; 87 | + reset-gpio = <&gpio3 10 GPIO_ACTIVE_LOW>; 88 | + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 89 | + <&clk IMX8MQ_CLK_PCIE1_AUX>, 90 | + <&clk IMX8MQ_CLK_PCIE1_PHY>, 91 | + <&clk IMX8MQ_CLK_DUMMY>; 92 | + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 93 | + fsl,max-link-speed = <1>; 94 | + ext_osc = <0>; 95 | + hard-wired = <1>; 96 | + status = "okay"; 97 | +}; 98 | + 99 | +&pcie1 { 100 | + pinctrl-names = "default"; 101 | + pinctrl-0 = <&pinctrl_pcie1>; 102 | + reset-gpio = <&gpio3 18 GPIO_ACTIVE_LOW>; 103 | + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 104 | + <&clk IMX8MQ_CLK_PCIE2_AUX>, 105 | + <&clk IMX8MQ_CLK_PCIE2_PHY>, 106 | + <&pcie1_refclk>; 107 | + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 108 | + ext_osc = <1>; 109 | + hard-wired = <1>; 110 | + status = "okay"; 111 | +}; 112 | + 113 | +&ecspi1 { 114 | + pinctrl-names = "default"; 115 | + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 116 | + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>, 117 | + <&gpio3 2 GPIO_ACTIVE_HIGH>; 118 | + num-cs = <2>; 119 | + status = "okay"; 120 | + 121 | + spidev@0 { 122 | + compatible = "rohm,dh2228fv"; 123 | + spi-max-frequency = <20000000>; 124 | + reg = <0>; 125 | + }; 126 | + 127 | + spidev@1 { 128 | + compatible = "rohm,dh2228fv"; 129 | + spi-max-frequency = <20000000>; 130 | + reg = <1>; 131 | + }; 132 | +}; 133 | + 134 | &fec1 { 135 | pinctrl-names = "default"; 136 | pinctrl-0 = <&pinctrl_fec1>; 137 | @@ -333,6 +418,54 @@ &wdog1 { 138 | }; 139 | 140 | &iomuxc { 141 | + pinctrl-names = "default"; 142 | + pinctrl-0 = <&pinctrl_hog>; 143 | + 144 | + pinctrl_hog: hoggrp { 145 | + fsl,pins = < 146 | + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x05 147 | + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 148 | + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 149 | + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 150 | + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 151 | + MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x19 152 | + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 153 | + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 154 | + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 155 | + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x19 156 | + MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 157 | + >; 158 | + }; 159 | + 160 | + pinctrl_pcie0: pcie0grp { 161 | + fsl,pins = < 162 | + MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 163 | + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16 164 | + >; 165 | + }; 166 | + 167 | + pinctrl_pcie1: pcie1grp { 168 | + fsl,pins = < 169 | + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 170 | + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 171 | + >; 172 | + }; 173 | + 174 | + pinctrl_ecspi1: ecspi1grp { 175 | + fsl,pins = < 176 | + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 177 | + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 178 | + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 179 | + >; 180 | + }; 181 | + 182 | + pinctrl_ecspi1_cs: ecspi1_cs_grp { 183 | + fsl,pins = < 184 | + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x82 185 | + MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x82 186 | + >; 187 | + }; 188 | + 189 | pinctrl_fec1: fec1grp { 190 | fsl,pins = < 191 | MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 192 | @@ -366,6 +499,20 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 193 | >; 194 | }; 195 | 196 | + pinctrl_i2c2: i2c2grp { 197 | + fsl,pins = < 198 | + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 199 | + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 200 | + >; 201 | + }; 202 | + 203 | + pinctrl_i2c3: i2c3grp { 204 | + fsl,pins = < 205 | + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f 206 | + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f 207 | + >; 208 | + }; 209 | + 210 | pinctrl_pmic: pmicirqgrp { 211 | fsl,pins = < 212 | MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 213 | @@ -478,4 +625,10 @@ pinctrl_wdog: wdoggrp { 214 | MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 215 | >; 216 | }; 217 | + 218 | + pinctrl_wifi_reset: wifiresetgrp { 219 | + fsl,pins = < 220 | + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 221 | + >; 222 | + }; 223 | }; 224 | -- 225 | 2.39.2 226 | 227 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-imx-5.15/0002-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch: -------------------------------------------------------------------------------- 1 | From aef5837a50af6adc53de4f907647cfd949912dba Mon Sep 17 00:00:00 2001 2 | From: Khem Raj 3 | Date: Tue, 7 Mar 2023 21:13:29 -0800 4 | Subject: [PATCH 2/4] MLK-15307-2 clk: imx8mq: set the parent clocks of PCIE 5 | 6 | Configure the parent clocks of PCIE. 7 | 8 | Signed-off-by: Richard Zhu 9 | Signed-off-by: Khem Raj 10 | --- 11 | drivers/clk/imx/clk-imx8mq.c | 6 ++++++ 12 | 1 file changed, 6 insertions(+) 13 | 14 | diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c 15 | index bf3100eb59ca..3a5ff7109ff1 100644 16 | --- a/drivers/clk/imx/clk-imx8mq.c 17 | +++ b/drivers/clk/imx/clk-imx8mq.c 18 | @@ -646,6 +646,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 19 | /* enable all the clocks just for bringup */ 20 | imx_clk_init_on(np, hws); 21 | 22 | + /* set pcie root's parent clk source */ 23 | + clk_set_parent(hws[IMX8MQ_CLK_PCIE1_CTRL]->clk, hws[IMX8MQ_SYS2_PLL_250M]->clk); 24 | + clk_set_parent(hws[IMX8MQ_CLK_PCIE1_PHY]->clk, hws[IMX8MQ_SYS2_PLL_100M]->clk); 25 | + clk_set_parent(hws[IMX8MQ_CLK_PCIE2_CTRL]->clk, hws[IMX8MQ_SYS2_PLL_250M]->clk); 26 | + clk_set_parent(hws[IMX8MQ_CLK_PCIE2_PHY]->clk, hws[IMX8MQ_SYS2_PLL_100M]->clk); 27 | + 28 | clk_set_parent(hws[IMX8MQ_CLK_CSI1_CORE]->clk, hws[IMX8MQ_SYS1_PLL_266M]->clk); 29 | clk_set_parent(hws[IMX8MQ_CLK_CSI1_PHY_REF]->clk, hws[IMX8MQ_SYS2_PLL_1000M]->clk); 30 | clk_set_parent(hws[IMX8MQ_CLK_CSI1_ESC]->clk, hws[IMX8MQ_SYS1_PLL_800M]->clk); 31 | -- 32 | 2.39.2 33 | 34 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-imx-5.15/0003-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch: -------------------------------------------------------------------------------- 1 | From dd3d8c2c0b77eb742b288cf83e4849f87c8db5c6 Mon Sep 17 00:00:00 2001 2 | From: Khem Raj 3 | Date: Tue, 7 Mar 2023 21:19:36 -0800 4 | Subject: [PATCH 3/4] PCI: imx: Use the external clock as REF_CLK when needed 5 | for i.MX8MQ 6 | 7 | Do not use the external clock when the internal PLL is used as PCIe 8 | REF_CLK. 9 | 10 | Signed-off-by: Ryosuke Saito 11 | Signed-off-by: Khem Raj 12 | --- 13 | drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++-------- 14 | 1 file changed, 7 insertions(+), 8 deletions(-) 15 | 16 | diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c 17 | index 3a8350cad812..841af6f55c7d 100644 18 | --- a/drivers/pci/controller/dwc/pci-imx6.c 19 | +++ b/drivers/pci/controller/dwc/pci-imx6.c 20 | @@ -1569,14 +1569,13 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 21 | break; 22 | case IMX8MQ: 23 | case IMX8MQ_EP: 24 | - /* 25 | - * TODO: Currently this code assumes external 26 | - * oscillator is being used 27 | - */ 28 | - regmap_update_bits(imx6_pcie->iomuxc_gpr, 29 | - imx6_pcie_grp_offset(imx6_pcie), 30 | - IMX8MQ_GPR_PCIE_REF_USE_PAD, 31 | - IMX8MQ_GPR_PCIE_REF_USE_PAD); 32 | + if (imx6_pcie->ext_osc) { 33 | + /* Use the external oscillator as REF clock */ 34 | + regmap_update_bits(imx6_pcie->iomuxc_gpr, 35 | + imx6_pcie_grp_offset(imx6_pcie), 36 | + IMX8MQ_GPR_PCIE_REF_USE_PAD, 37 | + IMX8MQ_GPR_PCIE_REF_USE_PAD); 38 | + } 39 | /* 40 | * Regarding the datasheet, the PCIE_VPH is suggested 41 | * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the 42 | -- 43 | 2.39.2 44 | 45 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-imx-5.15/0004-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch: -------------------------------------------------------------------------------- 1 | From 0845d9b5935ad8b3d450c2dfa62631c9c1df1bea Mon Sep 17 00:00:00 2001 2 | From: Khem Raj 3 | Date: Tue, 7 Mar 2023 21:21:57 -0800 4 | Subject: [PATCH 4/4] PCI: imx: Provide a clock to the device for i.MX8MQ 5 | 6 | When the internal PLL is configured as PCIe REF_CLK, we also have to 7 | output a clock via CLK2_P/N pin to the connector/device to provide it. 8 | Configure 100 MHz clock as its output. 9 | 10 | Signed-off-by: Ryosuke Saito 11 | Signed-off-by: Khem Raj 12 | --- 13 | drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++ 14 | 1 file changed, 35 insertions(+) 15 | 16 | diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c 17 | index 841af6f55c7d..ac36c7035460 100644 18 | --- a/drivers/pci/controller/dwc/pci-imx6.c 19 | +++ b/drivers/pci/controller/dwc/pci-imx6.c 20 | @@ -275,6 +275,12 @@ struct imx6_pcie { 21 | #define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) 22 | #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) 23 | 24 | +#define IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG 0x74 25 | +#define IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK GENMASK(3, 0) 26 | +#define IMX8MQ_ANA_PLLOUT_MONITOR_CKE BIT(4) 27 | +#define IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG 0x7C 28 | +#define IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK GENMASK(2, 0) 29 | + 30 | static int imx6_pcie_cz_enabled; 31 | static void imx6_pcie_ltssm_disable(struct device *dev); 32 | 33 | @@ -1575,6 +1581,35 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 34 | imx6_pcie_grp_offset(imx6_pcie), 35 | IMX8MQ_GPR_PCIE_REF_USE_PAD, 36 | IMX8MQ_GPR_PCIE_REF_USE_PAD); 37 | + } else { 38 | + /* 39 | + * Use the internal PLL as REF clock and also 40 | + * provide a clock to the device. 41 | + */ 42 | + struct regmap *anatop = 43 | + syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop"); 44 | + 45 | + if (IS_ERR(anatop)) { 46 | + dev_err(imx6_pcie->pci->dev, 47 | + "Couldn't configure the internal PLL as REF clock\n"); 48 | + break; 49 | + } 50 | + 51 | + /* Select SYSTEM_PLL1_CLK as the clock source */ 52 | + regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, 53 | + IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK, 0xb); 54 | + 55 | + /* 56 | + * SYSTEM_PLL1_CLK is 800 MHz, so divided by 8 57 | + * for generating 100 MHz as output. 58 | + */ 59 | + regmap_update_bits(anatop, IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG, 60 | + IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK, 0x7); 61 | + 62 | + /* Enable CLK2_P/N clock to provide it to the device */ 63 | + regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, 64 | + IMX8MQ_ANA_PLLOUT_MONITOR_CKE, 65 | + IMX8MQ_ANA_PLLOUT_MONITOR_CKE); 66 | } 67 | /* 68 | * Regarding the datasheet, the PCIE_VPH is suggested 69 | -- 70 | 2.39.2 71 | 72 | -------------------------------------------------------------------------------- /recipes-kernel/linux/linux-imx_%.bbappend: -------------------------------------------------------------------------------- 1 | FILESEXTRAPATHS:prepend := "${THISDIR}/files:" 2 | 3 | FILESPATH =. "${FILE_DIRNAME}/${BPN}-5.15:" 4 | 5 | SRC_URI:append:coral-dev = "\ 6 | file://0001-imx8mq-phanbell.dts-Enable-Coral-specifics-e.g.-PCIE.patch \ 7 | file://0002-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch \ 8 | file://0003-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch \ 9 | file://0004-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch \ 10 | file://extra.cfg \ 11 | file://wifi.cfg \ 12 | " 13 | -------------------------------------------------------------------------------- /recipes-security/optee-imx/optee-os_%.bbappend: -------------------------------------------------------------------------------- 1 | PLATFORM_FLAVOR:coral-dev = "mx8mqevk" 2 | -------------------------------------------------------------------------------- /recipes-support/common/edgetpu-common.inc: -------------------------------------------------------------------------------- 1 | HOMEPAGE = "https://coral.googlesource.com/edgetpu" 2 | SRC_URI = "git://coral.googlesource.com/edgetpu;protocol=https;branch=release-chef" 3 | SRCREV = "5df7f62a2d88dc0d9e98c8c794717d77b62daa89" 4 | -------------------------------------------------------------------------------- /recipes-support/python/python3-edgetpu.bb: -------------------------------------------------------------------------------- 1 | SUMMARY = "Edge TPU Python API" 2 | LICENSE = "Apache-2.0" 3 | LIC_FILES_CHKSUM = "file://LICENSE;md5=19d1f00e43228427ebb9a48f2e175959" 4 | 5 | require recipes-support/common/edgetpu-common.inc 6 | 7 | S = "${WORKDIR}/git" 8 | 9 | PV = "release-chef" 10 | 11 | RDEPENDS:${PN} = "libedgetpu python3 python3-numpy python3-pillow" 12 | RDEPENDS:${PN}-examples = "bash ${PN}" 13 | 14 | inherit setuptools3 15 | 16 | PACKAGES += "${PN}-examples" 17 | 18 | do_install:append:x86_64() { 19 | rm ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/*arm-linux-gnueabihf* 20 | rm ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/*aarch64* 21 | mv ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/_edgetpu_cpp_wrapper.cpython-*-x86_64-linux-gnu.so \ 22 | ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/_edgetpu_cpp_wrapper.so 23 | } 24 | 25 | do_install:append:arm() { 26 | rm ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/*x86_64* 27 | rm ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/*aarch64* 28 | mv ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/_edgetpu_cpp_wrapper.cpython-*-arm-linux-gnueabihf.so \ 29 | ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/_edgetpu_cpp_wrapper.so 30 | } 31 | 32 | do_install:append:aarch64() { 33 | rm ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/*x86_64* 34 | rm ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/*arm-linux-gnueabihf* 35 | mv ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/_edgetpu_cpp_wrapper.cpython-*-aarch64-linux-gnu.so \ 36 | ${D}${PYTHON_SITEPACKAGES_DIR}/edgetpu/swig/_edgetpu_cpp_wrapper.so 37 | } 38 | 39 | do_install:append() { 40 | install -d ${D}/${datadir}/edgetpu/examples/ 41 | install -d ${D}/${datadir}/edgetpu/examples/models 42 | install -d ${D}/${datadir}/edgetpu/examples/images 43 | 44 | cp -R --no-dereference --preserve=mode,links -v ${S}/test_data/*.jpg \ 45 | ${D}/${datadir}/edgetpu/examples/images 46 | 47 | cp -R --no-dereference --preserve=mode,links -v ${S}/test_data/*.tflite \ 48 | ${D}/${datadir}/edgetpu/examples/models 49 | 50 | cp -R --no-dereference --preserve=mode,links -v ${S}/test_data/*.txt \ 51 | ${D}/${datadir}/edgetpu/examples/models 52 | 53 | cp -R --no-dereference --preserve=mode,links -v ${S}/edgetpu/demo/* ${D}/${datadir}/edgetpu/examples/ 54 | } 55 | 56 | FILES:${PN}-examples = "${datadir}/edgetpu/examples/" 57 | 58 | BBCLASSEXTEND = "native nativesdk" 59 | 60 | INSANE_SKIP:${PN} += "already-stripped" 61 | -------------------------------------------------------------------------------- /wic/coral-bootpart.wks.in: -------------------------------------------------------------------------------- 1 | # short-description: Create SD card image with a boot partition 2 | # long-description: 3 | # Create an image that can be written onto a SD card using dd for use 4 | # with i.MX SoC family 5 | # It uses u-boot + other binaries gathered together on imx-boot file 6 | # 7 | # The disk layout used is: 8 | # - ---------- -------------- -------------- 9 | # | | imx-boot | boot | rootfs | 10 | # - ---------- -------------- -------------- 11 | # ^ ^ ^ ^ ^ 12 | # | | | | | 13 | # 0 | 8MiB 72MiB 72MiB + rootfs + IMAGE_EXTRA_SPACE (default 10MiB) 14 | # ${IMX_BOOT_SEEK} 32 or 33kiB, see reference manual 15 | # 16 | part u-boot --source rawcopy --sourceparams="file=imx-boot" --ondisk mmcblk --no-table --align ${IMX_BOOT_SEEK} 17 | part /boot --source bootimg-partition --ondisk mmcblk --fstype=ext4 --label boot --active --align 8192 --size 64 18 | part / --source rootfs --ondisk mmcblk --fstype=ext4 --label root --align 8192 --uuid=70672ec3-5eee-49ff-b3b1-eb1fbd406bf5 19 | 20 | bootloader --ptable gpt 21 | --------------------------------------------------------------------------------