├── .editorconfig
├── .gitignore
├── LICENSE
├── README.md
├── docs
└── Build.md
├── generate.py
├── requirements.txt
├── src
├── 6502
│ ├── cpu_6502.txt
│ ├── cpu_6502rorbug.txt
│ ├── cpu_65c02.txt
│ ├── cpu_65c02s.txt
│ ├── cpu_65c816.txt
│ ├── cpu_65ce02.txt
│ ├── cpu_65dtv02.txt
│ ├── cpu_r65c02.txt
│ ├── csg.svg
│ ├── index.html
│ ├── mos.svg
│ ├── out.sh
│ ├── rockwell.svg
│ ├── script.js
│ └── wdc.svg
├── c64disasm
│ ├── c64disasm_cbm.txt
│ ├── c64disasm_de.txt
│ ├── c64disasm_en.txt
│ ├── c64disasm_mm.txt
│ ├── c64disasm_mn.txt
│ ├── c64disasm_ms.txt
│ ├── c64disasm_sc.txt
│ ├── generate.py
│ └── out.sh
├── c64io
│ ├── c64io_mapc64.txt
│ ├── c64io_prg.txt
│ ├── generate.py
│ └── out.sh
├── c64mem
│ ├── c64mem_64er.txt
│ ├── c64mem_64intern.txt
│ ├── c64mem_64map.txt
│ ├── c64mem_jb.txt
│ ├── c64mem_mapc64.txt
│ ├── c64mem_prg.txt
│ ├── c64mem_src.txt
│ ├── c64mem_sta.txt
│ ├── format.py
│ ├── generate.py
│ ├── out.sh
│ ├── symbols.txt
│ └── texteinschub.md
├── charset
│ ├── .gitignore
│ ├── C64IALT.TXT
│ ├── C64IPRI.TXT
│ ├── all_charsets
│ │ ├── sjgray
│ │ │ ├── 324242-01-german.bin
│ │ │ ├── 901439-08.bin
│ │ │ ├── 901447-08.bin
│ │ │ ├── 901447-10.bin
│ │ │ ├── 901447-12-japan.bin
│ │ │ ├── 901447-14-swedish.bin
│ │ │ ├── 901640-01.bin
│ │ │ ├── cbm-french.bin
│ │ │ ├── cbm-greek.bin
│ │ │ ├── cbm-hungarian.bin
│ │ │ ├── cbm-norwegian.bin
│ │ │ ├── cbm-russian.bin
│ │ │ └── cbm-unknown-8096.bin
│ │ └── zimmers
│ │ │ ├── c128
│ │ │ ├── characters.390059-01.bin
│ │ │ ├── characters.danish-d.325175-02.bin
│ │ │ ├── characters.danish.325175-01.bin
│ │ │ ├── characters.french.325167-01.bin
│ │ │ ├── characters.german.315079-01.bin
│ │ │ ├── characters.ifb.325167-02.bin
│ │ │ ├── characters.norwegian.325078-02.bin
│ │ │ ├── characters.norwegian.325178-01..bin
│ │ │ ├── characters.spanish.325171-01.bin
│ │ │ ├── characters.swedish.325181-01.bin
│ │ │ └── characters.swiss.325173-01D.bin
│ │ │ ├── c64
│ │ │ ├── characters.325018-02.C2G007.bin
│ │ │ ├── characters.325018-02.bin
│ │ │ ├── characters.325056-03.bin
│ │ │ ├── characters.901225-01-DK.bin
│ │ │ ├── characters.901225-01.bin
│ │ │ ├── characters.906143-02.bin
│ │ │ └── characters.turkish.bin
│ │ │ ├── char
│ │ │ ├── c128.bin
│ │ │ ├── c16-hungarian.bin
│ │ │ ├── c16.bin
│ │ │ ├── c64-swedish.bin
│ │ │ ├── c64-swedish2.bin
│ │ │ ├── c64-swedish3.bin
│ │ │ ├── c64-swedish4.bin
│ │ │ ├── c64.bin
│ │ │ ├── c65-caff.bin
│ │ │ ├── pet-1.bin
│ │ │ ├── pet-2.bin
│ │ │ ├── pet-greek.bin
│ │ │ ├── pet-norwegian.bin
│ │ │ ├── pet-russian.bin
│ │ │ ├── pet-swedish.bin
│ │ │ ├── superpet-swedish.bin
│ │ │ ├── superpet.bin
│ │ │ ├── vic20-german.bin
│ │ │ ├── vic20-japanese.bin
│ │ │ ├── vic20-norwegian.bin
│ │ │ ├── vic20-swedish.bin
│ │ │ └── vic20.bin
│ │ │ ├── lcd
│ │ │ └── lcd-char-rom-u16.bin
│ │ │ ├── pet
│ │ │ ├── 324242-10_chargen_din_uc5_8296.rom
│ │ │ ├── characters-1.901447-08.bin
│ │ │ ├── characters-2.901447-10.bin
│ │ │ ├── characters-901447-german8296d.bin
│ │ │ ├── characters-french.bin
│ │ │ ├── characters-german.bin
│ │ │ ├── characters-german2.bin
│ │ │ ├── characters-japan.901447-12.bin
│ │ │ ├── characters-norwegian.bin
│ │ │ ├── characters-swedish.901447-14.bin
│ │ │ ├── characters.901640-01.bin
│ │ │ └── characters.swedish.bin
│ │ │ └── vic-20
│ │ │ ├── characters.901460-02.bin
│ │ │ ├── characters.901460-03.bin
│ │ │ ├── characters.DK_901460-03.bin
│ │ │ └── characters.NecP22101-207.bin
│ ├── bin
│ │ ├── c128_danish_lower.bin
│ │ ├── c128_danish_upper.bin
│ │ ├── c128_french_lower.bin
│ │ ├── c128_french_lower_alt.bin
│ │ ├── c128_french_upper.bin
│ │ ├── c128_french_upper_alt.bin
│ │ ├── c128_german_lower.bin
│ │ ├── c128_german_upper.bin
│ │ ├── c128_norwegian_lower.bin
│ │ ├── c128_norwegian_lower_alt.bin
│ │ ├── c128_norwegian_upper.bin
│ │ ├── c128_norwegian_upper_alt-bugs.bin
│ │ ├── c128_norwegian_upper_alt.bin
│ │ ├── c128_norwegian_upper_bugs.bin
│ │ ├── c128_spanish_lower.bin
│ │ ├── c128_spanish_lower_alt.bin
│ │ ├── c128_spanish_upper.bin
│ │ ├── c128_spanish_upper_alt.bin
│ │ ├── c128_swiss_lower.bin
│ │ ├── c128_swiss_lower_alt.bin
│ │ ├── c128_swiss_upper.bin
│ │ ├── c128_swiss_upper_alt.bin
│ │ ├── c128_us_lower.bin
│ │ ├── c64_danish_lower.bin
│ │ ├── c64_danish_lower_alt.bin
│ │ ├── c64_danish_upper.bin
│ │ ├── c64_danish_upper_alt.bin
│ │ ├── c64_japanese_upper-kanji.bin
│ │ ├── c64_japanese_upper.bin
│ │ ├── c64_spanish_lower.bin
│ │ ├── c64_spanish_upper.bin
│ │ ├── c64_swedish_lower.bin
│ │ ├── c64_swedish_lower_2.bin
│ │ ├── c64_swedish_lower_2alt.bin
│ │ ├── c64_swedish_lower_alt.bin
│ │ ├── c64_swedish_upper.bin
│ │ ├── c64_swedish_upper_alt.bin
│ │ ├── c64_swedish_upper_alt2.bin
│ │ ├── c64_swedish_upper_bugs.bin
│ │ ├── c64_turkish_lower.bin
│ │ ├── c64_turkish_upper.bin
│ │ ├── c64_us_lower.bin
│ │ ├── c64_us_lower_alt.bin
│ │ ├── c64_us_lower_buggy1.bin
│ │ ├── c64_us_upper.bin
│ │ ├── c64_us_upper_alt.bin
│ │ ├── c64_us_upper_buggy1.bin
│ │ ├── c64_us_upper_buggy2.bin
│ │ ├── lcd_us_lower.bin
│ │ ├── lcd_us_upper.bin
│ │ ├── pet_french_lower.bin
│ │ ├── pet_french_upper.bin
│ │ ├── pet_german_lower.bin
│ │ ├── pet_german_lower_alt.bin
│ │ ├── pet_german_lower_alt2.bin
│ │ ├── pet_german_upper.bin
│ │ ├── pet_greek_lower.bin
│ │ ├── pet_greek_upper.bin
│ │ ├── pet_hungarian_lower.bin
│ │ ├── pet_hungarian_upper.bin
│ │ ├── pet_japanese_upper.bin
│ │ ├── pet_japanese_upper_bug.bin
│ │ ├── pet_norwegian_lower.bin
│ │ ├── pet_norwegian_upper.bin
│ │ ├── pet_russian_upper.bin
│ │ ├── pet_swedish_lower.bin
│ │ ├── pet_swedish_upper.bin
│ │ ├── pet_us_lower.bin
│ │ ├── pet_us_lower_swapped.bin
│ │ ├── pet_us_upper.bin
│ │ ├── superpet_swedish_ascii.bin
│ │ ├── superpet_us_apl.bin
│ │ ├── superpet_us_ascii.bin
│ │ ├── ted_hungarian_lower.bin
│ │ ├── ted_hungarian_upper.bin
│ │ ├── ted_us_lower.bin
│ │ ├── vic-20_danish_lower.bin
│ │ ├── vic-20_danish_upper.bin
│ │ ├── vic-20_japanese_upper-kanji.bin
│ │ ├── vic-20_swedish_lower_alt.bin
│ │ ├── vic-20_us_lower.bin
│ │ └── vic-20_us_upper.bin
│ ├── bin16
│ │ ├── characters.324867-02.bin
│ │ ├── characters.901232-01.bin
│ │ ├── characters.901232-02.bin
│ │ └── characters.901233-03.swedish.bin
│ ├── bin16f
│ │ ├── characters-hungarian.bin
│ │ └── characters.901237-01.bin
│ ├── chargen
│ ├── charset.js
│ ├── charset2png.py
│ ├── compare.py
│ ├── control_codes_c128.txt
│ ├── control_codes_c64.txt
│ ├── control_codes_c65.txt
│ ├── control_codes_cbm2.txt
│ ├── control_codes_pet-b.txt
│ ├── control_codes_pet-n.txt
│ ├── control_codes_ted.txt
│ ├── control_codes_vic-20.txt
│ ├── generate.py
│ ├── keyboard_c128.txt
│ ├── keyboard_c64.txt
│ ├── keyboard_c65.txt
│ ├── keyboard_cbm2.txt
│ ├── keyboard_pet-b.txt
│ ├── keyboard_pet-n.txt
│ ├── keyboard_ted.txt
│ ├── keyboard_vic-20.txt
│ ├── out.sh
│ ├── palette_c128.txt
│ ├── palette_c64.txt
│ ├── palette_c65.txt
│ ├── palette_cbm2.txt
│ ├── palette_pet-b.txt
│ ├── palette_pet-n.txt
│ ├── palette_ted.txt
│ ├── palette_vic-20.txt
│ ├── script.js
│ └── style.css
├── colors
│ ├── colors.css
│ ├── index.html
│ ├── out.sh
│ └── script.js
├── commentaries.css
├── commentaries.js
├── kernal
│ ├── generate.py
│ ├── kernal_128intern.txt
│ ├── kernal_64intern.txt
│ ├── kernal_ct.txt
│ ├── kernal_dh.txt
│ ├── kernal_fk.txt
│ ├── kernal_ld.txt
│ ├── kernal_mapc64.txt
│ ├── kernal_mlr.txt
│ ├── kernal_pm.txt
│ ├── kernal_prg.txt
│ ├── kernal_sta.txt
│ └── out.sh
└── style.css
└── validate_html.sh
/.editorconfig:
--------------------------------------------------------------------------------
1 | root = true
2 |
3 | [*]
4 | insert_final_newline = true
5 | end_of_line = lf
6 |
7 | [*.{md}]
8 | indent_style = space
9 | indent_size = 4
10 | charset = utf-8
11 |
--------------------------------------------------------------------------------
/.gitignore:
--------------------------------------------------------------------------------
1 | /out/
2 | .venv
3 |
--------------------------------------------------------------------------------
/LICENSE:
--------------------------------------------------------------------------------
1 | BSD 2-Clause License
2 |
3 | Copyright (c) 2022, Michael Steil
4 | All rights reserved.
5 |
6 | Redistribution and use in source and binary forms, with or without
7 | modification, are permitted provided that the following conditions are met:
8 |
9 | 1. Redistributions of source code must retain the above copyright notice, this
10 | list of conditions and the following disclaimer.
11 |
12 | 2. Redistributions in binary form must reproduce the above copyright notice,
13 | this list of conditions and the following disclaimer in the documentation
14 | and/or other materials provided with the distribution.
15 |
16 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
20 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 | # Ultimate Commodore
64 Reference Guide
5 |
6 | An effort to collect `C64` reference material
7 | in machine readable form and maintain
8 | scripts to present this material to the web.
9 |
10 |
11 |
12 |
13 | [![Button Website]][Website]
14 | [![Button Building]][Building]
15 |
16 |
17 |
18 |
19 | ## Material
20 |
21 | *Reference material collected in this repository.*
22 |
23 |
24 |
25 | ### ROM Disassembly
26 |
27 |
28 |
29 | | KERNAL | BASIC | Lang | By / From |
30 | |:------:|:-----:|:----:|:---------:|
31 | | ◯ | [⬤][Disassembly BASIC] | :us: | **Microsoft**
32 | | [⬤][Disassembly KERNAL] | ◯ | :us: | **Commodore**
33 | | [⬤][Disassembly Lee] | [⬤][Disassembly Lee] | :us: | `Lee Davison`
34 | | ◯ | [⬤][Disassembly Bob] | :us: | `Bob Sander-Cederlof`
35 | | [⬤][Disassembly Buch] | [⬤][Disassembly Buch] | :de: | **Commodore-64-intern-Buch**
36 | | [⬤][Disassembly Magnus] | ◯ | :us: | `Magnus Nyman`
37 | | [⬤][Disassembly Marko] | [⬤][Disassembly Marko] | :us: | `Marko Mäkelä`
38 |
39 |
40 |
41 | ### Memory Map
42 |
43 |
44 |
45 | | Title | Lang | By / From |
46 | |:-----:|:----:|:---------:|
47 | | [`Mapping the Commodore 64`][Memory Sheldon] | :us: | `Sheldon Leemon`
48 | | [`Memory Map mit Wandervorschlägen`][Memory Hauck] | :de: | `Dr. H. Hauck`
49 | | [`Commodore-64-intern-Buch`][Memory Buch] | :de: | **Commodore**
50 | | [`Reference`][Memory Joe] | :us: | `Joe Forster / STA`
51 | | [`Comments in the original source`][Memory Original] | :us: | **Microsoft** / **Commodore** |
52 | | [`C64 Programmer's Reference Guide`][Memory Guide] | :us: |
53 | | [`64map`][Memory Map] | :us: |
54 | | [`Reference`][Memory Jim] | :us: | `Jim Butterfield`
55 |
56 |
57 |
58 | ### KERNAL API
59 |
60 |
61 |
62 | | Title | Lang | By / From |
63 | |:-----:|:----:|:---------:|
64 | | [`Commodore 64 Programmer's Reference Guide`][API Guide] | :us: | **Commodore**
65 | | [`COMPUTE!'s VIC-20 and Commodore 64 Tool Kit: Kernal`][API Dan] | :us: | `Dan Heeb`
66 | | [`Machine Language Routines for the Commodore 64 and 128`][API Todd] | :us: | `Todd D Heimarck`
`Patrick Parrish`
67 | | [`Mapping the Commodore 64`][API Sheldon] | :us: | `Sheldon Leemon`
68 | | [`Commodore 128 intern`][API 128] | :us: | `Jörg Schieb`
`Frank Thrun`
`Heinz Wrobel`
69 | | [`The almost completely commented C64 ROM disassembly`][API Lee] | :us: | `Lee Davison`
70 | | [`Cracking The Kernal`][API Peter] | :us: | `Peter Marcotty`
71 | | [`Kernal 64 / 128`][API Craig] | :us: | `Craig Taylor`
72 | | [`Commodore 64 standard KERNAL functions`][API Joe] | :us: | `Joe Forster / STA`
73 | | [`C64 KERNAL jump table`][API Frank] | :us: | `Frank Kontros`
74 | | [`Das neue Commodore-64-intern-Buch`][API Sheldon] | :de: | `Baloui`
`Brückmann`
`Englisch`
`Felt`
`Gelfand`
`Gerits`
`Krsnik`
75 |
76 |
77 |
78 |
79 | ## Contributions
80 |
81 | `Extensions` , `Translations` , `Corrections`
82 | of typos and content, .. **are welcome!**
83 |
84 |
85 |
86 |
87 | ## Credits
88 |
89 | The original effort of ***collecting***, ***converting***, ***formatting***
90 | and ***editing*** the collected files was done by **[Michael Steil]**.
91 |
92 |
93 |
94 |
95 |
96 |
97 |
98 |
99 | [Website]: http://pagetable.com/c64ref
100 |
101 | [Building]: docs/Build.md
102 |
103 | [Michael Steil]: mailto:mist64@mac.com
104 |
105 | [Disassembly KERNAL]: src/c64disasm/c64disasm_cbm.txt
106 | [Disassembly Magnus]: src/c64disasm/c64disasm_mn.txt
107 | [Disassembly BASIC]: src/c64disasm/c64disasm_ms.txt
108 | [Disassembly Marko]: src/c64disasm/c64disasm_mm.txt
109 | [Disassembly Buch]: src/c64disasm/c64disasm_de.txt
110 | [Disassembly Bob]: src/c64disasm/c64disasm_sc.txt
111 | [Disassembly Lee]: src/c64disasm/c64disasm_en.txt
112 |
113 | [Memory Original]: src/c64mem/c64mem_src.txt
114 | [Memory Sheldon]: src/c64mem/c64mem_mapc64.txt
115 | [Memory Hauck]: src/c64mem/c64mem_64er.txt
116 | [Memory Guide]: src/c64mem/c64mem_prg.txt
117 | [Memory Buch]: src/c64mem/c64mem_64intern.txt
118 | [Memory Joe]: src/c64mem/c64mem_sta.txt
119 | [Memory Map]: src/c64mem/c64mem_64map.txt
120 | [Memory Jim]: src/c64mem/c64mem_jb.txt
121 |
122 | [API Sheldon]: src/kernal/kernal_mapc64.txt
123 | [API Guide]: src/kernal/kernal_prg.txt
124 | [API Frank]: src/kernal/kernal_fk.txt
125 | [API Peter]: src/kernal/kernal_pm.txt
126 | [API Craig]: src/kernal/kernal_ct.txt
127 | [API Buch]: src/kernal/kernal_64intern.txt
128 | [API Todd]: src/kernal/kernal_mlr.txt
129 | [API 128]: src/kernal/kernal_128intern.txt
130 | [API Dan]: src/kernal/kernal_dh.txt
131 | [API Lee]: src/kernal/kernal_ld.txt
132 | [API Joe]: src/kernal/kernal_sta.txt
133 |
134 |
135 |
136 |
137 | [Button Building]: https://img.shields.io/badge/Building-5A6AB1?style=for-the-badge&logoColor=white&logo=GitBook
138 | [Button Website]: https://img.shields.io/badge/Website-6BA539?style=for-the-badge&logoColor=white&logo=OpenStreetMap
139 |
--------------------------------------------------------------------------------
/docs/Build.md:
--------------------------------------------------------------------------------
1 |
2 | # Building
3 |
4 | *How to build this project locally*
5 |
6 |
7 | ## Generating
8 |
9 | **Requirements:**
10 |
11 | - [Python]
12 | - [Markdown]
13 |
14 | See also [requirements.txt].
15 |
16 | The Python packages are installed into a virtual environment like this:
17 |
18 | ```sh
19 | python3 -m venv .venv # create a virtual environment
20 | source .venv/bin/activate # activate it
21 | python3 -m pip install -r requirements.txt # install the required packages
22 | ```
23 |
24 | To generate the `html` files, simply execute [`generate.py`][Generate]
25 |
26 | This will build the different pages from the repos *reference material* with the help of `shell` and `python` scripts.
27 |
28 | `./generate --wip` builds everything including `colors` and `c64io`.
29 |
30 | `./generate.py --only 6502 colors c64mem` only builds the selected categories (using the category path names as keys).
31 |
32 |
33 | The `6502` and the `color` reference are all Java Script and do not need to be generated while developing, but for release the umbrella `generate.py` adds navigation, matching titles and a link to the github project.
34 |
35 |
36 | ## Testing
37 |
38 | For testing start Python's built-in webserver and navigate to the local url:
39 | ```sh
40 | python3 -m http.server
41 | ```
42 | [`http://localhost:8000/c64ref/6502/`][Localhost8000]
43 |
44 |
45 | If the default port is already taken, choose your own port (eg. 6464):
46 |
47 | ```sh
48 | python3 -m http.server 6464
49 | ```
50 | [`http://localhost:6464/c64ref/6502/`][Localhost6464]
51 |
52 |
53 | Navigate using the menu bar or by directly going to the specific pages:
54 |
55 | * `6502` for _6502 Family CPU Reference_
56 | * `c64disasm` for _C64 BASIC & KERNAL ROM Disassembly_ (**Slow**)
57 | * `c64io` for _C64 I/O Map_ (**WIP**)
58 | * `c64mem` for _C64 Memory Map_
59 | * `charset` for _Character Set · PETSCII · Keyboard_
60 | * `colors` for _C64 Colors_ (**WIP**)
61 | * `kernal` for _C64 KERNAL API_
62 |
63 |
64 | ## Upload
65 |
66 | For uploading use
67 |
68 | ```
69 | ./generate upload
70 | ```
71 |
72 | It checks for changes in the working copy and won't let you build if there are any.
73 |
74 | ---
75 |
76 |
77 |
78 |
79 | [Generate]: ../generate.py
80 | [requirements.txt]: ../requirements.txt
81 |
82 | [Markdown]: https://pypi.org/project/Markdown/
83 | [Python]: https://www.python.org/
84 |
85 | [Localhost8000]: http://localhost:8000/c64ref/6502/
86 | [Localhost6464]: http://localhost:6464/c64ref/6502/
87 |
--------------------------------------------------------------------------------
/requirements.txt:
--------------------------------------------------------------------------------
1 | Markdown==3.6
2 |
--------------------------------------------------------------------------------
/src/6502/cpu_6502rorbug.txt:
--------------------------------------------------------------------------------
1 | ## This is a description file for a 6502-like CPU.
2 | ## See https://github.com/mist64/c64ref for details.
3 |
4 | [info]
5 | manufacturer MOS
6 | name 6502
7 | revision without ROR
8 | year 1975
9 | id 6502rorbug
10 | basedon 6502
11 | description This is the pre June 1976 version of the original implementation of the 6502 designed by MOS Technology, Inc. This version does not have the ROR instruction; the respective opcodes behave differently due to a bug in the mask.
12 |
13 | [operations]
14 | ASL0 shift N-----Z- /M7...M0/ ← 0
15 |
16 | [opcodes]
17 | 66 *ASL0 a8
18 | 6A *ASL0 A
19 | 6E *ASL0 a16
20 | 76 *ASL0 a8,X
21 | 7E *ASL0 a16,X
22 |
23 | [documentation-mnemos]
24 | ASL0 Arithmetic Shift Left Without Updating Carry
25 | This instruction shifts either the accumulator or the address memory location 1 bit to the left, with the bit 0 always being set to 0. ASL0 either shifts the accumulator left 1 bit or is a read/modify/write instruction that affects only memory.
26 | The instruction does not affect the overflow bit, sets N equal to the result bit 7 (bit 6 in the input), sets Z flag if the result is equal to 0, otherwise resets Z.
27 |
28 | [documentation-mnemos~private]
29 | ASL0 These are the buggy opcodes that were supposed to do a ROR.
30 |
31 | ## TODO should inherit from [documentation-mnemos~private] and [documentation-addmodes~private]
32 |
--------------------------------------------------------------------------------
/src/6502/cpu_65c02.txt:
--------------------------------------------------------------------------------
1 | ## This is a description file for a 6502-like CPU.
2 | ## See https://github.com/mist64/c64ref for details.
3 |
4 | [info]
5 | manufacturer WDC
6 | name 65C02
7 | year 1983 ## https://en.wikipedia.org/wiki/WDC_65C02; or 1981? https://en.wikipedia.org/wiki/Talk%3AWDC_65C02
8 | id 65c02
9 | basedon 6502
10 | description This is the CMOS-based reimplementation of the 6502 designed by Western Design Center, Inc. It supports all documented features of the original 6502, fixes all known quirks, adds 27 new opcodes and two addressing modes, and guarantees all undocumented opcodes to be NOPs. To distinguish it from derived versions, it is also sometimes called the 65SC02.
11 |
12 | [mnemos]
13 | BRA Branch Always
14 | PHX Push X Register
15 | PHY Push Y Register
16 | PLX Pull X Register
17 | PLY Pull Y Register
18 | STZ Store Zero
19 | TRB Test and Reset Memory Bits
20 | TSB Test and Set Memory Bits
21 |
22 | [operations]
23 | BRA ctrl -------- Branch Always
24 | PHX stack -------- X↓
25 | PHY stack -------- Y↑
26 | PLX stack N-----Z- X↑
27 | PLY stack N-----Z- Y↑
28 | STZ load -------- 0 → M
29 | TRB logic ------Z- ~A ∧ M → M
30 | TSB logic ------Z- A ∨ M → M
31 |
32 | [addmodes]
33 | (a8) 2 ($nn) Zero Page Indirect
34 | (a16,X) 3 ($nnnn,X) Absolute X-Indexed Indirect
35 |
36 | [opcodes]
37 | 04 TSB a8
38 | 0C TSB a16
39 | 12 ORA (a8)
40 | 14 TRB a8
41 | 1A INC A
42 | 1C TRB a16
43 | 32 AND (a8)
44 | 34 BIT a8,X
45 | 3A DEC A
46 | 3C BIT a16,X
47 | 52 EOR (a8)
48 | 5A PHY
49 | 64 STZ a8
50 | 72 ADC (a8)
51 | 74 STZ a8,X
52 | 7A PLY
53 | 7C JMP (a16,X)
54 | 80 BRA r8
55 | 89 BIT #d8
56 | 92 STA (a8)
57 | 9C STZ a16
58 | 9E STZ a16,X
59 | B2 LDA (a8)
60 | D2 CMP (a8)
61 | DA PHX
62 | F2 SBC (a8)
63 | FA PLX
64 |
65 | 02 *NOP #d8
66 | 03 *NOP
67 | 07 *NOP
68 | 0B *NOP
69 | 0F *NOP
70 | 13 *NOP
71 | 17 *NOP
72 | 1B *NOP
73 | 1F *NOP
74 | 22 *NOP #d8
75 | 23 *NOP
76 | 27 *NOP
77 | 2B *NOP
78 | 2F *NOP
79 | 33 *NOP
80 | 37 *NOP
81 | 3B *NOP
82 | 3F *NOP
83 | 42 *NOP #d8
84 | 43 *NOP
85 | 44 *NOP #d8
86 | 47 *NOP
87 | 4B *NOP
88 | 4F *NOP
89 | 53 *NOP
90 | 54 *NOP #d8
91 | 57 *NOP
92 | 5B *NOP
93 | 5C *NOP
94 | 5F *NOP
95 | 62 *NOP #d8
96 | 63 *NOP
97 | 67 *NOP
98 | 6B *NOP
99 | 6F *NOP
100 | 73 *NOP
101 | 77 *NOP
102 | 7B *NOP
103 | 7F *NOP
104 | 82 *NOP #d8
105 | 83 *NOP
106 | 87 *NOP
107 | 8B *NOP
108 | 8F *NOP
109 | 93 *NOP
110 | 97 *NOP
111 | 9B *NOP
112 | 9F *NOP
113 | A3 *NOP
114 | A7 *NOP
115 | AB *NOP
116 | AF *NOP
117 | B3 *NOP
118 | B7 *NOP
119 | BB *NOP
120 | BF *NOP
121 | C2 *NOP #d8
122 | C3 *NOP
123 | C7 *NOP
124 | CB *NOP
125 | CF *NOP
126 | D3 *NOP
127 | D4 *NOP #d8
128 | D7 *NOP
129 | DB *NOP
130 | DC *NOP
131 | DF *NOP
132 | E2 *NOP #d8
133 | E3 *NOP
134 | E7 *NOP
135 | EB *NOP
136 | EF *NOP
137 | F3 *NOP
138 | F4 *NOP #d8
139 | F7 *NOP
140 | FB *NOP
141 | FC *NOP
142 | FF *NOP
143 |
144 | [timing]
145 | ## updated timing
146 | 6c 6 ## JMP () fixed, one cycle extra
147 |
148 | ## ADC instructions add 1 cycle in decimal mode
149 | 61 6+d
150 | 65 3+d
151 | 69 2+d
152 | 6D 4+d
153 | 71 5+p+d
154 | 75 4+d
155 | 79 4+p+d
156 | 7D 4+p+d
157 |
158 | ## SBC instructions add 1 cycle in decimal mode
159 | E1 6+d
160 | E5 3+d
161 | E9 2+d
162 | ED 4+d
163 | F1 5+p+d
164 | F5 4+d
165 | F9 4+p+d
166 | FD 4+p+d
167 |
168 | ## new instructions
169 | 04 5
170 | 0C 6
171 | 12 5
172 | 14 5
173 | 1A 2
174 | 1C 6
175 | 32 5
176 | 34 3
177 | 3A 2
178 | 3C 4
179 | 52 5
180 | 5A 3
181 | 64 3
182 | 72 5+d
183 | 74 4
184 | 7A 4
185 | 7C 6
186 | 80 3+p
187 | 89 3
188 | 92 5
189 | 9C 4
190 | 9E 5
191 | B2 5
192 | D2 5
193 | DA 3
194 | F2 5+d
195 | FA 4
196 |
197 | ## NOPs
198 | 02 2
199 | 03 1
200 | 07 1
201 | 0B 1
202 | 0F 1
203 | 13 1
204 | 17 1
205 | 1B 1
206 | 1F 1
207 | 22 2
208 | 23 1
209 | 27 1
210 | 2B 1
211 | 2F 1
212 | 33 1
213 | 37 1
214 | 3B 1
215 | 3F 1
216 | 42 2
217 | 43 1
218 | 44 3
219 | 47 1
220 | 4B 1
221 | 4F 1
222 | 53 1
223 | 54 4
224 | 57 1
225 | 5B 1
226 | 5C 8
227 | 5F 1
228 | 62 2
229 | 63 1
230 | 67 1
231 | 6B 1
232 | 6F 1
233 | 73 1
234 | 77 1
235 | 7B 1
236 | 7F 1
237 | 82 2
238 | 83 1
239 | 87 1
240 | 8B 1
241 | 8F 1
242 | 93 1
243 | 97 1
244 | 9B 1
245 | 9F 1
246 | A3 1
247 | A7 1
248 | AB 1
249 | AF 1
250 | B3 1
251 | B7 1
252 | BB 1
253 | BF 1
254 | C2 2
255 | C3 1
256 | C7 1
257 | CB 1
258 | CF 1
259 | D3 1
260 | D4 4
261 | D7 1
262 | DB 1
263 | DC 4
264 | DF 1
265 | E2 2
266 | E3 1
267 | E7 1
268 | EB 1
269 | EF 1
270 | F3 1
271 | F4 4
272 | F7 1
273 | FB 1
274 | FC 4
275 | FF 1
276 |
277 | [documentation-mnemos]
278 | ## based on the 6502 docs
279 | BRA Branch Always
280 | This instruction takes an unconditional branch.
281 | BRA does not affect any of the flags or any other part of the machine other than the program counter.
282 |
283 | PHX Push Index Register X On Stack
284 | This instruction transfers the current value of the index register X to the next location on the stack, automatically decrementing the stack to point to the next empty location.
285 | The Push X instruction only affects the stack pointer register which is decremented by 1 as a result of the operation. It affects no flags.
286 |
287 | PHY Push Index Register Y On Stack
288 | This instruction transfers the current value of the index register Y to the next location on the stack, automatically decrementing the stack to point to the next empty location.
289 | The Push Y instruction only affects the stack pointer register which is decremented by 1 as a result of the operation. It affects no flags.
290 |
291 | PLX Pull Index Register X From Stack
292 | This instruction adds 1 to the current value of the stack pointer and uses it to address the stack and loads the contents of the stack into the X register.
293 | The PLX instruction does not affect the carry or overflow flags. It sets N if the bit 7 is on in index register X as a result of instructions, otherwise it is reset. If index register X is zero as a result of the PLA, then the Z flag is set, otherwise it is reset. The PLX instruction changes content of the index register X to the contents of the memory location at stack register plus 1 and also increments the stack register.
294 |
295 | PLY Pull Index Register Y From Stack
296 | This instruction adds 1 to the current value of the stack pointer and uses it to address the stack and loads the contents of the stack into the Y register.
297 | The PLY instruction does not affect the carry or overflow flags. It sets N if the bit 7 is on in index register Y as a result of instructions, otherwise it is reset. If index register Y is zero as a result of the PLA, then the Z flag is set, otherwise it is reset. The PLY instruction changes content of the index register Y to the contents of the memory location at stack register plus 1 and also increments the stack register.
298 |
299 | STZ Store Zero In Memory
300 | Transfers the value 0 to addressed memory location.
301 | No flags or registers in the microprocessor are affected by the store operation.
302 |
303 | ## https://github.com/MEGA65/c65-specifications/blob/master/c65manualupdated.txt
304 | TRB Test And Reset Memory Bits With Accumulator
305 | This instruction tests and resets bits in memory, using the accumulator for both a test mask, and a reset mask. It performs a logical AND between the inverted bits of the accumulator and the bits in memory, storing the result back into memory.
306 | The zero flag is set if all bits of the result of the AND are zero, otherwise it is reset.
307 |
308 | TSB Test And Set Memory Bits With Accumulator
309 | This instruction tests and sets bits in memory, using the accumulator for both a test mask, and a set mask. It performs a logical OR between the bits of the accumulator and the bits in memory, storing the result back into memory.
310 | The zero flag is set if all bits of the result of the OR are zero, otherwise it is reset.
311 |
312 | [documentation-addmodes]
313 | ## http://datasheets.chipdb.org/Western%20Design/W65C02S.pdf
314 |
315 | (a8) Zero Page Indirect
316 | With Zero Page Indirect addressing mode, the second byte of the instruction is a zero page indirect address that points to the low byte of a two byte effective address.
317 |
318 | (a16,X) Absolute X-Indexed Indirect
319 | With the Absolute Indexed Indirect addressing mode, the X Index Register is added to the second and third byes of the instruction to form an address to a pointer. This address mode is only used with the JMP instruction and the program Counter is loaded with the first and second bytes at this pointer.
320 |
--------------------------------------------------------------------------------
/src/6502/cpu_65c02s.txt:
--------------------------------------------------------------------------------
1 | ## This is a description file for a 6502-like CPU.
2 | ## See https://github.com/mist64/c64ref for details.
3 |
4 | [info]
5 | manufacturer WDC
6 | name 65C02S
7 | year 1986 ## or earlier; http://forum.6502.org/viewtopic.php?p=38895
8 | id 65c02s
9 | basedon r65c02
10 | description This is the later version of Western Design Center's 65C02, which supports the Rockwell extensions and adds two power saving opcodes borrowed from the 65c816.
11 |
12 | [mnemos]
13 | STP Stop the Clock
14 | WAI Wait for Interrupt
15 |
16 | [operations]
17 | STP ctrl -------- Stop the Clock
18 | WAI ctrl -------- Wait for Interrupt
19 |
20 | [opcodes]
21 | CB WAI
22 | DB STP
23 |
24 | [timing]
25 | CB 3
26 | DB 3
27 |
28 | [documentation-mnemos]
29 |
30 | STP Stop the Clock
31 | The processor halts until a hardware reset is applied. Power-supply current drops to nearly zero.
32 |
33 | WAI Wait for Interrupt
34 | The processor pauses at the current location until the next interrupt occurs. This allows for zero latency interrupt response.
35 |
36 |
37 |
38 |
--------------------------------------------------------------------------------
/src/6502/cpu_65c816.txt:
--------------------------------------------------------------------------------
1 | ## This is a description file for a 6502-like CPU.
2 | ## See https://github.com/mist64/c64ref for details.
3 |
4 | [info]
5 | manufacturer WDC
6 | name 65C816
7 | year 1984
8 | id 65c816 ## https://en.wikipedia.org/wiki/WDC_65C816
9 | basedon 65c02
10 | description This is the original implementation of the 16 bit version of the 65C02 designed by Western Design Center, Inc. It supports all instructions of original WDC 65C02, and adds support support for 16 bit registers, 24 bit addresses, a relocatable zero page and stack-relative addressing, filling all 256 opcodes. (The timing information corresponds to native mode.)
11 |
12 | [registers]
13 | # A,X,Y,P,S,DBR,D,K,PC
14 | A 16 Accumulator
15 | X 16 X Index Register
16 | Y 16 Y Index Register
17 | P 8 Processor Status
18 | S 16 Stack Pointer
19 | DBR 8 Data Bank Register
20 | D 16 Direct Page Register
21 | K 8 Program Bank Register
22 | PC 16 Program Counter
23 |
24 | [flags]
25 | 5 M Accumulator/Memory Width
26 | 4 X Index Register Width
27 | 10 E Emulation Mode
28 |
29 | [mnemos]
30 | BRL Branch Long
31 | COP Coprocessor
32 | JSL Jump to Subroutine Long
33 | MVN Move Memory Negative
34 | MVP Move Memory Positive
35 | PEA Push Effective Address
36 | PEI Push Effective Indirect Address
37 | PER Push Effective Relative Address
38 | PHB Push Data Bank Register
39 | PHD Push Direct Register
40 | PHK Push K Register
41 | PLB Pull Data Bank Register
42 | PLD Pull Direct Register
43 | REP Reset Processor Status Bits
44 | RTL Return From Subroutine Long
45 | SEP Set Processor Status Bits
46 | STP Stop the Clock
47 | TCD Transfer C Accumulator to Direct Register
48 | TCS Transfer C Accumulator to Stack Pointer
49 | TDC Transfer Direct Register to C Accumulator
50 | TSC Transfer Stack Pointer to C Accumulator
51 | TXY Transfer X to Y
52 | TYX Transfer Y to X
53 | WAI Wait for Interrupt
54 | WDM William D. Mensch, Jr.
55 | XBA Exchange B and A Accumulator
56 | XCE Exchange Carry and Emulation Flags
57 |
58 | [operations]
59 | BRL ctrl -------- Branch always long
60 | COP ctrl ----01-- Co-processor empowerment
61 | JSL ctrl -------- Jump to subroutine long
62 | MVN load -------- Move memory negative
63 | MVP load -------- Move memory positive
64 | PEA stack -------- Mw↓
65 | PEI stack -------- Mw↓
66 | PER stack -------- Mw↓
67 | PHB stack -------- B↓
68 | PHD stack -------- D↓
69 | PHK stack -------- K↓
70 | PLB stack *-----*- B↑
71 | PLD stack *-----*- D↑
72 | REP flags ******** P ⊼ M → P
73 | RTL ctrl -------- Return from subroutine long
74 | SEP flags ******** P ∨ M → P
75 | STP ctrl -------- Stop the clock
76 | TCD trans *-----*- C → D
77 | TCS trans -------- C → S
78 | TDC trans *-----*- D → C
79 | TSC trans *-----*- S → C
80 | TXY trans *-----*- T → Y
81 | TYX trans *-----*- Y → X
82 | WAI ctrl -------- Wait for interrupt
83 | WDM nop -------- Reserved for future expansion
84 | XBA trans *-----*- B ↔ A
85 | XCE flags -------** C ↔ E
86 |
87 | [addmodes]
88 | ## new 8/16 bit immediates
89 | #m:d8/d16 3-m #$nn/$nnnn Immediate (M)
90 | #x:d8/d16 3-x #$nn/$nnnn Immediate (X)
91 |
92 | ## new modes
93 | [a16] 3 [$nnnn] Absolute Indirect Long
94 | (a16,X) 3 ($nnnn,X) Absolute X-Indexed Indirect
95 | [a8] 2 [$nn] Direct Page Indirect Long
96 | [a8],Y 2 [$nn],Y Direct Page Indirect Y-Indexed Long
97 | a24 4 $nnnnnn Absolute Long
98 | a24,X 4 $nnnnnn,X Absolute X-Indexed Long
99 | r16 3 $nnnn Relative (word)
100 | src,dest 3 $nn,$nn Block Move
101 | a8,S 2 $nn,S Stack Relative
102 | (a8,S),Y 2 ($nn,S),Y Stack Relative Indirect Y-Indexed
103 |
104 | ## renamed modes (zero page -> direct page)
105 | a8 2 $nn Direct Page
106 | a8,X 2 $nn,X X-Indexed Direct Page
107 | a8,Y 2 $nn,Y Y-Indexed Direct Page
108 | (a8,X) 2 ($nn,X) X-Indexed Direct Page Indirect
109 | (a8),Y 2 ($nn),Y Direct Page Indirect Y-Indexed
110 |
111 | [opcodes]
112 | 02 COP #d8
113 | 03 ORA a8,S
114 | 07 ORA [a8]
115 | 0B PHD
116 | 0F ORA a24
117 | 13 ORA (a8,S),Y
118 | 17 ORA [a8],Y
119 | 1B TCS
120 | 1F ORA a24,X
121 | 22 JSL a24
122 | 23 AND a8,S
123 | 27 AND [a8]
124 | 2B PLD
125 | 2F AND a24
126 | 33 AND (a8,S),Y
127 | 37 AND [a8],Y
128 | 3B TSC
129 | 3F AND a24,X
130 | 42 WDM #d8
131 | 43 EOR a8,S
132 | 44 MVP src,dest
133 | 47 EOR [a8]
134 | 4B PHK
135 | 4F EOR a24
136 | 53 EOR (a8,S),Y
137 | 54 MVN src,dest
138 | 57 EOR [a8],Y
139 | 5B TCD
140 | 5C JMP a24
141 | 5F EOR a24,X
142 | 62 PER #d8
143 | 63 ADC a8,S
144 | 67 ADC [a8]
145 | 6B RTL
146 | 6F ADC a24
147 | 73 ADC (a8,S),Y
148 | 77 ADC [a8],Y
149 | 7B TDC
150 | 7F ADC a24,X
151 | 82 BRL r16
152 | 83 STA a8,S
153 | 87 STA [a8]
154 | 8B PHB
155 | 8F STA a24
156 | 93 STA (a8,S),Y
157 | 97 STA [a8],Y
158 | 9B TXY
159 | 9F STA a24,X
160 | A3 LDA a8,S
161 | A7 LDA [a8]
162 | AB PLB
163 | AF LDA a24
164 | B3 LDA (a8,S),Y
165 | B7 LDA [a8],Y
166 | BB TYX
167 | BF LDA a24,X
168 | C2 REP #d8
169 | C3 CMP a8,S
170 | C7 CMP [a8]
171 | CB WAI
172 | CF CMP a24
173 | D3 CMP (a8,S),Y
174 | D4 PEI a8
175 | D7 CMP [a8],Y
176 | DB STP
177 | DC JMP [a16]
178 | DF CMP a24,X
179 | E2 SEP #d8
180 | E3 SBC a8,S
181 | E7 SBC [a8]
182 | EB XBA
183 | EF SBC a24
184 | F3 SBC (a8,S),Y
185 | F4 PEA #d8
186 | F7 SBC [a8],Y
187 | FB XCE
188 | FC JSR (a16,X)
189 | FF SBC a24,X
190 |
191 | 09 ORA #m:d8/d16
192 | 29 AND #m:d8/d16
193 | 49 EOR #m:d8/d16
194 | 69 ADC #m:d8/d16
195 | 89 BIT #m:d8/d16
196 | A0 LDY #x:d8/d16
197 | A2 LDX #x:d8/d16
198 | A9 LDA #m:d8/d16
199 | C0 CPY #x:d8/d16
200 | C9 CMP #m:d8/d16
201 | E0 CPX #x:d8/d16
202 | E9 SBC #m:d8/d16
203 |
204 | [timing]
205 | 00 8
206 | 01 7-m+w
207 | 02 8
208 | 03 5-m
209 | 04 7-2*m+w
210 | 05 4-m+w
211 | 06 7-2*m+w
212 | 07 7-m+w
213 | 08 3
214 | 09 3-m
215 | 0A 2
216 | 0B 4
217 | 0C 8-2*m
218 | 0D 5-m
219 | 0E 8-2*m
220 | 0F 6-m
221 | 10 2+t
222 | 11 7-m+w-x+x*p
223 | 12 6-m+w
224 | 13 8-m
225 | 14 7-2*m+w
226 | 15 5-m+w
227 | 16 8-2*m+w
228 | 17 7-m+w
229 | 18 2
230 | 19 6-m-x+x*p
231 | 1A 2
232 | 1B 2
233 | 1C 8-2*m
234 | 1D 6-m-x+x*p
235 | 1E 9-2*m
236 | 1F 6-m
237 | 20 6
238 | 21 7-m+w
239 | 22 8
240 | 23 5-m
241 | 24 4-m+w
242 | 25 4-m+w
243 | 26 7-2*m+w
244 | 27 7-m+w
245 | 28 4
246 | 29 3-m
247 | 2A 2
248 | 2B 5
249 | 2C 5-m
250 | 2D 5-m
251 | 2E 8-2*m
252 | 2F 6-m
253 | 30 2+t
254 | 31 7-m+w-x+x*p
255 | 32 6-m+w
256 | 33 8-m
257 | 34 5-m+w
258 | 35 5-m+w
259 | 36 8-2*m+w
260 | 37 7-m+w
261 | 38 2
262 | 39 6-m-x+x*p
263 | 3A 2
264 | 3B 2
265 | 3C 6-m-x+x*p
266 | 3D 6-m-x+x*p
267 | 3E 9-2*m
268 | 3F 6-m
269 | 40 7
270 | 41 7-m+w
271 | 42 2
272 | 43 5-m
273 | 44 7
274 | 45 4-m+w
275 | 46 7-2*m+w
276 | 47 7-m+w
277 | 48 4-m
278 | 49 3-m
279 | 4A 2
280 | 4B 3
281 | 4C 3
282 | 4D 5-m
283 | 4E 8-2*m
284 | 4F 6-m
285 | 50 2+t
286 | 51 7-m+w-x+x*p
287 | 52 6-m+w
288 | 53 8-m
289 | 54 7
290 | 55 5-m+w
291 | 56 8-2*m+w
292 | 57 7-m+w
293 | 58 2
294 | 59 6-m-x+x*p
295 | 5A 4-x
296 | 5B 2
297 | 5C 4
298 | 5D 6-m-x+x*p
299 | 5E 9-2*m
300 | 5F 6-m
301 | 60 6
302 | 61 7-m+w
303 | 62 6
304 | 63 5-m
305 | 64 4-m+w
306 | 65 4-m+w
307 | 66 7-2*m+w
308 | 67 7-m+w
309 | 68 5-m
310 | 69 3-m
311 | 6A 2
312 | 6B 6
313 | 6C 5
314 | 6D 5-m
315 | 6E 8-2*m
316 | 6F 6-m
317 | 70 2+t
318 | 71 7-m+w-x+x*p
319 | 72 6-m+w
320 | 73 8-m
321 | 74 5-m+w
322 | 75 5-m+w
323 | 76 8-2*m+w
324 | 77 7-m+w
325 | 78 2
326 | 79 6-m-x+x*p
327 | 7A 5-x
328 | 7B 2
329 | 7C 6
330 | 7D 6-m-x+x*p
331 | 7E 9-2*m
332 | 7F 6-m
333 | 80 3
334 | 81 7-m+w
335 | 82 4
336 | 83 5-m
337 | 84 4-x+w
338 | 85 4-m+w
339 | 86 4-x+w
340 | 87 7-m+w
341 | 88 2
342 | 89 3-m
343 | 8A 2
344 | 8B 3
345 | 8C 5-x
346 | 8D 5-m
347 | 8E 5-x
348 | 8F 6-m
349 | 90 2+t
350 | 91 7-m+w
351 | 92 6-m+w
352 | 93 8-m
353 | 94 5-x+w
354 | 95 5-m+w
355 | 96 5-x+w
356 | 97 7-m+w
357 | 98 2
358 | 99 6-m
359 | 9A 2
360 | 9B 2
361 | 9C 5-m
362 | 9D 6-m
363 | 9E 6-m
364 | 9F 6-m
365 | A0 3-x
366 | A1 7-m+w
367 | A2 3-x
368 | A3 5-m
369 | A4 4-x+w
370 | A5 4-m+w
371 | A6 4-x+w
372 | A7 7-m+w
373 | A8 2
374 | A9 3-m
375 | AA 2
376 | AB 4
377 | AC 5-x
378 | AD 5-m
379 | AE 5-x
380 | AF 6-m
381 | B0 2+t
382 | B1 7-m+w-x+x*p
383 | B2 6-m+w
384 | B3 8-m
385 | B4 5-x+w
386 | B5 5-m+w
387 | B6 5-x+w
388 | B7 7-m+w
389 | B8 2
390 | B9 6-m-x+x*p
391 | BA 2
392 | BB 2
393 | BC 6-2*x+x*p
394 | BD 6-m-x+x*p
395 | BE 6-2*x+x*p
396 | BF 6-m
397 | C0 3-x
398 | C1 7-m+w
399 | C2 3
400 | C3 5-m
401 | C4 4-x+w
402 | C5 4-m+w
403 | C6 7-2*m+w
404 | C7 7-m+w
405 | C8 2
406 | C9 3-m
407 | CA 2
408 | CB 3
409 | CC 5-x
410 | CD 5-m
411 | CE 8-2*m
412 | CF 6-m
413 | D0 2+t
414 | D1 7-m+w-x+x*p
415 | D2 6-m+w
416 | D3 8-m
417 | D4 6+w
418 | D5 5-m+w
419 | D6 8-2*m+w
420 | D7 7-m+w
421 | D8 2
422 | D9 6-m-x+x*p
423 | DA 4-x
424 | DB 3
425 | DC 6
426 | DD 6-m-x+x*p
427 | DE 9-2*m
428 | DF 6-m
429 | E0 3-x
430 | E1 7-m+w
431 | E2 3
432 | E3 5-m
433 | E4 4-x+w
434 | E5 4-m+w
435 | E6 7-2*m+w
436 | E7 7-m+w
437 | E8 2
438 | E9 3-m
439 | EA 2
440 | EB 3
441 | EC 5-x
442 | ED 5-m
443 | EE 8-2*m
444 | EF 6-m
445 | F0 2+t
446 | F1 7-m+w-x+x*p
447 | F2 6-m+w
448 | F3 8-m
449 | F4 5
450 | F5 5-m+w
451 | F6 8-2*m+w
452 | F7 7-m+w
453 | F8 2
454 | F9 6-m-x+x*p
455 | FA 5-x
456 | FB 2
457 | FC 8
458 | FD 6-m-x+x*p
459 | FE 9-2*m
460 | FF 6-m
461 |
462 | [vectors]
463 | 00FFE4 COP
464 | 00FFE6 BRK
465 | 00FFE8 ABORT
466 | 00FFEA NMI
467 | 00FFEE IRQ
468 | 00FFFC RESET
469 |
470 | [documentation-mnemos|noinherit]
471 |
472 | [documentation-addmodes|noinherit]
473 |
--------------------------------------------------------------------------------
/src/6502/cpu_65dtv02.txt:
--------------------------------------------------------------------------------
1 | ## This is a description file for a 6502-like CPU.
2 | ## See https://github.com/mist64/c64ref for details.
3 |
4 | [info]
5 | name 65DTV02
6 | year 2005
7 | id 65dtv02
8 | basedon 6502
9 | description This is a modern reimplementation of the 6502 by Jeri Ellsworth as used in the C64DTV2. It reproduces all quirks of the original 6502 as well as most undocumented opcodes and adds three new instructions and an MMU. (The timing information corresponds to "skip internal cycles" mode.)
10 |
11 | [registers]
12 | # A,X,Y,S,P,PC,R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15
13 | A 8 Accumulator (alias for R0-R15)
14 | X 8 X Index Register (alias for R0-R15)
15 | Y 8 Y Index Register (alias for R0-R15)
16 | R0 8 Default Accumulator
17 | R1 8 Default Y Register
18 | R2 8 Default X Register
19 | R3 8 Reserved
20 | R4 8 Reserved
21 | R5 8 Reserved
22 | R6 8 Reserved
23 | R7 8 Reserved
24 | R8 8 Bank 0-3 Access Mode
25 | R9 8 CPU Control
26 | R10 8 Base Page Segment
27 | R11 8 Stack Segment
28 | R12 8 Bank 0 Segment
29 | R13 8 Bank 1 Segment
30 | R14 8 Bank 2 Segment
31 | R15 8 Bank 3 Segment
32 |
33 | [mnemos]
34 | # new instructions
35 | SAC Set Accumulator Mapping
36 | SIR Set Index Register Mapping
37 | BRA Branch Always
38 |
39 | # bugs in undocumented instructions
40 | 2B *ANC #d8 ## https://www.c64-wiki.com/wiki/C64DTV_Programming_Guide
41 | 9B *NOP a16,Y ## VICE source
42 | ##C7 *DCP a8 ## unclear -- https://www.c64-wiki.com/wiki/C64DTV_Programming_Guide
43 |
44 | [operations]
45 | SAC flags -------- Set Accumulator Mapping
46 | SIR flags -------- Set Index Register Mapping
47 | BRA ctrl -------- Branch Always
48 |
49 | [opcodes]
50 | 12 BRA r8
51 | 32 SAC #d8
52 | 42 SIR #d8
53 |
54 | [timing] ## "skip internal cycles" mode
55 | 00 6
56 | 01 6
57 | 02 X
58 | 03 7
59 | 04 3
60 | 05 3
61 | 06 4
62 | 07 4
63 | 08 2
64 | 09 2
65 | 0A 1
66 | 0B 2
67 | 0C 4
68 | 0D 4
69 | 0E 5
70 | 0F 5
71 | 10 2
72 | 11 5
73 | 12 2
74 | 13 6
75 | 14 3
76 | 15 3
77 | 16 4
78 | 17 4
79 | 18 1
80 | 19 4
81 | 1A 1
82 | 1B 5
83 | 1C 4
84 | 1D 4
85 | 1E 5
86 | 1F 5
87 | 20 5
88 | 21 6
89 | 22 X
90 | 23 7
91 | 24 3
92 | 25 3
93 | 26 4
94 | 27 4
95 | 28 2
96 | 29 2
97 | 2A 1
98 | 2B 2
99 | 2C 4
100 | 2D 4
101 | 2E 5
102 | 2F 5
103 | 30 2
104 | 31 5
105 | 32 2
106 | 33 6
107 | 34 3
108 | 35 3
109 | 36 4
110 | 37 4
111 | 38 1
112 | 39 4
113 | 3A 1
114 | 3B 5
115 | 3C 4
116 | 3D 4
117 | 3E 5
118 | 3F 5
119 | 40 4
120 | 41 6
121 | 42 2
122 | 43 7
123 | 44 3
124 | 45 3
125 | 46 4
126 | 47 4
127 | 48 2
128 | 49 2
129 | 4A 1
130 | 4B 2
131 | 4C 3
132 | 4D 4
133 | 4E 5
134 | 4F 5
135 | 50 2
136 | 51 5
137 | 52 X
138 | 53 6
139 | 54 3
140 | 55 3
141 | 56 4
142 | 57 4
143 | 58 1
144 | 59 4
145 | 5A 1
146 | 5B 5
147 | 5C 4
148 | 5D 4
149 | 5E 5
150 | 5F 5
151 | 60 4
152 | 61 6
153 | 62 X
154 | 63 7
155 | 64 3
156 | 65 3
157 | 66 4
158 | 67 4
159 | 68 2
160 | 69 2
161 | 6A 1
162 | 6B 2
163 | 6C 5
164 | 6D 4
165 | 6E 5
166 | 6F 5
167 | 70 2
168 | 71 5
169 | 72 X
170 | 73 6
171 | 74 3
172 | 75 3
173 | 76 4
174 | 77 4
175 | 78 1
176 | 79 4
177 | 7A 1
178 | 7B 5
179 | 7C 4
180 | 7D 4
181 | 7E 5
182 | 7F 5
183 | 80 2
184 | 81 6
185 | 82 2
186 | 83 6
187 | 84 3
188 | 85 3
189 | 86 3
190 | 87 3
191 | 88 1
192 | 89 2
193 | 8A 1
194 | 8B 2
195 | 8C 4
196 | 8D 4
197 | 8E 4
198 | 8F 4
199 | 90 2
200 | 91 5
201 | 92 X
202 | 93 5
203 | 94 3
204 | 95 3
205 | 96 3
206 | 97 3
207 | 98 1
208 | 99 4
209 | 9A 1
210 | 9B 4
211 | 9C 4
212 | 9D 4
213 | 9E 4
214 | 9F 4
215 | A0 2
216 | A1 6
217 | A2 2
218 | A3 6
219 | A4 3
220 | A5 3
221 | A6 3
222 | A7 3
223 | A8 1
224 | A9 2
225 | AA 1
226 | AB 2
227 | AC 4
228 | AD 4
229 | AE 4
230 | AF 4
231 | B0 2
232 | B1 5
233 | B2 X
234 | B3 5
235 | B4 3
236 | B5 3
237 | B6 3
238 | B7 3
239 | B8 1
240 | B9 4
241 | BA 1
242 | BB 4
243 | BC 4
244 | BD 4
245 | BE 4
246 | BF 4
247 | C0 2
248 | C1 6
249 | C2 2
250 | C3 7
251 | C4 3
252 | C5 3
253 | C6 4
254 | C7 4
255 | C8 1
256 | C9 2
257 | CA 1
258 | CB 2
259 | CC 4
260 | CD 4
261 | CE 5
262 | CF 5
263 | D0 2
264 | D1 5
265 | D2 X
266 | D3 6
267 | D4 3
268 | D5 3
269 | D6 4
270 | D7 4
271 | D8 1
272 | D9 4
273 | DA 1
274 | DB 5
275 | DC 4
276 | DD 4
277 | DE 5
278 | DF 5
279 | E0 2
280 | E1 6
281 | E2 2
282 | E3 7
283 | E4 3
284 | E5 3
285 | E6 4
286 | E7 4
287 | E8 1
288 | E9 2
289 | EA 1
290 | EB 2
291 | EC 4
292 | ED 4
293 | EE 5
294 | EF 5
295 | F0 2
296 | F1 5
297 | F2 X
298 | F3 6
299 | F4 3
300 | F5 3
301 | F6 4
302 | F7 4
303 | F8 1
304 | F9 4
305 | FA 1
306 | FB 5
307 | FC 4
308 | FD 4
309 | FE 5
310 | FF 5
311 |
312 | [documentation-mnemos]
313 | ## https://www.c64-wiki.com/wiki/C64DTV_Programming_Guide
314 |
315 | SAC Set Accumulator Mapping
316 | The 65DTV02 has a register file of 16 bytes, some of which double as control/MMU registers. The lower four bits of the SAC instruction's immediate operand assign the register that will be accessed through read operations to the accumulator, and the upper four bits assign the register that will be accessed through write operations to the accumulator. The default register for the accumulator is 0.
317 |
318 | SIR Set Index Register Mapping
319 | The 65DTV02 has a register file of 16 bytes, some of which double as control/MMU registers. The lower four bits of the SIR instruction's immediate operand assign the register that index register X is mapped to, and the upper four bits assign the register that index register Y is mapped to. The default register for the index register X is 2, and the default for the index register Y is 1.
320 |
321 | BRA Branch Always
322 | This instruction takes an unconditional branch.
323 | BRA does not affect any of the flags or any other part of the machine other than the program counter.
324 |
--------------------------------------------------------------------------------
/src/6502/cpu_r65c02.txt:
--------------------------------------------------------------------------------
1 | ## This is a description file for a 6502-like CPU.
2 | ## See https://github.com/mist64/c64ref for details.
3 |
4 | [info]
5 | manufacturer Rockwell
6 | name R65C02
7 | year 1983 ## https://archive.org/details/micro-6502-journal-60/page/n71/mode/2up?q=65c02
8 | id r65c02
9 | basedon 65c02
10 | description This is the Rockwell-variant of the WDC 65c02, which adds 32 new bit testing and manipulation opcodes.
11 |
12 | [mnemos]
13 | BBR0 Branch on Bit 0 Reset
14 | BBR1 Branch on Bit 1 Reset
15 | BBR2 Branch on Bit 2 Reset
16 | BBR3 Branch on Bit 3 Reset
17 | BBR4 Branch on Bit 4 Reset
18 | BBR5 Branch on Bit 5 Reset
19 | BBR6 Branch on Bit 6 Reset
20 | BBR7 Branch on Bit 7 Reset
21 | BBS0 Branch on Bit 0 Set
22 | BBS1 Branch on Bit 1 Set
23 | BBS2 Branch on Bit 2 Set
24 | BBS3 Branch on Bit 3 Set
25 | BBS4 Branch on Bit 4 Set
26 | BBS5 Branch on Bit 5 Set
27 | BBS6 Branch on Bit 6 Set
28 | BBS7 Branch on Bit 7 Set
29 | RMB0 Reset Memory Bit 0
30 | RMB1 Reset Memory Bit 1
31 | RMB2 Reset Memory Bit 2
32 | RMB3 Reset Memory Bit 3
33 | RMB4 Reset Memory Bit 4
34 | RMB5 Reset Memory Bit 5
35 | RMB6 Reset Memory Bit 6
36 | RMB7 Reset Memory Bit 7
37 | SMB0 Set Memory Bit 0
38 | SMB1 Set Memory Bit 1
39 | SMB2 Set Memory Bit 2
40 | SMB3 Set Memory Bit 3
41 | SMB4 Set Memory Bit 4
42 | SMB5 Set Memory Bit 5
43 | SMB6 Set Memory Bit 6
44 | SMB7 Set Memory Bit 7
45 |
46 |
47 | [operations]
48 | BBR0 ctrl -------- Branch on M0 = 0
49 | BBR1 ctrl -------- Branch on M1 = 0
50 | BBR2 ctrl -------- Branch on M2 = 0
51 | BBR3 ctrl -------- Branch on M3 = 0
52 | BBR4 ctrl -------- Branch on M4 = 0
53 | BBR5 ctrl -------- Branch on M5 = 0
54 | BBR6 ctrl -------- Branch on M6 = 0
55 | BBR7 ctrl -------- Branch on M7 = 0
56 | BBS0 ctrl -------- Branch on M0 = 1
57 | BBS1 ctrl -------- Branch on M1 = 1
58 | BBS2 ctrl -------- Branch on M2 = 1
59 | BBS3 ctrl -------- Branch on M3 = 1
60 | BBS4 ctrl -------- Branch on M4 = 1
61 | BBS5 ctrl -------- Branch on M5 = 1
62 | BBS6 ctrl -------- Branch on M6 = 1
63 | BBS7 ctrl -------- Branch on M7 = 1
64 | RMB0 logic -------- 0 → M0
65 | RMB1 logic -------- 0 → M1
66 | RMB2 logic -------- 0 → M2
67 | RMB3 logic -------- 0 → M3
68 | RMB4 logic -------- 0 → M4
69 | RMB5 logic -------- 0 → M5
70 | RMB6 logic -------- 0 → M6
71 | RMB7 logic -------- 0 → M7
72 | SMB0 logic -------- 1 → M0
73 | SMB1 logic -------- 1 → M1
74 | SMB2 logic -------- 1 → M2
75 | SMB3 logic -------- 1 → M3
76 | SMB4 logic -------- 1 → M4
77 | SMB5 logic -------- 1 → M5
78 | SMB6 logic -------- 1 → M6
79 | SMB7 logic -------- 1 → M7
80 |
81 | [addmodes]
82 | a8,r8 3 $nn,$nnnn Zero Page, Relative
83 |
84 | [opcodes]
85 | 07 RMB0 a8
86 | 0F BBR0 a8,r8
87 | 17 RMB1 a8
88 | 1F BBR1 a8,r8
89 | 27 RMB2 a8
90 | 2F BBR2 a8,r8
91 | 37 RMB3 a8
92 | 3F BBR3 a8,r8
93 | 47 RMB4 a8
94 | 4F BBR4 a8,r8
95 | 57 RMB5 a8
96 | 5F BBR5 a8,r8
97 | 67 RMB6 a8
98 | 6F BBR6 a8,r8
99 | 77 RMB7 a8
100 | 7F BBR7 a8,r8
101 | 87 SMB0 a8
102 | 8F BBS0 a8,r8
103 | 97 SMB1 a8
104 | 9F BBS1 a8,r8
105 | A7 SMB2 a8
106 | AF BBS2 a8,r8
107 | B7 SMB3 a8
108 | BF BBS3 a8,r8
109 | C7 SMB4 a8
110 | CF BBS4 a8,r8
111 | D7 SMB5 a8
112 | DF BBS5 a8,r8
113 | E7 SMB6 a8
114 | EF BBS6 a8,r8
115 | F7 SMB7 a8
116 | FF BBS7 a8,r8
117 |
118 | [timing]
119 | 07 5
120 | 0F 5+t+p
121 | 17 5
122 | 1F 5+t+p
123 | 27 5
124 | 2F 5+t+p
125 | 37 5
126 | 3F 5+t+p
127 | 47 5
128 | 4F 5+t+p
129 | 57 5
130 | 5F 5+t+p
131 | 67 5
132 | 6F 5+t+p
133 | 77 5
134 | 7F 5+t+p
135 | 87 5
136 | 8F 5+t+p
137 | 97 5
138 | 9F 5+t+p
139 | A7 5
140 | AF 5+t+p
141 | B7 5
142 | BF 5+t+p
143 | C7 5
144 | CF 5+t+p
145 | D7 5
146 | DF 5+t+p
147 | E7 5
148 | EF 5+t+p
149 | F7 5
150 | FF 5+t+p
151 |
152 | [documentation-mnemos]
153 |
154 | BBR0 Branch on Bit 0 Reset
155 | This instruction tests the specified zero page location and branches if bit 0 is clear.
156 |
157 | BBR1 Branch on Bit 1 Reset
158 | This instruction tests the specified zero page location and branches if bit 1 is clear.
159 |
160 | BBR2 Branch on Bit 2 Reset
161 | This instruction tests the specified zero page location and branches if bit 2 is clear.
162 |
163 | BBR3 Branch on Bit 3 Reset
164 | This instruction tests the specified zero page location and branches if bit 3 is clear.
165 |
166 | BBR4 Branch on Bit 4 Reset
167 | This instruction tests the specified zero page location and branches if bit 4 is clear.
168 |
169 | BBR5 Branch on Bit 5 Reset
170 | This instruction tests the specified zero page location and branches if bit 5 is clear.
171 |
172 | BBR6 Branch on Bit 6 Reset
173 | This instruction tests the specified zero page location and branches if bit 6 is clear.
174 |
175 | BBR7 Branch on Bit 7 Reset
176 | This instruction tests the specified zero page location and branches if bit 7 is clear.
177 |
178 | BBS0 Branch on Bit 0 Set
179 | This instruction tests the specified zero page location and branches if bit 0 is set.
180 |
181 | BBS1 Branch on Bit 1 Set
182 | This instruction tests the specified zero page location and branches if bit 1 is set.
183 |
184 | BBS2 Branch on Bit 2 Set
185 | This instruction tests the specified zero page location and branches if bit 2 is set.
186 |
187 | BBS3 Branch on Bit 3 Set
188 | This instruction tests the specified zero page location and branches if bit 3 is set.
189 |
190 | BBS4 Branch on Bit 4 Set
191 | This instruction tests the specified zero page location and branches if bit 4 is set.
192 |
193 | BBS5 Branch on Bit 5 Set
194 | This instruction tests the specified zero page location and branches if bit 5 is set.
195 |
196 | BBS6 Branch on Bit 6 Set
197 | This instruction tests the specified zero page location and branches if bit 6 is set.
198 |
199 | BBS7 Branch on Bit 7 Set
200 | This instruction tests the specified zero page location and branches if bit 7 is set.
201 |
202 | RMB0 Reset Memory Bit 0
203 | This instruction clears bit 0 in the specified zero page location. It does not affect any flags or registers.
204 |
205 | RMB1 Reset Memory Bit 1
206 | This instruction clears bit 1 in the specified zero page location. It does not affect any flags or registers.
207 |
208 | RMB2 Reset Memory Bit 2
209 | This instruction clears bit 2 in the specified zero page location. It does not affect any flags or registers.
210 |
211 | RMB3 Reset Memory Bit 3
212 | This instruction clears bit 3 in the specified zero page location. It does not affect any flags or registers.
213 |
214 | RMB4 Reset Memory Bit 4
215 | This instruction clears bit 4 in the specified zero page location. It does not affect any flags or registers.
216 |
217 | RMB5 Reset Memory Bit 5
218 | This instruction clears bit 5 in the specified zero page location. It does not affect any flags or registers.
219 |
220 | RMB6 Reset Memory Bit 6
221 | This instruction clears bit 6 in the specified zero page location. It does not affect any flags or registers.
222 |
223 | RMB7 Reset Memory Bit 7
224 | This instruction clears bit 7 in the specified zero page location. It does not affect any flags or registers.
225 |
226 | SMB0 Set Memory Bit 0
227 | This instruction sets bit 0 in the specified zero page location. It does not affect any flags or registers.
228 |
229 | SMB1 Set Memory Bit 1
230 | This instruction sets bit 1 in the specified zero page location. It does not affect any flags or registers.
231 |
232 | SMB2 Set Memory Bit 2
233 | This instruction sets bit 2 in the specified zero page location. It does not affect any flags or registers.
234 |
235 | SMB3 Set Memory Bit 3
236 | This instruction sets bit 3 in the specified zero page location. It does not affect any flags or registers.
237 |
238 | SMB4 Set Memory Bit 4
239 | This instruction sets bit 4 in the specified zero page location. It does not affect any flags or registers.
240 |
241 | SMB5 Set Memory Bit 5
242 | This instruction sets bit 5 in the specified zero page location. It does not affect any flags or registers.
243 |
244 | SMB6 Set Memory Bit 6
245 | This instruction sets bit 6 in the specified zero page location. It does not affect any flags or registers.
246 |
247 | SMB7 Set Memory Bit 7
248 | This instruction sets bit 7 in the specified zero page location. It does not affect any flags or registers.
249 |
250 |
251 | [documentation-addmodes]
252 | ## http://archive.6502.org/datasheets/mos_65ce02_mpu.pdf
253 |
254 | a8,r8 Zero Page, Relative
255 | This mode is used only with the bit-test branch instructions (BBS and BCC). The second byte of the instruction specifies the zero page memory to be tested. The third byte of the instruction is the offset, whose range is -128 to 127 bytes, referenced to the location of the next instruction.
256 |
--------------------------------------------------------------------------------
/src/6502/csg.svg:
--------------------------------------------------------------------------------
1 |
--------------------------------------------------------------------------------
/src/6502/mos.svg:
--------------------------------------------------------------------------------
1 |
--------------------------------------------------------------------------------
/src/6502/out.sh:
--------------------------------------------------------------------------------
1 | cp -p index.html $1
2 |
3 | cp -p *.js cpu_*.txt $1
4 |
--------------------------------------------------------------------------------
/src/6502/rockwell.svg:
--------------------------------------------------------------------------------
1 |
--------------------------------------------------------------------------------
/src/6502/wdc.svg:
--------------------------------------------------------------------------------
1 |
--------------------------------------------------------------------------------
/src/c64disasm/generate.py:
--------------------------------------------------------------------------------
1 | #!/usr/bin/env python3
2 |
3 | import html, re, os
4 |
5 | filenames = [
6 | "c64disasm_ms.txt;c64disasm_cbm.txt",
7 | "c64disasm_de.txt",
8 | "c64disasm_en.txt",
9 | "c64disasm_sc.txt",
10 | "c64disasm_mn.txt",
11 | "c64disasm_mm.txt"
12 | ]
13 | names = [
14 | "Microsoft/Commodore Source",
15 | "Data Becker [German]",
16 | "Lee Davison",
17 | "Bob Sander-Cederlof [BASIC only]",
18 | "Magnus Nyman [KERNAL only]",
19 | "Marko Mäkelä"
20 | ]
21 | links = [
22 | "https://github.com/mist64/cbmsrc",
23 | "https://www.pagetable.com/?p=1015",
24 | "https://github.com/Project-64/reloaded/blob/master/c64/firmware/C64LD11.S",
25 | "https://www.pagetable.com/?p=728",
26 | "https://www.telecomm.at/documents/Jiffydos_Romlisting.doc",
27 | "https://github.com/Project-64/reloaded/blob/master/c64/C64DIS11.TXT"
28 | ]
29 | descriptions = [
30 | "The original M6502 BASIC source by Microsoft (KIM-1 version, not everything lines up, Commodore extensions are missing, but lots of comments by the original authors)
and the original C64 KERNAL source by Commodore (lots of comments by the original authors)",
31 | "German-language comments from Das neue Commodore-64-intern-Buch by Data Becker, ISBN 3890113079. Some minor corrections have been made.",
32 | "Comments from The almost completely commented C64 ROM disassembly V1.01 by Lee Davison. Some minor corrections have been made.",
33 | "Comments adapted from S-C DocuMentor for Applesoft by Bob Sander-Cederlof, for the version of Microsoft BASIC that shipped with the Apple II.",
34 | "Comments from JIFFYDOS version 6.01/version 6.02 by Magnus Nyman (Harlekin/FairLight), which were written for the JiffyDOS KERNAL, so some serial code and all tape code is missing comments.",
35 | "Comments from the Commodore 64 BASIC/KERNAL ROM Disassembly Version 1.0 (June 1994) by Marko Mäkelä."
36 | ]
37 |
38 | def cross_reference(string, symbols):
39 | hex_numbers = list(set(re.findall(r'(?" + hex_number + "")
44 | elif (dec_number >= 0xa000 and dec_number <= 0xbfff) or (dec_number >= 0xe000 and dec_number <= 0xffff):
45 | string = string.replace(hex_number, "" + hex_number + "")
46 |
47 | for symbol in symbols:
48 | string = re.sub('\\b' + symbol + '\\b', '' + symbol + '', string)
49 |
50 | return string
51 |
52 | asm_donor_index = 1
53 | source_index = 0 # we treat the Microsoft/Commodore source differently
54 |
55 | symbols = []
56 | symbol_lines = [line.rstrip() for line in open('../c64mem/c64mem_src.txt')]
57 | for line in symbol_lines:
58 | if line.startswith('#') or line.startswith('-'):
59 | continue
60 | symbol = line[13:19].rstrip()
61 | if symbol != '':
62 | symbols.append(symbol)
63 | symbols = set(symbols)
64 |
65 | data = []
66 | linenumber = []
67 | address = []
68 | for filename in filenames:
69 | d = []
70 | for f in filename.split(";"):
71 | d += [line.rstrip() for line in open(f)]
72 | data.append(d)
73 | linenumber.append(0)
74 | address.append(0)
75 | files = len(filenames)
76 |
77 | asmaddress = 0
78 | asmlinenumber = 0
79 |
80 | for i in range(0, files):
81 | while True:
82 | line = data[i][linenumber[i]]
83 | if len(line) > 0 and line[0] == '.':
84 | break
85 | linenumber[i] = linenumber[i] + 1
86 |
87 |
88 | print('')
89 | print('')
90 | print('')
91 | print('')
92 | print('BASIC & KERNAL ROM Disassembly | Ultimate C64 Reference')
93 | print('')
94 |
95 | print('')
104 | print('')
105 | print('')
106 |
107 | print('')
108 | print('')
109 |
110 | print('')
137 | print('')
138 |
139 | print('')
140 | print('')
141 | print('')
142 |
143 | print('
This allows you to view different commentaries side-by-side. You can enable/disable individual columns:')
144 | print('
')
148 |
149 | print('
')
150 | print('
')
151 |
152 | print('')
153 | print('| Disassembly | ')
154 | for i in range(0, files):
155 | print('' + names[i] + ' | ')
156 | print('
')
157 |
158 | count = 0
159 | while(True):
160 | count += 1
161 | # if count > 80:
162 | # break
163 |
164 | for i in range(0, files):
165 | if linenumber[i] >= len(data[i]):
166 | continue
167 | while len(data[i][linenumber[i]]) > 0 and (data[i][linenumber[i]][0] == '-' or data[i][linenumber[i]][0] == '#'):
168 | linenumber[i] = linenumber[i] + 1
169 |
170 | if asmlinenumber >= len(data[asm_donor_index]):
171 | break
172 |
173 | asm = data[asm_donor_index][asmlinenumber][0:32].rstrip()
174 | asmlinenumber = asmlinenumber + 1
175 |
176 | if len(asm) == 0:
177 | continue
178 | if asm[0] == '#' or asm[0] == '-':
179 | continue
180 |
181 | has_address = False
182 | if asm[0] == '.':
183 | hexaddress = asm[2:6]
184 | asmaddress = int(hexaddress, 16)
185 | has_address = True
186 |
187 | asm = cross_reference(asm, [])
188 |
189 | print('')
190 | print('| ')
191 | if has_address:
192 | print('')
193 | print('' + asm + ' | ')
194 |
195 | for i in range(0, files):
196 | print('')
197 | comments = []
198 | while True:
199 | if linenumber[i] >= len(data[i]):
200 | break
201 |
202 | line = data[i][linenumber[i]]
203 |
204 | if line.startswith('.'):
205 | address[i] = int(line[2:6], 16)
206 | if address[i] > asmaddress:
207 | break
208 | comment = line[32:]
209 | comment = html.escape(comment)
210 |
211 | comment = cross_reference(comment, symbols)
212 |
213 | if comment.startswith('***'):
214 | comment = '' + comment[3:] + ''
215 | elif comment.startswith('SUBTTL'):
216 | comment = '' + comment[6:] + ''
217 | elif comment.startswith('.LIB '):
218 | comment = '' + comment + ''
219 | else:
220 | scomment = comment.lstrip()
221 |
222 | if scomment.startswith(';'):
223 | comment = '' + comment + ''
224 |
225 | if len(comment) != 0:
226 | comment = '' + comment + '
'
227 |
228 | if len(comment) != 0:
229 | comments.append(comment)
230 |
231 | linenumber[i] = linenumber[i] + 1
232 |
233 | if len(comments):
234 | for comment in comments:
235 | print(comment)
236 | else:
237 | print(' ')
238 |
239 | print(' | ')
240 | print('
')
241 |
242 | print('
')
243 | print('
')
244 |
245 | print('
16 |
17 |
Based on Pepto's work.
18 |
19 |
20 |
21 |
22 | | Palette |
23 | Adjustments |
24 |
25 |
26 | |
27 |
114 | |
115 |
116 |
178 | |
179 |
180 |
181 |
182 |
colors
183 |
Link to this Palette
184 |
185 |
186 |
187 |
Colorspace Diagram
188 |
189 |
190 | |
191 |
192 | |
193 |
194 |
195 |
196 |
197 |
198 |
199 |
200 |
204 | |
205 |
206 |
207 |
208 |
209 |
210 |
Palette
211 |
212 |
213 |
214 |
215 |
216 |
217 |
218 |
219 |
220 |
221 |
222 |
223 |
224 |
225 |
226 |
227 |
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229 | |
230 | |
231 | |
232 |
233 |
234 |
235 |
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237 |
238 |
239 |
242 |
243 |
244 |
245 |
247 |
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251 |