├── .gitignore ├── FPGA for software developers.pdf ├── FPGA for software developers.pptx ├── Go_Board_Constraints.pcf ├── LICENSE ├── Makefile ├── README.md ├── alu.v ├── apio.ini ├── boot.mem ├── catch.hpp ├── copy_boot_mem.sh ├── grom8.core ├── grom8.ice ├── grom8.vlt ├── grom8_cpu.ice ├── grom_computer.v ├── grom_computer_tb.gtkw ├── grom_computer_tb.v ├── grom_cpu.v ├── grom_top.v ├── hex_to_2_x_7seg.ice ├── hex_to_7seg.v ├── instruction_set.txt ├── ram_memory.v ├── test_alu.cpp ├── test_comp.cpp └── test_cpu.cpp /.gitignore: -------------------------------------------------------------------------------- 1 | /.vscode 2 | /obj_dir 3 | /abc.history 4 | /grom.bin 5 | /grom.blif 6 | /grom.out 7 | /grom.txt 8 | /grom.vcd 9 | 10 | *.dblite 11 | *.asc 12 | *.bin 13 | *.blif 14 | *.out 15 | *.vcd 16 | -------------------------------------------------------------------------------- /FPGA for software developers.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mmicko/grom8/5478ab8ed65c90d2ab2dc36b9eab60d22ede5066/FPGA for software developers.pdf -------------------------------------------------------------------------------- /FPGA for software developers.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mmicko/grom8/5478ab8ed65c90d2ab2dc36b9eab60d22ede5066/FPGA for software developers.pptx -------------------------------------------------------------------------------- /Go_Board_Constraints.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | 3 | # iCEcube PCF 4 | 5 | # Version: 2014.12.27052 6 | 7 | # File Generated: Apr 27 2015 09:46:33 8 | 9 | # Family & Device: iCE40HX1K 10 | 11 | # Package: VQ100 12 | 13 | # ############################################################################## 14 | 15 | ### Main FPGA Clock 16 | set_io i_Clk 15 17 | 18 | ## Push-Button Switches 19 | set_io i_Switch_1 53 20 | 21 | ### LED Pins: 22 | set_io o_LED_1 56 23 | set_io o_LED_2 57 24 | set_io o_LED_3 59 25 | set_io o_LED_4 60 26 | 27 | ### 7 Segment Outputs 28 | set_io o_Segment1_A 3 29 | set_io o_Segment1_B 4 30 | set_io o_Segment1_C 93 31 | set_io o_Segment1_D 91 32 | set_io o_Segment1_E 90 33 | set_io o_Segment1_F 1 34 | set_io o_Segment1_G 2 35 | set_io o_Segment2_A 100 36 | set_io o_Segment2_B 99 37 | set_io o_Segment2_C 97 38 | set_io o_Segment2_D 95 39 | set_io o_Segment2_E 94 40 | set_io o_Segment2_F 8 41 | set_io o_Segment2_G 96 42 | 43 | ## UART Outputs 44 | #set_io i_UART_RX 73 45 | #set_io o_UART_TX 74 46 | 47 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 Miodrag Milanović 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ifeq ($(OS),Windows_NT) 2 | SILENT_OUT := >nul 3 | EXE := .exe 4 | else 5 | SILENT_OUT := >/dev/null 6 | EXE := 7 | endif 8 | .PHONY: all sim clean prog test test_alu test_cpu test_comp 9 | all: grom.bin 10 | 11 | sim: grom.out 12 | vvp grom.out 13 | 14 | grom.bin: grom_top.v hex_to_7seg.v grom_computer.v ram_memory.v grom_cpu.v alu.v Go_Board_Constraints.pcf 15 | yosys -q -p "synth_ice40 -abc2 -top grom_top -blif grom.blif" hex_to_7seg.v grom_computer.v ram_memory.v alu.v grom_cpu.v grom_top.v 16 | arachne-pnr -d 1k -P vq100 -p Go_Board_Constraints.pcf grom.blif -o grom.txt 17 | icepack grom.txt grom.bin 18 | icetime -d hx1k -P vq100 grom.txt 19 | 20 | grom.out: grom_computer_tb.v ram_memory.v alu.v grom_cpu.v grom_computer.v 21 | iverilog -D DISASSEMBLY -o grom.out grom_computer_tb.v ram_memory.v alu.v grom_cpu.v grom_computer.v 22 | 23 | prog: grom.bin 24 | iceprog grom.bin 25 | 26 | clean: 27 | $(RM) -f grom.blif grom.txt grom.bin grom.out rotor.out abc.history grom.vcd 28 | $(RM) -f -r obj_dir 29 | 30 | test: test_alu test_cpu test_comp 31 | 32 | test_comp: obj_dir/computer/Vgrom_computer$(EXE) 33 | @obj_dir/computer/Vgrom_computer$(EXE) 34 | 35 | test_alu: obj_dir/alu/Valu$(EXE) 36 | @obj_dir/alu/Valu$(EXE) 37 | 38 | test_cpu: obj_dir/cpu/Vgrom_cpu$(EXE) 39 | @obj_dir/cpu/Vgrom_cpu$(EXE) 40 | 41 | obj_dir: 42 | @mkdir obj_dir 43 | 44 | obj_dir/computer/Vgrom_computer$(EXE): obj_dir grom8.vlt grom_computer.v ram_memory.v grom_cpu.v alu.v test_comp.cpp 45 | @verilator_bin -Wall --Mdir obj_dir/computer --top-module grom_computer --cc grom8.vlt grom_computer.v ram_memory.v grom_cpu.v alu.v --exe test_comp.cpp 46 | @make -C obj_dir/computer -j -f Vgrom_computer.mk Vgrom_computer CC=gcc CXXFLAGS=-Wno-attributes VM_USER_DIR=../.. $(SILENT_OUT) 47 | 48 | obj_dir/alu/Valu$(EXE): obj_dir grom8.vlt alu.v test_alu.cpp 49 | @verilator_bin -Wall --Mdir obj_dir/alu --top-module alu --cc grom8.vlt alu.v --exe test_alu.cpp 50 | @make -C obj_dir/alu -j -f Valu.mk Valu CC=gcc CXXFLAGS=-Wno-attributes VM_USER_DIR=../.. $(SILENT_OUT) 51 | 52 | obj_dir/cpu/Vgrom_cpu$(EXE): obj_dir grom8.vlt grom_cpu.v alu.v test_cpu.cpp 53 | @verilator_bin -Wall --Mdir obj_dir/cpu --top-module grom_cpu --cc grom8.vlt grom_cpu.v alu.v --exe test_cpu.cpp 54 | @make -C obj_dir/cpu -j -f Vgrom_cpu.mk Vgrom_cpu CXXFLAGS=-Wno-attributes VM_USER_DIR=../.. $(SILENT_OUT) 55 | 56 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Grom-8 FPGA 2 | 3 | This CPU implementation is made for purely educational purposes, in order to learn various constructs in Verilog. 4 | It is far from perfect, but includes all needed features one CPU needs. 5 | 6 | GROM-8 is simple 8-bit CPU, with : 7 | * 4 general purpose registers 8 | * 12 bit address bus and PC (program counter) 9 | * Code and data segment registers (CS,DS) (4 bit) 10 | * Stack pointer (SP) (12 bit) 11 | * 8-bit ALU with C-carry, Z-zero and S-sign flags 12 | 13 | 14 | Instruction set 15 | ================================ 16 | 17 | |7..4|3..2|1..0 |2nd |Instruction | 18 | |----|----|-----|------|-------------| 19 | |0000|dst |src | |MOV dst, src| 20 | |0001|00 |reg | |ADD reg | 21 | |0001|01 |reg | |SUB reg | 22 | |0001|10 |reg | |ADC reg | 23 | |0001|11 |reg | |SBC reg | 24 | |0010|00 |reg | |AND reg | 25 | |0010|01 |reg | |OR reg | 26 | |0010|10 |reg | |NOT reg | 27 | |0010|11 |reg | |XOR reg | 28 | |0011|00 |reg | |INC reg | 29 | |0011|01 |reg | |DEC reg | 30 | |0011|10 |reg | |CMP reg | 31 | |0011|11 |reg | |TST reg | 32 | |0100|00 |00 | |SHL| 33 | |0100|00 |01 | |SHR| 34 | |0100|00 |10 | |SAL| 35 | |0100|00 |11 | |SAR| 36 | |0100|01 |00 | |ROL| 37 | |0100|01 |01 | |ROR| 38 | |0100|01 |10 | |RCL | 39 | |0100|01 |11 | |RCR | 40 | |0100|10 |reg | |PUSH reg| 41 | |0100|11 |reg | |POP reg| 42 | |0101|dst |src | |LOAD dst, [src]| 43 | |0110|dst |src | |STORE [dst], src| 44 | |0111|00 |reg | |MOV CS, reg| 45 | |0111|01 |reg | |MOV DS, reg| 46 | |0111|10 |00 | |PUSH CS| 47 | |0111|10 |01 | |PUSH DS| 48 | |0111|10 |10 | |???| 49 | |0111|10 |11 | |???| 50 | |0111|11 |00 | |???| 51 | |0111|11 |01 | |???| 52 | |0111|11 |10 | |RET| 53 | |0111|11 |11 | |HLT| 54 | |1000|00 |00 |val |JMP val | 55 | |1000|00 |01 |val |JC val | 56 | |1000|00 |10 |val |JNC val | 57 | |1000|00 |11 |val |JM val | 58 | |1000|01 |00 |val |JP val | 59 | |1000|01 |01 |val |JZ val | 60 | |1000|01 |10 |val |JNZ val | 61 | |1000|01 |11 |val |??? | 62 | |1000|10 |00 |val |JR val | 63 | |1000|10 |01 |val |JRC val | 64 | |1000|10 |10 |val |JRNC val | 65 | |1000|10 |11 |val |JRM val | 66 | |1000|11 |00 |val |JRP val | 67 | |1000|11 |01 |val |JRZ val | 68 | |1000|11 |10 |val |JRNZ val | 69 | |1000|11 |11 |val |???| 70 | |1001|high| |low |JUMP addr| 71 | |1010|high| |low |CALL addr| 72 | |1011|high| |low |MOV SP,addr| 73 | |1100|xx |reg |val |IN reg,[val]| 74 | |1101|xx |reg |val |OUT [val],reg| 75 | |1110|xx |00 |val |MOV CS,val| 76 | |1110|xx |01 |val |MOV DS,val| 77 | |1110|xx |10 |val |???| 78 | |1110|xx |11 |val |???| 79 | |1111|00 |reg |val |MOV reg, val| 80 | |1111|01 |reg |val |LOAD reg, [val]| 81 | |1111|10 |reg |val |STORE [val], reg| 82 | |1111|11 |xx |val |???| 83 | -------------------------------------------------------------------------------- /alu.v: -------------------------------------------------------------------------------- 1 | module alu( 2 | input clk, 3 | input [7:0] A, 4 | input [7:0] B, 5 | input [3:0] operation, 6 | output reg [7:0] result, 7 | output reg CF, 8 | output reg ZF, 9 | output reg SF 10 | ); 11 | 12 | localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000; 13 | localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001; 14 | localparam ALU_OP_ADC /* verilator public_flat */ = 4'b0010; 15 | localparam ALU_OP_SBC /* verilator public_flat */ = 4'b0011; 16 | 17 | localparam ALU_OP_AND /* verilator public_flat */ = 4'b0100; 18 | localparam ALU_OP_OR /* verilator public_flat */ = 4'b0101; 19 | localparam ALU_OP_NOT /* verilator public_flat */ = 4'b0110; 20 | localparam ALU_OP_XOR /* verilator public_flat */ = 4'b0111; 21 | 22 | localparam ALU_OP_SHL /* verilator public_flat */ = 4'b1000; 23 | localparam ALU_OP_SHR /* verilator public_flat */ = 4'b1001; 24 | localparam ALU_OP_SAL /* verilator public_flat */ = 4'b1010; 25 | localparam ALU_OP_SAR /* verilator public_flat */ = 4'b1011; 26 | 27 | localparam ALU_OP_ROL /* verilator public_flat */ = 4'b1100; 28 | localparam ALU_OP_ROR /* verilator public_flat */ = 4'b1101; 29 | localparam ALU_OP_RCL /* verilator public_flat */ = 4'b1110; 30 | localparam ALU_OP_RCR /* verilator public_flat */ = 4'b1111; 31 | 32 | reg [8:0] tmp; 33 | 34 | always @(posedge clk) 35 | begin 36 | case (operation) 37 | ALU_OP_ADD : 38 | tmp = A + B; 39 | ALU_OP_SUB : 40 | tmp = A - B; 41 | ALU_OP_ADC : 42 | tmp = A + B + { 7'b0000000, CF }; 43 | ALU_OP_SBC : 44 | tmp = A - B - { 7'b0000000, CF }; 45 | ALU_OP_AND : 46 | tmp = {1'b0, A & B }; 47 | ALU_OP_OR : 48 | tmp = {1'b0, A | B }; 49 | ALU_OP_NOT : 50 | tmp = {1'b0, ~B }; 51 | ALU_OP_XOR : 52 | tmp = {1'b0, A ^ B}; 53 | ALU_OP_SHL : 54 | tmp = { A[7], A[6:0], 1'b0}; 55 | ALU_OP_SHR : 56 | tmp = { A[0], 1'b0, A[7:1]}; 57 | ALU_OP_SAL : 58 | // Same as SHL 59 | tmp = { A[7], A[6:0], 1'b0}; 60 | ALU_OP_SAR : 61 | tmp = { A[0], A[7], A[7:1]}; 62 | ALU_OP_ROL : 63 | tmp = { A[7], A[6:0], A[7]}; 64 | ALU_OP_ROR : 65 | tmp = { A[0], A[0], A[7:1]}; 66 | ALU_OP_RCL : 67 | tmp = { A[7], A[6:0], CF}; 68 | ALU_OP_RCR : 69 | tmp = { A[0], CF, A[7:1]}; 70 | endcase 71 | 72 | CF <= tmp[8]; 73 | ZF <= tmp[7:0] == 0; 74 | SF <= tmp[7]; 75 | 76 | result <= tmp[7:0]; 77 | end 78 | endmodule 79 | 80 | -------------------------------------------------------------------------------- /apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = go-board 3 | 4 | -------------------------------------------------------------------------------- /boot.mem: -------------------------------------------------------------------------------- 1 | 00 2 | 00 3 | 00 4 | 00 5 | 00 6 | 00 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | 00 13 | 00 14 | 00 15 | 00 16 | 00 17 | 00 18 | 00 19 | 00 20 | 00 21 | 00 22 | 00 23 | 00 24 | 00 25 | 00 26 | 00 27 | 00 28 | 00 29 | 00 30 | 00 31 | 00 32 | 00 33 | 00 34 | 00 35 | 00 36 | 00 37 | 00 38 | 00 39 | 00 40 | 00 41 | 00 42 | 00 43 | 00 44 | 00 45 | 00 46 | 00 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2847 | 00 2848 | 00 2849 | 00 2850 | 00 2851 | 00 2852 | 00 2853 | 00 2854 | 00 2855 | 00 2856 | 00 2857 | 00 2858 | 00 2859 | 00 2860 | 00 2861 | 00 2862 | 00 2863 | 00 2864 | 00 2865 | 00 2866 | 00 2867 | 00 2868 | 00 2869 | 00 2870 | 00 2871 | 00 2872 | 00 2873 | 00 2874 | 00 2875 | 00 2876 | 00 2877 | 00 2878 | 00 2879 | 00 2880 | 00 2881 | 00 2882 | 00 2883 | 00 2884 | 00 2885 | 00 2886 | 00 2887 | 00 2888 | 00 2889 | 00 2890 | 00 2891 | 00 2892 | 00 2893 | 00 2894 | 00 2895 | 00 2896 | 00 2897 | 00 2898 | 00 2899 | 00 2900 | 00 2901 | 00 2902 | 00 2903 | 00 2904 | 00 2905 | 00 2906 | 00 2907 | 00 2908 | 00 2909 | 00 2910 | 00 2911 | 00 2912 | 00 2913 | 00 2914 | 00 2915 | 00 2916 | 00 2917 | 00 2918 | 00 2919 | 00 2920 | 00 2921 | 00 2922 | 00 2923 | 00 2924 | 00 2925 | 00 2926 | 00 2927 | 00 2928 | 00 2929 | 00 2930 | 00 2931 | 00 2932 | 00 2933 | 00 2934 | 00 2935 | 00 2936 | 00 2937 | 00 2938 | 00 2939 | 00 2940 | 00 2941 | 00 2942 | 00 2943 | 00 2944 | 00 2945 | 00 2946 | 00 2947 | 00 2948 | 00 2949 | 00 2950 | 00 2951 | 00 2952 | 00 2953 | 00 2954 | 00 2955 | 00 2956 | 00 2957 | 00 2958 | 00 2959 | 00 2960 | 00 2961 | 00 2962 | 00 2963 | 00 2964 | 00 2965 | 00 2966 | 00 2967 | 00 2968 | 00 2969 | 00 2970 | 00 2971 | 00 2972 | 00 2973 | 00 2974 | 00 2975 | 00 2976 | 00 2977 | 00 2978 | 00 2979 | 00 2980 | 00 2981 | 00 2982 | 00 2983 | 00 2984 | 00 2985 | 00 2986 | 00 2987 | 00 2988 | 00 2989 | 00 2990 | 00 2991 | 00 2992 | 00 2993 | 00 2994 | 00 2995 | 00 2996 | 00 2997 | 00 2998 | 00 2999 | 00 3000 | 00 3001 | 00 3002 | 00 3003 | 00 3004 | 00 3005 | 00 3006 | 00 3007 | 00 3008 | 00 3009 | 00 3010 | 00 3011 | 00 3012 | 00 3013 | 00 3014 | 00 3015 | 00 3016 | 00 3017 | 00 3018 | 00 3019 | 00 3020 | 00 3021 | 00 3022 | 00 3023 | 00 3024 | 00 3025 | 00 3026 | 00 3027 | 00 3028 | 00 3029 | 00 3030 | 00 3031 | 00 3032 | 00 3033 | 00 3034 | 00 3035 | 00 3036 | 00 3037 | 00 3038 | 00 3039 | 00 3040 | 00 3041 | 00 3042 | 00 3043 | 00 3044 | 00 3045 | 00 3046 | 00 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3147 | 00 3148 | 00 3149 | 00 3150 | 00 3151 | 00 3152 | 00 3153 | 00 3154 | 00 3155 | 00 3156 | 00 3157 | 00 3158 | 00 3159 | 00 3160 | 00 3161 | 00 3162 | 00 3163 | 00 3164 | 00 3165 | 00 3166 | 00 3167 | 00 3168 | 00 3169 | 00 3170 | 00 3171 | 00 3172 | 00 3173 | 00 3174 | 00 3175 | 00 3176 | 00 3177 | 00 3178 | 00 3179 | 00 3180 | 00 3181 | 00 3182 | 00 3183 | 00 3184 | 00 3185 | 00 3186 | 00 3187 | 00 3188 | 00 3189 | 00 3190 | 00 3191 | 00 3192 | 00 3193 | 00 3194 | 00 3195 | 00 3196 | 00 3197 | 00 3198 | 00 3199 | 00 3200 | 00 3201 | 00 3202 | 00 3203 | 00 3204 | 00 3205 | 00 3206 | 00 3207 | 00 3208 | 00 3209 | 00 3210 | 00 3211 | 00 3212 | 00 3213 | 00 3214 | 00 3215 | 00 3216 | 00 3217 | 00 3218 | 00 3219 | 00 3220 | 00 3221 | 00 3222 | 00 3223 | 00 3224 | 00 3225 | 00 3226 | 00 3227 | 00 3228 | 00 3229 | 00 3230 | 00 3231 | 00 3232 | 00 3233 | 00 3234 | 00 3235 | 00 3236 | 00 3237 | 00 3238 | 00 3239 | 00 3240 | 00 3241 | 00 3242 | 00 3243 | 00 3244 | 00 3245 | 00 3246 | 00 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3447 | 00 3448 | 00 3449 | 00 3450 | 00 3451 | 00 3452 | 00 3453 | 00 3454 | 00 3455 | 00 3456 | 00 3457 | 00 3458 | 00 3459 | 00 3460 | 00 3461 | 00 3462 | 00 3463 | 00 3464 | 00 3465 | 00 3466 | 00 3467 | 00 3468 | 00 3469 | 00 3470 | 00 3471 | 00 3472 | 00 3473 | 00 3474 | 00 3475 | 00 3476 | 00 3477 | 00 3478 | 00 3479 | 00 3480 | 00 3481 | 00 3482 | 00 3483 | 00 3484 | 00 3485 | 00 3486 | 00 3487 | 00 3488 | 00 3489 | 00 3490 | 00 3491 | 00 3492 | 00 3493 | 00 3494 | 00 3495 | 00 3496 | 00 3497 | 00 3498 | 00 3499 | 00 3500 | 00 3501 | 00 3502 | 00 3503 | 00 3504 | 00 3505 | 00 3506 | 00 3507 | 00 3508 | 00 3509 | 00 3510 | 00 3511 | 00 3512 | 00 3513 | 00 3514 | 00 3515 | 00 3516 | 00 3517 | 00 3518 | 00 3519 | 00 3520 | 00 3521 | 00 3522 | 00 3523 | 00 3524 | 00 3525 | 00 3526 | 00 3527 | 00 3528 | 00 3529 | 00 3530 | 00 3531 | 00 3532 | 00 3533 | 00 3534 | 00 3535 | 00 3536 | 00 3537 | 00 3538 | 00 3539 | 00 3540 | 00 3541 | 00 3542 | 00 3543 | 00 3544 | 00 3545 | 00 3546 | 00 3547 | 00 3548 | 00 3549 | 00 3550 | 00 3551 | 00 3552 | 00 3553 | 00 3554 | 00 3555 | 00 3556 | 00 3557 | 00 3558 | 00 3559 | 00 3560 | 00 3561 | 00 3562 | 00 3563 | 00 3564 | 00 3565 | 00 3566 | 00 3567 | 00 3568 | 00 3569 | 00 3570 | 00 3571 | 00 3572 | 00 3573 | 00 3574 | 00 3575 | 00 3576 | 00 3577 | 00 3578 | 00 3579 | 00 3580 | 00 3581 | 00 3582 | 00 3583 | 00 3584 | 00 3585 | 00 3586 | 00 3587 | 00 3588 | 00 3589 | 00 3590 | 00 3591 | 00 3592 | 00 3593 | 00 3594 | 00 3595 | 00 3596 | 00 3597 | 00 3598 | 00 3599 | 00 3600 | 00 3601 | 00 3602 | 00 3603 | 00 3604 | 00 3605 | 00 3606 | 00 3607 | 00 3608 | 00 3609 | 00 3610 | 00 3611 | 00 3612 | 00 3613 | 00 3614 | 00 3615 | 00 3616 | 00 3617 | 00 3618 | 00 3619 | 00 3620 | 00 3621 | 00 3622 | 00 3623 | 00 3624 | 00 3625 | 00 3626 | 00 3627 | 00 3628 | 00 3629 | 00 3630 | 00 3631 | 00 3632 | 00 3633 | 00 3634 | 00 3635 | 00 3636 | 00 3637 | 00 3638 | 00 3639 | 00 3640 | 00 3641 | 00 3642 | 00 3643 | 00 3644 | 00 3645 | 00 3646 | 00 3647 | 00 3648 | 00 3649 | 00 3650 | 00 3651 | 00 3652 | 00 3653 | 00 3654 | 00 3655 | 00 3656 | 00 3657 | 00 3658 | 00 3659 | 00 3660 | 00 3661 | 00 3662 | 00 3663 | 00 3664 | 00 3665 | 00 3666 | 00 3667 | 00 3668 | 00 3669 | 00 3670 | 00 3671 | 00 3672 | 00 3673 | 00 3674 | 00 3675 | 00 3676 | 00 3677 | 00 3678 | 00 3679 | 00 3680 | 00 3681 | 00 3682 | 00 3683 | 00 3684 | 00 3685 | 00 3686 | 00 3687 | 00 3688 | 00 3689 | 00 3690 | 00 3691 | 00 3692 | 00 3693 | 00 3694 | 00 3695 | 00 3696 | 00 3697 | 00 3698 | 00 3699 | 00 3700 | 00 3701 | 00 3702 | 00 3703 | 00 3704 | 00 3705 | 00 3706 | 00 3707 | 00 3708 | 00 3709 | 00 3710 | 00 3711 | 00 3712 | 00 3713 | 00 3714 | 00 3715 | 00 3716 | 00 3717 | 00 3718 | 00 3719 | 00 3720 | 00 3721 | 00 3722 | 00 3723 | 00 3724 | 00 3725 | 00 3726 | 00 3727 | 00 3728 | 00 3729 | 00 3730 | 00 3731 | 00 3732 | 00 3733 | 00 3734 | 00 3735 | 00 3736 | 00 3737 | 00 3738 | 00 3739 | 00 3740 | 00 3741 | 00 3742 | 00 3743 | 00 3744 | 00 3745 | 00 3746 | 00 3747 | 00 3748 | 00 3749 | 00 3750 | 00 3751 | 00 3752 | 00 3753 | 00 3754 | 00 3755 | 00 3756 | 00 3757 | 00 3758 | 00 3759 | 00 3760 | 00 3761 | 00 3762 | 00 3763 | 00 3764 | 00 3765 | 00 3766 | 00 3767 | 00 3768 | 00 3769 | 00 3770 | 00 3771 | 00 3772 | 00 3773 | 00 3774 | 00 3775 | 00 3776 | 00 3777 | 00 3778 | 00 3779 | 00 3780 | 00 3781 | 00 3782 | 00 3783 | 00 3784 | 00 3785 | 00 3786 | 00 3787 | 00 3788 | 00 3789 | 00 3790 | 00 3791 | 00 3792 | 00 3793 | 00 3794 | 00 3795 | 00 3796 | 00 3797 | 00 3798 | 00 3799 | 00 3800 | 00 3801 | 00 3802 | 00 3803 | 00 3804 | 00 3805 | 00 3806 | 00 3807 | 00 3808 | 00 3809 | 00 3810 | 00 3811 | 00 3812 | 00 3813 | 00 3814 | 00 3815 | 00 3816 | 00 3817 | 00 3818 | 00 3819 | 00 3820 | 00 3821 | 00 3822 | 00 3823 | 00 3824 | 00 3825 | 00 3826 | 00 3827 | 00 3828 | 00 3829 | 00 3830 | 00 3831 | 00 3832 | 00 3833 | 00 3834 | 00 3835 | 00 3836 | 00 3837 | 00 3838 | 00 3839 | 00 3840 | 00 3841 | 00 3842 | 00 3843 | 00 3844 | 00 3845 | 00 3846 | 00 3847 | 00 3848 | 00 3849 | 00 3850 | 00 3851 | 00 3852 | 00 3853 | 00 3854 | 00 3855 | 00 3856 | 00 3857 | 00 3858 | 00 3859 | 00 3860 | 00 3861 | 00 3862 | 00 3863 | 00 3864 | 00 3865 | 00 3866 | 00 3867 | 00 3868 | 00 3869 | 00 3870 | 00 3871 | 00 3872 | 00 3873 | 00 3874 | 00 3875 | 00 3876 | 00 3877 | 00 3878 | 00 3879 | 00 3880 | 00 3881 | 00 3882 | 00 3883 | 00 3884 | 00 3885 | 00 3886 | 00 3887 | 00 3888 | 00 3889 | 00 3890 | 00 3891 | 00 3892 | 00 3893 | 00 3894 | 00 3895 | 00 3896 | 00 3897 | 00 3898 | 00 3899 | 00 3900 | 00 3901 | 00 3902 | 00 3903 | 00 3904 | 00 3905 | 00 3906 | 00 3907 | 00 3908 | 00 3909 | 00 3910 | 00 3911 | 00 3912 | 00 3913 | 00 3914 | 00 3915 | 00 3916 | 00 3917 | 00 3918 | 00 3919 | 00 3920 | 00 3921 | 00 3922 | 00 3923 | 00 3924 | 00 3925 | 00 3926 | 00 3927 | 00 3928 | 00 3929 | 00 3930 | 00 3931 | 00 3932 | 00 3933 | 00 3934 | 00 3935 | 00 3936 | 00 3937 | 00 3938 | 00 3939 | 00 3940 | 00 3941 | 00 3942 | 00 3943 | 00 3944 | 00 3945 | 00 3946 | 00 3947 | 00 3948 | 00 3949 | 00 3950 | 00 3951 | 00 3952 | 00 3953 | 00 3954 | 00 3955 | 00 3956 | 00 3957 | 00 3958 | 00 3959 | 00 3960 | 00 3961 | 00 3962 | 00 3963 | 00 3964 | 00 3965 | 00 3966 | 00 3967 | 00 3968 | 00 3969 | 00 3970 | 00 3971 | 00 3972 | 00 3973 | 00 3974 | 00 3975 | 00 3976 | 00 3977 | 00 3978 | 00 3979 | 00 3980 | 00 3981 | 00 3982 | 00 3983 | 00 3984 | 00 3985 | 00 3986 | 00 3987 | 00 3988 | 00 3989 | 00 3990 | 00 3991 | 00 3992 | 00 3993 | 00 3994 | 00 3995 | 00 3996 | 00 3997 | 00 3998 | 00 3999 | 00 4000 | 00 4001 | 00 4002 | 00 4003 | 00 4004 | 00 4005 | 00 4006 | 00 4007 | 00 4008 | 00 4009 | 00 4010 | 00 4011 | 00 4012 | 00 4013 | 00 4014 | 00 4015 | 00 4016 | 00 4017 | 00 4018 | 00 4019 | 00 4020 | 00 4021 | 00 4022 | 00 4023 | 00 4024 | 00 4025 | 00 4026 | 00 4027 | 00 4028 | 00 4029 | 00 4030 | 00 4031 | 00 4032 | 00 4033 | 00 4034 | 00 4035 | 00 4036 | 00 4037 | 00 4038 | 00 4039 | 00 4040 | 00 4041 | 00 4042 | 00 4043 | 00 4044 | 00 4045 | 00 4046 | 00 4047 | 00 4048 | 00 4049 | 00 4050 | 00 4051 | 00 4052 | 00 4053 | 00 4054 | 00 4055 | 00 4056 | 00 4057 | 00 4058 | 00 4059 | 00 4060 | 00 4061 | 00 4062 | 00 4063 | 00 4064 | 00 4065 | 00 4066 | 00 4067 | 00 4068 | 00 4069 | 00 4070 | 00 4071 | 00 4072 | 00 4073 | 00 4074 | 00 4075 | 00 4076 | 00 4077 | 00 4078 | 00 4079 | 00 4080 | 00 4081 | 00 4082 | 00 4083 | 00 4084 | 00 4085 | 00 4086 | 00 4087 | 00 4088 | 00 4089 | 00 4090 | 00 4091 | 00 4092 | 00 4093 | 00 4094 | 00 4095 | 00 4096 | 00 4097 | -------------------------------------------------------------------------------- /copy_boot_mem.sh: -------------------------------------------------------------------------------- 1 | cp $FILES_ROOT/boot.mem $WORK_ROOT/boot.mem 2 | -------------------------------------------------------------------------------- /grom8.core: -------------------------------------------------------------------------------- 1 | CAPI=1 2 | [main] 3 | name = ::grom8:0 4 | backend = icestorm 5 | simulators = icarus isim modelsim 6 | 7 | [fileset rtl] 8 | files = 9 | grom_top.v 10 | hex_to_7seg.v 11 | grom_computer.v 12 | ram_memory.v 13 | grom_cpu.v 14 | alu.v 15 | boot.mem[is_include_file] 16 | file_type = verilogSource 17 | 18 | [fileset rtl_tb] 19 | files = grom_computer_tb.v[file_type=verilogSource] 20 | usage = sim 21 | 22 | [fileset contraints] 23 | files = Go_Board_Constraints.pcf[file_type=PCF] 24 | 25 | [icestorm] 26 | top_module = grom_top 27 | yosys_synth_options = -abc2 28 | arachne_pnr_options = -d 1k -P vq100 29 | 30 | [simulator] 31 | toplevel = grom_computer_tb 32 | 33 | [scripts] 34 | pre_build_scripts = copy_boot_mem.sh 35 | pre_synth_scripts = copy_boot_mem.sh 36 | 37 | -------------------------------------------------------------------------------- /grom8.ice: -------------------------------------------------------------------------------- 1 | { 2 | "version": "1.1", 3 | "package": { 4 | "name": "Grom-8", 5 | "version": "1.0", 6 | "description": "Grom-8 CPU", 7 | "author": "Miodrag Milanovic", 8 | "image": "" 9 | }, 10 | "design": { 11 | "board": "go-board", 12 | "graph": { 13 | "blocks": [ 14 | { 15 | "id": "bdb8d2d8-7cef-4b5f-b70d-2e12d75d6818", 16 | "type": "basic.input", 17 | "data": { 18 | "name": "RESET", 19 | "pins": [ 20 | { 21 | "index": "0", 22 | "name": "SW1", 23 | "value": "53" 24 | } 25 | ], 26 | "virtual": false, 27 | "clock": false 28 | }, 29 | "position": { 30 | "x": -24, 31 | "y": -80 32 | } 33 | }, 34 | { 35 | "id": "6f8327c5-f293-4e30-b5ae-624e40c04225", 36 | "type": "basic.output", 37 | "data": { 38 | "name": "HALTLED", 39 | "pins": [ 40 | { 41 | "index": "0", 42 | "name": "LED1", 43 | "value": "56" 44 | } 45 | ], 46 | "virtual": false 47 | }, 48 | "position": { 49 | "x": 336, 50 | "y": 64 51 | } 52 | }, 53 | { 54 | "id": "5e7621b5-809d-4478-9b4e-65071a6c8daa", 55 | "type": "basic.output", 56 | "data": { 57 | "name": "S1", 58 | "range": "[6:0]", 59 | "pins": [ 60 | { 61 | "index": "6", 62 | "name": "S1_A", 63 | "value": "3" 64 | }, 65 | { 66 | "index": "5", 67 | "name": "S1_B", 68 | "value": "4" 69 | }, 70 | { 71 | "index": "4", 72 | "name": "S1_C", 73 | "value": "93" 74 | }, 75 | { 76 | "index": "3", 77 | "name": "S1_D", 78 | "value": "91" 79 | }, 80 | { 81 | "index": "2", 82 | "name": "S1_E", 83 | "value": "90" 84 | }, 85 | { 86 | "index": "1", 87 | "name": "S1_F", 88 | "value": "1" 89 | }, 90 | { 91 | "index": "0", 92 | "name": "S1_G", 93 | "value": "2" 94 | } 95 | ], 96 | "virtual": false 97 | }, 98 | "position": { 99 | "x": 1680, 100 | "y": 80 101 | } 102 | }, 103 | { 104 | "id": "021cb0ba-e841-4d9a-bc44-67810b81d710", 105 | "type": "basic.output", 106 | "data": { 107 | "name": "S2", 108 | "range": "[6:0]", 109 | "pins": [ 110 | { 111 | "index": "6", 112 | "name": "S2_A", 113 | "value": "100" 114 | }, 115 | { 116 | "index": "5", 117 | "name": "S2_B", 118 | "value": "99" 119 | }, 120 | { 121 | "index": "4", 122 | "name": "S2_C", 123 | "value": "97" 124 | }, 125 | { 126 | "index": "3", 127 | "name": "S2_D", 128 | "value": "95" 129 | }, 130 | { 131 | "index": "2", 132 | "name": "S2_E", 133 | "value": "94" 134 | }, 135 | { 136 | "index": "1", 137 | "name": "S2_F", 138 | "value": "8" 139 | }, 140 | { 141 | "index": "0", 142 | "name": "S2_G", 143 | "value": "96" 144 | } 145 | ], 146 | "virtual": false 147 | }, 148 | "position": { 149 | "x": 1680, 150 | "y": 360 151 | } 152 | }, 153 | { 154 | "id": "1d9f62e8-b997-4346-8e61-eba916c67862", 155 | "type": "basic.code", 156 | "data": { 157 | "code": " reg [7:0] display_out = 8'h12;\r\n \r\n always @(posedge clk)\r\n\tbegin\r\n\t\tif(ioreq==1 && we==1)\r\n\t\tbegin\r\n\t\t\tdisplay_out <= data_in;\r\n\t\tend\r\n\tend", 158 | "params": [], 159 | "ports": { 160 | "in": [ 161 | { 162 | "name": "clk" 163 | }, 164 | { 165 | "name": "ioreq" 166 | }, 167 | { 168 | "name": "we" 169 | }, 170 | { 171 | "name": "data_in", 172 | "range": "[7:0]", 173 | "size": 8 174 | } 175 | ], 176 | "out": [ 177 | { 178 | "name": "display_out", 179 | "range": "[7:0]", 180 | "size": 8 181 | } 182 | ] 183 | } 184 | }, 185 | "position": { 186 | "x": 592, 187 | "y": 264 188 | }, 189 | "size": { 190 | "width": 400, 191 | "height": 176 192 | } 193 | }, 194 | { 195 | "id": "f8016266-b629-4008-b686-0fe84a768cf5", 196 | "type": "basic.code", 197 | "data": { 198 | "code": "reg [7:0] data_out;\r\nreg [7:0] store[0:4095];\r\n\r\ninitial\r\nbegin\r\n store[0] <= 8'b11100001; // MOV DS,2\r\n store[1] <= 8'b00000010; //\r\n store[2] <= 8'b01010100; // LOAD R1,[R0]\r\n store[3] <= 8'b00110001; // INC R1\r\n store[4] <= 8'b00110001; // INC R1\r\n store[5] <= 8'b01100001; // STORE [R0],R1\r\n store[6] <= 8'b11010001; // OUT [0],R1\r\n store[7] <= 8'b00000000; //\r\n store[8] <= 8'b01111111; // HLT\r\nend\r\n\r\nalways @(posedge clk)\r\nif (we)\r\n store[addr] <= data_in;\r\nelse\r\n data_out <= store[addr];", 199 | "params": [], 200 | "ports": { 201 | "in": [ 202 | { 203 | "name": "clk" 204 | }, 205 | { 206 | "name": "addr", 207 | "range": "[11:0]", 208 | "size": 12 209 | }, 210 | { 211 | "name": "data_in", 212 | "range": "[7:0]", 213 | "size": 8 214 | }, 215 | { 216 | "name": "we" 217 | } 218 | ], 219 | "out": [ 220 | { 221 | "name": "data_out", 222 | "range": "[7:0]", 223 | "size": 8 224 | } 225 | ] 226 | } 227 | }, 228 | "position": { 229 | "x": 1136, 230 | "y": -208 231 | }, 232 | "size": { 233 | "width": 464, 234 | "height": 352 235 | } 236 | }, 237 | { 238 | "id": "b511a537-abcf-4dd2-9c5e-ad3844607914", 239 | "type": "32200dc0915d45d6ec035bcec61c8472f0cc7b88", 240 | "position": { 241 | "x": 664, 242 | "y": 24 243 | }, 244 | "size": { 245 | "width": 96, 246 | "height": 64 247 | } 248 | }, 249 | { 250 | "id": "05a21837-18d6-40bb-8a04-30c0da0a2f97", 251 | "type": "11a6f454705778e2f00adba4e5b28dcd9411bc8f", 252 | "position": { 253 | "x": 840, 254 | "y": 8 255 | }, 256 | "size": { 257 | "width": 96, 258 | "height": 64 259 | } 260 | }, 261 | { 262 | "id": "4052d141-b548-4386-bf3e-5bdb814da8f8", 263 | "type": "f74ad96c4881fd66d8a66099b6a383f13790bde7", 264 | "position": { 265 | "x": 1240, 266 | "y": 304 267 | }, 268 | "size": { 269 | "width": 96, 270 | "height": 64 271 | } 272 | }, 273 | { 274 | "id": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 275 | "type": "58213494ca3694cf7d54a3aa8ef34196dc2fa7a9", 276 | "position": { 277 | "x": 192, 278 | "y": -128 279 | }, 280 | "size": { 281 | "width": 96, 282 | "height": 160 283 | } 284 | } 285 | ], 286 | "wires": [ 287 | { 288 | "source": { 289 | "block": "05a21837-18d6-40bb-8a04-30c0da0a2f97", 290 | "port": "664caf9e-5f40-4df4-800a-b626af702e62" 291 | }, 292 | "target": { 293 | "block": "f8016266-b629-4008-b686-0fe84a768cf5", 294 | "port": "we" 295 | }, 296 | "vertices": [ 297 | { 298 | "x": 1000, 299 | "y": 48 300 | } 301 | ] 302 | }, 303 | { 304 | "source": { 305 | "block": "b511a537-abcf-4dd2-9c5e-ad3844607914", 306 | "port": "664caf9e-5f40-4df4-800a-b626af702e62" 307 | }, 308 | "target": { 309 | "block": "05a21837-18d6-40bb-8a04-30c0da0a2f97", 310 | "port": "97b51945-d716-4b6c-9db9-970d08541249" 311 | } 312 | }, 313 | { 314 | "source": { 315 | "block": "1d9f62e8-b997-4346-8e61-eba916c67862", 316 | "port": "display_out" 317 | }, 318 | "target": { 319 | "block": "4052d141-b548-4386-bf3e-5bdb814da8f8", 320 | "port": "d3746d71-9a02-4b67-8de3-1e6db572a1b6" 321 | }, 322 | "size": 8 323 | }, 324 | { 325 | "source": { 326 | "block": "4052d141-b548-4386-bf3e-5bdb814da8f8", 327 | "port": "a214789b-db10-4525-ba80-20c320c62a32" 328 | }, 329 | "target": { 330 | "block": "5e7621b5-809d-4478-9b4e-65071a6c8daa", 331 | "port": "in" 332 | }, 333 | "size": 7 334 | }, 335 | { 336 | "source": { 337 | "block": "4052d141-b548-4386-bf3e-5bdb814da8f8", 338 | "port": "0a33152f-2efc-4333-a306-35ed1b32b5c9" 339 | }, 340 | "target": { 341 | "block": "021cb0ba-e841-4d9a-bc44-67810b81d710", 342 | "port": "in" 343 | }, 344 | "size": 7 345 | }, 346 | { 347 | "source": { 348 | "block": "bdb8d2d8-7cef-4b5f-b70d-2e12d75d6818", 349 | "port": "out" 350 | }, 351 | "target": { 352 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 353 | "port": "7137e9cd-16ae-4d4e-96e9-39ee108889b0" 354 | } 355 | }, 356 | { 357 | "source": { 358 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 359 | "port": "ef426d56-bc16-4230-a54f-cc61ac61cfb5" 360 | }, 361 | "target": { 362 | "block": "b511a537-abcf-4dd2-9c5e-ad3844607914", 363 | "port": "18c2ebc7-5152-439c-9b3f-851c59bac834" 364 | } 365 | }, 366 | { 367 | "source": { 368 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 369 | "port": "cc25dd56-f44c-4ae1-abd5-20df6f53ff18" 370 | }, 371 | "target": { 372 | "block": "05a21837-18d6-40bb-8a04-30c0da0a2f97", 373 | "port": "18c2ebc7-5152-439c-9b3f-851c59bac834" 374 | } 375 | }, 376 | { 377 | "source": { 378 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 379 | "port": "cc25dd56-f44c-4ae1-abd5-20df6f53ff18" 380 | }, 381 | "target": { 382 | "block": "1d9f62e8-b997-4346-8e61-eba916c67862", 383 | "port": "we" 384 | }, 385 | "vertices": [ 386 | { 387 | "x": 480, 388 | "y": 168 389 | } 390 | ] 391 | }, 392 | { 393 | "source": { 394 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 395 | "port": "2ccf9cd7-4d75-49e7-bafb-0fb3522d58a0" 396 | }, 397 | "target": { 398 | "block": "6f8327c5-f293-4e30-b5ae-624e40c04225", 399 | "port": "in" 400 | } 401 | }, 402 | { 403 | "source": { 404 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 405 | "port": "ef426d56-bc16-4230-a54f-cc61ac61cfb5" 406 | }, 407 | "target": { 408 | "block": "1d9f62e8-b997-4346-8e61-eba916c67862", 409 | "port": "ioreq" 410 | }, 411 | "vertices": [ 412 | { 413 | "x": 520, 414 | "y": 208 415 | } 416 | ] 417 | }, 418 | { 419 | "source": { 420 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 421 | "port": "60084d58-17f4-4238-a8eb-1b3dc4f1bb84" 422 | }, 423 | "target": { 424 | "block": "f8016266-b629-4008-b686-0fe84a768cf5", 425 | "port": "addr" 426 | }, 427 | "vertices": [ 428 | { 429 | "x": 1048, 430 | "y": -72 431 | } 432 | ], 433 | "size": 12 434 | }, 435 | { 436 | "source": { 437 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 438 | "port": "612403e6-8ef2-4c0e-84a0-875ff8805a03" 439 | }, 440 | "target": { 441 | "block": "f8016266-b629-4008-b686-0fe84a768cf5", 442 | "port": "data_in" 443 | }, 444 | "vertices": [ 445 | { 446 | "x": 1000, 447 | "y": -32 448 | } 449 | ], 450 | "size": 8 451 | }, 452 | { 453 | "source": { 454 | "block": "f8016266-b629-4008-b686-0fe84a768cf5", 455 | "port": "data_out" 456 | }, 457 | "target": { 458 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 459 | "port": "0a1ce504-dd8a-48e0-98c5-05df511d2fcb" 460 | }, 461 | "vertices": [ 462 | { 463 | "x": 104, 464 | "y": -248 465 | } 466 | ], 467 | "size": 8 468 | }, 469 | { 470 | "source": { 471 | "block": "61c26392-d6cc-4b30-b48e-038ea0413bb9", 472 | "port": "612403e6-8ef2-4c0e-84a0-875ff8805a03" 473 | }, 474 | "target": { 475 | "block": "1d9f62e8-b997-4346-8e61-eba916c67862", 476 | "port": "data_in" 477 | }, 478 | "vertices": [ 479 | { 480 | "x": 448, 481 | "y": 176 482 | } 483 | ], 484 | "size": 8 485 | } 486 | ] 487 | }, 488 | "state": { 489 | "pan": { 490 | "x": 186.3237, 491 | "y": 307.3236 492 | }, 493 | "zoom": 0.9627 494 | } 495 | }, 496 | "dependencies": { 497 | "32200dc0915d45d6ec035bcec61c8472f0cc7b88": { 498 | "package": { 499 | "name": "NOT", 500 | "version": "1.0.0", 501 | "description": "NOT logic gate", 502 | "author": "Jesús Arroyo", 503 | "image": "%3Csvg%20xmlns=%22http://www.w3.org/2000/svg%22%20width=%2291.33%22%20height=%2245.752%22%20version=%221%22%3E%3Cpath%20d=%22M0%2020.446h27v2H0zM70.322%2020.447h15.3v2h-15.3z%22/%3E%3Cpath%20d=%22M66.05%2026.746c-2.9%200-5.3-2.4-5.3-5.3s2.4-5.3%205.3-5.3%205.3%202.4%205.3%205.3-2.4%205.3-5.3%205.3zm0-8.6c-1.8%200-3.3%201.5-3.3%203.3%200%201.8%201.5%203.3%203.3%203.3%201.8%200%203.3-1.5%203.3-3.3%200-1.8-1.5-3.3-3.3-3.3z%22/%3E%3Cpath%20d=%22M25.962%202.563l33.624%2018.883L25.962%2040.33V2.563z%22%20fill=%22none%22%20stroke=%22#000%22%20stroke-width=%223%22/%3E%3C/svg%3E" 504 | }, 505 | "design": { 506 | "graph": { 507 | "blocks": [ 508 | { 509 | "id": "5365ed8c-e5db-4445-938f-8d689830ea5c", 510 | "type": "basic.code", 511 | "data": { 512 | "code": "// NOT logic gate\n\nassign c = ~ a;", 513 | "params": [], 514 | "ports": { 515 | "in": [ 516 | { 517 | "name": "a" 518 | } 519 | ], 520 | "out": [ 521 | { 522 | "name": "c" 523 | } 524 | ] 525 | } 526 | }, 527 | "position": { 528 | "x": 256, 529 | "y": 48 530 | } 531 | }, 532 | { 533 | "id": "18c2ebc7-5152-439c-9b3f-851c59bac834", 534 | "type": "basic.input", 535 | "data": { 536 | "name": "" 537 | }, 538 | "position": { 539 | "x": 64, 540 | "y": 144 541 | } 542 | }, 543 | { 544 | "id": "664caf9e-5f40-4df4-800a-b626af702e62", 545 | "type": "basic.output", 546 | "data": { 547 | "name": "" 548 | }, 549 | "position": { 550 | "x": 752, 551 | "y": 144 552 | } 553 | } 554 | ], 555 | "wires": [ 556 | { 557 | "source": { 558 | "block": "18c2ebc7-5152-439c-9b3f-851c59bac834", 559 | "port": "out" 560 | }, 561 | "target": { 562 | "block": "5365ed8c-e5db-4445-938f-8d689830ea5c", 563 | "port": "a" 564 | } 565 | }, 566 | { 567 | "source": { 568 | "block": "5365ed8c-e5db-4445-938f-8d689830ea5c", 569 | "port": "c" 570 | }, 571 | "target": { 572 | "block": "664caf9e-5f40-4df4-800a-b626af702e62", 573 | "port": "in" 574 | } 575 | } 576 | ] 577 | }, 578 | "state": { 579 | "pan": { 580 | "x": 0, 581 | "y": 0 582 | }, 583 | "zoom": 1 584 | } 585 | } 586 | }, 587 | "11a6f454705778e2f00adba4e5b28dcd9411bc8f": { 588 | "package": { 589 | "name": "AND", 590 | "version": "1.0.0", 591 | "description": "AND logic gate", 592 | "author": "Jesús Arroyo", 593 | "image": "%3Csvg%20xmlns=%22http://www.w3.org/2000/svg%22%20viewBox=%22-252%20400.9%2090%2040%22%3E%3Cpath%20d=%22M-252%20409.9h26v2h-26zM-252%20429.9h27v2h-27z%22/%3E%3Cpath%20d=%22M-227%20400.9v39.9h20.4c11.3%200%2020-9%2020-20s-8.7-20-20-20H-227zm2.9%202.8h17.6c9.8%200%2016.7%207.6%2016.7%2017.1%200%209.5-7.4%2017.1-17.1%2017.1H-224c-.1.1-.1-34.2-.1-34.2z%22/%3E%3Cpath%20d=%22M-187.911%20419.9H-162v2h-25.911z%22/%3E%3C/svg%3E" 594 | }, 595 | "design": { 596 | "graph": { 597 | "blocks": [ 598 | { 599 | "id": "00925b04-5004-4307-a737-fa4e97c8b6ab", 600 | "type": "basic.code", 601 | "data": { 602 | "code": "// AND logic gate\n\nassign c = a & b;", 603 | "params": [], 604 | "ports": { 605 | "in": [ 606 | { 607 | "name": "a" 608 | }, 609 | { 610 | "name": "b" 611 | } 612 | ], 613 | "out": [ 614 | { 615 | "name": "c" 616 | } 617 | ] 618 | } 619 | }, 620 | "position": { 621 | "x": 256, 622 | "y": 48 623 | } 624 | }, 625 | { 626 | "id": "18c2ebc7-5152-439c-9b3f-851c59bac834", 627 | "type": "basic.input", 628 | "data": { 629 | "name": "" 630 | }, 631 | "position": { 632 | "x": 64, 633 | "y": 80 634 | } 635 | }, 636 | { 637 | "id": "664caf9e-5f40-4df4-800a-b626af702e62", 638 | "type": "basic.output", 639 | "data": { 640 | "name": "" 641 | }, 642 | "position": { 643 | "x": 752, 644 | "y": 144 645 | } 646 | }, 647 | { 648 | "id": "97b51945-d716-4b6c-9db9-970d08541249", 649 | "type": "basic.input", 650 | "data": { 651 | "name": "" 652 | }, 653 | "position": { 654 | "x": 64, 655 | "y": 208 656 | } 657 | } 658 | ], 659 | "wires": [ 660 | { 661 | "source": { 662 | "block": "18c2ebc7-5152-439c-9b3f-851c59bac834", 663 | "port": "out" 664 | }, 665 | "target": { 666 | "block": "00925b04-5004-4307-a737-fa4e97c8b6ab", 667 | "port": "a" 668 | } 669 | }, 670 | { 671 | "source": { 672 | "block": "97b51945-d716-4b6c-9db9-970d08541249", 673 | "port": "out" 674 | }, 675 | "target": { 676 | "block": "00925b04-5004-4307-a737-fa4e97c8b6ab", 677 | "port": "b" 678 | } 679 | }, 680 | { 681 | "source": { 682 | "block": "00925b04-5004-4307-a737-fa4e97c8b6ab", 683 | "port": "c" 684 | }, 685 | "target": { 686 | "block": "664caf9e-5f40-4df4-800a-b626af702e62", 687 | "port": "in" 688 | } 689 | } 690 | ] 691 | }, 692 | "state": { 693 | "pan": { 694 | "x": 0, 695 | "y": 0 696 | }, 697 | "zoom": 1 698 | } 699 | } 700 | }, 701 | "f74ad96c4881fd66d8a66099b6a383f13790bde7": { 702 | "package": { 703 | "name": "HEX to 2 x 7seg", 704 | "version": "1.0", 705 | "description": "8-bit value to two 7seg displays", 706 | "author": "Miodrag Milanovic", 707 | "image": "%3Csvg%20xmlns=%22http://www.w3.org/2000/svg%22%20width=%22898.3%22%20height=%22898.3%22%20viewBox=%220%200%20898.3%20898.3%22%3E%3Cpath%20d=%22M120.2%20882.5l433.4-433.3L120.2%2015.8%200%20136l313.2%20313.2L0%20762.3z%22/%3E%3Cpath%20d=%22M344.7%20762.3l120.2%20120.2%20433.4-433.3L464.9%2015.8%20344.7%20136l313.2%20313.2z%22/%3E%3C/svg%3E" 708 | }, 709 | "design": { 710 | "graph": { 711 | "blocks": [ 712 | { 713 | "id": "a214789b-db10-4525-ba80-20c320c62a32", 714 | "type": "basic.output", 715 | "data": { 716 | "name": "Segment1", 717 | "range": "[6:0]", 718 | "size": 7 719 | }, 720 | "position": { 721 | "x": 808, 722 | "y": 136 723 | } 724 | }, 725 | { 726 | "id": "129a3e9c-cee8-4e02-9114-a44a9515fbef", 727 | "type": "basic.input", 728 | "data": { 729 | "name": "clk", 730 | "clock": true 731 | }, 732 | "position": { 733 | "x": 128, 734 | "y": 136 735 | } 736 | }, 737 | { 738 | "id": "d3746d71-9a02-4b67-8de3-1e6db572a1b6", 739 | "type": "basic.input", 740 | "data": { 741 | "name": "input_value", 742 | "range": "[7:0]", 743 | "clock": false, 744 | "size": 8 745 | }, 746 | "position": { 747 | "x": 128, 748 | "y": 328 749 | } 750 | }, 751 | { 752 | "id": "0a33152f-2efc-4333-a306-35ed1b32b5c9", 753 | "type": "basic.output", 754 | "data": { 755 | "name": "Segment2", 756 | "range": "[6:0]", 757 | "size": 7 758 | }, 759 | "position": { 760 | "x": 808, 761 | "y": 328 762 | } 763 | }, 764 | { 765 | "id": "540818d8-c478-45b8-b5af-0fa3f2832ded", 766 | "type": "basic.code", 767 | "data": { 768 | "code": "// @include hex_to_7seg.v\r\n\r\n hex_to_7seg upper_digit\r\n (.i_Clk(clk),\r\n .i_Value(data_input[7:4]),\r\n .o_Segment_A(S1[6]),\r\n .o_Segment_B(S1[5]),\r\n .o_Segment_C(S1[4]),\r\n .o_Segment_D(S1[3]),\r\n .o_Segment_E(S1[2]),\r\n .o_Segment_F(S1[1]),\r\n .o_Segment_G(S1[0]));\r\n\r\n hex_to_7seg lower_digit\r\n (.i_Clk(clk),\r\n .i_Value(data_input[3:0]),\r\n .o_Segment_A(S2[6]),\r\n .o_Segment_B(S2[5]),\r\n .o_Segment_C(S2[4]),\r\n .o_Segment_D(S2[3]),\r\n .o_Segment_E(S2[2]),\r\n .o_Segment_F(S2[1]),\r\n .o_Segment_G(S2[0]));\r\n", 769 | "params": [], 770 | "ports": { 771 | "in": [ 772 | { 773 | "name": "clk" 774 | }, 775 | { 776 | "name": "data_input", 777 | "range": "[7:0]", 778 | "size": 8 779 | } 780 | ], 781 | "out": [ 782 | { 783 | "name": "S1", 784 | "range": "[6:0]", 785 | "size": 7 786 | }, 787 | { 788 | "name": "S2", 789 | "range": "[6:0]", 790 | "size": 7 791 | } 792 | ] 793 | } 794 | }, 795 | "position": { 796 | "x": 376, 797 | "y": 72 798 | }, 799 | "size": { 800 | "width": 352, 801 | "height": 384 802 | } 803 | } 804 | ], 805 | "wires": [ 806 | { 807 | "source": { 808 | "block": "d3746d71-9a02-4b67-8de3-1e6db572a1b6", 809 | "port": "out" 810 | }, 811 | "target": { 812 | "block": "540818d8-c478-45b8-b5af-0fa3f2832ded", 813 | "port": "data_input" 814 | }, 815 | "size": 8 816 | }, 817 | { 818 | "source": { 819 | "block": "540818d8-c478-45b8-b5af-0fa3f2832ded", 820 | "port": "S1" 821 | }, 822 | "target": { 823 | "block": "a214789b-db10-4525-ba80-20c320c62a32", 824 | "port": "in" 825 | }, 826 | "size": 7 827 | }, 828 | { 829 | "source": { 830 | "block": "540818d8-c478-45b8-b5af-0fa3f2832ded", 831 | "port": "S2" 832 | }, 833 | "target": { 834 | "block": "0a33152f-2efc-4333-a306-35ed1b32b5c9", 835 | "port": "in" 836 | }, 837 | "size": 7 838 | }, 839 | { 840 | "source": { 841 | "block": "129a3e9c-cee8-4e02-9114-a44a9515fbef", 842 | "port": "out" 843 | }, 844 | "target": { 845 | "block": "540818d8-c478-45b8-b5af-0fa3f2832ded", 846 | "port": "clk" 847 | } 848 | } 849 | ] 850 | }, 851 | "state": { 852 | "pan": { 853 | "x": -58, 854 | "y": 19 855 | }, 856 | "zoom": 1 857 | } 858 | } 859 | }, 860 | "58213494ca3694cf7d54a3aa8ef34196dc2fa7a9": { 861 | "package": { 862 | "name": "Grom-8 CPU", 863 | "version": "1.0", 864 | "description": "Grom-8 CPU Core", 865 | "author": "Miodrag Milanovic", 866 | "image": "%3Csvg%20height=%22512%22%20viewBox=%220%200%20512%20512%22%20width=%22512%22%20xmlns=%22http://www.w3.org/2000/svg%22%3E%3Cpath%20d=%22M199%20387h-62.218c-.221%200%20.221%200%200%200C91.805%20387%2056%20350.337%2056%20305.36c0-44.977%2036.456-81.537%2081.433-81.537%203.922%200%207.778.222%2011.557.769%2013.941-56.938%2065.316-99.218%20126.554-99.218%2071.961%200%20130.293%2058.319%20130.293%20130.28%200%2010.593-1.264%2020.879-3.661%2030.743%201.212-.091%202.423-.03%203.661-.03%2027.7%200%2050.163%2022.563%2050.163%2050.263S433.537%20387%20405.837%20387H338%22%20fill=%22none%22%20stroke=%22#000%22%20stroke-miterlimit=%2210%22%20stroke-width=%2230%22/%3E%3Cpath%20stroke=%22#000%22%20stroke-linecap=%22round%22%20stroke-miterlimit=%2210%22%20stroke-width=%224%22%20d=%22M286.705%20270.678l-71.022%20100.615%2059.185%2026.633-38.47%2088.53%2082.858-97.408-62.144-35.511z%22/%3E%3C/svg%3E" 867 | }, 868 | "design": { 869 | "graph": { 870 | "blocks": [ 871 | { 872 | "id": "60084d58-17f4-4238-a8eb-1b3dc4f1bb84", 873 | "type": "basic.output", 874 | "data": { 875 | "name": "addr", 876 | "range": "[11:0]", 877 | "size": 12 878 | }, 879 | "position": { 880 | "x": 856, 881 | "y": 160 882 | } 883 | }, 884 | { 885 | "id": "d8aa167e-2d9b-4926-bc59-89564fcb5c02", 886 | "type": "basic.input", 887 | "data": { 888 | "name": "clk", 889 | "clock": true 890 | }, 891 | "position": { 892 | "x": 280, 893 | "y": 192 894 | } 895 | }, 896 | { 897 | "id": "612403e6-8ef2-4c0e-84a0-875ff8805a03", 898 | "type": "basic.output", 899 | "data": { 900 | "name": "data_out", 901 | "range": "[7:0]", 902 | "size": 8 903 | }, 904 | "position": { 905 | "x": 856, 906 | "y": 248 907 | } 908 | }, 909 | { 910 | "id": "7137e9cd-16ae-4d4e-96e9-39ee108889b0", 911 | "type": "basic.input", 912 | "data": { 913 | "name": "reset", 914 | "clock": false 915 | }, 916 | "position": { 917 | "x": 280, 918 | "y": 328 919 | } 920 | }, 921 | { 922 | "id": "cc25dd56-f44c-4ae1-abd5-20df6f53ff18", 923 | "type": "basic.output", 924 | "data": { 925 | "name": "we" 926 | }, 927 | "position": { 928 | "x": 856, 929 | "y": 328 930 | } 931 | }, 932 | { 933 | "id": "ef426d56-bc16-4230-a54f-cc61ac61cfb5", 934 | "type": "basic.output", 935 | "data": { 936 | "name": "ioreq" 937 | }, 938 | "position": { 939 | "x": 856, 940 | "y": 408 941 | } 942 | }, 943 | { 944 | "id": "0a1ce504-dd8a-48e0-98c5-05df511d2fcb", 945 | "type": "basic.input", 946 | "data": { 947 | "name": "data_in", 948 | "range": "[7:0]", 949 | "clock": false, 950 | "size": 8 951 | }, 952 | "position": { 953 | "x": 280, 954 | "y": 464 955 | } 956 | }, 957 | { 958 | "id": "2ccf9cd7-4d75-49e7-bafb-0fb3522d58a0", 959 | "type": "basic.output", 960 | "data": { 961 | "name": "hlt" 962 | }, 963 | "position": { 964 | "x": 856, 965 | "y": 496 966 | } 967 | }, 968 | { 969 | "id": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 970 | "type": "basic.code", 971 | "data": { 972 | "code": "// @include grom_cpu.v\n// @include alu.v\n\ngrom_cpu cpu(\n\t.clk(clk),\n\t.reset(reset),\n\t.addr(addr),\n\t.data_in(data_in),\n\t.data_out(data_out),\n\t.we(we),\n\t.ioreq(ioreq),\n\t.hlt(hlt)\n);\n", 973 | "params": [], 974 | "ports": { 975 | "in": [ 976 | { 977 | "name": "clk" 978 | }, 979 | { 980 | "name": "reset" 981 | }, 982 | { 983 | "name": "data_in", 984 | "range": "[7:0]", 985 | "size": 8 986 | } 987 | ], 988 | "out": [ 989 | { 990 | "name": "addr", 991 | "range": "[11:0]", 992 | "size": 12 993 | }, 994 | { 995 | "name": "data_out", 996 | "range": "[7:0]", 997 | "size": 8 998 | }, 999 | { 1000 | "name": "we" 1001 | }, 1002 | { 1003 | "name": "ioreq" 1004 | }, 1005 | { 1006 | "name": "hlt" 1007 | } 1008 | ] 1009 | } 1010 | }, 1011 | "position": { 1012 | "x": 480, 1013 | "y": 152 1014 | }, 1015 | "size": { 1016 | "width": 288, 1017 | "height": 416 1018 | } 1019 | } 1020 | ], 1021 | "wires": [ 1022 | { 1023 | "source": { 1024 | "block": "7137e9cd-16ae-4d4e-96e9-39ee108889b0", 1025 | "port": "out" 1026 | }, 1027 | "target": { 1028 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 1029 | "port": "reset" 1030 | } 1031 | }, 1032 | { 1033 | "source": { 1034 | "block": "0a1ce504-dd8a-48e0-98c5-05df511d2fcb", 1035 | "port": "out" 1036 | }, 1037 | "target": { 1038 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 1039 | "port": "data_in" 1040 | }, 1041 | "size": 8 1042 | }, 1043 | { 1044 | "source": { 1045 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 1046 | "port": "addr" 1047 | }, 1048 | "target": { 1049 | "block": "60084d58-17f4-4238-a8eb-1b3dc4f1bb84", 1050 | "port": "in" 1051 | }, 1052 | "size": 12 1053 | }, 1054 | { 1055 | "source": { 1056 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 1057 | "port": "data_out" 1058 | }, 1059 | "target": { 1060 | "block": "612403e6-8ef2-4c0e-84a0-875ff8805a03", 1061 | "port": "in" 1062 | }, 1063 | "size": 8 1064 | }, 1065 | { 1066 | "source": { 1067 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 1068 | "port": "we" 1069 | }, 1070 | "target": { 1071 | "block": "cc25dd56-f44c-4ae1-abd5-20df6f53ff18", 1072 | "port": "in" 1073 | } 1074 | }, 1075 | { 1076 | "source": { 1077 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 1078 | "port": "ioreq" 1079 | }, 1080 | "target": { 1081 | "block": "ef426d56-bc16-4230-a54f-cc61ac61cfb5", 1082 | "port": "in" 1083 | } 1084 | }, 1085 | { 1086 | "source": { 1087 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 1088 | "port": "hlt" 1089 | }, 1090 | "target": { 1091 | "block": "2ccf9cd7-4d75-49e7-bafb-0fb3522d58a0", 1092 | "port": "in" 1093 | } 1094 | }, 1095 | { 1096 | "source": { 1097 | "block": "d8aa167e-2d9b-4926-bc59-89564fcb5c02", 1098 | "port": "out" 1099 | }, 1100 | "target": { 1101 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 1102 | "port": "clk" 1103 | } 1104 | } 1105 | ] 1106 | }, 1107 | "state": { 1108 | "pan": { 1109 | "x": -158, 1110 | "y": -77 1111 | }, 1112 | "zoom": 1 1113 | } 1114 | } 1115 | } 1116 | } 1117 | } -------------------------------------------------------------------------------- /grom8.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | lint_off -msg INITIALDLY 3 | lint_off -msg BLKSEQ -------------------------------------------------------------------------------- /grom8_cpu.ice: -------------------------------------------------------------------------------- 1 | { 2 | "version": "1.1", 3 | "package": { 4 | "name": "Grom-8 CPU", 5 | "version": "1.0", 6 | "description": "Grom-8 CPU Core", 7 | "author": "Miodrag Milanovic", 8 | "image": "%3Csvg%20height=%22512%22%20viewBox=%220%200%20512%20512%22%20width=%22512%22%20xmlns=%22http://www.w3.org/2000/svg%22%3E%3Cpath%20d=%22M199%20387h-62.218c-.221%200%20.221%200%200%200C91.805%20387%2056%20350.337%2056%20305.36c0-44.977%2036.456-81.537%2081.433-81.537%203.922%200%207.778.222%2011.557.769%2013.941-56.938%2065.316-99.218%20126.554-99.218%2071.961%200%20130.293%2058.319%20130.293%20130.28%200%2010.593-1.264%2020.879-3.661%2030.743%201.212-.091%202.423-.03%203.661-.03%2027.7%200%2050.163%2022.563%2050.163%2050.263S433.537%20387%20405.837%20387H338%22%20fill=%22none%22%20stroke=%22#000%22%20stroke-miterlimit=%2210%22%20stroke-width=%2230%22/%3E%3Cpath%20stroke=%22#000%22%20stroke-linecap=%22round%22%20stroke-miterlimit=%2210%22%20stroke-width=%224%22%20d=%22M286.705%20270.678l-71.022%20100.615%2059.185%2026.633-38.47%2088.53%2082.858-97.408-62.144-35.511z%22/%3E%3C/svg%3E" 9 | }, 10 | "design": { 11 | "board": "go-board", 12 | "graph": { 13 | "blocks": [ 14 | { 15 | "id": "60084d58-17f4-4238-a8eb-1b3dc4f1bb84", 16 | "type": "basic.output", 17 | "data": { 18 | "name": "addr", 19 | "range": "[11:0]", 20 | "pins": [ 21 | { 22 | "index": "11", 23 | "name": "", 24 | "value": "0" 25 | }, 26 | { 27 | "index": "10", 28 | "name": "", 29 | "value": "0" 30 | }, 31 | { 32 | "index": "9", 33 | "name": "", 34 | "value": "0" 35 | }, 36 | { 37 | "index": "8", 38 | "name": "", 39 | "value": "0" 40 | }, 41 | { 42 | "index": "7", 43 | "name": "", 44 | "value": "0" 45 | }, 46 | { 47 | "index": "6", 48 | "name": "", 49 | "value": "0" 50 | }, 51 | { 52 | "index": "5", 53 | "name": "", 54 | "value": "0" 55 | }, 56 | { 57 | "index": "4", 58 | "name": "", 59 | "value": "0" 60 | }, 61 | { 62 | "index": "3", 63 | "name": "", 64 | "value": "0" 65 | }, 66 | { 67 | "index": "2", 68 | "name": "", 69 | "value": "0" 70 | }, 71 | { 72 | "index": "1", 73 | "name": "", 74 | "value": "0" 75 | }, 76 | { 77 | "index": "0", 78 | "name": "", 79 | "value": "0" 80 | } 81 | ], 82 | "virtual": true 83 | }, 84 | "position": { 85 | "x": 856, 86 | "y": 160 87 | } 88 | }, 89 | { 90 | "id": "d8aa167e-2d9b-4926-bc59-89564fcb5c02", 91 | "type": "basic.input", 92 | "data": { 93 | "name": "clk", 94 | "pins": [ 95 | { 96 | "index": "0", 97 | "name": "", 98 | "value": "0" 99 | } 100 | ], 101 | "virtual": true, 102 | "clock": true 103 | }, 104 | "position": { 105 | "x": 280, 106 | "y": 192 107 | } 108 | }, 109 | { 110 | "id": "612403e6-8ef2-4c0e-84a0-875ff8805a03", 111 | "type": "basic.output", 112 | "data": { 113 | "name": "data_out", 114 | "range": "[7:0]", 115 | "pins": [ 116 | { 117 | "index": "7", 118 | "name": "", 119 | "value": "0" 120 | }, 121 | { 122 | "index": "6", 123 | "name": "", 124 | "value": "0" 125 | }, 126 | { 127 | "index": "5", 128 | "name": "", 129 | "value": "0" 130 | }, 131 | { 132 | "index": "4", 133 | "name": "", 134 | "value": "0" 135 | }, 136 | { 137 | "index": "3", 138 | "name": "", 139 | "value": "0" 140 | }, 141 | { 142 | "index": "2", 143 | "name": "", 144 | "value": "0" 145 | }, 146 | { 147 | "index": "1", 148 | "name": "", 149 | "value": "0" 150 | }, 151 | { 152 | "index": "0", 153 | "name": "", 154 | "value": "0" 155 | } 156 | ], 157 | "virtual": true 158 | }, 159 | "position": { 160 | "x": 856, 161 | "y": 248 162 | } 163 | }, 164 | { 165 | "id": "7137e9cd-16ae-4d4e-96e9-39ee108889b0", 166 | "type": "basic.input", 167 | "data": { 168 | "name": "reset", 169 | "pins": [ 170 | { 171 | "index": "0", 172 | "name": "", 173 | "value": "0" 174 | } 175 | ], 176 | "virtual": true, 177 | "clock": false 178 | }, 179 | "position": { 180 | "x": 280, 181 | "y": 328 182 | } 183 | }, 184 | { 185 | "id": "cc25dd56-f44c-4ae1-abd5-20df6f53ff18", 186 | "type": "basic.output", 187 | "data": { 188 | "name": "we", 189 | "pins": [ 190 | { 191 | "index": "0", 192 | "name": "", 193 | "value": "0" 194 | } 195 | ], 196 | "virtual": true 197 | }, 198 | "position": { 199 | "x": 856, 200 | "y": 328 201 | } 202 | }, 203 | { 204 | "id": "ef426d56-bc16-4230-a54f-cc61ac61cfb5", 205 | "type": "basic.output", 206 | "data": { 207 | "name": "ioreq", 208 | "pins": [ 209 | { 210 | "index": "0", 211 | "name": "", 212 | "value": "0" 213 | } 214 | ], 215 | "virtual": true 216 | }, 217 | "position": { 218 | "x": 856, 219 | "y": 408 220 | } 221 | }, 222 | { 223 | "id": "0a1ce504-dd8a-48e0-98c5-05df511d2fcb", 224 | "type": "basic.input", 225 | "data": { 226 | "name": "data_in", 227 | "range": "[7:0]", 228 | "pins": [ 229 | { 230 | "index": "7", 231 | "name": "", 232 | "value": "0" 233 | }, 234 | { 235 | "index": "6", 236 | "name": "", 237 | "value": "0" 238 | }, 239 | { 240 | "index": "5", 241 | "name": "", 242 | "value": "0" 243 | }, 244 | { 245 | "index": "4", 246 | "name": "", 247 | "value": "0" 248 | }, 249 | { 250 | "index": "3", 251 | "name": "", 252 | "value": "0" 253 | }, 254 | { 255 | "index": "2", 256 | "name": "", 257 | "value": "0" 258 | }, 259 | { 260 | "index": "1", 261 | "name": "", 262 | "value": "0" 263 | }, 264 | { 265 | "index": "0", 266 | "name": "", 267 | "value": "0" 268 | } 269 | ], 270 | "virtual": true, 271 | "clock": false 272 | }, 273 | "position": { 274 | "x": 280, 275 | "y": 464 276 | } 277 | }, 278 | { 279 | "id": "2ccf9cd7-4d75-49e7-bafb-0fb3522d58a0", 280 | "type": "basic.output", 281 | "data": { 282 | "name": "hlt", 283 | "pins": [ 284 | { 285 | "index": "0", 286 | "name": "", 287 | "value": "0" 288 | } 289 | ], 290 | "virtual": true 291 | }, 292 | "position": { 293 | "x": 856, 294 | "y": 496 295 | } 296 | }, 297 | { 298 | "id": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 299 | "type": "basic.code", 300 | "data": { 301 | "code": "// @include grom_cpu.v\n// @include alu.v\n\ngrom_cpu cpu(\n\t.clk(clk),\n\t.reset(reset),\n\t.addr(addr),\n\t.data_in(data_in),\n\t.data_out(data_out),\n\t.we(we),\n\t.ioreq(ioreq),\n\t.hlt(hlt)\n);\n", 302 | "params": [], 303 | "ports": { 304 | "in": [ 305 | { 306 | "name": "clk" 307 | }, 308 | { 309 | "name": "reset" 310 | }, 311 | { 312 | "name": "data_in", 313 | "range": "[7:0]", 314 | "size": 8 315 | } 316 | ], 317 | "out": [ 318 | { 319 | "name": "addr", 320 | "range": "[11:0]", 321 | "size": 12 322 | }, 323 | { 324 | "name": "data_out", 325 | "range": "[7:0]", 326 | "size": 8 327 | }, 328 | { 329 | "name": "we" 330 | }, 331 | { 332 | "name": "ioreq" 333 | }, 334 | { 335 | "name": "hlt" 336 | } 337 | ] 338 | } 339 | }, 340 | "position": { 341 | "x": 480, 342 | "y": 152 343 | }, 344 | "size": { 345 | "width": 288, 346 | "height": 416 347 | } 348 | } 349 | ], 350 | "wires": [ 351 | { 352 | "source": { 353 | "block": "7137e9cd-16ae-4d4e-96e9-39ee108889b0", 354 | "port": "out" 355 | }, 356 | "target": { 357 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 358 | "port": "reset" 359 | } 360 | }, 361 | { 362 | "source": { 363 | "block": "0a1ce504-dd8a-48e0-98c5-05df511d2fcb", 364 | "port": "out" 365 | }, 366 | "target": { 367 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 368 | "port": "data_in" 369 | }, 370 | "size": 8 371 | }, 372 | { 373 | "source": { 374 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 375 | "port": "addr" 376 | }, 377 | "target": { 378 | "block": "60084d58-17f4-4238-a8eb-1b3dc4f1bb84", 379 | "port": "in" 380 | }, 381 | "size": 12 382 | }, 383 | { 384 | "source": { 385 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 386 | "port": "data_out" 387 | }, 388 | "target": { 389 | "block": "612403e6-8ef2-4c0e-84a0-875ff8805a03", 390 | "port": "in" 391 | }, 392 | "size": 8 393 | }, 394 | { 395 | "source": { 396 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 397 | "port": "we" 398 | }, 399 | "target": { 400 | "block": "cc25dd56-f44c-4ae1-abd5-20df6f53ff18", 401 | "port": "in" 402 | } 403 | }, 404 | { 405 | "source": { 406 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 407 | "port": "ioreq" 408 | }, 409 | "target": { 410 | "block": "ef426d56-bc16-4230-a54f-cc61ac61cfb5", 411 | "port": "in" 412 | } 413 | }, 414 | { 415 | "source": { 416 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 417 | "port": "hlt" 418 | }, 419 | "target": { 420 | "block": "2ccf9cd7-4d75-49e7-bafb-0fb3522d58a0", 421 | "port": "in" 422 | } 423 | }, 424 | { 425 | "source": { 426 | "block": "d8aa167e-2d9b-4926-bc59-89564fcb5c02", 427 | "port": "out" 428 | }, 429 | "target": { 430 | "block": "aa6c8682-fe13-4a26-aa83-fde87ccd2238", 431 | "port": "clk" 432 | } 433 | } 434 | ] 435 | }, 436 | "state": { 437 | "pan": { 438 | "x": -158, 439 | "y": -77 440 | }, 441 | "zoom": 1 442 | } 443 | }, 444 | "dependencies": {} 445 | } -------------------------------------------------------------------------------- /grom_computer.v: -------------------------------------------------------------------------------- 1 | module grom_computer 2 | (input clk, // Main Clock 3 | input reset, // reset 4 | output hlt, 5 | output reg[7:0] display_out 6 | ); 7 | 8 | wire [11:0] addr; 9 | wire [7:0] memory_out; 10 | wire [7:0] memory_in; 11 | wire mem_enable; 12 | wire we; 13 | wire ioreq; 14 | 15 | grom_cpu cpu(.clk(clk),.reset(reset),.addr(addr),.data_in(memory_out),.data_out(memory_in),.we(we),.ioreq(ioreq),.hlt(hlt)); 16 | 17 | assign mem_enable = we & ~ioreq; 18 | 19 | ram_memory memory(.clk(clk),.addr(addr),.data_in(memory_in),.we(mem_enable),.data_out(memory_out)); 20 | 21 | always @(posedge clk) 22 | begin 23 | if(ioreq==1 && we==1) 24 | begin 25 | display_out <= memory_in; 26 | `ifdef DISASSEMBLY 27 | $display("Display output : %h", memory_in); 28 | `endif 29 | end 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /grom_computer_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.77 (w)1999-2016 BSI 3 | [*] Wed Nov 01 14:49:21 2017 4 | [*] 5 | [timestart] 0 6 | [size] 1920 1017 7 | [pos] -1 -1 8 | *-16.000000 364700 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [treeopen] grom_computer_tb. 10 | [treeopen] grom_computer_tb.computer. 11 | [treeopen] grom_computer_tb.computer.cpu. 12 | [sst_width] 197 13 | [signals_width] 167 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 300 16 | @200 17 | -grom_computer_tb 18 | @28 19 | grom_computer_tb.clk 20 | @22 21 | grom_computer_tb.display_out[7:0] 22 | @28 23 | grom_computer_tb.hlt 24 | grom_computer_tb.reset 25 | @200 26 | -computer 27 | @22 28 | grom_computer_tb.computer.addr[11:0] 29 | @28 30 | grom_computer_tb.computer.clk 31 | @22 32 | grom_computer_tb.computer.display_out[7:0] 33 | @28 34 | grom_computer_tb.computer.hlt 35 | grom_computer_tb.computer.ioreq 36 | grom_computer_tb.computer.mem_enable 37 | @22 38 | grom_computer_tb.computer.memory_in[7:0] 39 | grom_computer_tb.computer.memory_out[7:0] 40 | @28 41 | grom_computer_tb.computer.reset 42 | grom_computer_tb.computer.we 43 | @200 44 | -cpu 45 | @22 46 | grom_computer_tb.computer.cpu.CS[3:0] 47 | grom_computer_tb.computer.cpu.DS[3:0] 48 | grom_computer_tb.computer.cpu.FUTURE_PC[11:0] 49 | grom_computer_tb.computer.cpu.IR[7:0] 50 | grom_computer_tb.computer.cpu.PC[11:0] 51 | @28 52 | grom_computer_tb.computer.cpu.RESULT_REG[1:0] 53 | @22 54 | grom_computer_tb.computer.cpu.SP[11:0] 55 | grom_computer_tb.computer.cpu.VALUE[7:0] 56 | grom_computer_tb.computer.cpu.addr[11:0] 57 | @28 58 | grom_computer_tb.computer.cpu.alu_CF 59 | grom_computer_tb.computer.cpu.alu_SF 60 | grom_computer_tb.computer.cpu.alu_ZF 61 | @22 62 | grom_computer_tb.computer.cpu.alu_a[7:0] 63 | grom_computer_tb.computer.cpu.alu_b[7:0] 64 | grom_computer_tb.computer.cpu.alu_op[3:0] 65 | grom_computer_tb.computer.cpu.alu_res[7:0] 66 | @28 67 | grom_computer_tb.computer.cpu.clk 68 | @22 69 | grom_computer_tb.computer.cpu.data_in[7:0] 70 | grom_computer_tb.computer.cpu.data_out[7:0] 71 | @28 72 | grom_computer_tb.computer.cpu.hlt 73 | grom_computer_tb.computer.cpu.ioreq 74 | grom_computer_tb.computer.cpu.jump 75 | grom_computer_tb.computer.cpu.reset 76 | @22 77 | grom_computer_tb.computer.cpu.state[4:0] 78 | @28 79 | grom_computer_tb.computer.cpu.we 80 | @200 81 | -alu 82 | @22 83 | grom_computer_tb.computer.cpu.alu.A[7:0] 84 | grom_computer_tb.computer.cpu.alu.B[7:0] 85 | @28 86 | grom_computer_tb.computer.cpu.alu.CF 87 | grom_computer_tb.computer.cpu.alu.SF 88 | grom_computer_tb.computer.cpu.alu.ZF 89 | grom_computer_tb.computer.cpu.alu.clk 90 | @22 91 | grom_computer_tb.computer.cpu.alu.operation[3:0] 92 | grom_computer_tb.computer.cpu.alu.result[7:0] 93 | grom_computer_tb.computer.cpu.alu.tmp[8:0] 94 | @200 95 | -memory 96 | @23 97 | grom_computer_tb.computer.memory.addr[11:0] 98 | @28 99 | grom_computer_tb.computer.memory.clk 100 | @22 101 | grom_computer_tb.computer.memory.data_in[7:0] 102 | grom_computer_tb.computer.memory.data_out[7:0] 103 | @28 104 | grom_computer_tb.computer.memory.we 105 | [pattern_trace] 1 106 | [pattern_trace] 0 107 | -------------------------------------------------------------------------------- /grom_computer_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module grom_computer_tb(); 3 | reg clk = 0; 4 | reg reset; 5 | wire [7:0] display_out; 6 | wire hlt; 7 | 8 | grom_computer computer(.clk(clk),.reset(reset),.hlt(hlt),.display_out(display_out)); 9 | 10 | always 11 | #(5) clk <= !clk; 12 | 13 | initial 14 | begin 15 | $dumpfile("grom_computer_tb.vcd"); 16 | $dumpvars(0,grom_computer_tb); 17 | reset = 1; 18 | #20 19 | reset = 0; 20 | #900 21 | $finish; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /grom_cpu.v: -------------------------------------------------------------------------------- 1 | module grom_cpu( 2 | input clk, 3 | input reset, 4 | output reg [11:0] addr, 5 | input [7:0] data_in, 6 | output reg [7:0] data_out, 7 | output reg we, 8 | output reg ioreq, 9 | output reg hlt 10 | ); 11 | 12 | reg[11:0] PC /* verilator public_flat */; // Program counter 13 | reg[7:0] IR /* verilator public_flat */; // Instruction register 14 | reg[7:0] VALUE /* verilator public_flat */; // Temp reg for storing 2nd operand 15 | reg[3:0] CS /* verilator public_flat */; // Code segment regiser 16 | reg[3:0] DS /* verilator public_flat */; // Data segment regiser 17 | reg[11:0] SP /* verilator public_flat */; // Stack pointer regiser 18 | reg[7:0] R[0:3] /* verilator public_flat */; // General purpose registers 19 | reg[11:0] FUTURE_PC /* verilator public_flat */; // PC to jump to 20 | 21 | localparam STATE_RESET /*verilator public_flat*/ = 5'b00000; 22 | localparam STATE_FETCH_PREP /*verilator public_flat*/ = 5'b00001; 23 | localparam STATE_FETCH_WAIT /*verilator public_flat*/ = 5'b00010; 24 | localparam STATE_FETCH /*verilator public_flat*/ = 5'b00011; 25 | localparam STATE_EXECUTE /*verilator public_flat*/ = 5'b00100; 26 | localparam STATE_FETCH_VALUE_PREP /*verilator public_flat*/ = 5'b00101; 27 | localparam STATE_FETCH_VALUE /*verilator public_flat*/ = 5'b00110; 28 | localparam STATE_EXECUTE_DBL /*verilator public_flat*/ = 5'b00111; 29 | localparam STATE_LOAD_VALUE /*verilator public_flat*/ = 5'b01000; 30 | localparam STATE_LOAD_VALUE_WAIT /*verilator public_flat*/ = 5'b01001; 31 | localparam STATE_ALU_RESULT_WAIT /*verilator public_flat*/ = 5'b01010; 32 | localparam STATE_ALU_RESULT /*verilator public_flat*/ = 5'b01011; 33 | localparam STATE_PUSH_PC_LOW /*verilator public_flat*/ = 5'b01100; 34 | localparam STATE_JUMP /*verilator public_flat*/ = 5'b01101; 35 | localparam STATE_RET_VALUE_WAIT /*verilator public_flat*/ = 5'b01110; 36 | localparam STATE_RET_VALUE /*verilator public_flat*/ = 5'b01111; 37 | localparam STATE_RET_VALUE_WAIT2 /*verilator public_flat*/ = 5'b10000; 38 | localparam STATE_RET_VALUE2 /*verilator public_flat*/ = 5'b10001; 39 | 40 | reg [4:0] state /* verilator public_flat */ = STATE_RESET; 41 | 42 | reg [7:0] alu_a /* verilator public_flat */; 43 | reg [7:0] alu_b /* verilator public_flat */; 44 | reg [3:0] alu_op /* verilator public_flat */; 45 | 46 | reg [1:0] RESULT_REG /* verilator public_flat */; 47 | 48 | wire [7:0] alu_res /* verilator public_flat */; 49 | wire alu_CF /* verilator public_flat */; 50 | wire alu_ZF /* verilator public_flat */; 51 | wire alu_SF /* verilator public_flat */; 52 | reg jump; 53 | 54 | alu alu(.clk(clk),.A(alu_a),.B(alu_b),.operation(alu_op),.result(alu_res),.CF(alu_CF),.ZF(alu_ZF),.SF(alu_SF)); 55 | 56 | always @(posedge clk) 57 | begin 58 | if (reset) 59 | begin 60 | state <= STATE_RESET; 61 | hlt <= 0; 62 | end 63 | else 64 | begin 65 | case (state) 66 | STATE_RESET : 67 | begin 68 | PC <= 12'h000; 69 | state <= STATE_FETCH_PREP; 70 | CS <= 4'h0; 71 | DS <= 4'h0; 72 | R[0] <= 8'h00; 73 | R[1] <= 8'h00; 74 | R[2] <= 8'h00; 75 | R[3] <= 8'h00; 76 | SP <= 12'hfff; 77 | end 78 | 79 | STATE_FETCH_PREP : 80 | begin 81 | addr <= PC; 82 | we <= 0; 83 | ioreq <= 0; 84 | 85 | state <= STATE_FETCH_WAIT; 86 | end 87 | 88 | STATE_FETCH_WAIT : 89 | begin 90 | // Sync with memory due to CLK 91 | state <= (hlt) ? STATE_FETCH_PREP : STATE_FETCH; 92 | end 93 | 94 | STATE_FETCH : 95 | begin 96 | IR <= data_in; 97 | PC <= PC + 1; 98 | 99 | state <= STATE_EXECUTE; 100 | end 101 | STATE_EXECUTE : 102 | begin 103 | `ifdef DISASSEMBLY 104 | $display(" PC %h R0 %h R1 %h R2 %h R3 %h CS %h DS %h SP %h ALU [%d %d %d]", PC, R[0], R[1], R[2], R[3], CS, DS, SP, alu_CF,alu_SF,alu_ZF); 105 | `endif 106 | if (IR[7]) 107 | begin 108 | addr <= PC; 109 | state <= STATE_FETCH_VALUE_PREP; 110 | PC <= PC + 1; 111 | end 112 | else 113 | begin 114 | case(IR[6:4]) 115 | 3'b000 : 116 | begin 117 | `ifdef DISASSEMBLY 118 | $display("MOV R%d,R%d",IR[3:2],IR[1:0]); 119 | `endif 120 | R[IR[3:2]] <= R[IR[1:0]]; 121 | state <= STATE_FETCH_PREP; 122 | end 123 | 3'b001 : 124 | begin 125 | alu_a <= R[0]; // first input R0 126 | alu_b <= R[IR[1:0]]; 127 | RESULT_REG <= 0; // result in R0 128 | alu_op <= { 2'b00, IR[3:2] }; 129 | 130 | state <= STATE_ALU_RESULT_WAIT; 131 | 132 | `ifdef DISASSEMBLY 133 | case(IR[3:2]) 134 | 2'b00 : begin 135 | $display("ADD R%d",IR[1:0]); 136 | end 137 | 2'b01 : begin 138 | $display("SUB R%d",IR[1:0]); 139 | end 140 | 2'b10 : begin 141 | $display("ADC R%d",IR[1:0]); 142 | end 143 | 2'b11 : begin 144 | $display("SBC R%d",IR[1:0]); 145 | end 146 | endcase 147 | `endif 148 | end 149 | 3'b010 : 150 | begin 151 | alu_a <= R[0]; // first input R0 152 | alu_b <= R[IR[1:0]]; 153 | RESULT_REG <= 0; // result in R0 154 | alu_op <= { 2'b01, IR[3:2] }; 155 | state <= STATE_ALU_RESULT_WAIT; 156 | `ifdef DISASSEMBLY 157 | case(IR[3:2]) 158 | 2'b00 : begin 159 | $display("AND R%d",IR[1:0]); 160 | end 161 | 2'b01 : begin 162 | $display("OR R%d",IR[1:0]); 163 | end 164 | 2'b10 : begin 165 | $display("NOT R%d",IR[1:0]); 166 | end 167 | 2'b11 : begin 168 | $display("XOR R%d",IR[1:0]); 169 | end 170 | endcase 171 | `endif 172 | end 173 | 3'b011 : 174 | begin 175 | RESULT_REG <= IR[1:0]; // result in REG 176 | // CMP and TEST are not storing result 177 | state <= IR[3] ? STATE_FETCH_PREP : STATE_ALU_RESULT_WAIT; 178 | // CMP and TEST are having first input R0, for INC and DEC is REG 179 | alu_a <= IR[3] ? R[0] : R[IR[1:0]]; 180 | // CMP and TEST are having second input REG, for INC and DEC is 1 181 | alu_b <= IR[3] ? R[IR[1:0]] : 8'b00000001; 182 | 183 | case(IR[3:2]) 184 | 2'b00 : begin 185 | `ifdef DISASSEMBLY 186 | $display("INC R%d",IR[1:0]); 187 | `endif 188 | alu_op <= 4'b0000; // ALU_OP_ADD 189 | end 190 | 2'b01 : begin 191 | `ifdef DISASSEMBLY 192 | $display("DEC R%d",IR[1:0]); 193 | `endif 194 | alu_op <= 4'b0001; // ALU_OP_SUB 195 | end 196 | 2'b10 : begin 197 | `ifdef DISASSEMBLY 198 | $display("CMP R%d",IR[1:0]); 199 | `endif 200 | alu_op <= 4'b0001; // ALU_OP_SUB 201 | end 202 | 2'b11 : begin 203 | `ifdef DISASSEMBLY 204 | $display("TST R%d",IR[1:0]); 205 | `endif 206 | alu_op <= 4'b0100; // ALU_OP_AND 207 | end 208 | endcase 209 | end 210 | 3'b100 : 211 | begin 212 | if (IR[3]==0) 213 | begin 214 | alu_a <= R[0]; // first input R0 215 | // no 2nd input 216 | RESULT_REG <= 0; // result in R0 217 | alu_op <= { 1'b1, IR[2:0] }; 218 | `ifdef DISASSEMBLY 219 | case(IR[2:0]) 220 | 3'b000 : begin 221 | $display("SHL"); 222 | end 223 | 3'b001 : begin 224 | $display("SHR"); 225 | end 226 | 3'b010 : begin 227 | $display("SAL"); 228 | end 229 | 3'b011 : begin 230 | $display("SAR"); 231 | end 232 | 3'b100 : begin 233 | $display("ROL"); 234 | end 235 | 3'b101 : begin 236 | $display("ROR"); 237 | end 238 | 3'b110 : begin 239 | $display("RCL"); 240 | end 241 | 3'b111 : begin 242 | $display("RCR"); 243 | end 244 | endcase 245 | `endif 246 | state <= STATE_ALU_RESULT_WAIT; 247 | end 248 | else 249 | begin 250 | if (IR[2]==0) 251 | begin 252 | `ifdef DISASSEMBLY 253 | $display("PUSH R%d",IR[1:0]); 254 | `endif 255 | addr <= SP; 256 | we <= 1; 257 | ioreq <= 0; 258 | data_out <= R[IR[1:0]]; 259 | SP <= SP - 1; 260 | state <= STATE_FETCH_PREP; 261 | end 262 | else 263 | begin 264 | `ifdef DISASSEMBLY 265 | $display("POP R%d",IR[1:0]); 266 | `endif 267 | addr <= SP + 1; 268 | we <= 0; 269 | ioreq <= 0; 270 | RESULT_REG <= IR[1:0]; 271 | SP <= SP + 1; 272 | state <= STATE_LOAD_VALUE_WAIT; 273 | end 274 | end 275 | end 276 | 3'b101 : 277 | begin 278 | `ifdef DISASSEMBLY 279 | $display("LOAD R%d,[R%d]", IR[3:2], IR[1:0]); 280 | `endif 281 | addr <= { DS, R[IR[1:0]] }; 282 | we <= 0; 283 | ioreq <= 0; 284 | RESULT_REG <= IR[3:2]; 285 | 286 | state <= STATE_LOAD_VALUE_WAIT; 287 | end 288 | 3'b110 : 289 | begin 290 | `ifdef DISASSEMBLY 291 | $display("STORE [R%d],R%d", IR[3:2], IR[1:0]); 292 | `endif 293 | addr <= { DS, R[IR[3:2]] }; 294 | we <= 1; 295 | ioreq <= 0; 296 | data_out <= R[IR[1:0]]; 297 | 298 | state <= STATE_FETCH_PREP; 299 | end 300 | 3'b111 : 301 | begin 302 | // Special instuctions 303 | case(IR[3:2]) 304 | 2'b00 : begin 305 | CS <= R[IR[1:0]][3:0]; 306 | state <= STATE_FETCH_PREP; 307 | `ifdef DISASSEMBLY 308 | $display("MOV CS,R%d",IR[1:0]); 309 | `endif 310 | end 311 | 2'b01 : begin 312 | DS <= R[IR[1:0]][3:0]; 313 | state <= STATE_FETCH_PREP; 314 | `ifdef DISASSEMBLY 315 | $display("MOV DS,R%d",IR[1:0]); 316 | `endif 317 | end 318 | 2'b10 : begin 319 | case(IR[1:0]) 320 | 2'b00 : begin 321 | `ifdef DISASSEMBLY 322 | $display("PUSH CS"); 323 | `endif 324 | addr <= SP; 325 | we <= 1; 326 | ioreq <= 0; 327 | data_out <= { 4'b0000, CS}; 328 | SP <= SP - 1; 329 | state <= STATE_FETCH_PREP; 330 | end 331 | 2'b01 : begin 332 | `ifdef DISASSEMBLY 333 | $display("PUSH DS"); 334 | `endif 335 | addr <= SP; 336 | we <= 1; 337 | ioreq <= 0; 338 | data_out <= { 4'b0000, DS}; 339 | SP <= SP - 1; 340 | state <= STATE_FETCH_PREP; 341 | end 342 | 2'b10 : begin 343 | `ifdef DISASSEMBLY 344 | $display("Unused opcode"); 345 | `endif 346 | end 347 | 2'b11 : begin 348 | `ifdef DISASSEMBLY 349 | $display("Unused opcode"); 350 | `endif 351 | end 352 | endcase 353 | state <= STATE_FETCH_PREP; 354 | end 355 | 2'b11 : begin 356 | case(IR[1:0]) 357 | 2'b00 : begin 358 | `ifdef DISASSEMBLY 359 | $display("Unused opcode"); 360 | `endif 361 | state <= STATE_FETCH_PREP; 362 | end 363 | 2'b01 : begin 364 | `ifdef DISASSEMBLY 365 | $display("Unused opcode"); 366 | `endif 367 | state <= STATE_FETCH_PREP; 368 | end 369 | 2'b10 : begin 370 | `ifdef DISASSEMBLY 371 | $display("RET"); 372 | `endif 373 | addr <= SP + 1; 374 | we <= 0; 375 | ioreq <= 0; 376 | SP <= SP + 1; 377 | state <= STATE_RET_VALUE_WAIT; 378 | end 379 | 2'b11 : begin 380 | hlt <= 1; 381 | `ifdef DISASSEMBLY 382 | $display("HALT"); 383 | `endif 384 | state <= STATE_FETCH_PREP; 385 | end 386 | endcase 387 | end 388 | endcase 389 | end 390 | endcase 391 | end 392 | end 393 | STATE_FETCH_VALUE_PREP : 394 | begin 395 | // Sync with memory due to CLK 396 | state <= STATE_FETCH_VALUE; 397 | end 398 | STATE_FETCH_VALUE : 399 | begin 400 | VALUE <= data_in; 401 | state <= STATE_EXECUTE_DBL; 402 | end 403 | STATE_EXECUTE_DBL : 404 | begin 405 | case(IR[6:4]) 406 | 3'b000 : 407 | begin 408 | if (IR[3]==0) 409 | begin 410 | case(IR[2:0]) 411 | 3'b000 : 412 | begin 413 | `ifdef DISASSEMBLY 414 | $display("JMP %h ",{ CS, VALUE[7:0] }); 415 | `endif 416 | jump = 1; 417 | end 418 | 3'b001 : 419 | begin 420 | `ifdef DISASSEMBLY 421 | $display("JC %h ",{CS, VALUE[7:0] }); 422 | `endif 423 | jump = (alu_CF==1); 424 | end 425 | 3'b010 : 426 | begin 427 | `ifdef DISASSEMBLY 428 | $display("JNC %h ",{CS, VALUE[7:0] }); 429 | `endif 430 | jump = (alu_CF==0); 431 | end 432 | 3'b011 : 433 | begin 434 | `ifdef DISASSEMBLY 435 | $display("JM %h ",{CS, VALUE[7:0] }); 436 | `endif 437 | jump = (alu_SF==1); 438 | end 439 | 3'b100 : 440 | begin 441 | `ifdef DISASSEMBLY 442 | $display("JP %h ",{CS, VALUE[7:0] }); 443 | `endif 444 | jump = (alu_SF==0); 445 | end 446 | 3'b101 : 447 | begin 448 | `ifdef DISASSEMBLY 449 | $display("JZ %h ",{CS, VALUE[7:0] }); 450 | `endif 451 | jump = (alu_ZF==1); 452 | end 453 | 3'b110 : 454 | begin 455 | `ifdef DISASSEMBLY 456 | $display("JNZ %h ",{CS, VALUE[7:0] }); 457 | `endif 458 | jump = (alu_ZF==0); 459 | end 460 | 3'b111 : 461 | begin 462 | `ifdef DISASSEMBLY 463 | $display("Unused opcode %h",IR); 464 | `endif 465 | jump = 0; 466 | end 467 | endcase 468 | 469 | if (jump) 470 | begin 471 | PC <= { CS, VALUE[7:0] }; 472 | addr <= { CS, VALUE[7:0] }; 473 | we <= 0; 474 | ioreq <= 0; 475 | end 476 | state <= STATE_FETCH_PREP; 477 | end 478 | else 479 | begin 480 | case(IR[2:0]) 481 | 3'b000 : 482 | begin 483 | `ifdef DISASSEMBLY 484 | $display("JR %h ", PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]} ); 485 | `endif 486 | jump = 1; 487 | end 488 | 3'b001 : 489 | begin 490 | `ifdef DISASSEMBLY 491 | $display("JRC %h ",{CS, VALUE[7:0] }); 492 | `endif 493 | jump = (alu_CF==1); 494 | end 495 | 3'b010 : 496 | begin 497 | `ifdef DISASSEMBLY 498 | $display("JRNC %h ",{CS, VALUE[7:0] }); 499 | `endif 500 | jump = (alu_CF==0); 501 | end 502 | 3'b011 : 503 | begin 504 | `ifdef DISASSEMBLY 505 | $display("JRM %h ",{CS, VALUE[7:0] }); 506 | `endif 507 | jump = (alu_SF==1); 508 | end 509 | 3'b100 : 510 | begin 511 | `ifdef DISASSEMBLY 512 | $display("JRP %h ",{CS, VALUE[7:0] }); 513 | `endif 514 | jump = (alu_SF==0); 515 | end 516 | 3'b101 : 517 | begin 518 | `ifdef DISASSEMBLY 519 | $display("JRZ %h ",{CS, VALUE[7:0] }); 520 | `endif 521 | jump = (alu_ZF==1); 522 | end 523 | 3'b110 : 524 | begin 525 | `ifdef DISASSEMBLY 526 | $display("JRNZ %h ",{CS, VALUE[7:0] }); 527 | `endif 528 | jump = (alu_ZF==0); 529 | end 530 | 3'b111 : 531 | begin 532 | `ifdef DISASSEMBLY 533 | $display("Unused opcode %h",IR); 534 | `endif 535 | jump = 0; 536 | end 537 | endcase 538 | if (jump) 539 | begin 540 | PC <= PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]}; 541 | addr <= PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]}; 542 | we <= 0; 543 | ioreq <= 0; 544 | end 545 | state <= STATE_FETCH_PREP; 546 | end 547 | end 548 | 3'b001 : 549 | begin 550 | `ifdef DISASSEMBLY 551 | $display("JUMP %h ",{ IR[3:0], VALUE[7:0] }); 552 | `endif 553 | PC <= { IR[3:0], VALUE[7:0] }; 554 | addr <= { IR[3:0], VALUE[7:0] }; 555 | we <= 0; 556 | ioreq <= 0; 557 | state <= STATE_FETCH_PREP; 558 | end 559 | 3'b010 : 560 | begin 561 | `ifdef DISASSEMBLY 562 | $display("CALL %h ",{ IR[3:0], VALUE[7:0] }); 563 | `endif 564 | FUTURE_PC <= { IR[3:0], VALUE[7:0] }; 565 | addr <= SP; 566 | we <= 1; 567 | ioreq <= 0; 568 | data_out <= { 4'b0000, PC[11:8]}; 569 | SP <= SP - 1; 570 | state <= STATE_PUSH_PC_LOW; 571 | end 572 | 3'b011 : 573 | begin 574 | `ifdef DISASSEMBLY 575 | $display("MOV SP,%h ",{ IR[3:0], VALUE[7:0] }); 576 | `endif 577 | SP <= { IR[3:0], VALUE[7:0] }; 578 | state <= STATE_FETCH_PREP; 579 | end 580 | 3'b100 : 581 | begin 582 | `ifdef DISASSEMBLY 583 | $display("IN R%d,[0x%h]",IR[1:0], VALUE); 584 | `endif 585 | ioreq <= 1; 586 | we <= 0; 587 | addr <= { 4'b0000, VALUE }; 588 | RESULT_REG <= IR[1:0]; 589 | state <= STATE_LOAD_VALUE_WAIT; 590 | end 591 | 3'b101 : 592 | begin 593 | `ifdef DISASSEMBLY 594 | $display("OUT [0x%h],R%d",VALUE,IR[1:0]); 595 | `endif 596 | ioreq <= 1; 597 | we <= 1; 598 | addr <= { 4'b0000, VALUE }; 599 | data_out <= R[IR[1:0]]; 600 | state <= STATE_FETCH_PREP; 601 | end 602 | 3'b110 : 603 | begin 604 | // Special instuctions 605 | case(IR[1:0]) 606 | 2'b00 : begin 607 | `ifdef DISASSEMBLY 608 | $display("MOV CS,0x%h",VALUE); 609 | `endif 610 | CS <= VALUE[3:0]; 611 | state <= STATE_FETCH_PREP; 612 | end 613 | 2'b01 : begin 614 | `ifdef DISASSEMBLY 615 | $display("MOV DS,0x%h",VALUE); 616 | `endif 617 | DS <= VALUE[3:0]; 618 | state <= STATE_FETCH_PREP; 619 | end 620 | 2'b10 : begin 621 | `ifdef DISASSEMBLY 622 | $display("Unused opcode %h",IR); 623 | `endif 624 | state <= STATE_FETCH_PREP; 625 | end 626 | 2'b11 : begin 627 | `ifdef DISASSEMBLY 628 | $display("Unused opcode %h",IR); 629 | `endif 630 | state <= STATE_FETCH_PREP; 631 | end 632 | endcase 633 | end 634 | 3'b111 : 635 | begin 636 | case(IR[3:2]) 637 | 2'b00 : begin 638 | `ifdef DISASSEMBLY 639 | $display("MOV R%d,0x%h",IR[1:0],VALUE); 640 | `endif 641 | R[IR[1:0]] <= VALUE; 642 | state <= STATE_FETCH_PREP; 643 | end 644 | 2'b01 : begin 645 | `ifdef DISASSEMBLY 646 | $display("LOAD R%d,[0x%h]",IR[1:0], {DS, VALUE}); 647 | `endif 648 | addr <= { DS, VALUE }; 649 | we <= 0; 650 | ioreq <= 0; 651 | RESULT_REG <= IR[1:0]; 652 | 653 | state <= STATE_LOAD_VALUE_WAIT; 654 | end 655 | 2'b10 : begin 656 | `ifdef DISASSEMBLY 657 | $display("STORE [0x%h],R%d", {DS, VALUE}, IR[1:0]); 658 | `endif 659 | addr <= { DS, VALUE }; 660 | we <= 1; 661 | ioreq <= 0; 662 | data_out <= R[IR[1:0]]; 663 | 664 | state <= STATE_FETCH_PREP; 665 | end 666 | 2'b11 : begin 667 | `ifdef DISASSEMBLY 668 | $display("Unused opcode %h",IR); 669 | `endif 670 | state <= STATE_FETCH_PREP; 671 | end 672 | endcase 673 | end 674 | endcase 675 | end 676 | STATE_LOAD_VALUE_WAIT : 677 | begin 678 | // Sync with memory due to CLK 679 | state <= STATE_LOAD_VALUE; 680 | end 681 | STATE_LOAD_VALUE : 682 | begin 683 | R[RESULT_REG] <= data_in; 684 | we <= 0; 685 | state <= STATE_FETCH_PREP; 686 | end 687 | STATE_ALU_RESULT_WAIT : 688 | begin 689 | state <= STATE_ALU_RESULT; 690 | end 691 | STATE_ALU_RESULT : 692 | begin 693 | R[RESULT_REG] <= alu_res; 694 | state <= STATE_FETCH_PREP; 695 | end 696 | STATE_PUSH_PC_LOW : 697 | begin 698 | addr <= SP; 699 | we <= 1; 700 | ioreq <= 0; 701 | data_out <= PC[7:0]; 702 | SP <= SP - 1; 703 | state <= STATE_JUMP; 704 | end 705 | STATE_JUMP : 706 | begin 707 | `ifdef DISASSEMBLY 708 | $display("Jumping to %h",FUTURE_PC); 709 | `endif 710 | PC <= FUTURE_PC; 711 | state <= STATE_FETCH_PREP; 712 | end 713 | STATE_RET_VALUE_WAIT : 714 | begin 715 | // Sync with memory due to CLK 716 | state <= STATE_RET_VALUE; 717 | end 718 | STATE_RET_VALUE : 719 | begin 720 | FUTURE_PC <= { 4'b0000, data_in }; 721 | we <= 0; 722 | state <= STATE_RET_VALUE_WAIT2; 723 | 724 | addr <= SP + 1; 725 | we <= 0; 726 | ioreq <= 0; 727 | SP <= SP + 1; 728 | end 729 | STATE_RET_VALUE_WAIT2 : 730 | begin 731 | // Sync with memory due to CLK 732 | state <= STATE_RET_VALUE2; 733 | end 734 | STATE_RET_VALUE2 : 735 | begin 736 | FUTURE_PC <= FUTURE_PC | ({ 4'b0000, data_in } << 8); 737 | we <= 0; 738 | state <= STATE_JUMP; 739 | end 740 | default : 741 | begin 742 | state <= STATE_FETCH_PREP; 743 | end 744 | endcase 745 | end 746 | end 747 | endmodule 748 | -------------------------------------------------------------------------------- /grom_top.v: -------------------------------------------------------------------------------- 1 | module grom_top 2 | (input i_Clk, // Main Clock 3 | input i_Switch_1, // SW1 button 4 | 5 | output o_LED_1, 6 | output o_LED_2, 7 | output o_LED_3, 8 | output o_LED_4, 9 | // Segment1 is upper digit, Segment2 is lower digit 10 | output o_Segment1_A, 11 | output o_Segment1_B, 12 | output o_Segment1_C, 13 | output o_Segment1_D, 14 | output o_Segment1_E, 15 | output o_Segment1_F, 16 | output o_Segment1_G, 17 | // 18 | output o_Segment2_A, 19 | output o_Segment2_B, 20 | output o_Segment2_C, 21 | output o_Segment2_D, 22 | output o_Segment2_E, 23 | output o_Segment2_F, 24 | output o_Segment2_G 25 | ); 26 | 27 | wire [7:0] display_out; 28 | wire hlt; 29 | 30 | grom_computer computer(.clk(i_Clk),.reset(i_Switch_1),.hlt(hlt),.display_out(display_out)); 31 | 32 | hex_to_7seg upper_digit 33 | (.i_Clk(i_Clk), 34 | .i_Value(display_out[7:4]), 35 | .o_Segment_A(o_Segment1_A), 36 | .o_Segment_B(o_Segment1_B), 37 | .o_Segment_C(o_Segment1_C), 38 | .o_Segment_D(o_Segment1_D), 39 | .o_Segment_E(o_Segment1_E), 40 | .o_Segment_F(o_Segment1_F), 41 | .o_Segment_G(o_Segment1_G)); 42 | 43 | hex_to_7seg lower_digit 44 | (.i_Clk(i_Clk), 45 | .i_Value(display_out[3:0]), 46 | .o_Segment_A(o_Segment2_A), 47 | .o_Segment_B(o_Segment2_B), 48 | .o_Segment_C(o_Segment2_C), 49 | .o_Segment_D(o_Segment2_D), 50 | .o_Segment_E(o_Segment2_E), 51 | .o_Segment_F(o_Segment2_F), 52 | .o_Segment_G(o_Segment2_G)); 53 | 54 | assign o_LED_1 = hlt; 55 | assign o_LED_2 = 1'b0; 56 | assign o_LED_3 = 1'b1; 57 | assign o_LED_4 = 1'b0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /hex_to_2_x_7seg.ice: -------------------------------------------------------------------------------- 1 | { 2 | "version": "1.1", 3 | "package": { 4 | "name": "HEX to 2 x 7seg", 5 | "version": "1.0", 6 | "description": "8-bit value to two 7seg displays", 7 | "author": "Miodrag Milanovic", 8 | "image": "%3Csvg%20xmlns=%22http://www.w3.org/2000/svg%22%20width=%22898.3%22%20height=%22898.3%22%20viewBox=%220%200%20898.3%20898.3%22%3E%3Cpath%20d=%22M120.2%20882.5l433.4-433.3L120.2%2015.8%200%20136l313.2%20313.2L0%20762.3z%22/%3E%3Cpath%20d=%22M344.7%20762.3l120.2%20120.2%20433.4-433.3L464.9%2015.8%20344.7%20136l313.2%20313.2z%22/%3E%3C/svg%3E" 9 | }, 10 | "design": { 11 | "board": "go-board", 12 | "graph": { 13 | "blocks": [ 14 | { 15 | "id": "a214789b-db10-4525-ba80-20c320c62a32", 16 | "type": "basic.output", 17 | "data": { 18 | "name": "Segment1", 19 | "range": "[6:0]", 20 | "pins": [ 21 | { 22 | "index": "6", 23 | "name": "", 24 | "value": "0" 25 | }, 26 | { 27 | "index": "5", 28 | "name": "", 29 | "value": "0" 30 | }, 31 | { 32 | "index": "4", 33 | "name": "", 34 | "value": "0" 35 | }, 36 | { 37 | "index": "3", 38 | "name": "", 39 | "value": "0" 40 | }, 41 | { 42 | "index": "2", 43 | "name": "", 44 | "value": "0" 45 | }, 46 | { 47 | "index": "1", 48 | "name": "", 49 | "value": "0" 50 | }, 51 | { 52 | "index": "0", 53 | "name": "", 54 | "value": "0" 55 | } 56 | ], 57 | "virtual": true 58 | }, 59 | "position": { 60 | "x": 808, 61 | "y": 136 62 | } 63 | }, 64 | { 65 | "id": "129a3e9c-cee8-4e02-9114-a44a9515fbef", 66 | "type": "basic.input", 67 | "data": { 68 | "name": "clk", 69 | "pins": [ 70 | { 71 | "index": "0", 72 | "name": "", 73 | "value": "0" 74 | } 75 | ], 76 | "virtual": true, 77 | "clock": true 78 | }, 79 | "position": { 80 | "x": 128, 81 | "y": 136 82 | } 83 | }, 84 | { 85 | "id": "d3746d71-9a02-4b67-8de3-1e6db572a1b6", 86 | "type": "basic.input", 87 | "data": { 88 | "name": "input_value", 89 | "range": "[7:0]", 90 | "pins": [ 91 | { 92 | "index": "7", 93 | "name": "", 94 | "value": "0" 95 | }, 96 | { 97 | "index": "6", 98 | "name": "", 99 | "value": "0" 100 | }, 101 | { 102 | "index": "5", 103 | "name": "", 104 | "value": "0" 105 | }, 106 | { 107 | "index": "4", 108 | "name": "", 109 | "value": "0" 110 | }, 111 | { 112 | "index": "3", 113 | "name": "", 114 | "value": "0" 115 | }, 116 | { 117 | "index": "2", 118 | "name": "", 119 | "value": "0" 120 | }, 121 | { 122 | "index": "1", 123 | "name": "", 124 | "value": "0" 125 | }, 126 | { 127 | "index": "0", 128 | "name": "", 129 | "value": "0" 130 | } 131 | ], 132 | "virtual": true, 133 | "clock": false 134 | }, 135 | "position": { 136 | "x": 128, 137 | "y": 328 138 | } 139 | }, 140 | { 141 | "id": "0a33152f-2efc-4333-a306-35ed1b32b5c9", 142 | "type": "basic.output", 143 | "data": { 144 | "name": "Segment2", 145 | "range": "[6:0]", 146 | "pins": [ 147 | { 148 | "index": "6", 149 | "name": "", 150 | "value": "0" 151 | }, 152 | { 153 | "index": "5", 154 | "name": "", 155 | "value": "0" 156 | }, 157 | { 158 | "index": "4", 159 | "name": "", 160 | "value": "0" 161 | }, 162 | { 163 | "index": "3", 164 | "name": "", 165 | "value": "0" 166 | }, 167 | { 168 | "index": "2", 169 | "name": "", 170 | "value": "0" 171 | }, 172 | { 173 | "index": "1", 174 | "name": "", 175 | "value": "0" 176 | }, 177 | { 178 | "index": "0", 179 | "name": "", 180 | "value": "0" 181 | } 182 | ], 183 | "virtual": true 184 | }, 185 | "position": { 186 | "x": 808, 187 | "y": 328 188 | } 189 | }, 190 | { 191 | "id": "540818d8-c478-45b8-b5af-0fa3f2832ded", 192 | "type": "basic.code", 193 | "data": { 194 | "code": "// @include hex_to_7seg.v\r\n\r\n hex_to_7seg upper_digit\r\n (.i_Clk(clk),\r\n .i_Value(data_input[7:4]),\r\n .o_Segment_A(S1[6]),\r\n .o_Segment_B(S1[5]),\r\n .o_Segment_C(S1[4]),\r\n .o_Segment_D(S1[3]),\r\n .o_Segment_E(S1[2]),\r\n .o_Segment_F(S1[1]),\r\n .o_Segment_G(S1[0]));\r\n\r\n hex_to_7seg lower_digit\r\n (.i_Clk(clk),\r\n .i_Value(data_input[3:0]),\r\n .o_Segment_A(S2[6]),\r\n .o_Segment_B(S2[5]),\r\n .o_Segment_C(S2[4]),\r\n .o_Segment_D(S2[3]),\r\n .o_Segment_E(S2[2]),\r\n .o_Segment_F(S2[1]),\r\n .o_Segment_G(S2[0]));\r\n", 195 | "params": [], 196 | "ports": { 197 | "in": [ 198 | { 199 | "name": "clk" 200 | }, 201 | { 202 | "name": "data_input", 203 | "range": "[7:0]", 204 | "size": 8 205 | } 206 | ], 207 | "out": [ 208 | { 209 | "name": "S1", 210 | "range": "[6:0]", 211 | "size": 7 212 | }, 213 | { 214 | "name": "S2", 215 | "range": "[6:0]", 216 | "size": 7 217 | } 218 | ] 219 | } 220 | }, 221 | "position": { 222 | "x": 376, 223 | "y": 72 224 | }, 225 | "size": { 226 | "width": 352, 227 | "height": 384 228 | } 229 | } 230 | ], 231 | "wires": [ 232 | { 233 | "source": { 234 | "block": "d3746d71-9a02-4b67-8de3-1e6db572a1b6", 235 | "port": "out" 236 | }, 237 | "target": { 238 | "block": "540818d8-c478-45b8-b5af-0fa3f2832ded", 239 | "port": "data_input" 240 | }, 241 | "size": 8 242 | }, 243 | { 244 | "source": { 245 | "block": "540818d8-c478-45b8-b5af-0fa3f2832ded", 246 | "port": "S1" 247 | }, 248 | "target": { 249 | "block": "a214789b-db10-4525-ba80-20c320c62a32", 250 | "port": "in" 251 | }, 252 | "size": 7 253 | }, 254 | { 255 | "source": { 256 | "block": "540818d8-c478-45b8-b5af-0fa3f2832ded", 257 | "port": "S2" 258 | }, 259 | "target": { 260 | "block": "0a33152f-2efc-4333-a306-35ed1b32b5c9", 261 | "port": "in" 262 | }, 263 | "size": 7 264 | }, 265 | { 266 | "source": { 267 | "block": "129a3e9c-cee8-4e02-9114-a44a9515fbef", 268 | "port": "out" 269 | }, 270 | "target": { 271 | "block": "540818d8-c478-45b8-b5af-0fa3f2832ded", 272 | "port": "clk" 273 | } 274 | } 275 | ] 276 | }, 277 | "state": { 278 | "pan": { 279 | "x": -58, 280 | "y": 19 281 | }, 282 | "zoom": 1 283 | } 284 | }, 285 | "dependencies": {} 286 | } -------------------------------------------------------------------------------- /hex_to_7seg.v: -------------------------------------------------------------------------------- 1 | module hex_to_7seg 2 | ( 3 | input i_Clk, 4 | input [3:0] i_Value, 5 | output o_Segment_A, 6 | output o_Segment_B, 7 | output o_Segment_C, 8 | output o_Segment_D, 9 | output o_Segment_E, 10 | output o_Segment_F, 11 | output o_Segment_G 12 | ); 13 | 14 | reg [6:0] out = 7'b0000000; 15 | 16 | always @(posedge i_Clk) 17 | begin 18 | case (i_Value) 19 | 4'b0000 : out <= 7'b0000001; 20 | 4'b0001 : out <= 7'b1001111; 21 | 4'b0010 : out <= 7'b0010010; 22 | 4'b0011 : out <= 7'b0000110; 23 | 4'b0100 : out <= 7'b1001100; 24 | 4'b0101 : out <= 7'b0100100; 25 | 4'b0110 : out <= 7'b0100000; 26 | 4'b0111 : out <= 7'b0001111; 27 | 4'b1000 : out <= 7'b0000000; 28 | 4'b1001 : out <= 7'b0000100; 29 | 4'b1010 : out <= 7'b0001000; 30 | 4'b1011 : out <= 7'b1100000; 31 | 4'b1100 : out <= 7'b0110001; 32 | 4'b1101 : out <= 7'b1000010; 33 | 4'b1110 : out <= 7'b0110000; 34 | 4'b1111 : out <= 7'b0111000; 35 | endcase 36 | end 37 | 38 | assign o_Segment_A = out[6]; 39 | assign o_Segment_B = out[5]; 40 | assign o_Segment_C = out[4]; 41 | assign o_Segment_D = out[3]; 42 | assign o_Segment_E = out[2]; 43 | assign o_Segment_F = out[1]; 44 | assign o_Segment_G = out[0]; 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /instruction_set.txt: -------------------------------------------------------------------------------- 1 | IR - Instruction register (8 bit) 2 | PC - Program counter (12 bit) 3 | SEG - Segment register (4 bit only used) 4 | R0-R3 - registers (8 bit) 5 | 6 | 7 | 0000 dst src MOV dst, src 8 | 9 | 0001 00 reg ADD reg r0 = r0 + reg 10 | 0001 01 reg SUB reg r0 = r0 - reg 11 | 0001 10 reg ADC reg r0 = r0 + reg + C 12 | 0001 11 reg SBC reg r0 = r0 - reg - C 13 | 14 | 0010 00 reg AND reg r0 = r0 and reg 15 | 0010 01 reg OR reg r0 = r0 or reg 16 | 0010 10 reg NOT reg r0 = not reg 17 | 0010 11 reg XOR reg r0 = r0 xor reg 18 | 19 | 0011 00 reg INC reg reg = reg + 1 20 | 0011 01 reg DEC reg reg = reg - 1 21 | 0011 10 reg CMP reg flags of r0 - reg 22 | 0011 11 reg TST reg flags of r0 and reg 23 | 24 | 0100 00 00 SHL 25 | 0100 00 01 SHR 26 | 0100 00 10 SAL 27 | 0100 00 11 SAR 28 | 29 | 0100 01 00 ROL 30 | 0100 01 01 ROR 31 | 0100 01 10 RCL rotate with carry 32 | 0100 01 11 RCR rotate with carry 33 | 34 | 0100 10 reg PUSH reg 35 | 0100 11 reg POP reg 36 | 37 | 0101 dst src LOAD dst, [src] 38 | 39 | 0110 dst src STORE [dst], src 40 | 41 | 0111 00 reg MOV CS, reg 42 | 0111 01 reg MOV DS, reg 43 | 44 | 0111 10 00 PUSH CS 45 | 0111 10 01 PUSH DS 46 | 0111 10 10 ??? 47 | 0111 10 11 ??? 48 | 49 | 0111 11 00 ??? 50 | 0111 11 01 ??? 51 | 0111 11 10 RET 52 | 0111 11 11 HLT 53 | 54 | ============================================================ 55 | 56 | 1000 00 00 val JMP val (unconditionally jump) 57 | 1000 00 01 val JC val (carry=1 jump) 58 | 1000 00 10 val JNC val (carry=0 jump) 59 | 1000 00 11 val JM val (sign=1 jump) 60 | 1000 01 00 val JP val (sign=0 jump) 61 | 1000 01 01 val JZ val (zero=1 jump) 62 | 1000 01 10 val JNZ val (zero=0 jump) 63 | 1000 01 11 val ??? 64 | 65 | 1000 10 00 val JR val (unconditionally jump) 66 | 1000 10 01 val JRC val (carry=1 jump) 67 | 1000 10 10 val JRNC val (carry=0 jump) 68 | 1000 10 11 val JRM val (sign=1 jump) 69 | 1000 11 00 val JRP val (sign=0 jump) 70 | 1000 11 01 val JRZ val (zero=1 jump) 71 | 1000 11 10 val JRNZ val (zero=0 jump) 72 | 1000 11 11 val ??? 73 | 74 | 1001 high low JUMP addr 75 | 76 | 1010 high low CALL addr 77 | 78 | 1011 high low MOV SP,addr 79 | 80 | 1100 xx reg val IN reg,[val] 81 | 1101 xx reg val OUT [val],reg 82 | 83 | 1110 xx 00 val MOV CS,val 84 | 1110 xx 01 val MOV DS,val 85 | 1110 xx 10 val ??? 86 | 1110 xx 11 val ??? 87 | 88 | 1111 00 reg val MOV reg, val 89 | 1111 01 reg val LOAD reg, [val] 90 | 1111 10 reg val STORE [val], reg 91 | 1111 11 xx val ??? 92 | -------------------------------------------------------------------------------- /ram_memory.v: -------------------------------------------------------------------------------- 1 | module ram_memory( 2 | input clk, 3 | input [11:0] addr, 4 | input [7:0] data_in, 5 | input we, 6 | output reg [7:0] data_out 7 | ); 8 | 9 | reg [7:0] store[0:4095] /* verilator public_flat */; 10 | 11 | initial 12 | begin 13 | $readmemh("boot.mem", store); 14 | `ifndef VERILATOR 15 | store[0] <= 8'b11100001; // MOV DS,2 16 | store[1] <= 8'b00000010; // 17 | store[2] <= 8'b01010100; // LOAD R1,[R0] 18 | store[3] <= 8'b00110001; // INC R1 19 | store[4] <= 8'b00110001; // INC R1 20 | store[5] <= 8'b01100001; // STORE [R0],R1 21 | store[6] <= 8'b11010001; // OUT [0],R1 22 | store[7] <= 8'b00000000; // 23 | store[8] <= 8'b00110001; // INC R1 24 | store[9] <= 8'b10100001; // CALL 0x100 25 | store[10] <= 8'b00000000; // 26 | store[11] <= 8'b01111111; // HLT 27 | 28 | 29 | store[256] <= 8'b11010001; // OUT [0],R1 30 | store[257] <= 8'b00000000; // 31 | store[258] <= 8'b01111110; // RET 32 | `endif 33 | end 34 | 35 | always @(posedge clk) 36 | if (we) 37 | store[addr] <= data_in; 38 | else 39 | data_out <= store[addr]; 40 | endmodule 41 | -------------------------------------------------------------------------------- /test_alu.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "Valu.h" 4 | #include "verilated.h" 5 | 6 | #define CATCH_CONFIG_RUNNER 7 | #include "catch.hpp" 8 | 9 | int main( int argc, char* argv[] ) 10 | { 11 | Verilated::commandArgs(argc, argv); 12 | int result = Catch::Session().run( argc, argv ); 13 | return ( result < 0xff ? result : 0xff ); 14 | } 15 | 16 | TEST_CASE("Test ALU_OP_ADD", "ALU") 17 | { 18 | std::unique_ptr top = std::make_unique(); 19 | top->clk = 0; 20 | for(int A=0;A<0x100;A++) 21 | { 22 | for(int B=0;B<0x100;B++) 23 | { 24 | top->A = A; 25 | top->B = B; 26 | top->operation = top->alu__DOT__ALU_OP_ADD; 27 | top->clk ^= 1; top->eval(); 28 | top->clk ^= 1; top->eval(); 29 | uint8_t res = A + B; 30 | REQUIRE(res==top->result); 31 | REQUIRE(((res==0) ? 1:0)==top->ZF); 32 | REQUIRE((((A + B)>0xff) ? 1 : 0 )==top->CF); 33 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 34 | } 35 | } 36 | } 37 | 38 | 39 | TEST_CASE("Test ALU_OP_ADC", "ALU") 40 | { 41 | std::unique_ptr top = std::make_unique(); 42 | top->clk = 0; 43 | for(int A=0;A<0x100;A++) 44 | { 45 | for(int B=0;B<0x100;B++) 46 | { 47 | // Set CF to 0 48 | { 49 | top->A = 0; 50 | top->B = 0; 51 | top->operation = top->alu__DOT__ALU_OP_ADD; 52 | top->clk ^= 1; top->eval(); 53 | top->clk ^= 1; top->eval(); 54 | } 55 | 56 | top->A = A; 57 | top->B = B; 58 | top->operation = top->alu__DOT__ALU_OP_ADC; 59 | top->clk ^= 1; top->eval(); 60 | top->clk ^= 1; top->eval(); 61 | uint8_t res = A + B; 62 | REQUIRE(res==top->result); 63 | REQUIRE(((res==0) ? 1:0)==top->ZF); 64 | REQUIRE((((A + B)>0xff) ? 1 : 0 )==top->CF); 65 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 66 | } 67 | } 68 | 69 | for(int A=0;A<0x100;A++) 70 | { 71 | for(int B=0;B<0x100;B++) 72 | { 73 | // Set CF to 1 74 | { 75 | top->A = 0; 76 | top->B = 1; 77 | top->operation = top->alu__DOT__ALU_OP_SUB; 78 | top->clk ^= 1; top->eval(); 79 | top->clk ^= 1; top->eval(); 80 | } 81 | top->A = A; 82 | top->B = B; 83 | top->operation = top->alu__DOT__ALU_OP_ADC; 84 | int res = A + B + 1; 85 | top->clk ^= 1; top->eval(); 86 | top->clk ^= 1; top->eval(); 87 | REQUIRE((res&0xff)==top->result); 88 | REQUIRE((((res&0xff)==0) ? 1:0)==top->ZF); 89 | REQUIRE((((res)>0xff) ? 1 : 0 )==top->CF); 90 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 91 | } 92 | } 93 | } 94 | 95 | 96 | TEST_CASE("Test ALU_OP_SUB", "ALU") 97 | { 98 | std::unique_ptr top = std::make_unique(); 99 | top->clk = 0; 100 | for(int A=0;A<0x100;A++) 101 | { 102 | for(int B=0;B<0x100;B++) 103 | { 104 | top->A = A; 105 | top->B = B; 106 | top->operation = top->alu__DOT__ALU_OP_SUB; 107 | top->clk ^= 1; top->eval(); 108 | top->clk ^= 1; top->eval(); 109 | uint8_t res = A - B; 110 | REQUIRE(res==top->result); 111 | REQUIRE(((res==0) ? 1:0)==top->ZF); 112 | REQUIRE((((A - B)<0) ? 1 : 0 )==top->CF); 113 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 114 | } 115 | } 116 | } 117 | 118 | TEST_CASE("Test ALU_OP_SBC", "ALU") 119 | { 120 | std::unique_ptr top = std::make_unique(); 121 | top->clk = 0; 122 | for(int A=0;A<0x100;A++) 123 | { 124 | for(int B=0;B<0x100;B++) 125 | { 126 | // Set CF to 1 127 | { 128 | top->A = 0; 129 | top->B = 1; 130 | top->operation = top->alu__DOT__ALU_OP_SUB; 131 | top->clk ^= 1; top->eval(); 132 | top->clk ^= 1; top->eval(); 133 | } 134 | REQUIRE(1==top->CF); 135 | top->A = A; 136 | top->B = B; 137 | top->operation = top->alu__DOT__ALU_OP_SBC; 138 | int res = A - B - 1; 139 | top->clk ^= 1; top->eval(); 140 | top->clk ^= 1; top->eval(); 141 | REQUIRE((res&0xff)==top->result); 142 | REQUIRE((((res&0xff)==0) ? 1:0)==top->ZF); 143 | REQUIRE((((res)<0) ? 1 : 0 )==top->CF); 144 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 145 | } 146 | } 147 | } 148 | 149 | TEST_CASE("Test ALU_OP_AND", "ALU") 150 | { 151 | std::unique_ptr top = std::make_unique(); 152 | top->clk = 0; 153 | for(int A=0;A<0x100;A++) 154 | { 155 | for(int B=0;B<0x100;B++) 156 | { 157 | top->A = A; 158 | top->B = B; 159 | top->operation = top->alu__DOT__ALU_OP_AND; 160 | top->clk ^= 1; top->eval(); 161 | top->clk ^= 1; top->eval(); 162 | uint8_t res = A & B; 163 | REQUIRE(res==top->result); 164 | REQUIRE(((res==0) ? 1:0)==top->ZF); 165 | REQUIRE(0==top->CF); 166 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 167 | } 168 | } 169 | } 170 | 171 | TEST_CASE("Test ALU_OP_OR", "ALU") 172 | { 173 | std::unique_ptr top = std::make_unique(); 174 | top->clk = 0; 175 | for(int A=0;A<0x100;A++) 176 | { 177 | for(int B=0;B<0x100;B++) 178 | { 179 | top->A = A; 180 | top->B = B; 181 | top->operation = top->alu__DOT__ALU_OP_OR; 182 | top->clk ^= 1; top->eval(); 183 | top->clk ^= 1; top->eval(); 184 | uint8_t res = A | B; 185 | REQUIRE(res==top->result); 186 | REQUIRE(((res==0) ? 1:0)==top->ZF); 187 | REQUIRE(0==top->CF); 188 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 189 | } 190 | } 191 | } 192 | 193 | 194 | TEST_CASE("Test ALU_OP_XOR", "ALU") 195 | { 196 | std::unique_ptr top = std::make_unique(); 197 | top->clk = 0; 198 | for(int A=0;A<0x100;A++) 199 | { 200 | for(int B=0;B<0x100;B++) 201 | { 202 | top->A = A; 203 | top->B = B; 204 | top->operation = top->alu__DOT__ALU_OP_XOR; 205 | top->clk ^= 1; top->eval(); 206 | top->clk ^= 1; top->eval(); 207 | uint8_t res = A ^ B; 208 | REQUIRE(res==top->result); 209 | REQUIRE(((res==0) ? 1:0)==top->ZF); 210 | REQUIRE(0==top->CF); 211 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 212 | } 213 | } 214 | } 215 | 216 | TEST_CASE("Test ALU_OP_NOT", "ALU") 217 | { 218 | std::unique_ptr top = std::make_unique(); 219 | top->clk = 0; 220 | for(int B=0;B<0x100;B++) 221 | { 222 | top->A = 0; 223 | top->B = B; 224 | top->operation = top->alu__DOT__ALU_OP_NOT; 225 | top->clk ^= 1; top->eval(); 226 | top->clk ^= 1; top->eval(); 227 | uint8_t res = ~B; 228 | REQUIRE(res==top->result); 229 | REQUIRE(((res==0) ? 1:0)==top->ZF); 230 | REQUIRE(0==top->CF); 231 | REQUIRE(((res & 0x80) ? 1 : 0) == top->SF); 232 | } 233 | } 234 | -------------------------------------------------------------------------------- /test_comp.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "Vgrom_computer.h" 4 | #include "verilated.h" 5 | 6 | #define CATCH_CONFIG_RUNNER 7 | #include "catch.hpp" 8 | 9 | int main( int argc, char* argv[] ) 10 | { 11 | Verilated::commandArgs(argc, argv); 12 | int result = Catch::Session().run( argc, argv ); 13 | return ( result < 0xff ? result : 0xff ); 14 | } 15 | 16 | TEST_CASE("Reset CPU", "Computer") 17 | { 18 | std::unique_ptr top = std::make_unique(); 19 | 20 | top->clk = 0; 21 | top->reset = 1; 22 | 23 | top->clk ^= 1; top->eval(); // mid clock 24 | REQUIRE(top->hlt == 0); 25 | REQUIRE(top->grom_computer__DOT__cpu__DOT__state == top->grom_computer__DOT__cpu__DOT__STATE_RESET); 26 | top->clk ^= 1; top->eval(); 27 | 28 | top->reset = 0; 29 | 30 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // one Clock 31 | 32 | REQUIRE(top->grom_computer__DOT__cpu__DOT__CS == 0); 33 | REQUIRE(top->grom_computer__DOT__cpu__DOT__DS == 0); 34 | REQUIRE(top->grom_computer__DOT__cpu__DOT__R[0] == 0); 35 | REQUIRE(top->grom_computer__DOT__cpu__DOT__R[1] == 0); 36 | REQUIRE(top->grom_computer__DOT__cpu__DOT__R[2] == 0); 37 | REQUIRE(top->grom_computer__DOT__cpu__DOT__R[3] == 0); 38 | REQUIRE(top->grom_computer__DOT__cpu__DOT__SP == 0xfff); 39 | } 40 | 41 | TEST_CASE("Check memory", "Computer") 42 | { 43 | std::unique_ptr top = std::make_unique(); 44 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // one Clock 45 | 46 | for(int i=0;i<0x1000;i++) 47 | { 48 | REQUIRE(top->grom_computer__DOT__memory__DOT__store[i] == 0); 49 | } 50 | } -------------------------------------------------------------------------------- /test_cpu.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "Vgrom_cpu.h" 4 | #include "verilated.h" 5 | 6 | #define CATCH_CONFIG_RUNNER 7 | #include "catch.hpp" 8 | 9 | int main( int argc, char* argv[] ) 10 | { 11 | Verilated::commandArgs(argc, argv); 12 | int result = Catch::Session().run( argc, argv ); 13 | return ( result < 0xff ? result : 0xff ); 14 | } 15 | 16 | TEST_CASE("Reset CPU", "CPU") 17 | { 18 | std::unique_ptr top = std::make_unique(); 19 | 20 | top->clk = 0; 21 | top->reset = 1; 22 | 23 | top->clk ^= 1; top->eval(); // mid clock 24 | REQUIRE(top->hlt == 0); 25 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_RESET); 26 | top->clk ^= 1; top->eval(); 27 | 28 | top->reset = 0; 29 | 30 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // one Clock 31 | 32 | REQUIRE(top->grom_cpu__DOT__CS == 0); 33 | REQUIRE(top->grom_cpu__DOT__DS == 0); 34 | REQUIRE(top->grom_cpu__DOT__R[0] == 0); 35 | REQUIRE(top->grom_cpu__DOT__R[1] == 0); 36 | REQUIRE(top->grom_cpu__DOT__R[2] == 0); 37 | REQUIRE(top->grom_cpu__DOT__R[3] == 0); 38 | REQUIRE(top->grom_cpu__DOT__SP == 0xfff); 39 | } 40 | 41 | TEST_CASE("Fetch instruction", "CPU") 42 | { 43 | std::unique_ptr top = std::make_unique(); 44 | 45 | top->clk = 0; 46 | 47 | top->data_in = 0x7f; 48 | 49 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH_PREP 50 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH_PREP); 51 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH_WAIT 52 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH_WAIT); 53 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH 54 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH); 55 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_EXECUTE 56 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_EXECUTE); 57 | 58 | REQUIRE(top->grom_cpu__DOT__IR == 0x7f); 59 | } 60 | 61 | 62 | void executeSimpleInstruction(Vgrom_cpu *top) 63 | { 64 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH_PREP 65 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH_PREP); 66 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH_WAIT 67 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH_WAIT); 68 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH 69 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH); 70 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_EXECUTE 71 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_EXECUTE); 72 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH_PREP 73 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH_PREP); 74 | } 75 | 76 | TEST_CASE("HLT instruction", "CPU") 77 | { 78 | std::unique_ptr top = std::make_unique(); 79 | 80 | top->clk = 0; 81 | 82 | top->data_in = 0x7f; // HLT 83 | executeSimpleInstruction(top.get()); 84 | 85 | REQUIRE(top->hlt == 1); 86 | } 87 | 88 | TEST_CASE("After HLT cpu should remain in loop", "CPU") 89 | { 90 | std::unique_ptr top = std::make_unique(); 91 | 92 | top->clk = 0; 93 | 94 | top->data_in = 0x7f; // HLT 95 | executeSimpleInstruction(top.get()); 96 | 97 | REQUIRE(top->hlt == 1); 98 | 99 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH_PREP); 100 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH_WAIT 101 | REQUIRE(top->grom_cpu__DOT__state == top->grom_cpu__DOT__STATE_FETCH_WAIT); 102 | top->clk ^= 1; top->eval(); top->clk ^= 1; top->eval(); // STATE_FETCH 103 | 104 | REQUIRE(top->hlt == 1); 105 | } 106 | --------------------------------------------------------------------------------