├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile ├── README.md ├── modules ├── axi4 │ ├── axi_if.sv │ ├── axi_lite_if.sv │ ├── axi_lite_pkg.sv │ └── axi_pkg.sv ├── bus │ ├── arbiter.sv │ └── interconnect_bus.sv ├── cache │ ├── cache.sv │ ├── cachemem.sv │ ├── dcache.sv │ └── icache.sv ├── core │ ├── alu.sv │ ├── control.sv │ ├── core.sv │ ├── csr_file.sv │ ├── datapath.sv │ ├── decode.sv │ ├── decode_execute.sv │ ├── execute.sv │ ├── fetch.sv │ ├── lsu.sv │ ├── pc_mux.sv │ ├── pkg │ │ ├── alu_op_pkg.sv │ │ ├── csr_addr_pkg.sv │ │ ├── pc_mux_pkg.sv │ │ ├── src_a_mux_pkg.sv │ │ ├── src_b_mux_pkg.sv │ │ └── type_pkg.sv │ ├── regfile.sv │ ├── src_a_mux.sv │ ├── src_b_mux.sv │ └── writeback.sv └── ram │ ├── blockram.sv │ ├── pkg │ └── ram_pkg.sv │ └── ram.sv ├── scripts ├── create_project.tcl └── simulation.tcl └── tests ├── tb_top.sv ├── test.sh └── testlog.txt /.gitignore: -------------------------------------------------------------------------------- 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