├── .cproject ├── .gitignore ├── .mxproject ├── .project ├── .settings ├── language.settings.xml └── stm32cubeide.project.prefs ├── Core ├── Inc │ ├── main.h │ ├── stm32f1xx_hal_conf.h │ └── stm32f1xx_it.h ├── Src │ ├── main.c │ ├── stm32f1xx_hal_msp.c │ ├── stm32f1xx_it.c │ ├── syscalls.c │ ├── sysmem.c │ └── system_stm32f1xx.c └── Startup │ └── startup_stm32f103rbtx.s ├── Debug ├── Core │ ├── Src │ │ └── subdir.mk │ └── Startup │ │ └── subdir.mk ├── Drivers │ └── STM32F1xx_HAL_Driver │ │ └── Src │ │ └── subdir.mk ├── STM32_PatternDriver.bin ├── STM32_PatternDriver.list ├── makefile ├── objects.list ├── objects.mk └── sources.mk ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32F1xx │ │ │ ├── Include │ │ │ ├── stm32f103xb.h │ │ │ ├── stm32f1xx.h │ │ │ └── system_stm32f1xx.h │ │ │ └── License.md │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ └── LICENSE.txt └── STM32F1xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32f1xx_hal.h │ ├── stm32f1xx_hal_cortex.h │ ├── stm32f1xx_hal_def.h │ ├── stm32f1xx_hal_dma.h │ ├── stm32f1xx_hal_dma_ex.h │ ├── stm32f1xx_hal_exti.h │ ├── stm32f1xx_hal_flash.h │ ├── stm32f1xx_hal_flash_ex.h │ ├── stm32f1xx_hal_gpio.h │ ├── stm32f1xx_hal_gpio_ex.h │ ├── stm32f1xx_hal_pwr.h │ ├── stm32f1xx_hal_rcc.h │ ├── stm32f1xx_hal_rcc_ex.h │ ├── stm32f1xx_hal_tim.h │ ├── stm32f1xx_hal_tim_ex.h │ └── stm32f1xx_hal_uart.h │ ├── License.md │ └── Src │ ├── stm32f1xx_hal.c │ ├── stm32f1xx_hal_cortex.c │ ├── stm32f1xx_hal_dma.c │ ├── stm32f1xx_hal_exti.c │ ├── stm32f1xx_hal_flash.c │ ├── stm32f1xx_hal_flash_ex.c │ ├── stm32f1xx_hal_gpio.c │ ├── stm32f1xx_hal_gpio_ex.c │ ├── stm32f1xx_hal_pwr.c │ ├── stm32f1xx_hal_rcc.c │ ├── stm32f1xx_hal_rcc_ex.c │ ├── stm32f1xx_hal_tim.c │ ├── stm32f1xx_hal_tim_ex.c │ └── stm32f1xx_hal_uart.c ├── LICENSE ├── README.md ├── STM32F103RBTX_FLASH.ld ├── STM32_PatternDriver Debug.launch ├── STM32_PatternDriver.ioc └── img ├── DS1Z_QuickPrint4.png └── Datasheet.png /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Object files 5 | *.o 6 | *.ko 7 | *.obj 8 | *.elf 9 | 10 | # Linker output 11 | *.ilk 12 | *.map 13 | *.exp 14 | 15 | # Precompiled Headers 16 | *.gch 17 | *.pch 18 | 19 | # Libraries 20 | *.lib 21 | *.a 22 | *.la 23 | *.lo 24 | 25 | # Shared objects (inc. Windows DLLs) 26 | *.dll 27 | *.so 28 | *.so.* 29 | *.dylib 30 | 31 | # Executables 32 | *.exe 33 | *.out 34 | *.app 35 | *.i*86 36 | *.x86_64 37 | *.hex 38 | 39 | # Debug files 40 | *.dSYM/ 41 | *.su 42 | *.idb 43 | *.pdb 44 | 45 | # Kernel Module Compile Results 46 | *.mod* 47 | *.cmd 48 | .tmp_versions/ 49 | modules.order 50 | Module.symvers 51 | Mkfile.old 52 | dkms.conf 53 | -------------------------------------------------------------------------------- /.mxproject: -------------------------------------------------------------------------------- 1 | [PreviousLibFiles] 2 | LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xb.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; 3 | 4 | [PreviousUsedCubeIDEFiles] 5 | SourceFiles=Core\Src\main.c;Core\Src\stm32f1xx_it.c;Core\Src\stm32f1xx_hal_msp.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;;; 6 | HeaderPath=Drivers\STM32F1xx_HAL_Driver\Inc;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F1xx\Include;Drivers\CMSIS\Include;Core\Inc; 7 | CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;USE_HAL_DRIVER; 8 | 9 | [PreviousGenFiles] 10 | AdvancedFolderStructure=true 11 | HeaderFileListSize=3 12 | HeaderFiles#0=C:/Users/simon/Documents/STM32/cubeide/STM32_PatternDriver/Core/Inc/stm32f1xx_it.h 13 | HeaderFiles#1=C:/Users/simon/Documents/STM32/cubeide/STM32_PatternDriver/Core/Inc/stm32f1xx_hal_conf.h 14 | HeaderFiles#2=C:/Users/simon/Documents/STM32/cubeide/STM32_PatternDriver/Core/Inc/main.h 15 | HeaderFolderListSize=1 16 | HeaderPath#0=C:/Users/simon/Documents/STM32/cubeide/STM32_PatternDriver/Core/Inc 17 | HeaderFiles=; 18 | SourceFileListSize=3 19 | SourceFiles#0=C:/Users/simon/Documents/STM32/cubeide/STM32_PatternDriver/Core/Src/stm32f1xx_it.c 20 | SourceFiles#1=C:/Users/simon/Documents/STM32/cubeide/STM32_PatternDriver/Core/Src/stm32f1xx_hal_msp.c 21 | SourceFiles#2=C:/Users/simon/Documents/STM32/cubeide/STM32_PatternDriver/Core/Src/main.c 22 | SourceFolderListSize=1 23 | SourcePath#0=C:/Users/simon/Documents/STM32/cubeide/STM32_PatternDriver/Core/Src 24 | SourceFiles=; 25 | 26 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | STM32_PatternDriver 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | com.st.stm32cube.ide.mcu.MCUProjectNature 23 | com.st.stm32cube.ide.mcu.MCUCubeProjectNature 24 | org.eclipse.cdt.core.cnature 25 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature 26 | com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature 27 | com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature 28 | com.st.stm32cube.ide.mcu.MCURootProjectNature 29 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 30 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 31 | 32 | 33 | -------------------------------------------------------------------------------- /.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /.settings/stm32cubeide.project.prefs: -------------------------------------------------------------------------------- 1 | 66BE74F758C12D739921AEA421D593D3=5 2 | 8DF89ED150041C4CBC7CB9A9CAA90856=E0AFCEA9985570D7F4C5108830E3F2DB 3 | DC22A860405A8BF2F2C095E5B6529F12=E0AFCEA9985570D7F4C5108830E3F2DB 4 | eclipse.preferences.version=1 5 | -------------------------------------------------------------------------------- /Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __MAIN_H 23 | #define __MAIN_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f1xx_hal.h" 31 | 32 | /* Private includes ----------------------------------------------------------*/ 33 | /* USER CODE BEGIN Includes */ 34 | 35 | /* USER CODE END Includes */ 36 | 37 | /* Exported types ------------------------------------------------------------*/ 38 | /* USER CODE BEGIN ET */ 39 | 40 | /* USER CODE END ET */ 41 | 42 | /* Exported constants --------------------------------------------------------*/ 43 | /* USER CODE BEGIN EC */ 44 | 45 | /* USER CODE END EC */ 46 | 47 | /* Exported macro ------------------------------------------------------------*/ 48 | /* USER CODE BEGIN EM */ 49 | 50 | /* USER CODE END EM */ 51 | 52 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); 53 | 54 | /* Exported functions prototypes ---------------------------------------------*/ 55 | void Error_Handler(void); 56 | 57 | /* USER CODE BEGIN EFP */ 58 | 59 | /* USER CODE END EFP */ 60 | 61 | /* Private defines -----------------------------------------------------------*/ 62 | #define TIM2_PERIOD 512-1 63 | #define B1_Pin GPIO_PIN_13 64 | #define B1_GPIO_Port GPIOC 65 | #define B1_EXTI_IRQn EXTI15_10_IRQn 66 | #define USART_TX_Pin GPIO_PIN_2 67 | #define USART_TX_GPIO_Port GPIOA 68 | #define USART_RX_Pin GPIO_PIN_3 69 | #define USART_RX_GPIO_Port GPIOA 70 | #define LD2_Pin GPIO_PIN_5 71 | #define LD2_GPIO_Port GPIOA 72 | #define TMS_Pin GPIO_PIN_13 73 | #define TMS_GPIO_Port GPIOA 74 | #define TCK_Pin GPIO_PIN_14 75 | #define TCK_GPIO_Port GPIOA 76 | #define SWO_Pin GPIO_PIN_3 77 | #define SWO_GPIO_Port GPIOB 78 | /* USER CODE BEGIN Private defines */ 79 | 80 | /* USER CODE END Private defines */ 81 | 82 | #ifdef __cplusplus 83 | } 84 | #endif 85 | 86 | #endif /* __MAIN_H */ 87 | -------------------------------------------------------------------------------- /Core/Inc/stm32f1xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F1xx_IT_H 22 | #define __STM32F1xx_IT_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Private includes ----------------------------------------------------------*/ 29 | /* USER CODE BEGIN Includes */ 30 | 31 | /* USER CODE END Includes */ 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN ET */ 35 | 36 | /* USER CODE END ET */ 37 | 38 | /* Exported constants --------------------------------------------------------*/ 39 | /* USER CODE BEGIN EC */ 40 | 41 | /* USER CODE END EC */ 42 | 43 | /* Exported macro ------------------------------------------------------------*/ 44 | /* USER CODE BEGIN EM */ 45 | 46 | /* USER CODE END EM */ 47 | 48 | /* Exported functions prototypes ---------------------------------------------*/ 49 | void NMI_Handler(void); 50 | void HardFault_Handler(void); 51 | void MemManage_Handler(void); 52 | void BusFault_Handler(void); 53 | void UsageFault_Handler(void); 54 | void SVC_Handler(void); 55 | void DebugMon_Handler(void); 56 | void PendSV_Handler(void); 57 | void SysTick_Handler(void); 58 | void DMA1_Channel2_IRQHandler(void); 59 | void EXTI15_10_IRQHandler(void); 60 | /* USER CODE BEGIN EFP */ 61 | 62 | /* USER CODE END EFP */ 63 | 64 | #ifdef __cplusplus 65 | } 66 | #endif 67 | 68 | #endif /* __STM32F1xx_IT_H */ 69 | -------------------------------------------------------------------------------- /Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.c 5 | * @brief : Main program body 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "main.h" 21 | 22 | /* Private includes ----------------------------------------------------------*/ 23 | /* USER CODE BEGIN Includes */ 24 | 25 | /* USER CODE END Includes */ 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* USER CODE BEGIN PTD */ 29 | 30 | /* USER CODE END PTD */ 31 | 32 | /* Private define ------------------------------------------------------------*/ 33 | /* USER CODE BEGIN PD */ 34 | #undef TIM2_PERIOD 35 | #define TIM2_PERIOD 16-1 36 | // 64 MHz timer -> count to 16 = 4 MHz updates -> toggle on match -> 2 MHz signal 37 | 38 | /* USER CODE END PD */ 39 | 40 | /* Private macro -------------------------------------------------------------*/ 41 | /* USER CODE BEGIN PM */ 42 | 43 | /* USER CODE END PM */ 44 | 45 | /* Private variables ---------------------------------------------------------*/ 46 | TIM_HandleTypeDef htim2; 47 | DMA_HandleTypeDef hdma_tim2_up; 48 | 49 | UART_HandleTypeDef huart2; 50 | 51 | /* USER CODE BEGIN PV */ 52 | 53 | /* USER CODE END PV */ 54 | 55 | /* Private function prototypes -----------------------------------------------*/ 56 | void SystemClock_Config(void); 57 | static void MX_GPIO_Init(void); 58 | static void MX_USART2_UART_Init(void); 59 | static void MX_DMA_Init(void); 60 | static void MX_TIM2_Init(void); 61 | /* USER CODE BEGIN PFP */ 62 | 63 | /* USER CODE END PFP */ 64 | 65 | /* Private user code ---------------------------------------------------------*/ 66 | /* USER CODE BEGIN 0 */ 67 | 68 | /* USER CODE END 0 */ 69 | 70 | /** 71 | * @brief The application entry point. 72 | * @retval int 73 | */ 74 | int main(void) 75 | { 76 | /* USER CODE BEGIN 1 */ 77 | 78 | /* USER CODE END 1 */ 79 | 80 | /* MCU Configuration--------------------------------------------------------*/ 81 | 82 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 83 | HAL_Init(); 84 | 85 | /* USER CODE BEGIN Init */ 86 | 87 | /* USER CODE END Init */ 88 | 89 | /* Configure the system clock */ 90 | SystemClock_Config(); 91 | 92 | /* USER CODE BEGIN SysInit */ 93 | 94 | /* USER CODE END SysInit */ 95 | 96 | /* Initialize all configured peripherals */ 97 | MX_GPIO_Init(); 98 | MX_USART2_UART_Init(); 99 | MX_DMA_Init(); 100 | MX_TIM2_Init(); 101 | /* USER CODE BEGIN 2 */ 102 | // uint32_t pixelclock[8] = {0x00000000, 0xffffffff, 0xffffffff, 0x0000, 0x00, 0x00, 0xffffffff, 0x00}; 103 | uint32_t pixelclock[16]; 104 | for(int i=0;i<16;i++) 105 | pixelclock[i]=0; 106 | // the pixelclock goes straight to the BSRR register 107 | // [31 ... 16] are reset bits corresponding to Ports [15 ... 0] 108 | // [15 ... 0] are set bits corresponding to Ports [15 ... 0] 109 | // if a reset bit is set, the GPIO port will be set LOW 110 | // if a set bit is set, the GPIO port will be set HIGH 111 | pixelclock[ 0] = 0x00000001; // set SI signal on 1st clock edge 112 | pixelclock[ 2] = 0x00010000; // reset SI signal on 3rd clock edge 113 | pixelclock[ 9] = 0x00000002; // set the ESH signal high 114 | pixelclock[13] = 0x00020000; // set the ESH signal low 115 | 116 | // DMA, circular memory-to-peripheral mode, full word (32 bit) transfer 117 | HAL_DMA_Start(&hdma_tim2_up, (uint32_t)pixelclock, (uint32_t)&(GPIOC->BSRR), 16); 118 | HAL_TIM_Base_Start(&htim2); 119 | HAL_TIM_OC_Start(&htim2, TIM_CHANNEL_1); 120 | TIM2->DIER |= (1 << 8); // set UDE bit (update dma request enable) 121 | 122 | /* USER CODE END 2 */ 123 | 124 | /* Infinite loop */ 125 | /* USER CODE BEGIN WHILE */ 126 | while (1) 127 | { 128 | /* USER CODE END WHILE */ 129 | 130 | /* USER CODE BEGIN 3 */ 131 | HAL_Delay(100); 132 | } 133 | /* USER CODE END 3 */ 134 | } 135 | 136 | /** 137 | * @brief System Clock Configuration 138 | * @retval None 139 | */ 140 | void SystemClock_Config(void) 141 | { 142 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 143 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 144 | 145 | /** Initializes the RCC Oscillators according to the specified parameters 146 | * in the RCC_OscInitTypeDef structure. 147 | */ 148 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 149 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; 150 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 151 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 152 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; 153 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; 154 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 155 | { 156 | Error_Handler(); 157 | } 158 | /** Initializes the CPU, AHB and APB buses clocks 159 | */ 160 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 161 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 162 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 163 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 164 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 165 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 166 | 167 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 168 | { 169 | Error_Handler(); 170 | } 171 | } 172 | 173 | /** 174 | * @brief TIM2 Initialization Function 175 | * @param None 176 | * @retval None 177 | */ 178 | static void MX_TIM2_Init(void) 179 | { 180 | 181 | /* USER CODE BEGIN TIM2_Init 0 */ 182 | 183 | /* USER CODE END TIM2_Init 0 */ 184 | 185 | TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 186 | TIM_MasterConfigTypeDef sMasterConfig = {0}; 187 | TIM_OC_InitTypeDef sConfigOC = {0}; 188 | 189 | /* USER CODE BEGIN TIM2_Init 1 */ 190 | 191 | /* USER CODE END TIM2_Init 1 */ 192 | htim2.Instance = TIM2; 193 | htim2.Init.Prescaler = 0; 194 | htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 195 | htim2.Init.Period = TIM2_PERIOD; 196 | htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 197 | htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 198 | if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 199 | { 200 | Error_Handler(); 201 | } 202 | sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 203 | if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 204 | { 205 | Error_Handler(); 206 | } 207 | if (HAL_TIM_OC_Init(&htim2) != HAL_OK) 208 | { 209 | Error_Handler(); 210 | } 211 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 212 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 213 | if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 214 | { 215 | Error_Handler(); 216 | } 217 | sConfigOC.OCMode = TIM_OCMODE_TOGGLE; 218 | sConfigOC.Pulse = 0; 219 | sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 220 | sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 221 | if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 222 | { 223 | Error_Handler(); 224 | } 225 | /* USER CODE BEGIN TIM2_Init 2 */ 226 | 227 | /* USER CODE END TIM2_Init 2 */ 228 | HAL_TIM_MspPostInit(&htim2); 229 | 230 | } 231 | 232 | /** 233 | * @brief USART2 Initialization Function 234 | * @param None 235 | * @retval None 236 | */ 237 | static void MX_USART2_UART_Init(void) 238 | { 239 | 240 | /* USER CODE BEGIN USART2_Init 0 */ 241 | 242 | /* USER CODE END USART2_Init 0 */ 243 | 244 | /* USER CODE BEGIN USART2_Init 1 */ 245 | 246 | /* USER CODE END USART2_Init 1 */ 247 | huart2.Instance = USART2; 248 | huart2.Init.BaudRate = 115200; 249 | huart2.Init.WordLength = UART_WORDLENGTH_8B; 250 | huart2.Init.StopBits = UART_STOPBITS_1; 251 | huart2.Init.Parity = UART_PARITY_NONE; 252 | huart2.Init.Mode = UART_MODE_TX_RX; 253 | huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 254 | huart2.Init.OverSampling = UART_OVERSAMPLING_16; 255 | if (HAL_UART_Init(&huart2) != HAL_OK) 256 | { 257 | Error_Handler(); 258 | } 259 | /* USER CODE BEGIN USART2_Init 2 */ 260 | 261 | /* USER CODE END USART2_Init 2 */ 262 | 263 | } 264 | 265 | /** 266 | * Enable DMA controller clock 267 | */ 268 | static void MX_DMA_Init(void) 269 | { 270 | 271 | /* DMA controller clock enable */ 272 | __HAL_RCC_DMA1_CLK_ENABLE(); 273 | 274 | /* DMA interrupt init */ 275 | /* DMA1_Channel2_IRQn interrupt configuration */ 276 | HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); 277 | HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 278 | 279 | } 280 | 281 | /** 282 | * @brief GPIO Initialization Function 283 | * @param None 284 | * @retval None 285 | */ 286 | static void MX_GPIO_Init(void) 287 | { 288 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 289 | 290 | /* GPIO Ports Clock Enable */ 291 | __HAL_RCC_GPIOC_CLK_ENABLE(); 292 | __HAL_RCC_GPIOD_CLK_ENABLE(); 293 | __HAL_RCC_GPIOA_CLK_ENABLE(); 294 | __HAL_RCC_GPIOB_CLK_ENABLE(); 295 | 296 | /*Configure GPIO pin Output Level */ 297 | HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET); 298 | 299 | /*Configure GPIO pin Output Level */ 300 | HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 301 | 302 | /*Configure GPIO pin : B1_Pin */ 303 | GPIO_InitStruct.Pin = B1_Pin; 304 | GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 305 | GPIO_InitStruct.Pull = GPIO_NOPULL; 306 | HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); 307 | 308 | /*Configure GPIO pins : PC0 PC1 PC2 PC3 */ 309 | GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; 310 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 311 | GPIO_InitStruct.Pull = GPIO_NOPULL; 312 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 313 | HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 314 | 315 | /*Configure GPIO pin : LD2_Pin */ 316 | GPIO_InitStruct.Pin = LD2_Pin; 317 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 318 | GPIO_InitStruct.Pull = GPIO_NOPULL; 319 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 320 | HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); 321 | 322 | /* EXTI interrupt init*/ 323 | HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); 324 | HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 325 | 326 | } 327 | 328 | /* USER CODE BEGIN 4 */ 329 | 330 | /* USER CODE END 4 */ 331 | 332 | /** 333 | * @brief This function is executed in case of error occurrence. 334 | * @retval None 335 | */ 336 | void Error_Handler(void) 337 | { 338 | /* USER CODE BEGIN Error_Handler_Debug */ 339 | /* User can add his own implementation to report the HAL error return state */ 340 | __disable_irq(); 341 | while (1) 342 | { 343 | } 344 | /* USER CODE END Error_Handler_Debug */ 345 | } 346 | 347 | #ifdef USE_FULL_ASSERT 348 | /** 349 | * @brief Reports the name of the source file and the source line number 350 | * where the assert_param error has occurred. 351 | * @param file: pointer to the source file name 352 | * @param line: assert_param error line source number 353 | * @retval None 354 | */ 355 | void assert_failed(uint8_t *file, uint32_t line) 356 | { 357 | /* USER CODE BEGIN 6 */ 358 | /* User can add his own implementation to report the file name and line number, 359 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 360 | /* USER CODE END 6 */ 361 | } 362 | #endif /* USE_FULL_ASSERT */ 363 | 364 | -------------------------------------------------------------------------------- /Core/Src/stm32f1xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_hal_msp.c 5 | * @brief This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | /* USER CODE BEGIN Includes */ 24 | 25 | /* USER CODE END Includes */ 26 | extern DMA_HandleTypeDef hdma_tim2_up; 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | 62 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); 63 | /** 64 | * Initializes the Global MSP. 65 | */ 66 | void HAL_MspInit(void) 67 | { 68 | /* USER CODE BEGIN MspInit 0 */ 69 | 70 | /* USER CODE END MspInit 0 */ 71 | 72 | __HAL_RCC_AFIO_CLK_ENABLE(); 73 | __HAL_RCC_PWR_CLK_ENABLE(); 74 | 75 | /* System interrupt init*/ 76 | 77 | /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 78 | */ 79 | __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80 | 81 | /* USER CODE BEGIN MspInit 1 */ 82 | 83 | /* USER CODE END MspInit 1 */ 84 | } 85 | 86 | /** 87 | * @brief TIM_Base MSP Initialization 88 | * This function configures the hardware resources used in this example 89 | * @param htim_base: TIM_Base handle pointer 90 | * @retval None 91 | */ 92 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) 93 | { 94 | if(htim_base->Instance==TIM2) 95 | { 96 | /* USER CODE BEGIN TIM2_MspInit 0 */ 97 | 98 | /* USER CODE END TIM2_MspInit 0 */ 99 | /* Peripheral clock enable */ 100 | __HAL_RCC_TIM2_CLK_ENABLE(); 101 | 102 | /* TIM2 DMA Init */ 103 | /* TIM2_UP Init */ 104 | hdma_tim2_up.Instance = DMA1_Channel2; 105 | hdma_tim2_up.Init.Direction = DMA_MEMORY_TO_PERIPH; 106 | hdma_tim2_up.Init.PeriphInc = DMA_PINC_DISABLE; 107 | hdma_tim2_up.Init.MemInc = DMA_MINC_ENABLE; 108 | hdma_tim2_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; 109 | hdma_tim2_up.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; 110 | hdma_tim2_up.Init.Mode = DMA_CIRCULAR; 111 | hdma_tim2_up.Init.Priority = DMA_PRIORITY_HIGH; 112 | if (HAL_DMA_Init(&hdma_tim2_up) != HAL_OK) 113 | { 114 | Error_Handler(); 115 | } 116 | 117 | __HAL_LINKDMA(htim_base,hdma[TIM_DMA_ID_UPDATE],hdma_tim2_up); 118 | 119 | /* USER CODE BEGIN TIM2_MspInit 1 */ 120 | 121 | /* USER CODE END TIM2_MspInit 1 */ 122 | } 123 | 124 | } 125 | 126 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) 127 | { 128 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 129 | if(htim->Instance==TIM2) 130 | { 131 | /* USER CODE BEGIN TIM2_MspPostInit 0 */ 132 | 133 | /* USER CODE END TIM2_MspPostInit 0 */ 134 | 135 | __HAL_RCC_GPIOA_CLK_ENABLE(); 136 | /**TIM2 GPIO Configuration 137 | PA0-WKUP ------> TIM2_CH1 138 | */ 139 | GPIO_InitStruct.Pin = GPIO_PIN_0; 140 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 141 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 142 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 143 | 144 | /* USER CODE BEGIN TIM2_MspPostInit 1 */ 145 | 146 | /* USER CODE END TIM2_MspPostInit 1 */ 147 | } 148 | 149 | } 150 | /** 151 | * @brief TIM_Base MSP De-Initialization 152 | * This function freeze the hardware resources used in this example 153 | * @param htim_base: TIM_Base handle pointer 154 | * @retval None 155 | */ 156 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) 157 | { 158 | if(htim_base->Instance==TIM2) 159 | { 160 | /* USER CODE BEGIN TIM2_MspDeInit 0 */ 161 | 162 | /* USER CODE END TIM2_MspDeInit 0 */ 163 | /* Peripheral clock disable */ 164 | __HAL_RCC_TIM2_CLK_DISABLE(); 165 | 166 | /* TIM2 DMA DeInit */ 167 | HAL_DMA_DeInit(htim_base->hdma[TIM_DMA_ID_UPDATE]); 168 | /* USER CODE BEGIN TIM2_MspDeInit 1 */ 169 | 170 | /* USER CODE END TIM2_MspDeInit 1 */ 171 | } 172 | 173 | } 174 | 175 | /** 176 | * @brief UART MSP Initialization 177 | * This function configures the hardware resources used in this example 178 | * @param huart: UART handle pointer 179 | * @retval None 180 | */ 181 | void HAL_UART_MspInit(UART_HandleTypeDef* huart) 182 | { 183 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 184 | if(huart->Instance==USART2) 185 | { 186 | /* USER CODE BEGIN USART2_MspInit 0 */ 187 | 188 | /* USER CODE END USART2_MspInit 0 */ 189 | /* Peripheral clock enable */ 190 | __HAL_RCC_USART2_CLK_ENABLE(); 191 | 192 | __HAL_RCC_GPIOA_CLK_ENABLE(); 193 | /**USART2 GPIO Configuration 194 | PA2 ------> USART2_TX 195 | PA3 ------> USART2_RX 196 | */ 197 | GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; 198 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 199 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 200 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 201 | 202 | /* USER CODE BEGIN USART2_MspInit 1 */ 203 | 204 | /* USER CODE END USART2_MspInit 1 */ 205 | } 206 | 207 | } 208 | 209 | /** 210 | * @brief UART MSP De-Initialization 211 | * This function freeze the hardware resources used in this example 212 | * @param huart: UART handle pointer 213 | * @retval None 214 | */ 215 | void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) 216 | { 217 | if(huart->Instance==USART2) 218 | { 219 | /* USER CODE BEGIN USART2_MspDeInit 0 */ 220 | 221 | /* USER CODE END USART2_MspDeInit 0 */ 222 | /* Peripheral clock disable */ 223 | __HAL_RCC_USART2_CLK_DISABLE(); 224 | 225 | /**USART2 GPIO Configuration 226 | PA2 ------> USART2_TX 227 | PA3 ------> USART2_RX 228 | */ 229 | HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); 230 | 231 | /* USER CODE BEGIN USART2_MspDeInit 1 */ 232 | 233 | /* USER CODE END USART2_MspDeInit 1 */ 234 | } 235 | 236 | } 237 | 238 | /* USER CODE BEGIN 1 */ 239 | 240 | /* USER CODE END 1 */ 241 | 242 | -------------------------------------------------------------------------------- /Core/Src/stm32f1xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | #include "stm32f1xx_it.h" 23 | /* Private includes ----------------------------------------------------------*/ 24 | /* USER CODE BEGIN Includes */ 25 | /* USER CODE END Includes */ 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* USER CODE BEGIN TD */ 29 | 30 | /* USER CODE END TD */ 31 | 32 | /* Private define ------------------------------------------------------------*/ 33 | /* USER CODE BEGIN PD */ 34 | 35 | /* USER CODE END PD */ 36 | 37 | /* Private macro -------------------------------------------------------------*/ 38 | /* USER CODE BEGIN PM */ 39 | 40 | /* USER CODE END PM */ 41 | 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* USER CODE BEGIN PV */ 44 | 45 | /* USER CODE END PV */ 46 | 47 | /* Private function prototypes -----------------------------------------------*/ 48 | /* USER CODE BEGIN PFP */ 49 | 50 | /* USER CODE END PFP */ 51 | 52 | /* Private user code ---------------------------------------------------------*/ 53 | /* USER CODE BEGIN 0 */ 54 | 55 | /* USER CODE END 0 */ 56 | 57 | /* External variables --------------------------------------------------------*/ 58 | extern DMA_HandleTypeDef hdma_tim2_up; 59 | /* USER CODE BEGIN EV */ 60 | 61 | /* USER CODE END EV */ 62 | 63 | /******************************************************************************/ 64 | /* Cortex-M3 Processor Interruption and Exception Handlers */ 65 | /******************************************************************************/ 66 | /** 67 | * @brief This function handles Non maskable interrupt. 68 | */ 69 | void NMI_Handler(void) 70 | { 71 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 72 | 73 | /* USER CODE END NonMaskableInt_IRQn 0 */ 74 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 75 | while (1) 76 | { 77 | } 78 | /* USER CODE END NonMaskableInt_IRQn 1 */ 79 | } 80 | 81 | /** 82 | * @brief This function handles Hard fault interrupt. 83 | */ 84 | void HardFault_Handler(void) 85 | { 86 | /* USER CODE BEGIN HardFault_IRQn 0 */ 87 | 88 | /* USER CODE END HardFault_IRQn 0 */ 89 | while (1) 90 | { 91 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 92 | /* USER CODE END W1_HardFault_IRQn 0 */ 93 | } 94 | } 95 | 96 | /** 97 | * @brief This function handles Memory management fault. 98 | */ 99 | void MemManage_Handler(void) 100 | { 101 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 102 | 103 | /* USER CODE END MemoryManagement_IRQn 0 */ 104 | while (1) 105 | { 106 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 107 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 108 | } 109 | } 110 | 111 | /** 112 | * @brief This function handles Prefetch fault, memory access fault. 113 | */ 114 | void BusFault_Handler(void) 115 | { 116 | /* USER CODE BEGIN BusFault_IRQn 0 */ 117 | 118 | /* USER CODE END BusFault_IRQn 0 */ 119 | while (1) 120 | { 121 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 122 | /* USER CODE END W1_BusFault_IRQn 0 */ 123 | } 124 | } 125 | 126 | /** 127 | * @brief This function handles Undefined instruction or illegal state. 128 | */ 129 | void UsageFault_Handler(void) 130 | { 131 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 132 | 133 | /* USER CODE END UsageFault_IRQn 0 */ 134 | while (1) 135 | { 136 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 137 | /* USER CODE END W1_UsageFault_IRQn 0 */ 138 | } 139 | } 140 | 141 | /** 142 | * @brief This function handles System service call via SWI instruction. 143 | */ 144 | void SVC_Handler(void) 145 | { 146 | /* USER CODE BEGIN SVCall_IRQn 0 */ 147 | 148 | /* USER CODE END SVCall_IRQn 0 */ 149 | /* USER CODE BEGIN SVCall_IRQn 1 */ 150 | 151 | /* USER CODE END SVCall_IRQn 1 */ 152 | } 153 | 154 | /** 155 | * @brief This function handles Debug monitor. 156 | */ 157 | void DebugMon_Handler(void) 158 | { 159 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 160 | 161 | /* USER CODE END DebugMonitor_IRQn 0 */ 162 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 163 | 164 | /* USER CODE END DebugMonitor_IRQn 1 */ 165 | } 166 | 167 | /** 168 | * @brief This function handles Pendable request for system service. 169 | */ 170 | void PendSV_Handler(void) 171 | { 172 | /* USER CODE BEGIN PendSV_IRQn 0 */ 173 | 174 | /* USER CODE END PendSV_IRQn 0 */ 175 | /* USER CODE BEGIN PendSV_IRQn 1 */ 176 | 177 | /* USER CODE END PendSV_IRQn 1 */ 178 | } 179 | 180 | /** 181 | * @brief This function handles System tick timer. 182 | */ 183 | void SysTick_Handler(void) 184 | { 185 | /* USER CODE BEGIN SysTick_IRQn 0 */ 186 | 187 | /* USER CODE END SysTick_IRQn 0 */ 188 | HAL_IncTick(); 189 | /* USER CODE BEGIN SysTick_IRQn 1 */ 190 | 191 | /* USER CODE END SysTick_IRQn 1 */ 192 | } 193 | 194 | /******************************************************************************/ 195 | /* STM32F1xx Peripheral Interrupt Handlers */ 196 | /* Add here the Interrupt Handlers for the used peripherals. */ 197 | /* For the available peripheral interrupt handler names, */ 198 | /* please refer to the startup file (startup_stm32f1xx.s). */ 199 | /******************************************************************************/ 200 | 201 | /** 202 | * @brief This function handles DMA1 channel2 global interrupt. 203 | */ 204 | void DMA1_Channel2_IRQHandler(void) 205 | { 206 | /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ 207 | 208 | /* USER CODE END DMA1_Channel2_IRQn 0 */ 209 | HAL_DMA_IRQHandler(&hdma_tim2_up); 210 | /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ 211 | 212 | /* USER CODE END DMA1_Channel2_IRQn 1 */ 213 | } 214 | 215 | /** 216 | * @brief This function handles EXTI line[15:10] interrupts. 217 | */ 218 | void EXTI15_10_IRQHandler(void) 219 | { 220 | /* USER CODE BEGIN EXTI15_10_IRQn 0 */ 221 | 222 | /* USER CODE END EXTI15_10_IRQn 0 */ 223 | HAL_GPIO_EXTI_IRQHandler(B1_Pin); 224 | /* USER CODE BEGIN EXTI15_10_IRQn 1 */ 225 | 226 | /* USER CODE END EXTI15_10_IRQn 1 */ 227 | } 228 | 229 | /* USER CODE BEGIN 1 */ 230 | 231 | /* USER CODE END 1 */ 232 | 233 | -------------------------------------------------------------------------------- /Core/Src/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2021 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | 33 | 34 | /* Variables */ 35 | extern int __io_putchar(int ch) __attribute__((weak)); 36 | extern int __io_getchar(void) __attribute__((weak)); 37 | 38 | 39 | char *__env[1] = { 0 }; 40 | char **environ = __env; 41 | 42 | 43 | /* Functions */ 44 | void initialise_monitor_handles() 45 | { 46 | } 47 | 48 | int _getpid(void) 49 | { 50 | return 1; 51 | } 52 | 53 | int _kill(int pid, int sig) 54 | { 55 | errno = EINVAL; 56 | return -1; 57 | } 58 | 59 | void _exit (int status) 60 | { 61 | _kill(status, -1); 62 | while (1) {} /* Make sure we hang here */ 63 | } 64 | 65 | __attribute__((weak)) int _read(int file, char *ptr, int len) 66 | { 67 | int DataIdx; 68 | 69 | for (DataIdx = 0; DataIdx < len; DataIdx++) 70 | { 71 | *ptr++ = __io_getchar(); 72 | } 73 | 74 | return len; 75 | } 76 | 77 | __attribute__((weak)) int _write(int file, char *ptr, int len) 78 | { 79 | int DataIdx; 80 | 81 | for (DataIdx = 0; DataIdx < len; DataIdx++) 82 | { 83 | __io_putchar(*ptr++); 84 | } 85 | return len; 86 | } 87 | 88 | int _close(int file) 89 | { 90 | return -1; 91 | } 92 | 93 | 94 | int _fstat(int file, struct stat *st) 95 | { 96 | st->st_mode = S_IFCHR; 97 | return 0; 98 | } 99 | 100 | int _isatty(int file) 101 | { 102 | return 1; 103 | } 104 | 105 | int _lseek(int file, int ptr, int dir) 106 | { 107 | return 0; 108 | } 109 | 110 | int _open(char *path, int flags, ...) 111 | { 112 | /* Pretend like we always fail */ 113 | return -1; 114 | } 115 | 116 | int _wait(int *status) 117 | { 118 | errno = ECHILD; 119 | return -1; 120 | } 121 | 122 | int _unlink(char *name) 123 | { 124 | errno = ENOENT; 125 | return -1; 126 | } 127 | 128 | int _times(struct tms *buf) 129 | { 130 | return -1; 131 | } 132 | 133 | int _stat(char *file, struct stat *st) 134 | { 135 | st->st_mode = S_IFCHR; 136 | return 0; 137 | } 138 | 139 | int _link(char *old, char *new) 140 | { 141 | errno = EMLINK; 142 | return -1; 143 | } 144 | 145 | int _fork(void) 146 | { 147 | errno = EAGAIN; 148 | return -1; 149 | } 150 | 151 | int _execve(char *name, char **argv, char **env) 152 | { 153 | errno = ENOMEM; 154 | return -1; 155 | } 156 | -------------------------------------------------------------------------------- /Core/Src/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Generated by STM32CubeIDE 5 | * @brief STM32CubeIDE System Memory calls file 6 | * 7 | * For more information about which C functions 8 | * need which of these lowlevel functions 9 | * please consult the newlib libc manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2021 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | 27 | /** 28 | * Pointer to the current high watermark of the heap usage 29 | */ 30 | static uint8_t *__sbrk_heap_end = NULL; 31 | 32 | /** 33 | * @brief _sbrk() allocates memory to the newlib heap and is used by malloc 34 | * and others from the C library 35 | * 36 | * @verbatim 37 | * ############################################################################ 38 | * # .data # .bss # newlib heap # MSP stack # 39 | * # # # # Reserved by _Min_Stack_Size # 40 | * ############################################################################ 41 | * ^-- RAM start ^-- _end _estack, RAM end --^ 42 | * @endverbatim 43 | * 44 | * This implementation starts allocating at the '_end' linker symbol 45 | * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack 46 | * The implementation considers '_estack' linker symbol to be RAM end 47 | * NOTE: If the MSP stack, at any point during execution, grows larger than the 48 | * reserved size, please increase the '_Min_Stack_Size'. 49 | * 50 | * @param incr Memory size 51 | * @return Pointer to allocated memory 52 | */ 53 | void *_sbrk(ptrdiff_t incr) 54 | { 55 | extern uint8_t _end; /* Symbol defined in the linker script */ 56 | extern uint8_t _estack; /* Symbol defined in the linker script */ 57 | extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ 58 | const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 59 | const uint8_t *max_heap = (uint8_t *)stack_limit; 60 | uint8_t *prev_heap_end; 61 | 62 | /* Initialize heap end at first call */ 63 | if (NULL == __sbrk_heap_end) 64 | { 65 | __sbrk_heap_end = &_end; 66 | } 67 | 68 | /* Protect heap from growing into the reserved MSP stack */ 69 | if (__sbrk_heap_end + incr > max_heap) 70 | { 71 | errno = ENOMEM; 72 | return (void *)-1; 73 | } 74 | 75 | prev_heap_end = __sbrk_heap_end; 76 | __sbrk_heap_end += incr; 77 | 78 | return (void *)prev_heap_end; 79 | } 80 | -------------------------------------------------------------------------------- /Core/Startup/startup_stm32f103rbtx.s: -------------------------------------------------------------------------------- 1 | /** 2 | *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ 3 | * @file startup_stm32f103xb.s 4 | * @author MCD Application Team 5 | * @brief STM32F103xB Devices vector table for Atollic toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Configure the clock system 11 | * - Branches to main in the C library (which eventually 12 | * calls main()). 13 | * After Reset the Cortex-M3 processor is in Thread mode, 14 | * priority is Privileged, and the Stack is set to Main. 15 | ****************************************************************************** 16 | * @attention 17 | * 18 | *

© Copyright (c) 2017 STMicroelectronics. 19 | * All rights reserved.

20 | * 21 | * This software component is licensed by ST under BSD 3-Clause license, 22 | * the "License"; You may not use this file except in compliance with the 23 | * License. You may obtain a copy of the License at: 24 | * opensource.org/licenses/BSD-3-Clause 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | .syntax unified 30 | .cpu cortex-m3 31 | .fpu softvfp 32 | .thumb 33 | 34 | .global g_pfnVectors 35 | .global Default_Handler 36 | 37 | /* start address for the initialization values of the .data section. 38 | defined in linker script */ 39 | .word _sidata 40 | /* start address for the .data section. defined in linker script */ 41 | .word _sdata 42 | /* end address for the .data section. defined in linker script */ 43 | .word _edata 44 | /* start address for the .bss section. defined in linker script */ 45 | .word _sbss 46 | /* end address for the .bss section. defined in linker script */ 47 | .word _ebss 48 | 49 | .equ BootRAM, 0xF108F85F 50 | /** 51 | * @brief This is the code that gets called when the processor first 52 | * starts execution following a reset event. Only the absolutely 53 | * necessary set is performed, after which the application 54 | * supplied main() routine is called. 55 | * @param None 56 | * @retval : None 57 | */ 58 | 59 | .section .text.Reset_Handler 60 | .weak Reset_Handler 61 | .type Reset_Handler, %function 62 | Reset_Handler: 63 | 64 | /* Copy the data segment initializers from flash to SRAM */ 65 | ldr r0, =_sdata 66 | ldr r1, =_edata 67 | ldr r2, =_sidata 68 | movs r3, #0 69 | b LoopCopyDataInit 70 | 71 | CopyDataInit: 72 | ldr r4, [r2, r3] 73 | str r4, [r0, r3] 74 | adds r3, r3, #4 75 | 76 | LoopCopyDataInit: 77 | adds r4, r0, r3 78 | cmp r4, r1 79 | bcc CopyDataInit 80 | 81 | /* Zero fill the bss segment. */ 82 | ldr r2, =_sbss 83 | ldr r4, =_ebss 84 | movs r3, #0 85 | b LoopFillZerobss 86 | 87 | FillZerobss: 88 | str r3, [r2] 89 | adds r2, r2, #4 90 | 91 | LoopFillZerobss: 92 | cmp r2, r4 93 | bcc FillZerobss 94 | 95 | /* Call the clock system intitialization function.*/ 96 | bl SystemInit 97 | /* Call static constructors */ 98 | bl __libc_init_array 99 | /* Call the application's entry point.*/ 100 | bl main 101 | bx lr 102 | .size Reset_Handler, .-Reset_Handler 103 | 104 | /** 105 | * @brief This is the code that gets called when the processor receives an 106 | * unexpected interrupt. This simply enters an infinite loop, preserving 107 | * the system state for examination by a debugger. 108 | * 109 | * @param None 110 | * @retval : None 111 | */ 112 | .section .text.Default_Handler,"ax",%progbits 113 | Default_Handler: 114 | Infinite_Loop: 115 | b Infinite_Loop 116 | .size Default_Handler, .-Default_Handler 117 | /****************************************************************************** 118 | * 119 | * The minimal vector table for a Cortex M3. Note that the proper constructs 120 | * must be placed on this to ensure that it ends up at physical address 121 | * 0x0000.0000. 122 | * 123 | ******************************************************************************/ 124 | .section .isr_vector,"a",%progbits 125 | .type g_pfnVectors, %object 126 | .size g_pfnVectors, .-g_pfnVectors 127 | 128 | 129 | g_pfnVectors: 130 | 131 | .word _estack 132 | .word Reset_Handler 133 | .word NMI_Handler 134 | .word HardFault_Handler 135 | .word MemManage_Handler 136 | .word BusFault_Handler 137 | .word UsageFault_Handler 138 | .word 0 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word SVC_Handler 143 | .word DebugMon_Handler 144 | .word 0 145 | .word PendSV_Handler 146 | .word SysTick_Handler 147 | .word WWDG_IRQHandler 148 | .word PVD_IRQHandler 149 | .word TAMPER_IRQHandler 150 | .word RTC_IRQHandler 151 | .word FLASH_IRQHandler 152 | .word RCC_IRQHandler 153 | .word EXTI0_IRQHandler 154 | .word EXTI1_IRQHandler 155 | .word EXTI2_IRQHandler 156 | .word EXTI3_IRQHandler 157 | .word EXTI4_IRQHandler 158 | .word DMA1_Channel1_IRQHandler 159 | .word DMA1_Channel2_IRQHandler 160 | .word DMA1_Channel3_IRQHandler 161 | .word DMA1_Channel4_IRQHandler 162 | .word DMA1_Channel5_IRQHandler 163 | .word DMA1_Channel6_IRQHandler 164 | .word DMA1_Channel7_IRQHandler 165 | .word ADC1_2_IRQHandler 166 | .word USB_HP_CAN1_TX_IRQHandler 167 | .word USB_LP_CAN1_RX0_IRQHandler 168 | .word CAN1_RX1_IRQHandler 169 | .word CAN1_SCE_IRQHandler 170 | .word EXTI9_5_IRQHandler 171 | .word TIM1_BRK_IRQHandler 172 | .word TIM1_UP_IRQHandler 173 | .word TIM1_TRG_COM_IRQHandler 174 | .word TIM1_CC_IRQHandler 175 | .word TIM2_IRQHandler 176 | .word TIM3_IRQHandler 177 | .word TIM4_IRQHandler 178 | .word I2C1_EV_IRQHandler 179 | .word I2C1_ER_IRQHandler 180 | .word I2C2_EV_IRQHandler 181 | .word I2C2_ER_IRQHandler 182 | .word SPI1_IRQHandler 183 | .word SPI2_IRQHandler 184 | .word USART1_IRQHandler 185 | .word USART2_IRQHandler 186 | .word USART3_IRQHandler 187 | .word EXTI15_10_IRQHandler 188 | .word RTC_Alarm_IRQHandler 189 | .word USBWakeUp_IRQHandler 190 | .word 0 191 | .word 0 192 | .word 0 193 | .word 0 194 | .word 0 195 | .word 0 196 | .word 0 197 | .word BootRAM /* @0x108. This is for boot in RAM mode for 198 | STM32F10x Medium Density devices. */ 199 | 200 | /******************************************************************************* 201 | * 202 | * Provide weak aliases for each Exception handler to the Default_Handler. 203 | * As they are weak aliases, any function with the same name will override 204 | * this definition. 205 | * 206 | *******************************************************************************/ 207 | 208 | .weak NMI_Handler 209 | .thumb_set NMI_Handler,Default_Handler 210 | 211 | .weak HardFault_Handler 212 | .thumb_set HardFault_Handler,Default_Handler 213 | 214 | .weak MemManage_Handler 215 | .thumb_set MemManage_Handler,Default_Handler 216 | 217 | .weak BusFault_Handler 218 | .thumb_set BusFault_Handler,Default_Handler 219 | 220 | .weak UsageFault_Handler 221 | .thumb_set UsageFault_Handler,Default_Handler 222 | 223 | .weak SVC_Handler 224 | .thumb_set SVC_Handler,Default_Handler 225 | 226 | .weak DebugMon_Handler 227 | .thumb_set DebugMon_Handler,Default_Handler 228 | 229 | .weak PendSV_Handler 230 | .thumb_set PendSV_Handler,Default_Handler 231 | 232 | .weak SysTick_Handler 233 | .thumb_set SysTick_Handler,Default_Handler 234 | 235 | .weak WWDG_IRQHandler 236 | .thumb_set WWDG_IRQHandler,Default_Handler 237 | 238 | .weak PVD_IRQHandler 239 | .thumb_set PVD_IRQHandler,Default_Handler 240 | 241 | .weak TAMPER_IRQHandler 242 | .thumb_set TAMPER_IRQHandler,Default_Handler 243 | 244 | .weak RTC_IRQHandler 245 | .thumb_set RTC_IRQHandler,Default_Handler 246 | 247 | .weak FLASH_IRQHandler 248 | .thumb_set FLASH_IRQHandler,Default_Handler 249 | 250 | .weak RCC_IRQHandler 251 | .thumb_set RCC_IRQHandler,Default_Handler 252 | 253 | .weak EXTI0_IRQHandler 254 | .thumb_set EXTI0_IRQHandler,Default_Handler 255 | 256 | .weak EXTI1_IRQHandler 257 | .thumb_set EXTI1_IRQHandler,Default_Handler 258 | 259 | .weak EXTI2_IRQHandler 260 | .thumb_set EXTI2_IRQHandler,Default_Handler 261 | 262 | .weak EXTI3_IRQHandler 263 | .thumb_set EXTI3_IRQHandler,Default_Handler 264 | 265 | .weak EXTI4_IRQHandler 266 | .thumb_set EXTI4_IRQHandler,Default_Handler 267 | 268 | .weak DMA1_Channel1_IRQHandler 269 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 270 | 271 | .weak DMA1_Channel2_IRQHandler 272 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 273 | 274 | .weak DMA1_Channel3_IRQHandler 275 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 276 | 277 | .weak DMA1_Channel4_IRQHandler 278 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 279 | 280 | .weak DMA1_Channel5_IRQHandler 281 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 282 | 283 | .weak DMA1_Channel6_IRQHandler 284 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 285 | 286 | .weak DMA1_Channel7_IRQHandler 287 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 288 | 289 | .weak ADC1_2_IRQHandler 290 | .thumb_set ADC1_2_IRQHandler,Default_Handler 291 | 292 | .weak USB_HP_CAN1_TX_IRQHandler 293 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 294 | 295 | .weak USB_LP_CAN1_RX0_IRQHandler 296 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 297 | 298 | .weak CAN1_RX1_IRQHandler 299 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 300 | 301 | .weak CAN1_SCE_IRQHandler 302 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 303 | 304 | .weak EXTI9_5_IRQHandler 305 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 306 | 307 | .weak TIM1_BRK_IRQHandler 308 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 309 | 310 | .weak TIM1_UP_IRQHandler 311 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 312 | 313 | .weak TIM1_TRG_COM_IRQHandler 314 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 315 | 316 | .weak TIM1_CC_IRQHandler 317 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 318 | 319 | .weak TIM2_IRQHandler 320 | .thumb_set TIM2_IRQHandler,Default_Handler 321 | 322 | .weak TIM3_IRQHandler 323 | .thumb_set TIM3_IRQHandler,Default_Handler 324 | 325 | .weak TIM4_IRQHandler 326 | .thumb_set TIM4_IRQHandler,Default_Handler 327 | 328 | .weak I2C1_EV_IRQHandler 329 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 330 | 331 | .weak I2C1_ER_IRQHandler 332 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 333 | 334 | .weak I2C2_EV_IRQHandler 335 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 336 | 337 | .weak I2C2_ER_IRQHandler 338 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 339 | 340 | .weak SPI1_IRQHandler 341 | .thumb_set SPI1_IRQHandler,Default_Handler 342 | 343 | .weak SPI2_IRQHandler 344 | .thumb_set SPI2_IRQHandler,Default_Handler 345 | 346 | .weak USART1_IRQHandler 347 | .thumb_set USART1_IRQHandler,Default_Handler 348 | 349 | .weak USART2_IRQHandler 350 | .thumb_set USART2_IRQHandler,Default_Handler 351 | 352 | .weak USART3_IRQHandler 353 | .thumb_set USART3_IRQHandler,Default_Handler 354 | 355 | .weak EXTI15_10_IRQHandler 356 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 357 | 358 | .weak RTC_Alarm_IRQHandler 359 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler 360 | 361 | .weak USBWakeUp_IRQHandler 362 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 363 | 364 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 365 | 366 | -------------------------------------------------------------------------------- /Debug/Core/Src/subdir.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | # Toolchain: GNU Tools for STM32 (9-2020-q2-update) 4 | ################################################################################ 5 | 6 | # Add inputs and outputs from these tool invocations to the build variables 7 | C_SRCS += \ 8 | ../Core/Src/main.c \ 9 | ../Core/Src/stm32f1xx_hal_msp.c \ 10 | ../Core/Src/stm32f1xx_it.c \ 11 | ../Core/Src/syscalls.c \ 12 | ../Core/Src/sysmem.c \ 13 | ../Core/Src/system_stm32f1xx.c 14 | 15 | OBJS += \ 16 | ./Core/Src/main.o \ 17 | ./Core/Src/stm32f1xx_hal_msp.o \ 18 | ./Core/Src/stm32f1xx_it.o \ 19 | ./Core/Src/syscalls.o \ 20 | ./Core/Src/sysmem.o \ 21 | ./Core/Src/system_stm32f1xx.o 22 | 23 | C_DEPS += \ 24 | ./Core/Src/main.d \ 25 | ./Core/Src/stm32f1xx_hal_msp.d \ 26 | ./Core/Src/stm32f1xx_it.d \ 27 | ./Core/Src/syscalls.d \ 28 | ./Core/Src/sysmem.d \ 29 | ./Core/Src/system_stm32f1xx.d 30 | 31 | 32 | # Each subdirectory must supply rules for building sources it contributes 33 | Core/Src/%.o: ../Core/Src/%.c Core/Src/subdir.mk 34 | arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Core/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" 35 | 36 | clean: clean-Core-2f-Src 37 | 38 | clean-Core-2f-Src: 39 | -$(RM) ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/stm32f1xx_hal_msp.d ./Core/Src/stm32f1xx_hal_msp.o ./Core/Src/stm32f1xx_it.d ./Core/Src/stm32f1xx_it.o ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/system_stm32f1xx.d ./Core/Src/system_stm32f1xx.o 40 | 41 | .PHONY: clean-Core-2f-Src 42 | 43 | -------------------------------------------------------------------------------- /Debug/Core/Startup/subdir.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | # Toolchain: GNU Tools for STM32 (9-2020-q2-update) 4 | ################################################################################ 5 | 6 | # Add inputs and outputs from these tool invocations to the build variables 7 | S_SRCS += \ 8 | ../Core/Startup/startup_stm32f103rbtx.s 9 | 10 | OBJS += \ 11 | ./Core/Startup/startup_stm32f103rbtx.o 12 | 13 | S_DEPS += \ 14 | ./Core/Startup/startup_stm32f103rbtx.d 15 | 16 | 17 | # Each subdirectory must supply rules for building sources it contributes 18 | Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk 19 | arm-none-eabi-gcc -mcpu=cortex-m3 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" 20 | 21 | clean: clean-Core-2f-Startup 22 | 23 | clean-Core-2f-Startup: 24 | -$(RM) ./Core/Startup/startup_stm32f103rbtx.d ./Core/Startup/startup_stm32f103rbtx.o 25 | 26 | .PHONY: clean-Core-2f-Startup 27 | 28 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | # Toolchain: GNU Tools for STM32 (9-2020-q2-update) 4 | ################################################################################ 5 | 6 | # Add inputs and outputs from these tool invocations to the build variables 7 | C_SRCS += \ 8 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c \ 9 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \ 10 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \ 11 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \ 12 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \ 13 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \ 14 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \ 15 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \ 16 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \ 17 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \ 18 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \ 19 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \ 20 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \ 21 | ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c 22 | 23 | OBJS += \ 24 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o \ 25 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o \ 26 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o \ 27 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o \ 28 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o \ 29 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o \ 30 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o \ 31 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o \ 32 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o \ 33 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o \ 34 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o \ 35 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o \ 36 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o \ 37 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o 38 | 39 | C_DEPS += \ 40 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d \ 41 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d \ 42 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d \ 43 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d \ 44 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d \ 45 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d \ 46 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d \ 47 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d \ 48 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d \ 49 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d \ 50 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d \ 51 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d \ 52 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d \ 53 | ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d 54 | 55 | 56 | # Each subdirectory must supply rules for building sources it contributes 57 | Drivers/STM32F1xx_HAL_Driver/Src/%.o: ../Drivers/STM32F1xx_HAL_Driver/Src/%.c Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk 58 | arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Core/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" 59 | 60 | clean: clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src 61 | 62 | clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src: 63 | -$(RM) ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o 64 | 65 | .PHONY: clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src 66 | 67 | -------------------------------------------------------------------------------- /Debug/STM32_PatternDriver.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mnemocron/STM32_PatternDriver/40dce761e0c979a7873f4907c1cb0b7e466fba1e/Debug/STM32_PatternDriver.bin -------------------------------------------------------------------------------- /Debug/makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | # Toolchain: GNU Tools for STM32 (9-2020-q2-update) 4 | ################################################################################ 5 | 6 | -include ../makefile.init 7 | 8 | RM := rm -rf 9 | 10 | # All of the sources participating in the build are defined here 11 | -include sources.mk 12 | -include Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk 13 | -include Core/Startup/subdir.mk 14 | -include Core/Src/subdir.mk 15 | -include objects.mk 16 | 17 | ifneq ($(MAKECMDGOALS),clean) 18 | ifneq ($(strip $(S_DEPS)),) 19 | -include $(S_DEPS) 20 | endif 21 | ifneq ($(strip $(S_UPPER_DEPS)),) 22 | -include $(S_UPPER_DEPS) 23 | endif 24 | ifneq ($(strip $(C_DEPS)),) 25 | -include $(C_DEPS) 26 | endif 27 | endif 28 | 29 | -include ../makefile.defs 30 | 31 | OPTIONAL_TOOL_DEPS := \ 32 | $(wildcard ../makefile.defs) \ 33 | $(wildcard ../makefile.init) \ 34 | $(wildcard ../makefile.targets) \ 35 | 36 | 37 | BUILD_ARTIFACT_NAME := STM32_PatternDriver 38 | BUILD_ARTIFACT_EXTENSION := elf 39 | BUILD_ARTIFACT_PREFIX := 40 | BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) 41 | 42 | # Add inputs and outputs from these tool invocations to the build variables 43 | EXECUTABLES += \ 44 | STM32_PatternDriver.elf \ 45 | 46 | SIZE_OUTPUT += \ 47 | default.size.stdout \ 48 | 49 | OBJDUMP_LIST += \ 50 | STM32_PatternDriver.list \ 51 | 52 | OBJCOPY_BIN += \ 53 | STM32_PatternDriver.bin \ 54 | 55 | 56 | # All Target 57 | all: main-build 58 | 59 | # Main-build Target 60 | main-build: STM32_PatternDriver.elf secondary-outputs 61 | 62 | # Tool invocations 63 | STM32_PatternDriver.elf: $(OBJS) $(USER_OBJS) C:\Users\simon\Documents\STM32\cubeide\STM32_PatternDriver\STM32F103RBTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) 64 | arm-none-eabi-gcc -o "STM32_PatternDriver.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m3 -T"C:\Users\simon\Documents\STM32\cubeide\STM32_PatternDriver\STM32F103RBTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="STM32_PatternDriver.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group 65 | @echo 'Finished building target: $@' 66 | @echo ' ' 67 | 68 | default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) 69 | arm-none-eabi-size $(EXECUTABLES) 70 | @echo 'Finished building: $@' 71 | @echo ' ' 72 | 73 | STM32_PatternDriver.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) 74 | arm-none-eabi-objdump -h -S $(EXECUTABLES) > "STM32_PatternDriver.list" 75 | @echo 'Finished building: $@' 76 | @echo ' ' 77 | 78 | STM32_PatternDriver.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) 79 | arm-none-eabi-objcopy -O binary $(EXECUTABLES) "STM32_PatternDriver.bin" 80 | @echo 'Finished building: $@' 81 | @echo ' ' 82 | 83 | # Other Targets 84 | clean: 85 | -$(RM) STM32_PatternDriver.bin STM32_PatternDriver.elf STM32_PatternDriver.list default.size.stdout 86 | -@echo ' ' 87 | 88 | secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) 89 | 90 | fail-specified-linker-script-missing: 91 | @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' 92 | @exit 2 93 | 94 | warn-no-linker-script-specified: 95 | @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' 96 | 97 | .PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified 98 | 99 | -include ../makefile.targets 100 | -------------------------------------------------------------------------------- /Debug/objects.list: -------------------------------------------------------------------------------- 1 | "./Core/Src/main.o" 2 | "./Core/Src/stm32f1xx_hal_msp.o" 3 | "./Core/Src/stm32f1xx_it.o" 4 | "./Core/Src/syscalls.o" 5 | "./Core/Src/sysmem.o" 6 | "./Core/Src/system_stm32f1xx.o" 7 | "./Core/Startup/startup_stm32f103rbtx.o" 8 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o" 9 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o" 10 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o" 11 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o" 12 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o" 13 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o" 14 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o" 15 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o" 16 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o" 17 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o" 18 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o" 19 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o" 20 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o" 21 | "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o" 22 | -------------------------------------------------------------------------------- /Debug/objects.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | # Toolchain: GNU Tools for STM32 (9-2020-q2-update) 4 | ################################################################################ 5 | 6 | USER_OBJS := 7 | 8 | LIBS := 9 | 10 | -------------------------------------------------------------------------------- /Debug/sources.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | # Toolchain: GNU Tools for STM32 (9-2020-q2-update) 4 | ################################################################################ 5 | 6 | ELF_SRCS := 7 | OBJ_SRCS := 8 | S_SRCS := 9 | C_SRCS := 10 | S_UPPER_SRCS := 11 | O_SRCS := 12 | SIZE_OUTPUT := 13 | OBJDUMP_LIST := 14 | EXECUTABLES := 15 | OBJS := 16 | S_DEPS := 17 | S_UPPER_DEPS := 18 | C_DEPS := 19 | OBJCOPY_BIN := 20 | 21 | # Every subdirectory with source files must be described here 22 | SUBDIRS := \ 23 | Core/Src \ 24 | Core/Startup \ 25 | Drivers/STM32F1xx_HAL_Driver/Src \ 26 | 27 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mnemocron/STM32_PatternDriver/40dce761e0c979a7873f4907c1cb0b7e466fba1e/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mnemocron/STM32_PatternDriver/40dce761e0c979a7873f4907c1cb0b7e466fba1e/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /** @addtogroup CMSIS 21 | * @{ 22 | */ 23 | 24 | /** @addtogroup stm32f10x_system 25 | * @{ 26 | */ 27 | 28 | /** 29 | * @brief Define to prevent recursive inclusion 30 | */ 31 | #ifndef __SYSTEM_STM32F10X_H 32 | #define __SYSTEM_STM32F10X_H 33 | 34 | #ifdef __cplusplus 35 | extern "C" { 36 | #endif 37 | 38 | /** @addtogroup STM32F10x_System_Includes 39 | * @{ 40 | */ 41 | 42 | /** 43 | * @} 44 | */ 45 | 46 | 47 | /** @addtogroup STM32F10x_System_Exported_types 48 | * @{ 49 | */ 50 | 51 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 52 | extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ 53 | extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @addtogroup STM32F10x_System_Exported_Constants 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F10x_System_Exported_Macros 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F10x_System_Exported_Functions 76 | * @{ 77 | */ 78 | 79 | extern void SystemInit(void); 80 | extern void SystemCoreClockUpdate(void); 81 | /** 82 | * @} 83 | */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /*__SYSTEM_STM32F10X_H */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 99 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/License.md: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. Definitions. 8 | 9 | "License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. 10 | 11 | "Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. 12 | 13 | "Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. 14 | 15 | "You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License. 16 | 17 | "Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files. 18 | 19 | "Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types. 20 | 21 | "Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below). 22 | 23 | "Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof. 24 | 25 | "Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution." 26 | 27 | "Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work. 28 | 29 | 2. Grant of Copyright License. 30 | 31 | Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form. 32 | 33 | 3. Grant of Patent License. 34 | 35 | Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed. 36 | 37 | 4. Redistribution. 38 | 39 | You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions: 40 | 1.You must give any other recipients of the Work or Derivative Works a copy of this License; and 41 | 2.You must cause any modified files to carry prominent notices stating that You changed the files; and 42 | 3.You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and 43 | 4.If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License. 44 | 45 | You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License. 46 | 47 | 5. Submission of Contributions. 48 | 49 | Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions. 50 | 51 | 6. Trademarks. 52 | 53 | This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file. 54 | 55 | 7. Disclaimer of Warranty. 56 | 57 | Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License. 58 | 59 | 8. Limitation of Liability. 60 | 61 | In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages. 62 | 63 | 9. Accepting Warranty or Additional Liability. 64 | 65 | While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. 66 | 67 | END OF TERMS AND CONDITIONS 68 | 69 | APPENDIX: 70 | 71 | Copyright [2019] [STMicroelectronics] 72 | 73 | Licensed under the Apache License, Version 2.0 (the "License"); 74 | you may not use this file except in compliance with the License. 75 | You may obtain a copy of the License at 76 | 77 | http://www.apache.org/licenses/LICENSE-2.0 78 | 79 | Unless required by applicable law or agreed to in writing, software 80 | distributed under the License is distributed on an "AS IS" BASIS, 81 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 82 | See the License for the specific language governing permissions and 83 | limitations under the License. -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6 (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 41 | #include "cmsis_armclang.h" 42 | 43 | 44 | /* 45 | * GNU Compiler 46 | */ 47 | #elif defined ( __GNUC__ ) 48 | #include "cmsis_gcc.h" 49 | 50 | 51 | /* 52 | * IAR Compiler 53 | */ 54 | #elif defined ( __ICCARM__ ) 55 | #include 56 | 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined ( __TI_ARM__ ) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 97 | #endif 98 | #ifndef __UNALIGNED_UINT16_WRITE 99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT16_READ 103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 105 | #endif 106 | #ifndef __UNALIGNED_UINT32_WRITE 107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 109 | #endif 110 | #ifndef __UNALIGNED_UINT32_READ 111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 113 | #endif 114 | #ifndef __ALIGNED 115 | #define __ALIGNED(x) __attribute__((aligned(x))) 116 | #endif 117 | #ifndef __RESTRICT 118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 119 | #define __RESTRICT 120 | #endif 121 | 122 | 123 | /* 124 | * TASKING Compiler 125 | */ 126 | #elif defined ( __TASKING__ ) 127 | /* 128 | * The CMSIS functions have been implemented as intrinsics in the compiler. 129 | * Please use "carm -?i" to get an up to date list of all intrinsics, 130 | * Including the CMSIS ones. 131 | */ 132 | 133 | #ifndef __ASM 134 | #define __ASM __asm 135 | #endif 136 | #ifndef __INLINE 137 | #define __INLINE inline 138 | #endif 139 | #ifndef __STATIC_INLINE 140 | #define __STATIC_INLINE static inline 141 | #endif 142 | #ifndef __STATIC_FORCEINLINE 143 | #define __STATIC_FORCEINLINE __STATIC_INLINE 144 | #endif 145 | #ifndef __NO_RETURN 146 | #define __NO_RETURN __attribute__((noreturn)) 147 | #endif 148 | #ifndef __USED 149 | #define __USED __attribute__((used)) 150 | #endif 151 | #ifndef __WEAK 152 | #define __WEAK __attribute__((weak)) 153 | #endif 154 | #ifndef __PACKED 155 | #define __PACKED __packed__ 156 | #endif 157 | #ifndef __PACKED_STRUCT 158 | #define __PACKED_STRUCT struct __packed__ 159 | #endif 160 | #ifndef __PACKED_UNION 161 | #define __PACKED_UNION union __packed__ 162 | #endif 163 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 164 | struct __packed__ T_UINT32 { uint32_t v; }; 165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 166 | #endif 167 | #ifndef __UNALIGNED_UINT16_WRITE 168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 170 | #endif 171 | #ifndef __UNALIGNED_UINT16_READ 172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 174 | #endif 175 | #ifndef __UNALIGNED_UINT32_WRITE 176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 178 | #endif 179 | #ifndef __UNALIGNED_UINT32_READ 180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 182 | #endif 183 | #ifndef __ALIGNED 184 | #define __ALIGNED(x) __align(x) 185 | #endif 186 | #ifndef __RESTRICT 187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 188 | #define __RESTRICT 189 | #endif 190 | 191 | 192 | /* 193 | * COSMIC Compiler 194 | */ 195 | #elif defined ( __CSMC__ ) 196 | #include 197 | 198 | #ifndef __ASM 199 | #define __ASM _asm 200 | #endif 201 | #ifndef __INLINE 202 | #define __INLINE inline 203 | #endif 204 | #ifndef __STATIC_INLINE 205 | #define __STATIC_INLINE static inline 206 | #endif 207 | #ifndef __STATIC_FORCEINLINE 208 | #define __STATIC_FORCEINLINE __STATIC_INLINE 209 | #endif 210 | #ifndef __NO_RETURN 211 | // NO RETURN is automatically detected hence no warning here 212 | #define __NO_RETURN 213 | #endif 214 | #ifndef __USED 215 | #warning No compiler specific solution for __USED. __USED is ignored. 216 | #define __USED 217 | #endif 218 | #ifndef __WEAK 219 | #define __WEAK __weak 220 | #endif 221 | #ifndef __PACKED 222 | #define __PACKED @packed 223 | #endif 224 | #ifndef __PACKED_STRUCT 225 | #define __PACKED_STRUCT @packed struct 226 | #endif 227 | #ifndef __PACKED_UNION 228 | #define __PACKED_UNION @packed union 229 | #endif 230 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 231 | @packed struct T_UINT32 { uint32_t v; }; 232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 233 | #endif 234 | #ifndef __UNALIGNED_UINT16_WRITE 235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 237 | #endif 238 | #ifndef __UNALIGNED_UINT16_READ 239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 241 | #endif 242 | #ifndef __UNALIGNED_UINT32_WRITE 243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 245 | #endif 246 | #ifndef __UNALIGNED_UINT32_READ 247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 249 | #endif 250 | #ifndef __ALIGNED 251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 252 | #define __ALIGNED(x) 253 | #endif 254 | #ifndef __RESTRICT 255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 256 | #define __RESTRICT 257 | #endif 258 | 259 | 260 | #else 261 | #error Unknown compiler. 262 | #endif 263 | 264 | 265 | #endif /* __CMSIS_COMPILER_H */ 266 | 267 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.2 5 | * @date 19. April 2017 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 107 | 108 | /** 109 | * MPU Region Attribute and Size Register Value 110 | * 111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 114 | * \param IsShareable Region is shareable between multiple bus masters. 115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 117 | * \param SubRegionDisable Sub-region disable field. 118 | * \param Size Region size of the region to be configured, for example 4K, 8K. 119 | */ 120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 122 | 123 | /** 124 | * MPU Memory Access Attribute for strongly ordered memory. 125 | * - TEX: 000b 126 | * - Shareable 127 | * - Non-cacheable 128 | * - Non-bufferable 129 | */ 130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 131 | 132 | /** 133 | * MPU Memory Access Attribute for device memory. 134 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 135 | * - Shareable or non-shareable 136 | * - Non-cacheable 137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 138 | * 139 | * \param IsShareable Configures the device memory as shareable or non-shareable. 140 | */ 141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 142 | 143 | /** 144 | * MPU Memory Access Attribute for normal memory. 145 | * - TEX: 1BBb (reflecting outer cacheability rules) 146 | * - Shareable or non-shareable 147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 149 | * 150 | * \param OuterCp Configures the outer cache policy. 151 | * \param InnerCp Configures the inner cache policy. 152 | * \param IsShareable Configures the memory as shareable or non-shareable. 153 | */ 154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 155 | 156 | /** 157 | * MPU Memory Access Attribute non-cacheable policy. 158 | */ 159 | #define ARM_MPU_CACHEP_NOCACHE 0U 160 | 161 | /** 162 | * MPU Memory Access Attribute write-back, write and read allocate policy. 163 | */ 164 | #define ARM_MPU_CACHEP_WB_WRA 1U 165 | 166 | /** 167 | * MPU Memory Access Attribute write-through, no write allocate policy. 168 | */ 169 | #define ARM_MPU_CACHEP_WT_NWA 2U 170 | 171 | /** 172 | * MPU Memory Access Attribute write-back, no write allocate policy. 173 | */ 174 | #define ARM_MPU_CACHEP_WB_NWA 3U 175 | 176 | 177 | /** 178 | * Struct for a single MPU Region 179 | */ 180 | typedef struct { 181 | uint32_t RBAR; //!< The region base address register value (RBAR) 182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 183 | } ARM_MPU_Region_t; 184 | 185 | /** Enable the MPU. 186 | * \param MPU_Control Default access permissions for unconfigured regions. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 189 | { 190 | __DSB(); 191 | __ISB(); 192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 195 | #endif 196 | } 197 | 198 | /** Disable the MPU. 199 | */ 200 | __STATIC_INLINE void ARM_MPU_Disable(void) 201 | { 202 | __DSB(); 203 | __ISB(); 204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 206 | #endif 207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 208 | } 209 | 210 | /** Clear and disable the given MPU region. 211 | * \param rnr Region number to be cleared. 212 | */ 213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 214 | { 215 | MPU->RNR = rnr; 216 | MPU->RASR = 0U; 217 | } 218 | 219 | /** Configure an MPU region. 220 | * \param rbar Value for RBAR register. 221 | * \param rsar Value for RSAR register. 222 | */ 223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 224 | { 225 | MPU->RBAR = rbar; 226 | MPU->RASR = rasr; 227 | } 228 | 229 | /** Configure the given MPU region. 230 | * \param rnr Region number to be configured. 231 | * \param rbar Value for RBAR register. 232 | * \param rsar Value for RSAR register. 233 | */ 234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 235 | { 236 | MPU->RNR = rnr; 237 | MPU->RBAR = rbar; 238 | MPU->RASR = rasr; 239 | } 240 | 241 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 242 | * \param dst Destination data is copied to. 243 | * \param src Source data is copied from. 244 | * \param len Amount of data words to be copied. 245 | */ 246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 247 | { 248 | uint32_t i; 249 | for (i = 0U; i < len; ++i) 250 | { 251 | dst[i] = src[i]; 252 | } 253 | } 254 | 255 | /** Load the given number of MPU regions from a table. 256 | * \param table Pointer to the MPU configuration table. 257 | * \param cnt Amount of regions to be configured. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 260 | { 261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 262 | while (cnt > MPU_TYPE_RALIASES) { 263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 264 | table += MPU_TYPE_RALIASES; 265 | cnt -= MPU_TYPE_RALIASES; 266 | } 267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 268 | } 269 | 270 | #endif 271 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct { 108 | uint32_t RBAR; /*!< Region Base Address Register value */ 109 | uint32_t RLAR; /*!< Region Limit Address Register value */ 110 | } ARM_MPU_Region_t; 111 | 112 | /** Enable the MPU. 113 | * \param MPU_Control Default access permissions for unconfigured regions. 114 | */ 115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 116 | { 117 | __DSB(); 118 | __ISB(); 119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 122 | #endif 123 | } 124 | 125 | /** Disable the MPU. 126 | */ 127 | __STATIC_INLINE void ARM_MPU_Disable(void) 128 | { 129 | __DSB(); 130 | __ISB(); 131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 133 | #endif 134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 135 | } 136 | 137 | #ifdef MPU_NS 138 | /** Enable the Non-secure MPU. 139 | * \param MPU_Control Default access permissions for unconfigured regions. 140 | */ 141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 142 | { 143 | __DSB(); 144 | __ISB(); 145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 148 | #endif 149 | } 150 | 151 | /** Disable the Non-secure MPU. 152 | */ 153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 154 | { 155 | __DSB(); 156 | __ISB(); 157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 159 | #endif 160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 161 | } 162 | #endif 163 | 164 | /** Set the memory attribute encoding to the given MPU. 165 | * \param mpu Pointer to the MPU to be configured. 166 | * \param idx The attribute index to be set [0-7] 167 | * \param attr The attribute value to be set. 168 | */ 169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 170 | { 171 | const uint8_t reg = idx / 4U; 172 | const uint32_t pos = ((idx % 4U) * 8U); 173 | const uint32_t mask = 0xFFU << pos; 174 | 175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 176 | return; // invalid index 177 | } 178 | 179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 180 | } 181 | 182 | /** Set the memory attribute encoding. 183 | * \param idx The attribute index to be set [0-7] 184 | * \param attr The attribute value to be set. 185 | */ 186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 187 | { 188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 189 | } 190 | 191 | #ifdef MPU_NS 192 | /** Set the memory attribute encoding to the Non-secure MPU. 193 | * \param idx The attribute index to be set [0-7] 194 | * \param attr The attribute value to be set. 195 | */ 196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 197 | { 198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 199 | } 200 | #endif 201 | 202 | /** Clear and disable the given MPU region of the given MPU. 203 | * \param mpu Pointer to MPU to be used. 204 | * \param rnr Region number to be cleared. 205 | */ 206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 207 | { 208 | mpu->RNR = rnr; 209 | mpu->RLAR = 0U; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | ARM_MPU_ClrRegionEx(MPU, rnr); 218 | } 219 | 220 | #ifdef MPU_NS 221 | /** Clear and disable the given Non-secure MPU region. 222 | * \param rnr Region number to be cleared. 223 | */ 224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 225 | { 226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 227 | } 228 | #endif 229 | 230 | /** Configure the given MPU region of the given MPU. 231 | * \param mpu Pointer to MPU to be used. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rlar Value for RLAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 237 | { 238 | mpu->RNR = rnr; 239 | mpu->RBAR = rbar; 240 | mpu->RLAR = rlar; 241 | } 242 | 243 | /** Configure the given MPU region. 244 | * \param rnr Region number to be configured. 245 | * \param rbar Value for RBAR register. 246 | * \param rlar Value for RLAR register. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 249 | { 250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 251 | } 252 | 253 | #ifdef MPU_NS 254 | /** Configure the given Non-secure MPU region. 255 | * \param rnr Region number to be configured. 256 | * \param rbar Value for RBAR register. 257 | * \param rlar Value for RLAR register. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 260 | { 261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 262 | } 263 | #endif 264 | 265 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 266 | * \param dst Destination data is copied to. 267 | * \param src Source data is copied from. 268 | * \param len Amount of data words to be copied. 269 | */ 270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 271 | { 272 | uint32_t i; 273 | for (i = 0U; i < len; ++i) 274 | { 275 | dst[i] = src[i]; 276 | } 277 | } 278 | 279 | /** Load the given number of MPU regions from a table to the given MPU. 280 | * \param mpu Pointer to the MPU registers to be used. 281 | * \param rnr First region number to be configured. 282 | * \param table Pointer to the MPU configuration table. 283 | * \param cnt Amount of regions to be configured. 284 | */ 285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 286 | { 287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 288 | if (cnt == 1U) { 289 | mpu->RNR = rnr; 290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 291 | } else { 292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 294 | 295 | mpu->RNR = rnrBase; 296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 299 | table += c; 300 | cnt -= c; 301 | rnrOffset = 0U; 302 | rnrBase += MPU_TYPE_RALIASES; 303 | mpu->RNR = rnrBase; 304 | } 305 | 306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 307 | } 308 | } 309 | 310 | /** Load the given number of MPU regions from a table. 311 | * \param rnr First region number to be configured. 312 | * \param table Pointer to the MPU configuration table. 313 | * \param cnt Amount of regions to be configured. 314 | */ 315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 316 | { 317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 318 | } 319 | 320 | #ifdef MPU_NS 321 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 322 | * \param rnr First region number to be configured. 323 | * \param table Pointer to the MPU configuration table. 324 | * \param cnt Amount of regions to be configured. 325 | */ 326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 327 | { 328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 329 | } 330 | #endif 331 | 332 | #endif 333 | 334 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. Definitions. 8 | 9 | "License" shall mean the terms and conditions for use, reproduction, 10 | and distribution as defined by Sections 1 through 9 of this document. 11 | 12 | "Licensor" shall mean the copyright owner or entity authorized by 13 | the copyright owner that is granting the License. 14 | 15 | "Legal Entity" shall mean the union of the acting entity and all 16 | other entities that control, are controlled by, or are under common 17 | control with that entity. For the purposes of this definition, 18 | "control" means (i) the power, direct or indirect, to cause the 19 | direction or management of such entity, whether by contract or 20 | otherwise, or (ii) ownership of fifty percent (50%) or more of the 21 | outstanding shares, or (iii) beneficial ownership of such entity. 22 | 23 | "You" (or "Your") shall mean an individual or Legal Entity 24 | exercising permissions granted by this License. 25 | 26 | "Source" form shall mean the preferred form for making modifications, 27 | including but not limited to software source code, documentation 28 | source, and configuration files. 29 | 30 | "Object" form shall mean any form resulting from mechanical 31 | transformation or translation of a Source form, including but 32 | not limited to compiled object code, generated documentation, 33 | and conversions to other media types. 34 | 35 | "Work" shall mean the work of authorship, whether in Source or 36 | Object form, made available under the License, as indicated by a 37 | copyright notice that is included in or attached to the work 38 | (an example is provided in the Appendix below). 39 | 40 | "Derivative Works" shall mean any work, whether in Source or Object 41 | form, that is based on (or derived from) the Work and for which the 42 | editorial revisions, annotations, elaborations, or other modifications 43 | represent, as a whole, an original work of authorship. For the purposes 44 | of this License, Derivative Works shall not include works that remain 45 | separable from, or merely link (or bind by name) to the interfaces of, 46 | the Work and Derivative Works thereof. 47 | 48 | "Contribution" shall mean any work of authorship, including 49 | the original version of the Work and any modifications or additions 50 | to that Work or Derivative Works thereof, that is intentionally 51 | submitted to Licensor for inclusion in the Work by the copyright owner 52 | or by an individual or Legal Entity authorized to submit on behalf of 53 | the copyright owner. For the purposes of this definition, "submitted" 54 | means any form of electronic, verbal, or written communication sent 55 | to the Licensor or its representatives, including but not limited to 56 | communication on electronic mailing lists, source code control systems, 57 | and issue tracking systems that are managed by, or on behalf of, the 58 | Licensor for the purpose of discussing and improving the Work, but 59 | excluding communication that is conspicuously marked or otherwise 60 | designated in writing by the copyright owner as "Not a Contribution." 61 | 62 | "Contributor" shall mean Licensor and any individual or Legal Entity 63 | on behalf of whom a Contribution has been received by Licensor and 64 | subsequently incorporated within the Work. 65 | 66 | 2. Grant of Copyright License. Subject to the terms and conditions of 67 | this License, each Contributor hereby grants to You a perpetual, 68 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 69 | copyright license to reproduce, prepare Derivative Works of, 70 | publicly display, publicly perform, sublicense, and distribute the 71 | Work and such Derivative Works in Source or Object form. 72 | 73 | 3. Grant of Patent License. Subject to the terms and conditions of 74 | this License, each Contributor hereby grants to You a perpetual, 75 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 76 | (except as stated in this section) patent license to make, have made, 77 | use, offer to sell, sell, import, and otherwise transfer the Work, 78 | where such license applies only to those patent claims licensable 79 | by such Contributor that are necessarily infringed by their 80 | Contribution(s) alone or by combination of their Contribution(s) 81 | with the Work to which such Contribution(s) was submitted. If You 82 | institute patent litigation against any entity (including a 83 | cross-claim or counterclaim in a lawsuit) alleging that the Work 84 | or a Contribution incorporated within the Work constitutes direct 85 | or contributory patent infringement, then any patent licenses 86 | granted to You under this License for that Work shall terminate 87 | as of the date such litigation is filed. 88 | 89 | 4. Redistribution. You may reproduce and distribute copies of the 90 | Work or Derivative Works thereof in any medium, with or without 91 | modifications, and in Source or Object form, provided that You 92 | meet the following conditions: 93 | 94 | (a) You must give any other recipients of the Work or 95 | Derivative Works a copy of this License; and 96 | 97 | (b) You must cause any modified files to carry prominent notices 98 | stating that You changed the files; and 99 | 100 | (c) You must retain, in the Source form of any Derivative Works 101 | that You distribute, all copyright, patent, trademark, and 102 | attribution notices from the Source form of the Work, 103 | excluding those notices that do not pertain to any part of 104 | the Derivative Works; and 105 | 106 | (d) If the Work includes a "NOTICE" text file as part of its 107 | distribution, then any Derivative Works that You distribute must 108 | include a readable copy of the attribution notices contained 109 | within such NOTICE file, excluding those notices that do not 110 | pertain to any part of the Derivative Works, in at least one 111 | of the following places: within a NOTICE text file distributed 112 | as part of the Derivative Works; within the Source form or 113 | documentation, if provided along with the Derivative Works; or, 114 | within a display generated by the Derivative Works, if and 115 | wherever such third-party notices normally appear. The contents 116 | of the NOTICE file are for informational purposes only and 117 | do not modify the License. You may add Your own attribution 118 | notices within Derivative Works that You distribute, alongside 119 | or as an addendum to the NOTICE text from the Work, provided 120 | that such additional attribution notices cannot be construed 121 | as modifying the License. 122 | 123 | You may add Your own copyright statement to Your modifications and 124 | may provide additional or different license terms and conditions 125 | for use, reproduction, or distribution of Your modifications, or 126 | for any such Derivative Works as a whole, provided Your use, 127 | reproduction, and distribution of the Work otherwise complies with 128 | the conditions stated in this License. 129 | 130 | 5. Submission of Contributions. Unless You explicitly state otherwise, 131 | any Contribution intentionally submitted for inclusion in the Work 132 | by You to the Licensor shall be under the terms and conditions of 133 | this License, without any additional terms or conditions. 134 | Notwithstanding the above, nothing herein shall supersede or modify 135 | the terms of any separate license agreement you may have executed 136 | with Licensor regarding such Contributions. 137 | 138 | 6. Trademarks. This License does not grant permission to use the trade 139 | names, trademarks, service marks, or product names of the Licensor, 140 | except as required for reasonable and customary use in describing the 141 | origin of the Work and reproducing the content of the NOTICE file. 142 | 143 | 7. Disclaimer of Warranty. Unless required by applicable law or 144 | agreed to in writing, Licensor provides the Work (and each 145 | Contributor provides its Contributions) on an "AS IS" BASIS, 146 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 147 | implied, including, without limitation, any warranties or conditions 148 | of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A 149 | PARTICULAR PURPOSE. You are solely responsible for determining the 150 | appropriateness of using or redistributing the Work and assume any 151 | risks associated with Your exercise of permissions under this License. 152 | 153 | 8. Limitation of Liability. In no event and under no legal theory, 154 | whether in tort (including negligence), contract, or otherwise, 155 | unless required by applicable law (such as deliberate and grossly 156 | negligent acts) or agreed to in writing, shall any Contributor be 157 | liable to You for damages, including any direct, indirect, special, 158 | incidental, or consequential damages of any character arising as a 159 | result of this License or out of the use or inability to use the 160 | Work (including but not limited to damages for loss of goodwill, 161 | work stoppage, computer failure or malfunction, or any and all 162 | other commercial damages or losses), even if such Contributor 163 | has been advised of the possibility of such damages. 164 | 165 | 9. Accepting Warranty or Additional Liability. While redistributing 166 | the Work or Derivative Works thereof, You may choose to offer, 167 | and charge a fee for, acceptance of support, warranty, indemnity, 168 | or other liability obligations and/or rights consistent with this 169 | License. However, in accepting such obligations, You may act only 170 | on Your own behalf and on Your sole responsibility, not on behalf 171 | of any other Contributor, and only if You agree to indemnify, 172 | defend, and hold each Contributor harmless for any liability 173 | incurred by, or claims asserted against, such Contributor by reason 174 | of your accepting any such warranty or additional liability. 175 | 176 | END OF TERMS AND CONDITIONS 177 | 178 | APPENDIX: How to apply the Apache License to your work. 179 | 180 | To apply the Apache License to your work, attach the following 181 | boilerplate notice, with the fields enclosed by brackets "{}" 182 | replaced with your own identifying information. (Don't include 183 | the brackets!) The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright {yyyy} {name of copyright owner} 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal.h 4 | * @author MCD Application Team 5 | * @brief This file contains all the functions prototypes for the HAL 6 | * module driver. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F1xx_HAL_H 23 | #define __STM32F1xx_HAL_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f1xx_hal_conf.h" 31 | 32 | /** @addtogroup STM32F1xx_HAL_Driver 33 | * @{ 34 | */ 35 | 36 | /** @addtogroup HAL 37 | * @{ 38 | */ 39 | 40 | /* Exported constants --------------------------------------------------------*/ 41 | 42 | /** @defgroup HAL_Exported_Constants HAL Exported Constants 43 | * @{ 44 | */ 45 | 46 | /** @defgroup HAL_TICK_FREQ Tick Frequency 47 | * @{ 48 | */ 49 | typedef enum 50 | { 51 | HAL_TICK_FREQ_10HZ = 100U, 52 | HAL_TICK_FREQ_100HZ = 10U, 53 | HAL_TICK_FREQ_1KHZ = 1U, 54 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 55 | } HAL_TickFreqTypeDef; 56 | /** 57 | * @} 58 | */ 59 | /* Exported types ------------------------------------------------------------*/ 60 | extern __IO uint32_t uwTick; 61 | extern uint32_t uwTickPrio; 62 | extern HAL_TickFreqTypeDef uwTickFreq; 63 | 64 | /** 65 | * @} 66 | */ 67 | /* Exported macro ------------------------------------------------------------*/ 68 | /** @defgroup HAL_Exported_Macros HAL Exported Macros 69 | * @{ 70 | */ 71 | 72 | /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode 73 | * @brief Freeze/Unfreeze Peripherals in Debug mode 74 | * Note: On devices STM32F10xx8 and STM32F10xxB, 75 | * STM32F101xC/D/E and STM32F103xC/D/E, 76 | * STM32F101xF/G and STM32F103xF/G 77 | * STM32F10xx4 and STM32F10xx6 78 | * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in 79 | * debug mode (not accessible by the user software in normal mode). 80 | * Refer to errata sheet of these devices for more details. 81 | * @{ 82 | */ 83 | 84 | /* Peripherals on APB1 */ 85 | /** 86 | * @brief TIM2 Peripherals Debug mode 87 | */ 88 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) 89 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) 90 | 91 | /** 92 | * @brief TIM3 Peripherals Debug mode 93 | */ 94 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) 95 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) 96 | 97 | #if defined (DBGMCU_CR_DBG_TIM4_STOP) 98 | /** 99 | * @brief TIM4 Peripherals Debug mode 100 | */ 101 | #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) 102 | #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) 103 | #endif 104 | 105 | #if defined (DBGMCU_CR_DBG_TIM5_STOP) 106 | /** 107 | * @brief TIM5 Peripherals Debug mode 108 | */ 109 | #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) 110 | #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) 111 | #endif 112 | 113 | #if defined (DBGMCU_CR_DBG_TIM6_STOP) 114 | /** 115 | * @brief TIM6 Peripherals Debug mode 116 | */ 117 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) 118 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) 119 | #endif 120 | 121 | #if defined (DBGMCU_CR_DBG_TIM7_STOP) 122 | /** 123 | * @brief TIM7 Peripherals Debug mode 124 | */ 125 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) 126 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) 127 | #endif 128 | 129 | #if defined (DBGMCU_CR_DBG_TIM12_STOP) 130 | /** 131 | * @brief TIM12 Peripherals Debug mode 132 | */ 133 | #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) 134 | #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) 135 | #endif 136 | 137 | #if defined (DBGMCU_CR_DBG_TIM13_STOP) 138 | /** 139 | * @brief TIM13 Peripherals Debug mode 140 | */ 141 | #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) 142 | #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) 143 | #endif 144 | 145 | #if defined (DBGMCU_CR_DBG_TIM14_STOP) 146 | /** 147 | * @brief TIM14 Peripherals Debug mode 148 | */ 149 | #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) 150 | #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) 151 | #endif 152 | 153 | /** 154 | * @brief WWDG Peripherals Debug mode 155 | */ 156 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) 157 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) 158 | 159 | /** 160 | * @brief IWDG Peripherals Debug mode 161 | */ 162 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) 163 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) 164 | 165 | /** 166 | * @brief I2C1 Peripherals Debug mode 167 | */ 168 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) 169 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) 170 | 171 | #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 172 | /** 173 | * @brief I2C2 Peripherals Debug mode 174 | */ 175 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 176 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 177 | #endif 178 | 179 | #if defined (DBGMCU_CR_DBG_CAN1_STOP) 180 | /** 181 | * @brief CAN1 Peripherals Debug mode 182 | */ 183 | #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) 184 | #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) 185 | #endif 186 | 187 | #if defined (DBGMCU_CR_DBG_CAN2_STOP) 188 | /** 189 | * @brief CAN2 Peripherals Debug mode 190 | */ 191 | #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) 192 | #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) 193 | #endif 194 | 195 | /* Peripherals on APB2 */ 196 | #if defined (DBGMCU_CR_DBG_TIM1_STOP) 197 | /** 198 | * @brief TIM1 Peripherals Debug mode 199 | */ 200 | #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) 201 | #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) 202 | #endif 203 | 204 | #if defined (DBGMCU_CR_DBG_TIM8_STOP) 205 | /** 206 | * @brief TIM8 Peripherals Debug mode 207 | */ 208 | #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) 209 | #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) 210 | #endif 211 | 212 | #if defined (DBGMCU_CR_DBG_TIM9_STOP) 213 | /** 214 | * @brief TIM9 Peripherals Debug mode 215 | */ 216 | #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) 217 | #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) 218 | #endif 219 | 220 | #if defined (DBGMCU_CR_DBG_TIM10_STOP) 221 | /** 222 | * @brief TIM10 Peripherals Debug mode 223 | */ 224 | #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) 225 | #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) 226 | #endif 227 | 228 | #if defined (DBGMCU_CR_DBG_TIM11_STOP) 229 | /** 230 | * @brief TIM11 Peripherals Debug mode 231 | */ 232 | #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) 233 | #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) 234 | #endif 235 | 236 | 237 | #if defined (DBGMCU_CR_DBG_TIM15_STOP) 238 | /** 239 | * @brief TIM15 Peripherals Debug mode 240 | */ 241 | #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) 242 | #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) 243 | #endif 244 | 245 | #if defined (DBGMCU_CR_DBG_TIM16_STOP) 246 | /** 247 | * @brief TIM16 Peripherals Debug mode 248 | */ 249 | #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) 250 | #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) 251 | #endif 252 | 253 | #if defined (DBGMCU_CR_DBG_TIM17_STOP) 254 | /** 255 | * @brief TIM17 Peripherals Debug mode 256 | */ 257 | #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) 258 | #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) 259 | #endif 260 | 261 | /** 262 | * @} 263 | */ 264 | 265 | /** @defgroup HAL_Private_Macros HAL Private Macros 266 | * @{ 267 | */ 268 | #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 269 | ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 270 | ((FREQ) == HAL_TICK_FREQ_1KHZ)) 271 | /** 272 | * @} 273 | */ 274 | 275 | /* Exported functions --------------------------------------------------------*/ 276 | /** @addtogroup HAL_Exported_Functions 277 | * @{ 278 | */ 279 | /** @addtogroup HAL_Exported_Functions_Group1 280 | * @{ 281 | */ 282 | /* Initialization and de-initialization functions ******************************/ 283 | HAL_StatusTypeDef HAL_Init(void); 284 | HAL_StatusTypeDef HAL_DeInit(void); 285 | void HAL_MspInit(void); 286 | void HAL_MspDeInit(void); 287 | HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 288 | /** 289 | * @} 290 | */ 291 | 292 | /** @addtogroup HAL_Exported_Functions_Group2 293 | * @{ 294 | */ 295 | /* Peripheral Control functions ************************************************/ 296 | void HAL_IncTick(void); 297 | void HAL_Delay(uint32_t Delay); 298 | uint32_t HAL_GetTick(void); 299 | uint32_t HAL_GetTickPrio(void); 300 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 301 | HAL_TickFreqTypeDef HAL_GetTickFreq(void); 302 | void HAL_SuspendTick(void); 303 | void HAL_ResumeTick(void); 304 | uint32_t HAL_GetHalVersion(void); 305 | uint32_t HAL_GetREVID(void); 306 | uint32_t HAL_GetDEVID(void); 307 | uint32_t HAL_GetUIDw0(void); 308 | uint32_t HAL_GetUIDw1(void); 309 | uint32_t HAL_GetUIDw2(void); 310 | void HAL_DBGMCU_EnableDBGSleepMode(void); 311 | void HAL_DBGMCU_DisableDBGSleepMode(void); 312 | void HAL_DBGMCU_EnableDBGStopMode(void); 313 | void HAL_DBGMCU_DisableDBGStopMode(void); 314 | void HAL_DBGMCU_EnableDBGStandbyMode(void); 315 | void HAL_DBGMCU_DisableDBGStandbyMode(void); 316 | /** 317 | * @} 318 | */ 319 | 320 | /** 321 | * @} 322 | */ 323 | 324 | /** 325 | * @} 326 | */ 327 | /* Private types -------------------------------------------------------------*/ 328 | /* Private variables ---------------------------------------------------------*/ 329 | /** @defgroup HAL_Private_Variables HAL Private Variables 330 | * @{ 331 | */ 332 | /** 333 | * @} 334 | */ 335 | /* Private constants ---------------------------------------------------------*/ 336 | /** @defgroup HAL_Private_Constants HAL Private Constants 337 | * @{ 338 | */ 339 | /** 340 | * @} 341 | */ 342 | /* Private macros ------------------------------------------------------------*/ 343 | /* Private functions ---------------------------------------------------------*/ 344 | /** 345 | * @} 346 | */ 347 | 348 | /** 349 | * @} 350 | */ 351 | 352 | #ifdef __cplusplus 353 | } 354 | #endif 355 | 356 | #endif /* __STM32F1xx_HAL_H */ 357 | 358 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 359 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F1xx_HAL_DEF 23 | #define __STM32F1xx_HAL_DEF 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f1xx.h" 31 | #include "Legacy/stm32_hal_legacy.h" 32 | #include 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | 36 | /** 37 | * @brief HAL Status structures definition 38 | */ 39 | typedef enum 40 | { 41 | HAL_OK = 0x00U, 42 | HAL_ERROR = 0x01U, 43 | HAL_BUSY = 0x02U, 44 | HAL_TIMEOUT = 0x03U 45 | } HAL_StatusTypeDef; 46 | 47 | /** 48 | * @brief HAL Lock structures definition 49 | */ 50 | typedef enum 51 | { 52 | HAL_UNLOCKED = 0x00U, 53 | HAL_LOCKED = 0x01U 54 | } HAL_LockTypeDef; 55 | 56 | /* Exported macro ------------------------------------------------------------*/ 57 | #define HAL_MAX_DELAY 0xFFFFFFFFU 58 | 59 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) 60 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 61 | 62 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 63 | do{ \ 64 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 65 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 66 | } while(0U) 67 | 68 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 69 | 70 | /** @brief Reset the Handle's State field. 71 | * @param __HANDLE__ specifies the Peripheral Handle. 72 | * @note This macro can be used for the following purpose: 73 | * - When the Handle is declared as local variable; before passing it as parameter 74 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 75 | * to set to 0 the Handle's "State" field. 76 | * Otherwise, "State" field may have any random value and the first time the function 77 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 78 | * (i.e. HAL_PPP_MspInit() will not be executed). 79 | * - When there is a need to reconfigure the low level hardware: instead of calling 80 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 81 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 82 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 83 | * @retval None 84 | */ 85 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 86 | 87 | #if (USE_RTOS == 1U) 88 | /* Reserved for future use */ 89 | #error "USE_RTOS should be 0 in the current HAL release" 90 | #else 91 | #define __HAL_LOCK(__HANDLE__) \ 92 | do{ \ 93 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 94 | { \ 95 | return HAL_BUSY; \ 96 | } \ 97 | else \ 98 | { \ 99 | (__HANDLE__)->Lock = HAL_LOCKED; \ 100 | } \ 101 | }while (0U) 102 | 103 | #define __HAL_UNLOCK(__HANDLE__) \ 104 | do{ \ 105 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 106 | }while (0U) 107 | #endif /* USE_RTOS */ 108 | 109 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 110 | #ifndef __weak 111 | #define __weak __attribute__((weak)) 112 | #endif 113 | #ifndef __packed 114 | #define __packed __attribute__((packed)) 115 | #endif 116 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 117 | #ifndef __weak 118 | #define __weak __attribute__((weak)) 119 | #endif /* __weak */ 120 | #ifndef __packed 121 | #define __packed __attribute__((__packed__)) 122 | #endif /* __packed */ 123 | #endif /* __GNUC__ */ 124 | 125 | 126 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 127 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 128 | #ifndef __ALIGN_BEGIN 129 | #define __ALIGN_BEGIN 130 | #endif 131 | #ifndef __ALIGN_END 132 | #define __ALIGN_END __attribute__ ((aligned (4))) 133 | #endif 134 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 135 | #ifndef __ALIGN_END 136 | #define __ALIGN_END __attribute__ ((aligned (4))) 137 | #endif /* __ALIGN_END */ 138 | #ifndef __ALIGN_BEGIN 139 | #define __ALIGN_BEGIN 140 | #endif /* __ALIGN_BEGIN */ 141 | #else 142 | #ifndef __ALIGN_END 143 | #define __ALIGN_END 144 | #endif /* __ALIGN_END */ 145 | #ifndef __ALIGN_BEGIN 146 | #if defined (__CC_ARM) /* ARM Compiler V5*/ 147 | #define __ALIGN_BEGIN __align(4) 148 | #elif defined (__ICCARM__) /* IAR Compiler */ 149 | #define __ALIGN_BEGIN 150 | #endif /* __CC_ARM */ 151 | #endif /* __ALIGN_BEGIN */ 152 | #endif /* __GNUC__ */ 153 | 154 | 155 | /** 156 | * @brief __RAM_FUNC definition 157 | */ 158 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 159 | /* ARM Compiler V4/V5 and V6 160 | -------------------------- 161 | RAM functions are defined using the toolchain options. 162 | Functions that are executed in RAM should reside in a separate source module. 163 | Using the 'Options for File' dialog you can simply change the 'Code / Const' 164 | area of a module to a memory space in physical RAM. 165 | Available memory areas are declared in the 'Target' tab of the 'Options for Target' 166 | dialog. 167 | */ 168 | #define __RAM_FUNC 169 | 170 | #elif defined ( __ICCARM__ ) 171 | /* ICCARM Compiler 172 | --------------- 173 | RAM functions are defined using a specific toolchain keyword "__ramfunc". 174 | */ 175 | #define __RAM_FUNC __ramfunc 176 | 177 | #elif defined ( __GNUC__ ) 178 | /* GNU Compiler 179 | ------------ 180 | RAM functions are defined using a specific toolchain attribute 181 | "__attribute__((section(".RamFunc")))". 182 | */ 183 | #define __RAM_FUNC __attribute__((section(".RamFunc"))) 184 | 185 | #endif 186 | 187 | /** 188 | * @brief __NOINLINE definition 189 | */ 190 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 191 | /* ARM V4/V5 and V6 & GNU Compiler 192 | ------------------------------- 193 | */ 194 | #define __NOINLINE __attribute__ ( (noinline) ) 195 | 196 | #elif defined ( __ICCARM__ ) 197 | /* ICCARM Compiler 198 | --------------- 199 | */ 200 | #define __NOINLINE _Pragma("optimize = no_inline") 201 | 202 | #endif 203 | 204 | #ifdef __cplusplus 205 | } 206 | #endif 207 | 208 | #endif /* ___STM32F1xx_HAL_DEF */ 209 | 210 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 211 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_flash.h 4 | * @author MCD Application Team 5 | * @brief Header file of Flash HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F1xx_HAL_FLASH_H 22 | #define __STM32F1xx_HAL_FLASH_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f1xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F1xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup FLASH 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup FLASH_Private_Constants 40 | * @{ 41 | */ 42 | #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ 43 | /** 44 | * @} 45 | */ 46 | 47 | /** @addtogroup FLASH_Private_Macros 48 | * @{ 49 | */ 50 | 51 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ 52 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ 53 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) 54 | 55 | #if defined(FLASH_ACR_LATENCY) 56 | #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ 57 | ((__LATENCY__) == FLASH_LATENCY_1) || \ 58 | ((__LATENCY__) == FLASH_LATENCY_2)) 59 | 60 | #else 61 | #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) 62 | #endif /* FLASH_ACR_LATENCY */ 63 | /** 64 | * @} 65 | */ 66 | 67 | /* Exported types ------------------------------------------------------------*/ 68 | /** @defgroup FLASH_Exported_Types FLASH Exported Types 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @brief FLASH Procedure structure definition 74 | */ 75 | typedef enum 76 | { 77 | FLASH_PROC_NONE = 0U, 78 | FLASH_PROC_PAGEERASE = 1U, 79 | FLASH_PROC_MASSERASE = 2U, 80 | FLASH_PROC_PROGRAMHALFWORD = 3U, 81 | FLASH_PROC_PROGRAMWORD = 4U, 82 | FLASH_PROC_PROGRAMDOUBLEWORD = 5U 83 | } FLASH_ProcedureTypeDef; 84 | 85 | /** 86 | * @brief FLASH handle Structure definition 87 | */ 88 | typedef struct 89 | { 90 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 91 | 92 | __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ 93 | 94 | __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ 95 | 96 | __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ 97 | 98 | HAL_LockTypeDef Lock; /*!< FLASH locking object */ 99 | 100 | __IO uint32_t ErrorCode; /*!< FLASH error code 101 | This parameter can be a value of @ref FLASH_Error_Codes */ 102 | } FLASH_ProcessTypeDef; 103 | 104 | /** 105 | * @} 106 | */ 107 | 108 | /* Exported constants --------------------------------------------------------*/ 109 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 110 | * @{ 111 | */ 112 | 113 | /** @defgroup FLASH_Error_Codes FLASH Error Codes 114 | * @{ 115 | */ 116 | 117 | #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ 118 | #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ 119 | #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ 120 | #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ 121 | 122 | /** 123 | * @} 124 | */ 125 | 126 | /** @defgroup FLASH_Type_Program FLASH Type Program 127 | * @{ 128 | */ 129 | #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) 183 | 184 | /** 185 | * @brief Disable the FLASH half cycle access. 186 | * @note half cycle access can only be used with a low-frequency clock of less than 187 | 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. 188 | * @retval None 189 | */ 190 | #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) 191 | 192 | /** 193 | * @} 194 | */ 195 | 196 | #if defined(FLASH_ACR_LATENCY) 197 | /** @defgroup FLASH_EM_Latency FLASH Latency 198 | * @brief macros to handle FLASH Latency 199 | * @{ 200 | */ 201 | 202 | /** 203 | * @brief Set the FLASH Latency. 204 | * @param __LATENCY__ FLASH Latency 205 | * The value of this parameter depend on device used within the same series 206 | * @retval None 207 | */ 208 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) 209 | 210 | 211 | /** 212 | * @brief Get the FLASH Latency. 213 | * @retval FLASH Latency 214 | * The value of this parameter depend on device used within the same series 215 | */ 216 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 217 | 218 | /** 219 | * @} 220 | */ 221 | 222 | #endif /* FLASH_ACR_LATENCY */ 223 | /** @defgroup FLASH_Prefetch FLASH Prefetch 224 | * @brief macros to handle FLASH Prefetch buffer 225 | * @{ 226 | */ 227 | /** 228 | * @brief Enable the FLASH prefetch buffer. 229 | * @retval None 230 | */ 231 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) 232 | 233 | /** 234 | * @brief Disable the FLASH prefetch buffer. 235 | * @retval None 236 | */ 237 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) 238 | 239 | /** 240 | * @} 241 | */ 242 | 243 | /** 244 | * @} 245 | */ 246 | 247 | /* Include FLASH HAL Extended module */ 248 | #include "stm32f1xx_hal_flash_ex.h" 249 | 250 | /* Exported functions --------------------------------------------------------*/ 251 | /** @addtogroup FLASH_Exported_Functions 252 | * @{ 253 | */ 254 | 255 | /** @addtogroup FLASH_Exported_Functions_Group1 256 | * @{ 257 | */ 258 | /* IO operation functions *****************************************************/ 259 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 260 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 261 | 262 | /* FLASH IRQ handler function */ 263 | void HAL_FLASH_IRQHandler(void); 264 | /* Callbacks in non blocking modes */ 265 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 266 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 267 | 268 | /** 269 | * @} 270 | */ 271 | 272 | /** @addtogroup FLASH_Exported_Functions_Group2 273 | * @{ 274 | */ 275 | /* Peripheral Control functions ***********************************************/ 276 | HAL_StatusTypeDef HAL_FLASH_Unlock(void); 277 | HAL_StatusTypeDef HAL_FLASH_Lock(void); 278 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 279 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 280 | void HAL_FLASH_OB_Launch(void); 281 | 282 | /** 283 | * @} 284 | */ 285 | 286 | /** @addtogroup FLASH_Exported_Functions_Group3 287 | * @{ 288 | */ 289 | /* Peripheral State and Error functions ***************************************/ 290 | uint32_t HAL_FLASH_GetError(void); 291 | 292 | /** 293 | * @} 294 | */ 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /* Private function -------------------------------------------------*/ 301 | /** @addtogroup FLASH_Private_Functions 302 | * @{ 303 | */ 304 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 305 | #if defined(FLASH_BANK2_END) 306 | HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); 307 | #endif /* FLASH_BANK2_END */ 308 | 309 | /** 310 | * @} 311 | */ 312 | 313 | /** 314 | * @} 315 | */ 316 | 317 | /** 318 | * @} 319 | */ 320 | 321 | #ifdef __cplusplus 322 | } 323 | #endif 324 | 325 | #endif /* __STM32F1xx_HAL_FLASH_H */ 326 | 327 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 328 | 329 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_gpio.h 4 | * @author MCD Application Team 5 | * @brief Header file of GPIO HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32F1xx_HAL_GPIO_H 22 | #define STM32F1xx_HAL_GPIO_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f1xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F1xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup GPIO 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /** @defgroup GPIO_Exported_Types GPIO Exported Types 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief GPIO Init structure definition 46 | */ 47 | typedef struct 48 | { 49 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured. 50 | This parameter can be any value of @ref GPIO_pins_define */ 51 | 52 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 53 | This parameter can be a value of @ref GPIO_mode_define */ 54 | 55 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. 56 | This parameter can be a value of @ref GPIO_pull_define */ 57 | 58 | uint32_t Speed; /*!< Specifies the speed for the selected pins. 59 | This parameter can be a value of @ref GPIO_speed_define */ 60 | } GPIO_InitTypeDef; 61 | 62 | /** 63 | * @brief GPIO Bit SET and Bit RESET enumeration 64 | */ 65 | typedef enum 66 | { 67 | GPIO_PIN_RESET = 0u, 68 | GPIO_PIN_SET 69 | } GPIO_PinState; 70 | /** 71 | * @} 72 | */ 73 | 74 | /* Exported constants --------------------------------------------------------*/ 75 | 76 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants 77 | * @{ 78 | */ 79 | 80 | /** @defgroup GPIO_pins_define GPIO pins define 81 | * @{ 82 | */ 83 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ 84 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ 85 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ 86 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ 87 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ 88 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ 89 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ 90 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ 91 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ 92 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ 93 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ 94 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ 95 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ 96 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ 97 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ 98 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ 99 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ 100 | 101 | #define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */ 102 | /** 103 | * @} 104 | */ 105 | 106 | /** @defgroup GPIO_mode_define GPIO mode define 107 | * @brief GPIO Configuration Mode 108 | * Elements values convention: 0xX0yz00YZ 109 | * - X : GPIO mode or EXTI Mode 110 | * - y : External IT or Event trigger detection 111 | * - z : IO configuration on External IT or Event 112 | * - Y : Output type (Push Pull or Open Drain) 113 | * - Z : IO Direction mode (Input, Output, Alternate or Analog) 114 | * @{ 115 | */ 116 | #define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */ 117 | #define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */ 118 | #define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */ 119 | #define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */ 120 | #define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */ 121 | #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ 122 | 123 | #define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */ 124 | 125 | #define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */ 126 | #define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */ 127 | #define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 128 | 129 | #define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */ 130 | #define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */ 131 | #define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */ 132 | 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup GPIO_speed_define GPIO speed define 138 | * @brief GPIO Output Maximum frequency 139 | * @{ 140 | */ 141 | #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ 142 | #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ 143 | #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ 144 | 145 | /** 146 | * @} 147 | */ 148 | 149 | /** @defgroup GPIO_pull_define GPIO pull define 150 | * @brief GPIO Pull-Up or Pull-Down Activation 151 | * @{ 152 | */ 153 | #define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ 154 | #define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ 155 | #define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ 156 | /** 157 | * @} 158 | */ 159 | 160 | /** 161 | * @} 162 | */ 163 | 164 | /* Exported macro ------------------------------------------------------------*/ 165 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros 166 | * @{ 167 | */ 168 | 169 | /** 170 | * @brief Checks whether the specified EXTI line flag is set or not. 171 | * @param __EXTI_LINE__: specifies the EXTI line flag to check. 172 | * This parameter can be GPIO_PIN_x where x can be(0..15) 173 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 174 | */ 175 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 176 | 177 | /** 178 | * @brief Clears the EXTI's line pending flags. 179 | * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. 180 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 181 | * @retval None 182 | */ 183 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 184 | 185 | /** 186 | * @brief Checks whether the specified EXTI line is asserted or not. 187 | * @param __EXTI_LINE__: specifies the EXTI line to check. 188 | * This parameter can be GPIO_PIN_x where x can be(0..15) 189 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 190 | */ 191 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 192 | 193 | /** 194 | * @brief Clears the EXTI's line pending bits. 195 | * @param __EXTI_LINE__: specifies the EXTI lines to clear. 196 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 197 | * @retval None 198 | */ 199 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 200 | 201 | /** 202 | * @brief Generates a Software interrupt on selected EXTI line. 203 | * @param __EXTI_LINE__: specifies the EXTI line to check. 204 | * This parameter can be GPIO_PIN_x where x can be(0..15) 205 | * @retval None 206 | */ 207 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) 208 | /** 209 | * @} 210 | */ 211 | 212 | /* Include GPIO HAL Extension module */ 213 | #include "stm32f1xx_hal_gpio_ex.h" 214 | 215 | /* Exported functions --------------------------------------------------------*/ 216 | /** @addtogroup GPIO_Exported_Functions 217 | * @{ 218 | */ 219 | 220 | /** @addtogroup GPIO_Exported_Functions_Group1 221 | * @{ 222 | */ 223 | /* Initialization and de-initialization functions *****************************/ 224 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); 225 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); 226 | /** 227 | * @} 228 | */ 229 | 230 | /** @addtogroup GPIO_Exported_Functions_Group2 231 | * @{ 232 | */ 233 | /* IO operation functions *****************************************************/ 234 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 235 | void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); 236 | void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 237 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 238 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); 239 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); 240 | 241 | /** 242 | * @} 243 | */ 244 | 245 | /** 246 | * @} 247 | */ 248 | /* Private types -------------------------------------------------------------*/ 249 | /* Private variables ---------------------------------------------------------*/ 250 | /* Private constants ---------------------------------------------------------*/ 251 | /** @defgroup GPIO_Private_Constants GPIO Private Constants 252 | * @{ 253 | */ 254 | 255 | /** 256 | * @} 257 | */ 258 | 259 | /* Private macros ------------------------------------------------------------*/ 260 | /** @defgroup GPIO_Private_Macros GPIO Private Macros 261 | * @{ 262 | */ 263 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) 264 | #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u)) 265 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ 266 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ 267 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ 268 | ((MODE) == GPIO_MODE_AF_PP) ||\ 269 | ((MODE) == GPIO_MODE_AF_OD) ||\ 270 | ((MODE) == GPIO_MODE_IT_RISING) ||\ 271 | ((MODE) == GPIO_MODE_IT_FALLING) ||\ 272 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ 273 | ((MODE) == GPIO_MODE_EVT_RISING) ||\ 274 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\ 275 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ 276 | ((MODE) == GPIO_MODE_ANALOG)) 277 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ 278 | ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) 279 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ 280 | ((PULL) == GPIO_PULLDOWN)) 281 | /** 282 | * @} 283 | */ 284 | 285 | /* Private functions ---------------------------------------------------------*/ 286 | /** @defgroup GPIO_Private_Functions GPIO Private Functions 287 | * @{ 288 | */ 289 | 290 | /** 291 | * @} 292 | */ 293 | 294 | /** 295 | * @} 296 | */ 297 | 298 | /** 299 | * @} 300 | */ 301 | 302 | #ifdef __cplusplus 303 | } 304 | #endif 305 | 306 | #endif /* STM32F1xx_HAL_GPIO_H */ 307 | 308 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 309 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_tim_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of TIM HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32F1xx_HAL_TIM_EX_H 22 | #define STM32F1xx_HAL_TIM_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f1xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F1xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup TIMEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief TIM Hall sensor Configuration Structure definition 46 | */ 47 | 48 | typedef struct 49 | { 50 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 51 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 52 | 53 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 54 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 55 | 56 | uint32_t IC1Filter; /*!< Specifies the input capture filter. 57 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 58 | 59 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 60 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 61 | } TIM_HallSensor_InitTypeDef; 62 | /** 63 | * @} 64 | */ 65 | /* End of exported types -----------------------------------------------------*/ 66 | 67 | /* Exported constants --------------------------------------------------------*/ 68 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants 69 | * @{ 70 | */ 71 | 72 | /** @defgroup TIMEx_Remap TIM Extended Remapping 73 | * @{ 74 | */ 75 | /** 76 | * @} 77 | */ 78 | 79 | /** 80 | * @} 81 | */ 82 | /* End of exported constants -------------------------------------------------*/ 83 | 84 | /* Exported macro ------------------------------------------------------------*/ 85 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | /* End of exported macro -----------------------------------------------------*/ 93 | 94 | /* Private macro -------------------------------------------------------------*/ 95 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | /* End of private macro ------------------------------------------------------*/ 103 | 104 | /* Exported functions --------------------------------------------------------*/ 105 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions 106 | * @{ 107 | */ 108 | 109 | /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 110 | * @brief Timer Hall Sensor functions 111 | * @{ 112 | */ 113 | /* Timer Hall Sensor functions **********************************************/ 114 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); 115 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); 116 | 117 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); 118 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); 119 | 120 | /* Blocking mode: Polling */ 121 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); 122 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); 123 | /* Non-Blocking mode: Interrupt */ 124 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); 125 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); 126 | /* Non-Blocking mode: DMA */ 127 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 128 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); 129 | /** 130 | * @} 131 | */ 132 | 133 | /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions 134 | * @brief Timer Complementary Output Compare functions 135 | * @{ 136 | */ 137 | /* Timer Complementary Output Compare functions *****************************/ 138 | /* Blocking mode: Polling */ 139 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 140 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 141 | 142 | /* Non-Blocking mode: Interrupt */ 143 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 144 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 145 | 146 | /* Non-Blocking mode: DMA */ 147 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 148 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 149 | /** 150 | * @} 151 | */ 152 | 153 | /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions 154 | * @brief Timer Complementary PWM functions 155 | * @{ 156 | */ 157 | /* Timer Complementary PWM functions ****************************************/ 158 | /* Blocking mode: Polling */ 159 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 160 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 161 | 162 | /* Non-Blocking mode: Interrupt */ 163 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 164 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 165 | /* Non-Blocking mode: DMA */ 166 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 167 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 168 | /** 169 | * @} 170 | */ 171 | 172 | /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions 173 | * @brief Timer Complementary One Pulse functions 174 | * @{ 175 | */ 176 | /* Timer Complementary One Pulse functions **********************************/ 177 | /* Blocking mode: Polling */ 178 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 179 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 180 | 181 | /* Non-Blocking mode: Interrupt */ 182 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 183 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 184 | /** 185 | * @} 186 | */ 187 | 188 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions 189 | * @brief Peripheral Control functions 190 | * @{ 191 | */ 192 | /* Extended Control functions ************************************************/ 193 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 194 | uint32_t CommutationSource); 195 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 196 | uint32_t CommutationSource); 197 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 198 | uint32_t CommutationSource); 199 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, 200 | TIM_MasterConfigTypeDef *sMasterConfig); 201 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 202 | TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); 203 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); 204 | /** 205 | * @} 206 | */ 207 | 208 | /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 209 | * @brief Extended Callbacks functions 210 | * @{ 211 | */ 212 | /* Extended Callback **********************************************************/ 213 | void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); 214 | void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); 215 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); 216 | /** 217 | * @} 218 | */ 219 | 220 | /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 221 | * @brief Extended Peripheral State functions 222 | * @{ 223 | */ 224 | /* Extended Peripheral State functions ***************************************/ 225 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); 226 | HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); 227 | /** 228 | * @} 229 | */ 230 | 231 | /** 232 | * @} 233 | */ 234 | /* End of exported functions -------------------------------------------------*/ 235 | 236 | /* Private functions----------------------------------------------------------*/ 237 | /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions 238 | * @{ 239 | */ 240 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); 241 | void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); 242 | /** 243 | * @} 244 | */ 245 | /* End of private functions --------------------------------------------------*/ 246 | 247 | /** 248 | * @} 249 | */ 250 | 251 | /** 252 | * @} 253 | */ 254 | 255 | #ifdef __cplusplus 256 | } 257 | #endif 258 | 259 | 260 | #endif /* STM32F1xx_HAL_TIM_EX_H */ 261 | 262 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 263 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/License.md: -------------------------------------------------------------------------------- 1 | Copyright 2016(-2021) STMicroelectronics. 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without modification, 5 | are permitted provided that the following conditions are met: 6 | 7 | 1. Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | 2. Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | 14 | 3. Neither the name of the copyright holder nor the names of its contributors 15 | may be used to endorse or promote products derived from this software without 16 | specific prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 19 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 22 | ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 | ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_gpio_ex.c 4 | * @author MCD Application Team 5 | * @brief GPIO Extension HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. 8 | * + Extended features functions 9 | * 10 | @verbatim 11 | ============================================================================== 12 | ##### GPIO Peripheral extension features ##### 13 | ============================================================================== 14 | [..] GPIO module on STM32F1 family, manage also the AFIO register: 15 | (+) Possibility to use the EVENTOUT Cortex feature 16 | 17 | ##### How to use this driver ##### 18 | ============================================================================== 19 | [..] This driver provides functions to use EVENTOUT Cortex feature 20 | (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() 21 | (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() 22 | (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() 23 | 24 | @endverbatim 25 | ****************************************************************************** 26 | * @attention 27 | * 28 | *

© Copyright (c) 2016 STMicroelectronics. 29 | * All rights reserved.

30 | * 31 | * This software component is licensed by ST under BSD 3-Clause license, 32 | * the "License"; You may not use this file except in compliance with the 33 | * License. You may obtain a copy of the License at: 34 | * opensource.org/licenses/BSD-3-Clause 35 | * 36 | ****************************************************************************** 37 | */ 38 | 39 | /* Includes ------------------------------------------------------------------*/ 40 | #include "stm32f1xx_hal.h" 41 | 42 | /** @addtogroup STM32F1xx_HAL_Driver 43 | * @{ 44 | */ 45 | 46 | /** @defgroup GPIOEx GPIOEx 47 | * @brief GPIO HAL module driver 48 | * @{ 49 | */ 50 | 51 | #ifdef HAL_GPIO_MODULE_ENABLED 52 | 53 | /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions 54 | * @{ 55 | */ 56 | 57 | /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions 58 | * @brief Extended features functions 59 | * 60 | @verbatim 61 | ============================================================================== 62 | ##### Extended features functions ##### 63 | ============================================================================== 64 | [..] This section provides functions allowing to: 65 | (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() 66 | (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() 67 | (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() 68 | 69 | @endverbatim 70 | * @{ 71 | */ 72 | 73 | /** 74 | * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. 75 | * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. 76 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. 77 | * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. 78 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. 79 | * @retval None 80 | */ 81 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) 82 | { 83 | /* Verify the parameters */ 84 | assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); 85 | assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); 86 | 87 | /* Apply the new configuration */ 88 | MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); 89 | } 90 | 91 | /** 92 | * @brief Enables the Event Output. 93 | * @retval None 94 | */ 95 | void HAL_GPIOEx_EnableEventout(void) 96 | { 97 | SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 98 | } 99 | 100 | /** 101 | * @brief Disables the Event Output. 102 | * @retval None 103 | */ 104 | void HAL_GPIOEx_DisableEventout(void) 105 | { 106 | CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 107 | } 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | #endif /* HAL_GPIO_MODULE_ENABLED */ 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** 124 | * @} 125 | */ 126 | 127 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 128 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Simon Burkhardt 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32_PatternDriver 2 | STM32F1 (64MHz) produces a repeating 2MHz bit pattern on multiple GPIOs (TIM, DMA, GPIO) 3 | Project for STM32f103rb Nucleo-64 board clocked at 64 MHz 4 | 5 | --- 6 | 7 | > **[youtube video](https://www.youtube.com/watch?v=8z-pJSTi7ME)** 8 | 9 | 10 | ### Case Study: Pixel Clock and Shutter Action for Linear Image Sensor 11 | 12 | #### Excerpt from Datasheet 13 | 14 | ![img/Datasheet.png](img/Datasheet.png) 15 | 16 | Source: [ichaus.de/LFHxxx_datasheet_D1en.pdf](https://www.ichaus.de/upload/pdf/LFHxxx_datasheet_D1en.pdf) 17 | 18 | 19 | ### Waveforms on the Scope 20 | 21 | ![img/DS1Z_QuickPrint4.png](img/DS1Z_QuickPrint4.png) 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /STM32F103RBTX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | ** @file : LinkerScript.ld 5 | ** 6 | ** @author : Auto-generated by STM32CubeIDE 7 | ** 8 | ** Abstract : Linker script for NUCLEO-F103RB Board embedding STM32F103RBTx Device from stm32f1 series 9 | ** 128Kbytes FLASH 10 | ** 20Kbytes RAM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** Distribution: The file is distributed as is, without any warranty 20 | ** of any kind. 21 | ** 22 | ****************************************************************************** 23 | ** @attention 24 | ** 25 | ** Copyright (c) 2021 STMicroelectronics. 26 | ** All rights reserved. 27 | ** 28 | ** This software is licensed under terms that can be found in the LICENSE file 29 | ** in the root directory of this software component. 30 | ** If no LICENSE file comes with this software, it is provided AS-IS. 31 | ** 32 | ****************************************************************************** 33 | */ 34 | 35 | /* Entry Point */ 36 | ENTRY(Reset_Handler) 37 | 38 | /* Highest address of the user mode stack */ 39 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ 40 | 41 | _Min_Heap_Size = 0x200 ; /* required amount of heap */ 42 | _Min_Stack_Size = 0x400 ; /* required amount of stack */ 43 | 44 | /* Memories definition */ 45 | MEMORY 46 | { 47 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K 48 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K 49 | } 50 | 51 | /* Sections */ 52 | SECTIONS 53 | { 54 | /* The startup code into "FLASH" Rom type memory */ 55 | .isr_vector : 56 | { 57 | . = ALIGN(4); 58 | KEEP(*(.isr_vector)) /* Startup code */ 59 | . = ALIGN(4); 60 | } >FLASH 61 | 62 | /* The program code and other data into "FLASH" Rom type memory */ 63 | .text : 64 | { 65 | . = ALIGN(4); 66 | *(.text) /* .text sections (code) */ 67 | *(.text*) /* .text* sections (code) */ 68 | *(.glue_7) /* glue arm to thumb code */ 69 | *(.glue_7t) /* glue thumb to arm code */ 70 | *(.eh_frame) 71 | 72 | KEEP (*(.init)) 73 | KEEP (*(.fini)) 74 | 75 | . = ALIGN(4); 76 | _etext = .; /* define a global symbols at end of code */ 77 | } >FLASH 78 | 79 | /* Constant data into "FLASH" Rom type memory */ 80 | .rodata : 81 | { 82 | . = ALIGN(4); 83 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 84 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 85 | . = ALIGN(4); 86 | } >FLASH 87 | 88 | .ARM.extab : { 89 | . = ALIGN(4); 90 | *(.ARM.extab* .gnu.linkonce.armextab.*) 91 | . = ALIGN(4); 92 | } >FLASH 93 | 94 | .ARM : { 95 | . = ALIGN(4); 96 | __exidx_start = .; 97 | *(.ARM.exidx*) 98 | __exidx_end = .; 99 | . = ALIGN(4); 100 | } >FLASH 101 | 102 | .preinit_array : 103 | { 104 | . = ALIGN(4); 105 | PROVIDE_HIDDEN (__preinit_array_start = .); 106 | KEEP (*(.preinit_array*)) 107 | PROVIDE_HIDDEN (__preinit_array_end = .); 108 | . = ALIGN(4); 109 | } >FLASH 110 | 111 | .init_array : 112 | { 113 | . = ALIGN(4); 114 | PROVIDE_HIDDEN (__init_array_start = .); 115 | KEEP (*(SORT(.init_array.*))) 116 | KEEP (*(.init_array*)) 117 | PROVIDE_HIDDEN (__init_array_end = .); 118 | . = ALIGN(4); 119 | } >FLASH 120 | 121 | .fini_array : 122 | { 123 | . = ALIGN(4); 124 | PROVIDE_HIDDEN (__fini_array_start = .); 125 | KEEP (*(SORT(.fini_array.*))) 126 | KEEP (*(.fini_array*)) 127 | PROVIDE_HIDDEN (__fini_array_end = .); 128 | . = ALIGN(4); 129 | } >FLASH 130 | 131 | /* Used by the startup to initialize data */ 132 | _sidata = LOADADDR(.data); 133 | 134 | /* Initialized data sections into "RAM" Ram type memory */ 135 | .data : 136 | { 137 | . = ALIGN(4); 138 | _sdata = .; /* create a global symbol at data start */ 139 | *(.data) /* .data sections */ 140 | *(.data*) /* .data* sections */ 141 | *(.RamFunc) /* .RamFunc sections */ 142 | *(.RamFunc*) /* .RamFunc* sections */ 143 | 144 | . = ALIGN(4); 145 | _edata = .; /* define a global symbol at data end */ 146 | 147 | } >RAM AT> FLASH 148 | 149 | /* Uninitialized data section into "RAM" Ram type memory */ 150 | . = ALIGN(4); 151 | .bss : 152 | { 153 | /* This is used by the startup in order to initialize the .bss section */ 154 | _sbss = .; /* define a global symbol at bss start */ 155 | __bss_start__ = _sbss; 156 | *(.bss) 157 | *(.bss*) 158 | *(COMMON) 159 | 160 | . = ALIGN(4); 161 | _ebss = .; /* define a global symbol at bss end */ 162 | __bss_end__ = _ebss; 163 | } >RAM 164 | 165 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ 166 | ._user_heap_stack : 167 | { 168 | . = ALIGN(8); 169 | PROVIDE ( end = . ); 170 | PROVIDE ( _end = . ); 171 | . = . + _Min_Heap_Size; 172 | . = . + _Min_Stack_Size; 173 | . = ALIGN(8); 174 | } >RAM 175 | 176 | /* Remove information from the compiler libraries */ 177 | /DISCARD/ : 178 | { 179 | libc.a ( * ) 180 | libm.a ( * ) 181 | libgcc.a ( * ) 182 | } 183 | 184 | .ARM.attributes 0 : { *(.ARM.attributes) } 185 | } 186 | -------------------------------------------------------------------------------- /STM32_PatternDriver Debug.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | -------------------------------------------------------------------------------- /STM32_PatternDriver.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | Dma.Request0=TIM2_UP 3 | Dma.RequestsNb=1 4 | Dma.TIM2_UP.0.Direction=DMA_MEMORY_TO_PERIPH 5 | Dma.TIM2_UP.0.Instance=DMA1_Channel2 6 | Dma.TIM2_UP.0.MemDataAlignment=DMA_MDATAALIGN_WORD 7 | Dma.TIM2_UP.0.MemInc=DMA_MINC_ENABLE 8 | Dma.TIM2_UP.0.Mode=DMA_CIRCULAR 9 | Dma.TIM2_UP.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD 10 | Dma.TIM2_UP.0.PeriphInc=DMA_PINC_DISABLE 11 | Dma.TIM2_UP.0.Priority=DMA_PRIORITY_HIGH 12 | Dma.TIM2_UP.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority 13 | File.Version=6 14 | KeepUserPlacement=false 15 | Mcu.Family=STM32F1 16 | Mcu.IP0=DMA 17 | Mcu.IP1=NVIC 18 | Mcu.IP2=RCC 19 | Mcu.IP3=SYS 20 | Mcu.IP4=TIM2 21 | Mcu.IP5=USART2 22 | Mcu.IPNb=6 23 | Mcu.Name=STM32F103R(8-B)Tx 24 | Mcu.Package=LQFP64 25 | Mcu.Pin0=PC13-TAMPER-RTC 26 | Mcu.Pin1=PC14-OSC32_IN 27 | Mcu.Pin10=PA2 28 | Mcu.Pin11=PA3 29 | Mcu.Pin12=PA5 30 | Mcu.Pin13=PA13 31 | Mcu.Pin14=PA14 32 | Mcu.Pin15=PB3 33 | Mcu.Pin16=VP_SYS_VS_Systick 34 | Mcu.Pin17=VP_TIM2_VS_ClockSourceINT 35 | Mcu.Pin2=PC15-OSC32_OUT 36 | Mcu.Pin3=PD0-OSC_IN 37 | Mcu.Pin4=PD1-OSC_OUT 38 | Mcu.Pin5=PC0 39 | Mcu.Pin6=PC1 40 | Mcu.Pin7=PC2 41 | Mcu.Pin8=PC3 42 | Mcu.Pin9=PA0-WKUP 43 | Mcu.PinsNb=18 44 | Mcu.ThirdPartyNb=0 45 | Mcu.UserConstants=TIM2_PERIOD,512-1 46 | Mcu.UserName=STM32F103RBTx 47 | MxCube.Version=6.4.0 48 | MxDb.Version=DB.6.0.40 49 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false 50 | NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true 51 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false 52 | NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:true\:true\:true 53 | NVIC.ForceEnableDMAVector=true 54 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false 55 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false 56 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false 57 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false 58 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 59 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false 60 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true 61 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false 62 | PA0-WKUP.Signal=S_TIM2_CH1_ETR 63 | PA13.GPIOParameters=GPIO_Label 64 | PA13.GPIO_Label=TMS 65 | PA13.Locked=true 66 | PA13.Mode=Serial_Wire 67 | PA13.Signal=SYS_JTMS-SWDIO 68 | PA14.GPIOParameters=GPIO_Label 69 | PA14.GPIO_Label=TCK 70 | PA14.Locked=true 71 | PA14.Mode=Serial_Wire 72 | PA14.Signal=SYS_JTCK-SWCLK 73 | PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode 74 | PA2.GPIO_Label=USART_TX 75 | PA2.GPIO_Mode=GPIO_MODE_AF_PP 76 | PA2.GPIO_PuPd=GPIO_NOPULL 77 | PA2.GPIO_Speed=GPIO_SPEED_FREQ_LOW 78 | PA2.Locked=true 79 | PA2.Mode=Asynchronous 80 | PA2.Signal=USART2_TX 81 | PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode 82 | PA3.GPIO_Label=USART_RX 83 | PA3.GPIO_Mode=GPIO_MODE_AF_PP 84 | PA3.GPIO_PuPd=GPIO_NOPULL 85 | PA3.GPIO_Speed=GPIO_SPEED_FREQ_LOW 86 | PA3.Locked=true 87 | PA3.Mode=Asynchronous 88 | PA3.Signal=USART2_RX 89 | PA5.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP 90 | PA5.GPIO_Label=LD2 [Green Led] 91 | PA5.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP 92 | PA5.GPIO_PuPd=GPIO_NOPULL 93 | PA5.GPIO_Speed=GPIO_SPEED_FREQ_LOW 94 | PA5.Locked=true 95 | PA5.Signal=GPIO_Output 96 | PB3.GPIOParameters=GPIO_Label 97 | PB3.GPIO_Label=SWO 98 | PB3.Locked=true 99 | PB3.Signal=SYS_JTDO-TRACESWO 100 | PC0.Locked=true 101 | PC0.Signal=GPIO_Output 102 | PC1.Locked=true 103 | PC1.Signal=GPIO_Output 104 | PC13-TAMPER-RTC.GPIOParameters=GPIO_PuPd,GPIO_Label 105 | PC13-TAMPER-RTC.GPIO_Label=B1 [Blue PushButton] 106 | PC13-TAMPER-RTC.GPIO_PuPd=GPIO_NOPULL 107 | PC13-TAMPER-RTC.Locked=true 108 | PC13-TAMPER-RTC.Signal=GPXTI13 109 | PC14-OSC32_IN.Locked=true 110 | PC14-OSC32_IN.Mode=LSE-External-Oscillator 111 | PC14-OSC32_IN.Signal=RCC_OSC32_IN 112 | PC15-OSC32_OUT.Locked=true 113 | PC15-OSC32_OUT.Mode=LSE-External-Oscillator 114 | PC15-OSC32_OUT.Signal=RCC_OSC32_OUT 115 | PC2.Locked=true 116 | PC2.Signal=GPIO_Output 117 | PC3.Locked=true 118 | PC3.Signal=GPIO_Output 119 | PD0-OSC_IN.Locked=true 120 | PD0-OSC_IN.Mode=HSE-External-Clock-Source 121 | PD0-OSC_IN.Signal=RCC_OSC_IN 122 | PD1-OSC_OUT.Locked=true 123 | PD1-OSC_OUT.Mode=HSE-External-Clock-Source 124 | PD1-OSC_OUT.Signal=RCC_OSC_OUT 125 | PinOutPanel.RotationAngle=0 126 | ProjectManager.AskForMigrate=true 127 | ProjectManager.BackupPrevious=false 128 | ProjectManager.CompilerOptimize=6 129 | ProjectManager.ComputerToolchain=false 130 | ProjectManager.CoupleFile=false 131 | ProjectManager.CustomerFirmwarePackage= 132 | ProjectManager.DefaultFWLocation=true 133 | ProjectManager.DeletePrevious=true 134 | ProjectManager.DeviceId=STM32F103RBTx 135 | ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.4 136 | ProjectManager.FreePins=false 137 | ProjectManager.HalAssertFull=false 138 | ProjectManager.HeapSize=0x200 139 | ProjectManager.KeepUserCode=true 140 | ProjectManager.LastFirmware=true 141 | ProjectManager.LibraryCopy=1 142 | ProjectManager.MainLocation=Core/Src 143 | ProjectManager.NoMain=false 144 | ProjectManager.PreviousToolchain= 145 | ProjectManager.ProjectBuild=false 146 | ProjectManager.ProjectFileName=STM32_PatternDriver.ioc 147 | ProjectManager.ProjectName=STM32_PatternDriver 148 | ProjectManager.RegisterCallBack= 149 | ProjectManager.StackSize=0x400 150 | ProjectManager.TargetToolchain=STM32CubeIDE 151 | ProjectManager.ToolChainLocation= 152 | ProjectManager.UnderRoot=true 153 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true,4-MX_DMA_Init-DMA-false-HAL-true,5-MX_TIM2_Init-TIM2-false-HAL-true 154 | RCC.ADCFreqValue=32000000 155 | RCC.AHBFreq_Value=64000000 156 | RCC.APB1CLKDivider=RCC_HCLK_DIV2 157 | RCC.APB1Freq_Value=32000000 158 | RCC.APB1TimFreq_Value=64000000 159 | RCC.APB2Freq_Value=64000000 160 | RCC.APB2TimFreq_Value=64000000 161 | RCC.FCLKCortexFreq_Value=64000000 162 | RCC.FamilyName=M 163 | RCC.HCLKFreq_Value=64000000 164 | RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value 165 | RCC.MCOFreq_Value=64000000 166 | RCC.PLLCLKFreq_Value=64000000 167 | RCC.PLLMCOFreq_Value=32000000 168 | RCC.PLLMUL=RCC_PLL_MUL16 169 | RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE 170 | RCC.RTCFreq_Value=32768 171 | RCC.SYSCLKFreq_VALUE=64000000 172 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 173 | RCC.TimSysFreq_Value=64000000 174 | RCC.USBFreq_Value=64000000 175 | RCC.VCOOutput2Freq_Value=4000000 176 | SH.GPXTI13.0=GPIO_EXTI13 177 | SH.GPXTI13.ConfNb=1 178 | SH.S_TIM2_CH1_ETR.0=TIM2_CH1,Output Compare1 CH1 179 | SH.S_TIM2_CH1_ETR.ConfNb=1 180 | TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE 181 | TIM2.Channel-Output\ Compare1\ CH1=TIM_CHANNEL_1 182 | TIM2.IPParameters=Channel-Output Compare1 CH1,Period,TIM_MasterOutputTrigger,OCMode_1,AutoReloadPreload 183 | TIM2.OCMode_1=TIM_OCMODE_TOGGLE 184 | TIM2.Period=TIM2_PERIOD 185 | TIM2.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE 186 | USART2.IPParameters=VirtualMode 187 | USART2.VirtualMode=VM_ASYNC 188 | VP_SYS_VS_Systick.Mode=SysTick 189 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 190 | VP_TIM2_VS_ClockSourceINT.Mode=Internal 191 | VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT 192 | board=NUCLEO-F103RB 193 | boardIOC=true 194 | isbadioc=false 195 | -------------------------------------------------------------------------------- /img/DS1Z_QuickPrint4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mnemocron/STM32_PatternDriver/40dce761e0c979a7873f4907c1cb0b7e466fba1e/img/DS1Z_QuickPrint4.png -------------------------------------------------------------------------------- /img/Datasheet.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mnemocron/STM32_PatternDriver/40dce761e0c979a7873f4907c1cb0b7e466fba1e/img/Datasheet.png --------------------------------------------------------------------------------