├── README.md ├── Vivado-File ├── project_1 │ ├── project_1.cache │ │ └── wt │ │ │ └── project.wpc │ ├── project_1.hw │ │ └── project_1.lpr │ ├── project_1.srcs │ │ ├── sim_1 │ │ │ └── imports │ │ │ │ └── mohamed aziz │ │ │ │ ├── project_5 │ │ │ │ └── project_5.srcs │ │ │ │ │ └── sim_1 │ │ │ │ │ └── new │ │ │ │ │ └── Tb_top_project.v │ │ │ │ └── project_final │ │ │ │ └── Tb_top_project_behav.wcfg │ │ ├── sources_1 │ │ │ └── imports │ │ │ │ └── mohamed aziz │ │ │ │ ├── project_4 │ │ │ │ └── project_4.srcs │ │ │ │ │ └── sources_1 │ │ │ │ │ └── new │ │ │ │ │ └── ALU.v │ │ │ │ └── project_5 │ │ │ │ └── project_5.srcs │ │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── Tb_top_project.v │ │ │ │ └── sources_1 │ │ │ │ └── new │ │ │ │ ├── ALU_ctr.v │ │ │ │ ├── Counter.v │ │ │ │ ├── Data_Memory.v │ │ │ │ ├── Decoder.v │ │ │ │ ├── Execution.v │ │ │ │ ├── Fetch.v │ │ │ │ ├── Memory.v │ │ │ │ ├── Write_Back.v │ │ │ │ ├── decoder_controle.v │ │ │ │ ├── extend.v │ │ │ │ ├── hazard_unit.v │ │ │ │ ├── memory_instruction.v │ │ │ │ ├── register_file.v │ │ │ │ └── top_project.v │ │ └── utils_1 │ │ │ └── imports │ │ │ └── synth_1 │ │ │ └── top_project.dcp │ └── project_1.xpr ├── vivado.jou ├── vivado.log └── vivado_pid10972.str ├── sim ├── ALU_ctr_tb.v ├── Tb_full_adder.v ├── Tb_top_project.v ├── data_memory_tb.v ├── register_file_tb.v ├── tb_memory_instruction.v └── unit_hazard_tb.v └── src ├── ALU.v ├── ALU_ctr.v ├── Counter.v ├── Data_Memory.v ├── Decoder.v ├── Execution.v ├── Fetch.v ├── Full_adder.v ├── Memory.v ├── Write_Back.v ├── decoder_controle.v ├── extend.v ├── hazard_unit.v ├── memory_instruction.v ├── project_final.v ├── register_file.v ├── test_fetch.v └── top_project.v /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mohamedazizbelhouchet/RISC-V-PIPELINED-PROCESSOR-Implementation/HEAD/README.md -------------------------------------------------------------------------------- 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