├── BF.qsf ├── LICENSE ├── README.md ├── bf.qpf ├── bf.sdc ├── bfcode ├── helloworld.b ├── mandelbrot.b ├── rom_data.hex ├── rom_data.mif └── yapi.b ├── hdl ├── brainfuck.v ├── brainfuck_sim.sv ├── brainfuck_top.v ├── dmem16.qip ├── dmem16.v ├── dmem16_bb.v ├── dmem16_inst.v ├── drom32.qip ├── drom32.v ├── drom32_bb.v ├── drom32_inst.v ├── lcdcontrol.v └── uart.v ├── rom_data.mif └── tools ├── txt2mif └── txt2mif.c /BF.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2014 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition 21 | # Date created = 10:59:45 April 22, 2017 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # BF_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone III" 40 | set_global_assignment -name DEVICE EP3C16F484C6 41 | set_global_assignment -name TOP_LEVEL_ENTITY brainfuck_top 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:59:45 APRIL 22, 2017" 44 | set_global_assignment -name LAST_QUARTUS_VERSION 13.1 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA 49 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 50 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 51 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 52 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V 53 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 54 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 55 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 56 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 57 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 58 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 59 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 60 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 61 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 62 | set_location_assignment PIN_B12 -to clk 63 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk 64 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON 65 | set_location_assignment PIN_C20 -to LCD_DATA[7] 66 | set_location_assignment PIN_C21 -to LCD_DATA[3] 67 | set_location_assignment PIN_C22 -to LCD_DATA[2] 68 | set_location_assignment PIN_B21 -to LCD_DATA[5] 69 | set_location_assignment PIN_B22 -to LCD_DATA[4] 70 | set_location_assignment PIN_D20 -to LCD_DATA[6] 71 | set_location_assignment PIN_D21 -to LCD_DATA[1] 72 | set_location_assignment PIN_D22 -to LCD_DATA[0] 73 | set_location_assignment PIN_E21 -to LCD_EN 74 | set_location_assignment PIN_E22 -to LCD_RW 75 | set_location_assignment PIN_F22 -to LCD_RS 76 | set_location_assignment PIN_F21 -to LCD_BLON 77 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] 78 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] 79 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] 80 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] 81 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] 82 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] 83 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] 84 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] 85 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN 86 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS 87 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW 88 | set_location_assignment PIN_H2 -to key_d_en 89 | set_location_assignment PIN_E3 -to key_in[7] 90 | set_location_assignment PIN_H7 -to key_in[6] 91 | set_location_assignment PIN_J7 -to key_in[5] 92 | set_location_assignment PIN_G5 -to key_in[4] 93 | set_location_assignment PIN_G4 -to key_in[3] 94 | set_location_assignment PIN_H6 -to key_in[2] 95 | set_location_assignment PIN_H5 -to key_in[1] 96 | set_location_assignment PIN_J6 -to key_in[0] 97 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_d_en 98 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_in[7] 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_in[6] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_in[5] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_in[4] 102 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_in[3] 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_in[1] 104 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_in[2] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key_in[0] 106 | set_location_assignment PIN_G3 -to rst_n 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n 108 | set_global_assignment -name VERILOG_FILE hdl/uart.v 109 | set_global_assignment -name VERILOG_FILE hdl/drom32.v 110 | set_global_assignment -name SDC_FILE bf.sdc 111 | set_global_assignment -name VERILOG_FILE hdl/lcdcontrol.v 112 | set_global_assignment -name VERILOG_FILE hdl/brainfuck_top.v 113 | set_global_assignment -name VERILOG_FILE hdl/brainfuck.v 114 | set_global_assignment -name QIP_FILE hdl/dmem16.qip 115 | set_location_assignment PIN_J1 -to of_err 116 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to of_err 117 | set_location_assignment PIN_AB17 -to txd 118 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to txd 119 | set_location_assignment PIN_AB18 -to rxd 120 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rxd 121 | set_global_assignment -name QIP_FILE hdl/drom32.qip 122 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | This is free and unencumbered software released into the public domain. 2 | 3 | Anyone is free to copy, modify, publish, use, compile, sell, or 4 | distribute this software, either in source code form or as a compiled 5 | binary, for any purpose, commercial or non-commercial, and by any 6 | means. 7 | 8 | In jurisdictions that recognize copyright laws, the author or authors 9 | of this software dedicate any and all copyright interest in the 10 | software to the public domain. We make this dedication for the benefit 11 | of the public at large and to the detriment of our heirs and 12 | successors. We intend this dedication to be an overt act of 13 | relinquishment in perpetuity of all present and future rights to this 14 | software under copyright law. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 19 | IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 | OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 | ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 | OTHER DEALINGS IN THE SOFTWARE. 23 | 24 | For more information, please refer to 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Brainf__k CPU 2 | ## Updates 3 | 5/27/2017 4 | Support 16KB program 5 | Support TXD output through GPIO (Connext your RXD to GPIO01_D5, GND to GPIO1 GND) 6 | Mandelbrot.b can run now. Enjoy 7 | https://youtu.be/7C1cCE1fIII 8 | 9 | 5/20/2017 10 | Now, the loop command "]" uses stack to find the return address instead of searching for a corresponding "[" 11 | PIPELINE processing is implemented 12 | Can execute up to 4 consecutive commands of "+-" or "<>" 13 | Now it is 6 times faster than the first version. 14 | 15 | ## Whats this? 16 | A CPU that executes brainf\*\*k language written in Verilog HDL. The CPU can run on FPGA. The target device is Terasic DE0 with LCD. 17 | 18 | The project file has been tested with Quartus 13.1, which is the latest version that supports Cyclon III that is on DE0. 19 | 20 | ## What is Brainf\*\*k? 21 | It's a very simple programming language made of only 8 commands +-<>.,[] 22 | https://esolangs.org/wiki/Brainfuck 23 | 24 | ## Requirements 25 | - DE0 FPGA Board with LCD soldered 26 | - Quartus 13.1 and PC environment that can program DE0 27 | 28 | ## How to run 29 | 1. Write the brainf\*\*k code into rom_data.hex in MIF format. You can use txt2mif.c in tools folder to convert a brainf\*\*k code to MIF format. 30 | 2. On Quartus13.1, open project file "bf.qpf" 31 | 3. Then, compile, and transfer the SOF file to DE-0 32 | 4. Press Button[1] to reset the CPU state. 33 | 5. You will see output on the LCD and Tx port 34 | 35 | ## Limitations 36 | - Only tested with a few codes 37 | - Tested only on Ubuntu 16.04 38 | - Input function has never been tested. I will work on this 39 | - Program ROM is 16K byte 40 | - RAM is 4K byte 41 | -------------------------------------------------------------------------------- /bf.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2014 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition 21 | # Date created = 10:59:45 April 22, 2017 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.1" 26 | DATE = "10:59:45 April 22, 2017" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "BF" 31 | -------------------------------------------------------------------------------- /bf.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************ 2 | # THIS IS A WIZARD-GENERATED FILE. 3 | # 4 | # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition 5 | # 6 | #************************************************************ 7 | 8 | # Copyright (C) 1991-2014 Altera Corporation 9 | # Your use of Altera Corporation's design tools, logic functions 10 | # and other software and tools, and its AMPP partner logic 11 | # functions, and any output files from any of the foregoing 12 | # (including device programming or simulation files), and any 13 | # associated documentation or information are expressly subject 14 | # to the terms and conditions of the Altera Program License 15 | # Subscription Agreement, Altera MegaCore Function License 16 | # Agreement, or other applicable license agreement, including, 17 | # without limitation, that your use is for the sole purpose of 18 | # programming logic devices manufactured by Altera and sold by 19 | # Altera or its authorized distributors. Please refer to the 20 | # applicable agreement for further details. 21 | 22 | 23 | 24 | # Clock constraints 25 | 26 | create_clock -name "CLK" -period 20.000us [get_ports {clk}] 27 | 28 | 29 | # Automatically constrain PLL and other generated clocks 30 | derive_pll_clocks -create_base_clocks 31 | 32 | # Automatically calculate clock uncertainty to jitter and other effects. 33 | derive_clock_uncertainty 34 | 35 | # tsu/th constraints 36 | 37 | # tco constraints 38 | 39 | # tpd constraints 40 | 41 | -------------------------------------------------------------------------------- /bfcode/helloworld.b: -------------------------------------------------------------------------------- 1 | ++++++++++[>+++++++>++++++++++>+++>+<<<<-]>++.>+.+++++++..+++.>++.<<+++++++++++++++.>.+++.------.--------.>+.>. 2 | -------------------------------------------------------------------------------- /bfcode/mandelbrot.b: -------------------------------------------------------------------------------- 1 | A mandelbrot set fractal viewer in brainf*** written by Erik Bosman 2 | +++++++++++++[->++>>>+++++>++>+<<<<<<]>>>>>++++++>--->>>>>>>>>>+++++++++++++++[[ 3 | >>>>>>>>>]+[<<<<<<<<<]>>>>>>>>>-]+[>>>>>>>>[-]>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>[-]+ 4 | <<<<<<<+++++[-[->>>>>>>>>+<<<<<<<<<]>>>>>>>>>]>>>>>>>+>>>>>>>>>>>>>>>>>>>>>>>>>> 5 | >+<<<<<<<<<<<<<<<<<[<<<<<<<<<]>>>[-]+[>>>>>>[>>>>>>>[-]>>]<<<<<<<<<[<<<<<<<<<]>> 6 | >>>>>[-]+<<<<<<++++[-[->>>>>>>>>+<<<<<<<<<]>>>>>>>>>]>>>>>>+<<<<<<+++++++[-[->>> 7 | >>>>>>+<<<<<<<<<]>>>>>>>>>]>>>>>>+<<<<<<<<<<<<<<<<[<<<<<<<<<]>>>[[-]>>>>>>[>>>>> 8 | >>[-<<<<<<+>>>>>>]<<<<<<[->>>>>>+<<+<<<+<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>> 9 | [>>>>>>>>[-<<<<<<<+>>>>>>>]<<<<<<<[->>>>>>>+<<+<<<+<<]>>>>>>>>]<<<<<<<<<[<<<<<<< 10 | <<]>>>>>>>[-<<<<<<<+>>>>>>>]<<<<<<<[->>>>>>>+<<+<<<<<]>>>>>>>>>+++++++++++++++[[ 11 | >>>>>>>>>]+>[-]>[-]>[-]>[-]>[-]>[-]>[-]>[-]>[-]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>-]+[ 12 | >+>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>->>>>[-<<<<+>>>>]<<<<[->>>>+<<<<<[->>[ 13 | -<<+>>]<<[->>+>>+<<<<]+>>>>>>>>>]<<<<<<<<[<<<<<<<<<]]>>>>>>>>>[>>>>>>>>>]<<<<<<< 14 | <<[>[->>>>>>>>>+<<<<<<<<<]<<<<<<<<<<]>[->>>>>>>>>+<<<<<<<<<]<+>>>>>>>>]<<<<<<<<< 15 | [>[-]<->>>>[-<<<<+>[<->-<<<<<<+>>>>>>]<[->+<]>>>>]<<<[->>>+<<<]<+<<<<<<<<<]>>>>> 16 | >>>>[>+>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>->>>>>[-<<<<<+>>>>>]<<<<<[->>>>>+ 17 | <<<<<<[->>>[-<<<+>>>]<<<[->>>+>+<<<<]+>>>>>>>>>]<<<<<<<<[<<<<<<<<<]]>>>>>>>>>[>> 18 | >>>>>>>]<<<<<<<<<[>>[->>>>>>>>>+<<<<<<<<<]<<<<<<<<<<<]>>[->>>>>>>>>+<<<<<<<<<]<< 19 | +>>>>>>>>]<<<<<<<<<[>[-]<->>>>[-<<<<+>[<->-<<<<<<+>>>>>>]<[->+<]>>>>]<<<[->>>+<< 20 | <]<+<<<<<<<<<]>>>>>>>>>[>>>>[-<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<+>>>>>>>>>>>>> 21 | >>>>>>>>>>>>>>>>>>>>>>>]>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>+++++++++++++++[[>>>> 22 | >>>>>]<<<<<<<<<-<<<<<<<<<[<<<<<<<<<]>>>>>>>>>-]+>>>>>>>>>>>>>>>>>>>>>+<<<[<<<<<< 23 | <<<]>>>>>>>>>[>>>[-<<<->>>]+<<<[->>>->[-<<<<+>>>>]<<<<[->>>>+<<<<<<<<<<<<<[<<<<< 24 | <<<<]>>>>[-]+>>>>>[>>>>>>>>>]>+<]]+>>>>[-<<<<->>>>]+<<<<[->>>>-<[-<<<+>>>]<<<[-> 25 | >>+<<<<<<<<<<<<[<<<<<<<<<]>>>[-]+>>>>>>[>>>>>>>>>]>[-]+<]]+>[-<[>>>>>>>>>]<<<<<< 26 | <<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]<<<<<<<[->+>>>-<<<<]>>>>>>>>>+++++++++++++++++++ 27 | +++++++>>[-<<<<+>>>>]<<<<[->>>>+<<[-]<<]>>[<<<<<<<+<[-<+>>>>+<<[-]]>[-<<[->+>>>- 28 | <<<<]>>>]>>>>>>>>>>>>>[>>[-]>[-]>[-]>>>>>]<<<<<<<<<[<<<<<<<<<]>>>[-]>>>>>>[>>>>> 29 | [-<<<<+>>>>]<<<<[->>>>+<<<+<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>>[-<<<<<<<< 30 | <+>>>>>>>>>]>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>+++++++++++++++[[>>>>>>>>>]+>[- 31 | ]>[-]>[-]>[-]>[-]>[-]>[-]>[-]>[-]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>-]+[>+>>>>>>>>]<<< 32 | <<<<<<[<<<<<<<<<]>>>>>>>>>[>->>>>>[-<<<<<+>>>>>]<<<<<[->>>>>+<<<<<<[->>[-<<+>>]< 33 | <[->>+>+<<<]+>>>>>>>>>]<<<<<<<<[<<<<<<<<<]]>>>>>>>>>[>>>>>>>>>]<<<<<<<<<[>[->>>> 34 | >>>>>+<<<<<<<<<]<<<<<<<<<<]>[->>>>>>>>>+<<<<<<<<<]<+>>>>>>>>]<<<<<<<<<[>[-]<->>> 35 | [-<<<+>[<->-<<<<<<<+>>>>>>>]<[->+<]>>>]<<[->>+<<]<+<<<<<<<<<]>>>>>>>>>[>>>>>>[-< 36 | <<<<+>>>>>]<<<<<[->>>>>+<<<<+<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>+>>>>>>>> 37 | ]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>->>>>>[-<<<<<+>>>>>]<<<<<[->>>>>+<<<<<<[->>[-<<+ 38 | >>]<<[->>+>>+<<<<]+>>>>>>>>>]<<<<<<<<[<<<<<<<<<]]>>>>>>>>>[>>>>>>>>>]<<<<<<<<<[> 39 | [->>>>>>>>>+<<<<<<<<<]<<<<<<<<<<]>[->>>>>>>>>+<<<<<<<<<]<+>>>>>>>>]<<<<<<<<<[>[- 40 | ]<->>>>[-<<<<+>[<->-<<<<<<+>>>>>>]<[->+<]>>>>]<<<[->>>+<<<]<+<<<<<<<<<]>>>>>>>>> 41 | [>>>>[-<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<+>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 42 | ]>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>>>[-<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<+> 43 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>]>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>++++++++ 44 | +++++++[[>>>>>>>>>]<<<<<<<<<-<<<<<<<<<[<<<<<<<<<]>>>>>>>>>-]+[>>>>>>>>[-<<<<<<<+ 45 | >>>>>>>]<<<<<<<[->>>>>>>+<<<<<<+<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>>>>>>[ 46 | -]>>>]<<<<<<<<<[<<<<<<<<<]>>>>+>[-<-<<<<+>>>>>]>[-<<<<<<[->>>>>+<++<<<<]>>>>>[-< 47 | <<<<+>>>>>]<->+>]<[->+<]<<<<<[->>>>>+<<<<<]>>>>>>[-]<<<<<<+>>>>[-<<<<->>>>]+<<<< 48 | [->>>>->>>>>[>>[-<<->>]+<<[->>->[-<<<+>>>]<<<[->>>+<<<<<<<<<<<<[<<<<<<<<<]>>>[-] 49 | +>>>>>>[>>>>>>>>>]>+<]]+>>>[-<<<->>>]+<<<[->>>-<[-<<+>>]<<[->>+<<<<<<<<<<<[<<<<< 50 | <<<<]>>>>[-]+>>>>>[>>>>>>>>>]>[-]+<]]+>[-<[>>>>>>>>>]<<<<<<<<]>>>>>>>>]<<<<<<<<< 51 | [<<<<<<<<<]>>>>[-<<<<+>>>>]<<<<[->>>>+>>>>>[>+>>[-<<->>]<<[->>+<<]>>>>>>>>]<<<<< 52 | <<<+<[>[->>>>>+<<<<[->>>>-<<<<<<<<<<<<<<+>>>>>>>>>>>[->>>+<<<]<]>[->>>-<<<<<<<<< 53 | <<<<<+>>>>>>>>>>>]<<]>[->>>>+<<<[->>>-<<<<<<<<<<<<<<+>>>>>>>>>>>]<]>[->>>+<<<]<< 54 | <<<<<<<<<<]>>>>[-]<<<<]>>>[-<<<+>>>]<<<[->>>+>>>>>>[>+>[-<->]<[->+<]>>>>>>>>]<<< 55 | <<<<<+<[>[->>>>>+<<<[->>>-<<<<<<<<<<<<<<+>>>>>>>>>>[->>>>+<<<<]>]<[->>>>-<<<<<<< 56 | <<<<<<<+>>>>>>>>>>]<]>>[->>>+<<<<[->>>>-<<<<<<<<<<<<<<+>>>>>>>>>>]>]<[->>>>+<<<< 57 | ]<<<<<<<<<<<]>>>>>>+<<<<<<]]>>>>[-<<<<+>>>>]<<<<[->>>>+>>>>>[>>>>>>>>>]<<<<<<<<< 58 | [>[->>>>>+<<<<[->>>>-<<<<<<<<<<<<<<+>>>>>>>>>>>[->>>+<<<]<]>[->>>-<<<<<<<<<<<<<< 59 | +>>>>>>>>>>>]<<]>[->>>>+<<<[->>>-<<<<<<<<<<<<<<+>>>>>>>>>>>]<]>[->>>+<<<]<<<<<<< 60 | <<<<<]]>[-]>>[-]>[-]>>>>>[>>[-]>[-]>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>>>>>[-< 61 | <<<+>>>>]<<<<[->>>>+<<<+<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>+++++++++++++++[ 62 | [>>>>>>>>>]+>[-]>[-]>[-]>[-]>[-]>[-]>[-]>[-]>[-]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>-]+ 63 | [>+>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>->>>>[-<<<<+>>>>]<<<<[->>>>+<<<<<[->> 64 | [-<<+>>]<<[->>+>+<<<]+>>>>>>>>>]<<<<<<<<[<<<<<<<<<]]>>>>>>>>>[>>>>>>>>>]<<<<<<<< 65 | <[>[->>>>>>>>>+<<<<<<<<<]<<<<<<<<<<]>[->>>>>>>>>+<<<<<<<<<]<+>>>>>>>>]<<<<<<<<<[ 66 | >[-]<->>>[-<<<+>[<->-<<<<<<<+>>>>>>>]<[->+<]>>>]<<[->>+<<]<+<<<<<<<<<]>>>>>>>>>[ 67 | >>>[-<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<+>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>]> 68 | >>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>[-]>>>>+++++++++++++++[[>>>>>>>>>]<<<<<<<<<-<<<<< 69 | <<<<[<<<<<<<<<]>>>>>>>>>-]+[>>>[-<<<->>>]+<<<[->>>->[-<<<<+>>>>]<<<<[->>>>+<<<<< 70 | <<<<<<<<[<<<<<<<<<]>>>>[-]+>>>>>[>>>>>>>>>]>+<]]+>>>>[-<<<<->>>>]+<<<<[->>>>-<[- 71 | <<<+>>>]<<<[->>>+<<<<<<<<<<<<[<<<<<<<<<]>>>[-]+>>>>>>[>>>>>>>>>]>[-]+<]]+>[-<[>> 72 | >>>>>>>]<<<<<<<<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>[-<<<+>>>]<<<[->>>+>>>>>>[>+>>> 73 | [-<<<->>>]<<<[->>>+<<<]>>>>>>>>]<<<<<<<<+<[>[->+>[-<-<<<<<<<<<<+>>>>>>>>>>>>[-<< 74 | +>>]<]>[-<<-<<<<<<<<<<+>>>>>>>>>>>>]<<<]>>[-<+>>[-<<-<<<<<<<<<<+>>>>>>>>>>>>]<]> 75 | [-<<+>>]<<<<<<<<<<<<<]]>>>>[-<<<<+>>>>]<<<<[->>>>+>>>>>[>+>>[-<<->>]<<[->>+<<]>> 76 | >>>>>>]<<<<<<<<+<[>[->+>>[-<<-<<<<<<<<<<+>>>>>>>>>>>[-<+>]>]<[-<-<<<<<<<<<<+>>>> 77 | >>>>>>>]<<]>>>[-<<+>[-<-<<<<<<<<<<+>>>>>>>>>>>]>]<[-<+>]<<<<<<<<<<<<]>>>>>+<<<<< 78 | ]>>>>>>>>>[>>>[-]>[-]>[-]>>>>]<<<<<<<<<[<<<<<<<<<]>>>[-]>[-]>>>>>[>>>>>>>[-<<<<< 79 | <+>>>>>>]<<<<<<[->>>>>>+<<<<+<<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>+>[-<-<<<<+>>>> 80 | >]>>[-<<<<<<<[->>>>>+<++<<<<]>>>>>[-<<<<<+>>>>>]<->+>>]<<[->>+<<]<<<<<[->>>>>+<< 81 | <<<]+>>>>[-<<<<->>>>]+<<<<[->>>>->>>>>[>>>[-<<<->>>]+<<<[->>>-<[-<<+>>]<<[->>+<< 82 | <<<<<<<<<[<<<<<<<<<]>>>>[-]+>>>>>[>>>>>>>>>]>+<]]+>>[-<<->>]+<<[->>->[-<<<+>>>]< 83 | <<[->>>+<<<<<<<<<<<<[<<<<<<<<<]>>>[-]+>>>>>>[>>>>>>>>>]>[-]+<]]+>[-<[>>>>>>>>>]< 84 | <<<<<<<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>[-<<<+>>>]<<<[->>>+>>>>>>[>+>[-<->]<[->+ 85 | <]>>>>>>>>]<<<<<<<<+<[>[->>>>+<<[->>-<<<<<<<<<<<<<+>>>>>>>>>>[->>>+<<<]>]<[->>>- 86 | <<<<<<<<<<<<<+>>>>>>>>>>]<]>>[->>+<<<[->>>-<<<<<<<<<<<<<+>>>>>>>>>>]>]<[->>>+<<< 87 | ]<<<<<<<<<<<]>>>>>[-]>>[-<<<<<<<+>>>>>>>]<<<<<<<[->>>>>>>+<<+<<<<<]]>>>>[-<<<<+> 88 | >>>]<<<<[->>>>+>>>>>[>+>>[-<<->>]<<[->>+<<]>>>>>>>>]<<<<<<<<+<[>[->>>>+<<<[->>>- 89 | <<<<<<<<<<<<<+>>>>>>>>>>>[->>+<<]<]>[->>-<<<<<<<<<<<<<+>>>>>>>>>>>]<<]>[->>>+<<[ 90 | ->>-<<<<<<<<<<<<<+>>>>>>>>>>>]<]>[->>+<<]<<<<<<<<<<<<]]>>>>[-]<<<<]>>>>[-<<<<+>> 91 | >>]<<<<[->>>>+>[-]>>[-<<<<<<<+>>>>>>>]<<<<<<<[->>>>>>>+<<+<<<<<]>>>>>>>>>[>>>>>> 92 | >>>]<<<<<<<<<[>[->>>>+<<<[->>>-<<<<<<<<<<<<<+>>>>>>>>>>>[->>+<<]<]>[->>-<<<<<<<< 93 | <<<<<+>>>>>>>>>>>]<<]>[->>>+<<[->>-<<<<<<<<<<<<<+>>>>>>>>>>>]<]>[->>+<<]<<<<<<<< 94 | <<<<]]>>>>>>>>>[>>[-]>[-]>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>[-]>[-]>>>>>[>>>>>[-<<<<+ 95 | >>>>]<<<<[->>>>+<<<+<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>>>>>>[-<<<<<+>>>>> 96 | ]<<<<<[->>>>>+<<<+<<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>+++++++++++++++[[>>>> 97 | >>>>>]+>[-]>[-]>[-]>[-]>[-]>[-]>[-]>[-]>[-]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>-]+[>+>> 98 | >>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>->>>>[-<<<<+>>>>]<<<<[->>>>+<<<<<[->>[-<<+ 99 | >>]<<[->>+>>+<<<<]+>>>>>>>>>]<<<<<<<<[<<<<<<<<<]]>>>>>>>>>[>>>>>>>>>]<<<<<<<<<[> 100 | [->>>>>>>>>+<<<<<<<<<]<<<<<<<<<<]>[->>>>>>>>>+<<<<<<<<<]<+>>>>>>>>]<<<<<<<<<[>[- 101 | ]<->>>>[-<<<<+>[<->-<<<<<<+>>>>>>]<[->+<]>>>>]<<<[->>>+<<<]<+<<<<<<<<<]>>>>>>>>> 102 | [>+>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>->>>>>[-<<<<<+>>>>>]<<<<<[->>>>>+<<<< 103 | <<[->>>[-<<<+>>>]<<<[->>>+>+<<<<]+>>>>>>>>>]<<<<<<<<[<<<<<<<<<]]>>>>>>>>>[>>>>>> 104 | >>>]<<<<<<<<<[>>[->>>>>>>>>+<<<<<<<<<]<<<<<<<<<<<]>>[->>>>>>>>>+<<<<<<<<<]<<+>>> 105 | >>>>>]<<<<<<<<<[>[-]<->>>>[-<<<<+>[<->-<<<<<<+>>>>>>]<[->+<]>>>>]<<<[->>>+<<<]<+ 106 | <<<<<<<<<]>>>>>>>>>[>>>>[-<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<+>>>>>>>>>>>>>>>>> 107 | >>>>>>>>>>>>>>>>>>>]>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>+++++++++++++++[[>>>>>>>> 108 | >]<<<<<<<<<-<<<<<<<<<[<<<<<<<<<]>>>>>>>>>-]+>>>>>>>>>>>>>>>>>>>>>+<<<[<<<<<<<<<] 109 | >>>>>>>>>[>>>[-<<<->>>]+<<<[->>>->[-<<<<+>>>>]<<<<[->>>>+<<<<<<<<<<<<<[<<<<<<<<< 110 | ]>>>>[-]+>>>>>[>>>>>>>>>]>+<]]+>>>>[-<<<<->>>>]+<<<<[->>>>-<[-<<<+>>>]<<<[->>>+< 111 | <<<<<<<<<<<[<<<<<<<<<]>>>[-]+>>>>>>[>>>>>>>>>]>[-]+<]]+>[-<[>>>>>>>>>]<<<<<<<<]> 112 | >>>>>>>]<<<<<<<<<[<<<<<<<<<]>>->>[-<<<<+>>>>]<<<<[->>>>+<<[-]<<]>>]<<+>>>>[-<<<< 113 | ->>>>]+<<<<[->>>>-<<<<<<.>>]>>>>[-<<<<<<<.>>>>>>>]<<<[-]>[-]>[-]>[-]>[-]>[-]>>>[ 114 | >[-]>[-]>[-]>[-]>[-]>[-]>>>]<<<<<<<<<[<<<<<<<<<]>>>>>>>>>[>>>>>[-]>>>>]<<<<<<<<< 115 | [<<<<<<<<<]>+++++++++++[-[->>>>>>>>>+<<<<<<<<<]>>>>>>>>>]>>>>+>>>>>>>>>+<<<<<<<< 116 | <<<<<<[<<<<<<<<<]>>>>>>>[-<<<<<<<+>>>>>>>]<<<<<<<[->>>>>>>+[-]>>[>>>>>>>>>]<<<<< 117 | <<<<[>>>>>>>[-<<<<<<+>>>>>>]<<<<<<[->>>>>>+<<<<<<<[<<<<<<<<<]>>>>>>>[-]+>>>]<<<< 118 | <<<<<<]]>>>>>>>[-<<<<<<<+>>>>>>>]<<<<<<<[->>>>>>>+>>[>+>>>>[-<<<<->>>>]<<<<[->>> 119 | >+<<<<]>>>>>>>>]<<+<<<<<<<[>>>>>[->>+<<]<<<<<<<<<<<<<<]>>>>>>>>>[>>>>>>>>>]<<<<< 120 | <<<<[>[-]<->>>>>>>[-<<<<<<<+>[<->-<<<+>>>]<[->+<]>>>>>>>]<<<<<<[->>>>>>+<<<<<<]< 121 | +<<<<<<<<<]>>>>>>>-<<<<[-]+<<<]+>>>>>>>[-<<<<<<<->>>>>>>]+<<<<<<<[->>>>>>>->>[>> 122 | >>>[->>+<<]>>>>]<<<<<<<<<[>[-]<->>>>>>>[-<<<<<<<+>[<->-<<<+>>>]<[->+<]>>>>>>>]<< 123 | <<<<[->>>>>>+<<<<<<]<+<<<<<<<<<]>+++++[-[->>>>>>>>>+<<<<<<<<<]>>>>>>>>>]>>>>+<<< 124 | <<[<<<<<<<<<]>>>>>>>>>[>>>>>[-<<<<<->>>>>]+<<<<<[->>>>>->>[-<<<<<<<+>>>>>>>]<<<< 125 | <<<[->>>>>>>+<<<<<<<<<<<<<<<<[<<<<<<<<<]>>>>[-]+>>>>>[>>>>>>>>>]>+<]]+>>>>>>>[-< 126 | <<<<<<->>>>>>>]+<<<<<<<[->>>>>>>-<<[-<<<<<+>>>>>]<<<<<[->>>>>+<<<<<<<<<<<<<<[<<< 127 | <<<<<<]>>>[-]+>>>>>>[>>>>>>>>>]>[-]+<]]+>[-<[>>>>>>>>>]<<<<<<<<]>>>>>>>>]<<<<<<< 128 | <<[<<<<<<<<<]>>>>[-]<<<+++++[-[->>>>>>>>>+<<<<<<<<<]>>>>>>>>>]>>>>-<<<<<[<<<<<<< 129 | <<]]>>>]<<<<.>>>>>>>>>>[>>>>>>[-]>>>]<<<<<<<<<[<<<<<<<<<]>++++++++++[-[->>>>>>>> 130 | >+<<<<<<<<<]>>>>>>>>>]>>>>>+>>>>>>>>>+<<<<<<<<<<<<<<<[<<<<<<<<<]>>>>>>>>[-<<<<<< 131 | <<+>>>>>>>>]<<<<<<<<[->>>>>>>>+[-]>[>>>>>>>>>]<<<<<<<<<[>>>>>>>>[-<<<<<<<+>>>>>> 132 | >]<<<<<<<[->>>>>>>+<<<<<<<<[<<<<<<<<<]>>>>>>>>[-]+>>]<<<<<<<<<<]]>>>>>>>>[-<<<<< 133 | <<<+>>>>>>>>]<<<<<<<<[->>>>>>>>+>[>+>>>>>[-<<<<<->>>>>]<<<<<[->>>>>+<<<<<]>>>>>> 134 | >>]<+<<<<<<<<[>>>>>>[->>+<<]<<<<<<<<<<<<<<<]>>>>>>>>>[>>>>>>>>>]<<<<<<<<<[>[-]<- 135 | >>>>>>>>[-<<<<<<<<+>[<->-<<+>>]<[->+<]>>>>>>>>]<<<<<<<[->>>>>>>+<<<<<<<]<+<<<<<< 136 | <<<]>>>>>>>>-<<<<<[-]+<<<]+>>>>>>>>[-<<<<<<<<->>>>>>>>]+<<<<<<<<[->>>>>>>>->[>>> 137 | >>>[->>+<<]>>>]<<<<<<<<<[>[-]<->>>>>>>>[-<<<<<<<<+>[<->-<<+>>]<[->+<]>>>>>>>>]<< 138 | <<<<<[->>>>>>>+<<<<<<<]<+<<<<<<<<<]>+++++[-[->>>>>>>>>+<<<<<<<<<]>>>>>>>>>]>>>>> 139 | +>>>>>>>>>>>>>>>>>>>>>>>>>>>+<<<<<<[<<<<<<<<<]>>>>>>>>>[>>>>>>[-<<<<<<->>>>>>]+< 140 | <<<<<[->>>>>>->>[-<<<<<<<<+>>>>>>>>]<<<<<<<<[->>>>>>>>+<<<<<<<<<<<<<<<<<[<<<<<<< 141 | <<]>>>>[-]+>>>>>[>>>>>>>>>]>+<]]+>>>>>>>>[-<<<<<<<<->>>>>>>>]+<<<<<<<<[->>>>>>>> 142 | -<<[-<<<<<<+>>>>>>]<<<<<<[->>>>>>+<<<<<<<<<<<<<<<[<<<<<<<<<]>>>[-]+>>>>>>[>>>>>> 143 | >>>]>[-]+<]]+>[-<[>>>>>>>>>]<<<<<<<<]>>>>>>>>]<<<<<<<<<[<<<<<<<<<]>>>>[-]<<<++++ 144 | +[-[->>>>>>>>>+<<<<<<<<<]>>>>>>>>>]>>>>>->>>>>>>>>>>>>>>>>>>>>>>>>>>-<<<<<<[<<<< 145 | <<<<<]]>>>] 146 | -------------------------------------------------------------------------------- /bfcode/rom_data.hex: -------------------------------------------------------------------------------- 1 | :040000003e20202b47 2 | :040001002b2b2b2b43 3 | :04000200202b2b2b4d 4 | :040003002b2b202b4c 5 | :040004002b2b2b2b40 6 | :04000500202831353d 7 | :040006002064696796 8 | :040007006974732970 9 | :040008000a0a5b3c3d 10 | :040009002b3e3e3e02 11 | :04000a003e3e3e3eee 12 | :04000b003e2b2b2b26 13 | :04000c002b2b2b2b38 14 | :04000d002b2b2b3c26 15 | :04000e003c3c3c3cf2 16 | :04000f003c3c2d5ddf 17 | :040010003e2b2b2b21 18 | :040011002b2b5b3cf2 19 | :040012002b2b0a2b53 20 | :040013002b2b2b2b31 21 | :040014002b2b3e2d1b 22 | :040015005d2b3e3ed7 23 | :040016003e3e3e3ee2 24 | :040017002b5b3c3cdb 25 | :040018002b2b2b5bfc 26 | :040019003e3e5b2dd3 27 | :04001a003c5d3c5ba6 28 | :04001b003e5d3c2dd1 29 | :04001c005d3e3e0af1 30 | :04001d005b3e2b3ed1 31 | :04001e005d3c5b3ca2 32 | :04001f005d3e5d3e9b 33 | :040020005b5b2d3eaf 34 | :040021003e3e3e2bea 35 | :040022003c3c3c3cde 36 | :040023005d3e3e3eb6 37 | :040024002b2b2b3e0d 38 | :040025002d5d3c5baa 39 | :040026003c3c3c3cda 40 | :040027000a5d3c3cea 41 | :040028003c3c3c3cd8 42 | :040029003c3c2b5bc9 43 | :04002a002d3e3e3edf 44 | :04002b003e3e3e3ecd 45 | :04002c003e3e3e3ecc 46 | :04002d003e5b3c2bc3 47 | :04002e005b2d3e3ebe 48 | :04002f003e3e2b3cde 49 | :040030003c3c3c5daf 50 | :040031003e0a3e3efb 51 | :040032003e3e5d3ca9 52 | :040033003c3c3c5bae 53 | :040034003e3e3e3ec4 54 | :040035003e5b3c3caa 55 | :040036003c3c2b3ed9 56 | :040037003e3e3e2dd2 57 | :040038005d3c3c3ca7 58 | :040039003c3c2d5bb7 59 | :04003a003c3c2b2be8 60 | :04003b002b2b0a2b2a 61 | :04003c002b2b2b2b08 62 | :04003d002b3e3e2ddf 63 | :04003e005d3e3e3e9b 64 | :04003f005b3c3c5b83 65 | :040040003c2b3c3cd1 66 | :040041002b3e3e3eca 67 | :040042002d5d3c5b8d 68 | :040043003e2b3c2ddb 69 | :040044005d3c2b2bbd 70 | :040045003c3c2b0afe 71 | :040046003e3e3e3eb2 72 | :040047003e3e2d5da3 73 | :040048003c3c5b2da8 74 | :040049005d3c3c2da5 75 | :04004a003c5b2d3ea4 76 | :04004b003e2b3c2dd3 77 | :04004c005b3e3e3e8f 78 | :04004d005d3e5b5b52 79 | :04004e003c2b3e2dd0 80 | :04004f005d3e2b3e9d 81 | :040050000a3e5d3cbf 82 | :040051003c3c3c3caf 83 | :040052005d3e5b2d7b 84 | :040053005d3e2b3c9b 85 | :040054003c3c2d5b9c 86 | :040055003e3e2b3cb8 87 | :040056003c2d5d3c98 88 | :040057005d3c3c3c88 89 | :040058003c2b3e3eb5 90 | :040059003e3e3e3e9f 91 | :04005a003e0a3e5bb5 92 | :04005b002d5d3e5b72 93 | :04005c003c3c3c2bb5 94 | :04005d003e3e3e2dac 95 | :04005e005d3c3c2b92 96 | :04005f002b2b2b2be5 97 | :040060002b2b2b2be4 98 | :040061002b3c5b2da0 99 | :040062003e3e2b3cab 100 | :040063002d5b3e3e89 101 | :040064003e5d0a3ea9 102 | :040065005b5b3c2b6e 103 | :040066003e2d5d3e84 104 | :040067002b3e3e5d85 105 | :040068003c3c3c3c98 106 | :040069003c5d3e5b55 107 | :04006a002d5d3e2b93 108 | :04006b003e5b3c3c74 109 | :04006c002b3c2b3eb4 110 | :04006d003e3e2d5d7d 111 | :04006e003c3c3c0ac4 112 | :04006f003c2b3c2bb3 113 | :040070003e3e5b2d7c 114 | :040071005b2d5b2d6f 115 | :040072005b2d5b2d6e 116 | :040073005b2d5b2d6d 117 | :040074005b2d5b2d6c 118 | :040075003c2d3e5b79 119 | :040076002d3c2b3caa 120 | :040077002d3e3e5d73 121 | :040078005d5d5d5d04 122 | :040079000a5d5d5d56 123 | :04007a005d5d3c5b25 124 | :04007b002b2b2b2bc9 125 | :04007c002b5b3c3c76 126 | :04007d003c2b2b2bb6 127 | :04007e002b2b2b2bc6 128 | :04007f002b3c2b2bb4 129 | :040080002b2b2b2bc4 130 | :040081002b2b3e3e9d 131 | :040082003e3e2d5d68 132 | :040083003c0a3c3caf 133 | :040084003c2b3c2d9c 134 | :040085003e3e3e3e73 135 | :040086005b3e2b3c6a 136 | :040087003c3c2b2b9b 137 | :040088002b2b2b2bbc 138 | :040089002b2b2b3caa 139 | :04008a002d3e3e3e7f 140 | :04008b002d5d3c3c63 141 | :04008c003c3c3c5b55 142 | :04008d003e3e0a2bb2 143 | :04008e003c3c2d5d60 144 | :04008f002b3c5b2d72 145 | :040090003e2d3c5d5c 146 | :040091003e5b3e3e4a 147 | :040092002e3c3c3c7c 148 | :040093003c5b2b2e6d 149 | :040094005b2d5d5d1a 150 | :040095003e3e2d5d55 151 | :040096003e5b3e3e45 152 | :040097002e3c3c0aa9 153 | :040098002d5d3e5b35 154 | :040099002d5d3e5b34 155 | :04009a002d5d3e3e50 156 | :04009b003e5b3e3e40 157 | :04009c005b3c3c3c45 158 | :04009d003c3c3c3c63 159 | :04009e003c2b3e3e6f 160 | :04009f003e3e3e3e59 161 | :0400a0003e3e2d5d4a 162 | :0400a1003c3c2d5d4d 163 | :0400a2000a5d3e3e6b 164 | :0400a3005b2d5d3c2c 165 | :0400a4003c3c5b2d4c 166 | :0400a5005d3c3c3c3a 167 | :0400a6003c3c3c3c5a 168 | :0400a7003c5d2b2b5a 169 | :0400a8002b2b2b2b9c 170 | :0400a9002b2b2b2b9b 171 | :0400aa002e0a0a0000000000000000000000000004 172 | :00000001FF -------------------------------------------------------------------------------- /bfcode/rom_data.mif: -------------------------------------------------------------------------------- 1 | DEPTH = 10; 2 | WIDTH = 32; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = HEX; 5 | CONTENT 6 | BEGIN 7 | 8 | 00 : 2B2B2B2B; 9 | 01 : 2B2B2B2B; 10 | 02 : 2B2B5B3E; 11 | 03 : 2B2B2B2B; 12 | 04 : 2B2B2B3E; 13 | 05 : 2B2B2B2B; 14 | 06 : 2B2B2B2B; 15 | 07 : 2B2B3E2B; 16 | 08 : 2B2B3E2B; 17 | 09 : 3C3C3C3C; 18 | 0A : 2D5D3E2B; 19 | 0B : 2B2E3E2B; 20 | 0C : 2E2B2B2B; 21 | 0D : 2B2B2B2B; 22 | 0E : 2E2E2B2B; 23 | 0F : 2B2E3E2B; 24 | 10 : 2B2E3C3C; 25 | 11 : 2B2B2B2B; 26 | 12 : 2B2B2B2B; 27 | 13 : 2B2B2B2B; 28 | 14 : 2B2B2B2E; 29 | 15 : 3E2E2B2B; 30 | 16 : 2B2E2D2D; 31 | 17 : 2D2D2D2D; 32 | 18 : 2E2D2D2D; 33 | 19 : 2D2D2D2D; 34 | 1A : 2D2E3E2B; 35 | 1B : 2E3E2E0A; 36 | 37 | END; 38 | -------------------------------------------------------------------------------- /bfcode/yapi.b: -------------------------------------------------------------------------------- 1 | [ yet another pi calculation program in bf 2 | Just like for pi16.b the accuracy of the result depends on the cellsize: 3 | 4 | - using 8 bit cells causes an overflow after 4 digits 5 | - using 16 bit cells causes an overflow after 537 digits 6 | - using 32 bit cells causes an overflow after several millions of digits 7 | 8 | It's about ~38 times shorter than pi16.b, ~364 times faster and works with 9 | not-wrapping (bignum) implementations. 10 | 11 | by Felix Nawothnig (felix.nawothnig@t-online.de) ] 12 | > +++++ +++++ +++++ (15 digits) 13 | [<+>>>>>>>>++++++++++<<<<<<<-]>+++++[<+++++++++>-]+>>>>>>+[<<+++[>>[-<]<[>]<-]>> 14 | [>+>]<[<]>]>[[->>>>+<<<<]>>>+++>-]<[<<<<]<<<<<<<<+[->>>>>>>>>>>>[<+[->>>>+<<<<]> 15 | >>>>]<<<<[>>>>>[<<<<+>>>>-]<<<<<-[<<++++++++++>>-]>>>[<<[<+<<+>>>-]<[>+<-]<++<<+ 16 | >>>>>>-]<<[-]<<-<[->>+<-[>>>]>[[<+>-]>+>>]<<<<<]>[-]>+<<<-[>>+<<-]<]<<<<+>>>>>>> 17 | >[-]>[<<<+>>>-]<<++++++++++<[->>+<-[>>>]>[[<+>-]>+>>]<<<<<]>[-]>+>[<<+<+>>>-]<<< 18 | <+<+>>[-[-[-[-[-[-[-[-[-<->[-<+<->>]]]]]]]]]]<[+++++[<<<++++++++<++++++++>>>>-]< 19 | <<<+<->>>>[>+<<<+++++++++<->>>-]<<<<<[>>+<<-]+<[->-<]>[>>.<<<<[+.[-]]>>-]>[>>.<< 20 | -]>[-]>[-]>>>[>>[<<<<<<<<+>>>>>>>>-]<<-]]>>[-]<<<[-]<<<<<<<<]++++++++++. -------------------------------------------------------------------------------- /hdl/brainfuck.v: -------------------------------------------------------------------------------- 1 | 2 | module brainfuck 3 | #( parameter AWIDTH = 12, DWIDTH = 16, PWIDTH = 12) 4 | // AWIDTH: Data address bits 5 | // DWIDTH: Data bits 6 | // PWIDTH: Program counter bits 7 | ( 8 | input clk, rst, // clk and async reset 9 | input s_rst, // clocked reset 10 | output [PWIDTH-1:0] pc, 11 | output op_r_req, 12 | input [31:0] op, 13 | input op_den, // ignored for now assuming SRAM 14 | output reg [AWIDTH-1:0] dp_adr, 15 | output reg [DWIDTH-1:0] data_out, 16 | output reg data_w_req, 17 | output reg data_w_sel, 18 | input data_w_wait, // ignored for now assuming SRAM 19 | input [DWIDTH-1:0] data_in, 20 | output reg data_r_req, 21 | output reg data_r_sel, 22 | input data_den // this does not stall operation. if 0, input is invalid 23 | ); 24 | 25 | // opecode 26 | // brainfuck operation code 27 | // 8'h2B: + 28 | // 8'h2C: , 29 | // 8'h2D: - 30 | // 8'h2E: . 31 | // 8'h3C: < 32 | // 8'h3E: > 33 | // 8'h5B: [ 34 | // 8'h5D: ] 35 | localparam OP_PLUS = 8'h2B, OP_DIN = 8'h2c, OP_MINUS = 8'h2D, OP_DOUT = 8'h2E; 36 | localparam OP_LEFT = 8'h3C, OP_RIGHT = 8'h3E, OP_LOOP_ST = 8'h5B, OP_LOOP_END = 8'h5D, OP_HLT = 8'h00; 37 | localparam CMD_NOP = 3'b000; 38 | localparam CMD_PLUS = 3'b010; 39 | localparam CMD_RIGHT = 3'b001; 40 | localparam CMD_DIN = 3'b011; 41 | localparam CMD_DOUT = 3'b100; 42 | localparam CMD_LST = 3'b101; 43 | localparam CMD_LEND = 3'b110; 44 | localparam CMD_HLT = 3'b111; 45 | 46 | // Initialization 47 | localparam MEM_MAX = {AWIDTH{1'b1}}; 48 | localparam INIT_WAIT = 4; 49 | reg [AWIDTH-1:0] init_cnt; 50 | reg [AWIDTH-1:0] mem_cnt; 51 | 52 | // high level state machine 53 | localparam INIT = 4'b0000, MEMI = 4'b0001, PREFETCH = 4'b0010, OPR = 4'b0100, HLT = 4'b1000; 54 | reg [4:0] cur_state; 55 | reg [4:0] nxt_state; 56 | reg hlt_en; 57 | 58 | // pipeline operation 59 | wire [2:0] cmd_0st; // Fetch, address change, get operation (op), change dp_adr, 60 | reg [2:0] cmd_1st; // Execute dp_adr change take effect, , dat change 61 | reg [2:0] cmd_2nd; // MEM data memory read/write 62 | wire [3:0] val_0st; 63 | reg [3:0] val_1st; 64 | reg [DWIDTH-1:0] dat; // copy of *dp 65 | wire [DWIDTH-1:0] dat_new; 66 | wire [DWIDTH-1:0] dat_tgt; // target of execution 67 | reg [PWIDTH+1:0] pc_reg; 68 | wire [2:0] pc_inc; 69 | wire [PWIDTH+1:0] pc_cur; 70 | wire [PWIDTH+1:0] pc_nxt; 71 | wire [PWIDTH+1:0] pc_prefetch; 72 | wire pc_dly; 73 | reg pc_mov; // move o the next ']' 74 | 75 | 76 | // stack for loop 77 | localparam SDEPTH = 6; 78 | reg [PWIDTH+1:0] stack[(1<, -1 for - and <, 0 for the rest. Bits extended for later calc 99 | wire [3:0] val[3:0]; // val0 masked by executed command (only +- seriese or <> series are executed at once) 100 | wire [3:0] vals; // sum of val[] 101 | reg [31:0] op_z; 102 | wire val0_plus_en, val1_plus_en, val2_plus_en, val3_plus_en; 103 | wire val0_right_en, val1_right_en, val2_right_en, val3_right_en; 104 | wire cmd0_nop, cmd1_nop, cmd2_nop, cmd3_nop; 105 | 106 | // init_cnt 107 | always @(posedge clk or posedge rst) begin 108 | if (rst) begin 109 | init_cnt <= 0; 110 | end 111 | else if (s_rst) begin 112 | init_cnt <= 0; 113 | end 114 | else if (init_cnt, or , use the input as the target of operation 480 | assign dat_fwd = (!data_r_sel_z & !data_den) ? 16'h0 : data_in; // if data_den==0 and data is from outside (not memory), replace it with zero 481 | 482 | always @(posedge clk or posedge rst) begin 483 | if (rst) 484 | data_r_sel_z <= 0; 485 | else if (s_rst) 486 | data_r_sel_z <= 0; 487 | else 488 | data_r_sel_z <= data_r_sel; 489 | end 490 | 491 | 492 | endmodule 493 | 494 | -------------------------------------------------------------------------------- /hdl/brainfuck_sim.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ps/1ps 2 | 3 | module brainfuck_tb; 4 | wire [7:0] LCD_DATA; 5 | reg clk, rst; 6 | wire rst_n; 7 | wire LCD_BLON, LCD_RW, LCD_EN, LCD_RS; 8 | reg key_d_en; 9 | reg [7:0] key_in; 10 | integer key_latency, j; 11 | 12 | brainfuck_top bft( 13 | .clk(clk), 14 | .rst_n(rst_n), 15 | .LCD_BLON(LCD_BLON), 16 | .LCD_RW(LCD_RW), 17 | .LCD_EN(LCD_EN), 18 | .LCD_RS(LCD_RS), 19 | .LCD_DATA(LCD_DATA), 20 | .key_in(key_in), 21 | .key_d_en(key_d_en) 22 | ); 23 | 24 | parameter STEP = 20000; // 20 ns = 50 MHz 25 | 26 | reg lcd_en_z; 27 | 28 | // Reset 29 | initial 30 | begin 31 | rst = 1; 32 | #50 33 | rst = 1; 34 | #STEP 35 | rst = 0; 36 | end 37 | 38 | assign rst_n = !rst; 39 | 40 | // clock 41 | always begin 42 | clk = 0; 43 | #(STEP/2); 44 | clk = 1; 45 | #(STEP/2); 46 | end 47 | 48 | always @(posedge clk) begin 49 | if (LCD_EN==1 & lcd_en_z==0) 50 | begin 51 | $display($stime, ", %h %c", {LCD_RS, LCD_DATA}, LCD_DATA); 52 | end 53 | end 54 | 55 | always @(posedge clk or rst) begin 56 | if (rst) 57 | lcd_en_z <= 0; 58 | else 59 | lcd_en_z <= LCD_EN; 60 | end 61 | 62 | initial begin 63 | key_d_en <= 0; 64 | key_in <= 255; 65 | key_latency <= 7; 66 | j = 0; 67 | while(1) begin 68 | @(posedge clk); 69 | key_latency = ($random & 5'h1f)+1; 70 | for(j=0; j0 & cmd_busy==0); 95 | assign cmd_busy = lcd_status | lcd_wen; 96 | assign cmd_in = {1'b1, d_o[7:0]}; 97 | assign cmd_en = (w_en & w_sel) ? 1'b1 : 1'b0; 98 | assign w_wait = (w_sel & cmd_len >= 6'h32) ? 1'b1 : 1'b0; 99 | 100 | always @(posedge clk or posedge rst) begin 101 | if (rst) begin 102 | lcd_wen <= 0; 103 | lcd_wdt <= 0; 104 | end 105 | else begin 106 | if (cmd_st) begin 107 | lcd_wen <= 1; 108 | lcd_wdt <= cmd[0]; 109 | end 110 | else begin 111 | lcd_wen <= 0; 112 | end 113 | end // else: !if(rst) 114 | end // always @ (posedge clk or rst) 115 | 116 | 117 | // program memory 118 | drom32 drom_inst ( .address ( pc ), .clock ( clk ), .q ( op ) ); 119 | 120 | // data memory 121 | dmem16 dmem_inst (.address ( dp ), .clock ( clk ), .data ( d_o ), .wren ( ram_w_en ), .q ( ram_d_i )); 122 | 123 | assign ram_w_en = (w_sel==0) ? w_en : 1'b0; 124 | assign ram_r_en = (r_sel==0) ? r_en : 1'b0; 125 | assign d_en = (r_sel==0) ? ram_d_en : key_d_en; 126 | assign d_i = (r_sel==0) ? ram_d_i : {8'h0, key_in}; 127 | assign s_rst = 0; 128 | 129 | always @(posedge clk or posedge rst) begin 130 | if (rst) 131 | op_en <= 0; 132 | else 133 | op_en <= pc_r; 134 | end 135 | 136 | always @(posedge clk or posedge rst) begin 137 | if (rst) 138 | ram_d_en <= 0; 139 | else 140 | ram_d_en <= ram_r_en; 141 | end 142 | 143 | endmodule // brainfuck_top 144 | 145 | -------------------------------------------------------------------------------- /hdl/dmem16.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dmem16.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dmem16_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dmem16_bb.v"] 6 | -------------------------------------------------------------------------------- /hdl/dmem16.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: dmem16.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.4 Build 182 03/12/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module dmem16 ( 40 | address, 41 | clock, 42 | data, 43 | wren, 44 | q); 45 | 46 | input [11:0] address; 47 | input clock; 48 | input [15:0] data; 49 | input wren; 50 | output [15:0] q; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_off 53 | `endif 54 | tri1 clock; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_on 57 | `endif 58 | 59 | wire [15:0] sub_wire0; 60 | wire [15:0] q = sub_wire0[15:0]; 61 | 62 | altsyncram altsyncram_component ( 63 | .address_a (address), 64 | .clock0 (clock), 65 | .data_a (data), 66 | .wren_a (wren), 67 | .q_a (sub_wire0), 68 | .aclr0 (1'b0), 69 | .aclr1 (1'b0), 70 | .address_b (1'b1), 71 | .addressstall_a (1'b0), 72 | .addressstall_b (1'b0), 73 | .byteena_a (1'b1), 74 | .byteena_b (1'b1), 75 | .clock1 (1'b1), 76 | .clocken0 (1'b1), 77 | .clocken1 (1'b1), 78 | .clocken2 (1'b1), 79 | .clocken3 (1'b1), 80 | .data_b (1'b1), 81 | .eccstatus (), 82 | .q_b (), 83 | .rden_a (1'b1), 84 | .rden_b (1'b1), 85 | .wren_b (1'b0)); 86 | defparam 87 | altsyncram_component.clock_enable_input_a = "BYPASS", 88 | altsyncram_component.clock_enable_output_a = "BYPASS", 89 | altsyncram_component.intended_device_family = "Cyclone III", 90 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 91 | altsyncram_component.lpm_type = "altsyncram", 92 | altsyncram_component.numwords_a = 4096, 93 | altsyncram_component.operation_mode = "SINGLE_PORT", 94 | altsyncram_component.outdata_aclr_a = "NONE", 95 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 96 | altsyncram_component.power_up_uninitialized = "FALSE", 97 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 98 | altsyncram_component.widthad_a = 12, 99 | altsyncram_component.width_a = 16, 100 | altsyncram_component.width_byteena_a = 1; 101 | 102 | 103 | endmodule 104 | 105 | // ============================================================ 106 | // CNX file retrieval info 107 | // ============================================================ 108 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 109 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 113 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 115 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 116 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 119 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 120 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 121 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 122 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 123 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 124 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 125 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 126 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 127 | // Retrieval info: PRIVATE: MIFfilename STRING "" 128 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 129 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 130 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 131 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 132 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 134 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 135 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 136 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 137 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 138 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 139 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 140 | // Retrieval info: PRIVATE: rden NUMERIC "0" 141 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 142 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 145 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 146 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 147 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 148 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 149 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 150 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 151 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 152 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 153 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 154 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 155 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 156 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 157 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 158 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" 159 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 160 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 161 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 162 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 163 | // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 164 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 165 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 166 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.v TRUE 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.inc FALSE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.cmp FALSE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.bsf FALSE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16_inst.v TRUE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16_bb.v TRUE 172 | // Retrieval info: LIB_FILE: altera_mf 173 | -------------------------------------------------------------------------------- /hdl/dmem16_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: dmem16.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.4 Build 182 03/12/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module dmem16 ( 35 | address, 36 | clock, 37 | data, 38 | wren, 39 | q); 40 | 41 | input [11:0] address; 42 | input clock; 43 | input [15:0] data; 44 | input wren; 45 | output [15:0] q; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_off 48 | `endif 49 | tri1 clock; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_on 52 | `endif 53 | 54 | endmodule 55 | 56 | // ============================================================ 57 | // CNX file retrieval info 58 | // ============================================================ 59 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 60 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 64 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 66 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 67 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 70 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 71 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 72 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 73 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 74 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 75 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 76 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 77 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 78 | // Retrieval info: PRIVATE: MIFfilename STRING "" 79 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 80 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 81 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 82 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 83 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 85 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 86 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 87 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 88 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 89 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 90 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 91 | // Retrieval info: PRIVATE: rden NUMERIC "0" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 96 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 97 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 98 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 99 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 100 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 101 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 102 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 103 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 104 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 105 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 106 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 107 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 108 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 109 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" 110 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 111 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 112 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 113 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 114 | // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 115 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 116 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 117 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.v TRUE 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.inc FALSE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.cmp FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.bsf FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16_inst.v TRUE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL dmem16_bb.v TRUE 123 | // Retrieval info: LIB_FILE: altera_mf 124 | -------------------------------------------------------------------------------- /hdl/dmem16_inst.v: -------------------------------------------------------------------------------- 1 | dmem16 dmem16_inst ( 2 | .address ( address_sig ), 3 | .clock ( clock_sig ), 4 | .data ( data_sig ), 5 | .wren ( wren_sig ), 6 | .q ( q_sig ) 7 | ); 8 | -------------------------------------------------------------------------------- /hdl/drom32.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "drom32.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "drom32_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "drom32_bb.v"] 6 | -------------------------------------------------------------------------------- /hdl/drom32.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: drom32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.4 Build 182 03/12/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module drom32 ( 40 | address, 41 | clock, 42 | q); 43 | 44 | input [11:0] address; 45 | input clock; 46 | output [31:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | wire [31:0] sub_wire0; 56 | wire [31:0] q = sub_wire0[31:0]; 57 | 58 | altsyncram altsyncram_component ( 59 | .address_a (address), 60 | .clock0 (clock), 61 | .q_a (sub_wire0), 62 | .aclr0 (1'b0), 63 | .aclr1 (1'b0), 64 | .address_b (1'b1), 65 | .addressstall_a (1'b0), 66 | .addressstall_b (1'b0), 67 | .byteena_a (1'b1), 68 | .byteena_b (1'b1), 69 | .clock1 (1'b1), 70 | .clocken0 (1'b1), 71 | .clocken1 (1'b1), 72 | .clocken2 (1'b1), 73 | .clocken3 (1'b1), 74 | .data_a ({32{1'b1}}), 75 | .data_b (1'b1), 76 | .eccstatus (), 77 | .q_b (), 78 | .rden_a (1'b1), 79 | .rden_b (1'b1), 80 | .wren_a (1'b0), 81 | .wren_b (1'b0)); 82 | defparam 83 | altsyncram_component.address_aclr_a = "NONE", 84 | altsyncram_component.clock_enable_input_a = "BYPASS", 85 | altsyncram_component.clock_enable_output_a = "BYPASS", 86 | altsyncram_component.init_file = "../rom_data.mif", 87 | altsyncram_component.intended_device_family = "Cyclone III", 88 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 89 | altsyncram_component.lpm_type = "altsyncram", 90 | altsyncram_component.numwords_a = 4096, 91 | altsyncram_component.operation_mode = "ROM", 92 | altsyncram_component.outdata_aclr_a = "NONE", 93 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 94 | altsyncram_component.widthad_a = 12, 95 | altsyncram_component.width_a = 32, 96 | altsyncram_component.width_byteena_a = 1; 97 | 98 | 99 | endmodule 100 | 101 | // ============================================================ 102 | // CNX file retrieval info 103 | // ============================================================ 104 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 105 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 108 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 110 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 111 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 114 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 115 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 116 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 117 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 118 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 119 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 120 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 121 | // Retrieval info: PRIVATE: MIFfilename STRING "../rom_data.mif" 122 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 123 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 124 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 125 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 126 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 127 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 128 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 129 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 130 | // Retrieval info: PRIVATE: WidthData NUMERIC "32" 131 | // Retrieval info: PRIVATE: rden NUMERIC "0" 132 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 133 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 134 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: INIT_FILE STRING "../rom_data.mif" 137 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 138 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 139 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 140 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 141 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 142 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 143 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 144 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 145 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 146 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 147 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 148 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 149 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 150 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 151 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 152 | // Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 153 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32.v TRUE 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32.inc FALSE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32.cmp FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32.bsf FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32_inst.v TRUE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32_bb.v TRUE 159 | // Retrieval info: LIB_FILE: altera_mf 160 | -------------------------------------------------------------------------------- /hdl/drom32_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: drom32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.4 Build 182 03/12/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module drom32 ( 35 | address, 36 | clock, 37 | q); 38 | 39 | input [11:0] address; 40 | input clock; 41 | output [31:0] q; 42 | `ifndef ALTERA_RESERVED_QIS 43 | // synopsys translate_off 44 | `endif 45 | tri1 clock; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_on 48 | `endif 49 | 50 | endmodule 51 | 52 | // ============================================================ 53 | // CNX file retrieval info 54 | // ============================================================ 55 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 56 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 57 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 58 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 59 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 60 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 61 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 62 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 63 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 65 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 66 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 67 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 68 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 69 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 70 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 71 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 72 | // Retrieval info: PRIVATE: MIFfilename STRING "../rom_data.mif" 73 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 74 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 75 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 76 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 77 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 78 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 79 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 80 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 81 | // Retrieval info: PRIVATE: WidthData NUMERIC "32" 82 | // Retrieval info: PRIVATE: rden NUMERIC "0" 83 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 84 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 85 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 86 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 87 | // Retrieval info: CONSTANT: INIT_FILE STRING "../rom_data.mif" 88 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 89 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 90 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 91 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 92 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 93 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 94 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 95 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 96 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 97 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 98 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 99 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 100 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 101 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 102 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 103 | // Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32.v TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32.inc FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32.cmp FALSE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32.bsf FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32_inst.v TRUE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL drom32_bb.v TRUE 110 | // Retrieval info: LIB_FILE: altera_mf 111 | -------------------------------------------------------------------------------- /hdl/drom32_inst.v: -------------------------------------------------------------------------------- 1 | drom32 drom32_inst ( 2 | .address ( address_sig ), 3 | .clock ( clock_sig ), 4 | .q ( q_sig ) 5 | ); 6 | -------------------------------------------------------------------------------- /hdl/lcdcontrol.v: -------------------------------------------------------------------------------- 1 | module LCDCONTROL ( 2 | input CLK, RST, 3 | input WRITE, 4 | input [8:0] WRDATA, 5 | output reg STATUS, 6 | output LCD_BLON, // LCD Back Light ON/OFF 7 | output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read 8 | output LCD_EN, // LCD Enable 9 | output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data 10 | inout [7:0] LCD_DATA // LCD Data bus 8 bits 11 | ); 12 | 13 | reg [8:0] cmd; 14 | reg [4:0] en_cnt; 15 | reg [17:0] wait_cnt; 16 | wire st; 17 | wire busy; 18 | reg rst_dly; 19 | reg [19:0] dly_cnt; 20 | 21 | assign LCD_RW = 1'b0; // always write 22 | assign LCD_BLON = 1'b1; // Backlight on 23 | assign LCD_RS = cmd[8]; 24 | assign LCD_DATA = cmd[7:0]; 25 | assign LCD_EN = (en_cnt!=0) ? 1'b1 : 1'b0; 26 | 27 | assign st = (WRITE==1 && busy==0) ? 1'b1 : 1'b0; 28 | 29 | always @(posedge CLK or posedge RST) 30 | begin 31 | if (RST) begin 32 | dly_cnt <= 20'h0; 33 | rst_dly <= 1'b1; 34 | end 35 | else if (dly_cnt!=20'hFFFFF) 36 | begin 37 | dly_cnt <= dly_cnt + 20'h1; 38 | rst_dly <= 1'b1; 39 | end 40 | else 41 | begin 42 | rst_dly <= 1'b0; 43 | end 44 | end 45 | 46 | always @(posedge CLK or posedge RST) 47 | begin 48 | if (RST) 49 | cmd <= 9'h0; 50 | else if (rst_dly) 51 | cmd <= 9'h0; 52 | else if (st) 53 | cmd <= WRDATA[8:0]; 54 | end 55 | 56 | always @(posedge CLK or posedge RST) 57 | begin 58 | if (RST) 59 | en_cnt <= 5'h0; 60 | else if (rst_dly) 61 | en_cnt <= 5'h0; 62 | else if (st) 63 | en_cnt <= 5'h10; 64 | else if (en_cnt!=5'h0) 65 | en_cnt <= en_cnt - 5'h1; 66 | end 67 | 68 | always @(posedge CLK or posedge RST) 69 | begin 70 | if (RST) 71 | wait_cnt <= 18'h00000; 72 | else if (rst_dly) 73 | wait_cnt <= 18'h00000; 74 | else if (en_cnt == 5'h1) 75 | wait_cnt <= 18'h3FFFF; // this should be changed depending on the command 76 | else if (wait_cnt!=18'h0) 77 | wait_cnt <= wait_cnt - 18'h1; 78 | end 79 | 80 | assign busy = (en_cnt==5'h0 && wait_cnt==18'h0) ? 1'b0 : 1'b1; 81 | 82 | always @(posedge CLK or posedge RST) 83 | begin 84 | if (RST) 85 | STATUS <= 1'b1; 86 | else if (rst_dly) 87 | STATUS <= 1'b1; 88 | else 89 | STATUS <= st | busy; 90 | end 91 | 92 | endmodule 93 | 94 | 95 | -------------------------------------------------------------------------------- /hdl/uart.v: -------------------------------------------------------------------------------- 1 | module uart 2 | #(parameter cnt_max=433) 3 | ( 4 | input clk, rst, 5 | output reg txd, 6 | input rxd, 7 | input [7:0] din, 8 | input din_en, 9 | output [7:0] dout, 10 | output dout_en, 11 | output reg of_err 12 | ); 13 | 14 | 15 | reg [7:0] din_fifo[63:0]; 16 | reg [5:0] fifo_head; 17 | reg [5:0] fifo_tail; 18 | wire [5:0] fifo_nxt; 19 | integer i; 20 | reg [8:0] uart_cnt; 21 | wire uart_en; 22 | 23 | wire tx_st, tx_end; 24 | reg tx_en; 25 | reg [3:0] tx_cnt; 26 | reg [7:0] txd_cur; 27 | 28 | always @(posedge clk or posedge rst) begin 29 | if (rst) 30 | fifo_head <= 0; 31 | else begin 32 | if (tx_st) 33 | fifo_head <= fifo_head + 6'h1; 34 | end 35 | end 36 | 37 | always @(posedge clk or posedge rst) begin 38 | if (rst) 39 | fifo_tail <= 6'h0; 40 | else begin 41 | if (din_en) 42 | fifo_tail <= fifo_tail + 6'h1; 43 | end 44 | end 45 | 46 | always @(posedge clk or posedge rst) begin 47 | if (rst) begin 48 | for(i=0; i<64; i=i+1) 49 | din_fifo[i] <= 0; 50 | end 51 | else if (din_en) begin 52 | din_fifo[fifo_tail] <= din; 53 | end 54 | end 55 | 56 | // Overflow error 57 | assign fifo_nxt = fifo_tail + 6'h1; 58 | always @(posedge clk or posedge rst) begin 59 | if (rst) 60 | of_err <= 0; 61 | else if (din_en & !tx_st & (fifo_head==fifo_nxt)) 62 | of_err <= 1; 63 | end 64 | 65 | // generate uart signals 66 | always @(posedge clk or posedge rst) begin 67 | if (rst) begin 68 | uart_cnt <= 0; 69 | end 70 | else begin 71 | if (uart_cnt==cnt_max) begin 72 | uart_cnt <= 0; 73 | end 74 | else begin 75 | uart_cnt = uart_cnt + 9'h1; 76 | end 77 | end 78 | end // always @ (posedge clk or posedge rst) 79 | assign uart_en = (uart_cnt==cnt_max) ? 1'b1 : 1'b0; 80 | 81 | 82 | // tx send (tx_st, tx_en) 83 | assign tx_st = (uart_en & !tx_en & (fifo_head != fifo_tail)) ? 1'b1 : 1'b0; 84 | assign tx_end = (uart_en & tx_cnt==4'h8) ? 1'b1 : 1'b0; 85 | 86 | always @(posedge clk or posedge rst) begin 87 | if (rst) 88 | tx_en <= 0; 89 | else if (tx_st) 90 | tx_en <= 1; 91 | else if (tx_end) // tx_end==1 & tx_st==0 92 | tx_en <= 0; 93 | end 94 | 95 | always @(posedge clk or posedge rst) begin 96 | if (rst) 97 | tx_cnt <= 0; 98 | else if (uart_en) begin 99 | if (tx_st) 100 | tx_cnt <= 0; 101 | else if (tx_en) 102 | tx_cnt <= tx_cnt + 4'h1; 103 | end 104 | end 105 | 106 | always @(posedge clk or posedge rst) begin 107 | if (rst) 108 | txd <= 1; 109 | else if (uart_en==1) begin 110 | if (tx_st) 111 | txd <= 0; 112 | else if (tx_en & tx_cnt==4'h8) 113 | txd <= 1; 114 | else if (tx_en) 115 | txd <= txd_cur[tx_cnt[2:0]]; 116 | else 117 | txd <= 1; 118 | end 119 | end // always @ (posedge clk or posedge rst) 120 | 121 | always @(posedge clk or posedge rst) begin 122 | if (rst) 123 | txd_cur <= 8'h0; 124 | else if (tx_st) 125 | txd_cur <= din_fifo[fifo_head]; 126 | end 127 | 128 | // receiver (not implemented yet) 129 | assign dout = 0; 130 | assign dout_en = 0; 131 | 132 | endmodule // uart 133 | -------------------------------------------------------------------------------- /rom_data.mif: -------------------------------------------------------------------------------- 1 | -- > +++++ +++++ +++++ (15 digits) 2 | -- 3 | -- [<+>>>>>>>>++++++++++<<<<<<<-]>+++++[<++ 4 | -- +++++++>-]+>>>>>>+[<<+++[>>[-<]<[>]<-]>> 5 | -- [>+>]<[<]>]>[[->>>>+<<<<]>>>+++>-]<[<<<< 6 | -- ]<<<<<<<<+[->>>>>>>>>>>>[<+[->>>>+<<<<]> 7 | -- >>>>]<<<<[>>>>>[<<<<+>>>>-]<<<<<-[<<++++ 8 | -- ++++++>>-]>>>[<<[<+<<+>>>-]<[>+<-]<++<<+ 9 | -- >>>>>>-]<<[-]<<-<[->>+<-[>>>]>[[<+>-]>+> 10 | -- >]<<<<<]>[-]>+<<<-[>>+<<-]<]<<<<+>>>>>>> 11 | -- >[-]>[<<<+>>>-]<<++++++++++<[->>+<-[>>>] 12 | -- >[[<+>-]>+>>]<<<<<]>[-]>+>[<<+<+>>>-]<<< 13 | -- <+<+>>[-[-[-[-[-[-[-[-[-<->[-<+<->>]]]]] 14 | -- ]]]]]<[+++++[<<<++++++++<++++++++>>>>-]< 15 | -- <<<+<->>>>[>+<<<+++++++++<->>>-]<<<<<[>> 16 | -- +<<-]+<[->-<]>[>>.<<<<[+.[-]]>>-]>[>>.<< 17 | -- -]>[-]>[-]>>>[>>[<<<<<<<<+>>>>>>>>-]<<-] 18 | -- ]>>[-]<<<[-]<<<<<<<<]++++++++++. 19 | -- 20 | DEPTH = 1024; 21 | WIDTH = 32; 22 | ADDRESS_RADIX = HEX; 23 | DATA_RADIX = HEX; 24 | CONTENT 25 | BEGIN 26 | 27 | 00 : 2B20203E; 28 | 01 : 2B2B2B2B; 29 | 02 : 2B2B2B20; 30 | 03 : 2B202B2B; 31 | 04 : 2B2B2B2B; 32 | 05 : 35312820; 33 | 06 : 67696420; 34 | 07 : 29737469; 35 | 08 : 3C5B0A0A; 36 | 09 : 3E3E3E2B; 37 | 0A : 3E3E3E3E; 38 | 0B : 2B2B2B3E; 39 | 0C : 2B2B2B2B; 40 | 0D : 3C2B2B2B; 41 | 0E : 3C3C3C3C; 42 | 0F : 5D2D3C3C; 43 | 10 : 2B2B2B3E; 44 | 11 : 3C5B2B2B; 45 | 12 : 2B0A2B2B; 46 | 13 : 2B2B2B2B; 47 | 14 : 2D3E2B2B; 48 | 15 : 3E3E2B5D; 49 | 16 : 3E3E3E3E; 50 | 17 : 3C3C5B2B; 51 | 18 : 5B2B2B2B; 52 | 19 : 2D5B3E3E; 53 | 1A : 5B3C5D3C; 54 | 1B : 2D3C5D3E; 55 | 1C : 0A3E3E5D; 56 | 1D : 3E2B3E5B; 57 | 1E : 3C5B3C5D; 58 | 1F : 3E5D3E5D; 59 | 20 : 3E2D5B5B; 60 | 21 : 2B3E3E3E; 61 | 22 : 3C3C3C3C; 62 | 23 : 3E3E3E5D; 63 | 24 : 3E2B2B2B; 64 | 25 : 5B3C5D2D; 65 | 26 : 3C3C3C3C; 66 | 27 : 3C3C5D0A; 67 | 28 : 3C3C3C3C; 68 | 29 : 5B2B3C3C; 69 | 2A : 3E3E3E2D; 70 | 2B : 3E3E3E3E; 71 | 2C : 3E3E3E3E; 72 | 2D : 2B3C5B3E; 73 | 2E : 3E3E2D5B; 74 | 2F : 3C2B3E3E; 75 | 30 : 5D3C3C3C; 76 | 31 : 3E3E0A3E; 77 | 32 : 3C5D3E3E; 78 | 33 : 5B3C3C3C; 79 | 34 : 3E3E3E3E; 80 | 35 : 3C3C5B3E; 81 | 36 : 3E2B3C3C; 82 | 37 : 2D3E3E3E; 83 | 38 : 3C3C3C5D; 84 | 39 : 5B2D3C3C; 85 | 3A : 2B2B3C3C; 86 | 3B : 2B0A2B2B; 87 | 3C : 2B2B2B2B; 88 | 3D : 2D3E3E2B; 89 | 3E : 3E3E3E5D; 90 | 3F : 5B3C3C5B; 91 | 40 : 3C3C2B3C; 92 | 41 : 3E3E3E2B; 93 | 42 : 5B3C5D2D; 94 | 43 : 2D3C2B3E; 95 | 44 : 2B2B3C5D; 96 | 45 : 0A2B3C3C; 97 | 46 : 3E3E3E3E; 98 | 47 : 5D2D3E3E; 99 | 48 : 2D5B3C3C; 100 | 49 : 2D3C3C5D; 101 | 4A : 3E2D5B3C; 102 | 4B : 2D3C2B3E; 103 | 4C : 3E3E3E5B; 104 | 4D : 5B5B3E5D; 105 | 4E : 2D3E2B3C; 106 | 4F : 3E2B3E5D; 107 | 50 : 3C5D3E0A; 108 | 51 : 3C3C3C3C; 109 | 52 : 2D5B3E5D; 110 | 53 : 3C2B3E5D; 111 | 54 : 5B2D3C3C; 112 | 55 : 3C2B3E3E; 113 | 56 : 3C5D2D3C; 114 | 57 : 3C3C3C5D; 115 | 58 : 3E3E2B3C; 116 | 59 : 3E3E3E3E; 117 | 5A : 5B3E0A3E; 118 | 5B : 5B3E5D2D; 119 | 5C : 2B3C3C3C; 120 | 5D : 2D3E3E3E; 121 | 5E : 2B3C3C5D; 122 | 5F : 2B2B2B2B; 123 | 60 : 2B2B2B2B; 124 | 61 : 2D5B3C2B; 125 | 62 : 3C2B3E3E; 126 | 63 : 3E3E5B2D; 127 | 64 : 3E0A5D3E; 128 | 65 : 2B3C5B5B; 129 | 66 : 3E5D2D3E; 130 | 67 : 5D3E3E2B; 131 | 68 : 3C3C3C3C; 132 | 69 : 5B3E5D3C; 133 | 6A : 2B3E5D2D; 134 | 6B : 3C3C5B3E; 135 | 6C : 3E2B3C2B; 136 | 6D : 5D2D3E3E; 137 | 6E : 0A3C3C3C; 138 | 6F : 2B3C2B3C; 139 | 70 : 2D5B3E3E; 140 | 71 : 2D5B2D5B; 141 | 72 : 2D5B2D5B; 142 | 73 : 2D5B2D5B; 143 | 74 : 2D5B2D5B; 144 | 75 : 5B3E2D3C; 145 | 76 : 3C2B3C2D; 146 | 77 : 5D3E3E2D; 147 | 78 : 5D5D5D5D; 148 | 79 : 5D5D5D0A; 149 | 7A : 5B3C5D5D; 150 | 7B : 2B2B2B2B; 151 | 7C : 3C3C5B2B; 152 | 7D : 2B2B2B3C; 153 | 7E : 2B2B2B2B; 154 | 7F : 2B2B3C2B; 155 | 80 : 2B2B2B2B; 156 | 81 : 3E3E2B2B; 157 | 82 : 5D2D3E3E; 158 | 83 : 3C3C0A3C; 159 | 84 : 2D3C2B3C; 160 | 85 : 3E3E3E3E; 161 | 86 : 3C2B3E5B; 162 | 87 : 2B2B3C3C; 163 | 88 : 2B2B2B2B; 164 | 89 : 3C2B2B2B; 165 | 8A : 3E3E3E2D; 166 | 8B : 3C3C5D2D; 167 | 8C : 5B3C3C3C; 168 | 8D : 2B0A3E3E; 169 | 8E : 5D2D3C3C; 170 | 8F : 2D5B3C2B; 171 | 90 : 5D3C2D3E; 172 | 91 : 3E3E5B3E; 173 | 92 : 3C3C3C2E; 174 | 93 : 2E2B5B3C; 175 | 94 : 5D5D2D5B; 176 | 95 : 5D2D3E3E; 177 | 96 : 3E3E5B3E; 178 | 97 : 0A3C3C2E; 179 | 98 : 5B3E5D2D; 180 | 99 : 5B3E5D2D; 181 | 9A : 3E3E5D2D; 182 | 9B : 3E3E5B3E; 183 | 9C : 3C3C3C5B; 184 | 9D : 3C3C3C3C; 185 | 9E : 3E3E2B3C; 186 | 9F : 3E3E3E3E; 187 | A0 : 5D2D3E3E; 188 | A1 : 5D2D3C3C; 189 | A2 : 3E3E5D0A; 190 | A3 : 3C5D2D5B; 191 | A4 : 2D5B3C3C; 192 | A5 : 3C3C3C5D; 193 | A6 : 3C3C3C3C; 194 | A7 : 2B2B5D3C; 195 | A8 : 2B2B2B2B; 196 | A9 : 2B2B2B2B; 197 | AA : 000A0A2E; 198 | 199 | END; 200 | -------------------------------------------------------------------------------- /tools/txt2mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/moizumi99/brainf__k_CPU/a9dd602500472a022e1263783df6555ecf9b460e/tools/txt2mif -------------------------------------------------------------------------------- /tools/txt2mif.c: -------------------------------------------------------------------------------- 1 | #include 2 | #define BYTES_PER_LINE 4 3 | 4 | void main(int argc, char *argv[]) { 5 | FILE *f1, *f2; 6 | int c; 7 | int i; 8 | int data; 9 | int adr=0; 10 | 11 | if (argc<3) { 12 | printf("txt2mif text_file_name mif_file_name\n"); 13 | } 14 | f1=fopen(argv[1], "r"); 15 | if (f1==NULL) { 16 | printf("Error opening %s\n", argv[1]); 17 | return; 18 | } 19 | f2=fopen(argv[2], "w"); 20 | if (f2==NULL) { 21 | printf("Error opening %s\n", argv[2]); 22 | return; 23 | } 24 | 25 | i = 0; 26 | while((c=fgetc(f1)) != EOF) { 27 | if (i==0) { 28 | fputs("-- ", f2); 29 | } 30 | i++; 31 | fputc(c, f2); 32 | if (c=='\n') { 33 | i=0; 34 | } 35 | if (i==80) { 36 | fputs("\n\n", f2); 37 | } 38 | } 39 | 40 | fseek(f1, 0, SEEK_SET); 41 | 42 | fprintf(f2, "DEPTH = 4096;\n"); 43 | fprintf(f2, "WIDTH = 32;\n"); 44 | fprintf(f2, "ADDRESS_RADIX = HEX;\n"); 45 | fprintf(f2, "DATA_RADIX = HEX;\n"); 46 | fprintf(f2, "CONTENT\n"); 47 | fprintf(f2, "BEGIN\n\n"); 48 | 49 | i = 0; 50 | adr = 0; 51 | data = 0; 52 | while((c=fgetc(f1)) != EOF) { 53 | data = data | (c << (8*i)); 54 | if (i==3) { 55 | fprintf(f2, "%02X : %08X;\n", adr, data); 56 | adr++; 57 | i=0; 58 | data = 0; 59 | } else { 60 | i++; 61 | } 62 | } 63 | if (i!=0) { 64 | fprintf(f2, "%02X : %08X;\n", adr, data); 65 | } 66 | fprintf(f2, "\nEND;\n"); 67 | fclose(f1); 68 | fclose(f2); 69 | 70 | return; 71 | } 72 | --------------------------------------------------------------------------------