├── stm32f411_fw_nrf24l01p
├── .gitignore
├── Drivers
│ ├── CMSIS
│ │ ├── Device
│ │ │ └── ST
│ │ │ │ └── STM32F4xx
│ │ │ │ └── Include
│ │ │ │ ├── stm32f4xx.h
│ │ │ │ └── system_stm32f4xx.h
│ │ └── Include
│ │ │ ├── cmsis_version.h
│ │ │ ├── tz_context.h
│ │ │ ├── cmsis_compiler.h
│ │ │ ├── mpu_armv8.h
│ │ │ └── mpu_armv7.h
│ └── STM32F4xx_HAL_Driver
│ │ ├── Inc
│ │ ├── stm32f4xx_hal_flash_ramfunc.h
│ │ ├── stm32f4xx_hal_dma_ex.h
│ │ ├── stm32f4xx_hal_def.h
│ │ ├── stm32f4xx_hal.h
│ │ └── stm32f4xx_hal_gpio.h
│ │ └── Src
│ │ ├── stm32f4xx_hal_flash_ramfunc.c
│ │ └── stm32f4xx_hal_dma_ex.c
├── .settings
│ ├── org.eclipse.cdt.core.prefs
│ ├── stm32cubeide.project.prefs
│ └── language.settings.xml
├── .project
├── Core
│ ├── Inc
│ │ ├── gpio.h
│ │ ├── spi.h
│ │ ├── stm32f4xx_it.h
│ │ └── main.h
│ └── Src
│ │ ├── stm32f4xx_hal_msp.c
│ │ ├── sysmem.c
│ │ ├── gpio.c
│ │ ├── syscalls.c
│ │ ├── spi.c
│ │ ├── stm32f4xx_it.c
│ │ └── main.c
├── nRF24L01p
│ ├── nrf24l01p.h
│ └── nrf24l01p.c
├── STM32F411CEUX_RAM.ld
├── STM32F411CEUX_FLASH.ld
├── stm32f411_fw_nrf24l01p.ioc
├── .mxproject
├── stm32f411_fw_receiver Debug.launch
└── stm32f411_fw_nrf24l01p Debug.launch
├── README.md
├── nrf24l01p.h
└── nrf24l01p.c
/stm32f411_fw_nrf24l01p/.gitignore:
--------------------------------------------------------------------------------
1 | /Debug/
2 |
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/stm32f411_fw_nrf24l01p/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
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https://raw.githubusercontent.com/mokhwasomssi/stm32_hal_nrf24l01p/HEAD/stm32f411_fw_nrf24l01p/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
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/stm32f411_fw_nrf24l01p/.settings/org.eclipse.cdt.core.prefs:
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1 | doxygen/doxygen_new_line_after_brief=true
2 | doxygen/doxygen_use_brief_tag=false
3 | doxygen/doxygen_use_javadoc_tags=true
4 | doxygen/doxygen_use_pre_tag=false
5 | doxygen/doxygen_use_structural_commands=false
6 | eclipse.preferences.version=1
7 |
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4 | DC22A860405A8BF2F2C095E5B6529F12=84C3300637DB61C09F66C8A399419EB3
5 | eclipse.preferences.version=1
6 |
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/stm32f411_fw_nrf24l01p/.project:
--------------------------------------------------------------------------------
1 |
2 |
3 | stm32f411_fw_nrf24l01p
4 |
5 |
6 |
7 |
8 |
9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder
10 | clean,full,incremental,
11 |
12 |
13 |
14 |
15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
16 | full,incremental,
17 |
18 |
19 |
20 |
21 |
22 | com.st.stm32cube.ide.mcu.MCUProjectNature
23 | com.st.stm32cube.ide.mcu.MCUCubeProjectNature
24 | org.eclipse.cdt.core.cnature
25 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature
26 | com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
27 | com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
28 | com.st.stm32cube.ide.mcu.MCURootProjectNature
29 | org.eclipse.cdt.managedbuilder.core.managedBuildNature
30 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
31 |
32 |
33 |
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/stm32f411_fw_nrf24l01p/Core/Inc/gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file gpio.h
4 | * @brief This file contains all the function prototypes for
5 | * the gpio.c file
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __GPIO_H__
21 | #define __GPIO_H__
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "main.h"
29 |
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* USER CODE BEGIN Private defines */
35 |
36 | /* USER CODE END Private defines */
37 |
38 | void MX_GPIO_Init(void);
39 |
40 | /* USER CODE BEGIN Prototypes */
41 |
42 | /* USER CODE END Prototypes */
43 |
44 | #ifdef __cplusplus
45 | }
46 | #endif
47 | #endif /*__ GPIO_H__ */
48 |
49 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
50 |
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/stm32f411_fw_nrf24l01p/Core/Inc/spi.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file spi.h
4 | * @brief This file contains all the function prototypes for
5 | * the spi.c file
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __SPI_H__
21 | #define __SPI_H__
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "main.h"
29 |
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | extern SPI_HandleTypeDef hspi2;
35 |
36 | /* USER CODE BEGIN Private defines */
37 |
38 | /* USER CODE END Private defines */
39 |
40 | void MX_SPI2_Init(void);
41 |
42 | /* USER CODE BEGIN Prototypes */
43 |
44 | /* USER CODE END Prototypes */
45 |
46 | #ifdef __cplusplus
47 | }
48 | #endif
49 |
50 | #endif /* __SPI_H__ */
51 |
52 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
53 |
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/stm32f411_fw_nrf24l01p/Drivers/CMSIS/Include/cmsis_version.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_version.h
3 | * @brief CMSIS Core(M) Version definitions
4 | * @version V5.0.2
5 | * @date 19. April 2017
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef __CMSIS_VERSION_H
32 | #define __CMSIS_VERSION_H
33 |
34 | /* CMSIS Version definitions */
35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
39 | #endif
40 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Core/Inc/stm32f4xx_it.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_IT_H
23 | #define __STM32F4xx_IT_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Private includes ----------------------------------------------------------*/
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 | /* USER CODE BEGIN ET */
36 |
37 | /* USER CODE END ET */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 | /* USER CODE BEGIN EC */
41 |
42 | /* USER CODE END EC */
43 |
44 | /* Exported macro ------------------------------------------------------------*/
45 | /* USER CODE BEGIN EM */
46 |
47 | /* USER CODE END EM */
48 |
49 | /* Exported functions prototypes ---------------------------------------------*/
50 | void NMI_Handler(void);
51 | void HardFault_Handler(void);
52 | void MemManage_Handler(void);
53 | void BusFault_Handler(void);
54 | void UsageFault_Handler(void);
55 | void SVC_Handler(void);
56 | void DebugMon_Handler(void);
57 | void PendSV_Handler(void);
58 | void SysTick_Handler(void);
59 | void EXTI9_5_IRQHandler(void);
60 | /* USER CODE BEGIN EFP */
61 |
62 | /* USER CODE END EFP */
63 |
64 | #ifdef __cplusplus
65 | }
66 | #endif
67 |
68 | #endif /* __STM32F4xx_IT_H */
69 |
70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
71 |
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/stm32f411_fw_nrf24l01p/Core/Src/stm32f4xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_hal_msp.c
5 | * @brief This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2021 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "main.h"
24 | /* USER CODE BEGIN Includes */
25 |
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN Define */
35 |
36 | /* USER CODE END Define */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN Macro */
40 |
41 | /* USER CODE END Macro */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* External functions --------------------------------------------------------*/
54 | /* USER CODE BEGIN ExternalFunctions */
55 |
56 | /* USER CODE END ExternalFunctions */
57 |
58 | /* USER CODE BEGIN 0 */
59 |
60 | /* USER CODE END 0 */
61 | /**
62 | * Initializes the Global MSP.
63 | */
64 | void HAL_MspInit(void)
65 | {
66 | /* USER CODE BEGIN MspInit 0 */
67 |
68 | /* USER CODE END MspInit 0 */
69 |
70 | __HAL_RCC_SYSCFG_CLK_ENABLE();
71 | __HAL_RCC_PWR_CLK_ENABLE();
72 |
73 | /* System interrupt init*/
74 |
75 | /* USER CODE BEGIN MspInit 1 */
76 |
77 | /* USER CODE END MspInit 1 */
78 | }
79 |
80 | /* USER CODE BEGIN 1 */
81 |
82 | /* USER CODE END 1 */
83 |
84 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
85 |
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/stm32f411_fw_nrf24l01p/Core/Inc/main.h:
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1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2021 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MAIN_H
24 | #define __MAIN_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_hal.h"
32 |
33 | /* Private includes ----------------------------------------------------------*/
34 | /* USER CODE BEGIN Includes */
35 |
36 | /* USER CODE END Includes */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* USER CODE BEGIN ET */
40 |
41 | /* USER CODE END ET */
42 |
43 | /* Exported constants --------------------------------------------------------*/
44 | /* USER CODE BEGIN EC */
45 |
46 | /* USER CODE END EC */
47 |
48 | /* Exported macro ------------------------------------------------------------*/
49 | /* USER CODE BEGIN EM */
50 |
51 | /* USER CODE END EM */
52 |
53 | /* Exported functions prototypes ---------------------------------------------*/
54 | void Error_Handler(void);
55 |
56 | /* USER CODE BEGIN EFP */
57 |
58 | /* USER CODE END EFP */
59 |
60 | /* Private defines -----------------------------------------------------------*/
61 | #define LED_Pin GPIO_PIN_13
62 | #define LED_GPIO_Port GPIOC
63 | #define CE_Pin GPIO_PIN_12
64 | #define CE_GPIO_Port GPIOB
65 | #define SPI2_CSN_Pin GPIO_PIN_13
66 | #define SPI2_CSN_GPIO_Port GPIOB
67 | #define IRQ_Pin GPIO_PIN_8
68 | #define IRQ_GPIO_Port GPIOA
69 | #define IRQ_EXTI_IRQn EXTI9_5_IRQn
70 | /* USER CODE BEGIN Private defines */
71 |
72 | /* USER CODE END Private defines */
73 |
74 | #ifdef __cplusplus
75 | }
76 | #endif
77 |
78 | #endif /* __MAIN_H */
79 |
80 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
81 |
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/stm32f411_fw_nrf24l01p/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash_ramfunc.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH RAMFUNC driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_FLASH_RAMFUNC_H
22 | #define __STM32F4xx_FLASH_RAMFUNC_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
28 | defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_hal_def.h"
32 |
33 | /** @addtogroup STM32F4xx_HAL_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup FLASH_RAMFUNC
38 | * @{
39 | */
40 |
41 | /* Exported types ------------------------------------------------------------*/
42 | /* Exported macro ------------------------------------------------------------*/
43 | /* Exported functions --------------------------------------------------------*/
44 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions
45 | * @{
46 | */
47 |
48 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
49 | * @{
50 | */
51 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);
52 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);
53 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);
54 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
55 | /**
56 | * @}
57 | */
58 |
59 | /**
60 | * @}
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
72 | #ifdef __cplusplus
73 | }
74 | #endif
75 |
76 |
77 | #endif /* __STM32F4xx_FLASH_RAMFUNC_H */
78 |
79 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
80 |
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/stm32f411_fw_nrf24l01p/Drivers/CMSIS/Include/tz_context.h:
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1 | /******************************************************************************
2 | * @file tz_context.h
3 | * @brief Context Management for Armv8-M TrustZone
4 | * @version V1.0.1
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef TZ_CONTEXT_H
32 | #define TZ_CONTEXT_H
33 |
34 | #include
35 |
36 | #ifndef TZ_MODULEID_T
37 | #define TZ_MODULEID_T
38 | /// \details Data type that identifies secure software modules called by a process.
39 | typedef uint32_t TZ_ModuleId_t;
40 | #endif
41 |
42 | /// \details TZ Memory ID identifies an allocated memory slot.
43 | typedef uint32_t TZ_MemoryId_t;
44 |
45 | /// Initialize secure context memory system
46 | /// \return execution status (1: success, 0: error)
47 | uint32_t TZ_InitContextSystem_S (void);
48 |
49 | /// Allocate context memory for calling secure software modules in TrustZone
50 | /// \param[in] module identifies software modules called from non-secure mode
51 | /// \return value != 0 id TrustZone memory slot identifier
52 | /// \return value 0 no memory available or internal error
53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
54 |
55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
56 | /// \param[in] id TrustZone memory slot identifier
57 | /// \return execution status (1: success, 0: error)
58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
59 |
60 | /// Load secure context (called on RTOS thread context switch)
61 | /// \param[in] id TrustZone memory slot identifier
62 | /// \return execution status (1: success, 0: error)
63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
64 |
65 | /// Store secure context (called on RTOS thread context switch)
66 | /// \param[in] id TrustZone memory slot identifier
67 | /// \return execution status (1: success, 0: error)
68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
69 |
70 | #endif // TZ_CONTEXT_H
71 |
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/stm32f411_fw_nrf24l01p/.settings/language.settings.xml:
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/stm32f411_fw_nrf24l01p/Core/Src/sysmem.c:
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1 | /**
2 | ******************************************************************************
3 | * @file sysmem.c
4 | * @author Generated by STM32CubeIDE
5 | * @brief STM32CubeIDE System Memory calls file
6 | *
7 | * For more information about which C functions
8 | * need which of these lowlevel functions
9 | * please consult the newlib libc manual
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © Copyright (c) 2020 STMicroelectronics.
14 | * All rights reserved.
15 | *
16 | * This software component is licensed by ST under BSD 3-Clause license,
17 | * the "License"; You may not use this file except in compliance with the
18 | * License. You may obtain a copy of the License at:
19 | * opensource.org/licenses/BSD-3-Clause
20 | *
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes */
25 | #include
26 | #include
27 |
28 | /**
29 | * Pointer to the current high watermark of the heap usage
30 | */
31 | static uint8_t *__sbrk_heap_end = NULL;
32 |
33 | /**
34 | * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
35 | * and others from the C library
36 | *
37 | * @verbatim
38 | * ############################################################################
39 | * # .data # .bss # newlib heap # MSP stack #
40 | * # # # # Reserved by _Min_Stack_Size #
41 | * ############################################################################
42 | * ^-- RAM start ^-- _end _estack, RAM end --^
43 | * @endverbatim
44 | *
45 | * This implementation starts allocating at the '_end' linker symbol
46 | * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
47 | * The implementation considers '_estack' linker symbol to be RAM end
48 | * NOTE: If the MSP stack, at any point during execution, grows larger than the
49 | * reserved size, please increase the '_Min_Stack_Size'.
50 | *
51 | * @param incr Memory size
52 | * @return Pointer to allocated memory
53 | */
54 | void *_sbrk(ptrdiff_t incr)
55 | {
56 | extern uint8_t _end; /* Symbol defined in the linker script */
57 | extern uint8_t _estack; /* Symbol defined in the linker script */
58 | extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
59 | const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
60 | const uint8_t *max_heap = (uint8_t *)stack_limit;
61 | uint8_t *prev_heap_end;
62 |
63 | /* Initialize heap end at first call */
64 | if (NULL == __sbrk_heap_end)
65 | {
66 | __sbrk_heap_end = &_end;
67 | }
68 |
69 | /* Protect heap from growing into the reserved MSP stack */
70 | if (__sbrk_heap_end + incr > max_heap)
71 | {
72 | errno = ENOMEM;
73 | return (void *)-1;
74 | }
75 |
76 | prev_heap_end = __sbrk_heap_end;
77 | __sbrk_heap_end += incr;
78 |
79 | return (void *)prev_heap_end;
80 | }
81 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Core/Src/gpio.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file gpio.c
4 | * @brief This file provides code for the configuration
5 | * of all used GPIO pins.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "gpio.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | /*----------------------------------------------------------------------------*/
28 | /* Configure GPIO */
29 | /*----------------------------------------------------------------------------*/
30 | /* USER CODE BEGIN 1 */
31 |
32 | /* USER CODE END 1 */
33 |
34 | /** Configure pins as
35 | * Analog
36 | * Input
37 | * Output
38 | * EVENT_OUT
39 | * EXTI
40 | */
41 | void MX_GPIO_Init(void)
42 | {
43 |
44 | GPIO_InitTypeDef GPIO_InitStruct = {0};
45 |
46 | /* GPIO Ports Clock Enable */
47 | __HAL_RCC_GPIOC_CLK_ENABLE();
48 | __HAL_RCC_GPIOH_CLK_ENABLE();
49 | __HAL_RCC_GPIOB_CLK_ENABLE();
50 | __HAL_RCC_GPIOA_CLK_ENABLE();
51 |
52 | /*Configure GPIO pin Output Level */
53 | HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_SET);
54 |
55 | /*Configure GPIO pin Output Level */
56 | HAL_GPIO_WritePin(CE_GPIO_Port, CE_Pin, GPIO_PIN_RESET);
57 |
58 | /*Configure GPIO pin Output Level */
59 | HAL_GPIO_WritePin(SPI2_CSN_GPIO_Port, SPI2_CSN_Pin, GPIO_PIN_SET);
60 |
61 | /*Configure GPIO pin : PtPin */
62 | GPIO_InitStruct.Pin = LED_Pin;
63 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
64 | GPIO_InitStruct.Pull = GPIO_NOPULL;
65 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
66 | HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
67 |
68 | /*Configure GPIO pins : PBPin PBPin */
69 | GPIO_InitStruct.Pin = CE_Pin|SPI2_CSN_Pin;
70 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
71 | GPIO_InitStruct.Pull = GPIO_NOPULL;
72 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
73 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
74 |
75 | /*Configure GPIO pin : PtPin */
76 | GPIO_InitStruct.Pin = IRQ_Pin;
77 | GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
78 | GPIO_InitStruct.Pull = GPIO_NOPULL;
79 | HAL_GPIO_Init(IRQ_GPIO_Port, &GPIO_InitStruct);
80 |
81 | /* EXTI interrupt init*/
82 | HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
83 | HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
84 |
85 | }
86 |
87 | /* USER CODE BEGIN 2 */
88 |
89 | /* USER CODE END 2 */
90 |
91 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
92 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_dma_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of DMA HAL extension module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_DMA_EX_H
22 | #define __STM32F4xx_HAL_DMA_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup DMAEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
41 | * @brief DMAEx Exported types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief HAL DMA Memory definition
47 | */
48 | typedef enum
49 | {
50 | MEMORY0 = 0x00U, /*!< Memory 0 */
51 | MEMORY1 = 0x01U /*!< Memory 1 */
52 | }HAL_DMA_MemoryTypeDef;
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /* Exported functions --------------------------------------------------------*/
59 | /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
60 | * @brief DMAEx Exported functions
61 | * @{
62 | */
63 |
64 | /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
65 | * @brief Extended features functions
66 | * @{
67 | */
68 |
69 | /* IO operation functions *******************************************************/
70 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
71 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
72 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
73 |
74 | /**
75 | * @}
76 | */
77 | /**
78 | * @}
79 | */
80 |
81 | /* Private functions ---------------------------------------------------------*/
82 | /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
83 | * @brief DMAEx Private functions
84 | * @{
85 | */
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | #ifdef __cplusplus
99 | }
100 | #endif
101 |
102 | #endif /*__STM32F4xx_HAL_DMA_EX_H*/
103 |
104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
105 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Core/Src/syscalls.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file syscalls.c
4 | * @author Auto-generated by STM32CubeIDE
5 | * @brief STM32CubeIDE Minimal System calls file
6 | *
7 | * For more information about which c-functions
8 | * need which of these lowlevel functions
9 | * please consult the Newlib libc-manual
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © Copyright (c) 2020 STMicroelectronics.
14 | * All rights reserved.
15 | *
16 | * This software component is licensed by ST under BSD 3-Clause license,
17 | * the "License"; You may not use this file except in compliance with the
18 | * License. You may obtain a copy of the License at:
19 | * opensource.org/licenses/BSD-3-Clause
20 | *
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes */
25 | #include
26 | #include
27 | #include
28 | #include
29 | #include
30 | #include
31 | #include
32 | #include
33 |
34 |
35 | /* Variables */
36 | extern int __io_putchar(int ch) __attribute__((weak));
37 | extern int __io_getchar(void) __attribute__((weak));
38 |
39 |
40 | char *__env[1] = { 0 };
41 | char **environ = __env;
42 |
43 |
44 | /* Functions */
45 | void initialise_monitor_handles()
46 | {
47 | }
48 |
49 | int _getpid(void)
50 | {
51 | return 1;
52 | }
53 |
54 | int _kill(int pid, int sig)
55 | {
56 | errno = EINVAL;
57 | return -1;
58 | }
59 |
60 | void _exit (int status)
61 | {
62 | _kill(status, -1);
63 | while (1) {} /* Make sure we hang here */
64 | }
65 |
66 | __attribute__((weak)) int _read(int file, char *ptr, int len)
67 | {
68 | int DataIdx;
69 |
70 | for (DataIdx = 0; DataIdx < len; DataIdx++)
71 | {
72 | *ptr++ = __io_getchar();
73 | }
74 |
75 | return len;
76 | }
77 |
78 | __attribute__((weak)) int _write(int file, char *ptr, int len)
79 | {
80 | int DataIdx;
81 |
82 | for (DataIdx = 0; DataIdx < len; DataIdx++)
83 | {
84 | __io_putchar(*ptr++);
85 | }
86 | return len;
87 | }
88 |
89 | int _close(int file)
90 | {
91 | return -1;
92 | }
93 |
94 |
95 | int _fstat(int file, struct stat *st)
96 | {
97 | st->st_mode = S_IFCHR;
98 | return 0;
99 | }
100 |
101 | int _isatty(int file)
102 | {
103 | return 1;
104 | }
105 |
106 | int _lseek(int file, int ptr, int dir)
107 | {
108 | return 0;
109 | }
110 |
111 | int _open(char *path, int flags, ...)
112 | {
113 | /* Pretend like we always fail */
114 | return -1;
115 | }
116 |
117 | int _wait(int *status)
118 | {
119 | errno = ECHILD;
120 | return -1;
121 | }
122 |
123 | int _unlink(char *name)
124 | {
125 | errno = ENOENT;
126 | return -1;
127 | }
128 |
129 | int _times(struct tms *buf)
130 | {
131 | return -1;
132 | }
133 |
134 | int _stat(char *file, struct stat *st)
135 | {
136 | st->st_mode = S_IFCHR;
137 | return 0;
138 | }
139 |
140 | int _link(char *old, char *new)
141 | {
142 | errno = EMLINK;
143 | return -1;
144 | }
145 |
146 | int _fork(void)
147 | {
148 | errno = EAGAIN;
149 | return -1;
150 | }
151 |
152 | int _execve(char *name, char **argv, char **env)
153 | {
154 | errno = ENOMEM;
155 | return -1;
156 | }
157 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Core/Src/spi.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file spi.c
4 | * @brief This file provides code for the configuration
5 | * of the SPI instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "spi.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | SPI_HandleTypeDef hspi2;
28 |
29 | /* SPI2 init function */
30 | void MX_SPI2_Init(void)
31 | {
32 |
33 | /* USER CODE BEGIN SPI2_Init 0 */
34 |
35 | /* USER CODE END SPI2_Init 0 */
36 |
37 | /* USER CODE BEGIN SPI2_Init 1 */
38 |
39 | /* USER CODE END SPI2_Init 1 */
40 | hspi2.Instance = SPI2;
41 | hspi2.Init.Mode = SPI_MODE_MASTER;
42 | hspi2.Init.Direction = SPI_DIRECTION_2LINES;
43 | hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
44 | hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
45 | hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
46 | hspi2.Init.NSS = SPI_NSS_SOFT;
47 | hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
48 | hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
49 | hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
50 | hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
51 | hspi2.Init.CRCPolynomial = 10;
52 | if (HAL_SPI_Init(&hspi2) != HAL_OK)
53 | {
54 | Error_Handler();
55 | }
56 | /* USER CODE BEGIN SPI2_Init 2 */
57 |
58 | /* USER CODE END SPI2_Init 2 */
59 |
60 | }
61 |
62 | void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
63 | {
64 |
65 | GPIO_InitTypeDef GPIO_InitStruct = {0};
66 | if(spiHandle->Instance==SPI2)
67 | {
68 | /* USER CODE BEGIN SPI2_MspInit 0 */
69 |
70 | /* USER CODE END SPI2_MspInit 0 */
71 | /* SPI2 clock enable */
72 | __HAL_RCC_SPI2_CLK_ENABLE();
73 |
74 | __HAL_RCC_GPIOB_CLK_ENABLE();
75 | /**SPI2 GPIO Configuration
76 | PB10 ------> SPI2_SCK
77 | PB14 ------> SPI2_MISO
78 | PB15 ------> SPI2_MOSI
79 | */
80 | GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_14|GPIO_PIN_15;
81 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
82 | GPIO_InitStruct.Pull = GPIO_NOPULL;
83 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
84 | GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
85 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
86 |
87 | /* USER CODE BEGIN SPI2_MspInit 1 */
88 |
89 | /* USER CODE END SPI2_MspInit 1 */
90 | }
91 | }
92 |
93 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
94 | {
95 |
96 | if(spiHandle->Instance==SPI2)
97 | {
98 | /* USER CODE BEGIN SPI2_MspDeInit 0 */
99 |
100 | /* USER CODE END SPI2_MspDeInit 0 */
101 | /* Peripheral clock disable */
102 | __HAL_RCC_SPI2_CLK_DISABLE();
103 |
104 | /**SPI2 GPIO Configuration
105 | PB10 ------> SPI2_SCK
106 | PB14 ------> SPI2_MISO
107 | PB15 ------> SPI2_MOSI
108 | */
109 | HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_14|GPIO_PIN_15);
110 |
111 | /* USER CODE BEGIN SPI2_MspDeInit 1 */
112 |
113 | /* USER CODE END SPI2_MspDeInit 1 */
114 | }
115 | }
116 |
117 | /* USER CODE BEGIN 1 */
118 |
119 | /* USER CODE END 1 */
120 |
121 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
122 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # stm32_hal_nrf24l01p
2 |
3 | ## Brief
4 |
5 | __nRF24L01+ is a single chip 2.4GHz transceiver.__
6 | ___TAG__ - `nRF24L01+` `SPI` `STM32 HAL`_
7 |
8 | 
9 |
10 | ## Library Features
11 | - 1:1 transaction
12 | - Static payload lengths (1 - 32bytes)
13 | - Use IRQ Pin
14 |
15 | ## Dev Environment
16 | - STM32CubeIDE
17 | - STM32 HAL driver
18 | - STM32F411
19 | - nRF24L01+ Module ([NRF24L01+PA+LNA 2.4GHz Wireless RF Transceiver Module](https://electropeak.com/nrf24l01-pa-lna-wireless-module))
20 | - Pinout
21 |
22 | 
23 | |Name|Description|
24 | |:---:|:---:|
25 | |VCC, GND|Power Supply, 1.9V - 3.6V|
26 | |MOSI, MISO, SCK, CSN|SPI|
27 | |CE|Chip Enable|
28 | |IRQ|Interrupt Pin, Active Low|
29 |
30 | ## STM32CubeMX
31 | - Project Manager
32 | 
33 |
34 | - SPI
35 | 
36 |
37 | - CSN, CE (GPIO_OUTPUT)
38 | 
39 |
40 | 
41 |
42 | - IRQ (GPIO_EXIT)
43 | 
44 |
45 | 
46 |
47 |
48 | ## Example
49 |
50 | ### nrf24l01p.h
51 | - SPI2, PB13 (CSN), PB12 (CE), PA8 (IRQ), Payload length 8
52 |
53 | ```c
54 | /* User Configurations */
55 | #define NRF24L01P_SPI (&hspi2)
56 |
57 | #define NRF24L01P_SPI_CS_PIN_PORT GPIOB
58 | #define NRF24L01P_SPI_CS_PIN_NUMBER GPIO_PIN_13
59 |
60 | #define NRF24L01P_CE_PIN_PORT GPIOB
61 | #define NRF24L01P_CE_PIN_NUMBER GPIO_PIN_12
62 |
63 | #define NRF24L01P_IRQ_PIN_PORT GPIOA
64 | #define NRF24L01P_IRQ_PIN_NUMBER GPIO_PIN_8
65 |
66 | #define NRF24L01P_PAYLOAD_LENGTH 8 // 1 - 32bytes
67 | ```
68 |
69 | ### main.c
70 | - Only contain relative things
71 |
72 | #### Transmitter
73 | ```c
74 | #include "nrf24l01p.h"
75 |
76 | // data array to be sent
77 | uint8_t tx_data[NRF24L01P_PAYLOAD_LENGTH] = {0, 1, 2, 3, 4, 5, 6, 7};
78 |
79 | // for rx interrupt
80 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
81 |
82 | int main(void)
83 | {
84 | nrf24l01p_tx_init(2500, _1Mbps);
85 |
86 | while (1)
87 | {
88 | // change tx datas
89 | for(int i= 0; i < 8; i++)
90 | tx_data[i]++;
91 |
92 | // transmit
93 | nrf24l01p_tx_transmit(tx_data);
94 | HAL_Delay(100);
95 | }
96 | }
97 |
98 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
99 | {
100 | if(GPIO_Pin == NRF24L01P_IRQ_PIN_NUMBER)
101 | nrf24l01p_tx_irq(); // clear interrupt flag
102 | }
103 | ```
104 |
105 | #### Receiver
106 | ```c
107 | #include "nrf24l01p.h"
108 |
109 | // data array to be read
110 | uint8_t rx_data[NRF24L01P_PAYLOAD_LENGTH] = { 0, };
111 |
112 | // for tx interrupt
113 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
114 |
115 | int main(void)
116 | {
117 | nrf24l01p_rx_init(2500, _1Mbps);
118 |
119 | while (1)
120 | {
121 | // Nothing to do
122 | HAL_Delay(100);
123 | }
124 | }
125 |
126 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
127 | {
128 | if(GPIO_Pin == NRF24L01P_IRQ_PIN_NUMBER)
129 | nrf24l01p_rx_receive(rx_data); // read data when data ready flag is set
130 | }
131 | ```
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f4xx.h
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © COPYRIGHT(c) 2017 STMicroelectronics
10 | *
11 | * Redistribution and use in source and binary forms, with or without modification,
12 | * are permitted provided that the following conditions are met:
13 | * 1. Redistributions of source code must retain the above copyright notice,
14 | * this list of conditions and the following disclaimer.
15 | * 2. Redistributions in binary form must reproduce the above copyright notice,
16 | * this list of conditions and the following disclaimer in the documentation
17 | * and/or other materials provided with the distribution.
18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 | * may be used to endorse or promote products derived from this software
20 | * without specific prior written permission.
21 | *
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 | *
33 | ******************************************************************************
34 | */
35 |
36 | /** @addtogroup CMSIS
37 | * @{
38 | */
39 |
40 | /** @addtogroup stm32f4xx_system
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief Define to prevent recursive inclusion
46 | */
47 | #ifndef __SYSTEM_STM32F4XX_H
48 | #define __SYSTEM_STM32F4XX_H
49 |
50 | #ifdef __cplusplus
51 | extern "C" {
52 | #endif
53 |
54 | /** @addtogroup STM32F4xx_System_Includes
55 | * @{
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 |
63 | /** @addtogroup STM32F4xx_System_Exported_types
64 | * @{
65 | */
66 | /* This variable is updated in three ways:
67 | 1) by calling CMSIS function SystemCoreClockUpdate()
68 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
69 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
70 | Note: If you use this function to configure the system clock; then there
71 | is no need to call the 2 first functions listed above, since SystemCoreClock
72 | variable is updated automatically.
73 | */
74 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
75 |
76 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
77 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
78 |
79 | /**
80 | * @}
81 | */
82 |
83 | /** @addtogroup STM32F4xx_System_Exported_Constants
84 | * @{
85 | */
86 |
87 | /**
88 | * @}
89 | */
90 |
91 | /** @addtogroup STM32F4xx_System_Exported_Macros
92 | * @{
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 |
99 | /** @addtogroup STM32F4xx_System_Exported_Functions
100 | * @{
101 | */
102 |
103 | extern void SystemInit(void);
104 | extern void SystemCoreClockUpdate(void);
105 | /**
106 | * @}
107 | */
108 |
109 | #ifdef __cplusplus
110 | }
111 | #endif
112 |
113 | #endif /*__SYSTEM_STM32F4XX_H */
114 |
115 | /**
116 | * @}
117 | */
118 |
119 | /**
120 | * @}
121 | */
122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
123 |
--------------------------------------------------------------------------------
/nrf24l01p.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * nrf24l01_plus.h
4 | *
5 | * Created on: 2021. 7. 20.
6 | * Author: mokhwasomssi
7 | *
8 | */
9 |
10 |
11 | #ifndef __NRF24L01P_H__
12 | #define __NRF24L01P_H__
13 |
14 |
15 | #include "spi.h" // header from stm32cubemx code generate
16 | #include
17 |
18 |
19 | /* User Configurations */
20 | #define NRF24L01P_SPI (&hspi2)
21 |
22 | #define NRF24L01P_SPI_CS_PIN_PORT GPIOB
23 | #define NRF24L01P_SPI_CS_PIN_NUMBER GPIO_PIN_13
24 |
25 | #define NRF24L01P_CE_PIN_PORT GPIOB
26 | #define NRF24L01P_CE_PIN_NUMBER GPIO_PIN_12
27 |
28 | #define NRF24L01P_IRQ_PIN_PORT GPIOA
29 | #define NRF24L01P_IRQ_PIN_NUMBER GPIO_PIN_8
30 |
31 | #define NRF24L01P_PAYLOAD_LENGTH 8 // 1 - 32bytes
32 |
33 |
34 | /* nRF24L01+ typedefs */
35 | typedef uint8_t count;
36 | typedef uint8_t widths;
37 | typedef uint8_t length;
38 | typedef uint16_t delay;
39 | typedef uint16_t channel;
40 |
41 | typedef enum
42 | {
43 | _250kbps = 2,
44 | _1Mbps = 0,
45 | _2Mbps = 1
46 | } air_data_rate;
47 |
48 | typedef enum
49 | {
50 | _0dBm = 3,
51 | _6dBm = 2,
52 | _12dBm = 1,
53 | _18dBm = 0
54 | } output_power;
55 |
56 |
57 | /* Main Functions */
58 | void nrf24l01p_rx_init(channel MHz, air_data_rate bps);
59 | void nrf24l01p_tx_init(channel MHz, air_data_rate bps);
60 |
61 | void nrf24l01p_rx_receive(uint8_t* rx_payload);
62 | void nrf24l01p_tx_transmit(uint8_t* tx_payload);
63 |
64 | // Check tx_ds or max_rt
65 | void nrf24l01p_tx_irq();
66 |
67 |
68 | /* Sub Functions */
69 | void nrf24l01p_reset();
70 |
71 | void nrf24l01p_prx_mode();
72 | void nrf24l01p_ptx_mode();
73 |
74 | void nrf24l01p_power_up();
75 | void nrf24l01p_power_down();
76 |
77 | uint8_t nrf24l01p_get_status();
78 | uint8_t nrf24l01p_get_fifo_status();
79 |
80 | // Static payload lengths
81 | void nrf24l01p_rx_set_payload_widths(widths bytes);
82 |
83 | uint8_t nrf24l01p_read_rx_fifo(uint8_t* rx_payload);
84 | uint8_t nrf24l01p_write_tx_fifo(uint8_t* tx_payload);
85 |
86 | void nrf24l01p_flush_rx_fifo();
87 | void nrf24l01p_flush_tx_fifo();
88 |
89 | // Clear IRQ pin. Change LOW to HIGH
90 | void nrf24l01p_clear_rx_dr();
91 | void nrf24l01p_clear_tx_ds();
92 | void nrf24l01p_clear_max_rt();
93 |
94 | void nrf24l01p_set_rf_channel(channel MHz);
95 | void nrf24l01p_set_rf_tx_output_power(output_power dBm);
96 | void nrf24l01p_set_rf_air_data_rate(air_data_rate bps);
97 |
98 | void nrf24l01p_set_crc_length(length bytes);
99 | void nrf24l01p_set_address_widths(widths bytes);
100 | void nrf24l01p_auto_retransmit_count(count cnt);
101 | void nrf24l01p_auto_retransmit_delay(delay us);
102 |
103 |
104 | /* nRF24L01+ Commands */
105 | #define NRF24L01P_CMD_R_REGISTER 0b00000000
106 | #define NRF24L01P_CMD_W_REGISTER 0b00100000
107 | #define NRF24L01P_CMD_R_RX_PAYLOAD 0b01100001
108 | #define NRF24L01P_CMD_W_TX_PAYLOAD 0b10100000
109 | #define NRF24L01P_CMD_FLUSH_TX 0b11100001
110 | #define NRF24L01P_CMD_FLUSH_RX 0b11100010
111 | #define NRF24L01P_CMD_REUSE_TX_PL 0b11100011
112 | #define NRF24L01P_CMD_R_RX_PL_WID 0b01100000
113 | #define NRF24L01P_CMD_W_ACK_PAYLOAD 0b10101000
114 | #define NRF24L01P_CMD_W_TX_PAYLOAD_NOACK 0b10110000
115 | #define NRF24L01P_CMD_NOP 0b11111111
116 |
117 | /* nRF24L01+ Registers */
118 | #define NRF24L01P_REG_CONFIG 0x00
119 | #define NRF24L01P_REG_EN_AA 0x01
120 | #define NRF24L01P_REG_EN_RXADDR 0x02
121 | #define NRF24L01P_REG_SETUP_AW 0x03
122 | #define NRF24L01P_REG_SETUP_RETR 0x04
123 | #define NRF24L01P_REG_RF_CH 0x05
124 | #define NRF24L01P_REG_RF_SETUP 0x06
125 | #define NRF24L01P_REG_STATUS 0x07
126 | #define NRF24L01P_REG_OBSERVE_TX 0x08 // Read-Only
127 | #define NRF24L01P_REG_RPD 0x09 // Read-Only
128 | #define NRF24L01P_REG_RX_ADDR_P0 0x0A
129 | #define NRF24L01P_REG_RX_ADDR_P1 0x0B
130 | #define NRF24L01P_REG_RX_ADDR_P2 0x0C
131 | #define NRF24L01P_REG_RX_ADDR_P3 0x0D
132 | #define NRF24L01P_REG_RX_ADDR_P4 0x0E
133 | #define NRF24L01P_REG_RX_ADDR_P5 0x0F
134 | #define NRF24L01P_REG_TX_ADDR 0x10
135 | #define NRF24L01P_REG_RX_PW_P0 0x11
136 | #define NRF24L01P_REG_RX_PW_P1 0x12
137 | #define NRF24L01P_REG_RX_PW_P2 0x13
138 | #define NRF24L01P_REG_RX_PW_P3 0x14
139 | #define NRF24L01P_REG_RX_PW_P4 0x15
140 | #define NRF24L01P_REG_RX_PW_P5 0x16
141 | #define NRF24L01P_REG_FIFO_STATUS 0x17
142 | #define NRF24L01P_REG_DYNPD 0x1C
143 | #define NRF24L01P_REG_FEATURE 0x1D
144 |
145 |
146 | #endif /* __NRF24L01P_H__ */
147 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/nRF24L01p/nrf24l01p.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * nrf24l01_plus.h
4 | *
5 | * Created on: 2021. 7. 20.
6 | * Author: mokhwasomssi
7 | *
8 | */
9 |
10 |
11 | #ifndef __NRF24L01P_H__
12 | #define __NRF24L01P_H__
13 |
14 |
15 | #include "spi.h" // header from stm32cubemx code generate
16 | #include
17 |
18 |
19 | /* User Configurations */
20 | #define NRF24L01P_SPI (&hspi2)
21 |
22 | #define NRF24L01P_SPI_CS_PIN_PORT GPIOB
23 | #define NRF24L01P_SPI_CS_PIN_NUMBER GPIO_PIN_13
24 |
25 | #define NRF24L01P_CE_PIN_PORT GPIOB
26 | #define NRF24L01P_CE_PIN_NUMBER GPIO_PIN_12
27 |
28 | #define NRF24L01P_IRQ_PIN_PORT GPIOA
29 | #define NRF24L01P_IRQ_PIN_NUMBER GPIO_PIN_8
30 |
31 | #define NRF24L01P_PAYLOAD_LENGTH 8 // 1 - 32bytes
32 |
33 |
34 | /* nRF24L01+ typedefs */
35 | typedef uint8_t count;
36 | typedef uint8_t widths;
37 | typedef uint8_t length;
38 | typedef uint16_t delay;
39 | typedef uint16_t channel;
40 |
41 | typedef enum
42 | {
43 | _250kbps = 2,
44 | _1Mbps = 0,
45 | _2Mbps = 1
46 | } air_data_rate;
47 |
48 | typedef enum
49 | {
50 | _0dBm = 3,
51 | _6dBm = 2,
52 | _12dBm = 1,
53 | _18dBm = 0
54 | } output_power;
55 |
56 |
57 | /* Main Functions */
58 | void nrf24l01p_rx_init(channel MHz, air_data_rate bps);
59 | void nrf24l01p_tx_init(channel MHz, air_data_rate bps);
60 |
61 | void nrf24l01p_rx_receive(uint8_t* rx_payload);
62 | void nrf24l01p_tx_transmit(uint8_t* tx_payload);
63 |
64 | // Check tx_ds or max_rt
65 | void nrf24l01p_tx_irq();
66 |
67 |
68 | /* Sub Functions */
69 | void nrf24l01p_reset();
70 |
71 | void nrf24l01p_prx_mode();
72 | void nrf24l01p_ptx_mode();
73 |
74 | void nrf24l01p_power_up();
75 | void nrf24l01p_power_down();
76 |
77 | uint8_t nrf24l01p_get_status();
78 | uint8_t nrf24l01p_get_fifo_status();
79 |
80 | // Static payload lengths
81 | void nrf24l01p_rx_set_payload_widths(widths bytes);
82 |
83 | uint8_t nrf24l01p_read_rx_fifo(uint8_t* rx_payload);
84 | uint8_t nrf24l01p_write_tx_fifo(uint8_t* tx_payload);
85 |
86 | void nrf24l01p_flush_rx_fifo();
87 | void nrf24l01p_flush_tx_fifo();
88 |
89 | // Clear IRQ pin. Change LOW to HIGH
90 | void nrf24l01p_clear_rx_dr();
91 | void nrf24l01p_clear_tx_ds();
92 | void nrf24l01p_clear_max_rt();
93 |
94 | void nrf24l01p_set_rf_channel(channel MHz);
95 | void nrf24l01p_set_rf_tx_output_power(output_power dBm);
96 | void nrf24l01p_set_rf_air_data_rate(air_data_rate bps);
97 |
98 | void nrf24l01p_set_crc_length(length bytes);
99 | void nrf24l01p_set_address_widths(widths bytes);
100 | void nrf24l01p_auto_retransmit_count(count cnt);
101 | void nrf24l01p_auto_retransmit_delay(delay us);
102 |
103 |
104 | /* nRF24L01+ Commands */
105 | #define NRF24L01P_CMD_R_REGISTER 0b00000000
106 | #define NRF24L01P_CMD_W_REGISTER 0b00100000
107 | #define NRF24L01P_CMD_R_RX_PAYLOAD 0b01100001
108 | #define NRF24L01P_CMD_W_TX_PAYLOAD 0b10100000
109 | #define NRF24L01P_CMD_FLUSH_TX 0b11100001
110 | #define NRF24L01P_CMD_FLUSH_RX 0b11100010
111 | #define NRF24L01P_CMD_REUSE_TX_PL 0b11100011
112 | #define NRF24L01P_CMD_R_RX_PL_WID 0b01100000
113 | #define NRF24L01P_CMD_W_ACK_PAYLOAD 0b10101000
114 | #define NRF24L01P_CMD_W_TX_PAYLOAD_NOACK 0b10110000
115 | #define NRF24L01P_CMD_NOP 0b11111111
116 |
117 | /* nRF24L01+ Registers */
118 | #define NRF24L01P_REG_CONFIG 0x00
119 | #define NRF24L01P_REG_EN_AA 0x01
120 | #define NRF24L01P_REG_EN_RXADDR 0x02
121 | #define NRF24L01P_REG_SETUP_AW 0x03
122 | #define NRF24L01P_REG_SETUP_RETR 0x04
123 | #define NRF24L01P_REG_RF_CH 0x05
124 | #define NRF24L01P_REG_RF_SETUP 0x06
125 | #define NRF24L01P_REG_STATUS 0x07
126 | #define NRF24L01P_REG_OBSERVE_TX 0x08 // Read-Only
127 | #define NRF24L01P_REG_RPD 0x09 // Read-Only
128 | #define NRF24L01P_REG_RX_ADDR_P0 0x0A
129 | #define NRF24L01P_REG_RX_ADDR_P1 0x0B
130 | #define NRF24L01P_REG_RX_ADDR_P2 0x0C
131 | #define NRF24L01P_REG_RX_ADDR_P3 0x0D
132 | #define NRF24L01P_REG_RX_ADDR_P4 0x0E
133 | #define NRF24L01P_REG_RX_ADDR_P5 0x0F
134 | #define NRF24L01P_REG_TX_ADDR 0x10
135 | #define NRF24L01P_REG_RX_PW_P0 0x11
136 | #define NRF24L01P_REG_RX_PW_P1 0x12
137 | #define NRF24L01P_REG_RX_PW_P2 0x13
138 | #define NRF24L01P_REG_RX_PW_P3 0x14
139 | #define NRF24L01P_REG_RX_PW_P4 0x15
140 | #define NRF24L01P_REG_RX_PW_P5 0x16
141 | #define NRF24L01P_REG_FIFO_STATUS 0x17
142 | #define NRF24L01P_REG_DYNPD 0x1C
143 | #define NRF24L01P_REG_FEATURE 0x1D
144 |
145 |
146 | #endif /* __NRF24L01P_H__ */
147 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/STM32F411CEUX_RAM.ld:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file LinkerScript.ld
4 | * @author Auto-generated by STM32CubeIDE
5 | * @brief Linker script for STM32F411CEUx Device from STM32F4 series
6 | * 512Kbytes FLASH
7 | * 128Kbytes RAM
8 | *
9 | * Set heap size, stack size and stack location according
10 | * to application requirements.
11 | *
12 | * Set memory bank area and size if external memory is used
13 | ******************************************************************************
14 | * @attention
15 | *
16 | * © Copyright (c) 2020 STMicroelectronics.
17 | * All rights reserved.
18 | *
19 | * This software component is licensed by ST under BSD 3-Clause license,
20 | * the "License"; You may not use this file except in compliance with the
21 | * License. You may obtain a copy of the License at:
22 | * opensource.org/licenses/BSD-3-Clause
23 | *
24 | ******************************************************************************
25 | */
26 |
27 | /* Entry Point */
28 | ENTRY(Reset_Handler)
29 |
30 | /* Highest address of the user mode stack */
31 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
32 |
33 | _Min_Heap_Size = 0x200; /* required amount of heap */
34 | _Min_Stack_Size = 0x400; /* required amount of stack */
35 |
36 | /* Memories definition */
37 | MEMORY
38 | {
39 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
40 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
41 | }
42 |
43 | /* Sections */
44 | SECTIONS
45 | {
46 | /* The startup code into "RAM" Ram type memory */
47 | .isr_vector :
48 | {
49 | . = ALIGN(4);
50 | KEEP(*(.isr_vector)) /* Startup code */
51 | . = ALIGN(4);
52 | } >RAM
53 |
54 | /* The program code and other data into "RAM" Ram type memory */
55 | .text :
56 | {
57 | . = ALIGN(4);
58 | *(.text) /* .text sections (code) */
59 | *(.text*) /* .text* sections (code) */
60 | *(.glue_7) /* glue arm to thumb code */
61 | *(.glue_7t) /* glue thumb to arm code */
62 | *(.eh_frame)
63 | *(.RamFunc) /* .RamFunc sections */
64 | *(.RamFunc*) /* .RamFunc* sections */
65 |
66 | KEEP (*(.init))
67 | KEEP (*(.fini))
68 |
69 | . = ALIGN(4);
70 | _etext = .; /* define a global symbols at end of code */
71 | } >RAM
72 |
73 | /* Constant data into "RAM" Ram type memory */
74 | .rodata :
75 | {
76 | . = ALIGN(4);
77 | *(.rodata) /* .rodata sections (constants, strings, etc.) */
78 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
79 | . = ALIGN(4);
80 | } >RAM
81 |
82 | .ARM.extab : {
83 | . = ALIGN(4);
84 | *(.ARM.extab* .gnu.linkonce.armextab.*)
85 | . = ALIGN(4);
86 | } >RAM
87 |
88 | .ARM : {
89 | . = ALIGN(4);
90 | __exidx_start = .;
91 | *(.ARM.exidx*)
92 | __exidx_end = .;
93 | . = ALIGN(4);
94 | } >RAM
95 |
96 | .preinit_array :
97 | {
98 | . = ALIGN(4);
99 | PROVIDE_HIDDEN (__preinit_array_start = .);
100 | KEEP (*(.preinit_array*))
101 | PROVIDE_HIDDEN (__preinit_array_end = .);
102 | . = ALIGN(4);
103 | } >RAM
104 |
105 | .init_array :
106 | {
107 | . = ALIGN(4);
108 | PROVIDE_HIDDEN (__init_array_start = .);
109 | KEEP (*(SORT(.init_array.*)))
110 | KEEP (*(.init_array*))
111 | PROVIDE_HIDDEN (__init_array_end = .);
112 | . = ALIGN(4);
113 | } >RAM
114 |
115 | .fini_array :
116 | {
117 | . = ALIGN(4);
118 | PROVIDE_HIDDEN (__fini_array_start = .);
119 | KEEP (*(SORT(.fini_array.*)))
120 | KEEP (*(.fini_array*))
121 | PROVIDE_HIDDEN (__fini_array_end = .);
122 | . = ALIGN(4);
123 | } >RAM
124 |
125 | /* Used by the startup to initialize data */
126 | _sidata = LOADADDR(.data);
127 |
128 | /* Initialized data sections into "RAM" Ram type memory */
129 | .data :
130 | {
131 | . = ALIGN(4);
132 | _sdata = .; /* create a global symbol at data start */
133 | *(.data) /* .data sections */
134 | *(.data*) /* .data* sections */
135 |
136 | . = ALIGN(4);
137 | _edata = .; /* define a global symbol at data end */
138 |
139 | } >RAM
140 |
141 | /* Uninitialized data section into "RAM" Ram type memory */
142 | . = ALIGN(4);
143 | .bss :
144 | {
145 | /* This is used by the startup in order to initialize the .bss section */
146 | _sbss = .; /* define a global symbol at bss start */
147 | __bss_start__ = _sbss;
148 | *(.bss)
149 | *(.bss*)
150 | *(COMMON)
151 |
152 | . = ALIGN(4);
153 | _ebss = .; /* define a global symbol at bss end */
154 | __bss_end__ = _ebss;
155 | } >RAM
156 |
157 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
158 | ._user_heap_stack :
159 | {
160 | . = ALIGN(8);
161 | PROVIDE ( end = . );
162 | PROVIDE ( _end = . );
163 | . = . + _Min_Heap_Size;
164 | . = . + _Min_Stack_Size;
165 | . = ALIGN(8);
166 | } >RAM
167 |
168 | /* Remove information from the compiler libraries */
169 | /DISCARD/ :
170 | {
171 | libc.a ( * )
172 | libm.a ( * )
173 | libgcc.a ( * )
174 | }
175 |
176 | .ARM.attributes 0 : { *(.ARM.attributes) }
177 | }
178 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/STM32F411CEUX_FLASH.ld:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file LinkerScript.ld
4 | * @author Auto-generated by STM32CubeIDE
5 | * @brief Linker script for STM32F411CEUx Device from STM32F4 series
6 | * 512Kbytes FLASH
7 | * 128Kbytes RAM
8 | *
9 | * Set heap size, stack size and stack location according
10 | * to application requirements.
11 | *
12 | * Set memory bank area and size if external memory is used
13 | ******************************************************************************
14 | * @attention
15 | *
16 | * © Copyright (c) 2020 STMicroelectronics.
17 | * All rights reserved.
18 | *
19 | * This software component is licensed by ST under BSD 3-Clause license,
20 | * the "License"; You may not use this file except in compliance with the
21 | * License. You may obtain a copy of the License at:
22 | * opensource.org/licenses/BSD-3-Clause
23 | *
24 | ******************************************************************************
25 | */
26 |
27 | /* Entry Point */
28 | ENTRY(Reset_Handler)
29 |
30 | /* Highest address of the user mode stack */
31 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
32 |
33 | _Min_Heap_Size = 0x200 ; /* required amount of heap */
34 | _Min_Stack_Size = 0x400 ; /* required amount of stack */
35 |
36 | /* Memories definition */
37 | MEMORY
38 | {
39 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
40 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
41 | }
42 |
43 | /* Sections */
44 | SECTIONS
45 | {
46 | /* The startup code into "FLASH" Rom type memory */
47 | .isr_vector :
48 | {
49 | . = ALIGN(4);
50 | KEEP(*(.isr_vector)) /* Startup code */
51 | . = ALIGN(4);
52 | } >FLASH
53 |
54 | /* The program code and other data into "FLASH" Rom type memory */
55 | .text :
56 | {
57 | . = ALIGN(4);
58 | *(.text) /* .text sections (code) */
59 | *(.text*) /* .text* sections (code) */
60 | *(.glue_7) /* glue arm to thumb code */
61 | *(.glue_7t) /* glue thumb to arm code */
62 | *(.eh_frame)
63 |
64 | KEEP (*(.init))
65 | KEEP (*(.fini))
66 |
67 | . = ALIGN(4);
68 | _etext = .; /* define a global symbols at end of code */
69 | } >FLASH
70 |
71 | /* Constant data into "FLASH" Rom type memory */
72 | .rodata :
73 | {
74 | . = ALIGN(4);
75 | *(.rodata) /* .rodata sections (constants, strings, etc.) */
76 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
77 | . = ALIGN(4);
78 | } >FLASH
79 |
80 | .ARM.extab : {
81 | . = ALIGN(4);
82 | *(.ARM.extab* .gnu.linkonce.armextab.*)
83 | . = ALIGN(4);
84 | } >FLASH
85 |
86 | .ARM : {
87 | . = ALIGN(4);
88 | __exidx_start = .;
89 | *(.ARM.exidx*)
90 | __exidx_end = .;
91 | . = ALIGN(4);
92 | } >FLASH
93 |
94 | .preinit_array :
95 | {
96 | . = ALIGN(4);
97 | PROVIDE_HIDDEN (__preinit_array_start = .);
98 | KEEP (*(.preinit_array*))
99 | PROVIDE_HIDDEN (__preinit_array_end = .);
100 | . = ALIGN(4);
101 | } >FLASH
102 |
103 | .init_array :
104 | {
105 | . = ALIGN(4);
106 | PROVIDE_HIDDEN (__init_array_start = .);
107 | KEEP (*(SORT(.init_array.*)))
108 | KEEP (*(.init_array*))
109 | PROVIDE_HIDDEN (__init_array_end = .);
110 | . = ALIGN(4);
111 | } >FLASH
112 |
113 | .fini_array :
114 | {
115 | . = ALIGN(4);
116 | PROVIDE_HIDDEN (__fini_array_start = .);
117 | KEEP (*(SORT(.fini_array.*)))
118 | KEEP (*(.fini_array*))
119 | PROVIDE_HIDDEN (__fini_array_end = .);
120 | . = ALIGN(4);
121 | } >FLASH
122 |
123 | /* Used by the startup to initialize data */
124 | _sidata = LOADADDR(.data);
125 |
126 | /* Initialized data sections into "RAM" Ram type memory */
127 | .data :
128 | {
129 | . = ALIGN(4);
130 | _sdata = .; /* create a global symbol at data start */
131 | *(.data) /* .data sections */
132 | *(.data*) /* .data* sections */
133 | *(.RamFunc) /* .RamFunc sections */
134 | *(.RamFunc*) /* .RamFunc* sections */
135 |
136 | . = ALIGN(4);
137 | _edata = .; /* define a global symbol at data end */
138 |
139 | } >RAM AT> FLASH
140 |
141 | /* Uninitialized data section into "RAM" Ram type memory */
142 | . = ALIGN(4);
143 | .bss :
144 | {
145 | /* This is used by the startup in order to initialize the .bss section */
146 | _sbss = .; /* define a global symbol at bss start */
147 | __bss_start__ = _sbss;
148 | *(.bss)
149 | *(.bss*)
150 | *(COMMON)
151 |
152 | . = ALIGN(4);
153 | _ebss = .; /* define a global symbol at bss end */
154 | __bss_end__ = _ebss;
155 | } >RAM
156 |
157 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
158 | ._user_heap_stack :
159 | {
160 | . = ALIGN(8);
161 | PROVIDE ( end = . );
162 | PROVIDE ( _end = . );
163 | . = . + _Min_Heap_Size;
164 | . = . + _Min_Stack_Size;
165 | . = ALIGN(8);
166 | } >RAM
167 |
168 | /* Remove information from the compiler libraries */
169 | /DISCARD/ :
170 | {
171 | libc.a ( * )
172 | libm.a ( * )
173 | libgcc.a ( * )
174 | }
175 |
176 | .ARM.attributes 0 : { *(.ARM.attributes) }
177 | }
178 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/stm32f411_fw_nrf24l01p.ioc:
--------------------------------------------------------------------------------
1 | #MicroXplorer Configuration settings - do not modify
2 | Mcu.Family=STM32F4
3 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
4 | ProjectManager.MainLocation=Core/Src
5 | PC15-OSC32_OUT.Mode=LSE-External-Oscillator
6 | PB13.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
7 | ProjectManager.ProjectFileName=stm32f411_fw_nrf24l01p.ioc
8 | RCC.CortexFreq_Value=100000000
9 | ProjectManager.KeepUserCode=true
10 | Mcu.UserName=STM32F411CEUx
11 | Mcu.PinsNb=14
12 | SPI2.VirtualType=VM_MASTER
13 | PB10.Mode=Full_Duplex_Master
14 | ProjectManager.NoMain=false
15 | PC13-ANTI_TAMP.GPIO_Label=LED
16 | RCC.PLLCLKFreq_Value=100000000
17 | RCC.PLLQCLKFreq_Value=50000000
18 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_SPI2_Init-SPI2-false-HAL-true
19 | PH1\ -\ OSC_OUT.Mode=HSE-External-Oscillator
20 | RCC.RTCFreq_Value=32000
21 | ProjectManager.DefaultFWLocation=true
22 | ProjectManager.DeletePrevious=true
23 | RCC.APB1CLKDivider=RCC_HCLK_DIV2
24 | PC14-OSC32_IN.Signal=RCC_OSC32_IN
25 | PB13.GPIO_Label=SPI2_CSN
26 | PB13.Signal=GPIO_Output
27 | PB15.Signal=SPI2_MOSI
28 | PinOutPanel.RotationAngle=0
29 | RCC.FamilyName=M
30 | PC13-ANTI_TAMP.PinState=GPIO_PIN_SET
31 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
32 | ProjectManager.StackSize=0x400
33 | PA13.Signal=SYS_JTMS-SWDIO
34 | RCC.FCLKCortexFreq_Value=100000000
35 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
36 | Mcu.IP2=SPI2
37 | Mcu.IP3=SYS
38 | Mcu.IP0=NVIC
39 | Mcu.IP1=RCC
40 | PH0\ -\ OSC_IN.Mode=HSE-External-Oscillator
41 | PA8.GPIO_Label=IRQ
42 | Mcu.UserConstants=
43 | PH0\ -\ OSC_IN.Signal=RCC_OSC_IN
44 | ProjectManager.TargetToolchain=STM32CubeIDE
45 | Mcu.ThirdPartyNb=0
46 | RCC.HCLKFreq_Value=100000000
47 | Mcu.IPNb=4
48 | RCC.I2SClocksFreq_Value=150000000
49 | ProjectManager.PreviousToolchain=
50 | RCC.APB2TimFreq_Value=100000000
51 | RCC.VcooutputI2S=150000000
52 | PB13.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
53 | SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
54 | PA8.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
55 | RCC.VCOInputMFreq_Value=1562500
56 | Mcu.Pin6=PB12
57 | Mcu.Pin7=PB13
58 | ProjectManager.RegisterCallBack=
59 | Mcu.Pin8=PB14
60 | Mcu.Pin9=PB15
61 | PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
62 | RCC.AHBFreq_Value=100000000
63 | SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8
64 | PB12.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
65 | Mcu.Pin0=PC13-ANTI_TAMP
66 | Mcu.Pin1=PC14-OSC32_IN
67 | GPIO.groupedBy=Group By Peripherals
68 | Mcu.Pin2=PC15-OSC32_OUT
69 | PB10.Signal=SPI2_SCK
70 | Mcu.Pin3=PH0 - OSC_IN
71 | Mcu.Pin4=PH1 - OSC_OUT
72 | RCC.VCOI2SOutputFreq_Value=300000000
73 | PB14.Signal=SPI2_MISO
74 | Mcu.Pin5=PB10
75 | ProjectManager.ProjectBuild=false
76 | RCC.HSE_VALUE=25000000
77 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
78 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
79 | PH1\ -\ OSC_OUT.Signal=RCC_OSC_OUT
80 | board=custom
81 | PC13-ANTI_TAMP.Signal=GPIO_Output
82 | RCC.VCOOutputFreq_Value=200000000
83 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
84 | ProjectManager.LastFirmware=false
85 | PB15.Mode=Full_Duplex_Master
86 | PB12.GPIO_Label=CE
87 | ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.26.1
88 | MxDb.Version=DB.6.0.21
89 | RCC.APB2Freq_Value=100000000
90 | PB13.PinState=GPIO_PIN_SET
91 | ProjectManager.BackupPrevious=false
92 | MxCube.Version=6.2.1
93 | PC14-OSC32_IN.Mode=LSE-External-Oscillator
94 | RCC.VCOInputFreq_Value=2083333.3333333333
95 | PA14.Mode=Serial_Wire
96 | PB14.Mode=Full_Duplex_Master
97 | File.Version=6
98 | VP_SYS_VS_Systick.Mode=SysTick
99 | RCC.EthernetFreq_Value=100000000
100 | SPI2.CalculateBaudRate=6.25 MBits/s
101 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
102 | PA8.Signal=GPXTI8
103 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
104 | PA13.Mode=Serial_Wire
105 | ProjectManager.FreePins=false
106 | RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOInputMFreq_Value,VCOOutputFreq_Value,VcooutputI2S
107 | ProjectManager.AskForMigrate=true
108 | Mcu.Name=STM32F411C(C-E)Ux
109 | ProjectManager.HalAssertFull=false
110 | RCC.RTCHSEDivFreq_Value=12500000
111 | ProjectManager.ProjectName=stm32f411_fw_nrf24l01p
112 | ProjectManager.UnderRoot=true
113 | ProjectManager.CoupleFile=true
114 | RCC.48MHZClocksFreq_Value=50000000
115 | RCC.SYSCLKFreq_VALUE=100000000
116 | Mcu.Package=UFQFPN48
117 | SPI2.Mode=SPI_MODE_MASTER
118 | NVIC.ForceEnableDMAVector=true
119 | KeepUserPlacement=false
120 | PA8.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
121 | SH.GPXTI8.0=GPIO_EXTI8
122 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
123 | ProjectManager.CompilerOptimize=6
124 | ProjectManager.ToolChainLocation=
125 | RCC.LSI_VALUE=32000
126 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
127 | NVIC.EXTI9_5_IRQn=true\:0\:0\:false\:false\:true\:true\:true
128 | SH.GPXTI8.ConfNb=1
129 | PA14.Signal=SYS_JTCK-SWCLK
130 | ProjectManager.HeapSize=0x200
131 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
132 | Mcu.Pin13=VP_SYS_VS_Systick
133 | ProjectManager.ComputerToolchain=false
134 | RCC.HSI_VALUE=16000000
135 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
136 | Mcu.Pin11=PA13
137 | Mcu.Pin12=PA14
138 | RCC.PLLM=12
139 | RCC.PLLN=96
140 | Mcu.Pin10=PA8
141 | RCC.APB1TimFreq_Value=100000000
142 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
143 | SPI2.Direction=SPI_DIRECTION_2LINES
144 | RCC.APB1Freq_Value=50000000
145 | ProjectManager.CustomerFirmwarePackage=
146 | ProjectManager.DeviceId=STM32F411CEUx
147 | PB12.GPIOParameters=GPIO_Speed,GPIO_Label
148 | PB12.Signal=GPIO_Output
149 | ProjectManager.LibraryCopy=1
150 | PC13-ANTI_TAMP.GPIOParameters=PinState,GPIO_Label
151 | isbadioc=false
152 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Core/Src/stm32f4xx_it.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | #include "stm32f4xx_it.h"
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN PD */
35 |
36 | /* USER CODE END PD */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN PM */
40 |
41 | /* USER CODE END PM */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* Private user code ---------------------------------------------------------*/
54 | /* USER CODE BEGIN 0 */
55 |
56 | /* USER CODE END 0 */
57 |
58 | /* External variables --------------------------------------------------------*/
59 |
60 | /* USER CODE BEGIN EV */
61 |
62 | /* USER CODE END EV */
63 |
64 | /******************************************************************************/
65 | /* Cortex-M4 Processor Interruption and Exception Handlers */
66 | /******************************************************************************/
67 | /**
68 | * @brief This function handles Non maskable interrupt.
69 | */
70 | void NMI_Handler(void)
71 | {
72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73 |
74 | /* USER CODE END NonMaskableInt_IRQn 0 */
75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76 | while (1)
77 | {
78 | }
79 | /* USER CODE END NonMaskableInt_IRQn 1 */
80 | }
81 |
82 | /**
83 | * @brief This function handles Hard fault interrupt.
84 | */
85 | void HardFault_Handler(void)
86 | {
87 | /* USER CODE BEGIN HardFault_IRQn 0 */
88 |
89 | /* USER CODE END HardFault_IRQn 0 */
90 | while (1)
91 | {
92 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
93 | /* USER CODE END W1_HardFault_IRQn 0 */
94 | }
95 | }
96 |
97 | /**
98 | * @brief This function handles Memory management fault.
99 | */
100 | void MemManage_Handler(void)
101 | {
102 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */
103 |
104 | /* USER CODE END MemoryManagement_IRQn 0 */
105 | while (1)
106 | {
107 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
108 | /* USER CODE END W1_MemoryManagement_IRQn 0 */
109 | }
110 | }
111 |
112 | /**
113 | * @brief This function handles Pre-fetch fault, memory access fault.
114 | */
115 | void BusFault_Handler(void)
116 | {
117 | /* USER CODE BEGIN BusFault_IRQn 0 */
118 |
119 | /* USER CODE END BusFault_IRQn 0 */
120 | while (1)
121 | {
122 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */
123 | /* USER CODE END W1_BusFault_IRQn 0 */
124 | }
125 | }
126 |
127 | /**
128 | * @brief This function handles Undefined instruction or illegal state.
129 | */
130 | void UsageFault_Handler(void)
131 | {
132 | /* USER CODE BEGIN UsageFault_IRQn 0 */
133 |
134 | /* USER CODE END UsageFault_IRQn 0 */
135 | while (1)
136 | {
137 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
138 | /* USER CODE END W1_UsageFault_IRQn 0 */
139 | }
140 | }
141 |
142 | /**
143 | * @brief This function handles System service call via SWI instruction.
144 | */
145 | void SVC_Handler(void)
146 | {
147 | /* USER CODE BEGIN SVCall_IRQn 0 */
148 |
149 | /* USER CODE END SVCall_IRQn 0 */
150 | /* USER CODE BEGIN SVCall_IRQn 1 */
151 |
152 | /* USER CODE END SVCall_IRQn 1 */
153 | }
154 |
155 | /**
156 | * @brief This function handles Debug monitor.
157 | */
158 | void DebugMon_Handler(void)
159 | {
160 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */
161 |
162 | /* USER CODE END DebugMonitor_IRQn 0 */
163 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */
164 |
165 | /* USER CODE END DebugMonitor_IRQn 1 */
166 | }
167 |
168 | /**
169 | * @brief This function handles Pendable request for system service.
170 | */
171 | void PendSV_Handler(void)
172 | {
173 | /* USER CODE BEGIN PendSV_IRQn 0 */
174 |
175 | /* USER CODE END PendSV_IRQn 0 */
176 | /* USER CODE BEGIN PendSV_IRQn 1 */
177 |
178 | /* USER CODE END PendSV_IRQn 1 */
179 | }
180 |
181 | /**
182 | * @brief This function handles System tick timer.
183 | */
184 | void SysTick_Handler(void)
185 | {
186 | /* USER CODE BEGIN SysTick_IRQn 0 */
187 |
188 | /* USER CODE END SysTick_IRQn 0 */
189 | HAL_IncTick();
190 | /* USER CODE BEGIN SysTick_IRQn 1 */
191 |
192 | /* USER CODE END SysTick_IRQn 1 */
193 | }
194 |
195 | /******************************************************************************/
196 | /* STM32F4xx Peripheral Interrupt Handlers */
197 | /* Add here the Interrupt Handlers for the used peripherals. */
198 | /* For the available peripheral interrupt handler names, */
199 | /* please refer to the startup file (startup_stm32f4xx.s). */
200 | /******************************************************************************/
201 |
202 | /**
203 | * @brief This function handles EXTI line[9:5] interrupts.
204 | */
205 | void EXTI9_5_IRQHandler(void)
206 | {
207 | /* USER CODE BEGIN EXTI9_5_IRQn 0 */
208 |
209 | /* USER CODE END EXTI9_5_IRQn 0 */
210 | HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
211 | /* USER CODE BEGIN EXTI9_5_IRQn 1 */
212 |
213 | /* USER CODE END EXTI9_5_IRQn 1 */
214 | }
215 |
216 | /* USER CODE BEGIN 1 */
217 |
218 | /* USER CODE END 1 */
219 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
220 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Core/Src/main.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.c
5 | * @brief : Main program body
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "main.h"
22 | #include "spi.h"
23 | #include "gpio.h"
24 |
25 | /* Private includes ----------------------------------------------------------*/
26 | /* USER CODE BEGIN Includes */
27 |
28 | #include "nrf24l01p.h"
29 |
30 | /* USER CODE END Includes */
31 |
32 | /* Private typedef -----------------------------------------------------------*/
33 | /* USER CODE BEGIN PTD */
34 |
35 | /* USER CODE END PTD */
36 |
37 | /* Private define ------------------------------------------------------------*/
38 | /* USER CODE BEGIN PD */
39 |
40 | //#define TRANSMITTER
41 | #define RECEIVER
42 |
43 | /* USER CODE END PD */
44 |
45 | /* Private macro -------------------------------------------------------------*/
46 | /* USER CODE BEGIN PM */
47 |
48 | /* USER CODE END PM */
49 |
50 | /* Private variables ---------------------------------------------------------*/
51 |
52 | /* USER CODE BEGIN PV */
53 |
54 | uint8_t rx_data[NRF24L01P_PAYLOAD_LENGTH] = {0};
55 | uint8_t tx_data[NRF24L01P_PAYLOAD_LENGTH] = {0, 1, 2, 3, 4, 5, 6, 7};
56 |
57 | /* USER CODE END PV */
58 |
59 | /* Private function prototypes -----------------------------------------------*/
60 | void SystemClock_Config(void);
61 | /* USER CODE BEGIN PFP */
62 |
63 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
64 |
65 | /* USER CODE END PFP */
66 |
67 | /* Private user code ---------------------------------------------------------*/
68 | /* USER CODE BEGIN 0 */
69 |
70 | /* USER CODE END 0 */
71 |
72 | /**
73 | * @brief The application entry point.
74 | * @retval int
75 | */
76 | int main(void)
77 | {
78 | /* USER CODE BEGIN 1 */
79 |
80 | /* USER CODE END 1 */
81 |
82 | /* MCU Configuration--------------------------------------------------------*/
83 |
84 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
85 | HAL_Init();
86 |
87 | /* USER CODE BEGIN Init */
88 |
89 | /* USER CODE END Init */
90 |
91 | /* Configure the system clock */
92 | SystemClock_Config();
93 |
94 | /* USER CODE BEGIN SysInit */
95 |
96 | /* USER CODE END SysInit */
97 |
98 | /* Initialize all configured peripherals */
99 | MX_GPIO_Init();
100 | MX_SPI2_Init();
101 | /* USER CODE BEGIN 2 */
102 |
103 |
104 | #ifdef RECEIVER
105 | nrf24l01p_rx_init(2500, _1Mbps);
106 | #endif
107 |
108 | #ifdef TRANSMITTER
109 | nrf24l01p_tx_init(2500, _1Mbps);
110 | #endif
111 |
112 | /* USER CODE END 2 */
113 |
114 | /* Infinite loop */
115 | /* USER CODE BEGIN WHILE */
116 | while (1)
117 | {
118 | /* USER CODE END WHILE */
119 |
120 | /* USER CODE BEGIN 3 */
121 | #ifdef RECEIVER
122 | // Nothing to do
123 | #endif
124 |
125 | #ifdef TRANSMITTER
126 |
127 | for(int i= 0; i < 8; i++)
128 | {
129 | tx_data[i]++;
130 | }
131 |
132 |
133 | nrf24l01p_tx_transmit(tx_data);
134 | #endif
135 |
136 | HAL_Delay(100);
137 |
138 | }
139 | /* USER CODE END 3 */
140 | }
141 |
142 | /**
143 | * @brief System Clock Configuration
144 | * @retval None
145 | */
146 | void SystemClock_Config(void)
147 | {
148 | RCC_OscInitTypeDef RCC_OscInitStruct = {0};
149 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
150 |
151 | /** Configure the main internal regulator output voltage
152 | */
153 | __HAL_RCC_PWR_CLK_ENABLE();
154 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
155 | /** Initializes the RCC Oscillators according to the specified parameters
156 | * in the RCC_OscInitTypeDef structure.
157 | */
158 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
159 | RCC_OscInitStruct.HSEState = RCC_HSE_ON;
160 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
161 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
162 | RCC_OscInitStruct.PLL.PLLM = 12;
163 | RCC_OscInitStruct.PLL.PLLN = 96;
164 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
165 | RCC_OscInitStruct.PLL.PLLQ = 4;
166 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
167 | {
168 | Error_Handler();
169 | }
170 | /** Initializes the CPU, AHB and APB buses clocks
171 | */
172 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
173 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
174 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
175 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
176 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
177 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
178 |
179 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
180 | {
181 | Error_Handler();
182 | }
183 | }
184 |
185 | /* USER CODE BEGIN 4 */
186 |
187 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
188 | {
189 | if(GPIO_Pin == NRF24L01P_IRQ_PIN_NUMBER)
190 | {
191 | #ifdef RECEIVER
192 | nrf24l01p_rx_receive(rx_data);
193 | #endif
194 |
195 | #ifdef TRANSMITTER
196 | nrf24l01p_tx_irq();
197 | #endif
198 | }
199 |
200 | }
201 |
202 | /* USER CODE END 4 */
203 |
204 | /**
205 | * @brief This function is executed in case of error occurrence.
206 | * @retval None
207 | */
208 | void Error_Handler(void)
209 | {
210 | /* USER CODE BEGIN Error_Handler_Debug */
211 | /* User can add his own implementation to report the HAL error return state */
212 | __disable_irq();
213 | while (1)
214 | {
215 | }
216 | /* USER CODE END Error_Handler_Debug */
217 | }
218 |
219 | #ifdef USE_FULL_ASSERT
220 | /**
221 | * @brief Reports the name of the source file and the source line number
222 | * where the assert_param error has occurred.
223 | * @param file: pointer to the source file name
224 | * @param line: assert_param error line source number
225 | * @retval None
226 | */
227 | void assert_failed(uint8_t *file, uint32_t line)
228 | {
229 | /* USER CODE BEGIN 6 */
230 | /* User can add his own implementation to report the file name and line number,
231 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
232 | /* USER CODE END 6 */
233 | }
234 | #endif /* USE_FULL_ASSERT */
235 |
236 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
237 |
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/stm32f411_fw_nrf24l01p/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash_ramfunc.c
4 | * @author MCD Application Team
5 | * @brief FLASH RAMFUNC module driver.
6 | * This file provides a FLASH firmware functions which should be
7 | * executed from internal SRAM
8 | * + Stop/Start the flash interface while System Run
9 | * + Enable/Disable the flash sleep while System Run
10 | @verbatim
11 | ==============================================================================
12 | ##### APIs executed from Internal RAM #####
13 | ==============================================================================
14 | [..]
15 | *** ARM Compiler ***
16 | --------------------
17 | [..] RAM functions are defined using the toolchain options.
18 | Functions that are be executed in RAM should reside in a separate
19 | source module. Using the 'Options for File' dialog you can simply change
20 | the 'Code / Const' area of a module to a memory space in physical RAM.
21 | Available memory areas are declared in the 'Target' tab of the
22 | Options for Target' dialog.
23 |
24 | *** ICCARM Compiler ***
25 | -----------------------
26 | [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
27 |
28 | *** GNU Compiler ***
29 | --------------------
30 | [..] RAM functions are defined using a specific toolchain attribute
31 | "__attribute__((section(".RamFunc")))".
32 |
33 | @endverbatim
34 | ******************************************************************************
35 | * @attention
36 | *
37 | * © Copyright (c) 2017 STMicroelectronics.
38 | * All rights reserved.
39 | *
40 | * This software component is licensed by ST under BSD 3-Clause license,
41 | * the "License"; You may not use this file except in compliance with the
42 | * License. You may obtain a copy of the License at:
43 | * opensource.org/licenses/BSD-3-Clause
44 | *
45 | ******************************************************************************
46 | */
47 |
48 | /* Includes ------------------------------------------------------------------*/
49 | #include "stm32f4xx_hal.h"
50 |
51 | /** @addtogroup STM32F4xx_HAL_Driver
52 | * @{
53 | */
54 |
55 | /** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
56 | * @brief FLASH functions executed from RAM
57 | * @{
58 | */
59 | #ifdef HAL_FLASH_MODULE_ENABLED
60 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
61 | defined(STM32F412Rx) || defined(STM32F412Cx)
62 |
63 | /* Private typedef -----------------------------------------------------------*/
64 | /* Private define ------------------------------------------------------------*/
65 | /* Private macro -------------------------------------------------------------*/
66 | /* Private variables ---------------------------------------------------------*/
67 | /* Private function prototypes -----------------------------------------------*/
68 | /* Exported functions --------------------------------------------------------*/
69 | /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
70 | * @{
71 | */
72 |
73 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
74 | * @brief Peripheral Extended features functions
75 | *
76 | @verbatim
77 |
78 | ===============================================================================
79 | ##### ramfunc functions #####
80 | ===============================================================================
81 | [..]
82 | This subsection provides a set of functions that should be executed from RAM
83 | transfers.
84 |
85 | @endverbatim
86 | * @{
87 | */
88 |
89 | /**
90 | * @brief Stop the flash interface while System Run
91 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
92 | * @note This mode couldn't be set while executing with the flash itself.
93 | * It should be done with specific routine executed from RAM.
94 | * @retval HAL status
95 | */
96 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
97 | {
98 | /* Enable Power ctrl clock */
99 | __HAL_RCC_PWR_CLK_ENABLE();
100 | /* Stop the flash interface while System Run */
101 | SET_BIT(PWR->CR, PWR_CR_FISSR);
102 |
103 | return HAL_OK;
104 | }
105 |
106 | /**
107 | * @brief Start the flash interface while System Run
108 | * @note This mode is only available for STM32F411xx/STM32F446xx devices.
109 | * @note This mode couldn't be set while executing with the flash itself.
110 | * It should be done with specific routine executed from RAM.
111 | * @retval HAL status
112 | */
113 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
114 | {
115 | /* Enable Power ctrl clock */
116 | __HAL_RCC_PWR_CLK_ENABLE();
117 | /* Start the flash interface while System Run */
118 | CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
119 |
120 | return HAL_OK;
121 | }
122 |
123 | /**
124 | * @brief Enable the flash sleep while System Run
125 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
126 | * @note This mode could n't be set while executing with the flash itself.
127 | * It should be done with specific routine executed from RAM.
128 | * @retval HAL status
129 | */
130 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
131 | {
132 | /* Enable Power ctrl clock */
133 | __HAL_RCC_PWR_CLK_ENABLE();
134 | /* Enable the flash sleep while System Run */
135 | SET_BIT(PWR->CR, PWR_CR_FMSSR);
136 |
137 | return HAL_OK;
138 | }
139 |
140 | /**
141 | * @brief Disable the flash sleep while System Run
142 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
143 | * @note This mode couldn't be set while executing with the flash itself.
144 | * It should be done with specific routine executed from RAM.
145 | * @retval HAL status
146 | */
147 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
148 | {
149 | /* Enable Power ctrl clock */
150 | __HAL_RCC_PWR_CLK_ENABLE();
151 | /* Disable the flash sleep while System Run */
152 | CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
153 |
154 | return HAL_OK;
155 | }
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
166 | #endif /* HAL_FLASH_MODULE_ENABLED */
167 | /**
168 | * @}
169 | */
170 |
171 | /**
172 | * @}
173 | */
174 |
175 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
176 |
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/stm32f411_fw_nrf24l01p/.mxproject:
--------------------------------------------------------------------------------
1 | [PreviousLibFiles]
2 | LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
3 |
4 | [PreviousUsedCubeIDEFiles]
5 | SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\spi.c;Core\Src\stm32f4xx_it.c;Core\Src\stm32f4xx_hal_msp.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Core\Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Core\Src/system_stm32f4xx.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;;
6 | HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;Core\Inc;
7 | CDefines=USE_HAL_DRIVER;STM32F411xE;USE_HAL_DRIVER;USE_HAL_DRIVER;
8 |
9 | [PreviousGenFiles]
10 | AdvancedFolderStructure=true
11 | HeaderFileListSize=5
12 | HeaderFiles#0=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Inc/gpio.h
13 | HeaderFiles#1=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Inc/spi.h
14 | HeaderFiles#2=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Inc/stm32f4xx_it.h
15 | HeaderFiles#3=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Inc/stm32f4xx_hal_conf.h
16 | HeaderFiles#4=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Inc/main.h
17 | HeaderFolderListSize=1
18 | HeaderPath#0=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Inc
19 | HeaderFiles=;
20 | SourceFileListSize=5
21 | SourceFiles#0=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Src/gpio.c
22 | SourceFiles#1=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Src/spi.c
23 | SourceFiles#2=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Src/stm32f4xx_it.c
24 | SourceFiles#3=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Src/stm32f4xx_hal_msp.c
25 | SourceFiles#4=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Src/main.c
26 | SourceFolderListSize=1
27 | SourcePath#0=C:/Users/mokhw/Desktop/GitHub/stm32_hal_nrf24l01p/stm32f411_fw_nrf24l01p/Core/Src
28 | SourceFiles=;
29 |
30 |
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/stm32f411_fw_nrf24l01p/stm32f411_fw_receiver Debug.launch:
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/stm32f411_fw_nrf24l01p/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_def.h
4 | * @author MCD Application Team
5 | * @brief This file contains HAL common defines, enumeration, macros and
6 | * structures definitions.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_HAL_DEF
23 | #define __STM32F4xx_HAL_DEF
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f4xx.h"
31 | #include "Legacy/stm32_hal_legacy.h"
32 | #include
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 |
36 | /**
37 | * @brief HAL Status structures definition
38 | */
39 | typedef enum
40 | {
41 | HAL_OK = 0x00U,
42 | HAL_ERROR = 0x01U,
43 | HAL_BUSY = 0x02U,
44 | HAL_TIMEOUT = 0x03U
45 | } HAL_StatusTypeDef;
46 |
47 | /**
48 | * @brief HAL Lock structures definition
49 | */
50 | typedef enum
51 | {
52 | HAL_UNLOCKED = 0x00U,
53 | HAL_LOCKED = 0x01U
54 | } HAL_LockTypeDef;
55 |
56 | /* Exported macro ------------------------------------------------------------*/
57 |
58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
59 |
60 | #define HAL_MAX_DELAY 0xFFFFFFFFU
61 |
62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
64 |
65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
66 | do{ \
67 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
68 | (__DMA_HANDLE__).Parent = (__HANDLE__); \
69 | } while(0U)
70 |
71 | /** @brief Reset the Handle's State field.
72 | * @param __HANDLE__ specifies the Peripheral Handle.
73 | * @note This macro can be used for the following purpose:
74 | * - When the Handle is declared as local variable; before passing it as parameter
75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
76 | * to set to 0 the Handle's "State" field.
77 | * Otherwise, "State" field may have any random value and the first time the function
78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed
79 | * (i.e. HAL_PPP_MspInit() will not be executed).
80 | * - When there is a need to reconfigure the low level hardware: instead of calling
81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function
83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware.
84 | * @retval None
85 | */
86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
87 |
88 | #if (USE_RTOS == 1U)
89 | /* Reserved for future use */
90 | #error "USE_RTOS should be 0 in the current HAL release"
91 | #else
92 | #define __HAL_LOCK(__HANDLE__) \
93 | do{ \
94 | if((__HANDLE__)->Lock == HAL_LOCKED) \
95 | { \
96 | return HAL_BUSY; \
97 | } \
98 | else \
99 | { \
100 | (__HANDLE__)->Lock = HAL_LOCKED; \
101 | } \
102 | }while (0U)
103 |
104 | #define __HAL_UNLOCK(__HANDLE__) \
105 | do{ \
106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \
107 | }while (0U)
108 | #endif /* USE_RTOS */
109 |
110 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
111 | #ifndef __weak
112 | #define __weak __attribute__((weak))
113 | #endif
114 | #ifndef __packed
115 | #define __packed __attribute__((packed))
116 | #endif
117 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
118 | #ifndef __weak
119 | #define __weak __attribute__((weak))
120 | #endif /* __weak */
121 | #ifndef __packed
122 | #define __packed __attribute__((__packed__))
123 | #endif /* __packed */
124 | #endif /* __GNUC__ */
125 |
126 |
127 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
128 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
129 | #ifndef __ALIGN_BEGIN
130 | #define __ALIGN_BEGIN
131 | #endif
132 | #ifndef __ALIGN_END
133 | #define __ALIGN_END __attribute__ ((aligned (4)))
134 | #endif
135 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
136 | #ifndef __ALIGN_END
137 | #define __ALIGN_END __attribute__ ((aligned (4)))
138 | #endif /* __ALIGN_END */
139 | #ifndef __ALIGN_BEGIN
140 | #define __ALIGN_BEGIN
141 | #endif /* __ALIGN_BEGIN */
142 | #else
143 | #ifndef __ALIGN_END
144 | #define __ALIGN_END
145 | #endif /* __ALIGN_END */
146 | #ifndef __ALIGN_BEGIN
147 | #if defined (__CC_ARM) /* ARM Compiler V5*/
148 | #define __ALIGN_BEGIN __align(4)
149 | #elif defined (__ICCARM__) /* IAR Compiler */
150 | #define __ALIGN_BEGIN
151 | #endif /* __CC_ARM */
152 | #endif /* __ALIGN_BEGIN */
153 | #endif /* __GNUC__ */
154 |
155 |
156 | /**
157 | * @brief __RAM_FUNC definition
158 | */
159 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
160 | /* ARM Compiler V4/V5 and V6
161 | --------------------------
162 | RAM functions are defined using the toolchain options.
163 | Functions that are executed in RAM should reside in a separate source module.
164 | Using the 'Options for File' dialog you can simply change the 'Code / Const'
165 | area of a module to a memory space in physical RAM.
166 | Available memory areas are declared in the 'Target' tab of the 'Options for Target'
167 | dialog.
168 | */
169 | #define __RAM_FUNC
170 |
171 | #elif defined ( __ICCARM__ )
172 | /* ICCARM Compiler
173 | ---------------
174 | RAM functions are defined using a specific toolchain keyword "__ramfunc".
175 | */
176 | #define __RAM_FUNC __ramfunc
177 |
178 | #elif defined ( __GNUC__ )
179 | /* GNU Compiler
180 | ------------
181 | RAM functions are defined using a specific toolchain attribute
182 | "__attribute__((section(".RamFunc")))".
183 | */
184 | #define __RAM_FUNC __attribute__((section(".RamFunc")))
185 |
186 | #endif
187 |
188 | /**
189 | * @brief __NOINLINE definition
190 | */
191 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
192 | /* ARM V4/V5 and V6 & GNU Compiler
193 | -------------------------------
194 | */
195 | #define __NOINLINE __attribute__ ( (noinline) )
196 |
197 | #elif defined ( __ICCARM__ )
198 | /* ICCARM Compiler
199 | ---------------
200 | */
201 | #define __NOINLINE _Pragma("optimize = no_inline")
202 |
203 | #endif
204 |
205 | #ifdef __cplusplus
206 | }
207 | #endif
208 |
209 | #endif /* ___STM32F4xx_HAL_DEF */
210 |
211 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
212 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Drivers/CMSIS/Include/cmsis_compiler.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_compiler.h
3 | * @brief CMSIS compiler generic header file
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #ifndef __CMSIS_COMPILER_H
26 | #define __CMSIS_COMPILER_H
27 |
28 | #include
29 |
30 | /*
31 | * Arm Compiler 4/5
32 | */
33 | #if defined ( __CC_ARM )
34 | #include "cmsis_armcc.h"
35 |
36 |
37 | /*
38 | * Arm Compiler 6 (armclang)
39 | */
40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
41 | #include "cmsis_armclang.h"
42 |
43 |
44 | /*
45 | * GNU Compiler
46 | */
47 | #elif defined ( __GNUC__ )
48 | #include "cmsis_gcc.h"
49 |
50 |
51 | /*
52 | * IAR Compiler
53 | */
54 | #elif defined ( __ICCARM__ )
55 | #include
56 |
57 |
58 | /*
59 | * TI Arm Compiler
60 | */
61 | #elif defined ( __TI_ARM__ )
62 | #include
63 |
64 | #ifndef __ASM
65 | #define __ASM __asm
66 | #endif
67 | #ifndef __INLINE
68 | #define __INLINE inline
69 | #endif
70 | #ifndef __STATIC_INLINE
71 | #define __STATIC_INLINE static inline
72 | #endif
73 | #ifndef __STATIC_FORCEINLINE
74 | #define __STATIC_FORCEINLINE __STATIC_INLINE
75 | #endif
76 | #ifndef __NO_RETURN
77 | #define __NO_RETURN __attribute__((noreturn))
78 | #endif
79 | #ifndef __USED
80 | #define __USED __attribute__((used))
81 | #endif
82 | #ifndef __WEAK
83 | #define __WEAK __attribute__((weak))
84 | #endif
85 | #ifndef __PACKED
86 | #define __PACKED __attribute__((packed))
87 | #endif
88 | #ifndef __PACKED_STRUCT
89 | #define __PACKED_STRUCT struct __attribute__((packed))
90 | #endif
91 | #ifndef __PACKED_UNION
92 | #define __PACKED_UNION union __attribute__((packed))
93 | #endif
94 | #ifndef __UNALIGNED_UINT32 /* deprecated */
95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; };
96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
97 | #endif
98 | #ifndef __UNALIGNED_UINT16_WRITE
99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
101 | #endif
102 | #ifndef __UNALIGNED_UINT16_READ
103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
105 | #endif
106 | #ifndef __UNALIGNED_UINT32_WRITE
107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
109 | #endif
110 | #ifndef __UNALIGNED_UINT32_READ
111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
113 | #endif
114 | #ifndef __ALIGNED
115 | #define __ALIGNED(x) __attribute__((aligned(x)))
116 | #endif
117 | #ifndef __RESTRICT
118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
119 | #define __RESTRICT
120 | #endif
121 |
122 |
123 | /*
124 | * TASKING Compiler
125 | */
126 | #elif defined ( __TASKING__ )
127 | /*
128 | * The CMSIS functions have been implemented as intrinsics in the compiler.
129 | * Please use "carm -?i" to get an up to date list of all intrinsics,
130 | * Including the CMSIS ones.
131 | */
132 |
133 | #ifndef __ASM
134 | #define __ASM __asm
135 | #endif
136 | #ifndef __INLINE
137 | #define __INLINE inline
138 | #endif
139 | #ifndef __STATIC_INLINE
140 | #define __STATIC_INLINE static inline
141 | #endif
142 | #ifndef __STATIC_FORCEINLINE
143 | #define __STATIC_FORCEINLINE __STATIC_INLINE
144 | #endif
145 | #ifndef __NO_RETURN
146 | #define __NO_RETURN __attribute__((noreturn))
147 | #endif
148 | #ifndef __USED
149 | #define __USED __attribute__((used))
150 | #endif
151 | #ifndef __WEAK
152 | #define __WEAK __attribute__((weak))
153 | #endif
154 | #ifndef __PACKED
155 | #define __PACKED __packed__
156 | #endif
157 | #ifndef __PACKED_STRUCT
158 | #define __PACKED_STRUCT struct __packed__
159 | #endif
160 | #ifndef __PACKED_UNION
161 | #define __PACKED_UNION union __packed__
162 | #endif
163 | #ifndef __UNALIGNED_UINT32 /* deprecated */
164 | struct __packed__ T_UINT32 { uint32_t v; };
165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
166 | #endif
167 | #ifndef __UNALIGNED_UINT16_WRITE
168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
170 | #endif
171 | #ifndef __UNALIGNED_UINT16_READ
172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
174 | #endif
175 | #ifndef __UNALIGNED_UINT32_WRITE
176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
178 | #endif
179 | #ifndef __UNALIGNED_UINT32_READ
180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
182 | #endif
183 | #ifndef __ALIGNED
184 | #define __ALIGNED(x) __align(x)
185 | #endif
186 | #ifndef __RESTRICT
187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
188 | #define __RESTRICT
189 | #endif
190 |
191 |
192 | /*
193 | * COSMIC Compiler
194 | */
195 | #elif defined ( __CSMC__ )
196 | #include
197 |
198 | #ifndef __ASM
199 | #define __ASM _asm
200 | #endif
201 | #ifndef __INLINE
202 | #define __INLINE inline
203 | #endif
204 | #ifndef __STATIC_INLINE
205 | #define __STATIC_INLINE static inline
206 | #endif
207 | #ifndef __STATIC_FORCEINLINE
208 | #define __STATIC_FORCEINLINE __STATIC_INLINE
209 | #endif
210 | #ifndef __NO_RETURN
211 | // NO RETURN is automatically detected hence no warning here
212 | #define __NO_RETURN
213 | #endif
214 | #ifndef __USED
215 | #warning No compiler specific solution for __USED. __USED is ignored.
216 | #define __USED
217 | #endif
218 | #ifndef __WEAK
219 | #define __WEAK __weak
220 | #endif
221 | #ifndef __PACKED
222 | #define __PACKED @packed
223 | #endif
224 | #ifndef __PACKED_STRUCT
225 | #define __PACKED_STRUCT @packed struct
226 | #endif
227 | #ifndef __PACKED_UNION
228 | #define __PACKED_UNION @packed union
229 | #endif
230 | #ifndef __UNALIGNED_UINT32 /* deprecated */
231 | @packed struct T_UINT32 { uint32_t v; };
232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
233 | #endif
234 | #ifndef __UNALIGNED_UINT16_WRITE
235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
237 | #endif
238 | #ifndef __UNALIGNED_UINT16_READ
239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
241 | #endif
242 | #ifndef __UNALIGNED_UINT32_WRITE
243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
245 | #endif
246 | #ifndef __UNALIGNED_UINT32_READ
247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
249 | #endif
250 | #ifndef __ALIGNED
251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
252 | #define __ALIGNED(x)
253 | #endif
254 | #ifndef __RESTRICT
255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
256 | #define __RESTRICT
257 | #endif
258 |
259 |
260 | #else
261 | #error Unknown compiler.
262 | #endif
263 |
264 |
265 | #endif /* __CMSIS_COMPILER_H */
266 |
267 |
--------------------------------------------------------------------------------
/nrf24l01p.c:
--------------------------------------------------------------------------------
1 | /*
2 | * nrf24l01_plus.c
3 | *
4 | * Created on: 2021. 7. 20.
5 | * Author: mokhwasomssi
6 | *
7 | */
8 |
9 |
10 | #include "nrf24l01p.h"
11 |
12 |
13 | static void cs_high()
14 | {
15 | HAL_GPIO_WritePin(NRF24L01P_SPI_CS_PIN_PORT, NRF24L01P_SPI_CS_PIN_NUMBER, GPIO_PIN_SET);
16 | }
17 |
18 | static void cs_low()
19 | {
20 | HAL_GPIO_WritePin(NRF24L01P_SPI_CS_PIN_PORT, NRF24L01P_SPI_CS_PIN_NUMBER, GPIO_PIN_RESET);
21 | }
22 |
23 | static void ce_high()
24 | {
25 | HAL_GPIO_WritePin(NRF24L01P_CE_PIN_PORT, NRF24L01P_CE_PIN_NUMBER, GPIO_PIN_SET);
26 | }
27 |
28 | static void ce_low()
29 | {
30 | HAL_GPIO_WritePin(NRF24L01P_CE_PIN_PORT, NRF24L01P_CE_PIN_NUMBER, GPIO_PIN_RESET);
31 | }
32 |
33 | static uint8_t read_register(uint8_t reg)
34 | {
35 | uint8_t command = NRF24L01P_CMD_R_REGISTER | reg;
36 | uint8_t status;
37 | uint8_t read_val;
38 |
39 | cs_low();
40 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
41 | HAL_SPI_Receive(NRF24L01P_SPI, &read_val, 1, 2000);
42 | cs_high();
43 |
44 | return read_val;
45 | }
46 |
47 | static uint8_t write_register(uint8_t reg, uint8_t value)
48 | {
49 | uint8_t command = NRF24L01P_CMD_W_REGISTER | reg;
50 | uint8_t status;
51 | uint8_t write_val = value;
52 |
53 | cs_low();
54 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
55 | HAL_SPI_Transmit(NRF24L01P_SPI, &write_val, 1, 2000);
56 | cs_high();
57 |
58 | return write_val;
59 | }
60 |
61 |
62 | /* nRF24L01+ Main Functions */
63 | void nrf24l01p_rx_init(channel MHz, air_data_rate bps)
64 | {
65 | nrf24l01p_reset();
66 |
67 | nrf24l01p_prx_mode();
68 | nrf24l01p_power_up();
69 |
70 | nrf24l01p_rx_set_payload_widths(NRF24L01P_PAYLOAD_LENGTH);
71 |
72 | nrf24l01p_set_rf_channel(MHz);
73 | nrf24l01p_set_rf_air_data_rate(bps);
74 | nrf24l01p_set_rf_tx_output_power(_0dBm);
75 |
76 | nrf24l01p_set_crc_length(1);
77 | nrf24l01p_set_address_widths(5);
78 |
79 | nrf24l01p_auto_retransmit_count(3);
80 | nrf24l01p_auto_retransmit_delay(250);
81 |
82 | ce_high();
83 | }
84 |
85 | void nrf24l01p_tx_init(channel MHz, air_data_rate bps)
86 | {
87 | nrf24l01p_reset();
88 |
89 | nrf24l01p_ptx_mode();
90 | nrf24l01p_power_up();
91 |
92 | nrf24l01p_set_rf_channel(MHz);
93 | nrf24l01p_set_rf_air_data_rate(bps);
94 | nrf24l01p_set_rf_tx_output_power(_0dBm);
95 |
96 | nrf24l01p_set_crc_length(1);
97 | nrf24l01p_set_address_widths(5);
98 |
99 | nrf24l01p_auto_retransmit_count(3);
100 | nrf24l01p_auto_retransmit_delay(250);
101 |
102 | ce_high();
103 | }
104 |
105 | void nrf24l01p_rx_receive(uint8_t* rx_payload)
106 | {
107 | nrf24l01p_read_rx_fifo(rx_payload);
108 | nrf24l01p_clear_rx_dr();
109 |
110 | HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
111 | }
112 |
113 | void nrf24l01p_tx_transmit(uint8_t* tx_payload)
114 | {
115 | nrf24l01p_write_tx_fifo(tx_payload);
116 | }
117 |
118 | void nrf24l01p_tx_irq()
119 | {
120 | uint8_t tx_ds = nrf24l01p_get_status();
121 | tx_ds &= 0x20;
122 |
123 | if(tx_ds)
124 | {
125 | // TX_DS
126 | HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
127 | nrf24l01p_clear_tx_ds();
128 | }
129 |
130 | else
131 | {
132 | // MAX_RT
133 | HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, SET);
134 | nrf24l01p_clear_max_rt();
135 | }
136 | }
137 |
138 | /* nRF24L01+ Sub Functions */
139 | void nrf24l01p_reset()
140 | {
141 | // Reset pins
142 | cs_high();
143 | ce_low();
144 |
145 | // Reset registers
146 | write_register(NRF24L01P_REG_CONFIG, 0x08);
147 | write_register(NRF24L01P_REG_EN_AA, 0x3F);
148 | write_register(NRF24L01P_REG_EN_RXADDR, 0x03);
149 | write_register(NRF24L01P_REG_SETUP_AW, 0x03);
150 | write_register(NRF24L01P_REG_SETUP_RETR, 0x03);
151 | write_register(NRF24L01P_REG_RF_CH, 0x02);
152 | write_register(NRF24L01P_REG_RF_SETUP, 0x07);
153 | write_register(NRF24L01P_REG_STATUS, 0x7E);
154 | write_register(NRF24L01P_REG_RX_PW_P0, 0x00);
155 | write_register(NRF24L01P_REG_RX_PW_P0, 0x00);
156 | write_register(NRF24L01P_REG_RX_PW_P1, 0x00);
157 | write_register(NRF24L01P_REG_RX_PW_P2, 0x00);
158 | write_register(NRF24L01P_REG_RX_PW_P3, 0x00);
159 | write_register(NRF24L01P_REG_RX_PW_P4, 0x00);
160 | write_register(NRF24L01P_REG_RX_PW_P5, 0x00);
161 | write_register(NRF24L01P_REG_FIFO_STATUS, 0x11);
162 | write_register(NRF24L01P_REG_DYNPD, 0x00);
163 | write_register(NRF24L01P_REG_FEATURE, 0x00);
164 |
165 | // Reset FIFO
166 | nrf24l01p_flush_rx_fifo();
167 | nrf24l01p_flush_tx_fifo();
168 | }
169 |
170 | void nrf24l01p_prx_mode()
171 | {
172 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
173 | new_config |= 1 << 0;
174 |
175 | write_register(NRF24L01P_REG_CONFIG, new_config);
176 | }
177 |
178 | void nrf24l01p_ptx_mode()
179 | {
180 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
181 | new_config &= 0xFE;
182 |
183 | write_register(NRF24L01P_REG_CONFIG, new_config);
184 | }
185 |
186 | uint8_t nrf24l01p_read_rx_fifo(uint8_t* rx_payload)
187 | {
188 | uint8_t command = NRF24L01P_CMD_R_RX_PAYLOAD;
189 | uint8_t status;
190 |
191 | cs_low();
192 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
193 | HAL_SPI_Receive(NRF24L01P_SPI, rx_payload, NRF24L01P_PAYLOAD_LENGTH, 2000);
194 | cs_high();
195 |
196 | return status;
197 | }
198 |
199 | uint8_t nrf24l01p_write_tx_fifo(uint8_t* tx_payload)
200 | {
201 | uint8_t command = NRF24L01P_CMD_W_TX_PAYLOAD;
202 | uint8_t status;
203 |
204 | cs_low();
205 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
206 | HAL_SPI_Transmit(NRF24L01P_SPI, tx_payload, NRF24L01P_PAYLOAD_LENGTH, 2000);
207 | cs_high();
208 |
209 | return status;
210 | }
211 |
212 | void nrf24l01p_flush_rx_fifo()
213 | {
214 | uint8_t command = NRF24L01P_CMD_FLUSH_RX;
215 | uint8_t status;
216 |
217 | cs_low();
218 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
219 | cs_high();
220 | }
221 |
222 | void nrf24l01p_flush_tx_fifo()
223 | {
224 | uint8_t command = NRF24L01P_CMD_FLUSH_TX;
225 | uint8_t status;
226 |
227 | cs_low();
228 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
229 | cs_high();
230 | }
231 |
232 | uint8_t nrf24l01p_get_status()
233 | {
234 | uint8_t command = NRF24L01P_CMD_NOP;
235 | uint8_t status;
236 |
237 | cs_low();
238 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
239 | cs_high();
240 |
241 | return status;
242 | }
243 |
244 | uint8_t nrf24l01p_get_fifo_status()
245 | {
246 | return read_register(NRF24L01P_REG_FIFO_STATUS);
247 | }
248 |
249 | void nrf24l01p_rx_set_payload_widths(widths bytes)
250 | {
251 | write_register(NRF24L01P_REG_RX_PW_P0, bytes);
252 | }
253 |
254 | void nrf24l01p_clear_rx_dr()
255 | {
256 | uint8_t new_status = nrf24l01p_get_status();
257 | new_status |= 0x40;
258 |
259 | write_register(NRF24L01P_REG_STATUS, new_status);
260 | }
261 |
262 | void nrf24l01p_clear_tx_ds()
263 | {
264 | uint8_t new_status = nrf24l01p_get_status();
265 | new_status |= 0x20;
266 |
267 | write_register(NRF24L01P_REG_STATUS, new_status);
268 | }
269 |
270 | void nrf24l01p_clear_max_rt()
271 | {
272 | uint8_t new_status = nrf24l01p_get_status();
273 | new_status |= 0x10;
274 |
275 | write_register(NRF24L01P_REG_STATUS, new_status);
276 | }
277 |
278 | void nrf24l01p_power_up()
279 | {
280 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
281 | new_config |= 1 << 1;
282 |
283 | write_register(NRF24L01P_REG_CONFIG, new_config);
284 | }
285 |
286 | void nrf24l01p_power_down()
287 | {
288 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
289 | new_config &= 0xFD;
290 |
291 | write_register(NRF24L01P_REG_CONFIG, new_config);
292 | }
293 |
294 | void nrf24l01p_set_crc_length(length bytes)
295 | {
296 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
297 |
298 | switch(bytes)
299 | {
300 | // CRCO bit in CONFIG resiger set 0
301 | case 1:
302 | new_config &= 0xFB;
303 | break;
304 | // CRCO bit in CONFIG resiger set 1
305 | case 2:
306 | new_config |= 1 << 2;
307 | break;
308 | }
309 |
310 | write_register(NRF24L01P_REG_CONFIG, new_config);
311 | }
312 |
313 | void nrf24l01p_set_address_widths(widths bytes)
314 | {
315 | write_register(NRF24L01P_REG_SETUP_AW, bytes - 2);
316 | }
317 |
318 | void nrf24l01p_auto_retransmit_count(count cnt)
319 | {
320 | uint8_t new_setup_retr = read_register(NRF24L01P_REG_SETUP_RETR);
321 |
322 | // Reset ARC register 0
323 | new_setup_retr |= 0xF0;
324 | new_setup_retr |= cnt;
325 | write_register(NRF24L01P_REG_SETUP_RETR, new_setup_retr);
326 | }
327 |
328 | void nrf24l01p_auto_retransmit_delay(delay us)
329 | {
330 | uint8_t new_setup_retr = read_register(NRF24L01P_REG_SETUP_RETR);
331 |
332 | // Reset ARD register 0
333 | new_setup_retr |= 0x0F;
334 | new_setup_retr |= ((us / 250) - 1) << 4;
335 | write_register(NRF24L01P_REG_SETUP_RETR, new_setup_retr);
336 | }
337 |
338 | void nrf24l01p_set_rf_channel(channel MHz)
339 | {
340 | uint16_t new_rf_ch = MHz - 2400;
341 | write_register(NRF24L01P_REG_RF_CH, new_rf_ch);
342 | }
343 |
344 | void nrf24l01p_set_rf_tx_output_power(output_power dBm)
345 | {
346 | uint8_t new_rf_setup = read_register(NRF24L01P_REG_RF_SETUP) & 0xF9;
347 | new_rf_setup |= (dBm << 1);
348 |
349 | write_register(NRF24L01P_REG_RF_SETUP, new_rf_setup);
350 | }
351 |
352 | void nrf24l01p_set_rf_air_data_rate(air_data_rate bps)
353 | {
354 | // Set value to 0
355 | uint8_t new_rf_setup = read_register(NRF24L01P_REG_RF_SETUP) & 0xD7;
356 |
357 | switch(bps)
358 | {
359 | case _1Mbps:
360 | break;
361 | case _2Mbps:
362 | new_rf_setup |= 1 << 3;
363 | break;
364 | case _250kbps:
365 | new_rf_setup |= 1 << 5;
366 | break;
367 | }
368 | write_register(NRF24L01P_REG_RF_SETUP, new_rf_setup);
369 | }
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/nRF24L01p/nrf24l01p.c:
--------------------------------------------------------------------------------
1 | /*
2 | * nrf24l01_plus.c
3 | *
4 | * Created on: 2021. 7. 20.
5 | * Author: mokhwasomssi
6 | *
7 | */
8 |
9 |
10 | #include "nrf24l01p.h"
11 |
12 |
13 | static void cs_high()
14 | {
15 | HAL_GPIO_WritePin(NRF24L01P_SPI_CS_PIN_PORT, NRF24L01P_SPI_CS_PIN_NUMBER, GPIO_PIN_SET);
16 | }
17 |
18 | static void cs_low()
19 | {
20 | HAL_GPIO_WritePin(NRF24L01P_SPI_CS_PIN_PORT, NRF24L01P_SPI_CS_PIN_NUMBER, GPIO_PIN_RESET);
21 | }
22 |
23 | static void ce_high()
24 | {
25 | HAL_GPIO_WritePin(NRF24L01P_CE_PIN_PORT, NRF24L01P_CE_PIN_NUMBER, GPIO_PIN_SET);
26 | }
27 |
28 | static void ce_low()
29 | {
30 | HAL_GPIO_WritePin(NRF24L01P_CE_PIN_PORT, NRF24L01P_CE_PIN_NUMBER, GPIO_PIN_RESET);
31 | }
32 |
33 | static uint8_t read_register(uint8_t reg)
34 | {
35 | uint8_t command = NRF24L01P_CMD_R_REGISTER | reg;
36 | uint8_t status;
37 | uint8_t read_val;
38 |
39 | cs_low();
40 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
41 | HAL_SPI_Receive(NRF24L01P_SPI, &read_val, 1, 2000);
42 | cs_high();
43 |
44 | return read_val;
45 | }
46 |
47 | static uint8_t write_register(uint8_t reg, uint8_t value)
48 | {
49 | uint8_t command = NRF24L01P_CMD_W_REGISTER | reg;
50 | uint8_t status;
51 | uint8_t write_val = value;
52 |
53 | cs_low();
54 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
55 | HAL_SPI_Transmit(NRF24L01P_SPI, &write_val, 1, 2000);
56 | cs_high();
57 |
58 | return write_val;
59 | }
60 |
61 |
62 | /* nRF24L01+ Main Functions */
63 | void nrf24l01p_rx_init(channel MHz, air_data_rate bps)
64 | {
65 | nrf24l01p_reset();
66 |
67 | nrf24l01p_prx_mode();
68 | nrf24l01p_power_up();
69 |
70 | nrf24l01p_rx_set_payload_widths(NRF24L01P_PAYLOAD_LENGTH);
71 |
72 | nrf24l01p_set_rf_channel(MHz);
73 | nrf24l01p_set_rf_air_data_rate(bps);
74 | nrf24l01p_set_rf_tx_output_power(_0dBm);
75 |
76 | nrf24l01p_set_crc_length(1);
77 | nrf24l01p_set_address_widths(5);
78 |
79 | nrf24l01p_auto_retransmit_count(3);
80 | nrf24l01p_auto_retransmit_delay(250);
81 |
82 | ce_high();
83 | }
84 |
85 | void nrf24l01p_tx_init(channel MHz, air_data_rate bps)
86 | {
87 | nrf24l01p_reset();
88 |
89 | nrf24l01p_ptx_mode();
90 | nrf24l01p_power_up();
91 |
92 | nrf24l01p_set_rf_channel(MHz);
93 | nrf24l01p_set_rf_air_data_rate(bps);
94 | nrf24l01p_set_rf_tx_output_power(_0dBm);
95 |
96 | nrf24l01p_set_crc_length(1);
97 | nrf24l01p_set_address_widths(5);
98 |
99 | nrf24l01p_auto_retransmit_count(3);
100 | nrf24l01p_auto_retransmit_delay(250);
101 |
102 | ce_high();
103 | }
104 |
105 | void nrf24l01p_rx_receive(uint8_t* rx_payload)
106 | {
107 | nrf24l01p_read_rx_fifo(rx_payload);
108 | nrf24l01p_clear_rx_dr();
109 |
110 | HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
111 | }
112 |
113 | void nrf24l01p_tx_transmit(uint8_t* tx_payload)
114 | {
115 | nrf24l01p_write_tx_fifo(tx_payload);
116 | }
117 |
118 | void nrf24l01p_tx_irq()
119 | {
120 | uint8_t tx_ds = nrf24l01p_get_status();
121 | tx_ds &= 0x20;
122 |
123 | if(tx_ds)
124 | {
125 | // TX_DS
126 | HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
127 | nrf24l01p_clear_tx_ds();
128 | }
129 |
130 | else
131 | {
132 | // MAX_RT
133 | HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, SET);
134 | nrf24l01p_clear_max_rt();
135 | }
136 | }
137 |
138 | /* nRF24L01+ Sub Functions */
139 | void nrf24l01p_reset()
140 | {
141 | // Reset pins
142 | cs_high();
143 | ce_low();
144 |
145 | // Reset registers
146 | write_register(NRF24L01P_REG_CONFIG, 0x08);
147 | write_register(NRF24L01P_REG_EN_AA, 0x3F);
148 | write_register(NRF24L01P_REG_EN_RXADDR, 0x03);
149 | write_register(NRF24L01P_REG_SETUP_AW, 0x03);
150 | write_register(NRF24L01P_REG_SETUP_RETR, 0x03);
151 | write_register(NRF24L01P_REG_RF_CH, 0x02);
152 | write_register(NRF24L01P_REG_RF_SETUP, 0x07);
153 | write_register(NRF24L01P_REG_STATUS, 0x7E);
154 | write_register(NRF24L01P_REG_RX_PW_P0, 0x00);
155 | write_register(NRF24L01P_REG_RX_PW_P0, 0x00);
156 | write_register(NRF24L01P_REG_RX_PW_P1, 0x00);
157 | write_register(NRF24L01P_REG_RX_PW_P2, 0x00);
158 | write_register(NRF24L01P_REG_RX_PW_P3, 0x00);
159 | write_register(NRF24L01P_REG_RX_PW_P4, 0x00);
160 | write_register(NRF24L01P_REG_RX_PW_P5, 0x00);
161 | write_register(NRF24L01P_REG_FIFO_STATUS, 0x11);
162 | write_register(NRF24L01P_REG_DYNPD, 0x00);
163 | write_register(NRF24L01P_REG_FEATURE, 0x00);
164 |
165 | // Reset FIFO
166 | nrf24l01p_flush_rx_fifo();
167 | nrf24l01p_flush_tx_fifo();
168 | }
169 |
170 | void nrf24l01p_prx_mode()
171 | {
172 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
173 | new_config |= 1 << 0;
174 |
175 | write_register(NRF24L01P_REG_CONFIG, new_config);
176 | }
177 |
178 | void nrf24l01p_ptx_mode()
179 | {
180 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
181 | new_config &= 0xFE;
182 |
183 | write_register(NRF24L01P_REG_CONFIG, new_config);
184 | }
185 |
186 | uint8_t nrf24l01p_read_rx_fifo(uint8_t* rx_payload)
187 | {
188 | uint8_t command = NRF24L01P_CMD_R_RX_PAYLOAD;
189 | uint8_t status;
190 |
191 | cs_low();
192 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
193 | HAL_SPI_Receive(NRF24L01P_SPI, rx_payload, NRF24L01P_PAYLOAD_LENGTH, 2000);
194 | cs_high();
195 |
196 | return status;
197 | }
198 |
199 | uint8_t nrf24l01p_write_tx_fifo(uint8_t* tx_payload)
200 | {
201 | uint8_t command = NRF24L01P_CMD_W_TX_PAYLOAD;
202 | uint8_t status;
203 |
204 | cs_low();
205 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
206 | HAL_SPI_Transmit(NRF24L01P_SPI, tx_payload, NRF24L01P_PAYLOAD_LENGTH, 2000);
207 | cs_high();
208 |
209 | return status;
210 | }
211 |
212 | void nrf24l01p_flush_rx_fifo()
213 | {
214 | uint8_t command = NRF24L01P_CMD_FLUSH_RX;
215 | uint8_t status;
216 |
217 | cs_low();
218 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
219 | cs_high();
220 | }
221 |
222 | void nrf24l01p_flush_tx_fifo()
223 | {
224 | uint8_t command = NRF24L01P_CMD_FLUSH_TX;
225 | uint8_t status;
226 |
227 | cs_low();
228 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
229 | cs_high();
230 | }
231 |
232 | uint8_t nrf24l01p_get_status()
233 | {
234 | uint8_t command = NRF24L01P_CMD_NOP;
235 | uint8_t status;
236 |
237 | cs_low();
238 | HAL_SPI_TransmitReceive(NRF24L01P_SPI, &command, &status, 1, 2000);
239 | cs_high();
240 |
241 | return status;
242 | }
243 |
244 | uint8_t nrf24l01p_get_fifo_status()
245 | {
246 | return read_register(NRF24L01P_REG_FIFO_STATUS);
247 | }
248 |
249 | void nrf24l01p_rx_set_payload_widths(widths bytes)
250 | {
251 | write_register(NRF24L01P_REG_RX_PW_P0, bytes);
252 | }
253 |
254 | void nrf24l01p_clear_rx_dr()
255 | {
256 | uint8_t new_status = nrf24l01p_get_status();
257 | new_status |= 0x40;
258 |
259 | write_register(NRF24L01P_REG_STATUS, new_status);
260 | }
261 |
262 | void nrf24l01p_clear_tx_ds()
263 | {
264 | uint8_t new_status = nrf24l01p_get_status();
265 | new_status |= 0x20;
266 |
267 | write_register(NRF24L01P_REG_STATUS, new_status);
268 | }
269 |
270 | void nrf24l01p_clear_max_rt()
271 | {
272 | uint8_t new_status = nrf24l01p_get_status();
273 | new_status |= 0x10;
274 |
275 | write_register(NRF24L01P_REG_STATUS, new_status);
276 | }
277 |
278 | void nrf24l01p_power_up()
279 | {
280 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
281 | new_config |= 1 << 1;
282 |
283 | write_register(NRF24L01P_REG_CONFIG, new_config);
284 | }
285 |
286 | void nrf24l01p_power_down()
287 | {
288 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
289 | new_config &= 0xFD;
290 |
291 | write_register(NRF24L01P_REG_CONFIG, new_config);
292 | }
293 |
294 | void nrf24l01p_set_crc_length(length bytes)
295 | {
296 | uint8_t new_config = read_register(NRF24L01P_REG_CONFIG);
297 |
298 | switch(bytes)
299 | {
300 | // CRCO bit in CONFIG resiger set 0
301 | case 1:
302 | new_config &= 0xFB;
303 | break;
304 | // CRCO bit in CONFIG resiger set 1
305 | case 2:
306 | new_config |= 1 << 2;
307 | break;
308 | }
309 |
310 | write_register(NRF24L01P_REG_CONFIG, new_config);
311 | }
312 |
313 | void nrf24l01p_set_address_widths(widths bytes)
314 | {
315 | write_register(NRF24L01P_REG_SETUP_AW, bytes - 2);
316 | }
317 |
318 | void nrf24l01p_auto_retransmit_count(count cnt)
319 | {
320 | uint8_t new_setup_retr = read_register(NRF24L01P_REG_SETUP_RETR);
321 |
322 | // Reset ARC register 0
323 | new_setup_retr |= 0xF0;
324 | new_setup_retr |= cnt;
325 | write_register(NRF24L01P_REG_SETUP_RETR, new_setup_retr);
326 | }
327 |
328 | void nrf24l01p_auto_retransmit_delay(delay us)
329 | {
330 | uint8_t new_setup_retr = read_register(NRF24L01P_REG_SETUP_RETR);
331 |
332 | // Reset ARD register 0
333 | new_setup_retr |= 0x0F;
334 | new_setup_retr |= ((us / 250) - 1) << 4;
335 | write_register(NRF24L01P_REG_SETUP_RETR, new_setup_retr);
336 | }
337 |
338 | void nrf24l01p_set_rf_channel(channel MHz)
339 | {
340 | uint16_t new_rf_ch = MHz - 2400;
341 | write_register(NRF24L01P_REG_RF_CH, new_rf_ch);
342 | }
343 |
344 | void nrf24l01p_set_rf_tx_output_power(output_power dBm)
345 | {
346 | uint8_t new_rf_setup = read_register(NRF24L01P_REG_RF_SETUP) & 0xF9;
347 | new_rf_setup |= (dBm << 1);
348 |
349 | write_register(NRF24L01P_REG_RF_SETUP, new_rf_setup);
350 | }
351 |
352 | void nrf24l01p_set_rf_air_data_rate(air_data_rate bps)
353 | {
354 | // Set value to 0
355 | uint8_t new_rf_setup = read_register(NRF24L01P_REG_RF_SETUP) & 0xD7;
356 |
357 | switch(bps)
358 | {
359 | case _1Mbps:
360 | break;
361 | case _2Mbps:
362 | new_rf_setup |= 1 << 3;
363 | break;
364 | case _250kbps:
365 | new_rf_setup |= 1 << 5;
366 | break;
367 | }
368 | write_register(NRF24L01P_REG_RF_SETUP, new_rf_setup);
369 | }
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_dma_ex.c
4 | * @author MCD Application Team
5 | * @brief DMA Extension HAL module driver
6 | * This file provides firmware functions to manage the following
7 | * functionalities of the DMA Extension peripheral:
8 | * + Extended features functions
9 | *
10 | @verbatim
11 | ==============================================================================
12 | ##### How to use this driver #####
13 | ==============================================================================
14 | [..]
15 | The DMA Extension HAL driver can be used as follows:
16 | (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
17 | for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
18 |
19 | -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
20 | -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
21 | -@- In Multi (Double) buffer mode, it is possible to update the base address for
22 | the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
23 |
24 | @endverbatim
25 | ******************************************************************************
26 | * @attention
27 | *
28 | * © Copyright (c) 2017 STMicroelectronics.
29 | * All rights reserved.
30 | *
31 | * This software component is licensed by ST under BSD 3-Clause license,
32 | * the "License"; You may not use this file except in compliance with the
33 | * License. You may obtain a copy of the License at:
34 | * opensource.org/licenses/BSD-3-Clause
35 | *
36 | ******************************************************************************
37 | */
38 |
39 | /* Includes ------------------------------------------------------------------*/
40 | #include "stm32f4xx_hal.h"
41 |
42 | /** @addtogroup STM32F4xx_HAL_Driver
43 | * @{
44 | */
45 |
46 | /** @defgroup DMAEx DMAEx
47 | * @brief DMA Extended HAL module driver
48 | * @{
49 | */
50 |
51 | #ifdef HAL_DMA_MODULE_ENABLED
52 |
53 | /* Private types -------------------------------------------------------------*/
54 | /* Private variables ---------------------------------------------------------*/
55 | /* Private Constants ---------------------------------------------------------*/
56 | /* Private macros ------------------------------------------------------------*/
57 | /* Private functions ---------------------------------------------------------*/
58 | /** @addtogroup DMAEx_Private_Functions
59 | * @{
60 | */
61 | static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
62 | /**
63 | * @}
64 | */
65 |
66 | /* Exported functions ---------------------------------------------------------*/
67 |
68 | /** @addtogroup DMAEx_Exported_Functions
69 | * @{
70 | */
71 |
72 |
73 | /** @addtogroup DMAEx_Exported_Functions_Group1
74 | *
75 | @verbatim
76 | ===============================================================================
77 | ##### Extended features functions #####
78 | ===============================================================================
79 | [..] This section provides functions allowing to:
80 | (+) Configure the source, destination address and data length and
81 | Start MultiBuffer DMA transfer
82 | (+) Configure the source, destination address and data length and
83 | Start MultiBuffer DMA transfer with interrupt
84 | (+) Change on the fly the memory0 or memory1 address.
85 |
86 | @endverbatim
87 | * @{
88 | */
89 |
90 |
91 | /**
92 | * @brief Starts the multi_buffer DMA Transfer.
93 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
94 | * the configuration information for the specified DMA Stream.
95 | * @param SrcAddress The source memory Buffer address
96 | * @param DstAddress The destination memory Buffer address
97 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
98 | * @param DataLength The length of data to be transferred from source to destination
99 | * @retval HAL status
100 | */
101 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
102 | {
103 | HAL_StatusTypeDef status = HAL_OK;
104 |
105 | /* Check the parameters */
106 | assert_param(IS_DMA_BUFFER_SIZE(DataLength));
107 |
108 | /* Memory-to-memory transfer not supported in double buffering mode */
109 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
110 | {
111 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
112 | status = HAL_ERROR;
113 | }
114 | else
115 | {
116 | /* Process Locked */
117 | __HAL_LOCK(hdma);
118 |
119 | if(HAL_DMA_STATE_READY == hdma->State)
120 | {
121 | /* Change DMA peripheral state */
122 | hdma->State = HAL_DMA_STATE_BUSY;
123 |
124 | /* Enable the double buffer mode */
125 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
126 |
127 | /* Configure DMA Stream destination address */
128 | hdma->Instance->M1AR = SecondMemAddress;
129 |
130 | /* Configure the source, destination address and the data length */
131 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
132 |
133 | /* Enable the peripheral */
134 | __HAL_DMA_ENABLE(hdma);
135 | }
136 | else
137 | {
138 | /* Return error status */
139 | status = HAL_BUSY;
140 | }
141 | }
142 | return status;
143 | }
144 |
145 | /**
146 | * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
147 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
148 | * the configuration information for the specified DMA Stream.
149 | * @param SrcAddress The source memory Buffer address
150 | * @param DstAddress The destination memory Buffer address
151 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
152 | * @param DataLength The length of data to be transferred from source to destination
153 | * @retval HAL status
154 | */
155 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
156 | {
157 | HAL_StatusTypeDef status = HAL_OK;
158 |
159 | /* Check the parameters */
160 | assert_param(IS_DMA_BUFFER_SIZE(DataLength));
161 |
162 | /* Memory-to-memory transfer not supported in double buffering mode */
163 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
164 | {
165 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
166 | return HAL_ERROR;
167 | }
168 |
169 | /* Check callback functions */
170 | if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
171 | {
172 | hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
173 | return HAL_ERROR;
174 | }
175 |
176 | /* Process locked */
177 | __HAL_LOCK(hdma);
178 |
179 | if(HAL_DMA_STATE_READY == hdma->State)
180 | {
181 | /* Change DMA peripheral state */
182 | hdma->State = HAL_DMA_STATE_BUSY;
183 |
184 | /* Initialize the error code */
185 | hdma->ErrorCode = HAL_DMA_ERROR_NONE;
186 |
187 | /* Enable the Double buffer mode */
188 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
189 |
190 | /* Configure DMA Stream destination address */
191 | hdma->Instance->M1AR = SecondMemAddress;
192 |
193 | /* Configure the source, destination address and the data length */
194 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
195 |
196 | /* Clear all flags */
197 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
198 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
199 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
200 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
201 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
202 |
203 | /* Enable Common interrupts*/
204 | hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
205 | hdma->Instance->FCR |= DMA_IT_FE;
206 |
207 | if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
208 | {
209 | hdma->Instance->CR |= DMA_IT_HT;
210 | }
211 |
212 | /* Enable the peripheral */
213 | __HAL_DMA_ENABLE(hdma);
214 | }
215 | else
216 | {
217 | /* Process unlocked */
218 | __HAL_UNLOCK(hdma);
219 |
220 | /* Return error status */
221 | status = HAL_BUSY;
222 | }
223 | return status;
224 | }
225 |
226 | /**
227 | * @brief Change the memory0 or memory1 address on the fly.
228 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
229 | * the configuration information for the specified DMA Stream.
230 | * @param Address The new address
231 | * @param memory the memory to be changed, This parameter can be one of
232 | * the following values:
233 | * MEMORY0 /
234 | * MEMORY1
235 | * @note The MEMORY0 address can be changed only when the current transfer use
236 | * MEMORY1 and the MEMORY1 address can be changed only when the current
237 | * transfer use MEMORY0.
238 | * @retval HAL status
239 | */
240 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
241 | {
242 | if(memory == MEMORY0)
243 | {
244 | /* change the memory0 address */
245 | hdma->Instance->M0AR = Address;
246 | }
247 | else
248 | {
249 | /* change the memory1 address */
250 | hdma->Instance->M1AR = Address;
251 | }
252 |
253 | return HAL_OK;
254 | }
255 |
256 | /**
257 | * @}
258 | */
259 |
260 | /**
261 | * @}
262 | */
263 |
264 | /** @addtogroup DMAEx_Private_Functions
265 | * @{
266 | */
267 |
268 | /**
269 | * @brief Set the DMA Transfer parameter.
270 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
271 | * the configuration information for the specified DMA Stream.
272 | * @param SrcAddress The source memory Buffer address
273 | * @param DstAddress The destination memory Buffer address
274 | * @param DataLength The length of data to be transferred from source to destination
275 | * @retval HAL status
276 | */
277 | static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
278 | {
279 | /* Configure DMA Stream data length */
280 | hdma->Instance->NDTR = DataLength;
281 |
282 | /* Peripheral to Memory */
283 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
284 | {
285 | /* Configure DMA Stream destination address */
286 | hdma->Instance->PAR = DstAddress;
287 |
288 | /* Configure DMA Stream source address */
289 | hdma->Instance->M0AR = SrcAddress;
290 | }
291 | /* Memory to Peripheral */
292 | else
293 | {
294 | /* Configure DMA Stream source address */
295 | hdma->Instance->PAR = SrcAddress;
296 |
297 | /* Configure DMA Stream destination address */
298 | hdma->Instance->M0AR = DstAddress;
299 | }
300 | }
301 |
302 | /**
303 | * @}
304 | */
305 |
306 | #endif /* HAL_DMA_MODULE_ENABLED */
307 | /**
308 | * @}
309 | */
310 |
311 | /**
312 | * @}
313 | */
314 |
315 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
316 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Drivers/CMSIS/Include/mpu_armv8.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv8.h
3 | * @brief CMSIS MPU API for Armv8-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV8_H
32 | #define ARM_MPU_ARMV8_H
33 |
34 | /** \brief Attribute for device memory (outer only) */
35 | #define ARM_MPU_ATTR_DEVICE ( 0U )
36 |
37 | /** \brief Attribute for non-cacheable, normal memory */
38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39 |
40 | /** \brief Attribute for normal memory (outer and inner)
41 | * \param NT Non-Transient: Set to 1 for non-transient data.
42 | * \param WB Write-Back: Set to 1 to use write-back update policy.
43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
45 | */
46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
48 |
49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51 |
52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54 |
55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57 |
58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60 |
61 | /** \brief Memory Attribute
62 | * \param O Outer memory attributes
63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
64 | */
65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
66 |
67 | /** \brief Normal memory non-shareable */
68 | #define ARM_MPU_SH_NON (0U)
69 |
70 | /** \brief Normal memory outer shareable */
71 | #define ARM_MPU_SH_OUTER (2U)
72 |
73 | /** \brief Normal memory inner shareable */
74 | #define ARM_MPU_SH_INNER (3U)
75 |
76 | /** \brief Memory access permissions
77 | * \param RO Read-Only: Set to 1 for read-only memory.
78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory.
79 | */
80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
81 |
82 | /** \brief Region Base Address Register value
83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
84 | * \param SH Defines the Shareability domain for this memory region.
85 | * \param RO Read-Only: Set to 1 for a read-only memory region.
86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
88 | */
89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90 | ((BASE & MPU_RBAR_BASE_Msk) | \
91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94 |
95 | /** \brief Region Limit Address Register value
96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
97 | * \param IDX The attribute index to be associated with this memory region.
98 | */
99 | #define ARM_MPU_RLAR(LIMIT, IDX) \
100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102 | (MPU_RLAR_EN_Msk))
103 |
104 | /**
105 | * Struct for a single MPU Region
106 | */
107 | typedef struct {
108 | uint32_t RBAR; /*!< Region Base Address Register value */
109 | uint32_t RLAR; /*!< Region Limit Address Register value */
110 | } ARM_MPU_Region_t;
111 |
112 | /** Enable the MPU.
113 | * \param MPU_Control Default access permissions for unconfigured regions.
114 | */
115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
116 | {
117 | __DSB();
118 | __ISB();
119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
122 | #endif
123 | }
124 |
125 | /** Disable the MPU.
126 | */
127 | __STATIC_INLINE void ARM_MPU_Disable(void)
128 | {
129 | __DSB();
130 | __ISB();
131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
133 | #endif
134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
135 | }
136 |
137 | #ifdef MPU_NS
138 | /** Enable the Non-secure MPU.
139 | * \param MPU_Control Default access permissions for unconfigured regions.
140 | */
141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
142 | {
143 | __DSB();
144 | __ISB();
145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
148 | #endif
149 | }
150 |
151 | /** Disable the Non-secure MPU.
152 | */
153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void)
154 | {
155 | __DSB();
156 | __ISB();
157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
159 | #endif
160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
161 | }
162 | #endif
163 |
164 | /** Set the memory attribute encoding to the given MPU.
165 | * \param mpu Pointer to the MPU to be configured.
166 | * \param idx The attribute index to be set [0-7]
167 | * \param attr The attribute value to be set.
168 | */
169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
170 | {
171 | const uint8_t reg = idx / 4U;
172 | const uint32_t pos = ((idx % 4U) * 8U);
173 | const uint32_t mask = 0xFFU << pos;
174 |
175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
176 | return; // invalid index
177 | }
178 |
179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
180 | }
181 |
182 | /** Set the memory attribute encoding.
183 | * \param idx The attribute index to be set [0-7]
184 | * \param attr The attribute value to be set.
185 | */
186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
187 | {
188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr);
189 | }
190 |
191 | #ifdef MPU_NS
192 | /** Set the memory attribute encoding to the Non-secure MPU.
193 | * \param idx The attribute index to be set [0-7]
194 | * \param attr The attribute value to be set.
195 | */
196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
197 | {
198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
199 | }
200 | #endif
201 |
202 | /** Clear and disable the given MPU region of the given MPU.
203 | * \param mpu Pointer to MPU to be used.
204 | * \param rnr Region number to be cleared.
205 | */
206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
207 | {
208 | mpu->RNR = rnr;
209 | mpu->RLAR = 0U;
210 | }
211 |
212 | /** Clear and disable the given MPU region.
213 | * \param rnr Region number to be cleared.
214 | */
215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
216 | {
217 | ARM_MPU_ClrRegionEx(MPU, rnr);
218 | }
219 |
220 | #ifdef MPU_NS
221 | /** Clear and disable the given Non-secure MPU region.
222 | * \param rnr Region number to be cleared.
223 | */
224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
225 | {
226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr);
227 | }
228 | #endif
229 |
230 | /** Configure the given MPU region of the given MPU.
231 | * \param mpu Pointer to MPU to be used.
232 | * \param rnr Region number to be configured.
233 | * \param rbar Value for RBAR register.
234 | * \param rlar Value for RLAR register.
235 | */
236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
237 | {
238 | mpu->RNR = rnr;
239 | mpu->RBAR = rbar;
240 | mpu->RLAR = rlar;
241 | }
242 |
243 | /** Configure the given MPU region.
244 | * \param rnr Region number to be configured.
245 | * \param rbar Value for RBAR register.
246 | * \param rlar Value for RLAR register.
247 | */
248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
249 | {
250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
251 | }
252 |
253 | #ifdef MPU_NS
254 | /** Configure the given Non-secure MPU region.
255 | * \param rnr Region number to be configured.
256 | * \param rbar Value for RBAR register.
257 | * \param rlar Value for RLAR register.
258 | */
259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
260 | {
261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
262 | }
263 | #endif
264 |
265 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
266 | * \param dst Destination data is copied to.
267 | * \param src Source data is copied from.
268 | * \param len Amount of data words to be copied.
269 | */
270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
271 | {
272 | uint32_t i;
273 | for (i = 0U; i < len; ++i)
274 | {
275 | dst[i] = src[i];
276 | }
277 | }
278 |
279 | /** Load the given number of MPU regions from a table to the given MPU.
280 | * \param mpu Pointer to the MPU registers to be used.
281 | * \param rnr First region number to be configured.
282 | * \param table Pointer to the MPU configuration table.
283 | * \param cnt Amount of regions to be configured.
284 | */
285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
286 | {
287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
288 | if (cnt == 1U) {
289 | mpu->RNR = rnr;
290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
291 | } else {
292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
294 |
295 | mpu->RNR = rnrBase;
296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
299 | table += c;
300 | cnt -= c;
301 | rnrOffset = 0U;
302 | rnrBase += MPU_TYPE_RALIASES;
303 | mpu->RNR = rnrBase;
304 | }
305 |
306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
307 | }
308 | }
309 |
310 | /** Load the given number of MPU regions from a table.
311 | * \param rnr First region number to be configured.
312 | * \param table Pointer to the MPU configuration table.
313 | * \param cnt Amount of regions to be configured.
314 | */
315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
316 | {
317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt);
318 | }
319 |
320 | #ifdef MPU_NS
321 | /** Load the given number of MPU regions from a table to the Non-secure MPU.
322 | * \param rnr First region number to be configured.
323 | * \param table Pointer to the MPU configuration table.
324 | * \param cnt Amount of regions to be configured.
325 | */
326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
327 | {
328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
329 | }
330 | #endif
331 |
332 | #endif
333 |
334 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Drivers/CMSIS/Include/mpu_armv7.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv7.h
3 | * @brief CMSIS MPU API for Armv7-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV7_H
32 | #define ARM_MPU_ARMV7_H
33 |
34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62 |
63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69 |
70 | /** MPU Region Base Address Register Value
71 | *
72 | * \param Region The region to be configured, number 0 to 15.
73 | * \param BaseAddress The base address for the region.
74 | */
75 | #define ARM_MPU_RBAR(Region, BaseAddress) \
76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 | ((Region) & MPU_RBAR_REGION_Msk) | \
78 | (MPU_RBAR_VALID_Msk))
79 |
80 | /**
81 | * MPU Memory Access Attributes
82 | *
83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 | * \param IsShareable Region is shareable between multiple bus masters.
85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 | */
88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93 |
94 | /**
95 | * MPU Region Attribute and Size Register Value
96 | *
97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 | * \param SubRegionDisable Sub-region disable field.
101 | * \param Size Region size of the region to be configured, for example 4K, 8K.
102 | */
103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107 |
108 | /**
109 | * MPU Region Attribute and Size Register Value
110 | *
111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
114 | * \param IsShareable Region is shareable between multiple bus masters.
115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
117 | * \param SubRegionDisable Sub-region disable field.
118 | * \param Size Region size of the region to be configured, for example 4K, 8K.
119 | */
120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122 |
123 | /**
124 | * MPU Memory Access Attribute for strongly ordered memory.
125 | * - TEX: 000b
126 | * - Shareable
127 | * - Non-cacheable
128 | * - Non-bufferable
129 | */
130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131 |
132 | /**
133 | * MPU Memory Access Attribute for device memory.
134 | * - TEX: 000b (if non-shareable) or 010b (if shareable)
135 | * - Shareable or non-shareable
136 | * - Non-cacheable
137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable)
138 | *
139 | * \param IsShareable Configures the device memory as shareable or non-shareable.
140 | */
141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142 |
143 | /**
144 | * MPU Memory Access Attribute for normal memory.
145 | * - TEX: 1BBb (reflecting outer cacheability rules)
146 | * - Shareable or non-shareable
147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules)
148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules)
149 | *
150 | * \param OuterCp Configures the outer cache policy.
151 | * \param InnerCp Configures the inner cache policy.
152 | * \param IsShareable Configures the memory as shareable or non-shareable.
153 | */
154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155 |
156 | /**
157 | * MPU Memory Access Attribute non-cacheable policy.
158 | */
159 | #define ARM_MPU_CACHEP_NOCACHE 0U
160 |
161 | /**
162 | * MPU Memory Access Attribute write-back, write and read allocate policy.
163 | */
164 | #define ARM_MPU_CACHEP_WB_WRA 1U
165 |
166 | /**
167 | * MPU Memory Access Attribute write-through, no write allocate policy.
168 | */
169 | #define ARM_MPU_CACHEP_WT_NWA 2U
170 |
171 | /**
172 | * MPU Memory Access Attribute write-back, no write allocate policy.
173 | */
174 | #define ARM_MPU_CACHEP_WB_NWA 3U
175 |
176 |
177 | /**
178 | * Struct for a single MPU Region
179 | */
180 | typedef struct {
181 | uint32_t RBAR; //!< The region base address register value (RBAR)
182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
183 | } ARM_MPU_Region_t;
184 |
185 | /** Enable the MPU.
186 | * \param MPU_Control Default access permissions for unconfigured regions.
187 | */
188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 | {
190 | __DSB();
191 | __ISB();
192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 | #endif
196 | }
197 |
198 | /** Disable the MPU.
199 | */
200 | __STATIC_INLINE void ARM_MPU_Disable(void)
201 | {
202 | __DSB();
203 | __ISB();
204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 | #endif
207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 | }
209 |
210 | /** Clear and disable the given MPU region.
211 | * \param rnr Region number to be cleared.
212 | */
213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
214 | {
215 | MPU->RNR = rnr;
216 | MPU->RASR = 0U;
217 | }
218 |
219 | /** Configure an MPU region.
220 | * \param rbar Value for RBAR register.
221 | * \param rsar Value for RSAR register.
222 | */
223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 | {
225 | MPU->RBAR = rbar;
226 | MPU->RASR = rasr;
227 | }
228 |
229 | /** Configure the given MPU region.
230 | * \param rnr Region number to be configured.
231 | * \param rbar Value for RBAR register.
232 | * \param rsar Value for RSAR register.
233 | */
234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 | {
236 | MPU->RNR = rnr;
237 | MPU->RBAR = rbar;
238 | MPU->RASR = rasr;
239 | }
240 |
241 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
242 | * \param dst Destination data is copied to.
243 | * \param src Source data is copied from.
244 | * \param len Amount of data words to be copied.
245 | */
246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 | {
248 | uint32_t i;
249 | for (i = 0U; i < len; ++i)
250 | {
251 | dst[i] = src[i];
252 | }
253 | }
254 |
255 | /** Load the given number of MPU regions from a table.
256 | * \param table Pointer to the MPU configuration table.
257 | * \param cnt Amount of regions to be configured.
258 | */
259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 | {
261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262 | while (cnt > MPU_TYPE_RALIASES) {
263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 | table += MPU_TYPE_RALIASES;
265 | cnt -= MPU_TYPE_RALIASES;
266 | }
267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 | }
269 |
270 | #endif
271 |
--------------------------------------------------------------------------------
/stm32f411_fw_nrf24l01p/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal.h
4 | * @author MCD Application Team
5 | * @brief This file contains all the functions prototypes for the HAL
6 | * module driver.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_HAL_H
23 | #define __STM32F4xx_HAL_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f4xx_hal_conf.h"
31 |
32 | /** @addtogroup STM32F4xx_HAL_Driver
33 | * @{
34 | */
35 |
36 | /** @addtogroup HAL
37 | * @{
38 | */
39 |
40 | /* Exported types ------------------------------------------------------------*/
41 | /* Exported constants --------------------------------------------------------*/
42 |
43 | /** @defgroup HAL_Exported_Constants HAL Exported Constants
44 | * @{
45 | */
46 |
47 | /** @defgroup HAL_TICK_FREQ Tick Frequency
48 | * @{
49 | */
50 | typedef enum
51 | {
52 | HAL_TICK_FREQ_10HZ = 100U,
53 | HAL_TICK_FREQ_100HZ = 10U,
54 | HAL_TICK_FREQ_1KHZ = 1U,
55 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
56 | } HAL_TickFreqTypeDef;
57 | /**
58 | * @}
59 | */
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /* Exported macro ------------------------------------------------------------*/
66 | /** @defgroup HAL_Exported_Macros HAL Exported Macros
67 | * @{
68 | */
69 |
70 | /** @brief Freeze/Unfreeze Peripherals in Debug mode
71 | */
72 | #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
73 | #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
74 | #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
75 | #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
76 | #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
77 | #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
78 | #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
79 | #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
80 | #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
81 | #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
82 | #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
83 | #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
84 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
85 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
86 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
87 | #define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
88 | #define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
89 | #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
90 | #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
91 | #define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
92 | #define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
93 | #define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
94 |
95 | #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
96 | #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
97 | #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
98 | #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
99 | #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
100 | #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
101 | #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
102 | #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
103 | #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
104 | #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
105 | #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
106 | #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
107 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
108 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
109 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
110 | #define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
111 | #define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
112 | #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
113 | #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
114 | #define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
115 | #define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
116 | #define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
117 |
118 | /** @brief Main Flash memory mapped at 0x00000000
119 | */
120 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
121 |
122 | /** @brief System Flash memory mapped at 0x00000000
123 | */
124 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
125 | SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
126 | }while(0);
127 |
128 | /** @brief Embedded SRAM mapped at 0x00000000
129 | */
130 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
131 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
132 | }while(0);
133 |
134 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
135 | /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
136 | */
137 | #define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
138 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
139 | }while(0);
140 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
141 |
142 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
143 | defined(STM32F469xx) || defined(STM32F479xx)
144 | /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
145 | */
146 | #define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
147 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
148 | }while(0);
149 |
150 | /** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
151 | */
152 | #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
153 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
154 | }while(0);
155 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
156 |
157 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
158 | /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
159 | * @{
160 | */
161 | /** @brief SYSCFG Break Lockup lock
162 | * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
163 | * @note The selected configuration is locked and can be unlocked by system reset
164 | */
165 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
166 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
167 | }while(0)
168 | /**
169 | * @}
170 | */
171 |
172 | /** @defgroup PVD_Lock_Enable PVD Lock
173 | * @{
174 | */
175 | /** @brief SYSCFG Break PVD lock
176 | * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
177 | * @note The selected configuration is locked and can be unlocked by system reset
178 | */
179 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
180 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
181 | }while(0)
182 | /**
183 | * @}
184 | */
185 | #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
186 | /**
187 | * @}
188 | */
189 |
190 | /** @defgroup HAL_Private_Macros HAL Private Macros
191 | * @{
192 | */
193 | #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
194 | ((FREQ) == HAL_TICK_FREQ_100HZ) || \
195 | ((FREQ) == HAL_TICK_FREQ_1KHZ))
196 | /**
197 | * @}
198 | */
199 |
200 | /* Exported variables --------------------------------------------------------*/
201 |
202 | /** @addtogroup HAL_Exported_Variables
203 | * @{
204 | */
205 | extern __IO uint32_t uwTick;
206 | extern uint32_t uwTickPrio;
207 | extern HAL_TickFreqTypeDef uwTickFreq;
208 | /**
209 | * @}
210 | */
211 |
212 | /* Exported functions --------------------------------------------------------*/
213 | /** @addtogroup HAL_Exported_Functions
214 | * @{
215 | */
216 | /** @addtogroup HAL_Exported_Functions_Group1
217 | * @{
218 | */
219 | /* Initialization and Configuration functions ******************************/
220 | HAL_StatusTypeDef HAL_Init(void);
221 | HAL_StatusTypeDef HAL_DeInit(void);
222 | void HAL_MspInit(void);
223 | void HAL_MspDeInit(void);
224 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
225 | /**
226 | * @}
227 | */
228 |
229 | /** @addtogroup HAL_Exported_Functions_Group2
230 | * @{
231 | */
232 | /* Peripheral Control functions ************************************************/
233 | void HAL_IncTick(void);
234 | void HAL_Delay(uint32_t Delay);
235 | uint32_t HAL_GetTick(void);
236 | uint32_t HAL_GetTickPrio(void);
237 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
238 | HAL_TickFreqTypeDef HAL_GetTickFreq(void);
239 | void HAL_SuspendTick(void);
240 | void HAL_ResumeTick(void);
241 | uint32_t HAL_GetHalVersion(void);
242 | uint32_t HAL_GetREVID(void);
243 | uint32_t HAL_GetDEVID(void);
244 | void HAL_DBGMCU_EnableDBGSleepMode(void);
245 | void HAL_DBGMCU_DisableDBGSleepMode(void);
246 | void HAL_DBGMCU_EnableDBGStopMode(void);
247 | void HAL_DBGMCU_DisableDBGStopMode(void);
248 | void HAL_DBGMCU_EnableDBGStandbyMode(void);
249 | void HAL_DBGMCU_DisableDBGStandbyMode(void);
250 | void HAL_EnableCompensationCell(void);
251 | void HAL_DisableCompensationCell(void);
252 | uint32_t HAL_GetUIDw0(void);
253 | uint32_t HAL_GetUIDw1(void);
254 | uint32_t HAL_GetUIDw2(void);
255 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
256 | defined(STM32F469xx) || defined(STM32F479xx)
257 | void HAL_EnableMemorySwappingBank(void);
258 | void HAL_DisableMemorySwappingBank(void);
259 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
260 | /**
261 | * @}
262 | */
263 |
264 | /**
265 | * @}
266 | */
267 | /* Private types -------------------------------------------------------------*/
268 | /* Private variables ---------------------------------------------------------*/
269 | /** @defgroup HAL_Private_Variables HAL Private Variables
270 | * @{
271 | */
272 | /**
273 | * @}
274 | */
275 | /* Private constants ---------------------------------------------------------*/
276 | /** @defgroup HAL_Private_Constants HAL Private Constants
277 | * @{
278 | */
279 | /**
280 | * @}
281 | */
282 | /* Private macros ------------------------------------------------------------*/
283 | /* Private functions ---------------------------------------------------------*/
284 | /**
285 | * @}
286 | */
287 |
288 | /**
289 | * @}
290 | */
291 |
292 | #ifdef __cplusplus
293 | }
294 | #endif
295 |
296 | #endif /* __STM32F4xx_HAL_H */
297 |
298 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
299 |
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/stm32f411_fw_nrf24l01p/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_gpio.h
4 | * @author MCD Application Team
5 | * @brief Header file of GPIO HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_GPIO_H
22 | #define __STM32F4xx_HAL_GPIO_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup GPIO
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup GPIO_Exported_Types GPIO Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief GPIO Init structure definition
46 | */
47 | typedef struct
48 | {
49 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
50 | This parameter can be any value of @ref GPIO_pins_define */
51 |
52 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
53 | This parameter can be a value of @ref GPIO_mode_define */
54 |
55 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
56 | This parameter can be a value of @ref GPIO_pull_define */
57 |
58 | uint32_t Speed; /*!< Specifies the speed for the selected pins.
59 | This parameter can be a value of @ref GPIO_speed_define */
60 |
61 | uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
62 | This parameter can be a value of @ref GPIO_Alternate_function_selection */
63 | }GPIO_InitTypeDef;
64 |
65 | /**
66 | * @brief GPIO Bit SET and Bit RESET enumeration
67 | */
68 | typedef enum
69 | {
70 | GPIO_PIN_RESET = 0,
71 | GPIO_PIN_SET
72 | }GPIO_PinState;
73 | /**
74 | * @}
75 | */
76 |
77 | /* Exported constants --------------------------------------------------------*/
78 |
79 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
80 | * @{
81 | */
82 |
83 | /** @defgroup GPIO_pins_define GPIO pins define
84 | * @{
85 | */
86 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
87 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
88 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
89 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
90 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
91 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
92 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
93 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
94 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
95 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
96 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
97 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
98 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
99 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
100 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
101 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
102 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
103 |
104 | #define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
105 | /**
106 | * @}
107 | */
108 |
109 | /** @defgroup GPIO_mode_define GPIO mode define
110 | * @brief GPIO Configuration Mode
111 | * Elements values convention: 0xX0yz00YZ
112 | * - X : GPIO mode or EXTI Mode
113 | * - y : External IT or Event trigger detection
114 | * - z : IO configuration on External IT or Event
115 | * - Y : Output type (Push Pull or Open Drain)
116 | * - Z : IO Direction mode (Input, Output, Alternate or Analog)
117 | * @{
118 | */
119 | #define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
120 | #define GPIO_MODE_OUTPUT_PP (MODE_PP | MODE_OUTPUT) /*!< Output Push Pull Mode */
121 | #define GPIO_MODE_OUTPUT_OD (MODE_OD | MODE_OUTPUT) /*!< Output Open Drain Mode */
122 | #define GPIO_MODE_AF_PP (MODE_PP | MODE_AF) /*!< Alternate Function Push Pull Mode */
123 | #define GPIO_MODE_AF_OD (MODE_OD | MODE_AF) /*!< Alternate Function Open Drain Mode */
124 |
125 | #define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
126 |
127 | #define GPIO_MODE_IT_RISING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
128 | #define GPIO_MODE_IT_FALLING (EXTI_MODE | GPIO_MODE_IT | FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
129 | #define GPIO_MODE_IT_RISING_FALLING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE | FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
130 |
131 | #define GPIO_MODE_EVT_RISING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE) /*!< External Event Mode with Rising edge trigger detection */
132 | #define GPIO_MODE_EVT_FALLING (EXTI_MODE | GPIO_MODE_EVT | FALLING_EDGE) /*!< External Event Mode with Falling edge trigger detection */
133 | #define GPIO_MODE_EVT_RISING_FALLING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE | FALLING_EDGE) /*!< External Event Mode with Rising/Falling edge trigger detection */
134 |
135 | /**
136 | * @}
137 | */
138 |
139 | /** @defgroup GPIO_speed_define GPIO speed define
140 | * @brief GPIO Output Maximum frequency
141 | * @{
142 | */
143 | #define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */
144 | #define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
145 | #define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
146 | #define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
147 | /**
148 | * @}
149 | */
150 |
151 | /** @defgroup GPIO_pull_define GPIO pull define
152 | * @brief GPIO Pull-Up or Pull-Down Activation
153 | * @{
154 | */
155 | #define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
156 | #define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
157 | #define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
158 | /**
159 | * @}
160 | */
161 |
162 | /**
163 | * @}
164 | */
165 |
166 | /* Exported macro ------------------------------------------------------------*/
167 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
168 | * @{
169 | */
170 |
171 | /**
172 | * @brief Checks whether the specified EXTI line flag is set or not.
173 | * @param __EXTI_LINE__ specifies the EXTI line flag to check.
174 | * This parameter can be GPIO_PIN_x where x can be(0..15)
175 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
176 | */
177 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
178 |
179 | /**
180 | * @brief Clears the EXTI's line pending flags.
181 | * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
182 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
183 | * @retval None
184 | */
185 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
186 |
187 | /**
188 | * @brief Checks whether the specified EXTI line is asserted or not.
189 | * @param __EXTI_LINE__ specifies the EXTI line to check.
190 | * This parameter can be GPIO_PIN_x where x can be(0..15)
191 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
192 | */
193 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
194 |
195 | /**
196 | * @brief Clears the EXTI's line pending bits.
197 | * @param __EXTI_LINE__ specifies the EXTI lines to clear.
198 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
199 | * @retval None
200 | */
201 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
202 |
203 | /**
204 | * @brief Generates a Software interrupt on selected EXTI line.
205 | * @param __EXTI_LINE__ specifies the EXTI line to check.
206 | * This parameter can be GPIO_PIN_x where x can be(0..15)
207 | * @retval None
208 | */
209 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
210 | /**
211 | * @}
212 | */
213 |
214 | /* Include GPIO HAL Extension module */
215 | #include "stm32f4xx_hal_gpio_ex.h"
216 |
217 | /* Exported functions --------------------------------------------------------*/
218 | /** @addtogroup GPIO_Exported_Functions
219 | * @{
220 | */
221 |
222 | /** @addtogroup GPIO_Exported_Functions_Group1
223 | * @{
224 | */
225 | /* Initialization and de-initialization functions *****************************/
226 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
227 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
228 | /**
229 | * @}
230 | */
231 |
232 | /** @addtogroup GPIO_Exported_Functions_Group2
233 | * @{
234 | */
235 | /* IO operation functions *****************************************************/
236 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
237 | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
238 | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
239 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
240 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
241 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
242 |
243 | /**
244 | * @}
245 | */
246 |
247 | /**
248 | * @}
249 | */
250 | /* Private types -------------------------------------------------------------*/
251 | /* Private variables ---------------------------------------------------------*/
252 | /* Private constants ---------------------------------------------------------*/
253 | /** @defgroup GPIO_Private_Constants GPIO Private Constants
254 | * @{
255 | */
256 | #define GPIO_MODE 0x00000003U
257 | #define EXTI_MODE 0x10000000U
258 | #define GPIO_MODE_IT 0x00010000U
259 | #define GPIO_MODE_EVT 0x00020000U
260 | #define RISING_EDGE 0x00100000U
261 | #define FALLING_EDGE 0x00200000U
262 | #define GPIO_OUTPUT_TYPE 0x00000010U
263 |
264 | #define MODE_INPUT 0x00000000U /*!< Input Mode */
265 | #define MODE_OUTPUT 0x00000001U /*!< Output Mode */
266 | #define MODE_AF 0x00000002U /*!< Alternate Function Mode */
267 | #define MODE_ANALOG 0x00000003U /*!< Analog Mode */
268 |
269 | #define MODE_PP 0x00000000U /*!< Push Pull Mode */
270 | #define MODE_OD 0x00000010U /*!< Open Drain Mode */
271 |
272 | /**
273 | * @}
274 | */
275 |
276 | /* Private macros ------------------------------------------------------------*/
277 | /** @defgroup GPIO_Private_Macros GPIO Private Macros
278 | * @{
279 | */
280 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
281 | #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
282 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
283 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
284 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
285 | ((MODE) == GPIO_MODE_AF_PP) ||\
286 | ((MODE) == GPIO_MODE_AF_OD) ||\
287 | ((MODE) == GPIO_MODE_IT_RISING) ||\
288 | ((MODE) == GPIO_MODE_IT_FALLING) ||\
289 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
290 | ((MODE) == GPIO_MODE_EVT_RISING) ||\
291 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\
292 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
293 | ((MODE) == GPIO_MODE_ANALOG))
294 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
295 | ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
296 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
297 | ((PULL) == GPIO_PULLDOWN))
298 | /**
299 | * @}
300 | */
301 |
302 | /* Private functions ---------------------------------------------------------*/
303 | /** @defgroup GPIO_Private_Functions GPIO Private Functions
304 | * @{
305 | */
306 |
307 | /**
308 | * @}
309 | */
310 |
311 | /**
312 | * @}
313 | */
314 |
315 | /**
316 | * @}
317 | */
318 |
319 | #ifdef __cplusplus
320 | }
321 | #endif
322 |
323 | #endif /* __STM32F4xx_HAL_GPIO_H */
324 |
325 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
326 |
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