├── .DS_Store ├── .gitignore ├── .vscode └── settings.json ├── ALU ├── .DS_Store ├── alu.srcs │ ├── .DS_Store │ ├── constrs_1 │ │ └── new │ │ │ └── ALU.xdc │ ├── sim_1 │ │ ├── .DS_Store │ │ └── new │ │ │ └── ALU_sim.v │ └── sources_1 │ │ └── new │ │ ├── ALU.v │ │ ├── BigALU.v │ │ ├── Fdiv.v │ │ ├── Register.v │ │ ├── Tube.v │ │ └── top.v ├── alu.xpr ├── sk2_1.wcfg ├── 嘶考.txt ├── 数据记录表.xlsx └── 第11章 RISC-V模型机设计实验项目1-7.pdf ├── CPU ├── ALU.v ├── CU.v ├── Fdiv.v ├── ID.v ├── IF.v ├── RAM.v ├── RegFile.v ├── Register.v ├── TMP ├── TOP.v ├── Tube.v ├── ip.coe └── ram.coe ├── Compile ├── 8 ├── 9 ├── 10 ├── 11 ├── acc.s ├── coe.txt ├── exam10.s ├── exam11.s ├── exam8.s ├── exam9.s ├── move.s ├── my_sum_rev.s ├── sum ├── sum.cpp ├── sum.s ├── sum_c_o2_r.s ├── sum_c_r.s ├── test.s └── tmp.s ├── IM ├── .DS_Store ├── IM.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── top.xdc │ ├── sim_1 │ │ └── new │ │ │ └── simu.v │ └── sources_1 │ │ ├── new │ │ ├── Fdiv.v │ │ ├── ID.v │ │ ├── IF.v │ │ ├── Register.v │ │ ├── Top.v │ │ ├── Tube.v │ │ └── button.v │ │ └── rom.coe └── IM.xpr ├── RAM ├── .DS_Store ├── RAM.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── RAM.xdc │ ├── sim_1 │ │ └── new │ │ │ └── sim.v │ ├── sources_1 │ │ ├── ip │ │ │ ├── RAM_A │ │ │ │ └── RAM_A.xci │ │ │ └── ip.coe │ │ └── new │ │ │ ├── DataSelector.v │ │ │ ├── Fdiv.v │ │ │ ├── RAM.v │ │ │ └── Tube.v │ └── utils_1 │ │ └── imports │ │ └── synth_1 │ │ └── RAM.dcp ├── RAM.xpr ├── RAM记录表.xlsx ├── top.bit └── wave.wcfg ├── README.md └── RegisterFile ├── RegisterFile.srcs ├── constrs_1 │ └── new │ │ └── RegFile.xdc ├── sim_1 │ └── new │ │ └── simu_RegFile.v ├── sources_1 │ └── new │ │ ├── ALU.v │ │ ├── BigALU.v │ │ ├── Fdiv.v │ │ ├── RegFile.v │ │ ├── Register.v │ │ ├── TOP.v │ │ └── Tube.v └── utils_1 │ └── imports │ └── synth_1 │ └── TOP.dcp ├── RegisterFile.xpr └── TOP.bit /.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/.DS_Store -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.sim 2 | *.ip_user_files 3 | *.hw 4 | *.hbs 5 | *cache 6 | *.runs 7 | *.ioplanning 8 | *.gen 9 | ip -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | {} -------------------------------------------------------------------------------- /ALU/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/ALU/.DS_Store -------------------------------------------------------------------------------- /ALU/alu.srcs/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/ALU/alu.srcs/.DS_Store -------------------------------------------------------------------------------- /ALU/alu.srcs/constrs_1/new/ALU.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD LVCMOS18 [get_ports clk_100M] 2 | set_property IOSTANDARD LVCMOS18 [get_ports clk_A] 3 | set_property IOSTANDARD LVCMOS18 [get_ports clk_B] 4 | set_property IOSTANDARD LVCMOS18 [get_ports clk_F] 5 | set_property IOSTANDARD LVCMOS18 [get_ports load] 6 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[7]}] 7 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[6]}] 8 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[5]}] 9 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[4]}] 10 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[3]}] 11 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[2]}] 12 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[1]}] 13 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[0]}] 14 | set_property IOSTANDARD LVCMOS18 [get_ports rst_] 15 | set_property IOSTANDARD LVCMOS18 [get_ports {FR[3]}] 16 | set_property IOSTANDARD LVCMOS18 [get_ports {FR[2]}] 17 | set_property IOSTANDARD LVCMOS18 [get_ports {FR[1]}] 18 | set_property IOSTANDARD LVCMOS18 [get_ports {FR[0]}] 19 | set_property IOSTANDARD LVCMOS18 [get_ports {choose_in[2]}] 20 | set_property IOSTANDARD LVCMOS18 [get_ports {choose_in[1]}] 21 | set_property IOSTANDARD LVCMOS18 [get_ports {choose_in[0]}] 22 | set_property IOSTANDARD LVCMOS18 [get_ports {choose_out[0]}] 23 | set_property IOSTANDARD LVCMOS18 [get_ports {choose_out[1]}] 24 | set_property IOSTANDARD LVCMOS18 [get_ports {data_in[7]}] 25 | set_property IOSTANDARD LVCMOS18 [get_ports {data_in[6]}] 26 | set_property IOSTANDARD LVCMOS18 [get_ports {data_in[5]}] 27 | set_property IOSTANDARD LVCMOS18 [get_ports {data_in[4]}] 28 | set_property IOSTANDARD LVCMOS18 [get_ports {data_in[3]}] 29 | set_property IOSTANDARD LVCMOS18 [get_ports {data_in[2]}] 30 | set_property IOSTANDARD LVCMOS18 [get_ports {data_in[1]}] 31 | set_property IOSTANDARD LVCMOS18 [get_ports {data_in[0]}] 32 | set_property IOSTANDARD LVCMOS18 [get_ports {seg[7]}] 33 | set_property IOSTANDARD LVCMOS18 [get_ports {seg[6]}] 34 | set_property IOSTANDARD LVCMOS18 [get_ports {seg[5]}] 35 | set_property IOSTANDARD LVCMOS18 [get_ports {seg[4]}] 36 | set_property IOSTANDARD LVCMOS18 [get_ports {seg[3]}] 37 | set_property IOSTANDARD LVCMOS18 [get_ports {seg[2]}] 38 | set_property IOSTANDARD LVCMOS18 [get_ports {seg[1]}] 39 | set_property IOSTANDARD LVCMOS18 [get_ports {seg[0]}] 40 | set_property IOSTANDARD LVCMOS18 [get_ports {ALU_OP[3]}] 41 | set_property IOSTANDARD LVCMOS18 [get_ports {ALU_OP[2]}] 42 | set_property IOSTANDARD LVCMOS18 [get_ports {ALU_OP[1]}] 43 | set_property IOSTANDARD LVCMOS18 [get_ports {ALU_OP[0]}] 44 | 45 | set_property PACKAGE_PIN C9 [get_ports {AN[7]}] 46 | set_property PACKAGE_PIN C10 [get_ports {AN[6]}] 47 | set_property PACKAGE_PIN D10 [get_ports {AN[5]}] 48 | set_property PACKAGE_PIN C11 [get_ports {AN[4]}] 49 | set_property PACKAGE_PIN M17 [get_ports {AN[3]}] 50 | set_property PACKAGE_PIN J14 [get_ports {AN[2]}] 51 | set_property PACKAGE_PIN K13 [get_ports {AN[1]}] 52 | set_property PACKAGE_PIN P14 [get_ports {AN[0]}] 53 | set_property PACKAGE_PIN V5 [get_ports {data[3]}] 54 | set_property PACKAGE_PIN T4 [get_ports {data[2]}] 55 | set_property PACKAGE_PIN V6 [get_ports {data[1]}] 56 | set_property PACKAGE_PIN F14 [get_ports {seg[7]}] 57 | set_property PACKAGE_PIN N14 [get_ports {seg[6]}] 58 | set_property PACKAGE_PIN J13 [get_ports {seg[5]}] 59 | set_property PACKAGE_PIN G13 [get_ports {seg[4]}] 60 | set_property PACKAGE_PIN F13 [get_ports {seg[3]}] 61 | set_property PACKAGE_PIN G14 [get_ports {seg[2]}] 62 | set_property PACKAGE_PIN M13 [get_ports {seg[1]}] 63 | set_property PACKAGE_PIN T5 [get_ports {data[0]}] 64 | set_property PACKAGE_PIN H14 [get_ports {seg[0]}] 65 | set_property PACKAGE_PIN V7 [get_ports {seletct[2]}] 66 | set_property PACKAGE_PIN R8 [get_ports {seletct[1]}] 67 | set_property PACKAGE_PIN U9 [get_ports {seletct[0]}] 68 | 69 | set_property PACKAGE_PIN E3 [get_ports clk_100M] 70 | set_property PACKAGE_PIN N17 [get_ports clk_A] 71 | set_property PACKAGE_PIN P18 [get_ports clk_B] 72 | set_property PACKAGE_PIN P17 [get_ports clk_F] 73 | set_property PACKAGE_PIN U17 [get_ports load] 74 | set_property PACKAGE_PIN U8 [get_ports rst_] 75 | set_property PACKAGE_PIN T14 [get_ports {ALU_OP[3]}] 76 | set_property PACKAGE_PIN V15 [get_ports {ALU_OP[2]}] 77 | set_property PACKAGE_PIN R15 [get_ports {ALU_OP[1]}] 78 | set_property PACKAGE_PIN U6 [get_ports {FR[3]}] 79 | set_property PACKAGE_PIN R5 [get_ports {FR[2]}] 80 | set_property PACKAGE_PIN U7 [get_ports {FR[1]}] 81 | set_property PACKAGE_PIN R6 [get_ports {FR[0]}] 82 | set_property PACKAGE_PIN V5 [get_ports {data_in[7]}] 83 | set_property PACKAGE_PIN T4 [get_ports {data_in[6]}] 84 | set_property PACKAGE_PIN V6 [get_ports {data_in[5]}] 85 | set_property PACKAGE_PIN T5 [get_ports {data_in[4]}] 86 | set_property PACKAGE_PIN T6 [get_ports {data_in[3]}] 87 | set_property PACKAGE_PIN V7 [get_ports {data_in[2]}] 88 | set_property PACKAGE_PIN R8 [get_ports {data_in[1]}] 89 | set_property PACKAGE_PIN U9 [get_ports {data_in[0]}] 90 | set_property PACKAGE_PIN U16 [get_ports {ALU_OP[0]}] 91 | set_property PACKAGE_PIN V10 [get_ports {choose_in[2]}] 92 | set_property PACKAGE_PIN R10 [get_ports {choose_in[1]}] 93 | set_property PACKAGE_PIN U11 [get_ports {choose_in[0]}] 94 | set_property PACKAGE_PIN U12 [get_ports {choose_out[1]}] 95 | set_property PACKAGE_PIN T13 [get_ports {choose_out[0]}] 96 | 97 | 98 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_A_IBUF] 99 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_B_IBUF] 100 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_F_IBUF] 101 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst__IBUF] 102 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets load_IBUF] -------------------------------------------------------------------------------- /ALU/alu.srcs/sim_1/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/ALU/alu.srcs/sim_1/.DS_Store -------------------------------------------------------------------------------- /ALU/alu.srcs/sim_1/new/ALU_sim.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ALU_sim(); 3 | reg[31:0]A,B; 4 | reg[3:0]OP; 5 | wire[31:0]F; 6 | wire ZF,SF,CF,OF; 7 | ALU alu(OP,A,B,F,ZF,SF,CF,OF); 8 | initial 9 | begin 10 | A=32'h7fff_fff0;B=32'h7fff_ffff; 11 | OP=4'b0; 12 | end 13 | always 14 | begin 15 | #100; 16 | OP=OP+1'b1; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /ALU/alu.srcs/sources_1/new/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ALU(OP,A,B,F,ZF,SF,CF,OF); 4 | input [3:0]OP; 5 | input [31:0]A,B; 6 | output reg[31:0]F; 7 | output CF,OF,ZF,SF; 8 | 9 | integer i; 10 | reg C1,C2; 11 | assign ZF = F ? 0 : 1; 12 | assign SF = F[31]; 13 | assign OF = A[31] ^ B[31] ^ C1 ^ F[31]; 14 | assign CF = C1; 15 | always @(*) 16 | begin 17 | case(OP) 18 | 4'b0000: 19 | begin 20 | {C1,F} = {1'b0,A} + {1'b0,B}; 21 | end 22 | 4'b0001: F = A << B; 23 | 4'b0010: F = $signed(A) < $signed(B) ? 1 : 0; 24 | 4'b0011: F = A < B ? 1'b1 : 1'b0; 25 | 4'b0100: F = A ^ B; 26 | 4'b0101: F = A >> B; 27 | 4'b0110: F = A | B; 28 | 4'b0111: F = A & B; 29 | 4'b1000: 30 | begin 31 | {C1,F} = {1'b0,A} - {1'b0,B}; 32 | end 33 | 4'b1101: 34 | begin 35 | F = A; 36 | for(i = 0; i < B && i < 32; i = i + 1'b1) 37 | F = {F[31],F[31:1]}; 38 | end 39 | default:F=0; 40 | endcase 41 | 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /ALU/alu.srcs/sources_1/new/BigALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module BigALU(ALU_OP,Data_A,Data_B,rst_,clk_A,clk_B,clk_F,A,B,F,FR); 4 | input [3:0]ALU_OP; 5 | input [31:0]Data_A,Data_B; 6 | input rst_,clk_A,clk_B,clk_F; 7 | output [31:0]F; 8 | output [3:0]FR; 9 | output [31:0]A,B; 10 | wire [31:0]res; 11 | wire ZF,SF,CF,OF; 12 | Register RA(clk_A,rst_,Data_A,A); 13 | Register RB(clk_B,rst_,Data_B,B); 14 | ALU alu(ALU_OP,A,B,res,ZF,SF,CF,OF); 15 | Register RF(clk_F,rst_,res,F); 16 | Register flag_register(clk_F,rst_,{28'b0,ZF,SF,CF,OF},FR); 17 | endmodule -------------------------------------------------------------------------------- /ALU/alu.srcs/sources_1/new/Fdiv.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Fdiv(input reset,input[31:0] mult,input clk_1M,output reg clk_1K); 3 | reg [31:0]counter; 4 | initial begin counter = 32'd0;end 5 | initial begin clk_1K = 0;end 6 | always @(posedge clk_1M or negedge reset) begin 7 | if(!reset)begin 8 | counter <= 32'd0; 9 | clk_1K <= 1'b0; 10 | end 11 | else if(counter == mult) begin 12 | clk_1K <= ~clk_1K; 13 | counter <= 32'd0; 14 | end 15 | else begin 16 | counter <= counter + 1'b1; 17 | end 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /ALU/alu.srcs/sources_1/new/Register.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Register(clk,rst_,X,Y); 3 | input clk,rst_; 4 | input [31:0]X; 5 | output reg [31:0]Y; 6 | always @(posedge clk or negedge rst_) 7 | begin 8 | if(!rst_) Y <= 32'b0; 9 | else Y <= X; 10 | end 11 | endmodule -------------------------------------------------------------------------------- /ALU/alu.srcs/sources_1/new/Tube.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module scan_data(reset,data,clk,AN,seg); 4 | output [7:0]AN; 5 | output [7:0]seg; 6 | input reset; 7 | input clk; 8 | input [31:0]data; 9 | wire clk_5ms; 10 | reg [2:0]select = 0; 11 | Fdiv utt(reset,32'd50000,clk,clk_5ms); 12 | 13 | always @(posedge clk_5ms or negedge reset) begin 14 | if(!reset)begin 15 | select <= 3'd0; 16 | end 17 | else begin 18 | select <= select + 3'd1; 19 | end 20 | end 21 | 22 | reg [3:0]data_in; 23 | show sh(data_in,select,AN,seg); 24 | always @(*) begin 25 | case (select) 26 | 7: data_in = data[31:28]; 27 | 6: data_in = data[27:24]; 28 | 5: data_in = data[23:20]; 29 | 4: data_in = data[19:16]; 30 | 3: data_in = data[15:12]; 31 | 2: data_in = data[11:8]; 32 | 1: data_in = data[7:4]; 33 | 0: data_in = data[3:0]; 34 | endcase 35 | end 36 | endmodule 37 | 38 | 39 | module show(data,seletct,AN,seg); 40 | input [3:0]data; 41 | input [2:0]seletct; 42 | output reg[7:0]AN; 43 | output reg [7:0]seg; 44 | 45 | always @(*) begin 46 | case(seletct) 47 | 0 : AN = 8'b11111110; 48 | 1 : AN = 8'b11111101; 49 | 2 : AN = 8'b11111011; 50 | 3 : AN = 8'b11110111; 51 | 4 : AN = 8'b11101111; 52 | 5 : AN = 8'b11011111; 53 | 6 : AN = 8'b10111111; 54 | 7 : AN = 8'b01111111; 55 | default: AN = 8'Hff; 56 | endcase 57 | end 58 | 59 | always @(*) begin 60 | case (data) 61 | 0 : seg = 8'b00000011; 62 | 1 : seg = 8'b10011111; 63 | 2 : seg = 8'b00100101; 64 | 3 : seg = 8'b00001101; 65 | 4 : seg = 8'b10011001; 66 | 5 : seg = 8'b01001001; 67 | 6 : seg = 8'b01000001; 68 | 7 : seg = 8'b00011111; 69 | 8 : seg = 8'b00000001; 70 | 9 : seg = 8'b00001001; 71 | 10: seg = 8'b00010001; 72 | 11: seg = 8'b11000001; 73 | 12: seg = 8'b01100011; 74 | 13: seg = 8'b10000101; 75 | 14: seg = 8'b01100001; 76 | 15: seg = 8'b01110001; 77 | default:seg = 8'Hff; 78 | endcase 79 | end 80 | endmodule -------------------------------------------------------------------------------- /ALU/alu.srcs/sources_1/new/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module top(clk_100M,rst_,clk_A,clk_B,clk_F,load,data_in,choose_out,choose_in,ALU_OP,FR,seg,AN); 3 | input clk_100M; 4 | input [7:0]data_in; 5 | input rst_,clk_A,clk_B,clk_F; 6 | input load; 7 | input [1:0]choose_out; 8 | input [2:0]choose_in; 9 | input [3:0]ALU_OP; 10 | output [3:0]FR; 11 | output [7:0]seg; 12 | output [7:0]AN; 13 | 14 | reg [31:0]A_input,B_input; 15 | reg [31:0]out; 16 | wire [31:0]A,B,F; 17 | 18 | BigALU alu(ALU_OP,A_input,B_input,rst_,clk_A,clk_B,clk_F,A,B,F,FR); 19 | scan_data show(rst_,out,clk_100M,AN,seg); 20 | 21 | always @(negedge rst_ or posedge load) 22 | begin 23 | if(!rst_) 24 | begin 25 | A_input <= 32'd0; 26 | B_input <= 32'd0; 27 | end 28 | else 29 | begin 30 | case(choose_in) 31 | 3'b000:A_input[31:24] <= data_in; 32 | 3'b001:A_input[23:16] <= data_in; 33 | 3'b010:A_input[15:8] <= data_in; 34 | 3'b011:A_input[7:0] <= data_in; 35 | 3'b100:B_input[31:24] <= data_in; 36 | 3'b101:B_input[23:16] <= data_in; 37 | 3'b110:B_input[15:8] <= data_in; 38 | 3'b111:B_input[7:0] <= data_in; 39 | endcase 40 | end 41 | end 42 | 43 | always @(*) 44 | begin 45 | if(!rst_) 46 | begin 47 | out <= 32'd0; 48 | end 49 | else 50 | begin 51 | case(choose_out) 52 | 2'b00:out <= A_input; 53 | 2'b01:out <= B_input; 54 | 2'b10:out <= F; 55 | 2'b11:out <= {28'b0,FR}; 56 | endcase 57 | end 58 | end 59 | 60 | endmodule -------------------------------------------------------------------------------- /ALU/alu.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 176 | 177 | 178 | 179 | 180 | 182 | 183 | 184 | 185 | 186 | 189 | 190 | 192 | 193 | 195 | 196 | 198 | 199 | 201 | 202 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | Vivado Synthesis Defaults 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | Default settings for Implementation. 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | default_dashboard 283 | 284 | 285 | 286 | -------------------------------------------------------------------------------- /ALU/sk2_1.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | A[31:0] 25 | A[31:0] 26 | 27 | 28 | B[31:0] 29 | B[31:0] 30 | 31 | 32 | OP[3:0] 33 | OP[3:0] 34 | 35 | 36 | F[31:0] 37 | F[31:0] 38 | 39 | 40 | ZF 41 | ZF 42 | 43 | 44 | SF 45 | SF 46 | 47 | 48 | CF 49 | CF 50 | 51 | 52 | OF 53 | OF 54 | 55 | 56 | -------------------------------------------------------------------------------- /ALU/嘶考.txt: -------------------------------------------------------------------------------- 1 | 有符号数比较大小通过相减之后判断OF和SF来进行 -------------------------------------------------------------------------------- /ALU/数据记录表.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/ALU/数据记录表.xlsx -------------------------------------------------------------------------------- /ALU/第11章 RISC-V模型机设计实验项目1-7.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/ALU/第11章 RISC-V模型机设计实验项目1-7.pdf -------------------------------------------------------------------------------- /CPU/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ALU(OP,A,B,F,ZF,SF,CF,OF); 4 | input [3:0]OP; 5 | input [31:0]A,B; 6 | output reg[31:0]F; 7 | output CF,OF,ZF,SF; 8 | 9 | integer i; 10 | reg C1,C2; 11 | assign ZF = F ? 0 : 1; 12 | assign SF = F[31]; 13 | assign OF = A[31] ^ B[31] ^ C1 ^ F[31]; 14 | assign CF = C1; 15 | always @(*) 16 | begin 17 | case(OP) 18 | 4'b0000: 19 | begin 20 | {C1,F} = {1'b0,A} + {1'b0,B}; 21 | end 22 | 4'b0001: F = A << B; 23 | 4'b0010: F = $signed(A) < $signed(B) ? 1 : 0; 24 | 4'b0011: F = A < B ? 1'b1 : 1'b0; 25 | 4'b0100: F = A ^ B; 26 | 4'b0101: F = A >> B; 27 | 4'b0110: F = A | B; 28 | 4'b0111: F = A & B; 29 | 4'b1000: 30 | begin 31 | {C1,F} = {1'b0,A} - {1'b0,B}; 32 | end 33 | 4'b1101: 34 | begin 35 | F = $signed(A) >>> B; 36 | end 37 | default:F=0; 38 | endcase 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /CPU/CU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module CU(rst_, clk, opcode, func3, func7, CF, OF, ZF, SF, ALU_OP, PC_Write, PC0_Write, IR_Write, Reg_Write, Mem_write, SE_s, Size_s, PC_s, rs2_imm_s, w_data_s, st); 4 | input rst_, clk; 5 | input [6:0] opcode; 6 | input [2:0] func3; 7 | input [6:0] func7; 8 | input CF, OF, ZF, SF; 9 | output [3:0] ALU_OP; 10 | output reg PC_Write, PC0_Write, IR_Write, Reg_Write, Mem_write; 11 | output SE_s; 12 | output [1:0] Size_s; 13 | output reg [1:0] PC_s; // 0: PC + 4, 1: PC0 + imm, 2: F 14 | output reg rs2_imm_s; // 0: rs2, 1: imm 15 | output reg [2:0] w_data_s; // 0: F, 1: imm, 2: MDR, 3: PC, 4: PC0 + imm 16 | 17 | wire IS_R, IS_IMM, IS_LUI, IS_S, IS_B, IS_J,IS_L, IS_AUIPC, IS_JALR; 18 | 19 | ID2 id2( 20 | .opcode(opcode), 21 | .func3(func3), 22 | .func7(func7), 23 | .IS_R(IS_R), 24 | .IS_IMM(IS_IMM), 25 | .IS_LUI(IS_LUI), 26 | .IS_S(IS_S), 27 | .IS_B(IS_B), 28 | .IS_J(IS_J), 29 | .IS_CSR(), 30 | .IS_L(IS_L), 31 | .IS_AUIPC(IS_AUIPC), 32 | .IS_JALR(IS_JALR), 33 | .ALU_OP(ALU_OP), 34 | .Size_s(Size_s), 35 | .SE_s(SE_s) 36 | ); 37 | 38 | reg cc; 39 | // generate cc 40 | always @(*) begin 41 | if (IS_B) begin 42 | case(func3) 43 | 3'b000: cc = ZF; //beq 44 | 3'b001: cc = ~ZF; //bne 45 | 3'b100: cc = (SF ^ OF) & (~ZF); //blt 46 | 3'b101: cc = ~((SF ^ OF) & (~ZF)); //bge 47 | 3'b110: cc = CF; //bltu 48 | 3'b111: cc = ~CF; //bgeu 49 | default: cc = 1'b0; 50 | endcase 51 | end 52 | else cc = 1'b0; 53 | end 54 | 55 | // status update 56 | output reg [3:0] st; 57 | reg [3:0] next_st; 58 | always @(posedge clk or negedge rst_) begin 59 | if (!rst_) st <= 4'd0; 60 | else st <= next_st; 61 | end 62 | 63 | // generate next status 64 | always @(*) begin 65 | next_st = 4'd0; 66 | case (st) 67 | 4'd0: next_st = 4'd1; 68 | 4'd1: begin 69 | if (IS_IMM || IS_R || IS_L || IS_S || IS_JALR || IS_B) next_st = 4'd2; //I+R+jal+B+S+L 70 | else if (IS_LUI) next_st = 4'd6; //lui 71 | else if (IS_J) next_st = 4'd11; //jal 72 | else next_st = 4'd15; //auipc 73 | end 74 | 4'd2: begin 75 | if(IS_R) next_st = 4'd3; //R 76 | else if (IS_IMM) next_st = 4'd5; //I 77 | else if (IS_L || IS_S || IS_JALR) next_st = 4'd7; //L + S + JARL 78 | else next_st = 4'd13; //B 79 | end 80 | 4'd3: next_st = 4'd4; //R 81 | 4'd4: next_st = 4'd1; //ret 82 | 4'd5: next_st = 4'd4; //I 83 | 4'd6: next_st = 4'd1; //ret 84 | 4'd7: begin 85 | if(IS_L) next_st = 4'd8; //L 86 | else if(IS_S) next_st = 4'd10; //S 87 | else next_st = 4'd12; //JALR 88 | end 89 | 4'd8: next_st = 4'd9; //L 90 | 4'd9: next_st = 4'd1; //ret 91 | 4'd10: next_st = 4'd1; //ret 92 | 4'd11: next_st = 4'd1; //ret 93 | 4'd12: next_st = 4'd1; //ret 94 | 4'd13: next_st = 4'd14; //B 95 | 4'd14: next_st = 4'd1; //ret 96 | 4'd15: next_st = 4'd1; //ret 97 | default: next_st = 4'd0; 98 | endcase 99 | end 100 | 101 | // generate signals 102 | always @(posedge clk or negedge rst_) begin 103 | if(!rst_) begin 104 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b0; 105 | PC_s <= 2'b0; 106 | rs2_imm_s <= 1'b0; 107 | w_data_s <= 3'b0; 108 | end else begin 109 | case (next_st) 110 | 4'd1: begin 111 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b11100; 112 | PC_s <= 2'b00; 113 | end 114 | 4'd2: {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00000; 115 | 4'd3: begin 116 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00000; 117 | rs2_imm_s <= 1'b0; 118 | end 119 | 4'd4: begin 120 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00010; 121 | w_data_s <= 3'b00; 122 | end 123 | 4'd5: begin 124 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00000; 125 | rs2_imm_s <= 1'b1; 126 | end 127 | 4'd6: begin 128 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00010; 129 | w_data_s <= 3'b01; 130 | end 131 | 4'd7: begin 132 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00000; 133 | rs2_imm_s <= 2'b1; 134 | end 135 | 4'd8: {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00000; 136 | 4'd9: begin 137 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00010; 138 | w_data_s <= 3'b10; 139 | end 140 | 4'd10: {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00001; 141 | 4'd11: begin 142 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b10010; 143 | PC_s <= 2'b01; 144 | w_data_s <= 3'b11; 145 | end 146 | 4'd12: begin 147 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b10010; 148 | PC_s <= 2'b10; 149 | w_data_s <= 3'b11; 150 | end 151 | 4'd13: begin 152 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00000; 153 | rs2_imm_s <= 1'b0; 154 | end 155 | 4'd14: begin 156 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= {cc, 4'b00000}; 157 | PC_s <= 2'b01; 158 | end 159 | 4'd15: begin 160 | {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b00010; 161 | w_data_s <= 3'b100; 162 | end 163 | default: {PC_Write, PC0_Write, IR_Write,Reg_Write, Mem_write} <= 5'b0; 164 | endcase 165 | end 166 | end 167 | endmodule 168 | -------------------------------------------------------------------------------- /CPU/Fdiv.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Fdiv(input reset,input[31:0] mult,input clk_1M,output reg clk_1K); 4 | reg [31:0]counter; 5 | initial begin counter = 32'd0;end 6 | initial begin clk_1K = 0;end 7 | always @(posedge clk_1M or negedge reset) begin 8 | if(!reset)begin 9 | counter <= 32'd0; 10 | clk_1K <= 1'b0; 11 | end 12 | else if(counter == mult) begin 13 | clk_1K <= ~clk_1K; 14 | counter <= 32'd0; 15 | end 16 | else begin 17 | counter <= counter + 1'b1; 18 | end 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /CPU/ID.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ID1(inst, rs1, rs2, rd, opcode, func3, func7, imm); 4 | input [31:0]inst; 5 | output [4:0]rs1, rs2, rd; 6 | output [6:0]opcode; 7 | output [2:0]func3; 8 | output [6:0]func7; 9 | output reg[31:0]imm; 10 | wire [31:0]I_shift, I_imm, S_imm, B_imm, U_imm, J_imm; 11 | 12 | assign func7 = inst[31:25]; 13 | assign rs2 = inst[24:20]; 14 | assign rs1 = inst[19:15]; 15 | assign func3 = inst[14:12]; 16 | assign rd = inst[11:7]; 17 | assign opcode = inst[6:0]; 18 | 19 | assign I_shift = {27'b0, inst[24:20]}; 20 | assign I_imm = {{20{inst[31]}}, inst[31:20]}; 21 | assign S_imm = {{20{inst[31]}}, inst[31:25], inst[11:7]}; 22 | assign B_imm = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0}; 23 | assign U_imm = {inst[31:12],{12'b0}}; 24 | assign J_imm = {{12{inst[31]}}, inst[19:12], inst[20], inst[30:21], 1'b0}; 25 | assign CSR_uimm = {27'b0,inst[19:15]}; 26 | 27 | reg [3:0]type; 28 | 29 | always @(*) begin 30 | case(opcode) 31 | //R 32 | 7'b0110011: type = 4'd1; 33 | //I 34 | 7'b0010011: type = 4'd2; 35 | 7'b0000011: type = 4'd2; 36 | 7'b1100111: type = 4'd2; 37 | //U 38 | 7'b0010111: type = 4'd3; //auipc 39 | 7'b0110111: type = 4'd3; //lui 40 | //S 41 | 7'b0100011: type = 4'd4; 42 | //B 43 | 7'b1100011: type = 4'd5; 44 | //J 45 | 7'b1101111: type = 4'd6; 46 | //csr 47 | 7'b1110011: type = 4'd7; 48 | default: type = 4'd0; 49 | endcase 50 | end 51 | 52 | always @(*) begin 53 | case(type) 54 | //R 55 | 4'd1:imm = 32'b0; 56 | //I 57 | 4'd2:imm = (opcode == 7'bb0010011 && (func3 == 3'b101 || func3 == 3'b001)) ? I_shift : I_imm; 58 | //U 59 | 4'd3:imm = U_imm; 60 | //S 61 | 4'd4:imm = S_imm; 62 | //B 63 | 4'd5:imm = B_imm; 64 | //J 65 | 4'd6:imm = J_imm; 66 | //csr 67 | 4'd7:imm = CSR_uimm; 68 | default: imm = 32'b0; 69 | endcase 70 | end 71 | endmodule 72 | 73 | module ID2(opcode, func3, func7, ALU_OP, IS_R, IS_IMM, IS_LUI, IS_S, IS_B, IS_J, IS_CSR, IS_L, IS_AUIPC, IS_JALR, Size_s, SE_s); 74 | input [6:0]opcode; 75 | input [2:0]func3; 76 | input [6:0]func7; 77 | output reg[6:0]ALU_OP; 78 | output IS_R, IS_IMM, IS_LUI, IS_S, IS_B, IS_J, IS_CSR, IS_L, IS_AUIPC, IS_JALR; 79 | 80 | assign IS_R = (opcode == 7'b0110011); 81 | assign IS_IMM = (opcode == 7'b0010011); 82 | assign IS_L = (opcode == 7'b0000011); 83 | assign IS_LUI = (opcode == 7'b0110111); 84 | assign IS_S = (opcode == 7'b0100011); 85 | assign IS_B = (opcode == 7'b1100011); 86 | assign IS_J = (opcode == 7'b1101111); 87 | assign IS_JALR = (opcode == 7'b1100111); 88 | assign IS_CSR = (opcode == 7'b1110011); 89 | assign IS_AUIPC = (opcode == 7'b0010111); 90 | 91 | always @(*) begin 92 | if (IS_R) ALU_OP = {func7[5], func3}; 93 | else if (IS_IMM) ALU_OP = (func3 == 3'b101) ? {func7[5], func3} : {1'b0, func3}; 94 | else if (IS_B) ALU_OP = 4'b1000; 95 | else ALU_OP = 4'b0000; 96 | end 97 | 98 | output reg [1:0]Size_s; 99 | output reg SE_s; 100 | 101 | // generate Size_s, SE_s 102 | always@(*) begin 103 | if (IS_L || IS_S) begin 104 | Size_s = func3[1:0]; 105 | SE_s = ~func3[2]; 106 | end else begin 107 | Size_s = 2'b00; 108 | SE_s = 1'b0; 109 | end 110 | end 111 | 112 | 113 | endmodule -------------------------------------------------------------------------------- /CPU/IF.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module IF(IR_Write, PC_Write, clk_im, pc, ir, rs1, rs2, rd, opcode, func3, func7, imm); 4 | input IR_Write, PC_Write, clk_im; 5 | output [4:0]rs1, rs2, rd; 6 | output [6:0]opcode; 7 | output [2:0]func3; 8 | output [6:0]func7; 9 | output [31:0]imm; 10 | output [31:0]pc; 11 | output [31:0]ir; 12 | 13 | 14 | 15 | Reg PC( 16 | .clk(~clk_im), 17 | .rst_(1'b1), 18 | .Reg_write(PC_Write), 19 | .Data_in(pc + 4), 20 | .Reg(pc) 21 | ); 22 | 23 | wire [31:0]inst_code; 24 | 25 | ROM IM ( 26 | .clka(clk_im), 27 | .addra(pc[7:2]), 28 | .wea(4'b1111), 29 | .douta(inst_code) 30 | ); 31 | 32 | 33 | Reg IR ( 34 | .clk(clk_im), 35 | .rst_(1'b1), 36 | .Reg_write(IR_Write), 37 | .Data_in(inst_code), 38 | .Reg(ir) 39 | ); 40 | 41 | ID1 id1( 42 | .inst(ir), 43 | .rs1(rs1), 44 | .rs2(rs2), 45 | .rd(rd), 46 | .opcode(opcode), 47 | .func3(func3), 48 | .func7(func7), 49 | .imm(imm) 50 | ); 51 | endmodule -------------------------------------------------------------------------------- /CPU/RAM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module W_Process(siz,EN,Low_Addr,RAM_in,D_in,wea); 4 | input [1:0]siz; 5 | input [31:0]RAM_in; 6 | input [1:0]Low_Addr; 7 | input EN; 8 | output [31:0] D_in; 9 | output[3:0] wea; 10 | assign wea = EN ? siz == 2'b00 ? 4'b0001 << Low_Addr[1:0] 11 | :siz == 2'b01 ? 4'b0011 << {Low_Addr[1],1'b0} 12 | :4'b1111 13 | :4'b0000; 14 | 15 | assign D_in = siz == 2'b00 ? {RAM_in[7:0],RAM_in[7:0],RAM_in[7:0],RAM_in[7:0]} 16 | :siz == 2'b01 ? {RAM_in[15:0],RAM_in[15:0]} 17 | :RAM_in; 18 | endmodule 19 | 20 | 21 | module SE(siz,SE,Low_Addr,D_in,Ex_out); 22 | input [1:0]siz; 23 | input SE; 24 | input [31:0]D_in; 25 | input [1:0]Low_Addr; 26 | output [31:0]Ex_out; 27 | 28 | wire [31:0] cur; 29 | assign cur = siz == 2'b00 ? D_in >> {Low_Addr[1:0],3'b0} 30 | :siz == 2'b01 ? D_in >> {Low_Addr[1],4'b0} 31 | :D_in; 32 | 33 | assign Ex_out = siz == 2'b00 ? {{24{cur[7] & SE}},cur[7:0]} 34 | : siz == 2'b01 ? {{16{cur[15] & SE}},cur[15:0]} 35 | : cur; 36 | endmodule 37 | 38 | module RAM(clk_DM,DM_Addr,RAM_Write,siz,SE_s,RAM_in,RAM_out,D_out,D_in,wea); 39 | input clk_DM; 40 | input [7:0]DM_Addr; 41 | input [1:0]siz; 42 | input SE_s; 43 | input [31:0]RAM_in; 44 | output [31:0]RAM_out; 45 | input RAM_Write; 46 | 47 | output [3:0]wea; 48 | output [31:0]D_in; 49 | output [31:0]D_out; 50 | 51 | W_Process read_process( 52 | .siz(siz), 53 | .RAM_in(RAM_in), 54 | .D_in(D_in), 55 | .wea(wea), 56 | .EN(RAM_Write), 57 | .Low_Addr(DM_Addr[1:0]) 58 | ); 59 | 60 | RAM_A Data_RAM ( 61 | .clka(clk_DM), // input wire clka 62 | .addra(DM_Addr[7:2]), // input wire [5 : 0] addra 63 | .dina(D_in), // input wire [31 : 0] dina 64 | .wea(wea), // input wire [3 : 0] wea 65 | .douta(D_out) // output wire [31 : 0] douta 66 | ); 67 | 68 | SE se( 69 | .siz(siz), 70 | .SE(SE_s), 71 | .D_in(D_out), 72 | .Ex_out(RAM_out), 73 | .Low_Addr(DM_Addr[1:0]) 74 | ); 75 | endmodule 76 | -------------------------------------------------------------------------------- /CPU/RegFile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Register_File(data_write,Reg_Write,rst_,clk_W,A_addr,B_addr,W_addr,A_out,B_out); 4 | input [31:0]data_write; 5 | input [4:0]A_addr,B_addr,W_addr; 6 | input Reg_Write,clk_W; 7 | input rst_; 8 | output [31:0]A_out,B_out; 9 | reg [31:0]Reg_Files[0:31]; 10 | assign A_out = Reg_Files[A_addr]; 11 | assign B_out = Reg_Files[B_addr]; 12 | 13 | integer i; 14 | 15 | always @(negedge rst_ or posedge clk_W) begin 16 | if(!rst_)begin 17 | Reg_Files[0] <= 32'h0000_0000; 18 | for(i = 1; i < 32; i = i + 1) Reg_Files[i] <= 32'h0000_0001; 19 | Reg_Files[7] <= 32'h0000_0007; 20 | Reg_Files[8] <= 32'hf7f7_f7f7; 21 | Reg_Files[9] <= 32'h37f7_f7f7; 22 | Reg_Files[29] <= 32'h8000_0002; 23 | Reg_Files[30] <= 32'hffff_ffff; 24 | Reg_Files[31] <= 32'h7fff_ffff; 25 | end else if(Reg_Write && W_addr != 5'd0)Reg_Files[W_addr] <= data_write; 26 | 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /CPU/Register.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Register(clk,rst_,Reg_write,Data_in,Reg); 4 | input clk,rst_,Reg_write; 5 | input [31:0]Data_in; 6 | output reg [31:0]Reg; 7 | always @(posedge clk or negedge rst_) 8 | begin 9 | if(!rst_) Reg <= 32'b0; 10 | else if (Reg_write) Reg <= Data_in; 11 | end 12 | endmodule -------------------------------------------------------------------------------- /CPU/TMP: -------------------------------------------------------------------------------- 1 | 00000000 2 | 01000513 3 | 00306593 4 | 03004613 5 | 010000EF 6 | 00062403 7 | 00000033 8 | 00000033 9 | 000502B3 10 | 0005E333 11 | 000073B3 12 | 0002AE03 13 | 01C383B3 14 | 00428293 15 | FFF30313 16 | 00030463 17 | FEDFF06F 18 | 00762023 19 | 00008067 20 | 00000010 21 | 00000010 22 | 00000010 23 | 00000010 24 | 00000010 25 | 00000010 26 | 00000010 27 | 00000010 28 | 00000010 29 | 00000010 30 | 00000010 31 | 00000010 32 | 00000010 33 | 00000010 34 | 00000010 35 | 00000010 36 | 00000010 37 | 00000010 38 | 00000010 39 | 00000010 40 | 00000010 41 | 00000010 42 | 00000010 43 | 00000010 44 | 00000010 45 | 00000010 46 | 00000010 47 | 00000010 48 | 00000010 49 | 00000010 50 | 00000010 51 | 00000010 52 | 00000010 53 | 00000010 54 | 00000010 55 | 00000010 56 | 00000010 57 | 00000010 58 | 00000010 59 | 00000010 60 | 00000010 61 | 00000010 62 | 00000010 63 | 00000010 64 | 00000010; 65 | -------------------------------------------------------------------------------- /CPU/TOP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module TOP(rst_, clk, clk_100m, switch, AN, Seg, Led, wea); 4 | input rst_, clk, clk_100m; 5 | input [2:0]switch; 6 | output [3:0]wea; 7 | output [7:0]AN; 8 | output [7:0]Seg; 9 | output [5:0]Led; 10 | 11 | wire [31:0] pc, ir, mdr, W_data, F, RAM_out, D_in, D_out; 12 | wire ZF, SF, CF, OF; 13 | wire [1:0] siz; 14 | CPU cpu( 15 | .rst_(rst_), 16 | .clk(~clk), 17 | .mdr(mdr), 18 | .ir(ir), 19 | .pc(pc), 20 | .W_data(W_data), 21 | .ZF(ZF), 22 | .SF(SF), 23 | .CF(CF), 24 | .OF(OF), 25 | .F(F), 26 | .RAM_out(RAM_out), 27 | .wea(wea), 28 | .D_in(D_in), 29 | .D_out(D_out), 30 | .Size_s(siz) 31 | ); 32 | 33 | assign Led [5:0] = {ZF, SF, CF, OF, siz}; 34 | 35 | reg [31:0] data_out; 36 | always @(*) begin 37 | case (switch) 38 | 3'b000: data_out = pc; 39 | 3'b001: data_out = ir; 40 | 3'b010: data_out = mdr; 41 | 3'b011: data_out = W_data; 42 | 3'b100: data_out = F; 43 | 3'b101: data_out = RAM_out; 44 | 3'b110: data_out = D_in; 45 | 3'b111: data_out = D_out; 46 | endcase 47 | end 48 | 49 | scan_data scan_data( 50 | .reset(rst_), 51 | .data(data_out), 52 | .clk(clk_100m), 53 | .AN(AN), 54 | .seg(Seg) 55 | ); 56 | 57 | endmodule 58 | 59 | module CPU(rst_, clk, pc, mdr, ir, W_data, ZF, SF, CF, OF, F, RAM_out, wea, D_in, D_out, Size_s); 60 | input rst_, clk; 61 | 62 | output wire CF, OF, ZF, SF; 63 | wire [3:0] ALU_OP; 64 | wire PC_Write, PC0_Write, IR_Write, Reg_Write, Mem_write; 65 | wire SE_s; 66 | output [1:0] Size_s; 67 | wire [1:0] PC_s; // 0: PC + 4, 1: PC0 + imm, 2: F 68 | wire rs2_imm_s; // 0: rs2, 1: imm 69 | wire [2:0] w_data_s; // 0: F, 1: imm, 2: MDR, 3: PC, 4: PC0 + imm 70 | wire [6:0]opcode; 71 | wire [2:0]func3; 72 | wire [6:0]func7; 73 | 74 | CU cu( 75 | .rst_(rst_), 76 | .clk(clk), 77 | .opcode(opcode), 78 | .func3(func3), 79 | .func7(func7), 80 | .CF(CF), 81 | .OF(OF), 82 | .ZF(ZF), 83 | .SF(SF), 84 | .ALU_OP(ALU_OP), 85 | .PC_Write(PC_Write), 86 | .PC0_Write(PC0_Write), 87 | .IR_Write(IR_Write), 88 | .Reg_Write(Reg_Write), 89 | .Mem_write(Mem_write), 90 | .SE_s(SE_s), 91 | .Size_s(Size_s), 92 | .PC_s(PC_s), 93 | .rs2_imm_s(rs2_imm_s), 94 | .w_data_s(w_data_s), 95 | .st(wea) 96 | ); 97 | 98 | 99 | output [31:0]pc; 100 | wire [31:0]pc0; 101 | output [31:0]ir; 102 | wire [4:0]rs1, rs2, rd; 103 | 104 | wire [31:0]imm; 105 | 106 | wire [31:0] pc_in; 107 | wire [31:0]inst_code; 108 | output wire [31:0]W_data; 109 | wire [31:0] R_Data_A, R_Data_B; 110 | wire [31:0] A,B; 111 | wire [31:0] ALU_B; 112 | assign ALU_B = rs2_imm_s ? imm : B; 113 | wire [31:0] res; 114 | wire _ZF, _SF, _CF, _OF; 115 | output [31:0] F; 116 | assign pc_in = (PC_s == 0) ? pc + 4 : (PC_s == 1) ? pc0 + imm : (PC_s == 2) ? F : 32'h0000_0000; 117 | 118 | Register PC( 119 | .clk(~clk), 120 | .rst_(rst_), 121 | .Reg_write(PC_Write), 122 | .Data_in(pc_in), 123 | .Reg(pc) 124 | ); 125 | 126 | Register PC0( 127 | .clk(~clk), 128 | .rst_(rst_), 129 | .Reg_write(PC0_Write), 130 | .Data_in(pc), 131 | .Reg(pc0) 132 | ); 133 | 134 | 135 | ROM IM ( 136 | .clka(clk), // input wire clka 137 | .addra(pc[8:2]), // input wire [6 : 0] addra 138 | .douta(inst_code) // output wire [31 : 0] douta 139 | ); 140 | 141 | 142 | Register IR ( 143 | .clk(~clk), 144 | .rst_(rst_), 145 | .Reg_write(IR_Write), 146 | .Data_in(inst_code), 147 | .Reg(ir) 148 | ); 149 | 150 | ID1 id1( 151 | .inst(ir), 152 | .rs1(rs1), 153 | .rs2(rs2), 154 | .rd(rd), 155 | .opcode(opcode), 156 | .func3(func3), 157 | .func7(func7), 158 | .imm(imm) 159 | ); 160 | 161 | //regfile + alu 162 | Register_File reg_files( 163 | .data_write(W_data), 164 | .Reg_Write(Reg_Write), 165 | .rst_(rst_), 166 | .clk_W(~clk), 167 | .A_addr(rs1), 168 | .B_addr(rs2), 169 | .W_addr(rd), 170 | .A_out(R_Data_A), 171 | .B_out(R_Data_B) 172 | ); 173 | 174 | Register RA( 175 | .clk(~clk), 176 | .rst_(rst_), 177 | .Reg_write(1), 178 | .Data_in(R_Data_A), 179 | .Reg(A) 180 | ); 181 | 182 | Register RB( 183 | .clk(~clk), 184 | .rst_(rst_), 185 | .Reg_write(1), 186 | .Data_in(R_Data_B), 187 | .Reg(B) 188 | ); 189 | 190 | ALU alu( 191 | .OP(ALU_OP), 192 | .A(A), 193 | .B(ALU_B), 194 | .F(res), 195 | .ZF(_ZF), 196 | .SF(_SF), 197 | .CF(_CF), 198 | .OF(_OF) 199 | ); 200 | 201 | Register RF( 202 | .clk(~clk), 203 | .rst_(rst_), 204 | .Reg_write(1), 205 | .Data_in(res), 206 | .Reg(F) 207 | ); 208 | 209 | Register flag_register( 210 | .clk(~clk), 211 | .rst_(rst_), 212 | .Reg_write(1), 213 | .Data_in({28'b0,_ZF,_SF,_CF,_OF}), 214 | .Reg({ZF,SF,CF,OF}) 215 | ); 216 | 217 | output [31:0]RAM_out; 218 | output wire [31:0] mdr; 219 | 220 | assign W_data = (w_data_s == 0) ? F : 221 | (w_data_s == 1) ? imm : 222 | (w_data_s == 2) ? mdr : 223 | (w_data_s == 3) ? pc : 224 | (w_data_s == 4) ? pc0 + imm 225 | : 32'h0000_0000; 226 | 227 | output [3:0] wea; 228 | 229 | output [31:0] D_out, D_in; 230 | RAM ram ( 231 | .clk_DM(clk), 232 | .DM_Addr({F[5:0],2'b0}), 233 | .RAM_Write(Mem_write), 234 | .siz(Size_s), 235 | .SE_s(SE_s), 236 | .RAM_in(B), 237 | .RAM_out(RAM_out), 238 | .D_in(D_in), 239 | .D_out(D_out) 240 | ); 241 | 242 | Register MDR ( 243 | .clk(~clk), 244 | .rst_(rst_), 245 | .Reg_write(1), 246 | .Data_in(RAM_out), 247 | .Reg(mdr) 248 | ); 249 | endmodule 250 | -------------------------------------------------------------------------------- /CPU/Tube.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module scan_data(reset,data,clk,AN,seg); 4 | output [7:0]AN; 5 | output [7:0]seg; 6 | input reset; 7 | input clk; 8 | input [31:0]data; 9 | wire clk_5ms; 10 | reg [2:0]select = 0; 11 | Fdiv utt(reset,32'd50000,clk,clk_5ms); 12 | 13 | always @(posedge clk_5ms or negedge reset) begin 14 | if(!reset)begin 15 | select <= 3'd0; 16 | end 17 | else begin 18 | select <= select + 3'd1; 19 | end 20 | end 21 | 22 | reg [3:0]data_in; 23 | show sh(data_in,select,AN,seg); 24 | always @(*) begin 25 | case (select) 26 | 7: data_in = data[31:28]; 27 | 6: data_in = data[27:24]; 28 | 5: data_in = data[23:20]; 29 | 4: data_in = data[19:16]; 30 | 3: data_in = data[15:12]; 31 | 2: data_in = data[11:8]; 32 | 1: data_in = data[7:4]; 33 | 0: data_in = data[3:0]; 34 | endcase 35 | end 36 | endmodule 37 | 38 | 39 | module show(data,seletct,AN,seg); 40 | input [3:0]data; 41 | input [2:0]seletct; 42 | output reg[7:0]AN; 43 | output reg [7:0]seg; 44 | 45 | always @(*) begin 46 | case(seletct) 47 | 0:AN = 8'b11111110; 48 | 1:AN = 8'b11111101; 49 | 2:AN = 8'b11111011; 50 | 3:AN = 8'b11110111; 51 | 4:AN = 8'b11101111; 52 | 5:AN = 8'b11011111; 53 | 6:AN = 8'b10111111; 54 | 7:AN = 8'b01111111; 55 | default: AN = 8'Hff; 56 | endcase 57 | end 58 | 59 | always @(*) begin 60 | case (data) 61 | 0:seg = 8'b00000011; 62 | 1:seg = 8'b10011111; 63 | 2:seg = 8'b00100101; 64 | 3:seg = 8'b00001101; 65 | 4:seg = 8'b10011001; 66 | 5:seg = 8'b01001001; 67 | 6:seg = 8'b01000001; 68 | 7:seg = 8'b00011111; 69 | 8:seg = 8'b00000001; 70 | 9:seg = 8'b00001001; 71 | 10:seg = 8'b00010001; 72 | 11:seg = 8'b11000001; 73 | 12:seg = 8'b01100011; 74 | 13:seg = 8'b10000101; 75 | 14:seg = 8'b01100001; 76 | 15:seg = 8'b01110001; 77 | default:seg = 8'Hff; 78 | endcase 79 | end 80 | endmodule -------------------------------------------------------------------------------- /CPU/ip.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector=01000F93 000F9D03 004F9D83 01BF9023 01AF9223 000FAD03 004FAD83 01BD0E33 01C02823 01002E83 00800F93 000F8D03 004F8D83 01BF8023 01AF8223 000FAD03 004FAD83 01BD0E33 01C02823 01002E83 01000F93 000FDD03 004FDD83 01BF9023 01AF9223 000FAD03 004FAD83 01BD0E33 01C02823 01002E83 00800F93 000FCD03 004FCD83 01BF8023 01AF8223 000FAD03 004FAD83 01BD0E33 01C02823 01002E83 87600093 00400113 002081B3 40208233 002092B3 0020D333 4020D3B3 0020A433 0020B4B3 0062F533 0062E5B3 0062C633 800006B7 FFF68713 12370793 00379813 0037D893 4037D913 FFF92993 FFF93A13 00192A93 00193B13 0FF67B93 0FF66B93 00010C37 FFFC0C13 FFFC4C93 00200093 FFF08093 04010463 00D74863 00E6C663 00000093 00000093 00E6D863 00D6D663 00000093 00000093 00E6E863 00D76663 00000093 00000093 00D77863 00D6F663 00000093 00000093 FA101CE3 00000093 23000097 00000093; 3 | -------------------------------------------------------------------------------- /CPU/ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 00000000 4 | 01000513 5 | 00306593 6 | 03004613 7 | 010000EF 8 | 00062403 9 | 00000033 10 | 00000033 11 | 000502B3 12 | 0005E333 13 | 000073B3 14 | 0002AE03 15 | 01C383B3 16 | 00428293 17 | FFF30313 18 | 00030463 19 | FEDFF06F 20 | 00762023 21 | 00008067 22 | 00000010 23 | 00000010 24 | 00000010 25 | 00000010 26 | 00000010 27 | 00000010 28 | 00000010 29 | 00000010 30 | 00000010 31 | 00000010 32 | 00000010 33 | 00000010 34 | 00000010 35 | 00000010 36 | 00000010 37 | 00000010 38 | 00000010 39 | 00000010 40 | 00000010 41 | 00000010 42 | 00000010 43 | 00000010 44 | 00000010 45 | 00000010 46 | 00000010 47 | 00000010 48 | 00000010 49 | 00000010 50 | 00000010 51 | 00000010 52 | 00000010 53 | 00000010 54 | 00000010 55 | 00000010 56 | 00000010 57 | 00000010 58 | 00000010 59 | 00000010 60 | 00000010 61 | 00000010 62 | 00000010 63 | 00000010 64 | 00000010 65 | 00000010 66 | 00000010; 67 | -------------------------------------------------------------------------------- /Compile/10: -------------------------------------------------------------------------------- 1 | 0x00000000 0x01000513 addi x10 x0 16 2 | 0x00000004 0x00306593 ori x11 x0 3 3 | 0x00000008 0x03004613 xori x12 x0 48 4 | 0x0000000C 0x008000EF jal x1 8 5 | 0x00000010 0x00062403 lw x8 0(x12) 6 | 0x00000014 0x000502B3 add x5 x10 x0 7 | 0x00000018 0x0005E333 or x6 x11 x0 8 | 0x0000001C 0x000073B3 and x7 x0 x0 9 | 0x00000020 0x0002AE03 lw x28 0(x5) 10 | 0x00000024 0x01C383B3 add x7 x7 x28 11 | 0x00000028 0x00428293 addi x5 x5 4 12 | 0x0000002C 0xFFF30313 addi x6 x6 -1 13 | 0x00000030 0x00030463 beq x6 x0 8 14 | 0x00000034 0xFEDFF06F jal x0 -20 15 | 0x00000038 0x00762023 sw x7 0(x12) 16 | 0x0000003C 0x00008067 jalr x0 x1 0 17 | -------------------------------------------------------------------------------- /Compile/11: -------------------------------------------------------------------------------- 1 | 0x00000000 0x01000F93 addi x31 x0 16 2 | 0x00000004 0x000F9D03 lh x26 0(x31) 3 | 0x00000008 0x004F9D83 lh x27 4(x31) 4 | 0x0000000C 0x01BF9023 sh x27 0(x31) 5 | 0x00000010 0x01AF9223 sh x26 4(x31) 6 | 0x00000014 0x000F9D03 lh x26 0(x31) 7 | 0x00000018 0x004F9D83 lh x27 4(x31) 8 | 0x0000001C 0x01BD0E33 add x28 x26 x27 9 | 0x00000020 0x01C01823 sh x28 16(x0) 10 | 0x00000024 0x01001E83 lh x29 16(x0) 11 | 0x00000028 0x00800F93 addi x31 x0 8 12 | 0x0000002C 0x000F8D03 lb x26 0(x31) 13 | 0x00000030 0x004F8D83 lb x27 4(x31) 14 | 0x00000034 0x01BF8023 sb x27 0(x31) 15 | 0x00000038 0x01AF8223 sb x26 4(x31) 16 | 0x0000003C 0x000F8D03 lb x26 0(x31) 17 | 0x00000040 0x004F8D83 lb x27 4(x31) 18 | 0x00000044 0x01BD0E33 add x28 x26 x27 19 | 0x00000048 0x01C00823 sb x28 16(x0) 20 | 0x0000004C 0x01000E83 lb x29 16(x0) 21 | 0x00000050 0x01000F93 addi x31 x0 16 22 | 0x00000054 0x000FDD03 lhu x26 0(x31) 23 | 0x00000058 0x004FDD83 lhu x27 4(x31) 24 | 0x0000005C 0x01BF9023 sh x27 0(x31) 25 | 0x00000060 0x01AF9223 sh x26 4(x31) 26 | 0x00000064 0x000FDD03 lhu x26 0(x31) 27 | 0x00000068 0x004FDD83 lhu x27 4(x31) 28 | 0x0000006C 0x01BD0E33 add x28 x26 x27 29 | 0x00000070 0x01C01823 sh x28 16(x0) 30 | 0x00000074 0x01005E83 lhu x29 16(x0) 31 | 0x00000078 0x00800F93 addi x31 x0 8 32 | 0x0000007C 0x000FCD03 lbu x26 0(x31) 33 | 0x00000080 0x004FCD83 lbu x27 4(x31) 34 | 0x00000084 0x01BF8023 sb x27 0(x31) 35 | 0x00000088 0x01AF8223 sb x26 4(x31) 36 | 0x0000008C 0x000FCD03 lbu x26 0(x31) 37 | 0x00000090 0x004FCD83 lbu x27 4(x31) 38 | 0x00000094 0x01BD0E33 add x28 x26 x27 39 | 0x00000098 0x01C00823 sb x28 16(x0) 40 | 0x0000009C 0x01004E83 lbu x29 16(x0) 41 | 0x000000A0 0x800006B7 lui x13 524288 42 | 0x000000A4 0xFFF68713 addi x14 x13 -1 43 | 0x000000A8 0x00000113 addi x2 x0 0 44 | 0x000000AC 0xFFF08093 addi x1 x1 -1 45 | 0x000000B0 0x04010463 beq x2 x0 72 46 | 0x000000B4 0x00D74863 blt x14 x13 16 47 | 0x000000B8 0x00E6C663 blt x13 x14 12 48 | 0x000000BC 0x00000093 addi x1 x0 0 49 | 0x000000C0 0x00000093 addi x1 x0 0 50 | 0x000000C4 0x00E6D863 bge x13 x14 16 51 | 0x000000C8 0x00D6D663 bge x13 x13 12 52 | 0x000000CC 0x00000093 addi x1 x0 0 53 | 0x000000D0 0x00000093 addi x1 x0 0 54 | 0x000000D4 0x00E6E863 bltu x13 x14 16 55 | 0x000000D8 0x00D76663 bltu x14 x13 12 56 | 0x000000DC 0x00000093 addi x1 x0 0 57 | 0x000000E0 0x00000093 addi x1 x0 0 58 | 0x000000E4 0x00D77863 bgeu x14 x13 16 59 | 0x000000E8 0x00D6F663 bgeu x13 x13 12 60 | 0x000000EC 0x00000093 addi x1 x0 0 61 | 0x000000F0 0x00000093 addi x1 x0 0 62 | 0x000000F4 0xFA101CE3 bne x0 x1 -72 63 | 0x000000F8 0x00000093 addi x1 x0 0 64 | 0x000000FC 0x23000097 auipc x1 143360 65 | 0x00000100 0x00000093 addi x1 x0 0 66 | -------------------------------------------------------------------------------- /Compile/8: -------------------------------------------------------------------------------- 1 | 0x00000000 0x87600093 addi x1 x0 -1930 2 | 0x00000004 0x00400113 addi x2 x0 4 3 | 0x00000008 0x002081B3 add x3 x1 x2 4 | 0x0000000C 0x40208233 sub x4 x1 x2 5 | 0x00000010 0x002092B3 sll x5 x1 x2 6 | 0x00000014 0x0020D333 srl x6 x1 x2 7 | 0x00000018 0x4020D3B3 sra x7 x1 x2 8 | 0x0000001C 0x0020A433 slt x8 x1 x2 9 | 0x00000020 0x0020B4B3 sltu x9 x1 x2 10 | 0x00000024 0x0062F533 and x10 x5 x6 11 | 0x00000028 0x0062E5B3 or x11 x5 x6 12 | 0x0000002C 0x0062C633 xor x12 x5 x6 13 | 0x00000030 0x800006B7 lui x13 524288 14 | 0x00000034 0xFFF68713 addi x14 x13 -1 15 | 0x00000038 0x12370793 addi x15 x14 291 16 | 0x0000003C 0x00379813 slli x16 x15 3 17 | 0x00000040 0x0037D893 srli x17 x15 3 18 | 0x00000044 0x4037D913 srai x18 x15 3 19 | 0x00000048 0xFFF92993 slti x19 x18 -1 20 | 0x0000004C 0xFFF93A13 sltiu x20 x18 -1 21 | 0x00000050 0x00192A93 slti x21 x18 1 22 | 0x00000054 0x00193B13 sltiu x22 x18 1 23 | 0x00000058 0x0FF67B93 andi x23 x12 255 24 | 0x0000005C 0x0FF66B93 ori x23 x12 255 25 | 0x00000060 0x00010C37 lui x24 16 26 | 0x00000064 0xFFFC0C13 addi x24 x24 -1 27 | 0x00000068 0xFFFC4C93 xori x25 x24 -1 28 | -------------------------------------------------------------------------------- /Compile/9: -------------------------------------------------------------------------------- 1 | 0x00000000 0x01000F93 addi x31 x0 16 2 | 0x00000004 0x000FAD03 lw x26 0(x31) 3 | 0x00000008 0x004FAD83 lw x27 4(x31) 4 | 0x0000000C 0x01BFA023 sw x27 0(x31) 5 | 0x00000010 0x01AFA223 sw x26 4(x31) 6 | 0x00000014 0x000FAD03 lw x26 0(x31) 7 | 0x00000018 0x004FAD83 lw x27 4(x31) 8 | 0x0000001C 0x01BD0E33 add x28 x26 x27 9 | 0x00000020 0x01C02823 sw x28 16(x0) 10 | 0x00000024 0x01002E83 lw x29 16(x0) 11 | 0x00000028 0x87600093 addi x1 x0 -1930 12 | 0x0000002C 0x00400113 addi x2 x0 4 13 | 0x00000030 0x002081B3 add x3 x1 x2 14 | 0x00000034 0x40208233 sub x4 x1 x2 15 | 0x00000038 0x002092B3 sll x5 x1 x2 16 | 0x0000003C 0x0020D333 srl x6 x1 x2 17 | 0x00000040 0x4020D3B3 sra x7 x1 x2 18 | 0x00000044 0x0020A433 slt x8 x1 x2 19 | 0x00000048 0x0020B4B3 sltu x9 x1 x2 20 | 0x0000004C 0x0062F533 and x10 x5 x6 21 | 0x00000050 0x0062E5B3 or x11 x5 x6 22 | 0x00000054 0x0062C633 xor x12 x5 x6 23 | 0x00000058 0x800006B7 lui x13 524288 24 | 0x0000005C 0xFFF68713 addi x14 x13 -1 25 | 0x00000060 0x12370793 addi x15 x14 291 26 | 0x00000064 0x00379813 slli x16 x15 3 27 | 0x00000068 0x0037D893 srli x17 x15 3 28 | 0x0000006C 0x4037D913 srai x18 x15 3 29 | 0x00000070 0xFFF92993 slti x19 x18 -1 30 | 0x00000074 0xFFF93A13 sltiu x20 x18 -1 31 | 0x00000078 0x00192A93 slti x21 x18 1 32 | 0x0000007C 0x00193B13 sltiu x22 x18 1 33 | 0x00000080 0x0FF67B93 andi x23 x12 255 34 | 0x00000084 0x0FF66B93 ori x23 x12 255 35 | 0x00000088 0x00010C37 lui x24 16 36 | 0x0000008C 0xFFFC0C13 addi x24 x24 -1 37 | 0x00000090 0xFFFC4C93 xori x25 x24 -1 38 | -------------------------------------------------------------------------------- /Compile/acc.s: -------------------------------------------------------------------------------- 1 | .data 2 | .word 0x100,0x101,0x102,0x103,0x104,0x105,0x106,0x107,0x108,0x109,0x110,0x111,0x112 3 | .text 4 | main: 5 | add t0, x0, x0 6 | li t1, 0x10000000 7 | addi t2, x0, 10 8 | L1: lw t3, 0x0(t1) 9 | add t0, t0, t3 10 | addi t1, t1, 4 11 | addi t2, t2, -1 12 | beq t2, x0, L2 13 | j L1 14 | L2: li t1, 0x10000000 15 | sw t0, 0x80(t1) 16 | ret 17 | 18 | -------------------------------------------------------------------------------- /Compile/coe.txt: -------------------------------------------------------------------------------- 1 | 002081B3,00209233,01211293,F9C08313,05208313,07802103,06202223,34422137,FC3117E3,F841CEE3,00200067,326073EF; -------------------------------------------------------------------------------- /Compile/exam10.s: -------------------------------------------------------------------------------- 1 | .text 2 | main: 3 | addi a0, x0, 0x10 #a0=0000_0010H，数据区域（数组）首址 4 | ori a1, x0, 3 #a1=0000_0003H，累加的数据个数 5 | xori a2, x0, 0x30 #a2=0000_0030H，累加和存放的单元 6 | jal BankSum #子程序调用 7 | lw s0, 0(a2) #读出累加和 8 | BankSum: 9 | add t0, a0, x0 #t0=数据区域首址 10 | or t1, a1, x0 #t1=计数器，初始为累加的数据个数 11 | and t2, x0, x0 #t2=累加和，初始清零 12 | L: lw t3, 0(t0) #t3=取出数据 13 | add t2, t2, t3 #累加 14 | addi t0, t0, 4 #移动数据区指针 15 | addi t1, t1, -1 #计数器-1 16 | beq t1, x0, exit #计数值=0，累加完成，退出循环 17 | j L #计数值≠0，继续累加，跳转至循环体首部 18 | exit: sw t2, 0(a2) #累加和，存到指定单元 19 | jr ra #子程序返回 20 | -------------------------------------------------------------------------------- /Compile/exam11.s: -------------------------------------------------------------------------------- 1 | .text 2 | 3 | 4 | BHtest: 5 | # test lh 6 | addi x31,x0,16 #x31=16 7 | lh x26,0(x31) #x26=DMem16[16] 8 | lh x27,4(x31) #x27=DMem16[20] 9 | sh x27,0(x31) #DMem16[16]=x27 10 | sh x26,4(x31) #DMem16[20]=x26 11 | lh x26,0(x31) #x26=DMem16[16] 12 | lh x27,4(x31) #x27=DMem16[20] 13 | add x28,x26,x27 #x28=x26+x27 14 | sh x28,16(x0) #DMem16[16]=x28 15 | lh x29,16(x0) #x29=DMem16[16] 16 | 17 | # test lb 18 | addi x31,x0,8 #x31=8 19 | lb x26,0(x31) #x26=DMem[8] 20 | lb x27,4(x31) #x27=DMem[12] 21 | sb x27,0(x31) #DMem[8]=x27 22 | sb x26,4(x31) #DMem[12]=x26 23 | lb x26,0(x31) #x26=DMem[8] 24 | lb x27,4(x31) #x27=DMem[12] 25 | add x28,x26,x27 #x28=x26+x27 26 | sb x28,16(x0) #DMem[8]=x28 27 | lb x29,16(x0) #x29=DMem[8] 28 | 29 | # test lhu 30 | addi x31,x0,16 #x31=16 31 | lhu x26,0(x31) #x26=DMem16[16] 32 | lhu x27,4(x31) #x27=DMem16[20] 33 | sh x27,0(x31) #DMem16[16]=x27 34 | sh x26,4(x31) #DMem16[20]=x26 35 | lhu x26,0(x31) #x26=DMem16[16] 36 | lhu x27,4(x31) #x27=DMem16[20] 37 | add x28,x26,x27 #x28=x26+x27 38 | sh x28,16(x0) #DMem16[16]=x28 39 | lhu x29,16(x0) #x29=DMem16[16] 40 | 41 | #test lbu 42 | addi x31,x0,8 #x31=8 43 | lbu x26,0(x31) #x26=DMem[8] 44 | lbu x27,4(x31) #x27=DMem[12] 45 | sb x27,0(x31) #DMem[8]=x27 46 | sb x26,4(x31) #DMem[12]=x26 47 | lbu x26,0(x31) #x26=DMem[8] 48 | lbu x27,4(x31) #x27=DMem[12] 49 | add x28,x26,x27 #x28=x26+x27 50 | sb x28,16(x0) #DMem[8]=x28 51 | lbu x29,16(x0) #x29=DMem[8] 52 | 53 | Itest: 54 | lui x13,0x80000 #x13=0x8000_0000 55 | addi x14,x13,-1 #x14=0x7FFF_FFFF 56 | addi x2,x0,0 #x2=0 57 | 58 | Jtest: 59 | addi x1,x1,-1 #x1 = x1 - 1 60 | beq x2,x0,exit #stop test 61 | blt x14,x13,nxt1 #if 0x7FFF_FFFF < 0x8000_0000 jump to nxt1 (false) 62 | blt x13,x14,nxt1 #if 0x8000_0000 < 0x7FFF_FFFF jump to nxt1 (true) 63 | addi x1,x0,0 # do nothing 64 | addi x1,x0,0 # do nothing 65 | 66 | nxt1: 67 | bge x13,x14,nxt2 #if 0x8000_0000 >= 0x7FFF_FFFF jump to nxt2(falase) 68 | bge x13,x13,nxt2 #if 0x8000_0000 = 0x8000_0000 jump to nxt2(true) 69 | 70 | 71 | addi x1,x0,0 # do nothing 72 | addi x1,x0,0 # do nothing 73 | nxt2: 74 | bltu x13,x14, nxt3 #if U(0x8000_0000) < U(0x7FFF_FFFF) jump to nxt3(flase) 75 | bltu x14,x13, nxt3 #if U(0x7FFF_FFFF) < U(0x8000_0000) jump to nxt3(true) 76 | 77 | addi x1,x0,0 # do nothing 78 | addi x1,x0,0 # do nothing 79 | nxt3: 80 | bgeu x14,x13, nxt4 #if U(0x7FFF_FFFF) >= U(0x8000_0000) jump to nxt4(false) 81 | bgeu x13,x13, nxt4 #if U(0x8000_0000) == U(0x8000_0000) jump to nxt4(true) 82 | 83 | addi x1,x0,0 # do nothing 84 | addi x1,x0,0 # do nothing 85 | nxt4: 86 | bne x0,x1,Jtest #if x1 != 0, jump Jtest 87 | 88 | exit: 89 | addi x1,x0,0 #x1 = 0 90 | auipc x1,0x23000 #x1 = 0x23000 + PC 91 | addi x1,x0,0 #x1 = 0 92 | -------------------------------------------------------------------------------- /Compile/exam8.s: -------------------------------------------------------------------------------- 1 | .text 2 | main: 3 | addi x1,x0,-0x78A #x1=0xFFFF_F876 4 | addi x2,x0,4 #x2=0x0000_0004 5 | add x3,x1,x2 #x3=0xFFFF_F87A 6 | sub x4,x1,x2 #x4=0xFFFF_F872 7 | sll x5,x1,x2 #x5=0xFFFF_8760 8 | srl x6,x1,x2 #x6=0x0FFF_FF87 9 | sra x7,x1,x2 #x7=0xFFFF_FF87 10 | slt x8,x1,x2 #x8=0x0000_0001 11 | sltu x9,x1,x2 #x9=0x0000_0000 12 | and x10,x5,x6 #x10=0x0FFF_8700 13 | or x11,x5,x6 #x11=0xFFFF_FFE7 14 | xor x12,x5,x6 #x12=0xF000_78E7 15 | lui x13,0x80000 #x13=0x8000_0000 16 | addi x14,x13,-1 #x14=0x7FFF_FFFF 17 | addi x15,x14,0x123 #x15=0x8000_0122 18 | slli x16,x15,3 #x16=0x0000_0910 19 | srli x17,x15,3 #x17=0x1000_0024 20 | srai x18,x15,3 #x18=0xF000_0024 21 | slti x19,x18,-1 #x19=0x0000_0001 22 | sltiu x20,x18,-1 #x20=0x0000_0001 23 | slti x21,x18,1 #x21=0x0000_0001 24 | sltiu x22,x18,1 #x22=0x0000_0000 25 | andi x23,x12,0xFF #x23=0x0000_00E7 26 | ori x23,x12,0xFF #x23=0xF000_78FF 27 | lui x24,0x00010 #x24=0x0001_0000 28 | addi x24,x24,-1 #x24=0x0000_FFFF 29 | xori x25,x24,-1 #x25=0xFFFF_0000 30 | -------------------------------------------------------------------------------- /Compile/exam9.s: -------------------------------------------------------------------------------- 1 | .text 2 | main: 3 | addi x31,x0,16 #x31=16 4 | lw x26,0(x31) #x26=DMem[16] 5 | lw x27,4(x31) #x27=DMem[20] 6 | sw x27,0(x31) # DMem[16]=x27 7 | sw x26,4(x31) # DMem[20]=x26 8 | lw x26,0(x31) #x26=DMem[16] 9 | lw x27,4(x31) #x27=DMem[20] 10 | add x28,x26,x27 #x28= x26+ x27 11 | sw x28,16(x0) # DMem[16]=x28 12 | lw x29,16(x0) #x29=DMem[16] 13 | addi x1,x0,-0x78A #x1=0xFFFF_F876 14 | addi x2,x0,4 #x2=0x0000_0004 15 | add x3,x1,x2 #x3=0xFFFF_F87A 16 | sub x4,x1,x2 #x4=0xFFFF_F872 17 | sll x5,x1,x2 #x5=0xFFFF_8760 18 | srl x6,x1,x2 #x6=0x0FFF_FF87 19 | sra x7,x1,x2 #x7=0xFFFF_FF87 20 | slt x8,x1,x2 #x8=0x0000_0001 21 | sltu x9,x1,x2 #x9=0x0000_0000 22 | and x10,x5,x6 #x10=0x0FFF_8700 23 | or x11,x5,x6 #x11=0xFFFF_FFE7 24 | xor x12,x5,x6 #x12=0xF000_78E7 25 | lui x13,0x80000 #x13=0x8000_0000 26 | addi x14,x13,-1 #x14=0x7FFF_FFFF 27 | addi x15,x14,0x123 #x15=0x8000_0122 28 | slli x16,x15,3 #x16=0x0000_0910 29 | srli x17,x15,3 #x17=0x1000_0024 30 | srai x18,x15,3 #x18=0xF000_0024 31 | slti x19,x18,-1 #x19=0x0000_0001 32 | sltiu x20,x18,-1 #x20=0x0000_0001 33 | slti x21,x18,1 #x21=0x0000_0001 34 | sltiu x22,x18,1 #x22=0x0000_0000 35 | andi x23,x12,0xFF #x23=0x0000_00E7 36 | ori x23,x12,0xFF #x23=0xF000_78FF 37 | lui x24,0x00010 #x24=0x0001_0000 38 | addi x24,x24,-1 #x24=0x0000_FFFF 39 | xori x25,x24,-1 #x25=0xFFFF_0000 40 | -------------------------------------------------------------------------------- /Compile/move.s: -------------------------------------------------------------------------------- 1 | BankMove: 2 | add t0, a0, zero; 3 | add t1, a1, zero; 4 | add t2, a2, zero; 5 | 6 | L1: lw t3, 0(t0); 7 | sw t3 0(t1); 8 | addi t1, t1, 4; 9 | addi t2, t2, -1; 10 | bne t2, zero, L1; 11 | jr ra 12 | 13 | main: 14 | addi a0,zero,0x30; 15 | addi a1,zero,0x60; 16 | addi a2,zero,10; 17 | jal BankMove -------------------------------------------------------------------------------- /Compile/my_sum_rev.s: -------------------------------------------------------------------------------- 1 | 2 | # my_sum.o： 文件格式 elf32-littleriscv 3 | 4 | 5 | # Disassembly of section 6 | .text 7 | 8 | 00000000 : 9 | 0: 00000293 li t0,0 10 | 4: 00000313 li t1,0 11 | 8: 00150393 addi t2,a0,1 12 | 13 | 0000000c : 14 | c: 00530333 add t1,t1,t0 15 | 10: 00128293 addi t0,t0,1 16 | 14: fe729ce3 bne t0,t2,c 17 | 18: 00030513 mv a0,t1 18 | 1c: 00008067 ret 19 | 20 | 00000020
: 21 | 20: 00000517 auipc a0,0x0 22 | 24: 00050513 mv a0,a0 23 | 28: 00052503 lw a0,0(a0) # 20
24 | 2c: ff810113 addi sp,sp,-8 25 | 30: 00112023 sw ra,0(sp) 26 | 34: 00812223 sw s0,4(sp) 27 | 38: fc9ff0ef jal ra,0 28 | 3c: 00012083 lw ra,0(sp) 29 | 40: 00412403 lw s0,4(sp) 30 | 44: 00810113 addi sp,sp,8 31 | 48: 00000297 auipc t0,0x0 32 | 4c: 00028293 mv t0,t0 33 | 50: 00a2a023 sw a0,0(t0) # 48 34 | 54: 00000513 li a0,0 35 | 58: 00008067 ret -------------------------------------------------------------------------------- /Compile/sum: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/Compile/sum -------------------------------------------------------------------------------- /Compile/sum.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | int main () { 3 | int x = 0x7FFFFFFF; 4 | std::cout << x << std::endl; 5 | x = -x; 6 | for (int i = 0; i < 8; ++i) { 7 | std::cout << (x & (0xf)) << ' '; 8 | x >>= 4; 9 | } 10 | x += 0x80000000; 11 | std::cout << std::endl << x << std::endl; 12 | } -------------------------------------------------------------------------------- /Compile/sum.s: -------------------------------------------------------------------------------- 1 | .data 2 | x: .word 100 3 | y: .word 0 4 | .globl main 5 | 6 | .text 7 | 8 | # 函数定义 9 | sum: 10 | li t0, 0 11 | li t1, 0 12 | addi t2, a0 , 1 13 | Loop: 14 | add t1, t1, t0 15 | addi t0, t0, 1 16 | bne t0, t2, Loop 17 | mv a0, t1 18 | jr ra 19 | 20 | main: 21 | la a0, x 22 | lw a0, 0(a0) 23 | addi sp, sp, -8 24 | sw ra, 0(sp) 25 | sw s0, 4(sp) 26 | jal sum 27 | lw ra, 0(sp) 28 | lw s0, 4(sp) 29 | addi sp, sp, 8 30 | la t0, y 31 | sw a0, 0(t0) 32 | li a0, 0 33 | jr ra 34 | -------------------------------------------------------------------------------- /Compile/sum_c_o2_r.s: -------------------------------------------------------------------------------- 1 | 2 | # sum.o： 文件格式 elf32-littleriscv 3 | 4 | 5 | .text: 6 | 7 | 00010074
: 8 | 10074: 00000513 li a0,0 9 | 10078: 00008067 ret 10 | 11 | 0001014c : 12 | 1014c: 02054063 bltz a0,1016c 13 | 10150: 00150713 addi a4,a0,1 14 | 10154: 00000793 li a5,0 15 | 10158: 00000513 li a0,0 16 | 1015c: 00f50533 add a0,a0,a5 17 | 10160: 00178793 addi a5,a5,1 18 | 10164: fee79ce3 bne a5,a4,1015c 19 | 10168: 00008067 ret 20 | 1016c: 00000513 li a0,0 21 | 10170: 00008067 ret 22 | 23 | 00010174 : 24 | 10174: ff010113 addi sp,sp,-16 25 | 10178: 00000593 li a1,0 26 | 1017c: 00812423 sw s0,8(sp) 27 | 10180: 00112623 sw ra,12(sp) 28 | 10184: 00050413 mv s0,a0 29 | 10188: 194000ef jal ra,1031c <__call_exitprocs> 30 | 1018c: c281a503 lw a0,-984(gp) # 119b8 <_global_impure_ptr> 31 | 10190: 03c52783 lw a5,60(a0) 32 | 10194: 00078463 beqz a5,1019c 33 | 10198: 000780e7 jalr a5 34 | 1019c: 00040513 mv a0,s0 35 | 101a0: 3a4000ef jal ra,10544 <_exit> 36 | -------------------------------------------------------------------------------- /Compile/sum_c_r.s: -------------------------------------------------------------------------------- 1 | 2 | # sum_c.o： 文件格式 elf32-littleriscv 3 | 4 | 5 | .text: 6 | 7 | 00010144 : 8 | 10144: fd010113 addi sp,sp,-48 9 | 10148: 02812623 sw s0,44(sp) 10 | 1014c: 03010413 addi s0,sp,48 11 | 10150: fca42e23 sw a0,-36(s0) 12 | 10154: fe042423 sw zero,-24(s0) 13 | 10158: fe042623 sw zero,-20(s0) 14 | 1015c: 0200006f j 1017c 15 | 10160: fe842703 lw a4,-24(s0) 16 | 10164: fec42783 lw a5,-20(s0) 17 | 10168: 00f707b3 add a5,a4,a5 18 | 1016c: fef42423 sw a5,-24(s0) 19 | 10170: fec42783 lw a5,-20(s0) 20 | 10174: 00178793 addi a5,a5,1 21 | 10178: fef42623 sw a5,-20(s0) 22 | 1017c: fec42703 lw a4,-20(s0) 23 | 10180: fdc42783 lw a5,-36(s0) 24 | 10184: fce7dee3 bge a5,a4,10160 25 | 10188: fe842783 lw a5,-24(s0) 26 | 1018c: 00078513 mv a0,a5 27 | 10190: 02c12403 lw s0,44(sp) 28 | 10194: 03010113 addi sp,sp,48 29 | 10198: 00008067 ret 30 | 31 | 0001019c
: 32 | 1019c: fe010113 addi sp,sp,-32 33 | 101a0: 00112e23 sw ra,28(sp) 34 | 101a4: 00812c23 sw s0,24(sp) 35 | 101a8: 02010413 addi s0,sp,32 36 | 101ac: 06400793 li a5,100 37 | 101b0: fef42623 sw a5,-20(s0) 38 | 101b4: fec42503 lw a0,-20(s0) 39 | 101b8: f8dff0ef jal ra,10144 40 | 101bc: fea42423 sw a0,-24(s0) 41 | 101c0: 00000793 li a5,0 42 | 101c4: 00078513 mv a0,a5 43 | 101c8: 01c12083 lw ra,28(sp) 44 | 101cc: 01812403 lw s0,24(sp) 45 | 101d0: 02010113 addi sp,sp,32 46 | 101d4: 00008067 ret 47 | 48 | 000101d8 : 49 | 101d8: ff010113 addi sp,sp,-16 50 | 101dc: 00000593 li a1,0 51 | 101e0: 00812423 sw s0,8(sp) 52 | 101e4: 00112623 sw ra,12(sp) 53 | 101e8: 00050413 mv s0,a0 54 | 101ec: 194000ef jal ra,10380 <__call_exitprocs> 55 | 101f0: c281a503 lw a0,-984(gp) # 11a18 <_global_impure_ptr> 56 | 101f4: 03c52783 lw a5,60(a0) 57 | 101f8: 00078463 beqz a5,10200 58 | 101fc: 000780e7 jalr a5 59 | 10200: 00040513 mv a0,s0 60 | 10204: 3a4000ef jal ra,105a8 <_exit> 61 | -------------------------------------------------------------------------------- /Compile/test.s: -------------------------------------------------------------------------------- 1 | .text 2 | 3 | main: 4 | addi a0, zero, 0x10 #a0=0000_0010H，数据区域（数组）首址 5 | ori a1, zero, 3 #a1=0000_0003H，累加的数据个数 6 | xori a2, zero, 0x30 #a2=0000_0030H，累加和存放的单元 7 | jal BankSum #子程序调用 8 | lw s0, 0(a2) #读出累加和 9 | BankSum: 10 | add t0, a0, zero #t0=数据区域首址 11 | or t1, a1, zero #t1=计数器，初始为累加的数据个数 12 | and t2, zero, zero #t2=累加和，初始清零 13 | L: lw t3, 0(t0) #t3=取出数据 14 | add t2, t2, t3 #累加 15 | addi t0, t0, 4 #移动数据区指针 16 | addi t1, t1, -1 #计数器-1 17 | beq t1, zero, exit #计数值=0，累加完成，退出循环 18 | j L #计数值≠0，继续累加，跳转至循环体首部 19 | exit: sw t2, 0(a2) #累加和，存到指定单元 20 | jr ra #子程序返回 21 | -------------------------------------------------------------------------------- /Compile/tmp.s: -------------------------------------------------------------------------------- 1 | addi t0,x0,5 #5→t0 2 | lui t1,0x800 #800 000h→t1 3 | L1: 4 | lw t2,0(t1) #Mem32[t1+0]→t2 5 | addi t2,t2,100 #t2+100→t2 6 | sw t2,0(t1) #t2→Mem32[t1+0] 7 | addi t1,t1,4 #t1+4→t1 8 | addi t0,t0,-1 #t0-1→t0 9 | bne t0,x0,L1 #if (t0≠0) goto L1 10 | exit: -------------------------------------------------------------------------------- /IM/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/IM/.DS_Store -------------------------------------------------------------------------------- /IM/IM.srcs/constrs_1/new/top.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD LVCMOS18 [get_ports clk_100m] 2 | set_property IOSTANDARD LVCMOS18 [get_ports IR_Write] 3 | set_property IOSTANDARD LVCMOS18 [get_ports PC_Write] 4 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[15]}] 5 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[14]}] 6 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[13]}] 7 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[12]}] 8 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[11]}] 9 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[10]}] 10 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[9]}] 11 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[8]}] 12 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[7]}] 13 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[6]}] 14 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[5]}] 15 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[4]}] 16 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[3]}] 17 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[2]}] 18 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[1]}] 19 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[0]}] 20 | set_property IOSTANDARD LVCMOS18 [get_ports {Led[16]}] 21 | set_property IOSTANDARD LVCMOS18 [get_ports {switch[2]}] 22 | set_property IOSTANDARD LVCMOS18 [get_ports {switch[1]}] 23 | set_property IOSTANDARD LVCMOS18 [get_ports {switch[0]}] 24 | 25 | 26 | set_property IOSTANDARD LVCMOS18 [get_ports clk_100M] 27 | set_property IOSTANDARD LVCMOS18 [get_ports rst_] 28 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[7]}] 29 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[6]}] 30 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[5]}] 31 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[4]}] 32 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[3]}] 33 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[2]}] 34 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[1]}] 35 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[0]}] 36 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[7]}] 37 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[6]}] 38 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[5]}] 39 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[4]}] 40 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[3]}] 41 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[2]}] 42 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[1]}] 43 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[0]}] 44 | 45 | set_property PACKAGE_PIN C9 [get_ports {AN[7]}] 46 | set_property PACKAGE_PIN C10 [get_ports {AN[6]}] 47 | set_property PACKAGE_PIN D10 [get_ports {AN[5]}] 48 | set_property PACKAGE_PIN C11 [get_ports {AN[4]}] 49 | set_property PACKAGE_PIN M17 [get_ports {AN[3]}] 50 | set_property PACKAGE_PIN J14 [get_ports {AN[2]}] 51 | set_property PACKAGE_PIN K13 [get_ports {AN[1]}] 52 | set_property PACKAGE_PIN P14 [get_ports {AN[0]}] 53 | set_property PACKAGE_PIN F14 [get_ports {Seg[7]}] 54 | set_property PACKAGE_PIN N14 [get_ports {Seg[6]}] 55 | set_property PACKAGE_PIN J13 [get_ports {Seg[5]}] 56 | set_property PACKAGE_PIN G13 [get_ports {Seg[4]}] 57 | set_property PACKAGE_PIN F13 [get_ports {Seg[3]}] 58 | set_property PACKAGE_PIN G14 [get_ports {Seg[2]}] 59 | set_property PACKAGE_PIN M13 [get_ports {Seg[1]}] 60 | set_property PACKAGE_PIN H14 [get_ports {Seg[0]}] 61 | 62 | set_property PACKAGE_PIN E3 [get_ports clk_100m] 63 | set_property PACKAGE_PIN N17 [get_ports rst_] 64 | 65 | set_property PACKAGE_PIN V5 [get_ports IR_Write] 66 | set_property PACKAGE_PIN T4 [get_ports PC_Write] 67 | 68 | set_property IOSTANDARD LVCMOS18 [get_ports clk_im] 69 | set_property PACKAGE_PIN U17 [get_ports clk_im] 70 | set_property PACKAGE_PIN V15 [get_ports {switch[2]}] 71 | set_property PACKAGE_PIN R15 [get_ports {switch[1]}] 72 | set_property PACKAGE_PIN U16 [get_ports {switch[0]}] 73 | set_property PACKAGE_PIN U6 [get_ports {Led[16]}] 74 | set_property PACKAGE_PIN R5 [get_ports {Led[15]}] 75 | set_property PACKAGE_PIN U7 [get_ports {Led[14]}] 76 | set_property PACKAGE_PIN R6 [get_ports {Led[13]}] 77 | set_property PACKAGE_PIN R7 [get_ports {Led[12]}] 78 | set_property PACKAGE_PIN U8 [get_ports {Led[11]}] 79 | set_property PACKAGE_PIN T8 [get_ports {Led[10]}] 80 | set_property PACKAGE_PIN V9 [get_ports {Led[9]}] 81 | set_property PACKAGE_PIN T10 [get_ports {Led[8]}] 82 | set_property PACKAGE_PIN V11 [get_ports {Led[7]}] 83 | set_property PACKAGE_PIN T11 [get_ports {Led[6]}] 84 | set_property PACKAGE_PIN V12 [get_ports {Led[5]}] 85 | set_property PACKAGE_PIN R12 [get_ports {Led[4]}] 86 | set_property PACKAGE_PIN U13 [get_ports {Led[3]}] 87 | set_property PACKAGE_PIN R13 [get_ports {Led[2]}] 88 | set_property PACKAGE_PIN U14 [get_ports {Led[1]}] 89 | set_property PACKAGE_PIN T15 [get_ports {Led[0]}] 90 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_im_IBUF] 91 | -------------------------------------------------------------------------------- /IM/IM.srcs/sim_1/new/simu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module simu(); 4 | 5 | // module IF(IR_Write, PC_Write, clk_im, pc, ir); 6 | 7 | reg IR_Write, PC_Write, clk_im, rst_; 8 | wire [31:0]pc; 9 | wire [31:0]inst; 10 | IF if0( 11 | .rst_(rst_), 12 | .IR_Write(IR_Write), 13 | .PC_Write(PC_Write), 14 | .clk_im(clk_im), 15 | .pc(pc), 16 | .ir(inst) 17 | ); 18 | always @(*) begin 19 | #10 20 | clk_im <= ~clk_im; 21 | end 22 | 23 | initial begin 24 | clk_im = 1; 25 | IR_Write = 0; 26 | PC_Write = 0; 27 | rst_ = 1; 28 | #6 29 | rst_ = 0; 30 | #6 31 | rst_ = 1; 32 | PC_Write = 1; 33 | IR_Write = 1; 34 | 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /IM/IM.srcs/sources_1/new/Fdiv.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Fdiv(input reset,input[31:0] mult,input clk_1M,output reg clk_1K); 3 | reg [31:0]counter; 4 | initial begin counter = 32'd0;end 5 | initial begin clk_1K = 0;end 6 | always @(posedge clk_1M or negedge reset) begin 7 | if(!reset)begin 8 | counter <= 32'd0; 9 | clk_1K <= 1'b0; 10 | end 11 | else if(counter == mult) begin 12 | clk_1K <= ~clk_1K; 13 | counter <= 32'd0; 14 | end 15 | else begin 16 | counter <= counter + 1'b1; 17 | end 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /IM/IM.srcs/sources_1/new/ID.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ID1(inst, rs1, rs2, rd, opcode, func3, func7, imm); 4 | input [31:0]inst; 5 | output [4:0]rs1, rs2, rd; 6 | output [6:0]opcode; 7 | output [2:0]func3; 8 | output [6:0]func7; 9 | output reg[31:0]imm; 10 | wire [31:0]I_shift, I_imm, S_imm, B_imm, U_imm, J_imm; 11 | 12 | assign func7 = inst[31:25]; 13 | assign rs2 = inst[24:20]; 14 | assign rs1 = inst[19:15]; 15 | assign func3 = inst[14:12]; 16 | assign rd = inst[11:7]; 17 | assign opcode = inst[6:0]; 18 | 19 | assign I_shift = {27'b0, inst[24:20]}; 20 | assign I_imm = {{20{inst[31]}}, inst[31:20]}; 21 | assign S_imm = {{20{inst[31]}}, inst[31:25], inst[11:7]}; 22 | // assign B_imm = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8],1'b0}; 23 | assign B_imm = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0}; 24 | assign U_imm = {inst[31:12],{12'b0}}; 25 | assign J_imm = {{12{inst[31]}}, inst[19:12], inst[20], inst[30:21], 1'b0}; 26 | assign CSR_uimm = {27'b0,inst[19:15]}; 27 | 28 | reg [3:0]type; 29 | 30 | always @(*) begin 31 | case(opcode) 32 | //R 33 | 7'b0110011: type = 4'd1; 34 | //I 35 | 7'b0010011: type = 4'd2; 36 | 7'b0000011: type = 4'd2; 37 | 7'b1100111: type = 4'd2; 38 | //U 39 | 7'b0010111: type = 4'd3; //auipc 40 | 7'b0110111: type = 4'd3; //lui 41 | //S 42 | 7'b0100011: type = 4'd4; 43 | //B 44 | 7'b1100011: type = 4'd5; 45 | //J 46 | 7'b1101111: type = 4'd6; 47 | //csr 48 | 7'b1110011: type = 4'd7; 49 | default: type = 4'd0; 50 | endcase 51 | end 52 | 53 | always @(*) begin 54 | case(type) 55 | //R 56 | 4'd1:imm = 32'b0; 57 | //I 58 | 4'd2:imm = (opcode == 7'bb0010011 && (func3 == 3'b101 || func3 == 3'b001)) ? I_shift : I_imm; 59 | //U 60 | 4'd3:imm = U_imm; 61 | //S 62 | 4'd4:imm = S_imm; 63 | //B 64 | 4'd5:imm = B_imm; 65 | //J 66 | 4'd6:imm = J_imm; 67 | //csr 68 | 4'd7:imm = CSR_uimm; 69 | default: imm = 32'b0; 70 | endcase 71 | end 72 | endmodule 73 | 74 | module ID2(opcode, func3, func7, ALU_OP, IS_R, IS_IMM, IS_LUI, IS_S, IS_B, IS_J, IS_CSR, IS_L, IS_AUIPC, IS_JALR); 75 | input [6:0]opcode; 76 | input [2:0]func3; 77 | input [6:0]func7; 78 | output reg[6:0]ALU_OP; 79 | output IS_R, IS_IMM, IS_LUI, IS_S, IS_B, IS_J, IS_CSR, IS_L, IS_AUIPC, IS_JALR; 80 | 81 | assign IS_R = (opcode == 7'b0110011); 82 | assign IS_IMM = (opcode == 7'b0010011); 83 | assign IS_L = (opcode == 7'b0000011); 84 | assign IS_LUI = (opcode == 7'b0110111); 85 | assign IS_S = (opcode == 7'b0100011); 86 | assign IS_B = (opcode == 7'b1100011); 87 | assign IS_J = (opcode == 7'b1101111); 88 | assign IS_JALR = (opcode == 7'b1100111); 89 | assign IS_CSR = (opcode == 7'b1110011); 90 | assign IS_AUIPC = (opcode == 7'b0010111); 91 | 92 | always @(*) begin 93 | if (IS_R) ALU_OP = {func7[5], func3}; 94 | else if (IS_IMM) ALU_OP = (func3 == 3'b101) ? {func7[5], func3} : {1'b0, func3}; 95 | else if (IS_B) ALU_OP = 4'b1000; 96 | else ALU_OP = 4'b0000; 97 | end 98 | 99 | 100 | 101 | endmodule -------------------------------------------------------------------------------- /IM/IM.srcs/sources_1/new/IF.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module IF(IR_Write, PC_Write, clk_im, pc, ir, rs1, rs2, rd, opcode, func3, func7, imm); 4 | input IR_Write, PC_Write, clk_im; 5 | output [4:0]rs1, rs2, rd; 6 | output [6:0]opcode; 7 | output [2:0]func3; 8 | output [6:0]func7; 9 | output [31:0]imm; 10 | output [31:0]pc; 11 | output [31:0]ir; 12 | 13 | 14 | 15 | Reg PC( 16 | .clk(~clk_im), 17 | .rst_(1'b1), 18 | .Reg_write(PC_Write), 19 | .Data_in(pc + 4), 20 | .Reg(pc) 21 | ); 22 | 23 | wire [31:0]inst_code; 24 | 25 | ROM IM ( 26 | .clka(clk_im), // input wire clka 27 | .addra(pc[7:2]), // input wire [5 : 0] addra 28 | .wea(4'b1111), // input wire [3 : 0] wea 29 | .douta(inst_code) // output wire [31 : 0] douta 30 | ); 31 | 32 | 33 | Reg IR ( 34 | .clk(clk_im), 35 | .rst_(1'b1), 36 | .Reg_write(IR_Write), 37 | .Data_in(inst_code), 38 | .Reg(ir) 39 | ); 40 | 41 | ID1 id1( 42 | .inst(ir), 43 | .rs1(rs1), 44 | .rs2(rs2), 45 | .rd(rd), 46 | .opcode(opcode), 47 | .func3(func3), 48 | .func7(func7), 49 | .imm(imm) 50 | ); 51 | endmodule -------------------------------------------------------------------------------- /IM/IM.srcs/sources_1/new/Register.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Register(clk,rst_,Reg_write,Data_in,Reg); 3 | input clk,rst_,Reg_write; 4 | input [31:0]Data_in; 5 | output reg [31:0]Reg; 6 | always @(posedge clk or negedge rst_) 7 | begin 8 | if(!rst_) Reg <= 32'b0; 9 | else if (Reg_write) Reg <= Data_in; 10 | end 11 | endmodule -------------------------------------------------------------------------------- /IM/IM.srcs/sources_1/new/Top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // IF(IR_Write, PC_Write, clk_im, pc, ir, rs1, rs2, rd, opcode, func3, func7, imm) 4 | module TOP(rst_, IR_Write, PC_Write, clk_100m, clk_im, switch, AN, Seg, Led); 5 | input rst_, IR_Write, PC_Write, clk_100m, clk_im; 6 | input [2:0]switch; 7 | output [7:0]AN; 8 | output [7:0]Seg; 9 | output reg [16:0]Led; 10 | 11 | wire [31:0]pc; 12 | wire [31:0]ir; 13 | wire [4:0]rs1, rs2, rd; 14 | wire [6:0]opcode; 15 | wire [2:0]func3; 16 | wire [6:0]func7; 17 | wire [31:0]imm; 18 | 19 | 20 | 21 | IF if1( 22 | .rst_(rst_), 23 | .IR_Write(IR_Write), 24 | .PC_Write(PC_Write), 25 | .clk_im(clk_im), 26 | .pc(pc), 27 | .ir(ir) 28 | ); 29 | 30 | 31 | ID1 id1( 32 | .inst(ir), 33 | .rs1(rs1), 34 | .rs2(rs2), 35 | .rd(rd), 36 | .opcode(opcode), 37 | .func3(func3), 38 | .func7(func7), 39 | .imm(imm) 40 | ); 41 | 42 | reg [31:0]data_tube; 43 | 44 | always @(*) begin 45 | case(switch[2]) 46 | 0: Led = {rd,rs1,rs2,2'b0}; 47 | 1: Led = {opcode,func3,func7}; 48 | endcase 49 | end 50 | 51 | always @(*) begin 52 | case(switch[1:0]) 53 | 0: data_tube = imm; 54 | 1: data_tube = pc; 55 | 2: data_tube = ir; 56 | endcase 57 | end 58 | 59 | scan_data(rst_,data_tube,clk_100m,AN,Seg); 60 | endmodule -------------------------------------------------------------------------------- /IM/IM.srcs/sources_1/new/Tube.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module scan_data(reset,data,clk,AN,seg); 4 | output [7:0]AN; 5 | output [7:0]seg; 6 | input reset; 7 | input clk; 8 | input [31:0]data; 9 | wire clk_5ms; 10 | reg [2:0]select = 0; 11 | Fdiv utt(reset,32'd50000,clk,clk_5ms); 12 | 13 | always @(posedge clk_5ms or negedge reset) begin 14 | if(!reset)begin 15 | select <= 3'd0; 16 | end 17 | else begin 18 | select <= select + 3'd1; 19 | end 20 | end 21 | 22 | reg [3:0]data_in; 23 | show sh(data_in,select,AN,seg); 24 | always @(*) begin 25 | case (select) 26 | 7: data_in = data[31:28]; 27 | 6: data_in = data[27:24]; 28 | 5: data_in = data[23:20]; 29 | 4: data_in = data[19:16]; 30 | 3: data_in = data[15:12]; 31 | 2: data_in = data[11:8]; 32 | 1: data_in = data[7:4]; 33 | 0: data_in = data[3:0]; 34 | endcase 35 | end 36 | endmodule 37 | 38 | 39 | module show(data,seletct,AN,seg); 40 | input [3:0]data; 41 | input [2:0]seletct; 42 | output reg[7:0]AN; 43 | output reg [7:0]seg; 44 | 45 | always @(*) begin 46 | case(seletct) 47 | 0:AN = 8'b11111110; 48 | 1:AN = 8'b11111101; 49 | 2:AN = 8'b11111011; 50 | 3:AN = 8'b11110111; 51 | 4:AN = 8'b11101111; 52 | 5:AN = 8'b11011111; 53 | 6:AN = 8'b10111111; 54 | 7:AN = 8'b01111111; 55 | default: AN = 8'Hff; 56 | endcase 57 | end 58 | 59 | always @(*) begin 60 | case (data) 61 | 0:seg = 8'b00000011; 62 | 1:seg = 8'b10011111; 63 | 2:seg = 8'b00100101; 64 | 3:seg = 8'b00001101; 65 | 4:seg = 8'b10011001; 66 | 5:seg = 8'b01001001; 67 | 6:seg = 8'b01000001; 68 | 7:seg = 8'b00011111; 69 | 8:seg = 8'b00000001; 70 | 9:seg = 8'b00001001; 71 | 10:seg = 8'b00010001; 72 | 11:seg = 8'b11000001; 73 | 12:seg = 8'b01100011; 74 | 13:seg = 8'b10000101; 75 | 14:seg = 8'b01100001; 76 | 15:seg = 8'b01110001; 77 | default:seg = 8'Hff; 78 | endcase 79 | end 80 | endmodule -------------------------------------------------------------------------------- /IM/IM.srcs/sources_1/new/button.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module Test_button(clk,in,out1,out); 5 | input clk; 6 | output reg[15:0]out = 0; 7 | output out1; 8 | input in; 9 | 10 | wire clk100us; 11 | Fdiv utt(1'd1,32'd1000000,clk,clk100us);//10ms 12 | core utu(clk100us,in,out1); 13 | always @(negedge out1) begin 14 | out <= out + 1; 15 | end 16 | endmodule 17 | 18 | module button(clk,in,out); 19 | input clk,in; 20 | output out; 21 | wire clk100us; 22 | Fdiv utt(1'd1,32'd1000000,clk,clk100us); 23 | core utt2(clk100us,in,out); 24 | endmodule 25 | 26 | module core(CP,in,out); 27 | input in,CP; 28 | output reg out; 29 | reg[2:0] ST; 30 | parameter S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100,S5=3'b101; 31 | always @( posedge CP) 32 | begin 33 | case(ST) 34 | S0: 35 | out <= 1'b0; 36 | S1: 37 | out <= in; 38 | S2: 39 | out <= 1'b0; 40 | S3: 41 | out <= 1'b1; 42 | S4: 43 | out <= in; 44 | S5: 45 | out <= in; 46 | endcase 47 | case(ST) 48 | S0: 49 | ST<=in?S1:S0; 50 | S1: 51 | ST<=in?S3:S2; 52 | S2: 53 | ST<=in?S1:S0; 54 | S3: 55 | ST<=in?S3:S4; 56 | S4: 57 | ST<=in?S5:S0; 58 | S5: 59 | ST<=in?S3:S4; 60 | endcase 61 | end 62 | endmodule 63 | -------------------------------------------------------------------------------- /IM/IM.srcs/sources_1/rom.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector=002081B3 00209233 01211293 F9C08313 05208313 07802103 06202223 34422137 FC3117E3 F841CEE3 00200067 262733EF; 3 | -------------------------------------------------------------------------------- /IM/IM.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 158 | 159 | 160 | 161 | 162 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 177 | 178 | 179 | 180 | 181 | 184 | 185 | 187 | 188 | 190 | 191 | 193 | 194 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | default_dashboard 282 | 283 | 284 | 285 | -------------------------------------------------------------------------------- /RAM/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/RAM/.DS_Store -------------------------------------------------------------------------------- /RAM/RAM.srcs/constrs_1/new/RAM.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD LVCMOS18 [get_ports clk_100M] 2 | set_property IOSTANDARD LVCMOS18 [get_ports rst_] 3 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[7]}] 4 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[6]}] 5 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[5]}] 6 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[4]}] 7 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[3]}] 8 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[2]}] 9 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[1]}] 10 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[0]}] 11 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[7]}] 12 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[6]}] 13 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[5]}] 14 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[4]}] 15 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[3]}] 16 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[2]}] 17 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[1]}] 18 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[0]}] 19 | 20 | set_property PACKAGE_PIN C9 [get_ports {AN[7]}] 21 | set_property PACKAGE_PIN C10 [get_ports {AN[6]}] 22 | set_property PACKAGE_PIN D10 [get_ports {AN[5]}] 23 | set_property PACKAGE_PIN C11 [get_ports {AN[4]}] 24 | set_property PACKAGE_PIN M17 [get_ports {AN[3]}] 25 | set_property PACKAGE_PIN J14 [get_ports {AN[2]}] 26 | set_property PACKAGE_PIN K13 [get_ports {AN[1]}] 27 | set_property PACKAGE_PIN P14 [get_ports {AN[0]}] 28 | set_property PACKAGE_PIN F14 [get_ports {Seg[7]}] 29 | set_property PACKAGE_PIN N14 [get_ports {Seg[6]}] 30 | set_property PACKAGE_PIN J13 [get_ports {Seg[5]}] 31 | set_property PACKAGE_PIN G13 [get_ports {Seg[4]}] 32 | set_property PACKAGE_PIN F13 [get_ports {Seg[3]}] 33 | set_property PACKAGE_PIN G14 [get_ports {Seg[2]}] 34 | set_property PACKAGE_PIN M13 [get_ports {Seg[1]}] 35 | set_property PACKAGE_PIN H14 [get_ports {Seg[0]}] 36 | 37 | set_property PACKAGE_PIN E3 [get_ports clk_100M] 38 | set_property PACKAGE_PIN U8 [get_ports rst_] 39 | 40 | 41 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst__IBUF] 42 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_DM_IBUF] 43 | 44 | set_property IOSTANDARD LVCMOS18 [get_ports DM_Write] 45 | set_property IOSTANDARD LVCMOS18 [get_ports SE_s] 46 | set_property IOSTANDARD LVCMOS18 [get_ports clk_100Mhz] 47 | set_property IOSTANDARD LVCMOS18 [get_ports clk_DM] 48 | set_property IOSTANDARD LVCMOS18 [get_ports clr] 49 | set_property IOSTANDARD LVCMOS18 [get_ports {siz[1]}] 50 | set_property IOSTANDARD LVCMOS18 [get_ports {siz[0]}] 51 | set_property IOSTANDARD LVCMOS18 [get_ports {DM_Addr[7]}] 52 | set_property IOSTANDARD LVCMOS18 [get_ports {DM_Addr[6]}] 53 | set_property IOSTANDARD LVCMOS18 [get_ports {DM_Addr[5]}] 54 | set_property IOSTANDARD LVCMOS18 [get_ports {DM_Addr[4]}] 55 | set_property IOSTANDARD LVCMOS18 [get_ports {DM_Addr[3]}] 56 | set_property IOSTANDARD LVCMOS18 [get_ports {DM_Addr[2]}] 57 | set_property IOSTANDARD LVCMOS18 [get_ports {DM_Addr[1]}] 58 | set_property IOSTANDARD LVCMOS18 [get_ports {DM_Addr[0]}] 59 | set_property IOSTANDARD LVCMOS18 [get_ports {Data_selector[2]}] 60 | set_property IOSTANDARD LVCMOS18 [get_ports {Data_selector[1]}] 61 | set_property IOSTANDARD LVCMOS18 [get_ports {Data_selector[0]}] 62 | 63 | set_property PACKAGE_PIN E3 [get_ports clk_100Mhz] 64 | set_property PACKAGE_PIN V5 [get_ports {DM_Addr[7]}] 65 | set_property PACKAGE_PIN T4 [get_ports {DM_Addr[6]}] 66 | set_property PACKAGE_PIN V6 [get_ports {DM_Addr[5]}] 67 | set_property PACKAGE_PIN T5 [get_ports {DM_Addr[4]}] 68 | set_property PACKAGE_PIN T6 [get_ports {DM_Addr[3]}] 69 | set_property PACKAGE_PIN V7 [get_ports {DM_Addr[2]}] 70 | set_property PACKAGE_PIN R8 [get_ports {DM_Addr[1]}] 71 | set_property PACKAGE_PIN U9 [get_ports {DM_Addr[0]}] 72 | set_property PACKAGE_PIN T9 [get_ports DM_Write] 73 | set_property PACKAGE_PIN V10 [get_ports SE_s] 74 | set_property PACKAGE_PIN N17 [get_ports clk_DM] 75 | set_property PACKAGE_PIN P18 [get_ports clr] 76 | set_property PACKAGE_PIN R10 [get_ports {Data_selector[2]}] 77 | set_property PACKAGE_PIN U11 [get_ports {Data_selector[1]}] 78 | set_property PACKAGE_PIN R11 [get_ports {Data_selector[0]}] 79 | set_property PACKAGE_PIN U12 [get_ports {siz[1]}] 80 | set_property PACKAGE_PIN T13 [get_ports {siz[0]}] 81 | -------------------------------------------------------------------------------- /RAM/RAM.srcs/sim_1/new/sim.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module sim(); 3 | 4 | reg clk; 5 | reg write; 6 | reg [7:0]addr; 7 | reg [31:0]data_in; 8 | wire [31:0]data_out; 9 | reg [1:0]siz; 10 | reg SE_s; 11 | 12 | RAM ram( 13 | .clk_DM(clk), 14 | .DM_Addr(addr), 15 | .RAM_Write(write), 16 | .siz(siz), 17 | .SE_s(SE_s), 18 | .RAM_in(data_in), 19 | .RAM_out(data_out) 20 | ); 21 | 22 | always @(*)begin 23 | #2 24 | clk <= ~clk; 25 | end 26 | always @(*)begin 27 | #128 28 | write <= ~write; 29 | end 30 | 31 | always @(*)begin 32 | #8 33 | addr[1:0] <= addr[1:0]+1; 34 | end 35 | always @(*)begin 36 | #4 37 | SE_s <= ~SE_s; 38 | end 39 | 40 | always @(*)begin 41 | #32 42 | siz <= siz + 1; 43 | end 44 | 45 | initial begin 46 | clk = 0; 47 | write = 0; 48 | addr = 0; 49 | data_in = 32'h12345678; 50 | SE_s = 0; 51 | siz = 0; 52 | 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /RAM/RAM.srcs/sources_1/ip/RAM_A/RAM_A.xci: -------------------------------------------------------------------------------- 1 | { 2 | "schema": "xilinx.com:schema:json_instance:1.0", 3 | "ip_inst": { 4 | "xci_name": "RAM_A", 5 | "component_reference": "xilinx.com:ip:blk_mem_gen:8.4", 6 | "ip_revision": "5", 7 | "gen_directory": "../../../../RAM.gen/sources_1/ip/RAM_A", 8 | "parameters": { 9 | "component_parameters": { 10 | "Component_Name": [ { "value": "RAM_A", "resolve_type": "user", "usage": "all" } ], 11 | "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ], 12 | "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ], 13 | "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ], 14 | "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 15 | "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], 16 | "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ], 17 | "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ], 18 | "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 19 | "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ], 20 | "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 21 | "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 22 | "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 23 | "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 24 | "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 25 | "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 26 | "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 27 | "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 28 | "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 29 | "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ], 30 | "Use_Byte_Write_Enable": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], 31 | "Byte_Size": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ], 32 | "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ], 33 | "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ], 34 | "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 35 | "Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], 36 | "Write_Depth_A": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], 37 | "Read_Width_A": [ { "value": "32", "resolve_type": "user", "usage": "all" } ], 38 | "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ], 39 | "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], 40 | "Write_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ], 41 | "Read_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ], 42 | "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], 43 | "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ], 44 | "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], 45 | "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 46 | "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 47 | "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 48 | "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 49 | "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 50 | "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 51 | "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 52 | "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], 53 | "Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], 54 | "Coe_File": [ { "value": "../ip.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ], 55 | "Fill_Remaining_Memory_Locations": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], 56 | "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], 57 | "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 58 | "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 59 | "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], 60 | "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], 61 | "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 62 | "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 63 | "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], 64 | "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], 65 | "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ], 66 | "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 67 | "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], 68 | "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ], 69 | "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], 70 | "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], 71 | "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], 72 | "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], 73 | "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ], 74 | "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 75 | "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 76 | "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ], 77 | "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ], 78 | "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], 79 | "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], 80 | "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], 81 | "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ] 82 | }, 83 | "model_parameters": { 84 | "C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], 85 | "C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], 86 | "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ], 87 | "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 88 | "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], 89 | "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 90 | "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 91 | 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"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 148 | "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 149 | "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 150 | "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 151 | "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 152 | "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 153 | "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 154 | "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 155 | "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], 156 | "C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], 157 | "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], 158 | "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 3.53845 mW", "resolve_type": "generated", "usage": "all" } ] 159 | }, 160 | "project_parameters": { 161 | "ARCHITECTURE": [ { "value": "artix7" } ], 162 | "BASE_BOARD_PART": [ { "value": "" } ], 163 | "BOARD_CONNECTIONS": [ { "value": "" } ], 164 | "DEVICE": [ { "value": "xc7a100t" } ], 165 | "PACKAGE": [ { "value": "csg324" } ], 166 | "PREFHDL": [ { "value": "VERILOG" } ], 167 | "SILICON_REVISION": [ { "value": "" } ], 168 | "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], 169 | "SPEEDGRADE": [ { "value": "-1" } ], 170 | "STATIC_POWER": [ { "value": "" } ], 171 | "TEMPERATURE_GRADE": [ { "value": "" } ], 172 | "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], 173 | "USE_RDI_GENERATION": [ { "value": "TRUE" } ] 174 | }, 175 | "runtime_parameters": { 176 | "IPCONTEXT": [ { "value": "IP_Flow" } ], 177 | "IPREVISION": [ { "value": "5" } ], 178 | "MANAGED": [ { "value": "TRUE" } ], 179 | "OUTPUTDIR": [ { "value": "../../../../RAM.gen/sources_1/ip/RAM_A" } ], 180 | "SELECTEDSIMMODEL": [ { "value": "" } ], 181 | "SHAREDDIR": [ { "value": "." } ], 182 | "SWVERSION": [ { "value": "2022.2" } ], 183 | "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] 184 | } 185 | }, 186 | "boundary": { 187 | "ports": { 188 | "clka": [ { "direction": "in", "driver_value": "0" } ], 189 | "wea": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], 190 | "addra": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ], 191 | "dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], 192 | "douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ] 193 | }, 194 | "interfaces": { 195 | "CLK.ACLK": { 196 | "vlnv": "xilinx.com:signal:clock:1.0", 197 | "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", 198 | "mode": "slave", 199 | "parameters": { 200 | "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ], 201 | "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ], 202 | "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], 203 | "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], 204 | "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], 205 | "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], 206 | "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], 207 | "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] 208 | } 209 | }, 210 | "RST.ARESETN": { 211 | "vlnv": "xilinx.com:signal:reset:1.0", 212 | "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", 213 | "mode": "slave", 214 | "parameters": { 215 | "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], 216 | "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] 217 | } 218 | }, 219 | "BRAM_PORTA": { 220 | "vlnv": "xilinx.com:interface:bram:1.0", 221 | "abstraction_type": "xilinx.com:interface:bram_rtl:1.0", 222 | "mode": "slave", 223 | "parameters": { 224 | "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], 225 | "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], 226 | "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], 227 | "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], 228 | "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], 229 | "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] 230 | }, 231 | "port_maps": { 232 | "ADDR": [ { "physical_name": "addra" } ], 233 | "CLK": [ { "physical_name": "clka" } ], 234 | "DIN": [ { "physical_name": "dina" } ], 235 | "DOUT": [ { "physical_name": "douta" } ], 236 | "WE": [ { "physical_name": "wea" } ] 237 | } 238 | } 239 | }, 240 | "memory_maps": { 241 | "S_1": { 242 | "address_blocks": { 243 | "Mem0": { 244 | "base_address": "0", 245 | "range": "4096", 246 | "usage": "memory", 247 | "access": "read-write", 248 | "parameters": { 249 | "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ], 250 | "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ] 251 | } 252 | } 253 | } 254 | } 255 | } 256 | } 257 | } 258 | } -------------------------------------------------------------------------------- /RAM/RAM.srcs/sources_1/ip/ip.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector=66778899 00632233 13010fff 20006789 FFFF0000 0000FFFF 88888888 99999999 aaaaaaaa bbbbbbbb; 3 | -------------------------------------------------------------------------------- /RAM/RAM.srcs/sources_1/new/DataSelector.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module DataSelector(select,out); 4 | input [2:0]select; 5 | output reg [31:0]out; 6 | 7 | always @(*) begin 8 | case (select) 9 | 0: out = 32'h7fffffff; 10 | 1: out = 32'hffffffff; 11 | 2: out = 32'h7; 12 | 3: out = 32'b1; 13 | 4: out = 32'b0; 14 | 5: out = 32'h0aaaaaaa; 15 | 6: out = 32'h5; 16 | 7: out = 32'h11223344; 17 | endcase 18 | end 19 | 20 | endmodule -------------------------------------------------------------------------------- /RAM/RAM.srcs/sources_1/new/Fdiv.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Fdiv(input reset,input[31:0] mult,input clk_1M,output reg clk_1K); 3 | reg [31:0]counter; 4 | initial begin counter = 32'd0;end 5 | initial begin clk_1K = 0;end 6 | always @(posedge clk_1M or negedge reset) begin 7 | if(!reset)begin 8 | counter <= 32'd0; 9 | clk_1K <= 1'b0; 10 | end 11 | else if(counter == mult) begin 12 | clk_1K <= ~clk_1K; 13 | counter <= 32'd0; 14 | end 15 | else begin 16 | counter <= counter + 1'b1; 17 | end 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /RAM/RAM.srcs/sources_1/new/RAM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module W_Process(siz,EN,Low_Addr,RAM_in,D_in,wea); 4 | input [1:0]siz; 5 | input [31:0]RAM_in; 6 | input [1:0]Low_Addr; 7 | input EN; 8 | output [31:0] D_in; 9 | output[3:0] wea; 10 | assign wea = EN ? siz == 2'b00 ? 4'b0001 << Low_Addr[1:0] 11 | :siz == 2'b01 ? 4'b0011 << {Low_Addr[1],1'b0} 12 | :4'b1111 13 | :4'b0000; 14 | 15 | assign D_in = siz == 2'b00 ? {RAM_in[7:0],RAM_in[7:0],RAM_in[7:0],RAM_in[7:0]} 16 | :siz == 2'b01 ? {RAM_in[15:0],RAM_in[15:0]} 17 | :RAM_in; 18 | endmodule 19 | 20 | 21 | module SE(siz,SE,Low_Addr,D_in,Ex_out); 22 | input [1:0]siz; 23 | input SE; 24 | input [31:0]D_in; 25 | input [1:0]Low_Addr; 26 | output [31:0]Ex_out; 27 | 28 | wire [31:0] cur; 29 | assign cur = siz == 2'b00 ? D_in >> {Low_Addr[1:0],3'b0} 30 | :siz == 2'b01 ? D_in >> {Low_Addr[1],4'b0} 31 | :D_in; 32 | 33 | assign Ex_out = siz == 2'b00 ? {{24{cur[7] & SE}},cur[7:0]} 34 | : siz == 2'b01 ? {{16{cur[15] & SE}},cur[15:0]} 35 | : cur; 36 | endmodule 37 | 38 | module RAM(clk_DM,DM_Addr,RAM_Write,siz,SE_s,RAM_in,RAM_out); 39 | input clk_DM; 40 | input [7:0]DM_Addr; 41 | input [1:0]siz; 42 | input SE_s; 43 | input [31:0]RAM_in; 44 | output [31:0]RAM_out; 45 | input RAM_Write; 46 | 47 | wire [3:0]wea; 48 | wire [31:0]D_in; 49 | wire [31:0]D_out; 50 | 51 | W_Process read_process( 52 | .siz(siz), 53 | .RAM_in(RAM_in), 54 | .D_in(D_in), 55 | .wea(wea), 56 | .EN(RAM_Write), 57 | .Low_Addr(DM_Addr[1:0]) 58 | ); 59 | 60 | RAM_A Data_RAM ( 61 | .clka(clk_DM), // input wire clka 62 | .addra(DM_Addr[7:2]), // input wire [5 : 0] addra 63 | .dina(D_in), // input wire [31 : 0] dina 64 | .wea(wea), // input wire [3 : 0] wea 65 | .douta(D_out) // output wire [31 : 0] douta 66 | ); 67 | 68 | SE se( 69 | .siz(siz), 70 | .SE(SE_s), 71 | .D_in(D_out), 72 | .Ex_out(RAM_out), 73 | .Low_Addr(DM_Addr[1:0]) 74 | ); 75 | endmodule 76 | 77 | module top(clr,clk_100Mhz,clk_DM,DM_Addr,DM_Write,Data_selector,Seg,AN,siz,SE_s); 78 | input clr,clk_100Mhz,clk_DM; 79 | input [7:0]DM_Addr; 80 | input DM_Write; 81 | input [2:0]Data_selector; 82 | input [1:0]siz; 83 | input SE_s; 84 | output [7:0]Seg; 85 | output [7:0]AN; 86 | 87 | wire [31:0]DM_in; 88 | DataSelector selecotr( 89 | .select(Data_selector), 90 | .out(DM_in) 91 | ); 92 | 93 | wire [31:0]RAM_out; 94 | reg [31:0] data_show; 95 | always @(posedge clk_DM)begin 96 | if(!DM_Write) data_show <= RAM_out; 97 | end 98 | 99 | RAM ram( 100 | .clk_DM(clk_DM), 101 | .DM_Addr(DM_Addr), 102 | .RAM_Write(DM_Write), 103 | .siz(siz), 104 | .SE_s(SE_s), 105 | .RAM_in(DM_in), 106 | .RAM_out(RAM_out) 107 | ); 108 | 109 | scan_data tube( 110 | .reset(clr), 111 | .data(RAM_out), 112 | .clk(clk_100Mhz), 113 | .AN(AN), 114 | .seg(Seg) 115 | ); 116 | endmodule -------------------------------------------------------------------------------- /RAM/RAM.srcs/sources_1/new/Tube.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module scan_data(reset,data,clk,AN,seg); 4 | output [7:0]AN; 5 | output [7:0]seg; 6 | input reset; 7 | input clk; 8 | input [31:0]data; 9 | wire clk_5ms; 10 | reg [2:0]select = 0; 11 | Fdiv utt(reset,32'd50000,clk,clk_5ms); 12 | 13 | always @(posedge clk_5ms or negedge reset) begin 14 | if(!reset)begin 15 | select <= 3'd0; 16 | end 17 | else begin 18 | select <= select + 3'd1; 19 | end 20 | end 21 | 22 | reg [3:0]data_in; 23 | show sh(data_in,select,AN,seg); 24 | always @(*) begin 25 | case (select) 26 | 7: data_in = data[31:28]; 27 | 6: data_in = data[27:24]; 28 | 5: data_in = data[23:20]; 29 | 4: data_in = data[19:16]; 30 | 3: data_in = data[15:12]; 31 | 2: data_in = data[11:8]; 32 | 1: data_in = data[7:4]; 33 | 0: data_in = data[3:0]; 34 | endcase 35 | end 36 | endmodule 37 | 38 | 39 | module show(data,seletct,AN,seg); 40 | input [3:0]data; 41 | input [2:0]seletct; 42 | output reg[7:0]AN; 43 | output reg [7:0]seg; 44 | 45 | always @(*) begin 46 | case(seletct) 47 | 0:AN = 8'b11111110; 48 | 1:AN = 8'b11111101; 49 | 2:AN = 8'b11111011; 50 | 3:AN = 8'b11110111; 51 | 4:AN = 8'b11101111; 52 | 5:AN = 8'b11011111; 53 | 6:AN = 8'b10111111; 54 | 7:AN = 8'b01111111; 55 | default: AN = 8'Hff; 56 | endcase 57 | end 58 | 59 | always @(*) begin 60 | case (data) 61 | 0:seg = 8'b00000011; 62 | 1:seg = 8'b10011111; 63 | 2:seg = 8'b00100101; 64 | 3:seg = 8'b00001101; 65 | 4:seg = 8'b10011001; 66 | 5:seg = 8'b01001001; 67 | 6:seg = 8'b01000001; 68 | 7:seg = 8'b00011111; 69 | 8:seg = 8'b00000001; 70 | 9:seg = 8'b00001001; 71 | 10:seg = 8'b00010001; 72 | 11:seg = 8'b11000001; 73 | 12:seg = 8'b01100011; 74 | 13:seg = 8'b10000101; 75 | 14:seg = 8'b01100001; 76 | 15:seg = 8'b01110001; 77 | default:seg = 8'Hff; 78 | endcase 79 | end 80 | endmodule -------------------------------------------------------------------------------- /RAM/RAM.srcs/utils_1/imports/synth_1/RAM.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/RAM/RAM.srcs/utils_1/imports/synth_1/RAM.dcp -------------------------------------------------------------------------------- /RAM/RAM.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 199 | 200 | 201 | 202 | 203 | 206 | 207 | 209 | 210 | 212 | 213 | 215 | 216 | 218 | 219 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | default_dashboard 307 | 308 | 309 | 310 | -------------------------------------------------------------------------------- /RAM/RAM记录表.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/RAM/RAM记录表.xlsx -------------------------------------------------------------------------------- /RAM/top.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/RAM/top.bit -------------------------------------------------------------------------------- /RAM/wave.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | clk 25 | clk 26 | 27 | 28 | write 29 | write 30 | 31 | 32 | addr[7:0] 33 | addr[7:0] 34 | 35 | 36 | data_in[31:0] 37 | data_in[31:0] 38 | 39 | 40 | data_out[31:0] 41 | data_out[31:0] 42 | 43 | 44 | siz[1:0] 45 | siz[1:0] 46 | 47 | 48 | SE_s 49 | SE_s 50 | 51 | 52 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Computer-organization-experiment 2 | 杭电计算机科学与技术专业计算机组成原理实验（RISC-V） 3 | 包含实验3~11，只有源码，ip核自己配置。 4 | -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/constrs_1/new/RegFile.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD LVCMOS18 [get_ports clk_Write] 2 | set_property IOSTANDARD LVCMOS18 [get_ports rst_] 3 | set_property IOSTANDARD LVCMOS18 [get_ports {ALU_OP[3]}] 4 | set_property IOSTANDARD LVCMOS18 [get_ports {ALU_OP[2]}] 5 | set_property IOSTANDARD LVCMOS18 [get_ports {ALU_OP[1]}] 6 | set_property IOSTANDARD LVCMOS18 [get_ports {ALU_OP[0]}] 7 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[7]}] 8 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[6]}] 9 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[5]}] 10 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[4]}] 11 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[3]}] 12 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[2]}] 13 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[1]}] 14 | set_property IOSTANDARD LVCMOS18 [get_ports {AN[0]}] 15 | set_property IOSTANDARD LVCMOS18 [get_ports {A_addr[4]}] 16 | set_property IOSTANDARD LVCMOS18 [get_ports {A_addr[3]}] 17 | set_property IOSTANDARD LVCMOS18 [get_ports {A_addr[2]}] 18 | set_property IOSTANDARD LVCMOS18 [get_ports {A_addr[1]}] 19 | set_property IOSTANDARD LVCMOS18 [get_ports {A_addr[0]}] 20 | set_property IOSTANDARD LVCMOS18 [get_ports {B_addr[4]}] 21 | set_property IOSTANDARD LVCMOS18 [get_ports {B_addr[3]}] 22 | set_property IOSTANDARD LVCMOS18 [get_ports {B_addr[2]}] 23 | set_property IOSTANDARD LVCMOS18 [get_ports {B_addr[1]}] 24 | set_property IOSTANDARD LVCMOS18 [get_ports {B_addr[0]}] 25 | set_property IOSTANDARD LVCMOS18 [get_ports {FR[3]}] 26 | set_property IOSTANDARD LVCMOS18 [get_ports {FR[2]}] 27 | set_property IOSTANDARD LVCMOS18 [get_ports {FR[1]}] 28 | set_property IOSTANDARD LVCMOS18 [get_ports {FR[0]}] 29 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[7]}] 30 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[6]}] 31 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[5]}] 32 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[4]}] 33 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[3]}] 34 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[2]}] 35 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[1]}] 36 | set_property IOSTANDARD LVCMOS18 [get_ports {Seg[0]}] 37 | set_property IOSTANDARD LVCMOS18 [get_ports {W_Addr[4]}] 38 | set_property IOSTANDARD LVCMOS18 [get_ports {W_Addr[3]}] 39 | set_property IOSTANDARD LVCMOS18 [get_ports {W_Addr[2]}] 40 | set_property IOSTANDARD LVCMOS18 [get_ports {W_Addr[1]}] 41 | set_property IOSTANDARD LVCMOS18 [get_ports {W_Addr[0]}] 42 | set_property IOSTANDARD LVCMOS18 [get_ports clk_100M] 43 | set_property IOSTANDARD LVCMOS18 [get_ports Reg_Write] 44 | set_property IOSTANDARD LVCMOS18 [get_ports clk_F] 45 | set_property IOSTANDARD LVCMOS18 [get_ports clk_Read] 46 | 47 | 48 | set_property PACKAGE_PIN C9 [get_ports {AN[7]}] 49 | set_property PACKAGE_PIN C10 [get_ports {AN[6]}] 50 | set_property PACKAGE_PIN D10 [get_ports {AN[5]}] 51 | set_property PACKAGE_PIN C11 [get_ports {AN[4]}] 52 | set_property PACKAGE_PIN M17 [get_ports {AN[3]}] 53 | set_property PACKAGE_PIN J14 [get_ports {AN[2]}] 54 | set_property PACKAGE_PIN K13 [get_ports {AN[1]}] 55 | set_property PACKAGE_PIN P14 [get_ports {AN[0]}] 56 | set_property PACKAGE_PIN F14 [get_ports {Seg[7]}] 57 | set_property PACKAGE_PIN N14 [get_ports {Seg[6]}] 58 | set_property PACKAGE_PIN J13 [get_ports {Seg[5]}] 59 | set_property PACKAGE_PIN G13 [get_ports {Seg[4]}] 60 | set_property PACKAGE_PIN F13 [get_ports {Seg[3]}] 61 | set_property PACKAGE_PIN G14 [get_ports {Seg[2]}] 62 | set_property PACKAGE_PIN M13 [get_ports {Seg[1]}] 63 | set_property PACKAGE_PIN H14 [get_ports {Seg[0]}] 64 | 65 | 66 | set_property PACKAGE_PIN T14 [get_ports {ALU_OP[3]}] 67 | set_property PACKAGE_PIN V15 [get_ports {ALU_OP[2]}] 68 | set_property PACKAGE_PIN R15 [get_ports {ALU_OP[1]}] 69 | set_property PACKAGE_PIN U16 [get_ports {ALU_OP[0]}] 70 | 71 | set_property PACKAGE_PIN U6 [get_ports {FR[3]}] 72 | set_property PACKAGE_PIN R5 [get_ports {FR[2]}] 73 | set_property PACKAGE_PIN U7 [get_ports {FR[1]}] 74 | set_property PACKAGE_PIN R6 [get_ports {FR[0]}] 75 | 76 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_F_IBUF] 77 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst__IBUF] 78 | #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets _Write_IBUF] 79 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_Write_IBUF] 80 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_Read_IBUF] 81 | 82 | set_property PACKAGE_PIN E3 [get_ports clk_100M] 83 | set_property PACKAGE_PIN N17 [get_ports clk_Read] 84 | set_property PACKAGE_PIN P18 [get_ports clk_Write] 85 | set_property PACKAGE_PIN P17 [get_ports clk_F] 86 | set_property PACKAGE_PIN U17 [get_ports rst_] 87 | 88 | set_property PACKAGE_PIN V5 [get_ports {A_addr[4]}] 89 | set_property PACKAGE_PIN T4 [get_ports {A_addr[3]}] 90 | set_property PACKAGE_PIN V6 [get_ports {A_addr[2]}] 91 | set_property PACKAGE_PIN T5 [get_ports {A_addr[1]}] 92 | set_property PACKAGE_PIN T6 [get_ports {A_addr[0]}] 93 | set_property PACKAGE_PIN V7 [get_ports {B_addr[4]}] 94 | set_property PACKAGE_PIN R8 [get_ports {B_addr[3]}] 95 | set_property PACKAGE_PIN U9 [get_ports {B_addr[2]}] 96 | set_property PACKAGE_PIN T9 [get_ports {B_addr[1]}] 97 | set_property PACKAGE_PIN V10 [get_ports {B_addr[0]}] 98 | set_property PACKAGE_PIN R10 [get_ports {W_Addr[4]}] 99 | set_property PACKAGE_PIN U11 [get_ports {W_Addr[3]}] 100 | set_property PACKAGE_PIN R11 [get_ports {W_Addr[2]}] 101 | set_property PACKAGE_PIN U12 [get_ports {W_Addr[1]}] 102 | set_property PACKAGE_PIN T13 [get_ports {W_Addr[0]}] 103 | set_property PACKAGE_PIN V14 [get_ports Reg_Write] 104 | -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/sim_1/new/simu_RegFile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module simu_RegFile(); 4 | 5 | reg [4:0]A_addr,B_addr,W_Addr; 6 | wire[31:0]A_out,B_out; 7 | reg rst_,clk_W; 8 | reg [31:0]data_write; 9 | Register_File rf(data_write,1'b1,rst_,clk_W,A_addr,B_addr,W_Addr,A_out,B_out); 10 | 11 | integer x; 12 | initial begin 13 | rst_ = 1; 14 | clk_W = 1; 15 | A_addr = 0; 16 | B_addr = 0; 17 | W_Addr = 0; 18 | #10 19 | rst_ = 0; 20 | #10 rst_ = 1; 21 | 22 | for(x = 0;x < 32; x = x + 1)begin 23 | #5 24 | A_addr = x; 25 | end 26 | 27 | for(x = 0;x < 32; x = x + 1)begin 28 | W_Addr = x; 29 | B_addr = x; 30 | data_write = x + 233; 31 | clk_W = 1; 32 | #2 33 | clk_W = 0; 34 | #2 35 | clk_W = 1; 36 | end 37 | 38 | for(x = 0;x < 32; x = x + 1)begin 39 | #5 40 | A_addr = x; 41 | end 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/sources_1/new/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ALU(OP,A,B,F,ZF,SF,CF,OF); 4 | input [3:0]OP; 5 | input [31:0]A,B; 6 | output reg[31:0]F; 7 | output CF,OF,ZF,SF; 8 | 9 | integer i; 10 | reg C1,C2; 11 | assign ZF = F ? 0 : 1; 12 | assign SF = F[31]; 13 | assign OF = A[31] ^ B[31] ^ C1 ^ F[31]; 14 | assign CF = C1; 15 | always @(*) 16 | begin 17 | case(OP) 18 | 4'b0000: 19 | begin 20 | {C1,F} = {1'b0,A} + {1'b0,B}; 21 | end 22 | 4'b0001: F = A << B; 23 | 4'b0010: F = $signed(A) < $signed(B) ? 1 : 0; 24 | 4'b0011: F = A < B ? 1'b1 : 1'b0; 25 | 4'b0100: F = A ^ B; 26 | 4'b0101: F = A >> B; 27 | 4'b0110: F = A | B; 28 | 4'b0111: F = A & B; 29 | 4'b1000: 30 | begin 31 | {C1,F} = {1'b0,A} - {1'b0,B}; 32 | end 33 | 4'b1101: 34 | begin 35 | F = $signed(A) >>> B; 36 | end 37 | default:F=0; 38 | endcase 39 | 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/sources_1/new/BigALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module BigALU(ALU_OP,Data_A,Data_B,rst_,clk_A,clk_B,clk_F,A,B,F,FR); 4 | input [3:0]ALU_OP; 5 | input [31:0]Data_A,Data_B; 6 | input rst_,clk_A,clk_B,clk_F; 7 | output [31:0]F; 8 | output [3:0]FR; 9 | output [31:0]A,B; 10 | wire [31:0]res; 11 | wire ZF,SF,CF,OF; 12 | Register RA(clk_A,rst_,Data_A,A); //暂存器 13 | Register RB(clk_B,rst_,Data_B,B); //暂存器 14 | ALU alu(ALU_OP,A,B,res,ZF,SF,CF,OF); //ALU 15 | Register RF(clk_F,rst_,res,F); //暂存器 16 | Register flag_register(clk_F,rst_,{28'b0,ZF,SF,CF,OF},FR); //暂存器 17 | endmodule -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/sources_1/new/Fdiv.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Fdiv(input reset,input[31:0] mult,input clk_1M,output reg clk_1K); 3 | reg [31:0]counter; 4 | initial begin counter = 32'd0;end 5 | initial begin clk_1K = 0;end 6 | always @(posedge clk_1M or negedge reset) begin 7 | if(!reset)begin 8 | counter <= 32'd0; 9 | clk_1K <= 1'b0; 10 | end 11 | else if(counter == mult) begin 12 | clk_1K <= ~clk_1K; 13 | counter <= 32'd0; 14 | end 15 | else begin 16 | counter <= counter + 1'b1; 17 | end 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/sources_1/new/RegFile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Register_File(data_write,Reg_Write,rst_,clk_W,A_addr,B_addr,W_addr,A_out,B_out); 3 | input [31:0]data_write; 4 | input [4:0]A_addr,B_addr,W_addr; 5 | input Reg_Write,clk_W; 6 | input rst_; 7 | output [31:0]A_out,B_out; 8 | 9 | reg [31:0]Reg_Files[0:31]; 10 | 11 | assign A_out = Reg_Files[A_addr]; 12 | assign B_out = Reg_Files[B_addr]; 13 | 14 | integer i; 15 | 16 | always @(negedge rst_ or negedge clk_W) begin 17 | if(!rst_)begin //初始化 18 | Reg_Files[0] <= 32'h0000_0000; 19 | for(i = 1; i < 32; i = i + 1) Reg_Files[i] <= 32'h0000_0001; 20 | Reg_Files[7] <= 32'h0000_0007; 21 | Reg_Files[8] <= 32'hf7f7_f7f7; 22 | Reg_Files[9] <= 32'h37f7_f7f7; 23 | Reg_Files[29] <= 32'h8000_0002; 24 | Reg_Files[30] <= 32'hffff_ffff; 25 | Reg_Files[31] <= 32'h7fff_ffff; 26 | end else if(Reg_Write && W_addr != 5'd0)Reg_Files[W_addr] <= data_write; //地址非0时写入 27 | 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/sources_1/new/Register.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Register(clk,rst_,X,Y); 3 | input clk,rst_; 4 | input [31:0]X; 5 | output reg [31:0]Y; 6 | always @(posedge clk or negedge rst_) 7 | begin 8 | if(!rst_) Y <= 32'b0; 9 | else Y <= X; 10 | end 11 | endmodule -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/sources_1/new/TOP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module BigBigALU(A_addr,B_addr,W_Addr,ALU_OP,Reg_Write,clk_100M,rst_,clk_Read,clk_F,clk_Write,F,FR); //链接寄存器堆和ALU 3 | input [4:0]A_addr,B_addr,W_Addr; 4 | input [3:0]ALU_OP; 5 | input Reg_Write,clk_100M; 6 | input rst_,clk_Read,clk_F,clk_Write; 7 | output [3:0]FR; 8 | output [31:0]F; 9 | 10 | wire [31:0]Reg_A,Reg_B; 11 | 12 | Register_File rgf( 13 | .rst_(rst_), 14 | .data_write(F), 15 | .Reg_Write(Reg_Write), 16 | .clk_W(clk_Write), 17 | .A_addr(A_addr), 18 | .B_addr(B_addr), 19 | .W_addr(W_Addr), 20 | .A_out(Reg_A), 21 | .B_out(Reg_B)); 22 | 23 | BigALU alu( 24 | .ALU_OP(ALU_OP), 25 | .Data_A(Reg_A), 26 | .Data_B(Reg_B), 27 | .rst_(rst_), 28 | .clk_A(clk_Read), 29 | .clk_B(clk_Read), 30 | .clk_F(clk_F), 31 | .F(F), 32 | .FR(FR)); 33 | endmodule 34 | 35 | 36 | 37 | module TOP(A_addr,B_addr,W_Addr,ALU_OP,Reg_Write,clk_100M,rst_,clk_Read,clk_F,clk_Write,AN,Seg,FR); //顶层模块 38 | input [4:0]A_addr,B_addr,W_Addr; 39 | input [3:0]ALU_OP; 40 | input Reg_Write,clk_100M; 41 | input rst_,clk_Read,clk_F,clk_Write; 42 | output [7:0]AN; 43 | output [7:0]Seg; 44 | output [3:0]FR; 45 | 46 | wire [31:0]F; 47 | 48 | BigBigALU aluu( 49 | .A_addr(A_addr), 50 | .B_addr(B_addr), 51 | .W_Addr(W_Addr), 52 | .ALU_OP(ALU_OP), 53 | .Reg_Write(Reg_Write), 54 | .clk_100M(clk_100M), 55 | .rst_(rst_), 56 | .clk_Read(clk_Read), 57 | .clk_F(clk_F), 58 | .clk_Write(clk_Write), 59 | .F(F), 60 | .FR(FR)); 61 | 62 | scan_data tube(rst_,F,clk_100M,AN,Seg); 63 | endmodule 64 | -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/sources_1/new/Tube.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module scan_data(reset,data,clk,AN,seg); 4 | output [7:0]AN; 5 | output [7:0]seg; 6 | input reset; 7 | input clk; 8 | input [31:0]data; 9 | wire clk_5ms; 10 | reg [2:0]select = 0; 11 | Fdiv utt(reset,32'd50000,clk,clk_5ms); 12 | 13 | always @(posedge clk_5ms or negedge reset) begin 14 | if(!reset)begin 15 | select <= 3'd0; 16 | end 17 | else begin 18 | select <= select + 3'd1; 19 | end 20 | end 21 | 22 | reg [3:0]data_in; 23 | show sh(data_in,select,AN,seg); 24 | always @(*) begin 25 | case (select) 26 | 7: data_in = data[31:28]; 27 | 6: data_in = data[27:24]; 28 | 5: data_in = data[23:20]; 29 | 4: data_in = data[19:16]; 30 | 3: data_in = data[15:12]; 31 | 2: data_in = data[11:8]; 32 | 1: data_in = data[7:4]; 33 | 0: data_in = data[3:0]; 34 | endcase 35 | end 36 | endmodule 37 | 38 | 39 | module show(data,seletct,AN,seg); 40 | input [3:0]data; 41 | input [2:0]seletct; 42 | output reg[7:0]AN; 43 | output reg [7:0]seg; 44 | 45 | always @(*) begin 46 | case(seletct) 47 | 0:AN = 8'b11111110; 48 | 1:AN = 8'b11111101; 49 | 2:AN = 8'b11111011; 50 | 3:AN = 8'b11110111; 51 | 4:AN = 8'b11101111; 52 | 5:AN = 8'b11011111; 53 | 6:AN = 8'b10111111; 54 | 7:AN = 8'b01111111; 55 | default: AN = 8'Hff; 56 | endcase 57 | end 58 | 59 | always @(*) begin 60 | case (data) 61 | 0:seg = 8'b00000011; 62 | 1:seg = 8'b10011111; 63 | 2:seg = 8'b00100101; 64 | 3:seg = 8'b00001101; 65 | 4:seg = 8'b10011001; 66 | 5:seg = 8'b01001001; 67 | 6:seg = 8'b01000001; 68 | 7:seg = 8'b00011111; 69 | 8:seg = 8'b00000001; 70 | 9:seg = 8'b00001001; 71 | 10:seg = 8'b00010001; 72 | 11:seg = 8'b11000001; 73 | 12:seg = 8'b01100011; 74 | 13:seg = 8'b10000101; 75 | 14:seg = 8'b01100001; 76 | 15:seg = 8'b01110001; 77 | default:seg = 8'Hff; 78 | endcase 79 | end 80 | endmodule -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.srcs/utils_1/imports/synth_1/TOP.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/RegisterFile/RegisterFile.srcs/utils_1/imports/synth_1/TOP.dcp -------------------------------------------------------------------------------- /RegisterFile/RegisterFile.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 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https://raw.githubusercontent.com/mrxYan6/Computer-organization-experiment/0e503f76e7de1e60598ffd7ba81f3babdb257596/RegisterFile/TOP.bit --------------------------------------------------------------------------------