├── .github ├── FUNDING.yml ├── ISSUE_TEMPLATE │ ├── bug_report.md │ └── feature_request.md └── workflows │ ├── ci.yml │ ├── codeql-analysis.yml │ └── publish-marketplace.yml ├── .gitignore ├── .prettierrc.js ├── .vscode ├── extensions.json ├── launch.json ├── settings.json └── tasks.json ├── .vscodeignore ├── CHANGELOG.md ├── CONTRIBUTING.md ├── LICENSE ├── README.md ├── configs ├── BSV.configuration.json ├── sdc.configuration.json ├── systemverilog.configuration.json ├── tcl.configuration.json ├── ucfconstraints.configuration.json ├── verilog-filelist.configuration.json ├── verilog.configuration.json ├── verilogams.configuration.json └── vhdl.configuration.json ├── eslint.config.mjs ├── images ├── icon.png └── sample.gif ├── language_examples ├── fibonacci_verilog │ ├── .gitignore │ ├── LICENSE │ ├── README.md │ ├── docs │ │ └── timing_chart.png │ ├── fpga │ │ ├── de1soc │ │ │ ├── fpga_top.qpf │ │ │ ├── fpga_top.qsf │ │ │ ├── fpga_top.sdc │ │ │ └── fpga_top.v │ │ └── mu500rx │ │ │ ├── displayik_7seg_16.v │ │ │ ├── fpga_top.qpf │ │ │ ├── fpga_top.qsf │ │ │ └── fpga_top.v │ ├── make_clean.sh │ ├── make_tb.sh │ ├── rtl │ │ └── fib.v │ └── testbench │ │ └── tb_fib.v ├── stopwatch_verilog │ ├── LICENSE │ ├── README.md │ ├── chattering.v │ ├── chattering.xlsx │ ├── clean.sh │ ├── cnt10.v │ ├── control.v │ ├── divider.v │ ├── seg7dec.v │ ├── stopwatch.qpf │ ├── stopwatch.qsf │ └── stopwatch.v ├── systemverilog │ ├── implication.sv │ ├── module_1.sv │ ├── module_instance.sv │ ├── property_1.sv │ └── with_parameter_port_list.sv ├── verilog_building_block │ ├── .gitignore │ ├── .travis.yml │ ├── LICENSE │ ├── README.md │ ├── make_clean.sh │ ├── make_test.sh │ ├── rtl │ │ ├── adder_tree.v │ │ ├── altera │ │ │ ├── memory.mif │ │ │ ├── ram_sp_altera.qip │ │ │ └── ram_sp_altera.v │ │ ├── button_debounce.v │ │ ├── ram_sp.v │ │ ├── shift_register.v │ │ ├── synchronizer.v │ │ └── uart_rx.v │ ├── script │ │ └── convert2mif.py │ └── test │ │ ├── ram_content.txt │ │ ├── tb_adder_tree.v │ │ ├── tb_button_debounce.v │ │ ├── tb_ram_sp.v │ │ ├── tb_shift_register.v │ │ ├── tb_synchronizer.v │ │ └── tb_uart_rx.v └── vga_display │ ├── LICENSE │ ├── README.md │ ├── make.sh │ ├── tb_vga_display.v │ └── vga_display.v ├── package.json ├── renovate.json ├── snippets ├── bsv.json ├── systemverilog.json ├── verilog.json └── verilogams.json ├── src ├── BsvProvider.ts ├── bsvLanguageServer │ └── bsvLanguage.ts ├── bsvjs │ └── syntaxes │ │ ├── bsv.interp │ │ ├── bsv.tokens │ │ ├── bsvLexer.interp │ │ ├── bsvLexer.tokens │ │ ├── bsvLexer.ts │ │ ├── bsvListener.ts │ │ ├── bsvParser.ts │ │ └── bsvVisitor.ts ├── commands │ └── ModuleInstantiation.ts ├── ctags.ts ├── extension.ts ├── extensionManager.ts ├── hover.ts ├── linter │ ├── BaseLinter.ts │ ├── IcarusLinter.ts │ ├── LintManager.ts │ ├── ModelsimLinter.ts │ ├── SlangLinter.ts │ ├── VerilatorLinter.ts │ └── XvlogLinter.ts ├── logger.ts ├── providers │ ├── CompletionItemProvider.ts │ ├── DefinitionProvider.ts │ ├── DocumentSymbolProvider.ts │ ├── FormatProvider.ts │ └── HoverProvider.ts └── test │ ├── bsv.ts │ ├── runTest.ts │ └── suite │ ├── bsv.test.ts │ ├── extension.test.ts │ └── index.ts ├── syntaxes ├── BSV.tmLanguage.json ├── bsc-lib │ ├── AlignedFIFOs.bsv │ ├── Arbiter.bsv │ ├── Arbitrate.bsv │ ├── Array.bsv │ ├── BRAM.bsv │ ├── BRAMCore.bsv │ ├── BRAMFIFO.bsv │ ├── BRAM_Compat.bsv │ ├── BUtils.bsv │ ├── BitUtils.bsv │ ├── BuildVector.bsv │ ├── BypassReg.bsv │ ├── CBus.bsv │ ├── CRC.bsv │ ├── Clocks.bsv │ ├── Cntrs.bsv │ ├── CommitIfc.bsv │ ├── CompletionBuffer.bsv │ ├── Complex.bsv │ ├── Contexts.bsv │ ├── DefaultValue.bsv │ ├── Divide.bsv │ ├── DummyDriver.bsv │ ├── EdgeDetect.bsv │ ├── FIFOF_.bsv │ ├── FIFOLevel.bsv │ ├── FShow.bsv │ ├── FixedPoint.bsv │ ├── FloatingPoint.bsv │ ├── Gearbox.bsv │ ├── Gray.bsv │ ├── GrayCounter.bsv │ ├── HList.bsv │ ├── Inout.bsv │ ├── LBus.bsv │ ├── LevelFIFO.bsv │ ├── MIMO.bsv │ ├── Math.bsv │ ├── Memory.bsv │ ├── Misc.bsv │ ├── ModuleCollect.bsv │ ├── ModuleContext.bsv │ ├── NullCrossingFIFOF.bsv │ ├── NumberTypes.bsv │ ├── PAClib.bsv │ ├── PreludeBSV.bsv │ ├── Printf.bsv │ ├── Probe.bsv │ ├── ProbeWire.bsv │ ├── RWire.bsv │ ├── Randomizable.bsv │ ├── SpecialFIFOs.bsv │ ├── SquareRoot.bsv │ ├── StmtFSMUtil.bsv │ ├── TieOff.bsv │ ├── TriState.bsv │ ├── TurboFIFO.bsv │ ├── UniqueWrappers.bsv │ ├── UnitAppendList.bsv │ └── ZBus.bsv ├── bsv.g4 ├── codeblock.json ├── sdc.tmLanguage.json ├── systemverilog.tmLanguage.json ├── systemverilog.tmLanguage.yaml ├── tcl.tmlanguage.json ├── ucf.tmLanguage.json ├── verilog-filelist.tmLanguage.json ├── verilog.tmLanguage.json ├── verilogams.tmLanguage.json └── vhdl.tmLanguage.json └── tsconfig.json /.github/FUNDING.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.github/FUNDING.yml -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug_report.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.github/ISSUE_TEMPLATE/bug_report.md -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/feature_request.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.github/ISSUE_TEMPLATE/feature_request.md -------------------------------------------------------------------------------- /.github/workflows/ci.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.github/workflows/ci.yml -------------------------------------------------------------------------------- /.github/workflows/codeql-analysis.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.github/workflows/codeql-analysis.yml -------------------------------------------------------------------------------- /.github/workflows/publish-marketplace.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.github/workflows/publish-marketplace.yml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.gitignore -------------------------------------------------------------------------------- /.prettierrc.js: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.prettierrc.js -------------------------------------------------------------------------------- /.vscode/extensions.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.vscode/extensions.json -------------------------------------------------------------------------------- /.vscode/launch.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.vscode/launch.json -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.vscode/settings.json -------------------------------------------------------------------------------- /.vscode/tasks.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.vscode/tasks.json -------------------------------------------------------------------------------- /.vscodeignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/.vscodeignore -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/CHANGELOG.md -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/CONTRIBUTING.md -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/README.md -------------------------------------------------------------------------------- /configs/BSV.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/BSV.configuration.json -------------------------------------------------------------------------------- /configs/sdc.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/sdc.configuration.json -------------------------------------------------------------------------------- /configs/systemverilog.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/systemverilog.configuration.json -------------------------------------------------------------------------------- /configs/tcl.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/tcl.configuration.json -------------------------------------------------------------------------------- /configs/ucfconstraints.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/ucfconstraints.configuration.json -------------------------------------------------------------------------------- /configs/verilog-filelist.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/verilog-filelist.configuration.json -------------------------------------------------------------------------------- /configs/verilog.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/verilog.configuration.json -------------------------------------------------------------------------------- /configs/verilogams.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/verilogams.configuration.json -------------------------------------------------------------------------------- /configs/vhdl.configuration.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/configs/vhdl.configuration.json -------------------------------------------------------------------------------- /eslint.config.mjs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/eslint.config.mjs -------------------------------------------------------------------------------- /images/icon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/images/icon.png -------------------------------------------------------------------------------- /images/sample.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/images/sample.gif -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/.gitignore -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/LICENSE -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/README.md -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/docs/timing_chart.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/docs/timing_chart.png -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/fpga/de1soc/fpga_top.qpf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/fpga/de1soc/fpga_top.qpf -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/fpga/de1soc/fpga_top.qsf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/fpga/de1soc/fpga_top.qsf -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/fpga/de1soc/fpga_top.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/fpga/de1soc/fpga_top.sdc -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/fpga/de1soc/fpga_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/fpga/de1soc/fpga_top.v -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/fpga/mu500rx/displayik_7seg_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/fpga/mu500rx/displayik_7seg_16.v -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/fpga/mu500rx/fpga_top.qpf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/fpga/mu500rx/fpga_top.qpf -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/fpga/mu500rx/fpga_top.qsf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/fpga/mu500rx/fpga_top.qsf -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/fpga/mu500rx/fpga_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/fpga/mu500rx/fpga_top.v -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/make_clean.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/make_clean.sh -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/make_tb.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/make_tb.sh -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/rtl/fib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/rtl/fib.v -------------------------------------------------------------------------------- /language_examples/fibonacci_verilog/testbench/tb_fib.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/fibonacci_verilog/testbench/tb_fib.v -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/LICENSE -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/README.md -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/chattering.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/chattering.v -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/chattering.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/chattering.xlsx -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/clean.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/clean.sh -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/cnt10.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/cnt10.v -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/control.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/control.v -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/divider.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/divider.v -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/seg7dec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/seg7dec.v -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/stopwatch.qpf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/stopwatch.qpf -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/stopwatch.qsf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/stopwatch.qsf -------------------------------------------------------------------------------- /language_examples/stopwatch_verilog/stopwatch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/stopwatch_verilog/stopwatch.v -------------------------------------------------------------------------------- /language_examples/systemverilog/implication.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/systemverilog/implication.sv -------------------------------------------------------------------------------- /language_examples/systemverilog/module_1.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/systemverilog/module_1.sv -------------------------------------------------------------------------------- /language_examples/systemverilog/module_instance.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/systemverilog/module_instance.sv -------------------------------------------------------------------------------- /language_examples/systemverilog/property_1.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/systemverilog/property_1.sv -------------------------------------------------------------------------------- /language_examples/systemverilog/with_parameter_port_list.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/systemverilog/with_parameter_port_list.sv -------------------------------------------------------------------------------- /language_examples/verilog_building_block/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/.gitignore -------------------------------------------------------------------------------- /language_examples/verilog_building_block/.travis.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/.travis.yml -------------------------------------------------------------------------------- /language_examples/verilog_building_block/LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/LICENSE -------------------------------------------------------------------------------- /language_examples/verilog_building_block/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/README.md -------------------------------------------------------------------------------- /language_examples/verilog_building_block/make_clean.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/make_clean.sh -------------------------------------------------------------------------------- /language_examples/verilog_building_block/make_test.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/make_test.sh -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/adder_tree.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/adder_tree.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/altera/memory.mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/altera/memory.mif -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/altera/ram_sp_altera.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/altera/ram_sp_altera.qip -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/altera/ram_sp_altera.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/altera/ram_sp_altera.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/button_debounce.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/button_debounce.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/ram_sp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/ram_sp.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/shift_register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/shift_register.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/synchronizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/synchronizer.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/rtl/uart_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/rtl/uart_rx.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/script/convert2mif.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/script/convert2mif.py -------------------------------------------------------------------------------- /language_examples/verilog_building_block/test/ram_content.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/test/ram_content.txt -------------------------------------------------------------------------------- /language_examples/verilog_building_block/test/tb_adder_tree.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/test/tb_adder_tree.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/test/tb_button_debounce.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/test/tb_button_debounce.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/test/tb_ram_sp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/test/tb_ram_sp.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/test/tb_shift_register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/test/tb_shift_register.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/test/tb_synchronizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/test/tb_synchronizer.v -------------------------------------------------------------------------------- /language_examples/verilog_building_block/test/tb_uart_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/verilog_building_block/test/tb_uart_rx.v -------------------------------------------------------------------------------- /language_examples/vga_display/LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/vga_display/LICENSE -------------------------------------------------------------------------------- /language_examples/vga_display/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/vga_display/README.md -------------------------------------------------------------------------------- /language_examples/vga_display/make.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/vga_display/make.sh -------------------------------------------------------------------------------- /language_examples/vga_display/tb_vga_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/vga_display/tb_vga_display.v -------------------------------------------------------------------------------- /language_examples/vga_display/vga_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/language_examples/vga_display/vga_display.v -------------------------------------------------------------------------------- /package.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/package.json -------------------------------------------------------------------------------- /renovate.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/renovate.json -------------------------------------------------------------------------------- /snippets/bsv.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/snippets/bsv.json -------------------------------------------------------------------------------- /snippets/systemverilog.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/snippets/systemverilog.json -------------------------------------------------------------------------------- /snippets/verilog.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/snippets/verilog.json -------------------------------------------------------------------------------- /snippets/verilogams.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/snippets/verilogams.json -------------------------------------------------------------------------------- /src/BsvProvider.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/BsvProvider.ts -------------------------------------------------------------------------------- /src/bsvLanguageServer/bsvLanguage.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvLanguageServer/bsvLanguage.ts -------------------------------------------------------------------------------- /src/bsvjs/syntaxes/bsv.interp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvjs/syntaxes/bsv.interp -------------------------------------------------------------------------------- /src/bsvjs/syntaxes/bsv.tokens: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvjs/syntaxes/bsv.tokens -------------------------------------------------------------------------------- /src/bsvjs/syntaxes/bsvLexer.interp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvjs/syntaxes/bsvLexer.interp -------------------------------------------------------------------------------- /src/bsvjs/syntaxes/bsvLexer.tokens: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvjs/syntaxes/bsvLexer.tokens -------------------------------------------------------------------------------- /src/bsvjs/syntaxes/bsvLexer.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvjs/syntaxes/bsvLexer.ts -------------------------------------------------------------------------------- /src/bsvjs/syntaxes/bsvListener.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvjs/syntaxes/bsvListener.ts -------------------------------------------------------------------------------- /src/bsvjs/syntaxes/bsvParser.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvjs/syntaxes/bsvParser.ts -------------------------------------------------------------------------------- /src/bsvjs/syntaxes/bsvVisitor.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/bsvjs/syntaxes/bsvVisitor.ts -------------------------------------------------------------------------------- /src/commands/ModuleInstantiation.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/commands/ModuleInstantiation.ts -------------------------------------------------------------------------------- /src/ctags.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/ctags.ts -------------------------------------------------------------------------------- /src/extension.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/extension.ts -------------------------------------------------------------------------------- /src/extensionManager.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/extensionManager.ts -------------------------------------------------------------------------------- /src/hover.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/hover.ts -------------------------------------------------------------------------------- /src/linter/BaseLinter.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/linter/BaseLinter.ts -------------------------------------------------------------------------------- /src/linter/IcarusLinter.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/linter/IcarusLinter.ts -------------------------------------------------------------------------------- /src/linter/LintManager.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/linter/LintManager.ts -------------------------------------------------------------------------------- /src/linter/ModelsimLinter.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/linter/ModelsimLinter.ts -------------------------------------------------------------------------------- /src/linter/SlangLinter.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/linter/SlangLinter.ts -------------------------------------------------------------------------------- /src/linter/VerilatorLinter.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/linter/VerilatorLinter.ts -------------------------------------------------------------------------------- /src/linter/XvlogLinter.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/linter/XvlogLinter.ts -------------------------------------------------------------------------------- /src/logger.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/logger.ts -------------------------------------------------------------------------------- /src/providers/CompletionItemProvider.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/providers/CompletionItemProvider.ts -------------------------------------------------------------------------------- /src/providers/DefinitionProvider.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/providers/DefinitionProvider.ts -------------------------------------------------------------------------------- /src/providers/DocumentSymbolProvider.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/providers/DocumentSymbolProvider.ts -------------------------------------------------------------------------------- /src/providers/FormatProvider.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/providers/FormatProvider.ts -------------------------------------------------------------------------------- /src/providers/HoverProvider.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/providers/HoverProvider.ts -------------------------------------------------------------------------------- /src/test/bsv.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/test/bsv.ts -------------------------------------------------------------------------------- /src/test/runTest.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/test/runTest.ts -------------------------------------------------------------------------------- /src/test/suite/bsv.test.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/test/suite/bsv.test.ts -------------------------------------------------------------------------------- /src/test/suite/extension.test.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/test/suite/extension.test.ts -------------------------------------------------------------------------------- /src/test/suite/index.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/src/test/suite/index.ts -------------------------------------------------------------------------------- /syntaxes/BSV.tmLanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/BSV.tmLanguage.json -------------------------------------------------------------------------------- /syntaxes/bsc-lib/AlignedFIFOs.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/AlignedFIFOs.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Arbiter.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Arbiter.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Arbitrate.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Arbitrate.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Array.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Array.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/BRAM.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/BRAM.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/BRAMCore.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/BRAMCore.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/BRAMFIFO.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/BRAMFIFO.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/BRAM_Compat.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/BRAM_Compat.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/BUtils.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/BUtils.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/BitUtils.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/BitUtils.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/BuildVector.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/BuildVector.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/BypassReg.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/BypassReg.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/CBus.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/CBus.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/CRC.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/CRC.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Clocks.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Clocks.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Cntrs.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Cntrs.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/CommitIfc.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/CommitIfc.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/CompletionBuffer.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/CompletionBuffer.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Complex.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Complex.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Contexts.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Contexts.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/DefaultValue.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/DefaultValue.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Divide.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Divide.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/DummyDriver.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/DummyDriver.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/EdgeDetect.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/EdgeDetect.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/FIFOF_.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/FIFOF_.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/FIFOLevel.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/FIFOLevel.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/FShow.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/FShow.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/FixedPoint.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/FixedPoint.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/FloatingPoint.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/FloatingPoint.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Gearbox.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Gearbox.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Gray.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Gray.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/GrayCounter.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/GrayCounter.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/HList.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/HList.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Inout.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Inout.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/LBus.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/LBus.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/LevelFIFO.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/LevelFIFO.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/MIMO.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/MIMO.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Math.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Math.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Memory.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Memory.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Misc.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Misc.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/ModuleCollect.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/ModuleCollect.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/ModuleContext.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/ModuleContext.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/NullCrossingFIFOF.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/NullCrossingFIFOF.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/NumberTypes.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/NumberTypes.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/PAClib.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/PAClib.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/PreludeBSV.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/PreludeBSV.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Printf.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Printf.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Probe.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Probe.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/ProbeWire.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/ProbeWire.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/RWire.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/RWire.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/Randomizable.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/Randomizable.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/SpecialFIFOs.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/SpecialFIFOs.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/SquareRoot.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/SquareRoot.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/StmtFSMUtil.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/StmtFSMUtil.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/TieOff.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/TieOff.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/TriState.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/TriState.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/TurboFIFO.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/TurboFIFO.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/UniqueWrappers.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/UniqueWrappers.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/UnitAppendList.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/UnitAppendList.bsv -------------------------------------------------------------------------------- /syntaxes/bsc-lib/ZBus.bsv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsc-lib/ZBus.bsv -------------------------------------------------------------------------------- /syntaxes/bsv.g4: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/bsv.g4 -------------------------------------------------------------------------------- /syntaxes/codeblock.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/codeblock.json -------------------------------------------------------------------------------- /syntaxes/sdc.tmLanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/sdc.tmLanguage.json -------------------------------------------------------------------------------- /syntaxes/systemverilog.tmLanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/systemverilog.tmLanguage.json -------------------------------------------------------------------------------- /syntaxes/systemverilog.tmLanguage.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/systemverilog.tmLanguage.yaml -------------------------------------------------------------------------------- /syntaxes/tcl.tmlanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/tcl.tmlanguage.json -------------------------------------------------------------------------------- /syntaxes/ucf.tmLanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/ucf.tmLanguage.json -------------------------------------------------------------------------------- /syntaxes/verilog-filelist.tmLanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/verilog-filelist.tmLanguage.json -------------------------------------------------------------------------------- /syntaxes/verilog.tmLanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/verilog.tmLanguage.json -------------------------------------------------------------------------------- /syntaxes/verilogams.tmLanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/verilogams.tmLanguage.json -------------------------------------------------------------------------------- /syntaxes/vhdl.tmLanguage.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/syntaxes/vhdl.tmLanguage.json -------------------------------------------------------------------------------- /tsconfig.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mshr-h/vscode-verilog-hdl-support/HEAD/tsconfig.json --------------------------------------------------------------------------------