├── .gitignore ├── LICENSE ├── README.md ├── Verilog ├── .gitignore ├── Am2901.v ├── Am2909.v ├── Am2911.v ├── CPU6.v ├── CPU6TestBench.v ├── Clock.v ├── CodeROM.v ├── ControlPanel.py ├── Instructions.v ├── LEDPanel.v ├── Makefile ├── MapROM.v ├── Microcode.py ├── PLL.v ├── RegisterRAM.v ├── build.bat ├── iCE40.v ├── ice40_alchitry_cu.pcf ├── iceblink40_vq100.pcf ├── parse_vcd.py ├── programs │ ├── alu_test.txt │ ├── blink.txt │ ├── bnz_test.txt │ ├── cylon.txt │ ├── diag.txt │ ├── hellorld.txt │ └── inst_test.txt └── roms │ ├── CPU-6309.txt │ └── CodeROM.txt ├── datapath.excalidraw └── images ├── Centurion1.gif ├── Centurion3.gif ├── DCX.png ├── Datapath.png ├── NOP_DLY.png └── cylon.gif /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | __pycache__/ 3 | .ipynb_checkpoints/ 4 | 5 | vcd/ 6 | *.vcd 7 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Madhu Siddalingaiah 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Centurion Hardware Resurrection 2 | 3 | This directory contains an [FPGA](https://en.wikipedia.org/wiki/Field-programmable_gate_array) implementation of the [Centurion Minicomputer](https://github.com/Nakazoto/CenturionComputer/wiki). 4 | 5 | The Centurion was an 8-bit minicomputer designed and built by Warrex Computer Corporation, headquartered in Richardson, Texas. The company operated from the mid 1970's into the mid 1980's, delivering approximately 1000 computers to customers in Texas, Oklahoma, and others. The computers were used for accounting and business functions in medium sized companies. 6 | 7 | The Centurion was made of almost entirely TTL MSI logic on a handful of PC boards in a single rack. Earlier models relied on magnetic core memory, later models used MOS memory up to 256 kB. It was technologically similar to the DEC VAX 11/780 or Data General Nova, but smaller and lower priced. Competition from even lower cost microcomputers, particularly the IBM XT and AT in the 1980's, led to decreased sales and the end of the line. 8 | 9 | Below is a picure of CPU6 board. Notice the prominent [Am2900 series](https://en.wikipedia.org/wiki/AMD_Am2900) bit slice components in center of the board. The HDL design described below implements the behavior of each of these components. The row of seven 2kx8 [EPROMs](https://en.wikipedia.org/wiki/EPROM) in the upper left contain about 2048 words of [microcode](https://en.wikipedia.org/wiki/Microcode), which is the true personality of the [CPU6 instruction set](https://github.com/Nakazoto/CenturionComputer/wiki/Instructions). 10 | 11 | ![CPU6](https://github.com/Nakazoto/CenturionComputer/raw/main/Computer/CPU6%20Board/HiRes%20Photos/CPU6_HiRes_Scan_Front.jpg "CPU6") 12 | 13 | ## Simulation 14 | 15 | The [Verilog](https://en.wikipedia.org/wiki/Verilog) implementation was simulated with [Icarus Verilog](http://iverilog.icarus.com/), specifically, [Icarus Verilog for Windows](https://bleyer.org/icarus/). 16 | 17 | The build process is straightforward: 18 | 19 | ``` 20 | > cd Verilog 21 | > iverilog -o CPU6TestBench CPU6TestBench.v 22 | > vvp CPU6TestBench 23 | ``` 24 | 25 | The simulation output is saved in the ```Verilog/vcd``` directory. It can be viewed using [GTK Wave](http://gtkwave.sourceforge.net/). 26 | 27 | Simulation supports several trace levels for debugging purposes. Uncomment any of the following macros in CPU6TestBench.v to enable tracing: 28 | 29 | ``` 30 | // `define TRACE_I // trace instructions 31 | // `define TRACE_WR // trace bus writes 32 | // `define TRACE_RD // trace bus reads 33 | // `define TRACE_UC // trace microcode 34 | ``` 35 | 36 | ## Synthesis 37 | 38 | [Project IceStorm](https://clifford.at/icestorm) open source tools were used for synthesis. Below is a demonstration program running on an [Alchitry Cu](https://alchitry.com/boards/cu) FPGA board containing a [Lattice iCE40 HX8K](https://www.latticesemi.com/iCE40): 39 | 40 | ![Centurion1](images/cylon.gif "Running code") 41 | 42 | The iCE40 HX8K FPGA has 32 4kBit synchronous RAM blocks. Most of the block RAM is used for microcode (2k x 56-bit). Storing microcode in internal block RAM reduces the need for external storage, which is convenient. One RAM block is used for register RAM (256 bytes) and one more is used for a small amount of memory (instructions and data). External RAM will be connected in the future, limited internal block RAM is available for testing. 43 | 44 | This version is operating with a CPU clock of 5MHz, which is the estimated the clock rate of the original Centurion CPU6. This design can operate as high as 40MHz, many times faster the original. 45 | 46 | Synthesis is known to work on [WSL](https://docs.microsoft.com/en-us/windows/wsl/install) Ubuntu running on Windows 11. The following command will perform synthesis: 47 | 48 | ``` 49 | cd Verilog 50 | make 51 | ``` 52 | 53 | USB support on WSL requires [usbipd](https://devblogs.microsoft.com/commandline/connecting-usb-devices-to-wsl) for device programming in WSL. To connect a USB device to WSL Ubuntu, the following commands must be executed from an **administrator** command prompt on Windows: 54 | 55 | ``` 56 | usbipd wsl list 57 | ``` 58 | ``` 59 | usbipd wsl attach --busid 60 | ``` 61 | 62 | Where busid is the appropriate USB bus ID from the wsl list command above. The device should appear in WSL Ubuntu using ```lsusb```. 63 | 64 | The board can be programmed from WSL Ubuntu using: 65 | 66 | ``` 67 | make sudo-prog 68 | ``` 69 | 70 | Resource utilization and timing analysis is below: 71 | 72 | ``` 73 | Info: Device utilisation: 74 | Info: ICESTORM_LC: 5382/ 7680 70% 75 | Info: ICESTORM_RAM: 30/ 32 93% 76 | Info: SB_IO: 9/ 256 3% 77 | Info: SB_GB: 5/ 8 62% 78 | Info: ICESTORM_PLL: 1/ 2 50% 79 | Info: SB_WARMBOOT: 0/ 1 0% 80 | 81 | Info: Max frequency for clock 'clock_$glb_clk': 39.35 MHz (PASS at 12.00 MHz) 82 | Info: Max frequency for clock 'clock20MHz_$glb_clk': 362.45 MHz (PASS at 12.00 MHz) 83 | 84 | Info: Max delay posedge clock_$glb_clk -> : 2.29 ns 85 | ``` 86 | 87 | Most of the LCs (about 4000 or so) are used for page table lookup, as that is not pipelined and cannot use block RAM. Without the page table, only 1200 LCs are required. 88 | 89 | ## Architecture 90 | 91 | The CPU6 is an interesting design. It is based on the [AMD Am2900](https://en.wikipedia.org/wiki/AMD_Am2900) family of bit slice devices. The entire CPU fits on a single board, using two Am2901s to make an 8-bit ALU. The control unit is [microcoded](https://en.wikipedia.org/wiki/Microcode), using 2 Am2909 microsequencers, and 1 Am2911 microsequencer with a 2048 word x 56-bit microprogram stored in seven EPROMs. It is typical of minicomputers of that era. Discrete CPUs based on the Am2900 family were soon superceded by fully integrated VLSI CPUs, such as the [Intel 8086](https://en.wikipedia.org/wiki/Intel_8086), [Motorola 68000](https://en.wikipedia.org/wiki/Motorola_68000), and numerous others. 92 | 93 | Below is a sample microcode execution trace. The marker shows the beginning of the very first instruction after reset. It executes a NOP (no operation) and then DLY (delay 4.55 ms). 94 | 95 | ![DCX Instruction](images/NOP_DLY.png "DCX Instruction Execution") 96 | 97 | ## Datapath 98 | 99 | Below is the CPU data path with enables for busses and registers. The enables are controlled by the microcode word at the output of the pipeline register. 100 | 101 | ![Data path](images/Datapath.png "Data path") 102 | 103 | ## Status 104 | 105 | All CPU6 instruction tests pass. Interrupt and DMA logic is pending. 106 | 107 | ### Links 108 | 109 | * [Schematics](https://github.com/Meisaka/CenMiniCom) 110 | * [Schematics and Microcode](https://github.com/sjsoftware/centurion-cpu6) 111 | -------------------------------------------------------------------------------- /Verilog/.gitignore: -------------------------------------------------------------------------------- 1 | 2 | __pycache__/ 3 | .ipynb_checkpoints/ 4 | 5 | vcd/ 6 | *.vcd 7 | 8 | CPU6TestBench 9 | *.bin 10 | *.rpt 11 | -------------------------------------------------------------------------------- /Verilog/Am2901.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * This module implements the AMD 2901 bit slice Arithment Logic Unit (ALU). 4 | * 5 | * It closely follows the Am2901 data sheet, however some adjustments have been made for FPGA synthesis: 6 | * * Q3/RAM3 tristate lines are replaced with independent in/out wires 7 | * * Overflow is not computed for exclusive OR and exclusive NOR operations, defaulting to zero 8 | * * Register writeback is fully synchronous, which is behaviorally identical to the real Am2901 9 | * 10 | * See https://github.com/Nakazoto/CenturionComputer/blob/main/Computer/CPU6%20Board/Datasheets/am2901a.pdf 11 | */ 12 | module Am2901(input wire clock, input wire [3:0] din, input wire [3:0] aSel, 13 | input wire [3:0] bSel, input wire [2:0] aluSrc, input wire [2:0] aluOp, 14 | input wire [2:0] aluDest, input cin, output reg[3:0] yout, output reg cout, 15 | output reg fzero, output reg f3, output reg ovr, 16 | input wire q0_in, input wire ram0_in, input wire q3_in, input wire ram3_in, 17 | output reg q0_out, output reg ram0_out, output reg q3_out, output reg ram3_out); 18 | 19 | integer i; 20 | initial begin 21 | for (i=0;i<16;i=i+1) regs[i] = 0; 22 | q = 0; 23 | end 24 | 25 | reg [3:0] regs[0:15]; 26 | reg [3:0] q; 27 | reg [4:0] f; 28 | reg writeRam; 29 | reg writeQ; 30 | 31 | reg [3:0] a; 32 | reg [3:0] b; 33 | reg [3:0] r; 34 | reg [3:0] s; 35 | reg [3:0] qv; 36 | reg [3:0] bv; 37 | reg [3:0] fvalue; 38 | reg [3:0] p, g; 39 | reg c3, c4; 40 | 41 | always @(*) begin 42 | a = regs[aSel]; 43 | b = regs[bSel]; 44 | r = 0; 45 | s = 0; 46 | 47 | case (aluSrc) 48 | 0: begin r = a; s = q; end 49 | 1: begin r = a; s = b; end 50 | 2: begin r = 0; s = q; end 51 | 3: begin r = 0; s = b; end 52 | 4: begin r = 0; s = a; end 53 | 5: begin r = din; s = a; end 54 | 6: begin r = din; s = q; end 55 | 7: begin r = din; s = 0; end 56 | default: ; 57 | endcase 58 | 59 | p = r | s; 60 | g = r & s; 61 | 62 | case (aluOp) 63 | 0: ; 64 | 1: begin p = (~r) | s; g = (~r) & s; end 65 | 2: begin p = r | (~s); g = r & (~s); end 66 | 3: ; 67 | 4: ; 68 | 5: begin p = (~r) | s; g = (~r) & s; end 69 | 6: ; 70 | 7: ; 71 | endcase 72 | 73 | c4 = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & cin); 74 | c3 = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin); 75 | 76 | ovr = 0; 77 | 78 | case (aluOp) 79 | 0: begin f = r + s + cin; ovr = c3 ^ c4; end 80 | 1: begin f = s + ((~r) & 4'hf) + cin; ovr = c3 ^ c4; end 81 | 2: begin f = r + ((~s) & 4'hf) + cin; ovr = c3 ^ c4; end 82 | 3: begin f = r | s; ovr = (~(p[3]&p[2]&p[1]&p[0])) | cin; end 83 | 4: begin f = r & s; ovr = g[3]|g[2]|g[1]|g[0] | cin; end 84 | 5: begin f = (~r) & s; ovr = g[3]|g[2]|g[1]|g[0] | cin; end 85 | 6: begin f = r ^ s; end 86 | 7: begin f = ~(r ^ s); end 87 | endcase 88 | 89 | cout = f[4]; 90 | fzero = 0; 91 | if (f[3:0] == 0) begin 92 | fzero = 1; 93 | end 94 | f3 = f[3]; 95 | 96 | qv = 0; 97 | bv = 0; 98 | writeQ = 0; 99 | writeRam = 0; 100 | fvalue = f[3:0]; 101 | 102 | q0_out = q[0]; 103 | ram0_out = fvalue[0]; 104 | q3_out = q[3]; 105 | ram3_out = fvalue[3]; 106 | 107 | case (aluDest) 108 | 0: begin yout = fvalue; qv = fvalue; writeQ = 1; end 109 | 1: begin yout = fvalue; end 110 | 2: begin yout = a; bv = fvalue; writeRam = 1; end 111 | 3: begin yout = fvalue; bv = fvalue; writeRam = 1; end 112 | 4: begin yout = fvalue; qv = { q3_in, q[3:1] }; bv = { ram3_in, fvalue[3:1] }; writeRam = 1; writeQ = 1; end 113 | 5: begin yout = fvalue; bv = { ram3_in, fvalue[3:1] }; writeRam = 1; end 114 | 6: begin yout = fvalue; qv = { q[2:0], q0_in }; bv = { fvalue[2:0], ram0_in }; writeRam = 1; writeQ = 1; end 115 | 7: begin yout = fvalue; bv = { fvalue[2:0], ram0_in }; writeRam = 1; end 116 | endcase 117 | end 118 | 119 | always @(posedge clock) begin 120 | if (writeQ == 1) begin 121 | q <= qv; 122 | end 123 | if (writeRam == 1) begin 124 | regs[bSel] <= bv; 125 | end 126 | end 127 | endmodule 128 | -------------------------------------------------------------------------------- /Verilog/Am2909.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * This module implements the AMD 2909 bit slice microprogram sequencer. 4 | * 5 | * It closely follows the Am2909 data sheet. 6 | * 7 | * See https://github.com/Nakazoto/CenturionComputer/blob/main/Computer/CPU6%20Board/Datasheets/am2909_am2911.pdf 8 | */ 9 | module Am2909(input wire clock, input wire [3:0] din, input wire [3:0] rin, input wire [3:0] orin, 10 | input wire s0, input wire s1, input wire zero, input wire cin, input wire re, input wire fe, 11 | input wire pup, output reg [3:0] yout, output reg cout); 12 | 13 | integer i; 14 | initial begin 15 | pc = 0; 16 | ar = 0; 17 | sp = 3; 18 | yout = 0; 19 | cout = 0; 20 | mux = 0; 21 | stackWr = 0; 22 | for (i=0;i<4;i=i+1) stack[i] = 0; 23 | end 24 | 25 | reg [3:0] pc; 26 | reg [3:0] ar; 27 | reg [1:0] sp, stackAddr; 28 | reg [3:0] mux; 29 | reg stackWr; 30 | reg [3:0] stack[0:3]; 31 | 32 | // Guideline #3: When modeling combinational logic with an "always" 33 | // block, use blocking assignments. 34 | always @(*) begin 35 | stackWr = 0; 36 | stackAddr = sp; 37 | if (fe == 0) begin 38 | if (pup == 1) begin 39 | stackWr = 1; 40 | // Lookahead to pre-increment stack pointer 41 | stackAddr = sp + 1; 42 | end 43 | end 44 | 45 | case ({s1, s0}) 46 | 2'b00: mux = pc; 47 | 2'b01: mux = ar; 48 | 2'b10: mux = stack[stackAddr]; 49 | 2'b11: mux = din; 50 | default: mux = 0; 51 | endcase 52 | if (zero == 0) begin 53 | yout = 0; 54 | end else begin 55 | yout = mux | orin; 56 | end 57 | cout = 0; 58 | if (yout == 4'hf && cin == 1) begin 59 | cout = 1; 60 | end 61 | end 62 | 63 | // Guideline #1: When modeling sequential logic, use nonblocking 64 | // assignments. 65 | always @(posedge clock) begin 66 | if (stackWr == 1) begin 67 | stack[stackAddr] <= pc; 68 | end 69 | if (re == 0) begin 70 | ar <= rin; 71 | end 72 | if (fe == 0) begin 73 | if (pup == 1) begin 74 | sp <= sp + 1; 75 | end else begin 76 | sp <= sp - 1; 77 | end 78 | end 79 | pc <= yout; 80 | if (cin == 1) begin 81 | pc <= yout + 1; 82 | end 83 | end 84 | endmodule 85 | -------------------------------------------------------------------------------- /Verilog/Am2911.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * This module implements the AMD 2911 bit slice microprogram sequencer. 4 | * 5 | * It closely follows the Am2911 data sheet. 6 | * 7 | * See https://github.com/Nakazoto/CenturionComputer/blob/main/Computer/CPU6%20Board/Datasheets/am2909_am2911.pdf 8 | */ 9 | module Am2911(input wire clock, input wire [3:0] din, 10 | input wire s0, input wire s1, input wire zero, input wire cin, input wire re, input wire fe, 11 | input wire pup, output reg [3:0] yout, output reg cout); 12 | 13 | integer i; 14 | initial begin 15 | pc = 0; 16 | ar = 0; 17 | sp = 3; 18 | yout = 0; 19 | cout = 0; 20 | mux = 0; 21 | stackWr = 0; 22 | for (i=0;i<4;i=i+1) stack[i] = 0; 23 | end 24 | 25 | reg [3:0] pc; 26 | reg [3:0] ar; 27 | reg [1:0] sp, stackAddr; 28 | reg [3:0] mux; 29 | reg stackWr; 30 | reg [3:0] stack[0:3]; 31 | 32 | always @(*) begin 33 | stackWr = 0; 34 | stackAddr = sp; 35 | if (fe == 0) begin 36 | if (pup == 1) begin 37 | stackWr = 1; 38 | // Lookahead to pre-increment stack pointer 39 | stackAddr = sp + 1; 40 | end 41 | end 42 | 43 | case ({s1, s0}) 44 | 2'b00: mux = pc; 45 | 2'b01: mux = ar; 46 | 2'b10: mux = stack[stackAddr]; 47 | 2'b11: mux = din; 48 | default: mux = 0; 49 | endcase 50 | 51 | if (zero == 0) begin 52 | yout = 0; 53 | end else begin 54 | yout = mux; 55 | end 56 | cout = 0; 57 | if (yout == 4'hf && cin == 1) begin 58 | cout = 1; 59 | end 60 | end 61 | 62 | always @(posedge clock) begin 63 | if (stackWr == 1) begin 64 | stack[stackAddr] <= pc; 65 | end 66 | if (re == 0) begin 67 | ar <= din; 68 | end 69 | if (fe == 0) begin 70 | if (pup == 1) begin 71 | sp <= sp + 1; 72 | end else begin 73 | sp <= sp - 1; 74 | end 75 | end 76 | pc <= yout; 77 | if (cin == 1) begin 78 | pc <= yout + 1; 79 | end 80 | end 81 | endmodule 82 | -------------------------------------------------------------------------------- /Verilog/CPU6.v: -------------------------------------------------------------------------------- 1 | 2 | `include "Am2909.v" 3 | `include "Am2911.v" 4 | `include "Am2901.v" 5 | `include "CodeROM.v" 6 | `include "MapROM.v" 7 | `include "RegisterRAM.v" 8 | 9 | // Include instruction names for simulation instruction tracing 10 | `ifdef TRACE_I 11 | `include "Instructions.v" 12 | `endif 13 | 14 | /** 15 | * This module implements the Centurion CPU6. 16 | * The original Centurion used a clock with three difference phases. 17 | * This design requires only a single phase. 18 | * 19 | * See https://github.com/Nakazoto/CenturionComputer/wiki/CPU6-Board 20 | */ 21 | module CPU6(input wire reset, input wire clock, input wire [7:0] dataInBus, 22 | output reg writeEnBus, output wire [18:0] addressBus, output wire [7:0] dataOutBus); 23 | 24 | integer i; 25 | initial begin 26 | cycle_counter = 0; 27 | for (i=0; i<256; i=i+1) page_table[i] = 0; 28 | end 29 | 30 | assign dataOutBus = bus_write; 31 | wire [7:0] page_address = { memory_address[15:11], page_table_base }; 32 | wire [7:0] page_table_out = page_table[page_address]; 33 | wire [18:0] virtual_address = { page_table_out, memory_address[10:0] }; 34 | assign addressBus = virtual_address; 35 | // Register space read mux 36 | wire [7:0] dataInCPU = virtual_address[18:8] == 0 ? dataOutBus : dataInBus; 37 | 38 | /* 39 | * Instrumentation 40 | */ 41 | 42 | wire instruction_start = uc_rom_address_pipe == 11'h101; 43 | reg [31:0] cycle_counter; 44 | assign pc_increment = h11 == 5 ? 1 : 0; 45 | reg [10:0] uc_rom_address_pipe; 46 | 47 | `ifdef TRACE_I 48 | Instructions inst_map(); 49 | `endif 50 | 51 | /* 52 | * Rising edge triggered registers 53 | */ 54 | // Microcode pipeline F5/H5/J5/K5/L5/M5 74LS377, E5/D5 74LS174 55 | reg [55:0] pipeline; 56 | // work_address B2/C2/B5/C5 74LS669 57 | reg [15:0] work_address; 58 | // memory_address B1/C1/B6/C6 74LS669 59 | reg [15:0] memory_address; 60 | // register_index C13 74LS377 61 | reg [7:0] register_index; 62 | // result_register C9 74LS377 63 | reg [7:0] result_register; 64 | // swap_register C12/C11 74LS173 65 | reg [7:0] swap_register; 66 | // flags_register J9 74LS378 67 | reg [7:0] flags_register; 68 | // condition_codes M12 74LS378 69 | reg [3:0] condition_codes; 70 | // bus_read, bus_write A11/A12 Am2907 71 | reg [7:0] bus_read, bus_write; 72 | // interrupt_level D9 74LS378, only four bits used 73 | reg [3:0] interrupt_level; 74 | // Page table base register D11 74LS378 75 | reg [2:0] page_table_base; 76 | // write delay 77 | reg writEnDelayed; 78 | 79 | // 6309 ROM 80 | wire [7:0] map_rom_address = DPBus; 81 | wire [7:0] map_rom_data; 82 | MapROM map_rom(map_rom_address, map_rom_data); 83 | 84 | // Microcode ROM(s) 85 | wire [10:0] uc_rom_address; 86 | wire [55:0] uc_rom_data; 87 | CodeROM uc_rom(uc_rom_address, uc_rom_data); 88 | 89 | // Synchronous Register RAM 90 | wire bit53 = pipeline[53]; 91 | wire reg_low_select = bit53; 92 | // High/low register select, C14 74LS157 mux, D10 74LS02 NOR gate 93 | wire [3:0] reg_addr_hi = pipeline[55] ? interrupt_level : register_index[7:4]; 94 | wire [7:0] reg_ram_addr = { reg_addr_hi, register_index[3:1], ~(reg_low_select | register_index[0]) }; 95 | wire rr_write_en = k11 == 4; 96 | wire [7:0] reg_ram_data_in = result_register; 97 | wire [7:0] reg_ram_data_out; 98 | RegisterRAM reg_ram(clock, rr_write_en, reg_ram_addr, reg_ram_data_in, reg_ram_data_out); 99 | 100 | // Sequencer shared nets 101 | 102 | wire seq_fe = pipeline[27] & jsr_; 103 | wire seq_pup = pipeline[28]; 104 | wire seq_zero = !reset; 105 | 106 | /* 107 | * Am2909/2911 Microsequencers 108 | */ 109 | 110 | // Sequencer 0 (microcode address bits 3:0) 111 | wire [3:0] seq0_din = pipeline[19:16]; 112 | wire [3:0] seq0_rin = FBus[3:0]; 113 | reg [3:0] seq0_orin; 114 | wire seq0_s0 = ~(pipeline[29] & jsr_); 115 | wire seq0_s1 = ~(pipeline[30] & jsr_); 116 | wire seq0_cin = 1; 117 | reg seq0_re; 118 | wire [3:0] seq0_yout; 119 | wire seq0_cout; 120 | 121 | Am2909 seq0(clock, seq0_din, seq0_rin, seq0_orin, seq0_s0, seq0_s1, seq_zero, seq0_cin, 122 | seq0_re, seq_fe, seq_pup, seq0_yout, seq0_cout); 123 | 124 | // Case control 125 | wire case_ = pipeline[33]; 126 | 127 | // Microcode conditional subroutine calls 128 | reg jsr_; 129 | 130 | // Sequencer 1 (microcode address bits 7:4) 131 | wire [3:0] seq1_din = pipeline[23:20]; 132 | wire [3:0] seq1_rin = FBus[7:4]; 133 | reg [3:0] seq1_orin; 134 | wire seq1_s0 = ~(pipeline[31] & jsr_); 135 | wire seq1_s1 = ~(~(pipeline[54] & ~pipeline[32]) & jsr_); 136 | wire seq1_cin = seq0_cout; 137 | reg seq1_re; 138 | wire [3:0] seq1_yout; 139 | wire seq1_cout; 140 | 141 | Am2909 seq1(clock, seq1_din, seq1_rin, seq1_orin, seq1_s0, seq1_s1, seq_zero, seq1_cin, 142 | seq1_re, seq_fe, seq_pup, seq1_yout, seq1_cout); 143 | 144 | 145 | // Sequencer 2 (microcode address bits 10:8) 146 | wire [3:0] seq2_din = { 1'b0 , pipeline[26:24] }; // only 3 bits are used 147 | wire [3:0] seq2_rin; 148 | wire seq2_s0 = ~(pipeline[31] & jsr_); 149 | wire seq2_s1 = ~(pipeline[32] & jsr_); 150 | wire seq2_cin = seq1_cout; 151 | wire seq2_re = 1; 152 | wire [3:0] seq2_yout; 153 | wire seq2_cout; 154 | 155 | Am2911 seq2(clock, seq2_din, seq2_s0, seq2_s1, seq_zero, seq2_cin, seq2_re, seq_fe, 156 | seq_pup, seq2_yout, seq2_cout); 157 | 158 | assign uc_rom_address = { seq2_yout, seq1_yout, seq0_yout }; 159 | 160 | /* 161 | * Am2901 bit slice Arithmetic Logic Units (ALUs) 162 | */ 163 | // ALU shared nets 164 | wire [3:0] alu_a = pipeline[50:47]; 165 | wire [3:0] alu_b = pipeline[46:43]; 166 | wire [2:0] alu_src = pipeline[36:34]; 167 | wire [2:0] alu_op = pipeline[39:37]; 168 | wire [2:0] alu_dest = pipeline[42:40]; 169 | 170 | // F9 Am2901 ALU 0 (bits 3:0) 171 | wire [3:0] alu0_din = DPBus[3:0]; 172 | reg alu0_cin; 173 | wire [3:0] alu0_yout; 174 | wire alu0_cout; 175 | wire alu0_f0; 176 | wire alu0_f3; 177 | wire alu0_ovr; 178 | reg alu0_q0_in; 179 | wire alu0_ram0_in, alu0_q3_in, alu0_ram3_in; 180 | wire alu0_q0_out, alu0_ram0_out, alu0_q3_out, alu0_ram3_out; 181 | Am2901 alu0(clock, alu0_din, alu_a, alu_b, alu_src, alu_op, alu_dest, alu0_cin, 182 | alu0_yout, alu0_cout, alu0_f0, alu0_f3, alu0_ovr, 183 | alu0_q0_in, alu0_ram0_in, alu0_q3_in, alu0_ram3_in, 184 | alu0_q0_out, alu0_ram0_out, alu0_q3_out, alu0_ram3_out); 185 | 186 | // F7 Am2901 ALU 1 (bits 7:4) 187 | wire [3:0] alu1_din = DPBus[7:4]; 188 | wire alu1_cin = alu0_cout; 189 | wire [3:0] alu1_yout; 190 | wire alu1_cout; 191 | wire alu1_f0; 192 | wire alu1_f3; 193 | wire alu1_ovr; 194 | wire alu1_q0_in, alu1_ram0_in, alu1_q3_in; 195 | wire alu1_q0_out, alu1_ram0_out, alu1_q3_out, alu1_ram3_out; 196 | reg alu1_ram3_in; 197 | Am2901 alu1(clock, alu1_din, alu_a, alu_b, alu_src, alu_op, alu_dest, alu1_cin, 198 | alu1_yout, alu1_cout, alu1_f0, alu1_f3, alu1_ovr, 199 | alu1_q0_in, alu1_ram0_in, alu1_q3_in, alu1_ram3_in, 200 | alu1_q0_out, alu1_ram0_out, alu1_q3_out, alu1_ram3_out); 201 | 202 | wire alu_i7 = alu_dest[1]; 203 | 204 | assign alu1_q0_in = alu0_q3_out; 205 | assign alu1_ram0_in = alu0_ram3_out; 206 | assign alu0_q3_in = alu1_q0_out; 207 | assign alu0_ram3_in = alu1_ram0_out; 208 | 209 | assign alu1_q3_in = alu0_ram0_out; 210 | assign alu0_ram0_in = alu1_q3_out; 211 | 212 | // Page table B9/B10 93L422 213 | reg [7:0] page_table[0:255]; 214 | 215 | // Decoders 216 | // d2d3 is decoded before pipeline, but outputs are registered. 217 | wire [3:0] d2d3 = pipeline[3:0]; 218 | wire [1:0] e7 = pipeline[14:13]; 219 | wire [2:0] h11 = pipeline[12:10]; 220 | wire [2:0] k11 = pipeline[9:7]; 221 | wire [2:0] e6 = pipeline[6:4]; 222 | 223 | // Muxes 224 | 225 | // J10 Link/carry mux 74LS151 226 | wire j10_enable = pipeline[21]; 227 | wire [2:0] j10 = pipeline[24:22]; 228 | reg cc_l; 229 | 230 | // J11 Fault/overflow mux 74LS151 231 | wire j11_enable = pipeline[18]; 232 | wire [2:0] j11 = { flags_register[2], pipeline[20:19] }; 233 | reg cc_f; 234 | 235 | // J12 Minus/sign mux 74LS153 236 | wire [1:0] j12 = pipeline[17:16]; 237 | reg cc_m, cc_v; 238 | 239 | // F6 ALU carry in mux 74LS153 (half used) 240 | // H6 ALU shift mux 241 | wire [1:0] f6h6 = pipeline[52:51]; 242 | 243 | // K9 JSR mux 74151 244 | wire k9_enable = pipeline[15]; 245 | wire [2:0] k9 = pipeline[18:16]; 246 | 247 | // J13 OR0/OR1 mux 74LS153 248 | wire [1:0] j13 = pipeline[21:20]; 249 | 250 | // K13 OR2/OR3 mux 74LS153 251 | wire [1:0] k13 = pipeline[23:22]; 252 | 253 | // Constant (immediate data) 254 | wire [7:0] constant = ~pipeline[16+7:16]; 255 | 256 | // Internal Busses 257 | reg [7:0] DPBus; 258 | reg [7:0] FBus; 259 | 260 | wire bad_page_n = ~(virtual_address[18:13] == 6'h3f && virtual_address[11] == 1); 261 | wire reg_n = ~(~virtual_address[12] & ~(memory_address[9] | memory_address[10]) & 262 | ~(virtual_address[15] | virtual_address[16]) & ~memory_address[8] & 263 | ~(virtual_address[13] | virtual_address[14]) & ~(virtual_address[11] | virtual_address[12])); 264 | wire not_mem = ~(bad_page_n & reg_n); 265 | 266 | // Guideline #3: When modeling combinational logic with an "always" 267 | // block, use blocking assignments. 268 | always @(*) begin 269 | jsr_ = 1; // Inverted output 270 | if (k9_enable == 0) begin 271 | case (k9) 272 | 0: ; // Bus busy 273 | 1: jsr_ = register_index[0] | register_index[4]; 274 | 2: jsr_ = ~register_index[0]; 275 | 3: jsr_ = ~not_mem; // NOT.MEM 276 | 4: jsr_ = reg_n & ~virtual_address[18]; 277 | 5: ; // DMA interrupt active 278 | 6: ; // Parity error 279 | 7: ; // Interrupt 280 | endcase 281 | end 282 | 283 | // Carry in 284 | alu0_cin = 0; 285 | case (f6h6) 286 | 0: alu0_cin = 0; 287 | 1: alu0_cin = 1; 288 | 2: alu0_cin = flags_register[3]; 289 | 3: alu0_cin = 0; 290 | endcase 291 | 292 | // Rotate 293 | alu1_ram3_in = 0; 294 | alu0_q0_in = 0; 295 | if (alu_i7 == 0) begin 296 | // Right shift 297 | case (f6h6) 298 | 0: alu1_ram3_in = alu1_f3; 299 | 1: alu1_ram3_in = flags_register[3]; 300 | 2: alu1_ram3_in = alu0_q0_out; 301 | 3: alu1_ram3_in = alu1_cout; 302 | endcase 303 | end else begin 304 | // Left shift 305 | case (f6h6) 306 | 0: alu0_q0_in = 0; 307 | 1: alu0_q0_in = flags_register[3]; 308 | 2: alu0_q0_in = alu1_f3; 309 | 3: alu0_q0_in = 1; 310 | endcase 311 | end 312 | 313 | cc_l = 0; 314 | if (j10_enable == 0) begin 315 | case (j10) 316 | 0: cc_l = condition_codes[3]; 317 | 1: cc_l = ~condition_codes[3]; 318 | 2: cc_l = flags_register[3]; 319 | 3: cc_l = 1; 320 | 4: cc_l = result_register[4]; 321 | 5: cc_l = alu1_ram3_in; 322 | 6: cc_l = alu_i7 ? alu1_q3_out : alu0_ram0_out; 323 | 7: cc_l = alu0_q0_out; 324 | endcase 325 | end 326 | 327 | cc_f = 0; 328 | if (j11_enable == 0) begin 329 | case (j11) 330 | 0: cc_f = result_register[5]; 331 | 1: cc_f = 1; 332 | 2: cc_f = condition_codes[2]; 333 | 3: cc_f = 0; 334 | 4: cc_f = result_register[5]; 335 | 5: cc_f = 1; 336 | 6: cc_f = condition_codes[2]; 337 | 7: cc_f = 1; 338 | endcase 339 | end 340 | 341 | cc_m = 0; 342 | cc_v = 0; 343 | case (j12) 344 | 0: begin cc_m = condition_codes[1]; cc_v = 0; end 345 | 1: begin cc_m = flags_register[1]; cc_v = flags_register[0]; end 346 | 2: begin cc_m = result_register[6]; cc_v = result_register[7]; end 347 | 3: begin cc_m = flags_register[1]; cc_v = flags_register[0] & flags_register[5]; end 348 | endcase 349 | 350 | seq0_orin = 0; 351 | if (case_ == 0) begin 352 | case (j13) 353 | 0: begin seq0_orin[0] = flags_register[1]; seq0_orin[1] = flags_register[0]; end 354 | 1: begin seq0_orin[0] = flags_register[4]; seq0_orin[1] = flags_register[2]; end 355 | 2: begin seq0_orin[0] = ~virtual_address[18]; seq0_orin[1] = bad_page_n; end // OR0 = PA18; OR1 = BAD.PG; 356 | 3: ; // Not used 357 | endcase 358 | case (k13) 359 | 0: seq0_orin[3] = condition_codes[3]; // OR2 = INT.EN; 360 | 1: ; // OR2 = LVL15.Q; OR3 = INTR.Q; 361 | 2: ; // OR2 = E10.6.Q; OR3 = DMA13.Q; 362 | 3: ; // Not used 363 | endcase 364 | end 365 | 366 | seq1_orin = 0; 367 | 368 | seq0_re = 1; 369 | seq1_re = 1; 370 | if (e6 == 6) begin 371 | seq0_re = 0; 372 | seq1_re = 0; 373 | end 374 | 375 | // Datapath muxes 376 | DPBus = 0; 377 | 378 | // 74LS139 (D2), 74LS138 (D3) 379 | case (d2d3) 380 | 0: DPBus = swap_register; 381 | 1: DPBus = reg_ram_data_out; 382 | 2: DPBus = { ~memory_address[15:12], memory_address[11:8] }; 383 | 3: DPBus = memory_address[7:0]; 384 | 4: DPBus = swap_register; 385 | 5: DPBus = reg_ram_data_out; 386 | 6: DPBus = { ~memory_address[15:12], memory_address[11:8] }; 387 | 7: DPBus = memory_address[7:0]; 388 | 8: ; // DPBus = translated address hi, 17:11 (17 down), and top 3 bits together 389 | 9: DPBus = { ~condition_codes[0], ~condition_codes[1], ~condition_codes[2], ~condition_codes[3], 4'b0000 }; // low nibble is sense switches 390 | 10: DPBus = bus_read; 391 | 11: DPBus = 8'h0f; // read ILR (interrupt level register?) { A8 4 bits, H14 4 bits } 392 | 12: ; // read switch 2 other half of dip switches and condition codes? 393 | 13: DPBus = constant; 394 | 14: ; 395 | 15: ; 396 | endcase 397 | 398 | FBus = { alu1_yout, alu0_yout }; 399 | if (h11 == 6) begin 400 | FBus = map_rom_data; 401 | end 402 | end 403 | 404 | // Guideline #1: When modeling sequential logic, use nonblocking 405 | // assignments. 406 | always @(posedge clock, posedge reset) begin 407 | if (reset == 1) begin 408 | work_address <= 0; 409 | memory_address <= 0; 410 | register_index <= 0; 411 | result_register <= 0; 412 | swap_register <= 0; 413 | condition_codes <= 0; 414 | flags_register <= 0; 415 | writeEnBus <= 0; 416 | writEnDelayed <= 0; 417 | pipeline <= 56'h42abc618b781c0; // First microcode word. Synth prefers it this way. 418 | uc_rom_address_pipe <= 0; 419 | interrupt_level <= 0; 420 | bus_read <= 0; 421 | bus_write <= 0; 422 | page_table_base <= 0; 423 | end else begin 424 | pipeline <= uc_rom_data; 425 | uc_rom_address_pipe <= uc_rom_address; 426 | if (instruction_start == 1) begin 427 | cycle_counter <= 1; 428 | end else begin 429 | cycle_counter <= cycle_counter + 1; 430 | end 431 | 432 | `ifdef TRACE_I 433 | if (uc_rom_address_pipe == 11'h103) begin 434 | $display("%x F:%x C:%x L:%x A:%x%x B:%x%x X:%x%x Y:%x%x Z:%x%x S:%x%x C:%x%x | %x%s", 435 | virtual_address-1, flags_register, condition_codes, interrupt_level, 436 | reg_ram.memory[1], reg_ram.memory[0], 437 | reg_ram.memory[3], reg_ram.memory[2], 438 | reg_ram.memory[5], reg_ram.memory[4], 439 | reg_ram.memory[7], reg_ram.memory[6], 440 | reg_ram.memory[9], reg_ram.memory[8], 441 | reg_ram.memory[11], reg_ram.memory[10], 442 | reg_ram.memory[13], reg_ram.memory[12], 443 | DPBus, inst_map.instruction_map[DPBus]); 444 | end 445 | `endif 446 | `ifdef TRACE_UC 447 | if (jsr_ == 0) begin 448 | $display(" uC %x JSR %x%x%x", uc_rom_address_pipe, seq2_din, seq1_din, seq0_din); 449 | end 450 | if (case_ == 0) begin 451 | $display(" uC %x OR %x -> %x", uc_rom_address_pipe, seq0_orin, uc_rom_address_pipe | seq0_orin); 452 | end 453 | if (k11 == 3) begin 454 | $display(" uC F11.%d <= %d", alu_b[3:1], alu_b[0]); 455 | end 456 | `endif 457 | `ifdef TRACE_WR 458 | if (writeEnBus == 1) begin 459 | $display(" WR %x %x", memory_address, bus_write); 460 | end 461 | `endif 462 | `ifdef TRACE_RD 463 | if (e7 == 3) begin 464 | $display(" RD %x %x", memory_address, dataInCPU); 465 | end 466 | `endif 467 | 468 | // 74LS138 469 | case (e6) 470 | 0: ; 471 | 1: result_register <= FBus; 472 | 2: register_index <= FBus; // uC bit 53 might simplify 16 bit register write 473 | 3: interrupt_level <= FBus[7:4]; // load D9 474 | 4: page_table_base <= FBus[2:0]; // load page table base register 475 | 5: memory_address <= work_address; 476 | 6: ; // load AR on 2909s, see above 477 | 7: condition_codes <= { cc_l, cc_f, cc_m, cc_v } ; // load condition code register M12 478 | endcase 479 | 480 | // 74LS138 (only half used) 481 | case (e7) 482 | 0: ; 483 | 1: ; 484 | 2: flags_register <= { 1'b0, 1'b0, flags_register[0], alu0_cout, alu1_cout, alu1_ovr, alu1_f3, alu0_f0 & alu1_f0 }; 485 | 3: bus_read <= dataInCPU; 486 | endcase 487 | 488 | // 74LS138 489 | case (h11) 490 | 0: ; 491 | 1: ; // Begin bus read cycle 492 | 2: ; // Begin bus write cycle 493 | 3: // Load work_address high byte 494 | begin 495 | work_address[15:8] <= result_register; 496 | if (e6 == 5) begin 497 | work_address[15:8] <= memory_address[15:8]; 498 | end 499 | end 500 | 4: work_address <= work_address + 1; // WAR increment 501 | 5: memory_address <= memory_address + 1; // MAR increment 502 | 6: ; // Select FBus source (combinational) 503 | 7: swap_register <= { DPBus[3:0], DPBus[7:4] }; 504 | endcase 505 | 506 | writeEnBus <= writEnDelayed; 507 | writEnDelayed <= 0; 508 | 509 | // 74LS138 510 | case (k11) 511 | 0: ; 512 | 1: ; 513 | 2: ; 514 | 3: ; // enable F11 addressable latch, machine state, bus state, A0-2 on F11 are B1-3 and D input is B0 515 | 4: ; 516 | 5: page_table[page_address] <= result_register; 517 | 6: // Load work_address low byte 518 | begin 519 | work_address[7:0] <= result_register; 520 | if (e6 == 5) begin 521 | work_address[7:0] <= memory_address[7:0]; 522 | end 523 | end 524 | 7: begin bus_write <= FBus; writEnDelayed <= 1; end 525 | endcase 526 | end 527 | end 528 | endmodule 529 | -------------------------------------------------------------------------------- /Verilog/CPU6TestBench.v: -------------------------------------------------------------------------------- 1 | 2 | // `define TRACE_I // trace instructions 3 | // `define TRACE_WR // trace bus writes 4 | // `define TRACE_RD // trace bus reads 5 | // `define TRACE_UC // trace microcode 6 | 7 | `timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps 8 | `include "CPU6.v" 9 | `include "Clock.v" 10 | 11 | /** 12 | * This file contains a test bench for the CPU6. 13 | * It includes two RAM banks and one ROM. 14 | * Writing to the MUX UART prints to the console. 15 | */ 16 | module Memory(input wire clock, input wire [18:0] address, input wire write_en, input wire [7:0] data_in, 17 | output reg [7:0] data_out); 18 | 19 | reg [7:0] rom_cells[0:8191]; 20 | reg [7:0] ram_cells[0:4095]; 21 | reg [7:0] low_ram_cells[0:4095]; 22 | 23 | integer i; 24 | initial begin 25 | for (i=0; i<4096; i=i+1) ram_cells[i] = 8'h00; 26 | for (i=0; i<4096; i=i+1) low_ram_cells[i] = 8'h00; 27 | end 28 | 29 | wire rom_select = address[18:13] == 4; 30 | wire ram_select = address[18:12] == 7'hb; 31 | wire low_ram_select = address[18:12] == 0; 32 | wire [12:0] low13 = address[12:0]; 33 | wire [11:0] low12 = address[11:0]; 34 | 35 | always @(*) begin 36 | data_out = 0; 37 | case (address) 38 | 19'h3fd00: data_out = 8'h71; // Reset vector, JMP 8001 39 | 19'h3fd01: data_out = 8'h80; 40 | 19'h3fd02: data_out = 8'h01; 41 | 19'h3f200: data_out = 8'h02; // Diag MUX 0 status 42 | 19'h3f110: data_out = 8'h0d; // Diag DIP switches 43 | default: 44 | begin 45 | if (rom_select) data_out = rom_cells[low13]; 46 | if (ram_select) data_out = ram_cells[low12]; 47 | if (low_ram_select) data_out = low_ram_cells[low12]; 48 | end 49 | endcase 50 | end 51 | 52 | always @(posedge clock) begin 53 | if (write_en) begin 54 | if (ram_select) ram_cells[low12] <= data_in; 55 | if (low_ram_select) low_ram_cells[low12] <= data_in; 56 | end 57 | end 58 | endmodule 59 | 60 | module CPU6TestBench; 61 | initial begin 62 | $dumpfile("vcd/CPUTestBench.vcd"); 63 | $dumpvars(0, CPU6TestBench); 64 | 65 | $write("hellorld: "); 66 | $readmemh("programs/hellorld.txt", ram.rom_cells); 67 | sim_end = 0; #0 reset = 0; #50 reset = 1; #200 reset = 0; 68 | wait(sim_end == 1); 69 | 70 | $write("bnz_test: "); 71 | $readmemh("programs/bnz_test.txt", ram.rom_cells); 72 | sim_end = 0; #0 reset = 0; #50 reset = 1; #200 reset = 0; 73 | wait(sim_end == 1); 74 | 75 | $write("alu_test: "); 76 | $readmemh("programs/alu_test.txt", ram.rom_cells); 77 | sim_end = 0; #0 reset = 0; #50 reset = 1; #200 reset = 0; 78 | wait(sim_end == 1); 79 | 80 | // $readmemh("programs/diag.txt", ram.rom_cells); 81 | // sim_end = 0; #0 reset = 0; #50 reset = 1; #200 reset = 0; 82 | // #17000000 $finish; 83 | 84 | // $readmemh("programs/inst_test.txt", ram.rom_cells); 85 | // sim_end = 0; #0 reset = 0; #50 reset = 1; #200 reset = 0; 86 | // #4100000 $finish; 87 | 88 | // $readmemh("programs/cylon.txt", ram.rom_cells); 89 | // sim_end = 0; #0 reset = 0; #50 reset = 1; #200 reset = 0; 90 | 91 | // $readmemh("programs/blink.txt", ram.rom_cells); 92 | // sim_end = 0; #0 reset = 0; #50 reset = 1; #200 reset = 0; 93 | 94 | $display("All done!"); 95 | $finish; 96 | end 97 | 98 | reg [8*64:1] ramfile; 99 | wire writeEnBus; 100 | wire [7:0] data_c2r, data_r2c; 101 | wire [18:0] addressBus; 102 | wire clock; 103 | Clock cg0(clock); 104 | Memory ram(clock, addressBus, writeEnBus, data_c2r, data_r2c); 105 | reg reset; 106 | CPU6 cpu(reset, clock, data_r2c, writeEnBus, addressBus, data_c2r); 107 | reg sim_end; 108 | wire [7:0] cc = data_c2r & 8'h7f; 109 | 110 | always @(posedge clock) begin 111 | if (writeEnBus == 1) begin 112 | // Pretend there's a UART here :-) 113 | if (addressBus == 19'h3f201) begin 114 | if ((cc >= 32) || (cc == 9) || (cc == 10) || (cc == 13)) begin 115 | $write("%s", cc); 116 | end 117 | end 118 | // A hack to stop simulation 119 | if (addressBus == 19'h3f900 && data_c2r == 8'h01) begin 120 | sim_end <= 1; 121 | end 122 | end 123 | end 124 | endmodule 125 | 126 | /* 127 | 128 | TotalSeconds : 1.0773913 129 | TotalMilliseconds : 1077.3913 130 | 4.9 ms simulation time = 220 times slower than hardware Centurion 131 | About 22.75 kHz clock simulated 132 | 133 | First instruction is fetched about 40 uS after reset. 134 | 135 | Cycle counts 136 | 137 | Opcode: 0x01, cycles: 4 138 | Opcode: 0x02, cycles: 5 139 | Opcode: 0x03, cycles: 5 140 | Opcode: 0x04, cycles: 8 141 | Opcode: 0x05, cycles: 8 142 | Opcode: 0x06, cycles: 5 143 | Opcode: 0x07, cycles: 5 144 | Opcode: 0x08, cycles: 5 145 | Opcode: 0x09, cycles: 22 146 | Opcode: 0x0a, cycles: 31 147 | Opcode: 0x0b, cycles: 44 148 | Opcode: 0x0c, cycles: 6 149 | Opcode: 0x0d, cycles: 9 150 | Opcode: 0x0e, cycles: 22725 151 | Opcode: 0x0f, cycles: 42 152 | 153 | Opcode: 0x21, cycles: 12 154 | 155 | Opcode: 0x38, cycles: 7 156 | Opcode: 0x39, cycles: 7 157 | Opcode: 0x3a, cycles: 6 158 | Opcode: 0x3b, cycles: 7 159 | Opcode: 0x3c, cycles: 10 160 | Opcode: 0x3d, cycles: 8 161 | Opcode: 0x3e, cycles: 10 162 | Opcode: 0x3f, cycles: 10 163 | Opcode: 0x81, cycles: 8 164 | Opcode: 0x83, cycles: 18 165 | 166 | 01 NOP 4 167 | 05 DI 8 168 | 3A CLAW 6 169 | 22 CLR 11 170 | a1 STAL 18 171 | b1 STAW 22 172 | 90 LDAW 12 173 | 5f XASW 8 174 | 81 LDAL 18 175 | c1 LDBL 18 176 | c0 LDBL 8 177 | 99 LAWB 19 178 | 42 AND 11 179 | 40 ADD 11 180 | 58 AABW 9 181 | 49 SABL 8 182 | 3d SLAW 8 183 | 71 JMP 14 184 | 14 BZ 9 (branch not taken) 185 | 15 BNZ 18 (branch taken) 186 | 187 | */ 188 | -------------------------------------------------------------------------------- /Verilog/Clock.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * A clock generator for simulation only. 4 | * This module is not used during synthesis. 5 | * 6 | * See https://d1.amobbs.com/bbs_upload782111/files_33/ourdev_585395BQ8J9A.pdf 7 | * pp 129 8 | */ 9 | module Clock(output reg clock); 10 | initial begin 11 | #0 clock = 0; 12 | end 13 | 14 | always begin 15 | #100 clock <= ~clock; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /Verilog/CodeROM.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * This module implements the CPU6 microcode ROM. 4 | * Microcode is loaded from a text file, which is synthesizable. 5 | */ 6 | module CodeROM(input wire [10:0] address, output wire [55:0] data); 7 | reg [55:0] memory[0:2047]; 8 | initial begin 9 | $readmemh("roms/CodeROM.txt", memory); 10 | end 11 | 12 | assign data = memory[address]; 13 | endmodule 14 | -------------------------------------------------------------------------------- /Verilog/ControlPanel.py: -------------------------------------------------------------------------------- 1 | 2 | import tkinter as tk 3 | from tkinter import ttk 4 | from tkinter import messagebox 5 | 6 | from parse_vcd import * 7 | 8 | TIMER_TICK_MS = 500 9 | 10 | class NavFrame(ttk.LabelFrame): 11 | def __init__(self, container, sigframes): 12 | super().__init__(container, text='Navigate') 13 | self.sigFrames = sigframes 14 | self.running = False 15 | self.index = 0 16 | tk.Label(self, text='Cycle', font=('Consolas', 12)).grid(column=0, row=0, sticky=tk.E) 17 | self.cycle = tk.Label(self, text='0', font=('Digital-7 Mono', 20), fg='#0000ff') 18 | self.cycle.grid(column=1, row=0, sticky=tk.E) 19 | 20 | ttk.Button(self, text='Reset', command=self.reset).grid(column=0, row=1, padx=5, pady=2) 21 | self.runBtn = ttk.Button(self, text='Run', command=self.run) 22 | self.runBtn.grid(column=0, row=2, padx=5, pady=2) 23 | self.stopBtn = ttk.Button(self, text='Stop', command=self.stop, state='disabled') 24 | self.stopBtn.grid(column=0, row=3, padx=5, pady=2) 25 | 26 | self.prevBtn = ttk.Button(self, text='Prev', command=self.prev) 27 | self.prevBtn.grid(column=0, row=4, padx=5, pady=2) 28 | 29 | self.nextBtn = ttk.Button(self, text='Next', command=self.next) 30 | self.nextBtn.grid(column=0, row=5, padx=5, pady=2) 31 | self.stepNBtn = ttk.Button(self, text='Step #', command=self.stepn) 32 | self.stepNBtn.grid(column=0, row=6, padx=5, pady=2) 33 | self.nClocks = ttk.Entry(self, width=5) 34 | self.nClocks.insert(0, '1') 35 | self.nClocks.focus() 36 | self.nClocks.grid(column=1, row=6, padx=5, pady=2, sticky=tk.W) 37 | 38 | def timer(self): 39 | self.winfo_toplevel().after(TIMER_TICK_MS, self.timer) 40 | if self.running: 41 | self.next() 42 | else: 43 | self.prevBtn.configure(state='normal') 44 | self.nextBtn.configure(state='normal') 45 | self.stepNBtn.configure(state='normal') 46 | self.runBtn.configure(state='normal') 47 | self.stopBtn.configure(state='disabled') 48 | self.nClocks.configure(state='normal') 49 | 50 | def updateAll(self): 51 | self.cycle.config(text = str(self.index)) 52 | for f in self.sigFrames: 53 | f.doUpdate(self.index) 54 | 55 | def reset(self): 56 | self.index = 0 57 | self.updateAll() 58 | 59 | def run(self): 60 | self.running = True 61 | self.prevBtn.configure(state='disabled') 62 | self.nextBtn.configure(state='disabled') 63 | self.stepNBtn.configure(state='disabled') 64 | self.runBtn.configure(state='disabled') 65 | self.stopBtn.configure(state='normal') 66 | self.nClocks.configure(state='disabled') 67 | 68 | def stop(self): 69 | self.running = False 70 | 71 | def prev(self): 72 | if self.index > 0: 73 | self.index -= 1 74 | self.updateAll() 75 | 76 | def next(self): 77 | self.index += 1 78 | self.updateAll() 79 | 80 | def stepn(self): 81 | try: 82 | n = int(self.nClocks.get()) 83 | while n > 0: 84 | self.index += 1 85 | n -= 1 86 | self.updateAll() 87 | except ValueError as e: 88 | msg = f'Count is not an int: {self.nClocks.get()}' 89 | messagebox.showwarning(title='Input Error', message=msg) 90 | 91 | ALU_SRC_MAP = [['A', 'Q'], ['A', 'B'], ['0', 'Q'], ['0', 'B'], ['0', 'A'], ['D', 'A'], ['D', 'Q'], ['D', '0']] 92 | ALU_OP_MAP = ['{r}+{s}', '{s}-{r}', '{r}-{s}', '{r}|{s}', '{r}&{s}', '(~{r})&{s}', '{r}^{s}', '~({r}^{s})'] 93 | ALU_MEM_DEST_MAP = ['', '', 'r{b}={f}', 'r{b}={f}', 'r{b}=({f})>>1', 'r{b}=({f})>>1', 'r{b}=({f})<<1', 'r{b} =({f})<<1'] 94 | ALU_Q_DEST_MAP = ['Q = {f}', '', '', '', 'Q>>=1', '', 'Q<<=1', ''] 95 | ALU_OUT_MAP = ['Y={f}', 'Y={f}', 'Y={a}', 'Y={f}', 'Y={f}', 'Y={f}', 'Y={f}', 'Y={f}'] 96 | 97 | class ALUFrame(ttk.LabelFrame): 98 | def __init__(self, container, title): 99 | super().__init__(container, text=title) 100 | self.app = container 101 | fontName = ('Consolas', 12) 102 | self.aluLabel = tk.Label(self, text='', font=fontName) 103 | self.aluLabel.grid(column=0, row=0, sticky=tk.E) 104 | self.doUpdate(0) 105 | 106 | def doUpdate(self, index): 107 | alu_a = self.app.getSignal(index, 'cpu.alu_a').value 108 | alu_b = self.app.getSignal(index, 'cpu.alu_b').value 109 | alu_src = self.app.getSignal(index, 'cpu.alu_src').value 110 | alu_op = self.app.getSignal(index, 'cpu.alu_op').value 111 | alu_dest = self.app.getSignal(index, 'cpu.alu_dest').value 112 | alu0_cin = self.app.getSignal(index, 'cpu.alu0_cin').value 113 | aluCode = self.getALUCode(alu_a, alu_b, alu_op, alu_src, alu_dest, alu0_cin).strip() 114 | self.aluLabel.config(text = f'{aluCode:25s}') 115 | 116 | def getALUCode(self, aluA, aluB, aluOp, aluSrc, aluDest, cin): 117 | r, s = ALU_SRC_MAP[aluSrc] 118 | if r == 'A': 119 | r = f'r{aluA}' 120 | elif r == 'B': 121 | r = f'r{aluB}' 122 | if s == 'A': 123 | s = f'r{aluA}' 124 | elif s == 'B': 125 | s = f'r{aluB}' 126 | f = ALU_OP_MAP[aluOp].format(r=r, s=s) 127 | mem = ALU_MEM_DEST_MAP[aluDest].format(b=aluB, f=f) 128 | q = ALU_Q_DEST_MAP[aluDest].format(f=f) 129 | a = f'r{aluA}' 130 | y = ALU_OUT_MAP[aluDest].format(f=f, a=a) 131 | if (aluOp == 0 or aluOp == 1) and cin == 1: 132 | return f'{mem}+{cin} {q} {y}+{cin}' 133 | return f'{mem} {q} {y}' 134 | 135 | class SignalIndicator(tk.Canvas): 136 | def __init__(self, container, signalName, w=15, h=15): 137 | super().__init__(container, width=w, height=h) 138 | self.signalName = signalName 139 | 140 | def doUpdate(self, signal): 141 | w = self.winfo_width()-3 142 | h = self.winfo_height()-3 143 | if signal.value: 144 | self.create_oval(2, 2, w, h, fill='#0f0', outline='#000') 145 | else: 146 | self.create_oval(2, 2, w, h, fill='#fff', outline='#000') 147 | 148 | class VectorIndicator(tk.Label): 149 | def __init__(self, container, signalName, size): 150 | # TrueType font from https://www.fontspace.com/digital-7-font-f7087 151 | fontValue = ('Digital-7 Mono', 20) 152 | super().__init__(container, text='', font=fontValue, fg='#ff0000') 153 | digits = (size+3) >> 2 154 | self.format = f'%0{digits}X' 155 | self.signalName = signalName 156 | 157 | def doUpdate(self, signal): 158 | self.config(text = self.format % signal.value) 159 | 160 | class OutputFrame(ttk.LabelFrame): 161 | def __init__(self, container, title, outputs): 162 | super().__init__(container, text=title) 163 | self.app = container 164 | self.indicators = [] 165 | fontName = ('Consolas', 12) 166 | row = 0 167 | for label, signalName in outputs.items(): 168 | tk.Label(self, text=label, font=fontName).grid(column=0, row=row, sticky=tk.E) 169 | ind = None 170 | signal = container.getSignal(0, signalName) 171 | if len(signal) == 1: 172 | ind = SignalIndicator(self, signalName) 173 | else: 174 | ind = VectorIndicator(self, signalName, len(signal)) 175 | self.indicators.append(ind) 176 | ind.grid(column=1, row=row, sticky=tk.E) 177 | row += 1 178 | self.doUpdate(0) 179 | 180 | def doUpdate(self, index): 181 | for ind in self.indicators: 182 | signal = self.app.getSignal(index, ind.signalName) 183 | ind.doUpdate(signal) 184 | 185 | class App(tk.Tk): 186 | def __init__(self, signals, signalTagMap): 187 | super().__init__() 188 | self.signals = signals 189 | self.signalTagMap = signalTagMap 190 | self.title('CPU6 Simulation Replay') 191 | #self.geometry('500x200') 192 | self.resizable(True, True) 193 | # windows only (remove the minimize/maximize button) 194 | self.attributes('-toolwindow', True) 195 | self.columnconfigure(0, weight=1) 196 | self.columnconfigure(1, weight=2) 197 | self.columnconfigure(2, weight=2) 198 | internal = {'μPC':'cpu.uc_rom_address', 'FBus': 'cpu.FBus', 'DPBus': 'cpu.DPBus', 199 | 'Result':'cpu.result_register', 'Flags':'cpu.flags_register', 'Swap':'cpu.swap_register', 200 | 'Reg. Index':'cpu.register_index', 'Work Address': 'cpu.work_address', 201 | 'ALU 1 Q':'alu1.q', 'ALU 0 Q':'alu0.q' } 202 | external = {'Bus Address': 'cpu.memory_address', 'Data In':'cpu.dataInBus', 'Data Out':'cpu.dataOutBus', 203 | 'Write En':'cpu.writeEnBus'} 204 | internFrame = OutputFrame(self, 'Internal Signals', internal) 205 | aluFrame = ALUFrame(self, 'ALU') 206 | outputFrame = OutputFrame(self, 'Output Signals', external) 207 | navFrame = NavFrame(self, [internFrame, outputFrame, aluFrame]) 208 | navFrame.grid(column=0, row=0, padx=2, pady=2) 209 | internFrame.grid(column=1, row=0, padx=2, pady=2, sticky=tk.NW) 210 | aluFrame.grid(column=1, row=1, padx=2, pady=2, sticky=tk.N) 211 | outputFrame.grid(column=2, row=0, padx=3, pady=2, sticky=tk.NW) 212 | # Assert reset after 500 ms 213 | self.after(500, navFrame.reset) 214 | self.after(TIMER_TICK_MS, navFrame.timer) 215 | 216 | def getSignal(self, index, name): 217 | tag = self.signalTagMap[name] 218 | sig = self.signals[index] 219 | return sig[tag] 220 | 221 | if __name__ == '__main__': 222 | vcd = VCDFile('vcd/CPUTestBench.vcd') 223 | signals = [] 224 | clockTag = vcd.signalTagMap['cg0.clock'] 225 | for sig in vcd.signals: 226 | if sig[clockTag].value == 1: 227 | signals.append(sig) 228 | app = App(signals, vcd.signalTagMap) 229 | app.mainloop() 230 | -------------------------------------------------------------------------------- /Verilog/Instructions.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * A mapping from instruction opcodes to mnemonics for instruction tracing during simulation. 4 | * This module is not used during synthesis. 5 | */ 6 | module Instructions(); 7 | reg [32:0] instruction_map[0:255]; 8 | initial begin 9 | instruction_map[0] = "HLT "; 10 | instruction_map[1] = "NOP "; 11 | instruction_map[2] = "SF "; 12 | instruction_map[3] = "RF "; 13 | instruction_map[4] = "EI "; 14 | instruction_map[5] = "DI "; 15 | instruction_map[6] = "SL "; 16 | instruction_map[7] = "RL "; 17 | instruction_map[8] = "CL "; 18 | instruction_map[9] = "RSR "; 19 | instruction_map[10] = "RI "; 20 | instruction_map[11] = "RIM "; 21 | instruction_map[12] = "ELO "; 22 | instruction_map[13] = "PCX "; 23 | instruction_map[14] = "DLY "; 24 | instruction_map[15] = "RSYS"; 25 | instruction_map[16] = "BL "; 26 | instruction_map[17] = "BNL "; 27 | instruction_map[18] = "BF "; 28 | instruction_map[19] = "BNF "; 29 | instruction_map[20] = "BZ "; 30 | instruction_map[21] = "BNZ "; 31 | instruction_map[22] = "BM "; 32 | instruction_map[23] = "BP "; 33 | instruction_map[24] = "BGZ "; 34 | instruction_map[25] = "BLE "; 35 | instruction_map[26] = "BS1 "; 36 | instruction_map[27] = "BS2 "; 37 | instruction_map[28] = "BS3 "; 38 | instruction_map[29] = "BS4 "; 39 | instruction_map[30] = "BTM?"; 40 | instruction_map[31] = "BEP?"; 41 | instruction_map[32] = "INR "; 42 | instruction_map[33] = "DCR "; 43 | instruction_map[34] = "CLR "; 44 | instruction_map[35] = "IVR "; 45 | instruction_map[36] = "SRR "; 46 | instruction_map[37] = "SLR "; 47 | instruction_map[38] = "RRR "; 48 | instruction_map[39] = "RLR "; 49 | instruction_map[40] = "INAL"; 50 | instruction_map[41] = "DCAL"; 51 | instruction_map[42] = "CLAL"; 52 | instruction_map[43] = "IVAL"; 53 | instruction_map[44] = "SRAL"; 54 | instruction_map[45] = "SLAL"; 55 | instruction_map[46] = "?2e "; 56 | instruction_map[47] = "?2f "; 57 | instruction_map[48] = "INRW"; 58 | instruction_map[49] = "DCR "; 59 | instruction_map[50] = "CLR "; 60 | instruction_map[51] = "IVR "; 61 | instruction_map[52] = "SRR "; 62 | instruction_map[53] = "SLR "; 63 | instruction_map[54] = "RRR "; 64 | instruction_map[55] = "RLR "; 65 | instruction_map[56] = "INAW"; 66 | instruction_map[57] = "DCAW"; 67 | instruction_map[58] = "CLAW"; 68 | instruction_map[59] = "IVAW"; 69 | instruction_map[60] = "SRAW"; 70 | instruction_map[61] = "SLAW"; 71 | instruction_map[62] = "INX "; 72 | instruction_map[63] = "DCX "; 73 | instruction_map[64] = "ADD "; 74 | instruction_map[65] = "SUB "; 75 | instruction_map[66] = "AND "; 76 | instruction_map[67] = "ORI "; 77 | instruction_map[68] = "ORE "; 78 | instruction_map[69] = "XFR "; 79 | instruction_map[70] = "?46 "; 80 | instruction_map[71] = "?47 "; 81 | instruction_map[72] = "AABL"; 82 | instruction_map[73] = "SABL"; 83 | instruction_map[74] = "NABL"; 84 | instruction_map[75] = "XAXL"; 85 | instruction_map[76] = "XAYL"; 86 | instruction_map[77] = "XABL"; 87 | instruction_map[78] = "XAZL"; 88 | instruction_map[79] = "XASL"; 89 | instruction_map[80] = "ADD "; 90 | instruction_map[81] = "SUB "; 91 | instruction_map[82] = "AND "; 92 | instruction_map[83] = "ORI "; 93 | instruction_map[84] = "ORE "; 94 | instruction_map[85] = "XFR "; 95 | instruction_map[86] = "?56 "; 96 | instruction_map[87] = "?57 "; 97 | instruction_map[88] = "AABW"; 98 | instruction_map[89] = "SABW"; 99 | instruction_map[90] = "NABW"; 100 | instruction_map[91] = "XAXW"; 101 | instruction_map[92] = "XAYW"; 102 | instruction_map[93] = "XABW"; 103 | instruction_map[94] = "XAZW"; 104 | instruction_map[95] = "XASW"; 105 | instruction_map[96] = "LDXW"; 106 | instruction_map[97] = "LDXW"; 107 | instruction_map[98] = "LDXW"; 108 | instruction_map[99] = "LDXW"; 109 | instruction_map[100] = "LDXW"; 110 | instruction_map[101] = "LDXW"; 111 | instruction_map[102] = "JSYS"; 112 | instruction_map[103] = "?67 "; 113 | instruction_map[104] = "STXW"; 114 | instruction_map[105] = "STXW"; 115 | instruction_map[106] = "STXW"; 116 | instruction_map[107] = "STXW"; 117 | instruction_map[108] = "STXW"; 118 | instruction_map[109] = "STXW"; 119 | instruction_map[110] = "LDCC"; 120 | instruction_map[111] = "STCC"; 121 | instruction_map[112] = "JMP "; 122 | instruction_map[113] = "JMP "; 123 | instruction_map[114] = "JMP "; 124 | instruction_map[115] = "JMP "; 125 | instruction_map[116] = "JMP "; 126 | instruction_map[117] = "JMP "; 127 | instruction_map[118] = "?76 "; 128 | instruction_map[119] = "?77 "; 129 | instruction_map[120] = "?78 "; 130 | instruction_map[121] = "JSR "; 131 | instruction_map[122] = "JSR "; 132 | instruction_map[123] = "JSR "; 133 | instruction_map[124] = "JSR "; 134 | instruction_map[125] = "JSR "; 135 | instruction_map[126] = "PUSH"; 136 | instruction_map[127] = "POP "; 137 | instruction_map[128] = "LDAL"; 138 | instruction_map[129] = "LDAL"; 139 | instruction_map[130] = "LDAL"; 140 | instruction_map[131] = "LDAL"; 141 | instruction_map[132] = "LDAL"; 142 | instruction_map[133] = "LDAL"; 143 | instruction_map[134] = "?86 "; 144 | instruction_map[135] = "?87 "; 145 | instruction_map[136] = "LALA"; 146 | instruction_map[137] = "LALB"; 147 | instruction_map[138] = "LALX"; 148 | instruction_map[139] = "LALY"; 149 | instruction_map[140] = "LALZ"; 150 | instruction_map[141] = "LALS"; 151 | instruction_map[142] = "LALC"; 152 | instruction_map[143] = "LALP"; 153 | instruction_map[144] = "LDAW"; 154 | instruction_map[145] = "LDAW"; 155 | instruction_map[146] = "LDAW"; 156 | instruction_map[147] = "LDAW"; 157 | instruction_map[148] = "LDAW"; 158 | instruction_map[149] = "LDAW"; 159 | instruction_map[150] = "?96 "; 160 | instruction_map[151] = "?97 "; 161 | instruction_map[152] = "LAWA"; 162 | instruction_map[153] = "LAWB"; 163 | instruction_map[154] = "LAWX"; 164 | instruction_map[155] = "LAWY"; 165 | instruction_map[156] = "LAWZ"; 166 | instruction_map[157] = "LAWS"; 167 | instruction_map[158] = "LAWC"; 168 | instruction_map[159] = "LAWP"; 169 | instruction_map[160] = "STAL"; 170 | instruction_map[161] = "STAL"; 171 | instruction_map[162] = "STAL"; 172 | instruction_map[163] = "STAL"; 173 | instruction_map[164] = "STAL"; 174 | instruction_map[165] = "STAL"; 175 | instruction_map[166] = "?a6 "; 176 | instruction_map[167] = "?a7 "; 177 | instruction_map[168] = "SALA"; 178 | instruction_map[169] = "SALB"; 179 | instruction_map[170] = "SALX"; 180 | instruction_map[171] = "SALY"; 181 | instruction_map[172] = "SALZ"; 182 | instruction_map[173] = "SALS"; 183 | instruction_map[174] = "SALC"; 184 | instruction_map[175] = "SALP"; 185 | instruction_map[176] = "STAW"; 186 | instruction_map[177] = "STAW"; 187 | instruction_map[178] = "STAW"; 188 | instruction_map[179] = "STAW"; 189 | instruction_map[180] = "STAW"; 190 | instruction_map[181] = "STAW"; 191 | instruction_map[182] = "?b6 "; 192 | instruction_map[183] = "?b7 "; 193 | instruction_map[184] = "SAWA"; 194 | instruction_map[185] = "SAWB"; 195 | instruction_map[186] = "SAWX"; 196 | instruction_map[187] = "SAWY"; 197 | instruction_map[188] = "SAWZ"; 198 | instruction_map[189] = "SAWS"; 199 | instruction_map[190] = "SAWC"; 200 | instruction_map[191] = "SAWP"; 201 | instruction_map[192] = "LDBL"; 202 | instruction_map[193] = "LDBL"; 203 | instruction_map[194] = "LDBL"; 204 | instruction_map[195] = "LDBL"; 205 | instruction_map[196] = "LDBL"; 206 | instruction_map[197] = "LDBL"; 207 | instruction_map[198] = "?c6 "; 208 | instruction_map[199] = "?c7 "; 209 | instruction_map[200] = "LBLA"; 210 | instruction_map[201] = "LBLB"; 211 | instruction_map[202] = "LBLX"; 212 | instruction_map[203] = "LBLY"; 213 | instruction_map[204] = "LBLZ"; 214 | instruction_map[205] = "LBLS"; 215 | instruction_map[206] = "LBLC"; 216 | instruction_map[207] = "LBLP"; 217 | instruction_map[208] = "LDBW"; 218 | instruction_map[209] = "LDBW"; 219 | instruction_map[210] = "LDBW"; 220 | instruction_map[211] = "LDBW"; 221 | instruction_map[212] = "LDBW"; 222 | instruction_map[213] = "LDBW"; 223 | instruction_map[214] = "?d6 "; 224 | instruction_map[215] = "?d7 "; 225 | instruction_map[216] = "LBWA"; 226 | instruction_map[217] = "LBWB"; 227 | instruction_map[218] = "LBWX"; 228 | instruction_map[219] = "LDBW"; 229 | instruction_map[220] = "LBWZ"; 230 | instruction_map[221] = "LBWS"; 231 | instruction_map[222] = "LBWC"; 232 | instruction_map[223] = "LBWP"; 233 | instruction_map[224] = "STBL"; 234 | instruction_map[225] = "STBL"; 235 | instruction_map[226] = "STBL"; 236 | instruction_map[227] = "STBL"; 237 | instruction_map[228] = "STBL"; 238 | instruction_map[229] = "STBL"; 239 | instruction_map[230] = "?e6 "; 240 | instruction_map[231] = "?e7 "; 241 | instruction_map[232] = "SBLA"; 242 | instruction_map[233] = "SBLB"; 243 | instruction_map[234] = "SBLX"; 244 | instruction_map[235] = "SBLY"; 245 | instruction_map[236] = "SBLZ"; 246 | instruction_map[237] = "SBLS"; 247 | instruction_map[238] = "SBLC"; 248 | instruction_map[239] = "SBLP"; 249 | instruction_map[240] = "STBW"; 250 | instruction_map[241] = "STBW"; 251 | instruction_map[242] = "STBW"; 252 | instruction_map[243] = "STBW"; 253 | instruction_map[244] = "STBW"; 254 | instruction_map[245] = "STBW"; 255 | instruction_map[246] = "?f6 "; 256 | instruction_map[247] = "?f7 "; 257 | instruction_map[248] = "SBWA"; 258 | instruction_map[249] = "SBWB"; 259 | instruction_map[250] = "SBWX"; 260 | instruction_map[251] = "SBWY"; 261 | instruction_map[252] = "SBWZ"; 262 | instruction_map[253] = "SBWS"; 263 | instruction_map[254] = "SBWC"; 264 | instruction_map[255] = "SBWP"; 265 | end 266 | endmodule 267 | -------------------------------------------------------------------------------- /Verilog/LEDPanel.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * The LED panel found on Alchitry Cu FPGA boards. 4 | * See ice40_alchitry_cu.pcf for pin configurations. 5 | */ 6 | module LEDPanel(input wire clock, input wire [18:0] address, input wire write_en, input wire [7:0] data_in, 7 | output wire [7:0] data_out, output reg [7:0] leds); 8 | 9 | always @(posedge clock) begin 10 | if (write_en == 1) begin 11 | if (address == 19'h5c00) begin 12 | leds <= data_in; 13 | end 14 | end 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /Verilog/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROJ = iCE40 3 | 4 | # iCEBlink40 5 | # PIN_DEF = iceblink40_vq100.pcf 6 | # DEVICE = hx1k 7 | # PACKAGE = vq100 8 | 9 | # Alchitry Cu 10 | PIN_DEF = ice40_alchitry_cu.pcf 11 | DEVICE = hx8k 12 | PACKAGE = cb132 13 | 14 | # Comment QUIET for detailed output 15 | #QUIET = -q 16 | 17 | all: $(PROJ).rpt $(PROJ).bin 18 | 19 | %.json: %.v roms/CodeROM.txt Makefile *.v 20 | yosys $(QUIET) -p 'synth_ice40 -top $(PROJ) -json $@' $< 21 | 22 | %.asc: $(PIN_DEF) %.json 23 | nextpnr-ice40 $(QUIET) --$(DEVICE) --package $(PACKAGE) --json $(word 2,$^) --pcf $(PIN_DEF) --asc $@ 24 | 25 | %.bin: %.asc 26 | icepack $< $@ 27 | 28 | %.rpt: %.asc 29 | icetime -d $(DEVICE) -mtr $@ $< 30 | 31 | prog: $(PROJ).bin 32 | sudo iceprog $< 33 | 34 | sudo-prog: $(PROJ).bin 35 | @echo 'Executing prog as root!!!' 36 | sudo iceprog $< 37 | 38 | test: CPU6TestBench 39 | vvp CPU6TestBench 40 | 41 | CPU6TestBench: *.v 42 | iverilog -o CPU6TestBench CPU6TestBench.v 43 | 44 | clean: 45 | rm $(PROJ).json $(PROJ).asc $(PROJ).bin $(PROJ).rpt CPU6TestBench 46 | 47 | .PHONY: all prog clean 48 | -------------------------------------------------------------------------------- /Verilog/MapROM.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * This module implements the CPU6 opcode mapping ROM (B13 6309). 4 | * Mapping code is loaded from a text file, which is synthesizable. 5 | */ 6 | module MapROM(input wire [7:0] address, output wire [7:0] data_out); 7 | reg [7:0] memory[0:255]; 8 | initial begin 9 | $readmemh("roms/CPU-6309.txt", memory); 10 | end 11 | 12 | assign data_out = memory[address]; 13 | endmodule 14 | -------------------------------------------------------------------------------- /Verilog/Microcode.py: -------------------------------------------------------------------------------- 1 | 2 | from collections import defaultdict 3 | 4 | ALU_SRC_MAP = [['A', 'Q'], ['A', 'B'], ['0', 'Q'], ['0', 'B'], ['0', 'A'], ['D', 'A'], ['D', 'Q'], ['D', '0']] 5 | ALU_OP_MAP = ['{r}+{s}', '{s}-{r}', '{r}-{s}', '{r}|{s}', '{r}&{s}', '(~{r})&{s}', '{r}^{s}', '~({r}^{s})'] 6 | ALU_MEM_DEST_MAP = ['', '', 'r{b}={f}', 'r{b}={f}', 'r{b}=({f})>>1', 'r{b}=({f})>>1', 'r{b}=({f})<<1', 'r{b} =({f})<<1'] 7 | ALU_Q_DEST_MAP = ['Q = {f}', '', '', '', 'Q>>=1', '', 'Q<<=1', ''] 8 | ALU_OUT_MAP = ['Y={f}', 'Y={f}', 'Y={a}', 'Y={f}', 'Y={f}', 'Y={f}', 'Y={f}', 'Y={f}'] 9 | 10 | class MicroCode(object): 11 | def __init__(self): 12 | with open('roms/CodeROM.txt') as f: 13 | lines = f.readlines() 14 | self.code = [int(line, 16) for line in lines] 15 | self.selects = defaultdict(int) 16 | 17 | def getBits(self, word, start, size): 18 | return (word >> start) & (~(-1 << size)) 19 | 20 | def disassemble(self): 21 | for addr, word in enumerate(self.code): 22 | self.disassembleOne(addr, word) 23 | print() 24 | print('Mux select distribution') 25 | for name, value in self.selects.items(): 26 | print(f'{name:3x}: {value}') 27 | 28 | def disassembleOne(self, addr, word): 29 | if word == 0: 30 | print(f'{addr:3x} {word:14x} unused') 31 | return 32 | seq0_din = self.getBits(word, 16, 4) 33 | seq0_s = ~self.getBits(word, 29, 2) & 3 34 | seq1_din = self.getBits(word, 20, 4) 35 | seq1_s = ~self.getBits(word, 29, 2) & 3 # pipeline 54 36 | seq2_din = self.getBits(word, 24, 3) 37 | s0 = ~self.getBits(word, 31, 1) & 1 38 | p32 = self.getBits(word, 32, 1) 39 | p54 = self.getBits(word, 54, 1) 40 | s1 = ~(~(p54 & (~p32 & 1) & 1)) & 1 41 | seq2_s = s1 << 1 | s0 42 | case_ = self.getBits(word, 33, 1) 43 | j13 = self.getBits(word, 20, 2) 44 | k13 = self.getBits(word, 22, 2) 45 | dest = (seq2_din << 8) | (seq1_din << 4) | seq0_din 46 | s1s0 = (seq2_s << 8) | (seq1_s << 4) | seq0_s 47 | self.selects[s1s0] += 1 48 | next = addr + 1 49 | if case_ == 0: 50 | # flags zHCVMZ 51 | if s1s0 == 0x033: 52 | dest = (next & 0xf00) | (dest & 0x0ff) 53 | elif s1s0 == 0x233: 54 | pass # TODO: high nibble is AR (happens once) 55 | elif s1s0 == 0x233: 56 | pass # TODO: high nibble is stack (rare case) 57 | jump = f'jump {dest:3x}' 58 | if j13 == 0: 59 | jump = f'switch flags(ZM) jump {dest|0:x}, {dest|1:x}, {dest|2:x}, {dest|3:x}' 60 | elif j13 == 1: 61 | jump = f'switch flags(VH) jump {dest|0:x}, {dest|1:x}, {dest|2:x}, {dest|3:x}' 62 | else: 63 | fe = self.getBits(word, 27, 1) 64 | pup = self.getBits(word, 28, 1) 65 | jump = '' 66 | if fe == 0: 67 | if pup == 1: 68 | jump = f'push {next:x} ' 69 | elif s1s0 == 0x222: 70 | jump = f'ret ' 71 | if s1s0 == 0x333: 72 | jump = f'{jump}jump {dest:3x}' 73 | elif s1s0 == 0x111: 74 | jump = f'{jump}jump AR' 75 | elif s1s0 == 0x033: 76 | dest = (next & 0xf00) | (dest & 0x0ff) 77 | jump = f'{jump}jump {dest:3x}' 78 | elif s1s0 == 0x133: 79 | dest = dest & 0x0ff 80 | jump = f'{jump}jump AR|{dest:3x}' 81 | elif s1s0 == 0x311: 82 | dest = dest & 0xf00 83 | jump = f'{jump}jump {dest:3x}|AR|AR' 84 | elif s1s0 == 0x300: 85 | dest = (dest & 0xf00) | (next & 0x0ff) 86 | jump = f'{jump}jump {dest:3x}' 87 | elif s1s0 != 0 and s1s0 != 0x222: 88 | jump = f'{jump}jump somewhere mux: {s1s0:3x}' 89 | dpBus = self.getDPBus(word) 90 | aluOp = self.getALUCode(word) 91 | fBus = self.getFBus(word) 92 | print(f'{addr:3x}: {dpBus} {aluOp} {fBus} {jump}') 93 | 94 | def getDPBus(self, word): 95 | d2d3 = self.getBits(word, 0, 4) 96 | constant = ~self.getBits(word, 16, 8) & 0xff 97 | if d2d3 == 0: 98 | return f'D=swap' 99 | elif d2d3 == 1: 100 | return f'D=reg_ram' 101 | elif d2d3 == 2: 102 | return f'D=mar_hi' 103 | elif d2d3 == 3: 104 | return f'D=mar_lo' 105 | elif d2d3 == 4: 106 | return f'D=swap' 107 | elif d2d3 == 5: 108 | return f'D=reg_ram' 109 | elif d2d3 == 6: 110 | return f'D=mar_hi' 111 | elif d2d3 == 7: 112 | return f'D=mar_lo' 113 | elif d2d3 == 8: 114 | return '' 115 | elif d2d3 == 9: 116 | return 'D=CC' 117 | elif d2d3 == 10: 118 | return 'D=bus_read' 119 | elif d2d3 == 11: 120 | return 'D=ILR?' 121 | elif d2d3 == 12: 122 | return 'D=dips?' 123 | elif d2d3 == 13: 124 | return f'D={constant:x}' 125 | elif d2d3 == 14: 126 | return '' 127 | elif d2d3 == 15: 128 | return '' 129 | 130 | def getFBus(self, word): 131 | h11 = self.getBits(word, 10, 3) 132 | if h11 == 6: 133 | return 'F=map_rom' 134 | return 'F=Y' 135 | 136 | def getALUCode(self, word): 137 | aluA = self.getBits(word, 47, 4) 138 | aluB = self.getBits(word, 43, 4) 139 | aluSrc = self.getBits(word, 34, 3) 140 | aluOp = self.getBits(word, 37, 3) 141 | aluDest = self.getBits(word, 40, 3) 142 | cin = 0 143 | cout = 0 144 | r, s = ALU_SRC_MAP[aluSrc] 145 | if r == 'A': 146 | r = f'r{aluA}' 147 | elif r == 'B': 148 | r = f'r{aluB}' 149 | if s == 'A': 150 | s = f'r{aluA}' 151 | elif s == 'B': 152 | s = f'r{aluB}' 153 | f = ALU_OP_MAP[aluOp].format(r=r, s=s) 154 | mem = ALU_MEM_DEST_MAP[aluDest].format(b=aluB, f=f) 155 | q = ALU_Q_DEST_MAP[aluDest].format(f=f) 156 | a = f'r{aluA}' 157 | y = ALU_OUT_MAP[aluDest].format(f=f, a=a) 158 | c = '' 159 | if cout: 160 | c = 'C' 161 | if (aluOp == 0 or aluOp == 1 or aluOp == 2) and cin: 162 | return f'{mem}+{cin} {q} {y}+{cin} {c}' 163 | return f'{mem} {q} {y} {c}' 164 | 165 | if __name__ == '__main__': 166 | mc = MicroCode() 167 | mc.disassemble() 168 | -------------------------------------------------------------------------------- /Verilog/PLL.v: -------------------------------------------------------------------------------- 1 | /** 2 | * PLL configuration 3 | * 4 | * This Verilog module was generated automatically 5 | * using the icepll tool from the IceStorm project. 6 | * Use at your own risk. 7 | * 8 | * Given input frequency: 100.000 MHz 9 | * Requested output frequency: 20.000 MHz 10 | * Achieved output frequency: 20.000 MHz 11 | */ 12 | 13 | module PLL( 14 | input clock_in, 15 | output clock_out, 16 | output locked 17 | ); 18 | 19 | SB_PLL40_CORE #( 20 | .FEEDBACK_PATH("SIMPLE"), 21 | .DIVR(4'b0100), // DIVR = 4 22 | .DIVF(7'b0011111), // DIVF = 31 23 | .DIVQ(3'b101), // DIVQ = 5 24 | .FILTER_RANGE(3'b010) // FILTER_RANGE = 2 25 | ) uut ( 26 | .LOCK(locked), 27 | .RESETB(1'b1), 28 | .BYPASS(1'b0), 29 | .REFERENCECLK(clock_in), 30 | .PLLOUTCORE(clock_out) 31 | ); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /Verilog/RegisterRAM.v: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * This module implements the register file (D13/D14). 4 | */ 5 | module RegisterRAM(input wire clock, input wire write_en, input wire [7:0] address, input wire [7:0] data_in, 6 | output reg [7:0] data_out); 7 | 8 | integer i; 9 | initial begin 10 | for (i=0; i<256; i=i+1) memory[i] = 8'h00; 11 | end 12 | 13 | reg [7:0] memory[0:255]; 14 | wire [7:0] register0 = memory[0]; 15 | wire [7:0] register1 = memory[1]; 16 | 17 | always @(posedge clock) begin 18 | data_out <= memory[address]; 19 | if (write_en == 1) begin 20 | memory[address] <= data_in; 21 | end 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /Verilog/build.bat: -------------------------------------------------------------------------------- 1 | 2 | iverilog -o CPU6TestBench CPU6TestBench.v 3 | vvp CPU6TestBench 4 | -------------------------------------------------------------------------------- /Verilog/iCE40.v: -------------------------------------------------------------------------------- 1 | 2 | `include "CPU6.v" 3 | `include "LEDPanel.v" 4 | `include "PLL.v" 5 | 6 | /** 7 | * This file contains the top level Centurion CPU synthesizable on an Alchitry Cu FGPA board. 8 | */ 9 | module BlockRAM(input wire clock, input wire [18:0] address, input wire write_en, input wire [7:0] data_in, 10 | output wire [7:0] data_out); 11 | 12 | initial begin 13 | $readmemh("programs/cylon.txt", ram_cells); 14 | end 15 | 16 | reg [7:0] ram_cells[0:255]; 17 | 18 | wire [7:0] mapped_address = address[7:0]; 19 | assign data_out = ram_cells[mapped_address]; 20 | 21 | always @(posedge clock) begin 22 | if (write_en == 1 && address[15:8] == 8'hff) begin 23 | ram_cells[mapped_address] <= data_in; 24 | end 25 | end 26 | endmodule 27 | 28 | /* 29 | DEVICE = hx8k (Alchitry Cu) 30 | CodeROM reg [55:0] memory[0:2047] 31 | RegisterRAM reg [7:0] memory[0:255]; 32 | reg [7:0] ram_cells[0:255]; 33 | 34 | Info: Device utilisation: 35 | Info: ICESTORM_LC: 1133/ 7680 14% 36 | Info: ICESTORM_RAM: 30/ 32 93% 37 | Info: SB_IO: 9/ 256 3% 38 | Info: SB_GB: 5/ 8 62% 39 | Info: ICESTORM_PLL: 1/ 2 50% 40 | Info: SB_WARMBOOT: 0/ 1 0% 41 | */ 42 | // Timing estimate: 23.39 ns (42.75 MHz) 43 | // icepll -m -f PLL.v -n PLL -i 100 -o 20 44 | module iCE40(input clock_100MHz, output LED1, output LED2, output LED3, output LED4, output LED5, output LED6, output LED7, output LED8); 45 | initial begin 46 | reset = 1; 47 | end 48 | 49 | assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8} = leds; 50 | 51 | reg reset; 52 | 53 | wire writeEnBus; 54 | wire [7:0] data_c2r, data_r2c; 55 | wire [18:0] addressBus; 56 | wire [7:0] leds; 57 | wire clock20MHz, locked, clock; 58 | 59 | PLL pll(clock_100MHz, clock20MHz, locked); 60 | Divide4 div(clock20MHz, clock); 61 | BlockRAM ram(clock, addressBus, writeEnBus, data_c2r, data_r2c); 62 | LEDPanel panel(clock, addressBus, writeEnBus, data_c2r, data_r2c, leds); 63 | CPU6 cpu (reset, clock, data_r2c, writeEnBus, addressBus, data_c2r); 64 | 65 | always @ (posedge clock) begin 66 | if (reset == 1 && locked == 1) begin 67 | reset <= 0; 68 | end 69 | end 70 | endmodule 71 | 72 | module Divide4(input wire clock_in, output wire clock_out); 73 | reg [1:0] counter; 74 | assign clock_out = counter[1]; 75 | always @(posedge clock_in) begin 76 | counter <= counter + 1; 77 | end 78 | endmodule 79 | -------------------------------------------------------------------------------- /Verilog/ice40_alchitry_cu.pcf: -------------------------------------------------------------------------------- 1 | 2 | # Alchitry CU 3 | 4 | # Clock 5 | set_io clock_100MHz P7 6 | 7 | # Onboard LEDs 8 | set_io LED1 J11 9 | set_io LED2 K11 10 | set_io LED3 K12 11 | set_io LED4 K14 12 | set_io LED5 L12 13 | set_io LED6 L14 14 | set_io LED7 M12 15 | set_io LED8 N14 16 | 17 | # Reset 18 | set_io RESETBTN P8 19 | 20 | 21 | ## Alchitry IO 22 | 23 | # LEDs, right-to-left 24 | set_io IO_LED1 G14 # BB21, IOR_141_GBIN2 25 | set_io IO_LED2 F14 # BB20, IOR_140_GBIN3 26 | set_io IO_LED3 E12 # BB18, IOR_147 27 | set_io IO_LED4 E14 # BB17, IOR_148 28 | set_io IO_LED5 D14 # BB15, IOR_152 29 | set_io IO_LED6 C14 # BB14, IOR_154 30 | set_io IO_LED7 B14 # BB12, IOR_161 31 | set_io IO_LED8 A12 # BB11, IOT_170 32 | 33 | set_io IO_LED9 C10 # BB9, IOT_186 34 | set_io IO_LED10 C9 # BB8, IOT_190 35 | set_io IO_LED11 A11 # BB6, IOT_179 36 | set_io IO_LED12 A10 # BB5, IOT_181 37 | set_io IO_LED13 A7 # BB3, IOT_197_GBIN1 38 | set_io IO_LED14 A6 # BB2, IOT_198_GBIN0 39 | set_io IO_LED15 A4 # AB24, IOT_219 40 | set_io IO_LED16 A3 # AB23, IOT_222 41 | 42 | set_io IO_LED17 A2 # AB21, IOT_223 43 | set_io IO_LED18 A1 # AB20, IOT_225 44 | set_io IO_LED19 C3 # AB18, IOL_4_P 45 | set_io IO_LED20 D3 # AB17, IOL_4_N 46 | set_io IO_LED21 B1 # AB15, IOL_2_P 47 | set_io IO_LED22 C1 # AB14, IOL_2_N 48 | set_io IO_LED23 D1 # AB12, IOL_5_P 49 | set_io IO_LED24 E1 # AB11, IOL_5_N 50 | 51 | # DIP Switches 52 | # set_io DIP1 C11 # BB40, IOT_174 53 | # set_io DIP2 C11 # BB39, IOT_174 54 | # set_io DIP3 C11 # BB37, IOT_174 55 | # set_io DIP4 C11 # BB36, IOT_174 56 | # set_io DIP5 C11 # BB34, IOT_174 57 | # set_io DIP6 C11 # BB33, IOT_174 58 | # set_io DIP7 C11 # BB31, IOT_174 59 | # set_io DIP8 C11 # BB30, IOT_174 60 | # 61 | # set_io DIP9 C11 # AB28, IOT_174 62 | # set_io DIP10 C11 # AB27, IOT_174 63 | # set_io DIP11 C11 # BB49, IOT_174 64 | # set_io DIP12 C11 # BB48, IOT_174 65 | # set_io DIP13 C11 # BB46, IOT_174 66 | # set_io DIP14 C11 # BB45, IOT_174 67 | # set_io DIP15 C11 # BB43, IOT_174 68 | # set_io DIP16 C11 # BB42, IOT_174 69 | # 70 | # set_io DIP17 C11 # AB40, IOT_174 71 | # set_io DIP18 C11 # AB39, IOT_174 72 | # set_io DIP19 C11 # AB37, IOT_174 73 | # set_io DIP20 C11 # AB36, IOT_174 74 | # set_io DIP21 C11 # AB34, IOT_174 75 | # set_io DIP22 C11 # AB33, IOT_174 76 | # set_io DIP23 C11 # AB31, IOT_174 77 | # set_io DIP24 C11 # AB30, IOT_174 78 | -------------------------------------------------------------------------------- /Verilog/iceblink40_vq100.pcf: -------------------------------------------------------------------------------- 1 | 2 | ###IOSet List 5 3 | set_io clock 13 4 | set_io --warn-no-port LED2 59 5 | set_io --warn-no-port LED3 56 6 | set_io --warn-no-port LED4 53 7 | set_io --warn-no-port LED5 51 8 | -------------------------------------------------------------------------------- /Verilog/parse_vcd.py: -------------------------------------------------------------------------------- 1 | 2 | from collections import defaultdict 3 | 4 | OP_CODES = { 5 | 0x0: 'HLT', 0x1: 'NOP', 0x2: 'SF', 0x3: 'RF', 0x4: 'EI', 0x5: 'DI', 0x6: 'SL', 0x7: 'RL', 0x8: 'CL', 6 | 0x9: 'RSR', 0x0A: 'RI', 0x0B: 'RIM', 0x0C: 'ELO', 0x0D: 'PCX', 0x0E: 'DLY', 0x0F: 'RSYS', 0x10: 'BL', 7 | 0x11: 'BNL', 0x12: 'BF', 0x13: 'BNF', 0x14: 'BZ', 0x15: 'BNZ', 0x16: 'BM', 0x17: 'BP', 0x18: 'BGZ', 8 | 0x19: 'BLE', 0x1A: 'BS1', 0x1B: 'BS2', 0x1C: 'BS3', 0x1D: 'BS4', 0x1E: 'BTM?', 0x1F: 'BEP?', 0x20: 'INR', 9 | 0x21: 'DCR', 0x22: 'CLR', 0x23: 'IVR', 0x24: 'SRR', 0x25: 'SLR', 0x26: 'RRR', 0x27: 'RLR', 0x28: 'INAL', 10 | 0x29: 'DCAL', 0x2A: 'CLAL', 0x2B: 'IVAL', 0x2C: 'SRAL', 0x2D: 'SLAL', 0x2E: '?', 0x2F: '?', 0x30: 'INRW', 11 | 0x31: 'DCR', 0x32: 'CLR', 0x33: 'IVR', 0x34: 'SRR', 0x35: 'SLR', 0x36: 'RRR', 0x37: 'RLR', 0x38: 'INAW', 12 | 0x39: 'DCAW', 0x3A: 'CLAW', 0x3B: 'IVAW', 0x3C: 'SRAW', 0x3D: 'SLAW', 0x3E: 'INX', 0x3F: 'DCX', 13 | 0x40: 'ADD', 0x41: 'SUB', 0x42: 'AND', 0x43: 'ORI', 0x44: 'ORE', 0x45: 'XFR', 0x46: '?', 0x47: '??', 14 | 0x48: 'AABL', 0x49: 'SABL', 0x4A: 'NABL', 0x4B: 'XAXL', 0x4C: 'XAYL', 0x4D: 'XABL', 0x4E: 'XAZL', 15 | 0x4F: 'XASL', 0x50: 'ADD', 0x51: 'SUB', 0x52: 'AND', 0x53: 'ORI', 0x54: 'ORE', 0x55: 'XFR', 0x56: '??', 16 | 0x57: '??', 0x58: 'AABW', 0x59: 'SABW', 0x5A: 'NABW', 0x5B: 'XAXW', 0x5C: 'XAYW', 0x5D: 'XABW', 17 | 0x5E: 'XAZW', 0x5F: 'XASW', 0x60: 'LDXW', 0x61: 'LDXW', 0x62: 'LDXW', 0x63: 'LDXW', 0x64: 'LDXW', 18 | 0x65: 'LDXW', 0x66: 'JSYS', 0x67: '??', 0x68: 'STXW', 0x69: 'STXW', 0x6A: 'STXW', 0x6B: 'STXW', 19 | 0x6C: 'STXW', 0x6D: 'STXW', 0x6E: 'LDCC', 0x6F: 'STCC', 0x70: 'JMP', 0x71: 'JMP', 0x72: 'JMP', 20 | 0x73: 'JMP', 0x74: 'JMP', 0x75: 'JMP', 0x76: '??', 0x77: '??', 0x78: '??', 0x79: 'JSR', 0x7A: 'JSR', 21 | 0x7B: 'JSR', 0x7C: 'JSR', 0x7D: 'JSR', 0x7E: 'PUSH', 0x7F: 'POP', 0x80: 'LDAL', 0x81: 'LDAL', 22 | 0x82: 'LDAL', 0x83: 'LDAL', 0x84: 'LDAL', 0x85: 'LDAL', 0x86: '??', 0x87: '??', 0x88: 'LALA', 23 | 0x89: 'LALB', 0x8A: 'LALX', 0x8B: 'LALY', 0x8C: 'LALZ', 0x8D: 'LALS', 0x8E: 'LALC', 0x8F: 'LALP', 24 | 0x90: 'LDAW', 0x91: 'LDAW', 0x92: 'LDAW', 0x93: 'LDAW', 0x94: 'LDAW', 0x95: 'LDAW', 0x96: '??', 25 | 0x97: '??', 0x98: 'LAWA', 0x99: 'LAWB', 0x9A: 'LAWX', 0x9B: 'LAWY', 0x9C: 'LAWZ', 0x9D: 'LAWS', 26 | 0x9E: 'LAWC', 0x9F: 'LAWP', 0xA0: 'STAL', 0xA1: 'STAL', 0xA2: 'STAL', 0xA3: 'STAL', 0xA4: 'STAL', 27 | 0xA5: 'STAL', 0xA6: '??', 0xA7: '??', 0xA8: 'SALA', 0xA9: 'SALB', 0xAA: 'SALX', 0xAB: 'SALY', 0xAC: 'SALZ', 28 | 0xAD: 'SALS', 0xAE: 'SALC', 0xAF: 'SALP', 0xB0: 'STAW', 0xB1: 'STAW', 0xB2: 'STAW', 0xB3: 'STAW', 29 | 0xB4: 'STAW', 0xB5: 'STAW', 0xB6: '??', 0xB7: '??', 0xB8: 'SAWA', 0xB9: 'SAWB', 0xBA: 'SAWX', 0xBB: 'SAWY', 30 | 0xBC: 'SAWZ', 0xBD: 'SAWS', 0xBE: 'SAWC', 0xBF: 'SAWP', 0xC0: 'LDBL', 0xC1: 'LDBL', 0xC2: 'LDBL', 31 | 0xC3: 'LDBL', 0xC4: 'LDBL', 0xC5: 'LDBL', 0xC6: '??', 0xC7: '??', 0xC8: 'LBLA', 0xC9: 'LBLB', 0xCA: 'LBLX', 32 | 0xCB: 'LBLY', 0xCC: 'LBLZ', 0xCD: 'LBLS', 0xCE: 'LBLC', 0xCF: 'LBLP', 0xD0: 'LDBW', 0xD1: 'LDBW', 33 | 0xD2: 'LDBW', 0xD3: 'LDBW', 0xD4: 'LDBW', 0xD5: 'LDBW', 0xD6: '??', 0xD7: '??', 0xD8: 'LBWA', 0xD9: 'LBWB', 34 | 0xDA: 'LBWX', 0xDB: 'LDBW', 0xDC: 'LBWZ', 0xDD: 'LBWS', 0xDE: 'LBWC', 0xDF: 'LBWP', 0xE0: 'STBL', 35 | 0xE1: 'STBL', 0xE2: 'STBL', 0xE3: 'STBL', 0xE4: 'STBL', 0xE5: 'STBL', 0xE6: '??', 0xE7: '??', 0xE8: 'SBLA', 36 | 0xE9: 'SBLB', 0xEA: 'SBLX', 0xEB: 'SBLY', 0xEC: 'SBLZ', 0xED: 'SBLS', 0xEE: 'SBLC', 0xEF: 'SBLP', 37 | 0xF0: 'STBW', 0xF1: 'STBW', 0xF2: 'STBW', 0xF3: 'STBW', 0xF4: 'STBW', 0xF5: 'STBW', 0xF6: '??', 0xF7: '??', 38 | 0xF8: 'SBWA', 0xF9: 'SBWB', 0xFA: 'SBWX', 0xFB: 'SBWY', 0xFC: 'SBWZ', 0xFD: 'SBWS', 0xFE: 'SBWC', 0xFF: 'SBWP' 39 | } 40 | 41 | def get_op_code(code): 42 | return OP_CODES.get(code, '') 43 | 44 | # $scope module CPU6TestBench $end 45 | # $var wire 1 ! writeEnBus $end 46 | # $var wire 8 " data_r2c [7:0] $end 47 | 48 | class SignalDef(object): 49 | def __init__(self, module, cols): 50 | self.module = module 51 | self.size, self.tag, self.name = 0, '', '' 52 | if len(cols) < 4: 53 | return 54 | size, self.tag, self.name = cols[2:2+3] 55 | self.size = int(size) 56 | 57 | def isValid(self): 58 | return self.size != 0 59 | 60 | def getName(self): 61 | return f'{self.module}.{self.name}' 62 | 63 | def __str__(self): 64 | return f'{self.getName()} {self.size} {self.tag}' 65 | 66 | radixMap = {'b': 2} 67 | 68 | class Signal(object): 69 | def __init__(self, time, sigDef, value): 70 | self.time = time 71 | self.sigDef = sigDef 72 | self.value = value 73 | 74 | def getName(self): 75 | return self.sigDef.getName() 76 | 77 | def getTag(self): 78 | return self.sigDef.tag 79 | 80 | def __len__(self): 81 | return self.sigDef.size 82 | 83 | def __str__(self): 84 | return self.value 85 | 86 | class VCDFile(object): 87 | def __init__(self, fname): 88 | self.signalTagMap = {} 89 | self.signalMap = {} 90 | self.signals = [] 91 | with open(fname) as f: 92 | content = f.read() 93 | lines = content.split('\n') 94 | index = 0 95 | while index < len(lines): 96 | line = lines[index] 97 | index += 1 98 | if line == '$dumpvars': 99 | break 100 | cols = line.split() 101 | if len(cols) > 0: 102 | if cols[0] == '$scope': 103 | module = cols[2] 104 | if cols[0] == '$var': 105 | sd = SignalDef(module, cols) 106 | if sd.isValid(): 107 | self.signalMap[sd.tag] = sd 108 | self.signalTagMap[sd.getName()] = sd.tag 109 | prevTime = -1 110 | time = 0 111 | signals = {} 112 | for tag, df in self.signalMap.items(): 113 | sig = Signal(time, df, -1) 114 | signals[sig.getTag()] = sig 115 | while index < len(lines): 116 | line = lines[index] 117 | index += 1 118 | cols = line.split() 119 | if len(cols) > 0: 120 | # #5000 121 | if line[0] == '#': 122 | time = int(line[1:]) 123 | if time != prevTime: 124 | if len(signals): 125 | self.signals.append(self.copy(signals)) 126 | prevTime = time 127 | else: 128 | # b101 B" 129 | # b101 :" 130 | # b1000000000000010000001111111110011011000000000000000000 9 131 | # 1$ 132 | if len(cols) > 1 and cols: 133 | valueStr = cols[0] 134 | value = -1 135 | if 'x' not in valueStr[1:]: 136 | value = int(valueStr[1:], radixMap[valueStr[0]]) 137 | sig = Signal(time, self.signalMap.get(cols[1]), value) 138 | signals[sig.getTag()] = sig 139 | elif cols[0] != '$end': 140 | valueStr = cols[0] 141 | #print(valueStr) 142 | value = -1 143 | if 'x' not in valueStr[0]: 144 | value = int(valueStr[0]) 145 | #print(value) 146 | sig = Signal(time, self.signalMap.get(valueStr[1:]), value) 147 | signals[sig.getTag()] = sig 148 | 149 | def copy(self, sigs): 150 | result = {} 151 | for k, v in sigs.items(): 152 | result[k] = v 153 | return result 154 | 155 | e6Map = {0:'', 1:'RR<-FBus', 2:'RI<-FBus', 3:'e6.3', 4:'e6.4', 5:'MR<>WR', 6:'AR<-', 7:'LoadCC'} 156 | k11Map = {0:'', 1:'k11.1', 2:'k11.2', 3:'Load F11', 4:'R[]<-', 5:'k11.5', 6:'WAR.LO<-', 7:'WrBus'} 157 | d2d3Map = {0:'D=Swap', 1:'D=Reg', 2:'D=MAR.HI', 3:'D=MAR.LO', 4:'d2d3.4', 5:'d2d3.5', 6:'d2d3.6', 7:'d2d3.7', 8:'d2d3.8', 158 | 9:'D=CC', 10:'D=BusIn', 11:'d2d3.11', 12:'d2d3.12', 13:'D=const', 14:'d2d3.14', 15:'d2d3.15'} 159 | h11Map = {0:'', 1:'StBusR', 2:'StBusW', 3:'WAR.HI', 4:'h11.4', 5:'h11.5', 6:'', 7:'LDSwap'} 160 | e7Map = {0:'', 1:'e7.1', 2:'LoadFl', 3:'BusR<-Bus', 4:'e7.4', 5:'e7.5', 6:'e7.6', 7:'e7.7'} 161 | 162 | ALU_SRC_MAP = [['A', 'Q'], ['A', 'B'], ['0', 'Q'], ['0', 'B'], ['0', 'A'], ['D', 'A'], ['D', 'Q'], ['D', '0']] 163 | ALU_OP_MAP = ['{r}+{s}', '{s}-{r}', '{r}-{s}', '{r}|{s}', '{r}&{s}', '(~{r})&{s}', '{r}^{s}', '~({r}^{s})'] 164 | ALU_MEM_DEST_MAP = ['', '', 'r{b}={f}', 'r{b}={f}', 'r{b}=({f})>>1', 'r{b}=({f})>>1', 'r{b}=({f})<<1', 'r{b} =({f})<<1'] 165 | ALU_Q_DEST_MAP = ['Q = {f}', '', '', '', 'Q>>=1', '', 'Q<<=1', ''] 166 | ALU_OUT_MAP = ['Y={f}', 'Y={f}', 'Y={a}', 'Y={f}', 'Y={f}', 'Y={f}', 'Y={f}', 'Y={f}'] 167 | 168 | 169 | class Disassembler(object): 170 | def __init__(self, signals, signalTagMap): 171 | self.signals = signals 172 | self.signalTagMap = signalTagMap 173 | 174 | def getSignal(self, sig, name): 175 | tag = self.signalTagMap[name] 176 | return sig[tag] 177 | 178 | def getALUCode(self, aluA, aluB, aluOp, aluSrc, aluDest, cin, cout): 179 | r, s = ALU_SRC_MAP[aluSrc] 180 | if r == 'A': 181 | r = f'r{aluA}' 182 | elif r == 'B': 183 | r = f'r{aluB}' 184 | if s == 'A': 185 | s = f'r{aluA}' 186 | elif s == 'B': 187 | s = f'r{aluB}' 188 | f = ALU_OP_MAP[aluOp].format(r=r, s=s) 189 | mem = ALU_MEM_DEST_MAP[aluDest].format(b=aluB, f=f) 190 | q = ALU_Q_DEST_MAP[aluDest].format(f=f) 191 | a = f'r{aluA}' 192 | y = ALU_OUT_MAP[aluDest].format(f=f, a=a) 193 | c = '' 194 | if cout: 195 | c = 'C' 196 | if (aluOp == 0 or aluOp == 1 or aluOp == 2) and cin: 197 | return f'{mem}+{cin} {q} {y}+{cin} {c}' 198 | return f'{mem} {q} {y} {c}' 199 | 200 | def disassembleAll(self): 201 | code = [] 202 | i = 0 203 | while i < len(self.signals): 204 | sig = self.signals[i] 205 | i += 1 206 | if self.getSignal(sig, 'cg0.clock').value == 1: 207 | instruction_start = self.getSignal(sig, 'cpu.instruction_start').value 208 | if instruction_start == 1: 209 | code.append('') 210 | memory_address = self.getSignal(sig, 'cpu.memory_address').value 211 | code.append(f'* memory_address: {memory_address:04x}') 212 | code.append(self.disassembleOne(sig)) 213 | return code 214 | 215 | def disassembleOne(self, sig): 216 | clock = self.getSignal(sig, 'cg0.clock') 217 | addr = self.getSignal(sig, 'cpu.uc_rom_address_pipe').value 218 | e6 = self.getSignal(sig, 'cpu.e6').value 219 | k11 = self.getSignal(sig, 'cpu.k11').value 220 | h11 = self.getSignal(sig, 'cpu.h11').value 221 | pcInc = self.getSignal(sig, 'cpu.pc_increment').value 222 | d2d3 = self.getSignal(sig, 'cpu.d2d3').value 223 | e7 = self.getSignal(sig, 'cpu.e7').value 224 | constant = self.getSignal(sig, 'cpu.constant').value 225 | dataInBus = self.getSignal(sig, 'cpu.dataInBus').value 226 | map_rom_data = self.getSignal(sig, 'cpu.map_rom_data').value 227 | reg_ram_data_out = self.getSignal(sig, 'cpu.reg_ram_data_out').value 228 | register_index = self.getSignal(sig, 'cpu.register_index').value 229 | FBus = self.getSignal(sig, 'cpu.FBus').value 230 | DPBus = self.getSignal(sig, 'cpu.DPBus').value 231 | memory_address = self.getSignal(sig, 'cpu.memory_address').value 232 | result_register = self.getSignal(sig, 'cpu.result_register').value 233 | alu0_yout = self.getSignal(sig, 'cpu.alu0_yout').value & 0xf 234 | alu1_yout = self.getSignal(sig, 'cpu.alu1_yout').value & 0xf 235 | bus_read = self.getSignal(sig, 'cpu.bus_read').value 236 | alu_out = (alu1_yout << 4) | alu0_yout 237 | mar_hi = (memory_address >> 8) & 0xff 238 | mar_lo = memory_address & 0xff 239 | bit53 = self.getSignal(sig, 'cpu.bit53').value 240 | reg_ram_addr = self.getSignal(sig, 'cpu.reg_ram_addr').value 241 | flags_register = self.getSignal(sig, 'cpu.flags_register').value 242 | swap_register = self.getSignal(sig, 'cpu.swap_register').value 243 | seq0_orin = self.getSignal(sig, 'cpu.seq0_orin').value 244 | case_ = self.getSignal(sig, 'cpu.case_').value 245 | j13 = self.getSignal(sig, 'cpu.j13').value 246 | condition_codes = self.getSignal(sig, 'cpu.condition_codes').value 247 | f6h6 = self.getSignal(sig, 'cpu.f6h6').value 248 | 249 | if k11 == 6: 250 | k11Map[6] = f'WR.LO<-RR({result_register:02x})' 251 | if e6 == 5: 252 | k11Map[6] = f'WR.LO<-MR.LO({mar_lo:02x})' 253 | if h11 == 3: 254 | h11Map[3] = f'WR.HI<-RR({result_register:02x})' 255 | if e6 == 5: 256 | h11Map[3] = f'WR.HI<-MR.HI({mar_hi:02x})' 257 | fbr = f'F=Y({alu_out:02x})' 258 | if h11 == 6: 259 | fbr = f'F=Map({map_rom_data:02x})' 260 | if h11 == 5: 261 | h11Map[5] = f'PC++({memory_address:04x})' 262 | if h11 == 7: 263 | h11Map[7] = f'Swap<-D({DPBus:02x})' 264 | if d2d3 == 0: 265 | d2d3Map[0] = f'D=Swap({swap_register:02x})' 266 | if d2d3 == 1: 267 | d2d3Map[1] = f'D=R[{reg_ram_addr:02x}]({reg_ram_data_out:02x})' 268 | if d2d3 == 9: 269 | d2d3Map[9] = f'D=CC({((~condition_codes)<<4)&0xff:02x})' 270 | if d2d3 == 10: 271 | d2d3Map[10] = f'D=BusR({bus_read:02x})' 272 | if d2d3 == 13: 273 | d2d3Map[13] = f'D=const({constant:02x})' 274 | if e6 == 1: 275 | e6Map[1] = f'RR<-F({FBus:02x})' 276 | if e6 == 2: 277 | e6Map[2] = f'RI<-F({FBus:02x})' 278 | if e6 == 6: 279 | e6Map[6] = f'AR<-F({FBus:02x})' 280 | if k11 == 4: 281 | k11Map[4] = f'R[{reg_ram_addr:02x}]<-RR({result_register:02x})' 282 | alu_a = self.getSignal(sig, 'cpu.alu_a').value 283 | alu_b = self.getSignal(sig, 'cpu.alu_b').value 284 | alu_src = self.getSignal(sig, 'cpu.alu_src').value 285 | alu_op = self.getSignal(sig, 'cpu.alu_op').value 286 | alu_dest = self.getSignal(sig, 'cpu.alu_dest').value 287 | alu0_cin = self.getSignal(sig, 'cpu.alu0_cin').value 288 | alu1_cout = self.getSignal(sig, 'cpu.alu1_cout').value 289 | aluCode = self.getALUCode(alu_a, alu_b, alu_op, alu_src, alu_dest, alu0_cin, alu1_cout) 290 | if k11 == 3: 291 | k11Map[3] = f'F11<-aluB({alu_b:1x})' 292 | if e7 == 2: 293 | e7Map[2] = f'LoadFl({flags_register:02x})' 294 | if e7 == 3: 295 | e7Map[3] = f'BusR<-Bus({dataInBus:02x})' 296 | 297 | inst = '' 298 | if addr == 0x103: 299 | inst = get_op_code(DPBus) 300 | time = int(clock.time/100) 301 | 302 | oren = ' ' 303 | if case_ == 0 and seq0_orin != 0: 304 | oren = f'OR{seq0_orin:1x}' 305 | comb = f'{time} {addr:03x}: {oren} {d2d3Map[d2d3]:12s} {aluCode:24s} {fbr:9s}' 306 | seq = f'{e6Map[e6]} {h11Map[h11]} {k11Map[k11]} {e7Map[e7]} {inst}' 307 | return f'{comb} f6hf({f6h6}) | {seq} | FL({flags_register:02x}) CC({condition_codes:02x})' 308 | 309 | if __name__ == '__main__': 310 | vcd = VCDFile('vcd/CPUTestBench.vcd') 311 | dis = Disassembler(vcd.signals, vcd.signalTagMap) 312 | code = dis.disassembleAll() 313 | with open('vcd/CPUTestBench.txt', 'wt') as f: 314 | for c in code: 315 | f.write(f'{c}\n') 316 | -------------------------------------------------------------------------------- /Verilog/programs/alu_test.txt: -------------------------------------------------------------------------------- 1 | 01 // NOP 2 | 01 // NOP 3 | 80 // LDAL #fc 4 | fc 5 | 01 // NOP 6 | 20 // INR AL, 1 7 | 10 8 | 14 // BZ 8 9 | 08 10 | C0 // LDBL 'A' 11 | 41 12 | e1 // STBL #f201 13 | f2 14 | 01 15 | 71 // JMP #8005 16 | 80 17 | 05 18 | 01 // NOP 19 | 01 // NOP 20 | 90 // LDAW #fffc 21 | ff 22 | fc 23 | 01 // NOP 24 | 30 // INRW A, 1 25 | 00 26 | 14 // BZ 8 27 | 08 28 | c0 // LDBL 'B' 29 | 42 30 | e1 // STBL #f201 31 | f2 32 | 01 33 | 71 // JMP #8017 34 | 80 35 | 17 36 | 80 // LDAL 4 37 | 04 38 | 21 // DCR AL, 1 39 | 10 40 | 14 // BZ 8 41 | 08 42 | c0 // LDBL 'C' 43 | 43 44 | e1 // STBL #f201 45 | f2 46 | 01 47 | 71 // JMP #8025 48 | 80 49 | 25 50 | 80 // LDAL 03 51 | 03 52 | c0 // LDBL 'D' 53 | 44 54 | e1 // STBL #f201 55 | f2 56 | 01 57 | 21 // DCR AL, 1 58 | 10 59 | 15 // BNZ f7 60 | f7 61 | 80 // LDAL '\n' 62 | 0a 63 | a1 // STAL #f201 64 | f2 65 | 01 66 | 90 // LDAW #0201 67 | 02 68 | 01 69 | 26 // RRR AL, 1 70 | 00 71 | 26 // RRR AL, 1 72 | 00 73 | 26 // RRR AL, 1 74 | 00 75 | 26 // RRR AL, 1 76 | 00 77 | 90 // LDAW #0201 78 | 02 79 | 01 80 | 36 // RRR AW, 1 81 | 00 82 | 36 // RRR AW, 1 83 | 00 84 | 36 // RRR AW, 1 85 | 00 86 | 36 // RRR AW, 1 87 | 00 88 | 90 // LDAW #4080 89 | 40 90 | 80 91 | 37 // RLR AW, 1 92 | 00 93 | 37 // RLR AW, 1 94 | 00 95 | 37 // RLR AW, 1 96 | 00 97 | 37 // RLR AW, 1 98 | 00 99 | 06 // SL 100 | 07 // RL 101 | 90 // LDAW #a55a 102 | a5 103 | 5a 104 | d1 // LDBW 0 105 | 00 106 | 00 107 | d1 // LDBW 108 | 00 109 | 24 110 | 80 // LDAL #99 111 | 99 112 | a1 // STAL #0003 113 | 00 114 | 03 115 | 21 // DCR AL, 1 116 | 10 117 | a1 // STAL #0004 118 | 00 119 | 04 120 | 80 // LDAL #01 121 | 01 122 | a1 // STAL #f900 (sim_end <= 1) 123 | f9 124 | 00 125 | 01 // NOP 126 | 01 127 | 01 128 | 01 129 | 01 130 | 01 131 | 01 132 | 01 133 | 01 134 | 01 135 | 01 136 | 01 137 | 01 138 | 01 139 | 01 140 | 01 141 | 01 142 | 01 143 | 01 144 | 01 145 | 01 146 | 01 147 | 01 148 | 01 149 | 01 150 | 01 151 | 01 152 | 01 153 | 01 154 | 01 155 | 01 156 | 01 157 | 01 158 | 01 159 | 01 160 | 01 161 | 01 162 | 01 163 | 01 164 | 01 165 | 01 166 | 01 167 | 01 168 | 01 169 | 01 170 | 01 171 | 01 172 | 01 173 | 01 174 | 01 175 | 01 176 | 01 177 | 01 178 | 01 179 | 01 180 | 01 181 | 01 182 | 01 183 | 01 184 | 01 185 | 01 186 | 01 187 | 01 188 | 01 189 | 01 190 | 01 191 | 01 192 | 01 193 | 01 194 | 01 195 | 01 196 | 01 197 | 01 198 | 01 199 | 01 200 | 01 201 | 01 202 | 01 203 | 01 204 | 01 205 | 01 206 | 01 207 | 01 208 | 01 209 | 01 210 | 01 211 | 01 212 | 01 213 | 01 214 | 01 215 | 01 216 | 01 217 | 01 218 | 01 219 | 01 220 | 01 221 | 01 222 | 01 223 | 01 224 | 01 225 | 01 226 | 01 227 | 01 228 | 01 229 | 01 230 | 01 231 | 01 232 | 01 233 | 01 234 | 01 235 | 01 236 | 01 237 | 01 238 | 01 239 | 01 240 | 01 241 | 01 242 | 01 243 | 01 244 | 01 245 | 01 246 | 01 247 | 01 248 | 01 249 | 01 250 | 01 251 | 01 252 | 01 253 | 01 254 | 01 255 | 01 256 | 01 257 | 01 258 | 01 259 | 01 260 | 01 261 | 01 262 | 01 263 | 01 264 | 01 265 | 01 266 | 01 267 | 01 268 | 01 269 | 01 270 | 01 271 | 01 272 | 01 273 | 01 274 | 01 275 | 01 276 | 01 277 | 01 278 | 01 279 | 01 280 | 01 281 | 01 282 | 01 283 | 01 284 | 01 285 | 01 286 | 01 287 | 01 288 | 01 289 | 01 290 | 01 291 | 01 292 | 01 293 | 01 294 | 01 295 | 01 296 | 01 297 | 01 298 | 01 299 | 01 300 | 01 301 | 01 302 | 01 303 | 01 304 | 01 305 | 01 306 | 01 307 | 01 308 | 01 309 | 01 310 | 01 311 | -------------------------------------------------------------------------------- /Verilog/programs/blink.txt: -------------------------------------------------------------------------------- 1 | 01 // NOP 2 | 01 // NOP 3 | 80 // LDAL #00 4 | 00 5 | 01 // NOP 6 | a1 // STAL #5c00 (LEDPanel) 7 | 5c 8 | 00 9 | 20 // INR AL, 1 10 | 10 11 | 0e //DLY (0e) 12 | 0e //DLY (0e) 13 | 0e //DLY (0e) 14 | 0e //DLY (0e) 15 | 0e //DLY (0e) 16 | 0e //DLY (0e) 17 | 0e //DLY (0e) 18 | 0e //DLY (0e) 19 | 71 // JMP #fd05 20 | fd 21 | 05 22 | 01 // NOP 23 | 01 24 | 01 25 | 01 26 | 01 27 | 01 28 | 01 29 | 01 30 | 01 31 | 01 32 | 01 33 | 01 34 | 01 35 | 01 36 | 01 37 | 01 38 | 01 39 | 01 40 | 01 41 | 01 42 | 01 43 | 01 44 | 01 45 | 01 46 | 01 47 | 01 48 | 01 49 | 01 50 | 01 51 | 01 52 | 01 53 | 01 54 | 01 55 | 01 56 | 01 57 | 01 58 | 01 59 | 01 60 | 01 61 | 01 62 | 01 63 | 01 64 | 01 65 | 01 66 | 01 67 | 01 68 | 01 69 | 01 70 | 01 71 | 01 72 | 01 73 | 01 74 | 01 75 | 01 76 | 01 77 | 01 78 | 01 79 | 01 80 | 01 81 | 01 82 | 01 83 | 01 84 | 01 85 | 01 86 | 01 87 | 01 88 | 01 89 | 01 90 | 01 91 | 01 92 | 01 93 | 01 94 | 01 95 | 01 96 | 01 97 | 01 98 | 01 99 | 01 100 | 01 101 | 01 102 | 01 103 | 01 104 | 01 105 | 01 106 | 01 107 | 01 108 | 01 109 | 01 110 | 01 111 | 01 112 | 01 113 | 01 114 | 01 115 | 01 116 | 01 117 | 01 118 | 01 119 | 01 120 | 01 121 | 01 122 | 01 123 | 01 124 | 01 125 | 01 126 | 01 127 | 01 128 | 01 129 | 01 130 | 01 131 | 01 132 | 01 133 | 01 134 | 01 135 | 01 136 | 01 137 | 01 138 | 01 139 | 01 140 | 01 141 | 01 142 | 01 143 | 01 144 | 01 145 | 01 146 | 01 147 | 01 148 | 01 149 | 01 150 | 01 151 | 01 152 | 01 153 | 01 154 | 01 155 | 01 156 | 01 157 | 01 158 | 01 159 | 01 160 | 01 161 | 01 162 | 01 163 | 01 164 | 01 165 | 01 166 | 01 167 | 01 168 | 01 169 | 01 170 | 01 171 | 01 172 | 01 173 | 01 174 | 01 175 | 01 176 | 01 177 | 01 178 | 01 179 | 01 180 | 01 181 | 01 182 | 01 183 | 01 184 | 01 185 | 01 186 | 01 187 | 01 188 | 01 189 | 01 190 | 01 191 | 01 192 | 01 193 | 01 194 | 01 195 | 01 196 | 01 197 | 01 198 | 01 199 | 01 200 | 01 201 | 01 202 | 01 203 | 01 204 | 01 205 | 01 206 | 01 207 | 01 208 | 01 209 | 01 210 | 01 211 | 01 212 | 01 213 | 01 214 | 01 215 | 01 216 | 01 217 | 01 218 | 01 219 | 01 220 | 01 221 | 01 222 | 01 223 | 01 224 | 01 225 | 01 226 | 01 227 | 01 228 | 01 229 | 01 230 | 01 231 | 01 232 | 01 233 | 01 234 | 01 235 | 01 236 | 01 237 | 01 238 | 01 239 | 01 240 | 01 241 | 01 242 | 01 243 | 01 244 | 01 245 | 01 246 | 01 247 | 01 248 | 01 249 | 01 250 | 01 251 | 01 252 | 01 253 | 01 254 | 01 255 | 01 256 | 01 257 | -------------------------------------------------------------------------------- /Verilog/programs/bnz_test.txt: -------------------------------------------------------------------------------- 1 | 01 // NOP 2 | 01 // NOP 3 | 80 // LDAL #fd or ff 4 | ff 5 | 01 // NOP 6 | 20 // INR AL, 1 7 | 10 8 | 15 // BNZ 8 9 | 08 10 | 80 // LDAL 'P' 11 | 50 12 | a1 // STAL #f201 13 | f2 14 | 01 15 | 71 // JMP #8005 16 | 80 17 | 05 18 | 80 // LDAL 'A' 19 | 41 20 | a1 // STAL #f201 21 | f2 22 | 01 23 | 80 // LDAL 'S' 24 | 53 25 | a1 // STAL #f201 26 | f2 27 | 01 28 | 80 // LDAL 'S' 29 | 53 30 | a1 // STAL #f201 31 | f2 32 | 01 33 | 80 // LDAL '\n' 34 | 0a 35 | a1 // STAL #f201 36 | f2 37 | 01 38 | 80 // LDAL #01 39 | 01 40 | a1 // STAL #f900 (sim_end <= 1) 41 | f9 42 | 00 43 | 01 // NOP 44 | 01 45 | 01 46 | 01 47 | 01 48 | 01 49 | 01 50 | 01 51 | 01 52 | 01 53 | 01 54 | 01 55 | 01 56 | 01 57 | 01 58 | 01 59 | 01 60 | 01 61 | 01 62 | 01 63 | 01 64 | 01 65 | 01 66 | 01 67 | 01 68 | 01 69 | 01 70 | 01 71 | 01 72 | 01 73 | 01 74 | 01 75 | 01 76 | 01 77 | 01 78 | 01 79 | 01 80 | 01 81 | 01 82 | 01 83 | 01 84 | 01 85 | 01 86 | 01 87 | 01 88 | 01 89 | 01 90 | 01 91 | 01 92 | 01 93 | 01 94 | 01 95 | 01 96 | 01 97 | 01 98 | 01 99 | 01 100 | 01 101 | 01 102 | 01 103 | 01 104 | 01 105 | 01 106 | 01 107 | 01 108 | 01 109 | 01 110 | 01 111 | 01 112 | 01 113 | 01 114 | 01 115 | 01 116 | 01 117 | 01 118 | 01 119 | 01 120 | 01 121 | 01 122 | 01 123 | 01 124 | 01 125 | 01 126 | 01 127 | 01 128 | 01 129 | 01 130 | 01 131 | 01 132 | 01 133 | 01 134 | 01 135 | 01 136 | 01 137 | 01 138 | 01 139 | 01 140 | 01 141 | 01 142 | 01 143 | 01 144 | 01 145 | 01 146 | 01 147 | 01 148 | 01 149 | 01 150 | 01 151 | 01 152 | 01 153 | 01 154 | 01 155 | 01 156 | 01 157 | 01 158 | 01 159 | 01 160 | 01 161 | 01 162 | 01 163 | 01 164 | 01 165 | 01 166 | 01 167 | 01 168 | 01 169 | 01 170 | 01 171 | 01 172 | 01 173 | 01 174 | 01 175 | 01 176 | 01 177 | 01 178 | 01 179 | 01 180 | 01 181 | 01 182 | 01 183 | 01 184 | 01 185 | 01 186 | 01 187 | 01 188 | 01 189 | 01 190 | 01 191 | 01 192 | 01 193 | 01 194 | 01 195 | 01 196 | 01 197 | 01 198 | 01 199 | 01 200 | 01 201 | 01 202 | 01 203 | 01 204 | 01 205 | 01 206 | 01 207 | 01 208 | 01 209 | 01 210 | 01 211 | 01 212 | 01 213 | 01 214 | 01 215 | 01 216 | 01 217 | 01 218 | 01 219 | 01 220 | 01 221 | 01 222 | 01 223 | 01 224 | 01 225 | 01 226 | 01 227 | 01 228 | 01 229 | 01 230 | 01 231 | 01 232 | 01 233 | 01 234 | 01 235 | 01 236 | 01 237 | 01 238 | 01 239 | 01 240 | 01 241 | 01 242 | 01 243 | 01 244 | 01 245 | 01 246 | 01 247 | 01 248 | 01 249 | 01 250 | 01 251 | 01 252 | 01 253 | 01 254 | 01 255 | 01 256 | 01 257 | -------------------------------------------------------------------------------- /Verilog/programs/cylon.txt: -------------------------------------------------------------------------------- 1 | 01 // NOP 2 | 01 // NOP 3 | 01 // NOP 4 | 80 // LDAL #01 5 | 01 6 | a1 // STAL #5c00 (LEDPanel) 7 | 5c 8 | 00 9 | 0e 10 | 0e 11 | 0e 12 | 0e 13 | 0e 14 | 0e 15 | 0e 16 | 0e 17 | 2d // SLAL 18 | 15 // BNZ 19 | f2 20 | 80 // LDAL #80 21 | 80 22 | a1 // STAL #5c00 (LEDPanel) 23 | 5c 24 | 00 25 | 0e 26 | 0e 27 | 0e 28 | 0e 29 | 0e 30 | 0e 31 | 0e 32 | 0e 33 | 80 // LDAL #40 34 | 40 35 | a1 // STAL #5c00 (LEDPanel) 36 | 5c 37 | 00 38 | 0e 39 | 0e 40 | 0e 41 | 0e 42 | 0e 43 | 0e 44 | 0e 45 | 0e 46 | 2c // SRAL 47 | 15 // BNZ 48 | f2 49 | 71 // JMP #fd03 50 | fd 51 | 03 52 | 01 // NOP 53 | 01 54 | 01 55 | 01 56 | 01 57 | 01 58 | 01 59 | 01 60 | 01 61 | 01 62 | 01 63 | 01 64 | 01 65 | 01 66 | 01 67 | 01 68 | 01 69 | 01 70 | 01 71 | 01 72 | 01 73 | 01 74 | 01 75 | 01 76 | 01 77 | 01 78 | 01 79 | 01 80 | 01 81 | 01 82 | 01 83 | 01 84 | 01 85 | 01 86 | 01 87 | 01 88 | 01 89 | 01 90 | 01 91 | 01 92 | 01 93 | 01 94 | 01 95 | 01 96 | 01 97 | 01 98 | 01 99 | 01 100 | 01 101 | 01 102 | 01 103 | 01 104 | 01 105 | 01 106 | 01 107 | 01 108 | 01 109 | 01 110 | 01 111 | 01 112 | 01 113 | 01 114 | 01 115 | 01 116 | 01 117 | 01 118 | 01 119 | 01 120 | 01 121 | 01 122 | 01 123 | 01 124 | 01 125 | 01 126 | 01 127 | 01 128 | 01 129 | 01 130 | 01 131 | 01 132 | 01 133 | 01 134 | 01 135 | 01 136 | 01 137 | 01 138 | 01 139 | 01 140 | 01 141 | 01 142 | 01 143 | 01 144 | 01 145 | 01 146 | 01 147 | 01 148 | 01 149 | 01 150 | 01 151 | 01 152 | 01 153 | 01 154 | 01 155 | 01 156 | 01 157 | 01 158 | 01 159 | 01 160 | 01 161 | 01 162 | 01 163 | 01 164 | 01 165 | 01 166 | 01 167 | 01 168 | 01 169 | 01 170 | 01 171 | 01 172 | 01 173 | 01 174 | 01 175 | 01 176 | 01 177 | 01 178 | 01 179 | 01 180 | 01 181 | 01 182 | 01 183 | 01 184 | 01 185 | 01 186 | 01 187 | 01 188 | 01 189 | 01 190 | 01 191 | 01 192 | 01 193 | 01 194 | 01 195 | 01 196 | 01 197 | 01 198 | 01 199 | 01 200 | 01 201 | 01 202 | 01 203 | 01 204 | 01 205 | 01 206 | 01 207 | 01 208 | 01 209 | 01 210 | 01 211 | 01 212 | 01 213 | 01 214 | 01 215 | 01 216 | 01 217 | 01 218 | 01 219 | 01 220 | 01 221 | 01 222 | 01 223 | 01 224 | 01 225 | 01 226 | 01 227 | 01 228 | 01 229 | 01 230 | 01 231 | 01 232 | 01 233 | 01 234 | 01 235 | 01 236 | 01 237 | 01 238 | 01 239 | 01 240 | 01 241 | 01 242 | 01 243 | 01 244 | 01 245 | 01 246 | 01 247 | 01 248 | 01 249 | 01 250 | 01 251 | 01 252 | 01 253 | 01 254 | 01 255 | 01 256 | 01 257 | 01 258 | 01 259 | 01 260 | 01 261 | 01 262 | 01 263 | 01 264 | 01 265 | 01 266 | 01 267 | 01 268 | 01 269 | 01 270 | -------------------------------------------------------------------------------- /Verilog/programs/hellorld.txt: -------------------------------------------------------------------------------- 1 | 01 // NOP 2 | 01 // NOP 3 | 80 // LDAL 'H' 4 | 48 5 | a1 // STAL #f201 6 | f2 7 | 01 8 | 80 // LDAL 'e' 9 | 65 10 | a1 // STAL #f201 11 | f2 12 | 01 13 | 80 // LDAL 'l' 14 | 6c 15 | a1 // STAL #f201 16 | f2 17 | 01 18 | 80 // LDAL 'l' 19 | 6c 20 | a1 // STAL #f201 21 | f2 22 | 01 23 | 80 // LDAL 'o' 24 | 6f 25 | a1 // STAL #f201 26 | f2 27 | 01 28 | 80 // LDAL 'r' 29 | 72 30 | a1 // STAL #f201 31 | f2 32 | 01 33 | 80 // LDAL 'l' 34 | 6c 35 | a1 // STAL #f201 36 | f2 37 | 01 38 | 80 // LDAL 'd' 39 | 64 40 | a1 // STAL #f201 41 | f2 42 | 01 43 | 80 // LDAL '!' 44 | 21 45 | a1 // STAL #f201 46 | f2 47 | 01 48 | 80 // LDAL '\n' 49 | 0a 50 | a1 // STAL #f201 51 | f2 52 | 01 53 | 80 // LDAL #01 54 | 01 55 | a1 // STAL #f900 (sim_end <= 1) 56 | f9 57 | 00 58 | 01 // NOP 59 | 01 60 | 01 61 | 01 62 | 01 63 | 01 64 | 01 65 | 01 66 | 01 67 | 01 68 | 01 69 | 01 70 | 01 71 | 01 72 | 01 73 | 01 74 | 01 75 | 01 76 | 01 77 | 01 78 | 01 79 | 01 80 | 01 81 | 01 82 | 01 83 | 01 84 | 01 85 | 01 86 | 01 87 | 01 88 | 01 89 | 01 90 | 01 91 | 01 92 | 01 93 | 01 94 | 01 95 | 01 96 | 01 97 | 01 98 | 01 99 | 01 100 | 01 101 | 01 102 | 01 103 | 01 104 | 01 105 | 01 106 | 01 107 | 01 108 | 01 109 | 01 110 | 01 111 | 01 112 | 01 113 | 01 114 | 01 115 | 01 116 | 01 117 | 01 118 | 01 119 | 01 120 | 01 121 | 01 122 | 01 123 | 01 124 | 01 125 | 01 126 | 01 127 | 01 128 | 01 129 | 01 130 | 01 131 | 01 132 | 01 133 | 01 134 | 01 135 | 01 136 | 01 137 | 01 138 | 01 139 | 01 140 | 01 141 | 01 142 | 01 143 | 01 144 | 01 145 | 01 146 | 01 147 | 01 148 | 01 149 | 01 150 | 01 151 | 01 152 | 01 153 | 01 154 | 01 155 | 01 156 | 01 157 | 01 158 | 01 159 | 01 160 | 01 161 | 01 162 | 01 163 | 01 164 | 01 165 | 01 166 | 01 167 | 01 168 | 01 169 | 01 170 | 01 171 | 01 172 | 01 173 | 01 174 | 01 175 | 01 176 | 01 177 | 01 178 | 01 179 | 01 180 | 01 181 | 01 182 | 01 183 | 01 184 | 01 185 | 01 186 | 01 187 | 01 188 | 01 189 | 01 190 | 01 191 | 01 192 | 01 193 | 01 194 | 01 195 | 01 196 | 01 197 | 01 198 | 01 199 | 01 200 | 01 201 | 01 202 | 01 203 | 01 204 | 01 205 | 01 206 | 01 207 | 01 208 | 01 209 | 01 210 | 01 211 | 01 212 | 01 213 | 01 214 | 01 215 | 01 216 | 01 217 | 01 218 | 01 219 | 01 220 | 01 221 | 01 222 | 01 223 | 01 224 | 01 225 | 01 226 | 01 227 | 01 228 | 01 229 | 01 230 | 01 231 | 01 232 | 01 233 | 01 234 | 01 235 | 01 236 | 01 237 | 01 238 | 01 239 | 01 240 | 01 241 | 01 242 | 01 243 | 01 244 | 01 245 | 01 246 | 01 247 | 01 248 | 01 249 | 01 250 | 01 251 | 01 252 | 01 253 | 01 254 | 01 255 | 01 256 | 01 257 | -------------------------------------------------------------------------------- /Verilog/roms/CPU-6309.txt: -------------------------------------------------------------------------------- 1 | 8b 2 | 01 3 | 19 4 | 4f 5 | 8b 6 | 8b 7 | 85 8 | af 9 | 7b 10 | 93 11 | 8b 12 | 8e 13 | ca 14 | 7e 15 | 8b 16 | 8b 17 | fd 18 | fd 19 | fc 20 | fc 21 | fb 22 | fb 23 | fa 24 | fa 25 | 56 26 | f9 27 | fe 28 | ee 29 | de 30 | ce 31 | ba 32 | 07 33 | ef 34 | ef 35 | ef 36 | ef 37 | ef 38 | ef 39 | ef 40 | ef 41 | 1d 42 | 1e 43 | 22 44 | 23 45 | 24 46 | 21 47 | 8b 48 | 8b 49 | f8 50 | f8 51 | f8 52 | f8 53 | f8 54 | f8 55 | f8 56 | f8 57 | 2e 58 | 2f 59 | 2a 60 | 25 61 | 4d 62 | 4e 63 | 1f 64 | 1f 65 | 45 66 | 45 67 | 45 68 | 45 69 | 45 70 | 45 71 | 4b 72 | a0 73 | 41 74 | 41 75 | 41 76 | 40 77 | 40 78 | 40 79 | 40 80 | 40 81 | 89 82 | 89 83 | 89 84 | 89 85 | 89 86 | 89 87 | 7c 88 | 7d 89 | 43 90 | 43 91 | 43 92 | 40 93 | 40 94 | 40 95 | 40 96 | 40 97 | 14 98 | 65 99 | 65 100 | 65 101 | 65 102 | 65 103 | b7 104 | b0 105 | 31 106 | 64 107 | 64 108 | 64 109 | 64 110 | 64 111 | 50 112 | 53 113 | 09 114 | 54 115 | 54 116 | 54 117 | 54 118 | 54 119 | 8b 120 | 89 121 | 89 122 | 64 123 | 64 124 | 64 125 | 64 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237 | 36 238 | 36 239 | 36 240 | 36 241 | 30 242 | 62 243 | 62 244 | 62 245 | 62 246 | 62 247 | 8b 248 | 13 249 | 34 250 | 36 251 | 36 252 | 36 253 | 36 254 | 36 255 | 36 256 | 36 -------------------------------------------------------------------------------- /Verilog/roms/CodeROM.txt: -------------------------------------------------------------------------------- 1 | 42abc618b781c0 2 | 00000000000000 3 | 400103fe430000 4 | 4013fe1e80f40d 5 | c00103fc820000 6 | e0637e18638401 7 | 4000fff804800d 8 | 404bfff8f8802d 9 | 40397fff850193 10 | 60037e19978252 11 | 40010399028470 12 | 400103fe430000 13 | 400103ff856f50 14 | 40037fff5e139a 15 | 4401c61cf8c800 16 | 00000000000000 17 | 44a22ffe434020 18 | 400103ff857400 19 | 40017fff4e001a 20 | 40007998ce820a 21 | 460173fc820010 22 | c681721bef8610 23 | 40007ffe430001 24 | 400103ff856000 25 | 400b7fff3e000a 26 | 40310218968180 27 | 401b921e8f8000 28 | 00000000000000 29 | 00037e10028001 30 | e001721b0ec210 31 | 404b2e18108400 32 | 40016aa000c000 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