├── MDK-ARM
├── CRSF.c
├── Crsf.h
├── CRSF_ELRS
│ ├── startup_stm32f103xe.d
│ ├── crc.o
│ ├── crsf.o
│ ├── gpio.o
│ ├── main.o
│ ├── crc.crf
│ ├── crsf.crf
│ ├── gpio.crf
│ ├── main.crf
│ ├── CRSF_ELRS.axf
│ ├── stm32f1xx_hal.o
│ ├── stm32f1xx_hal.crf
│ ├── startup_stm32f103xe.o
│ ├── stm32f1xx_hal_dma.crf
│ ├── CRSF_ELRS.build_log.htm
│ ├── stm32f1xx_hal_cortex.crf
│ ├── stm32f1xx_hal_cortex.o
│ ├── crc.d
│ ├── CRSF_ELRS.sct
│ ├── CRSF_ELRS.lnp
│ ├── gpio.d
│ ├── stm32f1xx_hal.d
│ ├── stm32f1xx_hal_dma.d
│ ├── crsf.d
│ ├── stm32f1xx_hal_cortex.d
│ └── main.d
├── CRSF_PROTOCOL.h
├── CRC.h
├── RTE
│ └── _CRSF_ELRS
│ │ └── RTE_Components.h
├── CRC.c
└── DebugConfig
│ └── CRSF_ELRS_STM32F103ZE_1.0.0.dbgconf
├── Core
├── Inc
│ ├── usart.h
│ ├── gpio.h
│ ├── stm32f1xx_it.h
│ └── main.h
└── Src
│ ├── usart.c
│ ├── gpio.c
│ ├── stm32f1xx_hal_msp.c
│ ├── main.c
│ ├── stm32f1xx_it.c
│ └── system_stm32f1xx.c
├── .gitignore
├── Drivers
├── CMSIS
│ ├── Include
│ │ ├── cmsis_version.h
│ │ ├── tz_context.h
│ │ ├── cmsis_compiler.h
│ │ ├── mpu_armv8.h
│ │ └── mpu_armv7.h
│ └── Device
│ │ └── ST
│ │ └── STM32F1xx
│ │ └── Include
│ │ ├── system_stm32f1xx.h
│ │ └── stm32f1xx.h
└── STM32F1xx_HAL_Driver
│ ├── Src
│ └── stm32f1xx_hal_gpio_ex.c
│ └── Inc
│ ├── stm32f1xx_hal_def.h
│ ├── stm32f1xx_hal_flash.h
│ ├── stm32f1xx_hal_tim_ex.h
│ ├── stm32f1xx_hal.h
│ ├── stm32f1xx_hal_gpio.h
│ ├── stm32f1xx_hal_exti.h
│ ├── stm32f1xx_hal_pwr.h
│ └── stm32f1xx_hal_dma_ex.h
├── README.md
└── CRSF_ELRS.ioc
/MDK-ARM/CRSF.c:
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/MDK-ARM/Crsf.h:
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/Core/Inc/usart.h:
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/Core/Src/usart.c:
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/MDK-ARM/CRSF_ELRS/startup_stm32f103xe.d:
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1 | crsf_elrs\startup_stm32f103xe.o: startup_stm32f103xe.s
2 |
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/MDK-ARM/CRSF_ELRS/crc.o:
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/MDK-ARM/CRSF_ELRS/crsf.o:
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/MDK-ARM/CRSF_ELRS/gpio.o:
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/MDK-ARM/CRSF_ELRS/main.o:
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/MDK-ARM/CRSF_PROTOCOL.h:
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/MDK-ARM/CRSF_ELRS/crc.crf:
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/MDK-ARM/CRSF_ELRS/crsf.crf:
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/MDK-ARM/CRSF_ELRS/gpio.crf:
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/MDK-ARM/CRSF_ELRS/main.crf:
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/MDK-ARM/CRSF_ELRS/CRSF_ELRS.axf:
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/MDK-ARM/CRSF_ELRS/stm32f1xx_hal.o:
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/MDK-ARM/CRSF_ELRS/stm32f1xx_hal.crf:
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/MDK-ARM/CRSF_ELRS/startup_stm32f103xe.o:
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/MDK-ARM/CRSF_ELRS/stm32f1xx_hal_dma.crf:
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/MDK-ARM/CRSF_ELRS/CRSF_ELRS.build_log.htm:
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/MDK-ARM/CRSF_ELRS/stm32f1xx_hal_cortex.crf:
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/MDK-ARM/CRSF_ELRS/stm32f1xx_hal_cortex.o:
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/MDK-ARM/CRSF_ELRS/crc.d:
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1 | crsf_elrs\crc.o: CRC.c
2 | crsf_elrs\crc.o: CRC.h
3 | crsf_elrs\crc.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdint.h
4 |
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/MDK-ARM/CRC.h:
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1 | #ifndef _CRC_H__
2 | #define _CRC_H__
3 |
4 | #include "stdint.h"
5 |
6 | void Crc_init(uint8_t poly);
7 | uint8_t Calc(uint8_t *data, uint8_t len);
8 |
9 | #endif
10 |
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/MDK-ARM/RTE/_CRSF_ELRS/RTE_Components.h:
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1 |
2 | /*
3 | * Auto generated Run-Time-Environment Component Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'CRSF_ELRS'
7 | * Target: 'CRSF_ELRS'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32f10x.h"
18 |
19 |
20 | #endif /* RTE_COMPONENTS_H */
21 |
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/MDK-ARM/CRSF_ELRS/CRSF_ELRS.sct:
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1 | ; *************************************************************
2 | ; *** Scatter-Loading Description File generated by uVision ***
3 | ; *************************************************************
4 |
5 | LR_IROM1 0x08000000 0x00080000 { ; load region size_region
6 | ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
7 | *.o (RESET, +First)
8 | *(InRoot$$Sections)
9 | .ANY (+RO)
10 | }
11 | RW_IRAM1 0x20000000 0x00010000 { ; RW data
12 | .ANY (+RW +ZI)
13 | }
14 | }
15 |
16 |
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/MDK-ARM/CRC.c:
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1 | #include "CRC.h"
2 |
3 |
4 | uint8_t _lut[256];
5 |
6 |
7 | void Crc_init(uint8_t poly)
8 | {
9 | for (int idx=0; idx<256; ++idx)
10 | {
11 | uint8_t crc = idx;
12 | for (int shift=0; shift<8; ++shift)
13 | {
14 | crc = (crc << 1) ^ ((crc & 0x80) ? poly : 0);
15 | }
16 | _lut[idx] = crc & 0xff;
17 | }
18 | }
19 |
20 | uint8_t Calc(uint8_t *data, uint8_t len)
21 | {
22 | uint8_t crc = 0;
23 | while (len--)
24 | {
25 | crc = _lut[crc ^ *data++];
26 | }
27 | return crc;
28 | }
29 |
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/.gitignore:
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1 | # Prerequisites
2 | *.d
3 |
4 | # Object files
5 | *.o
6 | *.ko
7 | *.obj
8 | *.elf
9 |
10 | # Linker output
11 | *.ilk
12 | *.map
13 | *.exp
14 |
15 | # Precompiled Headers
16 | *.gch
17 | *.pch
18 |
19 | # Libraries
20 | *.lib
21 | *.a
22 | *.la
23 | *.lo
24 |
25 | # Shared objects (inc. Windows DLLs)
26 | *.dll
27 | *.so
28 | *.so.*
29 | *.dylib
30 |
31 | # Executables
32 | *.exe
33 | *.out
34 | *.app
35 | *.i*86
36 | *.x86_64
37 | *.hex
38 |
39 | # Debug files
40 | *.dSYM/
41 | *.su
42 | *.idb
43 | *.pdb
44 |
45 | # Kernel Module Compile Results
46 | *.mod*
47 | *.cmd
48 | .tmp_versions/
49 | modules.order
50 | Module.symvers
51 | Mkfile.old
52 | dkms.conf
53 |
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/MDK-ARM/CRSF_ELRS/CRSF_ELRS.lnp:
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1 | --cpu Cortex-M3
2 | "crsf_elrs\startup_stm32f103xe.o"
3 | "crsf_elrs\main.o"
4 | "crsf_elrs\gpio.o"
5 | "crsf_elrs\usart.o"
6 | "crsf_elrs\stm32f1xx_it.o"
7 | "crsf_elrs\stm32f1xx_hal_msp.o"
8 | "crsf_elrs\stm32f1xx_hal_gpio_ex.o"
9 | "crsf_elrs\stm32f1xx_hal_tim.o"
10 | "crsf_elrs\stm32f1xx_hal_tim_ex.o"
11 | "crsf_elrs\stm32f1xx_hal_uart.o"
12 | "crsf_elrs\stm32f1xx_hal.o"
13 | "crsf_elrs\stm32f1xx_hal_rcc.o"
14 | "crsf_elrs\stm32f1xx_hal_rcc_ex.o"
15 | "crsf_elrs\stm32f1xx_hal_gpio.o"
16 | "crsf_elrs\stm32f1xx_hal_dma.o"
17 | "crsf_elrs\stm32f1xx_hal_cortex.o"
18 | "crsf_elrs\stm32f1xx_hal_pwr.o"
19 | "crsf_elrs\stm32f1xx_hal_flash.o"
20 | "crsf_elrs\stm32f1xx_hal_flash_ex.o"
21 | "crsf_elrs\stm32f1xx_hal_exti.o"
22 | "crsf_elrs\system_stm32f1xx.o"
23 | "crsf_elrs\crsf.o"
24 | "crsf_elrs\crc.o"
25 | --library_type=microlib --strict --scatter "CRSF_ELRS\CRSF_ELRS.sct"
26 | --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
27 | --info sizes --info totals --info unused --info veneers
28 | --list "CRSF_ELRS.map" -o CRSF_ELRS\CRSF_ELRS.axf
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/Core/Inc/gpio.h:
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1 | /**
2 | ******************************************************************************
3 | * @file gpio.h
4 | * @brief This file contains all the function prototypes for
5 | * the gpio.c file
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2023 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __GPIO_H__
21 | #define __GPIO_H__
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "main.h"
29 |
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* USER CODE BEGIN Private defines */
35 |
36 | /* USER CODE END Private defines */
37 |
38 | void MX_GPIO_Init(void);
39 |
40 | /* USER CODE BEGIN Prototypes */
41 |
42 | /* USER CODE END Prototypes */
43 |
44 | #ifdef __cplusplus
45 | }
46 | #endif
47 | #endif /*__ GPIO_H__ */
48 |
49 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
50 |
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/Core/Src/gpio.c:
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1 | /**
2 | ******************************************************************************
3 | * @file gpio.c
4 | * @brief This file provides code for the configuration
5 | * of all used GPIO pins.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2023 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "gpio.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | /*----------------------------------------------------------------------------*/
28 | /* Configure GPIO */
29 | /*----------------------------------------------------------------------------*/
30 | /* USER CODE BEGIN 1 */
31 |
32 | /* USER CODE END 1 */
33 |
34 | /** Configure pins as
35 | * Analog
36 | * Input
37 | * Output
38 | * EVENT_OUT
39 | * EXTI
40 | */
41 | void MX_GPIO_Init(void)
42 | {
43 |
44 | /* GPIO Ports Clock Enable */
45 | __HAL_RCC_GPIOA_CLK_ENABLE();
46 |
47 | }
48 |
49 | /* USER CODE BEGIN 2 */
50 |
51 | /* USER CODE END 2 */
52 |
53 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
54 |
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/Drivers/CMSIS/Include/cmsis_version.h:
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1 | /**************************************************************************//**
2 | * @file cmsis_version.h
3 | * @brief CMSIS Core(M) Version definitions
4 | * @version V5.0.2
5 | * @date 19. April 2017
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef __CMSIS_VERSION_H
32 | #define __CMSIS_VERSION_H
33 |
34 | /* CMSIS Version definitions */
35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
39 | #endif
40 |
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/MDK-ARM/CRSF_ELRS/gpio.d:
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1 | crsf_elrs\gpio.o: ../Core/Src/gpio.c
2 | crsf_elrs\gpio.o: ../Core/Inc/gpio.h
3 | crsf_elrs\gpio.o: ../Core/Inc/main.h
4 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
5 | crsf_elrs\gpio.o: ../Core/Inc/stm32f1xx_hal_conf.h
6 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
7 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
8 | crsf_elrs\gpio.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
9 | crsf_elrs\gpio.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
10 | crsf_elrs\gpio.o: ../Drivers/CMSIS/Include/core_cm3.h
11 | crsf_elrs\gpio.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdint.h
12 | crsf_elrs\gpio.o: ../Drivers/CMSIS/Include/cmsis_version.h
13 | crsf_elrs\gpio.o: ../Drivers/CMSIS/Include/cmsis_compiler.h
14 | crsf_elrs\gpio.o: ../Drivers/CMSIS/Include/cmsis_armcc.h
15 | crsf_elrs\gpio.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
16 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
17 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
18 | crsf_elrs\gpio.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stddef.h
19 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
20 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
21 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
22 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
23 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
24 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
25 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
26 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
27 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
28 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
29 | crsf_elrs\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
30 |
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/README.md:
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1 | # STM32_ToCrsf-Elrs
2 | STM32HAL库解析CRSF(ELRS)协议
3 |
4 | **串口配置**
5 |
6 | 波特率|数据位|校验位|停止位
7 | ------|------|------|------
8 | 420000|8|无|1
9 |
10 | **CRSF协议帧结构**
11 | 1. **设备地址**（Device Address）:**1字节**
12 | 2. **帧长度**（Length）：**1字节**
13 | 3. **帧类型**（Type）:**1字节（GPS、RC_channels、LINK_STATISTICS）**
14 | 4. **负载（数据）**（Payload）：**根据类型决定（例如RC_channels为22字节）**
15 | 5. **CRC校验**（CRC）：**1字节**
16 |
17 | **设备地址**
18 | ```
19 | typedef enum
20 | {
21 | CRSF_ADDRESS_BROADCAST = 0x00,
22 | CRSF_ADDRESS_USB = 0x10,
23 | CRSF_ADDRESS_TBS_CORE_PNP_PRO = 0x80,
24 | CRSF_ADDRESS_RESERVED1 = 0x8A,
25 | CRSF_ADDRESS_CURRENT_SENSOR = 0xC0,
26 | CRSF_ADDRESS_GPS = 0xC2,
27 | CRSF_ADDRESS_TBS_BLACKBOX = 0xC4,
28 | CRSF_ADDRESS_FLIGHT_CONTROLLER = 0xC8,
29 | CRSF_ADDRESS_RESERVED2 = 0xCA,
30 | CRSF_ADDRESS_RACE_TAG = 0xCC,
31 | CRSF_ADDRESS_RADIO_TRANSMITTER = 0xEA,
32 | CRSF_ADDRESS_CRSF_RECEIVER = 0xEC,
33 | CRSF_ADDRESS_CRSF_TRANSMITTER = 0xEE,
34 | } crsf_addr_e;
35 | ```
36 | **帧类型大小**
37 | ```
38 | typedef enum
39 | {
40 | CRSF_FRAMETYPE_GPS = 0x02,
41 | CRSF_FRAMETYPE_BATTERY_SENSOR = 0x08,
42 | CRSF_FRAMETYPE_LINK_STATISTICS = 0x14,
43 | CRSF_FRAMETYPE_OPENTX_SYNC = 0x10,
44 | CRSF_FRAMETYPE_RADIO_ID = 0x3A,
45 | CRSF_FRAMETYPE_RC_CHANNELS_PACKED = 0x16,
46 | CRSF_FRAMETYPE_ATTITUDE = 0x1E,
47 | CRSF_FRAMETYPE_FLIGHT_MODE = 0x21,
48 | // Extended Header Frames, range: 0x28 to 0x96
49 | CRSF_FRAMETYPE_DEVICE_PING = 0x28,
50 | CRSF_FRAMETYPE_DEVICE_INFO = 0x29,
51 | CRSF_FRAMETYPE_PARAMETER_SETTINGS_ENTRY = 0x2B,
52 | CRSF_FRAMETYPE_PARAMETER_READ = 0x2C,
53 | CRSF_FRAMETYPE_PARAMETER_WRITE = 0x2D,
54 | CRSF_FRAMETYPE_COMMAND = 0x32,
55 | // MSP commands
56 | CRSF_FRAMETYPE_MSP_REQ = 0x7A, // response request using msp sequence as command
57 | CRSF_FRAMETYPE_MSP_RESP = 0x7B, // reply with 58 byte chunked binary
58 | CRSF_FRAMETYPE_MSP_WRITE = 0x7C, // write with 8 byte chunked binary (OpenTX outbound telemetry buffer limit)
59 | } crsf_frame_type_e;
60 | ```
61 |
62 | [项目参考自：https://github.com/CapnBry/CRServoF](https://github.com/CapnBry/CRServoF)
63 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f1xx.h
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2017-2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file
13 | * in the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 |
19 | /** @addtogroup CMSIS
20 | * @{
21 | */
22 |
23 | /** @addtogroup stm32f10x_system
24 | * @{
25 | */
26 |
27 | /**
28 | * @brief Define to prevent recursive inclusion
29 | */
30 | #ifndef __SYSTEM_STM32F10X_H
31 | #define __SYSTEM_STM32F10X_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /** @addtogroup STM32F10x_System_Includes
38 | * @{
39 | */
40 |
41 | /**
42 | * @}
43 | */
44 |
45 |
46 | /** @addtogroup STM32F10x_System_Exported_types
47 | * @{
48 | */
49 |
50 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
51 | extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
52 | extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @addtogroup STM32F10x_System_Exported_Constants
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @addtogroup STM32F10x_System_Exported_Macros
67 | * @{
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @addtogroup STM32F10x_System_Exported_Functions
75 | * @{
76 | */
77 |
78 | extern void SystemInit(void);
79 | extern void SystemCoreClockUpdate(void);
80 | /**
81 | * @}
82 | */
83 |
84 | #ifdef __cplusplus
85 | }
86 | #endif
87 |
88 | #endif /*__SYSTEM_STM32F10X_H */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
--------------------------------------------------------------------------------
/MDK-ARM/CRSF_ELRS/stm32f1xx_hal.d:
--------------------------------------------------------------------------------
1 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
2 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
3 | crsf_elrs\stm32f1xx_hal.o: ../Core/Inc/stm32f1xx_hal_conf.h
4 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
5 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
6 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
7 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
8 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/CMSIS/Include/core_cm3.h
9 | crsf_elrs\stm32f1xx_hal.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdint.h
10 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/CMSIS/Include/cmsis_version.h
11 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/CMSIS/Include/cmsis_compiler.h
12 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/CMSIS/Include/cmsis_armcc.h
13 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
14 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
15 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
16 | crsf_elrs\stm32f1xx_hal.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stddef.h
17 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
18 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
19 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
20 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
21 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
22 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
23 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
24 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
25 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
26 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
27 | crsf_elrs\stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
28 |
--------------------------------------------------------------------------------
/MDK-ARM/CRSF_ELRS/stm32f1xx_hal_dma.d:
--------------------------------------------------------------------------------
1 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
2 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
3 | crsf_elrs\stm32f1xx_hal_dma.o: ../Core/Inc/stm32f1xx_hal_conf.h
4 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
5 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
6 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
7 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
8 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/CMSIS/Include/core_cm3.h
9 | crsf_elrs\stm32f1xx_hal_dma.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdint.h
10 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/CMSIS/Include/cmsis_version.h
11 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/CMSIS/Include/cmsis_compiler.h
12 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/CMSIS/Include/cmsis_armcc.h
13 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
14 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
15 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
16 | crsf_elrs\stm32f1xx_hal_dma.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stddef.h
17 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
18 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
19 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
20 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
21 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
22 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
23 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
24 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
25 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
26 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
27 | crsf_elrs\stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
28 |
--------------------------------------------------------------------------------
/MDK-ARM/CRSF_ELRS/crsf.d:
--------------------------------------------------------------------------------
1 | crsf_elrs\crsf.o: CRSF.c
2 | crsf_elrs\crsf.o: Crsf.h
3 | crsf_elrs\crsf.o: ../Core/Inc/usart.h
4 | crsf_elrs\crsf.o: ../Core/Inc/main.h
5 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
6 | crsf_elrs\crsf.o: ../Core/Inc/stm32f1xx_hal_conf.h
7 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
8 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
9 | crsf_elrs\crsf.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
10 | crsf_elrs\crsf.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
11 | crsf_elrs\crsf.o: ../Drivers/CMSIS/Include/core_cm3.h
12 | crsf_elrs\crsf.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdint.h
13 | crsf_elrs\crsf.o: ../Drivers/CMSIS/Include/cmsis_version.h
14 | crsf_elrs\crsf.o: ../Drivers/CMSIS/Include/cmsis_compiler.h
15 | crsf_elrs\crsf.o: ../Drivers/CMSIS/Include/cmsis_armcc.h
16 | crsf_elrs\crsf.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
17 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
18 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
19 | crsf_elrs\crsf.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stddef.h
20 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
21 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
22 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
23 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
24 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
25 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
26 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
27 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
28 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
29 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
30 | crsf_elrs\crsf.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
31 | crsf_elrs\crsf.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdio.h
32 | crsf_elrs\crsf.o: ..\MDK-ARM\Crsf.h
33 | crsf_elrs\crsf.o: CRC.h
34 | crsf_elrs\crsf.o: CRSF_PROTOCOL.h
35 | crsf_elrs\crsf.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdbool.h
36 | crsf_elrs\crsf.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\string.h
37 |
--------------------------------------------------------------------------------
/Core/Inc/stm32f1xx_it.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f1xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2023 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F1xx_IT_H
23 | #define __STM32F1xx_IT_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Private includes ----------------------------------------------------------*/
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 | /* USER CODE BEGIN ET */
36 |
37 | /* USER CODE END ET */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 | /* USER CODE BEGIN EC */
41 |
42 | /* USER CODE END EC */
43 |
44 | /* Exported macro ------------------------------------------------------------*/
45 | /* USER CODE BEGIN EM */
46 |
47 | /* USER CODE END EM */
48 |
49 | /* Exported functions prototypes ---------------------------------------------*/
50 | void NMI_Handler(void);
51 | void HardFault_Handler(void);
52 | void MemManage_Handler(void);
53 | void BusFault_Handler(void);
54 | void UsageFault_Handler(void);
55 | void SVC_Handler(void);
56 | void DebugMon_Handler(void);
57 | void PendSV_Handler(void);
58 | void SysTick_Handler(void);
59 | void USART1_IRQHandler(void);
60 | void USART2_IRQHandler(void);
61 | /* USER CODE BEGIN EFP */
62 |
63 | /* USER CODE END EFP */
64 |
65 | #ifdef __cplusplus
66 | }
67 | #endif
68 |
69 | #endif /* __STM32F1xx_IT_H */
70 |
71 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
72 |
--------------------------------------------------------------------------------
/Core/Inc/main.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2023 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MAIN_H
24 | #define __MAIN_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f1xx_hal.h"
32 |
33 | /* Private includes ----------------------------------------------------------*/
34 | /* USER CODE BEGIN Includes */
35 |
36 | /* USER CODE END Includes */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* USER CODE BEGIN ET */
40 |
41 | /* USER CODE END ET */
42 |
43 | /* Exported constants --------------------------------------------------------*/
44 | /* USER CODE BEGIN EC */
45 |
46 | /* USER CODE END EC */
47 |
48 | /* Exported macro ------------------------------------------------------------*/
49 | /* USER CODE BEGIN EM */
50 |
51 | /* USER CODE END EM */
52 |
53 | /* Exported functions prototypes ---------------------------------------------*/
54 | void Error_Handler(void);
55 |
56 | /* USER CODE BEGIN EFP */
57 |
58 | /* USER CODE END EFP */
59 |
60 | /* Private defines -----------------------------------------------------------*/
61 | /* USER CODE BEGIN Private defines */
62 |
63 | /* USER CODE END Private defines */
64 |
65 | #ifdef __cplusplus
66 | }
67 | #endif
68 |
69 | #endif /* __MAIN_H */
70 |
71 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
72 |
--------------------------------------------------------------------------------
/MDK-ARM/CRSF_ELRS/stm32f1xx_hal_cortex.d:
--------------------------------------------------------------------------------
1 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
2 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
3 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Core/Inc/stm32f1xx_hal_conf.h
4 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
5 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
6 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
7 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
8 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/CMSIS/Include/core_cm3.h
9 | crsf_elrs\stm32f1xx_hal_cortex.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdint.h
10 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/CMSIS/Include/cmsis_version.h
11 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/CMSIS/Include/cmsis_compiler.h
12 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/CMSIS/Include/cmsis_armcc.h
13 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
14 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
15 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
16 | crsf_elrs\stm32f1xx_hal_cortex.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stddef.h
17 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
18 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
19 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
20 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
21 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
22 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
23 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
24 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
25 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
26 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
27 | crsf_elrs\stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
28 |
--------------------------------------------------------------------------------
/MDK-ARM/CRSF_ELRS/main.d:
--------------------------------------------------------------------------------
1 | crsf_elrs\main.o: ../Core/Src/main.c
2 | crsf_elrs\main.o: ../Core/Inc/main.h
3 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
4 | crsf_elrs\main.o: ../Core/Inc/stm32f1xx_hal_conf.h
5 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
6 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
7 | crsf_elrs\main.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
8 | crsf_elrs\main.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
9 | crsf_elrs\main.o: ../Drivers/CMSIS/Include/core_cm3.h
10 | crsf_elrs\main.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdint.h
11 | crsf_elrs\main.o: ../Drivers/CMSIS/Include/cmsis_version.h
12 | crsf_elrs\main.o: ../Drivers/CMSIS/Include/cmsis_compiler.h
13 | crsf_elrs\main.o: ../Drivers/CMSIS/Include/cmsis_armcc.h
14 | crsf_elrs\main.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
15 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
16 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
17 | crsf_elrs\main.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stddef.h
18 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
19 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
20 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
21 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
22 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
23 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
24 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
25 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
26 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
27 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
28 | crsf_elrs\main.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
29 | crsf_elrs\main.o: ../Core/Inc/usart.h
30 | crsf_elrs\main.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdio.h
31 | crsf_elrs\main.o: ..\MDK-ARM\Crsf.h
32 | crsf_elrs\main.o: ../Core/Inc/usart.h
33 | crsf_elrs\main.o: ..\MDK-ARM\CRC.h
34 | crsf_elrs\main.o: ..\MDK-ARM\CRSF_PROTOCOL.h
35 | crsf_elrs\main.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\stdbool.h
36 | crsf_elrs\main.o: D:\Keil_v5_MDK\ARM\ARMCC\Bin\..\include\string.h
37 | crsf_elrs\main.o: ../Core/Inc/gpio.h
38 |
--------------------------------------------------------------------------------
/MDK-ARM/DebugConfig/CRSF_ELRS_STM32F103ZE_1.0.0.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32F101_102_103_105_107.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
4 | // STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
5 |
6 | // <<< Use Configuration Wizard in Context Menu >>>
7 |
8 | // Debug MCU configuration register (DBGMCU_CR)
9 | // Reserved bits must be kept at reset value
10 | // DBG_TIM11_STOP TIM11 counter stopped when core is halted
11 | // DBG_TIM10_STOP TIM10 counter stopped when core is halted
12 | // DBG_TIM9_STOP TIM9 counter stopped when core is halted
13 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted
14 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted
15 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted
16 | // DBG_CAN2_STOP Debug CAN2 stopped when core is halted
17 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
18 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
19 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
20 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted
21 | // DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted
22 | // DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted
23 | // DBG_CAN1_STOP Debug CAN1 stopped when Core is halted
24 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
25 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
26 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
27 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
28 | // DBG_WWDG_STOP Debug window watchdog stopped when core is halted
29 | // DBG_IWDG_STOP Debug independent watchdog stopped when core is halted
30 | // DBG_STANDBY Debug standby mode
31 | // DBG_STOP Debug stop mode
32 | // DBG_SLEEP Debug sleep mode
33 | //
34 | DbgMCU_CR = 0x00000007;
35 |
36 | // <<< end of configuration section >>>
37 |
--------------------------------------------------------------------------------
/Core/Src/stm32f1xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f1xx_hal_msp.c
5 | * @brief This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2023 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "main.h"
24 | /* USER CODE BEGIN Includes */
25 |
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN Define */
35 |
36 | /* USER CODE END Define */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN Macro */
40 |
41 | /* USER CODE END Macro */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* External functions --------------------------------------------------------*/
54 | /* USER CODE BEGIN ExternalFunctions */
55 |
56 | /* USER CODE END ExternalFunctions */
57 |
58 | /* USER CODE BEGIN 0 */
59 |
60 | /* USER CODE END 0 */
61 | /**
62 | * Initializes the Global MSP.
63 | */
64 | void HAL_MspInit(void)
65 | {
66 | /* USER CODE BEGIN MspInit 0 */
67 |
68 | /* USER CODE END MspInit 0 */
69 |
70 | __HAL_RCC_AFIO_CLK_ENABLE();
71 | __HAL_RCC_PWR_CLK_ENABLE();
72 |
73 | /* System interrupt init*/
74 |
75 | /** DISABLE: JTAG-DP Disabled and SW-DP Disabled
76 | */
77 | __HAL_AFIO_REMAP_SWJ_DISABLE();
78 |
79 | /* USER CODE BEGIN MspInit 1 */
80 |
81 | /* USER CODE END MspInit 1 */
82 | }
83 |
84 | /* USER CODE BEGIN 1 */
85 |
86 | /* USER CODE END 1 */
87 |
88 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
89 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/tz_context.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file tz_context.h
3 | * @brief Context Management for Armv8-M TrustZone
4 | * @version V1.0.1
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef TZ_CONTEXT_H
32 | #define TZ_CONTEXT_H
33 |
34 | #include
35 |
36 | #ifndef TZ_MODULEID_T
37 | #define TZ_MODULEID_T
38 | /// \details Data type that identifies secure software modules called by a process.
39 | typedef uint32_t TZ_ModuleId_t;
40 | #endif
41 |
42 | /// \details TZ Memory ID identifies an allocated memory slot.
43 | typedef uint32_t TZ_MemoryId_t;
44 |
45 | /// Initialize secure context memory system
46 | /// \return execution status (1: success, 0: error)
47 | uint32_t TZ_InitContextSystem_S (void);
48 |
49 | /// Allocate context memory for calling secure software modules in TrustZone
50 | /// \param[in] module identifies software modules called from non-secure mode
51 | /// \return value != 0 id TrustZone memory slot identifier
52 | /// \return value 0 no memory available or internal error
53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
54 |
55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
56 | /// \param[in] id TrustZone memory slot identifier
57 | /// \return execution status (1: success, 0: error)
58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
59 |
60 | /// Load secure context (called on RTOS thread context switch)
61 | /// \param[in] id TrustZone memory slot identifier
62 | /// \return execution status (1: success, 0: error)
63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
64 |
65 | /// Store secure context (called on RTOS thread context switch)
66 | /// \param[in] id TrustZone memory slot identifier
67 | /// \return execution status (1: success, 0: error)
68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
69 |
70 | #endif // TZ_CONTEXT_H
71 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_gpio_ex.c
4 | * @author MCD Application Team
5 | * @brief GPIO Extension HAL module driver.
6 | * This file provides firmware functions to manage the following
7 | * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
8 | * + Extended features functions
9 | *
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * Copyright (c) 2016 STMicroelectronics.
14 | * All rights reserved.
15 | *
16 | * This software is licensed under terms that can be found in the LICENSE file
17 | * in the root directory of this software component.
18 | * If no LICENSE file comes with this software, it is provided AS-IS.
19 | *
20 | ******************************************************************************
21 | @verbatim
22 | ==============================================================================
23 | ##### GPIO Peripheral extension features #####
24 | ==============================================================================
25 | [..] GPIO module on STM32F1 family, manage also the AFIO register:
26 | (+) Possibility to use the EVENTOUT Cortex feature
27 |
28 | ##### How to use this driver #####
29 | ==============================================================================
30 | [..] This driver provides functions to use EVENTOUT Cortex feature
31 | (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
32 | (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
33 | (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
34 |
35 | @endverbatim
36 | ******************************************************************************
37 | */
38 |
39 | /* Includes ------------------------------------------------------------------*/
40 | #include "stm32f1xx_hal.h"
41 |
42 | /** @addtogroup STM32F1xx_HAL_Driver
43 | * @{
44 | */
45 |
46 | /** @defgroup GPIOEx GPIOEx
47 | * @brief GPIO HAL module driver
48 | * @{
49 | */
50 |
51 | #ifdef HAL_GPIO_MODULE_ENABLED
52 |
53 | /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
54 | * @{
55 | */
56 |
57 | /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
58 | * @brief Extended features functions
59 | *
60 | @verbatim
61 | ==============================================================================
62 | ##### Extended features functions #####
63 | ==============================================================================
64 | [..] This section provides functions allowing to:
65 | (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
66 | (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
67 | (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
68 |
69 | @endverbatim
70 | * @{
71 | */
72 |
73 | /**
74 | * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
75 | * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
76 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
77 | * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
78 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
79 | * @retval None
80 | */
81 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
82 | {
83 | /* Verify the parameters */
84 | assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
85 | assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
86 |
87 | /* Apply the new configuration */
88 | MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));
89 | }
90 |
91 | /**
92 | * @brief Enables the Event Output.
93 | * @retval None
94 | */
95 | void HAL_GPIOEx_EnableEventout(void)
96 | {
97 | SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
98 | }
99 |
100 | /**
101 | * @brief Disables the Event Output.
102 | * @retval None
103 | */
104 | void HAL_GPIOEx_DisableEventout(void)
105 | {
106 | CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
107 | }
108 |
109 | /**
110 | * @}
111 | */
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | #endif /* HAL_GPIO_MODULE_ENABLED */
118 |
119 | /**
120 | * @}
121 | */
122 |
123 | /**
124 | * @}
125 | */
126 |
127 |
--------------------------------------------------------------------------------
/CRSF_ELRS.ioc:
--------------------------------------------------------------------------------
1 | #MicroXplorer Configuration settings - do not modify
2 | File.Version=6
3 | GPIO.groupedBy=
4 | KeepUserPlacement=false
5 | Mcu.Family=STM32F1
6 | Mcu.IP0=NVIC
7 | Mcu.IP1=RCC
8 | Mcu.IP2=SYS
9 | Mcu.IP3=USART1
10 | Mcu.IP4=USART2
11 | Mcu.IPNb=5
12 | Mcu.Name=STM32F103Z(C-D-E)Tx
13 | Mcu.Package=LQFP144
14 | Mcu.Pin0=OSC_IN
15 | Mcu.Pin1=OSC_OUT
16 | Mcu.Pin2=PA2
17 | Mcu.Pin3=PA3
18 | Mcu.Pin4=PA9
19 | Mcu.Pin5=PA10
20 | Mcu.Pin6=VP_SYS_VS_ND
21 | Mcu.Pin7=VP_SYS_VS_Systick
22 | Mcu.PinsNb=8
23 | Mcu.ThirdPartyNb=0
24 | Mcu.UserConstants=
25 | Mcu.UserName=STM32F103ZETx
26 | MxCube.Version=6.3.0
27 | MxDb.Version=DB.6.0.30
28 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
29 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
30 | NVIC.ForceEnableDMAVector=true
31 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
32 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
33 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
34 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
35 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
36 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
37 | NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true
38 | NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
39 | NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
40 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
41 | OSC_IN.Mode=HSE-External-Oscillator
42 | OSC_IN.Signal=RCC_OSC_IN
43 | OSC_OUT.Mode=HSE-External-Oscillator
44 | OSC_OUT.Signal=RCC_OSC_OUT
45 | PA10.Mode=Asynchronous
46 | PA10.Signal=USART1_RX
47 | PA2.Mode=Asynchronous
48 | PA2.Signal=USART2_TX
49 | PA3.Mode=Asynchronous
50 | PA3.Signal=USART2_RX
51 | PA9.Mode=Asynchronous
52 | PA9.Signal=USART1_TX
53 | PinOutPanel.RotationAngle=0
54 | ProjectManager.AskForMigrate=true
55 | ProjectManager.BackupPrevious=false
56 | ProjectManager.CompilerOptimize=6
57 | ProjectManager.ComputerToolchain=false
58 | ProjectManager.CoupleFile=true
59 | ProjectManager.CustomerFirmwarePackage=
60 | ProjectManager.DefaultFWLocation=true
61 | ProjectManager.DeletePrevious=true
62 | ProjectManager.DeviceId=STM32F103ZETx
63 | ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.5
64 | ProjectManager.FreePins=false
65 | ProjectManager.HalAssertFull=false
66 | ProjectManager.HeapSize=0x200
67 | ProjectManager.KeepUserCode=true
68 | ProjectManager.LastFirmware=true
69 | ProjectManager.LibraryCopy=1
70 | ProjectManager.MainLocation=Core/Src
71 | ProjectManager.NoMain=false
72 | ProjectManager.PreviousToolchain=
73 | ProjectManager.ProjectBuild=false
74 | ProjectManager.ProjectFileName=CRSF_ELRS.ioc
75 | ProjectManager.ProjectName=CRSF_ELRS
76 | ProjectManager.RegisterCallBack=
77 | ProjectManager.StackSize=0x400
78 | ProjectManager.TargetToolchain=MDK-ARM V5.32
79 | ProjectManager.ToolChainLocation=
80 | ProjectManager.UnderRoot=false
81 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true
82 | RCC.ADCFreqValue=36000000
83 | RCC.AHBFreq_Value=72000000
84 | RCC.APB1CLKDivider=RCC_HCLK_DIV2
85 | RCC.APB1Freq_Value=36000000
86 | RCC.APB1TimFreq_Value=72000000
87 | RCC.APB2Freq_Value=72000000
88 | RCC.APB2TimFreq_Value=72000000
89 | RCC.FCLKCortexFreq_Value=72000000
90 | RCC.FSMCFreq_Value=72000000
91 | RCC.FamilyName=M
92 | RCC.HCLKFreq_Value=72000000
93 | RCC.I2S2Freq_Value=72000000
94 | RCC.I2S3Freq_Value=72000000
95 | RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
96 | RCC.MCOFreq_Value=72000000
97 | RCC.PLLCLKFreq_Value=72000000
98 | RCC.PLLMCOFreq_Value=36000000
99 | RCC.PLLMUL=RCC_PLL_MUL9
100 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
101 | RCC.SDIOFreq_Value=72000000
102 | RCC.SDIOHCLKDiv2FreqValue=36000000
103 | RCC.SYSCLKFreq_VALUE=72000000
104 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
105 | RCC.TimSysFreq_Value=72000000
106 | RCC.USBFreq_Value=72000000
107 | RCC.VCOOutput2Freq_Value=8000000
108 | USART1.IPParameters=VirtualMode
109 | USART1.VirtualMode=VM_ASYNC
110 | USART2.BaudRate=420000
111 | USART2.IPParameters=VirtualMode,BaudRate
112 | USART2.VirtualMode=VM_ASYNC
113 | VP_SYS_VS_ND.Mode=No_Debug
114 | VP_SYS_VS_ND.Signal=SYS_VS_ND
115 | VP_SYS_VS_Systick.Mode=SysTick
116 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
117 | board=custom
118 |
--------------------------------------------------------------------------------
/Core/Src/main.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.c
5 | * @brief : Main program body
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2023 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "main.h"
22 | #include "usart.h"
23 | #include "gpio.h"
24 |
25 | /* Private includes ----------------------------------------------------------*/
26 | /* USER CODE BEGIN Includes */
27 |
28 | /* USER CODE END Includes */
29 |
30 | /* Private typedef -----------------------------------------------------------*/
31 | /* USER CODE BEGIN PTD */
32 |
33 | /* USER CODE END PTD */
34 |
35 | /* Private define ------------------------------------------------------------*/
36 | /* USER CODE BEGIN PD */
37 | /* USER CODE END PD */
38 |
39 | /* Private macro -------------------------------------------------------------*/
40 | /* USER CODE BEGIN PM */
41 |
42 | /* USER CODE END PM */
43 |
44 | /* Private variables ---------------------------------------------------------*/
45 | /* USER CODE BEGIN PV */
46 | //extern uint16_t CRSF_CH[17];
47 | extern int CrsfChannels[CRSF_NUM_CHANNELS];
48 | /* USER CODE END PV */
49 |
50 | /* Private function prototypes -----------------------------------------------*/
51 | void SystemClock_Config(void);
52 | /* USER CODE BEGIN PFP */
53 |
54 | /* USER CODE END PFP */
55 |
56 | /* Private user code ---------------------------------------------------------*/
57 | /* USER CODE BEGIN 0 */
58 |
59 | /* USER CODE END 0 */
60 |
61 | /**
62 | * @brief The application entry point.
63 | * @retval int
64 | */
65 | int main(void)
66 | {
67 | /* USER CODE BEGIN 1 */
68 | /* USER CODE END 1 */
69 |
70 | /* MCU Configuration--------------------------------------------------------*/
71 |
72 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
73 | HAL_Init();
74 |
75 | /* USER CODE BEGIN Init */
76 | Crc_init(0xD5);
77 | /* USER CODE END Init */
78 |
79 | /* Configure the system clock */
80 | SystemClock_Config();
81 |
82 | /* USER CODE BEGIN SysInit */
83 |
84 | /* USER CODE END SysInit */
85 |
86 | /* Initialize all configured peripherals */
87 | MX_GPIO_Init();
88 | MX_USART1_UART_Init();
89 | MX_USART2_UART_Init();
90 | /* USER CODE BEGIN 2 */
91 |
92 | HAL_UART_Receive_IT(&huart2, (uint8_t *)RxBuffer,LENGTH);
93 | /* USER CODE END 2 */
94 |
95 | /* Infinite loop */
96 | /* USER CODE BEGIN WHILE */
97 | while (1)
98 | {
99 | /* USER CODE END WHILE */
100 |
101 | // /* USER CODE BEGIN 3 */
102 |
103 | printf("ch1:%d\r\n",CrsfChannels[0]);
104 | printf("ch2:%d\r\n",CrsfChannels[1]);
105 | printf("ch3:%d\r\n",CrsfChannels[2]);
106 | printf("ch4:%d\r\n",CrsfChannels[3]);
107 | printf("ch5:%d\r\n",CrsfChannels[4]);
108 | printf("ch6:%d\r\n",CrsfChannels[5]);
109 | printf("ch7:%d\r\n",CrsfChannels[6]);
110 | printf("ch8:%d\r\n",CrsfChannels[7]);
111 | printf("ch9:%d\r\n",CrsfChannels[8]);
112 | printf("ch10:%d\r\n",CrsfChannels[9]);
113 | printf("ch11:%d\r\n",CrsfChannels[10]);
114 | printf("ch12:%d\r\n",CrsfChannels[11]);
115 | HAL_Delay(100);
116 |
117 | }
118 | /* USER CODE END 3 */
119 | }
120 |
121 | /**
122 | * @brief System Clock Configuration
123 | * @retval None
124 | */
125 | void SystemClock_Config(void)
126 | {
127 | RCC_OscInitTypeDef RCC_OscInitStruct = {0};
128 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
129 |
130 | /** Initializes the RCC Oscillators according to the specified parameters
131 | * in the RCC_OscInitTypeDef structure.
132 | */
133 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
134 | RCC_OscInitStruct.HSEState = RCC_HSE_ON;
135 | RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
136 | RCC_OscInitStruct.HSIState = RCC_HSI_ON;
137 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
138 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
139 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
140 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
141 | {
142 | Error_Handler();
143 | }
144 | /** Initializes the CPU, AHB and APB buses clocks
145 | */
146 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
147 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
148 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
149 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
150 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
151 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
152 |
153 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
154 | {
155 | Error_Handler();
156 | }
157 | }
158 |
159 | /* USER CODE BEGIN 4 */
160 |
161 | /* USER CODE END 4 */
162 |
163 | /**
164 | * @brief This function is executed in case of error occurrence.
165 | * @retval None
166 | */
167 | void Error_Handler(void)
168 | {
169 | /* USER CODE BEGIN Error_Handler_Debug */
170 | /* User can add his own implementation to report the HAL error return state */
171 | __disable_irq();
172 | while (1)
173 | {
174 | }
175 | /* USER CODE END Error_Handler_Debug */
176 | }
177 |
178 | #ifdef USE_FULL_ASSERT
179 | /**
180 | * @brief Reports the name of the source file and the source line number
181 | * where the assert_param error has occurred.
182 | * @param file: pointer to the source file name
183 | * @param line: assert_param error line source number
184 | * @retval None
185 | */
186 | void assert_failed(uint8_t *file, uint32_t line)
187 | {
188 | /* USER CODE BEGIN 6 */
189 | /* User can add his own implementation to report the file name and line number,
190 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
191 | /* USER CODE END 6 */
192 | }
193 | #endif /* USE_FULL_ASSERT */
194 |
195 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
196 |
--------------------------------------------------------------------------------
/Core/Src/stm32f1xx_it.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f1xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2023 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | #include "stm32f1xx_it.h"
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | #include "usart.h"
27 | /* USER CODE END Includes */
28 |
29 | /* Private typedef -----------------------------------------------------------*/
30 | /* USER CODE BEGIN TD */
31 |
32 | /* USER CODE END TD */
33 |
34 | /* Private define ------------------------------------------------------------*/
35 | /* USER CODE BEGIN PD */
36 |
37 | /* USER CODE END PD */
38 |
39 | /* Private macro -------------------------------------------------------------*/
40 | /* USER CODE BEGIN PM */
41 |
42 | /* USER CODE END PM */
43 |
44 | /* Private variables ---------------------------------------------------------*/
45 | /* USER CODE BEGIN PV */
46 |
47 | /* USER CODE END PV */
48 |
49 | /* Private function prototypes -----------------------------------------------*/
50 | /* USER CODE BEGIN PFP */
51 |
52 | /* USER CODE END PFP */
53 |
54 | /* Private user code ---------------------------------------------------------*/
55 | /* USER CODE BEGIN 0 */
56 |
57 | /* USER CODE END 0 */
58 |
59 | /* External variables --------------------------------------------------------*/
60 | extern UART_HandleTypeDef huart1;
61 | extern UART_HandleTypeDef huart2;
62 | /* USER CODE BEGIN EV */
63 |
64 | /* USER CODE END EV */
65 |
66 | /******************************************************************************/
67 | /* Cortex-M3 Processor Interruption and Exception Handlers */
68 | /******************************************************************************/
69 | /**
70 | * @brief This function handles Non maskable interrupt.
71 | */
72 | void NMI_Handler(void)
73 | {
74 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
75 |
76 | /* USER CODE END NonMaskableInt_IRQn 0 */
77 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
78 | while (1)
79 | {
80 | }
81 | /* USER CODE END NonMaskableInt_IRQn 1 */
82 | }
83 |
84 | /**
85 | * @brief This function handles Hard fault interrupt.
86 | */
87 | void HardFault_Handler(void)
88 | {
89 | /* USER CODE BEGIN HardFault_IRQn 0 */
90 |
91 | /* USER CODE END HardFault_IRQn 0 */
92 | while (1)
93 | {
94 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
95 | /* USER CODE END W1_HardFault_IRQn 0 */
96 | }
97 | }
98 |
99 | /**
100 | * @brief This function handles Memory management fault.
101 | */
102 | void MemManage_Handler(void)
103 | {
104 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */
105 |
106 | /* USER CODE END MemoryManagement_IRQn 0 */
107 | while (1)
108 | {
109 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
110 | /* USER CODE END W1_MemoryManagement_IRQn 0 */
111 | }
112 | }
113 |
114 | /**
115 | * @brief This function handles Prefetch fault, memory access fault.
116 | */
117 | void BusFault_Handler(void)
118 | {
119 | /* USER CODE BEGIN BusFault_IRQn 0 */
120 |
121 | /* USER CODE END BusFault_IRQn 0 */
122 | while (1)
123 | {
124 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */
125 | /* USER CODE END W1_BusFault_IRQn 0 */
126 | }
127 | }
128 |
129 | /**
130 | * @brief This function handles Undefined instruction or illegal state.
131 | */
132 | void UsageFault_Handler(void)
133 | {
134 | /* USER CODE BEGIN UsageFault_IRQn 0 */
135 |
136 | /* USER CODE END UsageFault_IRQn 0 */
137 | while (1)
138 | {
139 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
140 | /* USER CODE END W1_UsageFault_IRQn 0 */
141 | }
142 | }
143 |
144 | /**
145 | * @brief This function handles System service call via SWI instruction.
146 | */
147 | void SVC_Handler(void)
148 | {
149 | /* USER CODE BEGIN SVCall_IRQn 0 */
150 |
151 | /* USER CODE END SVCall_IRQn 0 */
152 | /* USER CODE BEGIN SVCall_IRQn 1 */
153 |
154 | /* USER CODE END SVCall_IRQn 1 */
155 | }
156 |
157 | /**
158 | * @brief This function handles Debug monitor.
159 | */
160 | void DebugMon_Handler(void)
161 | {
162 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */
163 |
164 | /* USER CODE END DebugMonitor_IRQn 0 */
165 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */
166 |
167 | /* USER CODE END DebugMonitor_IRQn 1 */
168 | }
169 |
170 | /**
171 | * @brief This function handles Pendable request for system service.
172 | */
173 | void PendSV_Handler(void)
174 | {
175 | /* USER CODE BEGIN PendSV_IRQn 0 */
176 |
177 | /* USER CODE END PendSV_IRQn 0 */
178 | /* USER CODE BEGIN PendSV_IRQn 1 */
179 |
180 | /* USER CODE END PendSV_IRQn 1 */
181 | }
182 |
183 | /**
184 | * @brief This function handles System tick timer.
185 | */
186 | void SysTick_Handler(void)
187 | {
188 | /* USER CODE BEGIN SysTick_IRQn 0 */
189 |
190 | /* USER CODE END SysTick_IRQn 0 */
191 | HAL_IncTick();
192 | /* USER CODE BEGIN SysTick_IRQn 1 */
193 |
194 | /* USER CODE END SysTick_IRQn 1 */
195 | }
196 |
197 | /******************************************************************************/
198 | /* STM32F1xx Peripheral Interrupt Handlers */
199 | /* Add here the Interrupt Handlers for the used peripherals. */
200 | /* For the available peripheral interrupt handler names, */
201 | /* please refer to the startup file (startup_stm32f1xx.s). */
202 | /******************************************************************************/
203 |
204 | /**
205 | * @brief This function handles USART1 global interrupt.
206 | */
207 | void USART1_IRQHandler(void)
208 | {
209 | /* USER CODE BEGIN USART1_IRQn 0 */
210 |
211 | /* USER CODE END USART1_IRQn 0 */
212 | HAL_UART_IRQHandler(&huart1);
213 | /* USER CODE BEGIN USART1_IRQn 1 */
214 | /* USER CODE END USART1_IRQn 1 */
215 | }
216 |
217 | /**
218 | * @brief This function handles USART2 global interrupt.
219 | */
220 | void USART2_IRQHandler(void)
221 | {
222 | /* USER CODE BEGIN USART2_IRQn 0 */
223 |
224 | /* USER CODE END USART2_IRQn 0 */
225 | HAL_UART_IRQHandler(&huart2);
226 | /* USER CODE BEGIN USART2_IRQn 1 */
227 |
228 | /* USER CODE END USART2_IRQn 1 */
229 | }
230 |
231 | /* USER CODE BEGIN 1 */
232 |
233 | /* USER CODE END 1 */
234 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
235 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_def.h
4 | * @author MCD Application Team
5 | * @brief This file contains HAL common defines, enumeration, macros and
6 | * structures definitions.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software is licensed under terms that can be found in the LICENSE file
14 | * in the root directory of this software component.
15 | * If no LICENSE file comes with this software, it is provided AS-IS.
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F1xx_HAL_DEF
22 | #define __STM32F1xx_HAL_DEF
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f1xx.h"
30 | #include "Legacy/stm32_hal_legacy.h"
31 | #include
32 |
33 | /* Exported types ------------------------------------------------------------*/
34 |
35 | /**
36 | * @brief HAL Status structures definition
37 | */
38 | typedef enum
39 | {
40 | HAL_OK = 0x00U,
41 | HAL_ERROR = 0x01U,
42 | HAL_BUSY = 0x02U,
43 | HAL_TIMEOUT = 0x03U
44 | } HAL_StatusTypeDef;
45 |
46 | /**
47 | * @brief HAL Lock structures definition
48 | */
49 | typedef enum
50 | {
51 | HAL_UNLOCKED = 0x00U,
52 | HAL_LOCKED = 0x01U
53 | } HAL_LockTypeDef;
54 |
55 | /* Exported macro ------------------------------------------------------------*/
56 | #define HAL_MAX_DELAY 0xFFFFFFFFU
57 |
58 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
59 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
60 |
61 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
62 | do{ \
63 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
64 | (__DMA_HANDLE__).Parent = (__HANDLE__); \
65 | } while(0U)
66 |
67 | #if !defined(UNUSED)
68 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
69 | #endif /* UNUSED */
70 |
71 | /** @brief Reset the Handle's State field.
72 | * @param __HANDLE__ specifies the Peripheral Handle.
73 | * @note This macro can be used for the following purpose:
74 | * - When the Handle is declared as local variable; before passing it as parameter
75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
76 | * to set to 0 the Handle's "State" field.
77 | * Otherwise, "State" field may have any random value and the first time the function
78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed
79 | * (i.e. HAL_PPP_MspInit() will not be executed).
80 | * - When there is a need to reconfigure the low level hardware: instead of calling
81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function
83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware.
84 | * @retval None
85 | */
86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
87 |
88 | #if (USE_RTOS == 1U)
89 | /* Reserved for future use */
90 | #error "USE_RTOS should be 0 in the current HAL release"
91 | #else
92 | #define __HAL_LOCK(__HANDLE__) \
93 | do{ \
94 | if((__HANDLE__)->Lock == HAL_LOCKED) \
95 | { \
96 | return HAL_BUSY; \
97 | } \
98 | else \
99 | { \
100 | (__HANDLE__)->Lock = HAL_LOCKED; \
101 | } \
102 | }while (0U)
103 |
104 | #define __HAL_UNLOCK(__HANDLE__) \
105 | do{ \
106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \
107 | }while (0U)
108 | #endif /* USE_RTOS */
109 |
110 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
111 | #ifndef __weak
112 | #define __weak __attribute__((weak))
113 | #endif
114 | #ifndef __packed
115 | #define __packed __attribute__((packed))
116 | #endif
117 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
118 | #ifndef __weak
119 | #define __weak __attribute__((weak))
120 | #endif /* __weak */
121 | #ifndef __packed
122 | #define __packed __attribute__((__packed__))
123 | #endif /* __packed */
124 | #endif /* __GNUC__ */
125 |
126 |
127 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
128 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
129 | #ifndef __ALIGN_BEGIN
130 | #define __ALIGN_BEGIN
131 | #endif
132 | #ifndef __ALIGN_END
133 | #define __ALIGN_END __attribute__ ((aligned (4)))
134 | #endif
135 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
136 | #ifndef __ALIGN_END
137 | #define __ALIGN_END __attribute__ ((aligned (4)))
138 | #endif /* __ALIGN_END */
139 | #ifndef __ALIGN_BEGIN
140 | #define __ALIGN_BEGIN
141 | #endif /* __ALIGN_BEGIN */
142 | #else
143 | #ifndef __ALIGN_END
144 | #define __ALIGN_END
145 | #endif /* __ALIGN_END */
146 | #ifndef __ALIGN_BEGIN
147 | #if defined (__CC_ARM) /* ARM Compiler V5*/
148 | #define __ALIGN_BEGIN __align(4)
149 | #elif defined (__ICCARM__) /* IAR Compiler */
150 | #define __ALIGN_BEGIN
151 | #endif /* __CC_ARM */
152 | #endif /* __ALIGN_BEGIN */
153 | #endif /* __GNUC__ */
154 |
155 |
156 | /**
157 | * @brief __RAM_FUNC definition
158 | */
159 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
160 | /* ARM Compiler V4/V5 and V6
161 | --------------------------
162 | RAM functions are defined using the toolchain options.
163 | Functions that are executed in RAM should reside in a separate source module.
164 | Using the 'Options for File' dialog you can simply change the 'Code / Const'
165 | area of a module to a memory space in physical RAM.
166 | Available memory areas are declared in the 'Target' tab of the 'Options for Target'
167 | dialog.
168 | */
169 | #define __RAM_FUNC
170 |
171 | #elif defined ( __ICCARM__ )
172 | /* ICCARM Compiler
173 | ---------------
174 | RAM functions are defined using a specific toolchain keyword "__ramfunc".
175 | */
176 | #define __RAM_FUNC __ramfunc
177 |
178 | #elif defined ( __GNUC__ )
179 | /* GNU Compiler
180 | ------------
181 | RAM functions are defined using a specific toolchain attribute
182 | "__attribute__((section(".RamFunc")))".
183 | */
184 | #define __RAM_FUNC __attribute__((section(".RamFunc")))
185 |
186 | #endif
187 |
188 | /**
189 | * @brief __NOINLINE definition
190 | */
191 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
192 | /* ARM V4/V5 and V6 & GNU Compiler
193 | -------------------------------
194 | */
195 | #define __NOINLINE __attribute__ ( (noinline) )
196 |
197 | #elif defined ( __ICCARM__ )
198 | /* ICCARM Compiler
199 | ---------------
200 | */
201 | #define __NOINLINE _Pragma("optimize = no_inline")
202 |
203 | #endif
204 |
205 | #ifdef __cplusplus
206 | }
207 | #endif
208 |
209 | #endif /* ___STM32F1xx_HAL_DEF */
210 |
211 |
212 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/cmsis_compiler.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_compiler.h
3 | * @brief CMSIS compiler generic header file
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #ifndef __CMSIS_COMPILER_H
26 | #define __CMSIS_COMPILER_H
27 |
28 | #include
29 |
30 | /*
31 | * Arm Compiler 4/5
32 | */
33 | #if defined ( __CC_ARM )
34 | #include "cmsis_armcc.h"
35 |
36 |
37 | /*
38 | * Arm Compiler 6 (armclang)
39 | */
40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
41 | #include "cmsis_armclang.h"
42 |
43 |
44 | /*
45 | * GNU Compiler
46 | */
47 | #elif defined ( __GNUC__ )
48 | #include "cmsis_gcc.h"
49 |
50 |
51 | /*
52 | * IAR Compiler
53 | */
54 | #elif defined ( __ICCARM__ )
55 | #include
56 |
57 |
58 | /*
59 | * TI Arm Compiler
60 | */
61 | #elif defined ( __TI_ARM__ )
62 | #include
63 |
64 | #ifndef __ASM
65 | #define __ASM __asm
66 | #endif
67 | #ifndef __INLINE
68 | #define __INLINE inline
69 | #endif
70 | #ifndef __STATIC_INLINE
71 | #define __STATIC_INLINE static inline
72 | #endif
73 | #ifndef __STATIC_FORCEINLINE
74 | #define __STATIC_FORCEINLINE __STATIC_INLINE
75 | #endif
76 | #ifndef __NO_RETURN
77 | #define __NO_RETURN __attribute__((noreturn))
78 | #endif
79 | #ifndef __USED
80 | #define __USED __attribute__((used))
81 | #endif
82 | #ifndef __WEAK
83 | #define __WEAK __attribute__((weak))
84 | #endif
85 | #ifndef __PACKED
86 | #define __PACKED __attribute__((packed))
87 | #endif
88 | #ifndef __PACKED_STRUCT
89 | #define __PACKED_STRUCT struct __attribute__((packed))
90 | #endif
91 | #ifndef __PACKED_UNION
92 | #define __PACKED_UNION union __attribute__((packed))
93 | #endif
94 | #ifndef __UNALIGNED_UINT32 /* deprecated */
95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; };
96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
97 | #endif
98 | #ifndef __UNALIGNED_UINT16_WRITE
99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
101 | #endif
102 | #ifndef __UNALIGNED_UINT16_READ
103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
105 | #endif
106 | #ifndef __UNALIGNED_UINT32_WRITE
107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
109 | #endif
110 | #ifndef __UNALIGNED_UINT32_READ
111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
113 | #endif
114 | #ifndef __ALIGNED
115 | #define __ALIGNED(x) __attribute__((aligned(x)))
116 | #endif
117 | #ifndef __RESTRICT
118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
119 | #define __RESTRICT
120 | #endif
121 |
122 |
123 | /*
124 | * TASKING Compiler
125 | */
126 | #elif defined ( __TASKING__ )
127 | /*
128 | * The CMSIS functions have been implemented as intrinsics in the compiler.
129 | * Please use "carm -?i" to get an up to date list of all intrinsics,
130 | * Including the CMSIS ones.
131 | */
132 |
133 | #ifndef __ASM
134 | #define __ASM __asm
135 | #endif
136 | #ifndef __INLINE
137 | #define __INLINE inline
138 | #endif
139 | #ifndef __STATIC_INLINE
140 | #define __STATIC_INLINE static inline
141 | #endif
142 | #ifndef __STATIC_FORCEINLINE
143 | #define __STATIC_FORCEINLINE __STATIC_INLINE
144 | #endif
145 | #ifndef __NO_RETURN
146 | #define __NO_RETURN __attribute__((noreturn))
147 | #endif
148 | #ifndef __USED
149 | #define __USED __attribute__((used))
150 | #endif
151 | #ifndef __WEAK
152 | #define __WEAK __attribute__((weak))
153 | #endif
154 | #ifndef __PACKED
155 | #define __PACKED __packed__
156 | #endif
157 | #ifndef __PACKED_STRUCT
158 | #define __PACKED_STRUCT struct __packed__
159 | #endif
160 | #ifndef __PACKED_UNION
161 | #define __PACKED_UNION union __packed__
162 | #endif
163 | #ifndef __UNALIGNED_UINT32 /* deprecated */
164 | struct __packed__ T_UINT32 { uint32_t v; };
165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
166 | #endif
167 | #ifndef __UNALIGNED_UINT16_WRITE
168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
170 | #endif
171 | #ifndef __UNALIGNED_UINT16_READ
172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
174 | #endif
175 | #ifndef __UNALIGNED_UINT32_WRITE
176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
178 | #endif
179 | #ifndef __UNALIGNED_UINT32_READ
180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
182 | #endif
183 | #ifndef __ALIGNED
184 | #define __ALIGNED(x) __align(x)
185 | #endif
186 | #ifndef __RESTRICT
187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
188 | #define __RESTRICT
189 | #endif
190 |
191 |
192 | /*
193 | * COSMIC Compiler
194 | */
195 | #elif defined ( __CSMC__ )
196 | #include
197 |
198 | #ifndef __ASM
199 | #define __ASM _asm
200 | #endif
201 | #ifndef __INLINE
202 | #define __INLINE inline
203 | #endif
204 | #ifndef __STATIC_INLINE
205 | #define __STATIC_INLINE static inline
206 | #endif
207 | #ifndef __STATIC_FORCEINLINE
208 | #define __STATIC_FORCEINLINE __STATIC_INLINE
209 | #endif
210 | #ifndef __NO_RETURN
211 | // NO RETURN is automatically detected hence no warning here
212 | #define __NO_RETURN
213 | #endif
214 | #ifndef __USED
215 | #warning No compiler specific solution for __USED. __USED is ignored.
216 | #define __USED
217 | #endif
218 | #ifndef __WEAK
219 | #define __WEAK __weak
220 | #endif
221 | #ifndef __PACKED
222 | #define __PACKED @packed
223 | #endif
224 | #ifndef __PACKED_STRUCT
225 | #define __PACKED_STRUCT @packed struct
226 | #endif
227 | #ifndef __PACKED_UNION
228 | #define __PACKED_UNION @packed union
229 | #endif
230 | #ifndef __UNALIGNED_UINT32 /* deprecated */
231 | @packed struct T_UINT32 { uint32_t v; };
232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
233 | #endif
234 | #ifndef __UNALIGNED_UINT16_WRITE
235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
237 | #endif
238 | #ifndef __UNALIGNED_UINT16_READ
239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
241 | #endif
242 | #ifndef __UNALIGNED_UINT32_WRITE
243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
245 | #endif
246 | #ifndef __UNALIGNED_UINT32_READ
247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
249 | #endif
250 | #ifndef __ALIGNED
251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
252 | #define __ALIGNED(x)
253 | #endif
254 | #ifndef __RESTRICT
255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
256 | #define __RESTRICT
257 | #endif
258 |
259 |
260 | #else
261 | #error Unknown compiler.
262 | #endif
263 |
264 |
265 | #endif /* __CMSIS_COMPILER_H */
266 |
267 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_flash.h
4 | * @author MCD Application Team
5 | * @brief Header file of Flash HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file in
13 | * the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | ******************************************************************************
16 | */
17 |
18 | /* Define to prevent recursive inclusion -------------------------------------*/
19 | #ifndef __STM32F1xx_HAL_FLASH_H
20 | #define __STM32F1xx_HAL_FLASH_H
21 |
22 | #ifdef __cplusplus
23 | extern "C" {
24 | #endif
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "stm32f1xx_hal_def.h"
28 |
29 | /** @addtogroup STM32F1xx_HAL_Driver
30 | * @{
31 | */
32 |
33 | /** @addtogroup FLASH
34 | * @{
35 | */
36 |
37 | /** @addtogroup FLASH_Private_Constants
38 | * @{
39 | */
40 | #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
41 | /**
42 | * @}
43 | */
44 |
45 | /** @addtogroup FLASH_Private_Macros
46 | * @{
47 | */
48 |
49 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
50 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
51 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
52 |
53 | #if defined(FLASH_ACR_LATENCY)
54 | #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
55 | ((__LATENCY__) == FLASH_LATENCY_1) || \
56 | ((__LATENCY__) == FLASH_LATENCY_2))
57 |
58 | #else
59 | #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
60 | #endif /* FLASH_ACR_LATENCY */
61 | /**
62 | * @}
63 | */
64 |
65 | /* Exported types ------------------------------------------------------------*/
66 | /** @defgroup FLASH_Exported_Types FLASH Exported Types
67 | * @{
68 | */
69 |
70 | /**
71 | * @brief FLASH Procedure structure definition
72 | */
73 | typedef enum
74 | {
75 | FLASH_PROC_NONE = 0U,
76 | FLASH_PROC_PAGEERASE = 1U,
77 | FLASH_PROC_MASSERASE = 2U,
78 | FLASH_PROC_PROGRAMHALFWORD = 3U,
79 | FLASH_PROC_PROGRAMWORD = 4U,
80 | FLASH_PROC_PROGRAMDOUBLEWORD = 5U
81 | } FLASH_ProcedureTypeDef;
82 |
83 | /**
84 | * @brief FLASH handle Structure definition
85 | */
86 | typedef struct
87 | {
88 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
89 |
90 | __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
91 |
92 | __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
93 |
94 | __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
95 |
96 | HAL_LockTypeDef Lock; /*!< FLASH locking object */
97 |
98 | __IO uint32_t ErrorCode; /*!< FLASH error code
99 | This parameter can be a value of @ref FLASH_Error_Codes */
100 | } FLASH_ProcessTypeDef;
101 |
102 | /**
103 | * @}
104 | */
105 |
106 | /* Exported constants --------------------------------------------------------*/
107 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
108 | * @{
109 | */
110 |
111 | /** @defgroup FLASH_Error_Codes FLASH Error Codes
112 | * @{
113 | */
114 |
115 | #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
116 | #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
117 | #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
118 | #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
119 |
120 | /**
121 | * @}
122 | */
123 |
124 | /** @defgroup FLASH_Type_Program FLASH Type Program
125 | * @{
126 | */
127 | #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA)
181 |
182 | /**
183 | * @brief Disable the FLASH half cycle access.
184 | * @note half cycle access can only be used with a low-frequency clock of less than
185 | 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
186 | * @retval None
187 | */
188 | #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
189 |
190 | /**
191 | * @}
192 | */
193 |
194 | #if defined(FLASH_ACR_LATENCY)
195 | /** @defgroup FLASH_EM_Latency FLASH Latency
196 | * @brief macros to handle FLASH Latency
197 | * @{
198 | */
199 |
200 | /**
201 | * @brief Set the FLASH Latency.
202 | * @param __LATENCY__ FLASH Latency
203 | * The value of this parameter depend on device used within the same series
204 | * @retval None
205 | */
206 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
207 |
208 |
209 | /**
210 | * @brief Get the FLASH Latency.
211 | * @retval FLASH Latency
212 | * The value of this parameter depend on device used within the same series
213 | */
214 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
215 |
216 | /**
217 | * @}
218 | */
219 |
220 | #endif /* FLASH_ACR_LATENCY */
221 | /** @defgroup FLASH_Prefetch FLASH Prefetch
222 | * @brief macros to handle FLASH Prefetch buffer
223 | * @{
224 | */
225 | /**
226 | * @brief Enable the FLASH prefetch buffer.
227 | * @retval None
228 | */
229 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
230 |
231 | /**
232 | * @brief Disable the FLASH prefetch buffer.
233 | * @retval None
234 | */
235 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
236 |
237 | /**
238 | * @}
239 | */
240 |
241 | /**
242 | * @}
243 | */
244 |
245 | /* Include FLASH HAL Extended module */
246 | #include "stm32f1xx_hal_flash_ex.h"
247 |
248 | /* Exported functions --------------------------------------------------------*/
249 | /** @addtogroup FLASH_Exported_Functions
250 | * @{
251 | */
252 |
253 | /** @addtogroup FLASH_Exported_Functions_Group1
254 | * @{
255 | */
256 | /* IO operation functions *****************************************************/
257 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
258 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
259 |
260 | /* FLASH IRQ handler function */
261 | void HAL_FLASH_IRQHandler(void);
262 | /* Callbacks in non blocking modes */
263 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
264 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
265 |
266 | /**
267 | * @}
268 | */
269 |
270 | /** @addtogroup FLASH_Exported_Functions_Group2
271 | * @{
272 | */
273 | /* Peripheral Control functions ***********************************************/
274 | HAL_StatusTypeDef HAL_FLASH_Unlock(void);
275 | HAL_StatusTypeDef HAL_FLASH_Lock(void);
276 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
277 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
278 | void HAL_FLASH_OB_Launch(void);
279 |
280 | /**
281 | * @}
282 | */
283 |
284 | /** @addtogroup FLASH_Exported_Functions_Group3
285 | * @{
286 | */
287 | /* Peripheral State and Error functions ***************************************/
288 | uint32_t HAL_FLASH_GetError(void);
289 |
290 | /**
291 | * @}
292 | */
293 |
294 | /**
295 | * @}
296 | */
297 |
298 | /* Private function -------------------------------------------------*/
299 | /** @addtogroup FLASH_Private_Functions
300 | * @{
301 | */
302 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
303 | #if defined(FLASH_BANK2_END)
304 | HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
305 | #endif /* FLASH_BANK2_END */
306 |
307 | /**
308 | * @}
309 | */
310 |
311 | /**
312 | * @}
313 | */
314 |
315 | /**
316 | * @}
317 | */
318 |
319 | #ifdef __cplusplus
320 | }
321 | #endif
322 |
323 | #endif /* __STM32F1xx_HAL_FLASH_H */
324 |
325 |
326 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_tim_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of TIM HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file
13 | * in the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 |
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef STM32F1xx_HAL_TIM_EX_H
21 | #define STM32F1xx_HAL_TIM_EX_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "stm32f1xx_hal_def.h"
29 |
30 | /** @addtogroup STM32F1xx_HAL_Driver
31 | * @{
32 | */
33 |
34 | /** @addtogroup TIMEx
35 | * @{
36 | */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
40 | * @{
41 | */
42 |
43 | /**
44 | * @brief TIM Hall sensor Configuration Structure definition
45 | */
46 |
47 | typedef struct
48 | {
49 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
50 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */
51 |
52 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
53 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
54 |
55 | uint32_t IC1Filter; /*!< Specifies the input capture filter.
56 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
57 |
58 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
59 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
60 | } TIM_HallSensor_InitTypeDef;
61 | /**
62 | * @}
63 | */
64 | /* End of exported types -----------------------------------------------------*/
65 |
66 | /* Exported constants --------------------------------------------------------*/
67 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
68 | * @{
69 | */
70 |
71 | /** @defgroup TIMEx_Remap TIM Extended Remapping
72 | * @{
73 | */
74 | /**
75 | * @}
76 | */
77 |
78 | /**
79 | * @}
80 | */
81 | /* End of exported constants -------------------------------------------------*/
82 |
83 | /* Exported macro ------------------------------------------------------------*/
84 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
85 | * @{
86 | */
87 |
88 | /**
89 | * @}
90 | */
91 | /* End of exported macro -----------------------------------------------------*/
92 |
93 | /* Private macro -------------------------------------------------------------*/
94 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
95 | * @{
96 | */
97 |
98 | /**
99 | * @}
100 | */
101 | /* End of private macro ------------------------------------------------------*/
102 |
103 | /* Exported functions --------------------------------------------------------*/
104 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
105 | * @{
106 | */
107 |
108 | /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
109 | * @brief Timer Hall Sensor functions
110 | * @{
111 | */
112 | /* Timer Hall Sensor functions **********************************************/
113 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
114 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
115 |
116 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
117 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
118 |
119 | /* Blocking mode: Polling */
120 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
121 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
122 | /* Non-Blocking mode: Interrupt */
123 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
124 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
125 | /* Non-Blocking mode: DMA */
126 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
127 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
128 | /**
129 | * @}
130 | */
131 |
132 | /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
133 | * @brief Timer Complementary Output Compare functions
134 | * @{
135 | */
136 | /* Timer Complementary Output Compare functions *****************************/
137 | /* Blocking mode: Polling */
138 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
139 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
140 |
141 | /* Non-Blocking mode: Interrupt */
142 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
143 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
144 |
145 | /* Non-Blocking mode: DMA */
146 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
147 | uint16_t Length);
148 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
149 | /**
150 | * @}
151 | */
152 |
153 | /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
154 | * @brief Timer Complementary PWM functions
155 | * @{
156 | */
157 | /* Timer Complementary PWM functions ****************************************/
158 | /* Blocking mode: Polling */
159 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
160 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
161 |
162 | /* Non-Blocking mode: Interrupt */
163 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
164 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
165 | /* Non-Blocking mode: DMA */
166 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
167 | uint16_t Length);
168 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
169 | /**
170 | * @}
171 | */
172 |
173 | /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
174 | * @brief Timer Complementary One Pulse functions
175 | * @{
176 | */
177 | /* Timer Complementary One Pulse functions **********************************/
178 | /* Blocking mode: Polling */
179 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
180 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
181 |
182 | /* Non-Blocking mode: Interrupt */
183 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
184 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
185 | /**
186 | * @}
187 | */
188 |
189 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
190 | * @brief Peripheral Control functions
191 | * @{
192 | */
193 | /* Extended Control functions ************************************************/
194 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
195 | uint32_t CommutationSource);
196 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
197 | uint32_t CommutationSource);
198 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
199 | uint32_t CommutationSource);
200 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
201 | const TIM_MasterConfigTypeDef *sMasterConfig);
202 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
203 | const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
204 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
205 | /**
206 | * @}
207 | */
208 |
209 | /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
210 | * @brief Extended Callbacks functions
211 | * @{
212 | */
213 | /* Extended Callback **********************************************************/
214 | void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
215 | void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
216 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
217 | /**
218 | * @}
219 | */
220 |
221 | /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
222 | * @brief Extended Peripheral State functions
223 | * @{
224 | */
225 | /* Extended Peripheral State functions ***************************************/
226 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
227 | HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
228 | /**
229 | * @}
230 | */
231 |
232 | /**
233 | * @}
234 | */
235 | /* End of exported functions -------------------------------------------------*/
236 |
237 | /* Private functions----------------------------------------------------------*/
238 | /** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
239 | * @{
240 | */
241 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
242 | void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
243 | /**
244 | * @}
245 | */
246 | /* End of private functions --------------------------------------------------*/
247 |
248 | /**
249 | * @}
250 | */
251 |
252 | /**
253 | * @}
254 | */
255 |
256 | #ifdef __cplusplus
257 | }
258 | #endif
259 |
260 |
261 | #endif /* STM32F1xx_HAL_TIM_EX_H */
262 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx.h
4 | * @author MCD Application Team
5 | * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
6 | *
7 | * The file is the unique include file that the application programmer
8 | * is using in the C source code, usually in main.c. This file contains:
9 | * - Configuration section that allows to select:
10 | * - The STM32F1xx device used in the target application
11 | * - To use or not the peripheral's drivers in application code(i.e.
12 | * code will be based on direct access to peripheral's registers
13 | * rather than drivers API), this option is controlled by
14 | * "#define USE_HAL_DRIVER"
15 | *
16 | ******************************************************************************
17 | * @attention
18 | *
19 | * Copyright (c) 2017-2021 STMicroelectronics.
20 | * All rights reserved.
21 | *
22 | * This software is licensed under terms that can be found in the LICENSE file
23 | * in the root directory of this software component.
24 | * If no LICENSE file comes with this software, it is provided AS-IS.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /** @addtogroup CMSIS
30 | * @{
31 | */
32 |
33 | /** @addtogroup stm32f1xx
34 | * @{
35 | */
36 |
37 | #ifndef __STM32F1XX_H
38 | #define __STM32F1XX_H
39 |
40 | #ifdef __cplusplus
41 | extern "C" {
42 | #endif /* __cplusplus */
43 |
44 | /** @addtogroup Library_configuration_section
45 | * @{
46 | */
47 |
48 | /**
49 | * @brief STM32 Family
50 | */
51 | #if !defined (STM32F1)
52 | #define STM32F1
53 | #endif /* STM32F1 */
54 |
55 | /* Uncomment the line below according to the target STM32L device used in your
56 | application
57 | */
58 |
59 | #if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
60 | !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
61 | !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
62 | /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
63 | /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
64 | /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
65 | /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
66 | /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
67 | /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
68 | /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
69 | /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
70 | /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
71 | /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
72 | /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
73 | /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
74 | /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
75 | /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
76 | #endif
77 |
78 | /* Tip: To avoid modifying this file each time you need to switch between these
79 | devices, you can define the device in your toolchain compiler preprocessor.
80 | */
81 |
82 | #if !defined (USE_HAL_DRIVER)
83 | /**
84 | * @brief Comment the line below if you will not use the peripherals drivers.
85 | In this case, these drivers will not be included and the application code will
86 | be based on direct access to peripherals registers
87 | */
88 | /*#define USE_HAL_DRIVER */
89 | #endif /* USE_HAL_DRIVER */
90 |
91 | /**
92 | * @brief CMSIS Device version number
93 | */
94 | #define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
95 | #define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
96 | #define __STM32F1_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
97 | #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
98 | #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
99 | |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
100 | |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
101 | |(__STM32F1_CMSIS_VERSION_RC))
102 |
103 | /**
104 | * @}
105 | */
106 |
107 | /** @addtogroup Device_Included
108 | * @{
109 | */
110 |
111 | #if defined(STM32F100xB)
112 | #include "stm32f100xb.h"
113 | #elif defined(STM32F100xE)
114 | #include "stm32f100xe.h"
115 | #elif defined(STM32F101x6)
116 | #include "stm32f101x6.h"
117 | #elif defined(STM32F101xB)
118 | #include "stm32f101xb.h"
119 | #elif defined(STM32F101xE)
120 | #include "stm32f101xe.h"
121 | #elif defined(STM32F101xG)
122 | #include "stm32f101xg.h"
123 | #elif defined(STM32F102x6)
124 | #include "stm32f102x6.h"
125 | #elif defined(STM32F102xB)
126 | #include "stm32f102xb.h"
127 | #elif defined(STM32F103x6)
128 | #include "stm32f103x6.h"
129 | #elif defined(STM32F103xB)
130 | #include "stm32f103xb.h"
131 | #elif defined(STM32F103xE)
132 | #include "stm32f103xe.h"
133 | #elif defined(STM32F103xG)
134 | #include "stm32f103xg.h"
135 | #elif defined(STM32F105xC)
136 | #include "stm32f105xc.h"
137 | #elif defined(STM32F107xC)
138 | #include "stm32f107xc.h"
139 | #else
140 | #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
141 | #endif
142 |
143 | /**
144 | * @}
145 | */
146 |
147 | /** @addtogroup Exported_types
148 | * @{
149 | */
150 | typedef enum
151 | {
152 | RESET = 0,
153 | SET = !RESET
154 | } FlagStatus, ITStatus;
155 |
156 | typedef enum
157 | {
158 | DISABLE = 0,
159 | ENABLE = !DISABLE
160 | } FunctionalState;
161 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
162 |
163 | typedef enum
164 | {
165 | SUCCESS = 0U,
166 | ERROR = !SUCCESS
167 | } ErrorStatus;
168 |
169 | /**
170 | * @}
171 | */
172 |
173 |
174 | /** @addtogroup Exported_macros
175 | * @{
176 | */
177 | #define SET_BIT(REG, BIT) ((REG) |= (BIT))
178 |
179 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
180 |
181 | #define READ_BIT(REG, BIT) ((REG) & (BIT))
182 |
183 | #define CLEAR_REG(REG) ((REG) = (0x0))
184 |
185 | #define WRITE_REG(REG, VAL) ((REG) = (VAL))
186 |
187 | #define READ_REG(REG) ((REG))
188 |
189 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
190 |
191 | #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
192 |
193 | /* Use of CMSIS compiler intrinsics for register exclusive access */
194 | /* Atomic 32-bit register access macro to set one or several bits */
195 | #define ATOMIC_SET_BIT(REG, BIT) \
196 | do { \
197 | uint32_t val; \
198 | do { \
199 | val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
200 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
201 | } while(0)
202 |
203 | /* Atomic 32-bit register access macro to clear one or several bits */
204 | #define ATOMIC_CLEAR_BIT(REG, BIT) \
205 | do { \
206 | uint32_t val; \
207 | do { \
208 | val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
209 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
210 | } while(0)
211 |
212 | /* Atomic 32-bit register access macro to clear and set one or several bits */
213 | #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
214 | do { \
215 | uint32_t val; \
216 | do { \
217 | val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
218 | } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
219 | } while(0)
220 |
221 | /* Atomic 16-bit register access macro to set one or several bits */
222 | #define ATOMIC_SETH_BIT(REG, BIT) \
223 | do { \
224 | uint16_t val; \
225 | do { \
226 | val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
227 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
228 | } while(0)
229 |
230 | /* Atomic 16-bit register access macro to clear one or several bits */
231 | #define ATOMIC_CLEARH_BIT(REG, BIT) \
232 | do { \
233 | uint16_t val; \
234 | do { \
235 | val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
236 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
237 | } while(0)
238 |
239 | /* Atomic 16-bit register access macro to clear and set one or several bits */
240 | #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
241 | do { \
242 | uint16_t val; \
243 | do { \
244 | val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
245 | } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
246 | } while(0)
247 |
248 |
249 | /**
250 | * @}
251 | */
252 |
253 | #if defined (USE_HAL_DRIVER)
254 | #include "stm32f1xx_hal.h"
255 | #endif /* USE_HAL_DRIVER */
256 |
257 |
258 | #ifdef __cplusplus
259 | }
260 | #endif /* __cplusplus */
261 |
262 | #endif /* __STM32F1xx_H */
263 | /**
264 | * @}
265 | */
266 |
267 | /**
268 | * @}
269 | */
270 |
271 |
272 |
273 |
274 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/mpu_armv8.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv8.h
3 | * @brief CMSIS MPU API for Armv8-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV8_H
32 | #define ARM_MPU_ARMV8_H
33 |
34 | /** \brief Attribute for device memory (outer only) */
35 | #define ARM_MPU_ATTR_DEVICE ( 0U )
36 |
37 | /** \brief Attribute for non-cacheable, normal memory */
38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39 |
40 | /** \brief Attribute for normal memory (outer and inner)
41 | * \param NT Non-Transient: Set to 1 for non-transient data.
42 | * \param WB Write-Back: Set to 1 to use write-back update policy.
43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
45 | */
46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
48 |
49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51 |
52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54 |
55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57 |
58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60 |
61 | /** \brief Memory Attribute
62 | * \param O Outer memory attributes
63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
64 | */
65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
66 |
67 | /** \brief Normal memory non-shareable */
68 | #define ARM_MPU_SH_NON (0U)
69 |
70 | /** \brief Normal memory outer shareable */
71 | #define ARM_MPU_SH_OUTER (2U)
72 |
73 | /** \brief Normal memory inner shareable */
74 | #define ARM_MPU_SH_INNER (3U)
75 |
76 | /** \brief Memory access permissions
77 | * \param RO Read-Only: Set to 1 for read-only memory.
78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory.
79 | */
80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
81 |
82 | /** \brief Region Base Address Register value
83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
84 | * \param SH Defines the Shareability domain for this memory region.
85 | * \param RO Read-Only: Set to 1 for a read-only memory region.
86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
88 | */
89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90 | ((BASE & MPU_RBAR_BASE_Msk) | \
91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94 |
95 | /** \brief Region Limit Address Register value
96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
97 | * \param IDX The attribute index to be associated with this memory region.
98 | */
99 | #define ARM_MPU_RLAR(LIMIT, IDX) \
100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102 | (MPU_RLAR_EN_Msk))
103 |
104 | /**
105 | * Struct for a single MPU Region
106 | */
107 | typedef struct {
108 | uint32_t RBAR; /*!< Region Base Address Register value */
109 | uint32_t RLAR; /*!< Region Limit Address Register value */
110 | } ARM_MPU_Region_t;
111 |
112 | /** Enable the MPU.
113 | * \param MPU_Control Default access permissions for unconfigured regions.
114 | */
115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
116 | {
117 | __DSB();
118 | __ISB();
119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
122 | #endif
123 | }
124 |
125 | /** Disable the MPU.
126 | */
127 | __STATIC_INLINE void ARM_MPU_Disable(void)
128 | {
129 | __DSB();
130 | __ISB();
131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
133 | #endif
134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
135 | }
136 |
137 | #ifdef MPU_NS
138 | /** Enable the Non-secure MPU.
139 | * \param MPU_Control Default access permissions for unconfigured regions.
140 | */
141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
142 | {
143 | __DSB();
144 | __ISB();
145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
148 | #endif
149 | }
150 |
151 | /** Disable the Non-secure MPU.
152 | */
153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void)
154 | {
155 | __DSB();
156 | __ISB();
157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
159 | #endif
160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
161 | }
162 | #endif
163 |
164 | /** Set the memory attribute encoding to the given MPU.
165 | * \param mpu Pointer to the MPU to be configured.
166 | * \param idx The attribute index to be set [0-7]
167 | * \param attr The attribute value to be set.
168 | */
169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
170 | {
171 | const uint8_t reg = idx / 4U;
172 | const uint32_t pos = ((idx % 4U) * 8U);
173 | const uint32_t mask = 0xFFU << pos;
174 |
175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
176 | return; // invalid index
177 | }
178 |
179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
180 | }
181 |
182 | /** Set the memory attribute encoding.
183 | * \param idx The attribute index to be set [0-7]
184 | * \param attr The attribute value to be set.
185 | */
186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
187 | {
188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr);
189 | }
190 |
191 | #ifdef MPU_NS
192 | /** Set the memory attribute encoding to the Non-secure MPU.
193 | * \param idx The attribute index to be set [0-7]
194 | * \param attr The attribute value to be set.
195 | */
196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
197 | {
198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
199 | }
200 | #endif
201 |
202 | /** Clear and disable the given MPU region of the given MPU.
203 | * \param mpu Pointer to MPU to be used.
204 | * \param rnr Region number to be cleared.
205 | */
206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
207 | {
208 | mpu->RNR = rnr;
209 | mpu->RLAR = 0U;
210 | }
211 |
212 | /** Clear and disable the given MPU region.
213 | * \param rnr Region number to be cleared.
214 | */
215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
216 | {
217 | ARM_MPU_ClrRegionEx(MPU, rnr);
218 | }
219 |
220 | #ifdef MPU_NS
221 | /** Clear and disable the given Non-secure MPU region.
222 | * \param rnr Region number to be cleared.
223 | */
224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
225 | {
226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr);
227 | }
228 | #endif
229 |
230 | /** Configure the given MPU region of the given MPU.
231 | * \param mpu Pointer to MPU to be used.
232 | * \param rnr Region number to be configured.
233 | * \param rbar Value for RBAR register.
234 | * \param rlar Value for RLAR register.
235 | */
236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
237 | {
238 | mpu->RNR = rnr;
239 | mpu->RBAR = rbar;
240 | mpu->RLAR = rlar;
241 | }
242 |
243 | /** Configure the given MPU region.
244 | * \param rnr Region number to be configured.
245 | * \param rbar Value for RBAR register.
246 | * \param rlar Value for RLAR register.
247 | */
248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
249 | {
250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
251 | }
252 |
253 | #ifdef MPU_NS
254 | /** Configure the given Non-secure MPU region.
255 | * \param rnr Region number to be configured.
256 | * \param rbar Value for RBAR register.
257 | * \param rlar Value for RLAR register.
258 | */
259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
260 | {
261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
262 | }
263 | #endif
264 |
265 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
266 | * \param dst Destination data is copied to.
267 | * \param src Source data is copied from.
268 | * \param len Amount of data words to be copied.
269 | */
270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
271 | {
272 | uint32_t i;
273 | for (i = 0U; i < len; ++i)
274 | {
275 | dst[i] = src[i];
276 | }
277 | }
278 |
279 | /** Load the given number of MPU regions from a table to the given MPU.
280 | * \param mpu Pointer to the MPU registers to be used.
281 | * \param rnr First region number to be configured.
282 | * \param table Pointer to the MPU configuration table.
283 | * \param cnt Amount of regions to be configured.
284 | */
285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
286 | {
287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
288 | if (cnt == 1U) {
289 | mpu->RNR = rnr;
290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
291 | } else {
292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
294 |
295 | mpu->RNR = rnrBase;
296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
299 | table += c;
300 | cnt -= c;
301 | rnrOffset = 0U;
302 | rnrBase += MPU_TYPE_RALIASES;
303 | mpu->RNR = rnrBase;
304 | }
305 |
306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
307 | }
308 | }
309 |
310 | /** Load the given number of MPU regions from a table.
311 | * \param rnr First region number to be configured.
312 | * \param table Pointer to the MPU configuration table.
313 | * \param cnt Amount of regions to be configured.
314 | */
315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
316 | {
317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt);
318 | }
319 |
320 | #ifdef MPU_NS
321 | /** Load the given number of MPU regions from a table to the Non-secure MPU.
322 | * \param rnr First region number to be configured.
323 | * \param table Pointer to the MPU configuration table.
324 | * \param cnt Amount of regions to be configured.
325 | */
326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
327 | {
328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
329 | }
330 | #endif
331 |
332 | #endif
333 |
334 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal.h
4 | * @author MCD Application Team
5 | * @brief This file contains all the functions prototypes for the HAL
6 | * module driver.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software is licensed under terms that can be found in the LICENSE file
14 | * in the root directory of this software component.
15 | * If no LICENSE file comes with this software, it is provided AS-IS.
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F1xx_HAL_H
22 | #define __STM32F1xx_HAL_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f1xx_hal_conf.h"
30 |
31 | /** @addtogroup STM32F1xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup HAL
36 | * @{
37 | */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 |
41 | /** @defgroup HAL_Exported_Constants HAL Exported Constants
42 | * @{
43 | */
44 |
45 | /** @defgroup HAL_TICK_FREQ Tick Frequency
46 | * @{
47 | */
48 | typedef enum
49 | {
50 | HAL_TICK_FREQ_10HZ = 100U,
51 | HAL_TICK_FREQ_100HZ = 10U,
52 | HAL_TICK_FREQ_1KHZ = 1U,
53 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
54 | } HAL_TickFreqTypeDef;
55 | /**
56 | * @}
57 | */
58 | /* Exported types ------------------------------------------------------------*/
59 | extern __IO uint32_t uwTick;
60 | extern uint32_t uwTickPrio;
61 | extern HAL_TickFreqTypeDef uwTickFreq;
62 |
63 | /**
64 | * @}
65 | */
66 | /* Exported macro ------------------------------------------------------------*/
67 | /** @defgroup HAL_Exported_Macros HAL Exported Macros
68 | * @{
69 | */
70 |
71 | /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
72 | * @brief Freeze/Unfreeze Peripherals in Debug mode
73 | * Note: On devices STM32F10xx8 and STM32F10xxB,
74 | * STM32F101xC/D/E and STM32F103xC/D/E,
75 | * STM32F101xF/G and STM32F103xF/G
76 | * STM32F10xx4 and STM32F10xx6
77 | * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
78 | * debug mode (not accessible by the user software in normal mode).
79 | * Refer to errata sheet of these devices for more details.
80 | * @{
81 | */
82 |
83 | /* Peripherals on APB1 */
84 | /**
85 | * @brief TIM2 Peripherals Debug mode
86 | */
87 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
88 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
89 |
90 | /**
91 | * @brief TIM3 Peripherals Debug mode
92 | */
93 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
94 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
95 |
96 | #if defined (DBGMCU_CR_DBG_TIM4_STOP)
97 | /**
98 | * @brief TIM4 Peripherals Debug mode
99 | */
100 | #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
101 | #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
102 | #endif
103 |
104 | #if defined (DBGMCU_CR_DBG_TIM5_STOP)
105 | /**
106 | * @brief TIM5 Peripherals Debug mode
107 | */
108 | #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
109 | #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
110 | #endif
111 |
112 | #if defined (DBGMCU_CR_DBG_TIM6_STOP)
113 | /**
114 | * @brief TIM6 Peripherals Debug mode
115 | */
116 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
117 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
118 | #endif
119 |
120 | #if defined (DBGMCU_CR_DBG_TIM7_STOP)
121 | /**
122 | * @brief TIM7 Peripherals Debug mode
123 | */
124 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
125 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
126 | #endif
127 |
128 | #if defined (DBGMCU_CR_DBG_TIM12_STOP)
129 | /**
130 | * @brief TIM12 Peripherals Debug mode
131 | */
132 | #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
133 | #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
134 | #endif
135 |
136 | #if defined (DBGMCU_CR_DBG_TIM13_STOP)
137 | /**
138 | * @brief TIM13 Peripherals Debug mode
139 | */
140 | #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
141 | #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
142 | #endif
143 |
144 | #if defined (DBGMCU_CR_DBG_TIM14_STOP)
145 | /**
146 | * @brief TIM14 Peripherals Debug mode
147 | */
148 | #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
149 | #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
150 | #endif
151 |
152 | /**
153 | * @brief WWDG Peripherals Debug mode
154 | */
155 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
156 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
157 |
158 | /**
159 | * @brief IWDG Peripherals Debug mode
160 | */
161 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
162 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
163 |
164 | /**
165 | * @brief I2C1 Peripherals Debug mode
166 | */
167 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
168 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
169 |
170 | #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
171 | /**
172 | * @brief I2C2 Peripherals Debug mode
173 | */
174 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
175 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
176 | #endif
177 |
178 | #if defined (DBGMCU_CR_DBG_CAN1_STOP)
179 | /**
180 | * @brief CAN1 Peripherals Debug mode
181 | */
182 | #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
183 | #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
184 | #endif
185 |
186 | #if defined (DBGMCU_CR_DBG_CAN2_STOP)
187 | /**
188 | * @brief CAN2 Peripherals Debug mode
189 | */
190 | #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
191 | #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
192 | #endif
193 |
194 | /* Peripherals on APB2 */
195 | #if defined (DBGMCU_CR_DBG_TIM1_STOP)
196 | /**
197 | * @brief TIM1 Peripherals Debug mode
198 | */
199 | #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
200 | #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
201 | #endif
202 |
203 | #if defined (DBGMCU_CR_DBG_TIM8_STOP)
204 | /**
205 | * @brief TIM8 Peripherals Debug mode
206 | */
207 | #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
208 | #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
209 | #endif
210 |
211 | #if defined (DBGMCU_CR_DBG_TIM9_STOP)
212 | /**
213 | * @brief TIM9 Peripherals Debug mode
214 | */
215 | #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
216 | #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
217 | #endif
218 |
219 | #if defined (DBGMCU_CR_DBG_TIM10_STOP)
220 | /**
221 | * @brief TIM10 Peripherals Debug mode
222 | */
223 | #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
224 | #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
225 | #endif
226 |
227 | #if defined (DBGMCU_CR_DBG_TIM11_STOP)
228 | /**
229 | * @brief TIM11 Peripherals Debug mode
230 | */
231 | #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
232 | #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
233 | #endif
234 |
235 |
236 | #if defined (DBGMCU_CR_DBG_TIM15_STOP)
237 | /**
238 | * @brief TIM15 Peripherals Debug mode
239 | */
240 | #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
241 | #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
242 | #endif
243 |
244 | #if defined (DBGMCU_CR_DBG_TIM16_STOP)
245 | /**
246 | * @brief TIM16 Peripherals Debug mode
247 | */
248 | #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
249 | #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
250 | #endif
251 |
252 | #if defined (DBGMCU_CR_DBG_TIM17_STOP)
253 | /**
254 | * @brief TIM17 Peripherals Debug mode
255 | */
256 | #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
257 | #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
258 | #endif
259 |
260 | /**
261 | * @}
262 | */
263 |
264 | /** @defgroup HAL_Private_Macros HAL Private Macros
265 | * @{
266 | */
267 | #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
268 | ((FREQ) == HAL_TICK_FREQ_100HZ) || \
269 | ((FREQ) == HAL_TICK_FREQ_1KHZ))
270 | /**
271 | * @}
272 | */
273 |
274 | /* Exported functions --------------------------------------------------------*/
275 | /** @addtogroup HAL_Exported_Functions
276 | * @{
277 | */
278 | /** @addtogroup HAL_Exported_Functions_Group1
279 | * @{
280 | */
281 | /* Initialization and de-initialization functions ******************************/
282 | HAL_StatusTypeDef HAL_Init(void);
283 | HAL_StatusTypeDef HAL_DeInit(void);
284 | void HAL_MspInit(void);
285 | void HAL_MspDeInit(void);
286 | HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
287 | /**
288 | * @}
289 | */
290 |
291 | /** @addtogroup HAL_Exported_Functions_Group2
292 | * @{
293 | */
294 | /* Peripheral Control functions ************************************************/
295 | void HAL_IncTick(void);
296 | void HAL_Delay(uint32_t Delay);
297 | uint32_t HAL_GetTick(void);
298 | uint32_t HAL_GetTickPrio(void);
299 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
300 | HAL_TickFreqTypeDef HAL_GetTickFreq(void);
301 | void HAL_SuspendTick(void);
302 | void HAL_ResumeTick(void);
303 | uint32_t HAL_GetHalVersion(void);
304 | uint32_t HAL_GetREVID(void);
305 | uint32_t HAL_GetDEVID(void);
306 | uint32_t HAL_GetUIDw0(void);
307 | uint32_t HAL_GetUIDw1(void);
308 | uint32_t HAL_GetUIDw2(void);
309 | void HAL_DBGMCU_EnableDBGSleepMode(void);
310 | void HAL_DBGMCU_DisableDBGSleepMode(void);
311 | void HAL_DBGMCU_EnableDBGStopMode(void);
312 | void HAL_DBGMCU_DisableDBGStopMode(void);
313 | void HAL_DBGMCU_EnableDBGStandbyMode(void);
314 | void HAL_DBGMCU_DisableDBGStandbyMode(void);
315 | /**
316 | * @}
317 | */
318 |
319 | /**
320 | * @}
321 | */
322 |
323 | /**
324 | * @}
325 | */
326 | /* Private types -------------------------------------------------------------*/
327 | /* Private variables ---------------------------------------------------------*/
328 | /** @defgroup HAL_Private_Variables HAL Private Variables
329 | * @{
330 | */
331 | /**
332 | * @}
333 | */
334 | /* Private constants ---------------------------------------------------------*/
335 | /** @defgroup HAL_Private_Constants HAL Private Constants
336 | * @{
337 | */
338 | /**
339 | * @}
340 | */
341 | /* Private macros ------------------------------------------------------------*/
342 | /* Private functions ---------------------------------------------------------*/
343 | /**
344 | * @}
345 | */
346 |
347 | /**
348 | * @}
349 | */
350 |
351 | #ifdef __cplusplus
352 | }
353 | #endif
354 |
355 | #endif /* __STM32F1xx_HAL_H */
356 |
357 |
358 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/mpu_armv7.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv7.h
3 | * @brief CMSIS MPU API for Armv7-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV7_H
32 | #define ARM_MPU_ARMV7_H
33 |
34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62 |
63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69 |
70 | /** MPU Region Base Address Register Value
71 | *
72 | * \param Region The region to be configured, number 0 to 15.
73 | * \param BaseAddress The base address for the region.
74 | */
75 | #define ARM_MPU_RBAR(Region, BaseAddress) \
76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 | ((Region) & MPU_RBAR_REGION_Msk) | \
78 | (MPU_RBAR_VALID_Msk))
79 |
80 | /**
81 | * MPU Memory Access Attributes
82 | *
83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 | * \param IsShareable Region is shareable between multiple bus masters.
85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 | */
88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93 |
94 | /**
95 | * MPU Region Attribute and Size Register Value
96 | *
97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 | * \param SubRegionDisable Sub-region disable field.
101 | * \param Size Region size of the region to be configured, for example 4K, 8K.
102 | */
103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107 |
108 | /**
109 | * MPU Region Attribute and Size Register Value
110 | *
111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
114 | * \param IsShareable Region is shareable between multiple bus masters.
115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
117 | * \param SubRegionDisable Sub-region disable field.
118 | * \param Size Region size of the region to be configured, for example 4K, 8K.
119 | */
120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122 |
123 | /**
124 | * MPU Memory Access Attribute for strongly ordered memory.
125 | * - TEX: 000b
126 | * - Shareable
127 | * - Non-cacheable
128 | * - Non-bufferable
129 | */
130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131 |
132 | /**
133 | * MPU Memory Access Attribute for device memory.
134 | * - TEX: 000b (if non-shareable) or 010b (if shareable)
135 | * - Shareable or non-shareable
136 | * - Non-cacheable
137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable)
138 | *
139 | * \param IsShareable Configures the device memory as shareable or non-shareable.
140 | */
141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142 |
143 | /**
144 | * MPU Memory Access Attribute for normal memory.
145 | * - TEX: 1BBb (reflecting outer cacheability rules)
146 | * - Shareable or non-shareable
147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules)
148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules)
149 | *
150 | * \param OuterCp Configures the outer cache policy.
151 | * \param InnerCp Configures the inner cache policy.
152 | * \param IsShareable Configures the memory as shareable or non-shareable.
153 | */
154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155 |
156 | /**
157 | * MPU Memory Access Attribute non-cacheable policy.
158 | */
159 | #define ARM_MPU_CACHEP_NOCACHE 0U
160 |
161 | /**
162 | * MPU Memory Access Attribute write-back, write and read allocate policy.
163 | */
164 | #define ARM_MPU_CACHEP_WB_WRA 1U
165 |
166 | /**
167 | * MPU Memory Access Attribute write-through, no write allocate policy.
168 | */
169 | #define ARM_MPU_CACHEP_WT_NWA 2U
170 |
171 | /**
172 | * MPU Memory Access Attribute write-back, no write allocate policy.
173 | */
174 | #define ARM_MPU_CACHEP_WB_NWA 3U
175 |
176 |
177 | /**
178 | * Struct for a single MPU Region
179 | */
180 | typedef struct {
181 | uint32_t RBAR; //!< The region base address register value (RBAR)
182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
183 | } ARM_MPU_Region_t;
184 |
185 | /** Enable the MPU.
186 | * \param MPU_Control Default access permissions for unconfigured regions.
187 | */
188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 | {
190 | __DSB();
191 | __ISB();
192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 | #endif
196 | }
197 |
198 | /** Disable the MPU.
199 | */
200 | __STATIC_INLINE void ARM_MPU_Disable(void)
201 | {
202 | __DSB();
203 | __ISB();
204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 | #endif
207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 | }
209 |
210 | /** Clear and disable the given MPU region.
211 | * \param rnr Region number to be cleared.
212 | */
213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
214 | {
215 | MPU->RNR = rnr;
216 | MPU->RASR = 0U;
217 | }
218 |
219 | /** Configure an MPU region.
220 | * \param rbar Value for RBAR register.
221 | * \param rsar Value for RSAR register.
222 | */
223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 | {
225 | MPU->RBAR = rbar;
226 | MPU->RASR = rasr;
227 | }
228 |
229 | /** Configure the given MPU region.
230 | * \param rnr Region number to be configured.
231 | * \param rbar Value for RBAR register.
232 | * \param rsar Value for RSAR register.
233 | */
234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 | {
236 | MPU->RNR = rnr;
237 | MPU->RBAR = rbar;
238 | MPU->RASR = rasr;
239 | }
240 |
241 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
242 | * \param dst Destination data is copied to.
243 | * \param src Source data is copied from.
244 | * \param len Amount of data words to be copied.
245 | */
246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 | {
248 | uint32_t i;
249 | for (i = 0U; i < len; ++i)
250 | {
251 | dst[i] = src[i];
252 | }
253 | }
254 |
255 | /** Load the given number of MPU regions from a table.
256 | * \param table Pointer to the MPU configuration table.
257 | * \param cnt Amount of regions to be configured.
258 | */
259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 | {
261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262 | while (cnt > MPU_TYPE_RALIASES) {
263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 | table += MPU_TYPE_RALIASES;
265 | cnt -= MPU_TYPE_RALIASES;
266 | }
267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 | }
269 |
270 | #endif
271 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_gpio.h
4 | * @author MCD Application Team
5 | * @brief Header file of GPIO HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file
13 | * in the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 |
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef STM32F1xx_HAL_GPIO_H
21 | #define STM32F1xx_HAL_GPIO_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "stm32f1xx_hal_def.h"
29 |
30 | /** @addtogroup STM32F1xx_HAL_Driver
31 | * @{
32 | */
33 |
34 | /** @addtogroup GPIO
35 | * @{
36 | */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /** @defgroup GPIO_Exported_Types GPIO Exported Types
40 | * @{
41 | */
42 |
43 | /**
44 | * @brief GPIO Init structure definition
45 | */
46 | typedef struct
47 | {
48 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
49 | This parameter can be any value of @ref GPIO_pins_define */
50 |
51 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
52 | This parameter can be a value of @ref GPIO_mode_define */
53 |
54 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
55 | This parameter can be a value of @ref GPIO_pull_define */
56 |
57 | uint32_t Speed; /*!< Specifies the speed for the selected pins.
58 | This parameter can be a value of @ref GPIO_speed_define */
59 | } GPIO_InitTypeDef;
60 |
61 | /**
62 | * @brief GPIO Bit SET and Bit RESET enumeration
63 | */
64 | typedef enum
65 | {
66 | GPIO_PIN_RESET = 0u,
67 | GPIO_PIN_SET
68 | } GPIO_PinState;
69 | /**
70 | * @}
71 | */
72 |
73 | /* Exported constants --------------------------------------------------------*/
74 |
75 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
76 | * @{
77 | */
78 |
79 | /** @defgroup GPIO_pins_define GPIO pins define
80 | * @{
81 | */
82 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
83 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
84 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
85 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
86 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
87 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
88 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
89 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
90 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
91 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
92 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
93 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
94 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
95 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
96 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
97 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
98 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
99 |
100 | #define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */
101 | /**
102 | * @}
103 | */
104 |
105 | /** @defgroup GPIO_mode_define GPIO mode define
106 | * @brief GPIO Configuration Mode
107 | * Elements values convention: 0xX0yz00YZ
108 | * - X : GPIO mode or EXTI Mode
109 | * - y : External IT or Event trigger detection
110 | * - z : IO configuration on External IT or Event
111 | * - Y : Output type (Push Pull or Open Drain)
112 | * - Z : IO Direction mode (Input, Output, Alternate or Analog)
113 | * @{
114 | */
115 | #define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */
116 | #define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */
117 | #define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */
118 | #define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */
119 | #define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */
120 | #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
121 |
122 | #define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */
123 |
124 | #define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */
125 | #define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */
126 | #define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
127 |
128 | #define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */
129 | #define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */
130 | #define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */
131 |
132 | /**
133 | * @}
134 | */
135 |
136 | /** @defgroup GPIO_speed_define GPIO speed define
137 | * @brief GPIO Output Maximum frequency
138 | * @{
139 | */
140 | #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
141 | #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
142 | #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
143 |
144 | /**
145 | * @}
146 | */
147 |
148 | /** @defgroup GPIO_pull_define GPIO pull define
149 | * @brief GPIO Pull-Up or Pull-Down Activation
150 | * @{
151 | */
152 | #define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
153 | #define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
154 | #define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
155 | /**
156 | * @}
157 | */
158 |
159 | /**
160 | * @}
161 | */
162 |
163 | /* Exported macro ------------------------------------------------------------*/
164 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
165 | * @{
166 | */
167 |
168 | /**
169 | * @brief Checks whether the specified EXTI line flag is set or not.
170 | * @param __EXTI_LINE__: specifies the EXTI line flag to check.
171 | * This parameter can be GPIO_PIN_x where x can be(0..15)
172 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
173 | */
174 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
175 |
176 | /**
177 | * @brief Clears the EXTI's line pending flags.
178 | * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
179 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
180 | * @retval None
181 | */
182 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
183 |
184 | /**
185 | * @brief Checks whether the specified EXTI line is asserted or not.
186 | * @param __EXTI_LINE__: specifies the EXTI line to check.
187 | * This parameter can be GPIO_PIN_x where x can be(0..15)
188 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
189 | */
190 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
191 |
192 | /**
193 | * @brief Clears the EXTI's line pending bits.
194 | * @param __EXTI_LINE__: specifies the EXTI lines to clear.
195 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
196 | * @retval None
197 | */
198 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
199 |
200 | /**
201 | * @brief Generates a Software interrupt on selected EXTI line.
202 | * @param __EXTI_LINE__: specifies the EXTI line to check.
203 | * This parameter can be GPIO_PIN_x where x can be(0..15)
204 | * @retval None
205 | */
206 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
207 | /**
208 | * @}
209 | */
210 |
211 | /* Include GPIO HAL Extension module */
212 | #include "stm32f1xx_hal_gpio_ex.h"
213 |
214 | /* Exported functions --------------------------------------------------------*/
215 | /** @addtogroup GPIO_Exported_Functions
216 | * @{
217 | */
218 |
219 | /** @addtogroup GPIO_Exported_Functions_Group1
220 | * @{
221 | */
222 | /* Initialization and de-initialization functions *****************************/
223 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
224 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
225 | /**
226 | * @}
227 | */
228 |
229 | /** @addtogroup GPIO_Exported_Functions_Group2
230 | * @{
231 | */
232 | /* IO operation functions *****************************************************/
233 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
234 | void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
235 | void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
236 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
237 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
238 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
239 |
240 | /**
241 | * @}
242 | */
243 |
244 | /**
245 | * @}
246 | */
247 | /* Private types -------------------------------------------------------------*/
248 | /* Private variables ---------------------------------------------------------*/
249 | /* Private constants ---------------------------------------------------------*/
250 | /** @defgroup GPIO_Private_Constants GPIO Private Constants
251 | * @{
252 | */
253 |
254 | /**
255 | * @}
256 | */
257 |
258 | /* Private macros ------------------------------------------------------------*/
259 | /** @defgroup GPIO_Private_Macros GPIO Private Macros
260 | * @{
261 | */
262 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
263 | #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u))
264 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
265 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
266 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
267 | ((MODE) == GPIO_MODE_AF_PP) ||\
268 | ((MODE) == GPIO_MODE_AF_OD) ||\
269 | ((MODE) == GPIO_MODE_IT_RISING) ||\
270 | ((MODE) == GPIO_MODE_IT_FALLING) ||\
271 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
272 | ((MODE) == GPIO_MODE_EVT_RISING) ||\
273 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\
274 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
275 | ((MODE) == GPIO_MODE_ANALOG))
276 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
277 | ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
278 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
279 | ((PULL) == GPIO_PULLDOWN))
280 | /**
281 | * @}
282 | */
283 |
284 | /* Private functions ---------------------------------------------------------*/
285 | /** @defgroup GPIO_Private_Functions GPIO Private Functions
286 | * @{
287 | */
288 |
289 | /**
290 | * @}
291 | */
292 |
293 | /**
294 | * @}
295 | */
296 |
297 | /**
298 | * @}
299 | */
300 |
301 | #ifdef __cplusplus
302 | }
303 | #endif
304 |
305 | #endif /* STM32F1xx_HAL_GPIO_H */
306 |
307 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_exti.h
4 | * @author MCD Application Team
5 | * @brief Header file of EXTI HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file
13 | * in the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 |
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef STM32F1xx_HAL_EXTI_H
21 | #define STM32F1xx_HAL_EXTI_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "stm32f1xx_hal_def.h"
29 |
30 | /** @addtogroup STM32F1xx_HAL_Driver
31 | * @{
32 | */
33 |
34 | /** @defgroup EXTI EXTI
35 | * @brief EXTI HAL module driver
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 |
41 | /** @defgroup EXTI_Exported_Types EXTI Exported Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief HAL EXTI common Callback ID enumeration definition
47 | */
48 | typedef enum
49 | {
50 | HAL_EXTI_COMMON_CB_ID = 0x00U
51 | } EXTI_CallbackIDTypeDef;
52 |
53 | /**
54 | * @brief EXTI Handle structure definition
55 | */
56 | typedef struct
57 | {
58 | uint32_t Line; /*!< Exti line number */
59 | void (* PendingCallback)(void); /*!< Exti pending callback */
60 | } EXTI_HandleTypeDef;
61 |
62 | /**
63 | * @brief EXTI Configuration structure definition
64 | */
65 | typedef struct
66 | {
67 | uint32_t Line; /*!< The Exti line to be configured. This parameter
68 | can be a value of @ref EXTI_Line */
69 | uint32_t Mode; /*!< The Exit Mode to be configured for a core.
70 | This parameter can be a combination of @ref EXTI_Mode */
71 | uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
72 | can be a value of @ref EXTI_Trigger */
73 | uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
74 | This parameter is only possible for line 0 to 15. It
75 | can be a value of @ref EXTI_GPIOSel */
76 | } EXTI_ConfigTypeDef;
77 |
78 | /**
79 | * @}
80 | */
81 |
82 | /* Exported constants --------------------------------------------------------*/
83 | /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
84 | * @{
85 | */
86 |
87 | /** @defgroup EXTI_Line EXTI Line
88 | * @{
89 | */
90 | #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
91 | #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
92 | #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
93 | #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
94 | #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
95 | #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
96 | #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
97 | #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
98 | #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
99 | #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
100 | #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
101 | #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
102 | #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
103 | #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
104 | #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
105 | #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
106 | #define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
107 | #define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
108 | #if defined(EXTI_IMR_IM18)
109 | #define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */
110 | #endif /* EXTI_IMR_IM18 */
111 | #if defined(EXTI_IMR_IM19)
112 | #define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
113 | #endif /* EXTI_IMR_IM19 */
114 |
115 | /**
116 | * @}
117 | */
118 |
119 | /** @defgroup EXTI_Mode EXTI Mode
120 | * @{
121 | */
122 | #define EXTI_MODE_NONE 0x00000000u
123 | #define EXTI_MODE_INTERRUPT 0x00000001u
124 | #define EXTI_MODE_EVENT 0x00000002u
125 | /**
126 | * @}
127 | */
128 |
129 | /** @defgroup EXTI_Trigger EXTI Trigger
130 | * @{
131 | */
132 | #define EXTI_TRIGGER_NONE 0x00000000u
133 | #define EXTI_TRIGGER_RISING 0x00000001u
134 | #define EXTI_TRIGGER_FALLING 0x00000002u
135 | #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
136 | /**
137 | * @}
138 | */
139 |
140 | /** @defgroup EXTI_GPIOSel EXTI GPIOSel
141 | * @brief
142 | * @{
143 | */
144 | #define EXTI_GPIOA 0x00000000u
145 | #define EXTI_GPIOB 0x00000001u
146 | #define EXTI_GPIOC 0x00000002u
147 | #define EXTI_GPIOD 0x00000003u
148 | #if defined (GPIOE)
149 | #define EXTI_GPIOE 0x00000004u
150 | #endif /* GPIOE */
151 | #if defined (GPIOF)
152 | #define EXTI_GPIOF 0x00000005u
153 | #endif /* GPIOF */
154 | #if defined (GPIOG)
155 | #define EXTI_GPIOG 0x00000006u
156 | #endif /* GPIOG */
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | /* Exported macro ------------------------------------------------------------*/
166 | /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
167 | * @{
168 | */
169 |
170 | /**
171 | * @}
172 | */
173 |
174 | /* Private constants --------------------------------------------------------*/
175 | /** @defgroup EXTI_Private_Constants EXTI Private Constants
176 | * @{
177 | */
178 | /**
179 | * @brief EXTI Line property definition
180 | */
181 | #define EXTI_PROPERTY_SHIFT 24u
182 | #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
183 | #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
184 | #define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
185 |
186 | /**
187 | * @brief EXTI bit usage
188 | */
189 | #define EXTI_PIN_MASK 0x0000001Fu
190 |
191 | /**
192 | * @brief EXTI Mask for interrupt & event mode
193 | */
194 | #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
195 |
196 | /**
197 | * @brief EXTI Mask for trigger possibilities
198 | */
199 | #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
200 |
201 | /**
202 | * @brief EXTI Line number
203 | */
204 | #if defined(EXTI_IMR_IM19)
205 | #define EXTI_LINE_NB 20UL
206 | #elif defined(EXTI_IMR_IM18)
207 | #define EXTI_LINE_NB 19UL
208 | #else /* EXTI_IMR_IM17 */
209 | #define EXTI_LINE_NB 18UL
210 | #endif /* EXTI_IMR_IM19 */
211 | /**
212 | * @}
213 | */
214 |
215 | /* Private macros ------------------------------------------------------------*/
216 | /** @defgroup EXTI_Private_Macros EXTI Private Macros
217 | * @{
218 | */
219 | #define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
220 | ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
221 | (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
222 | (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
223 |
224 | #define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
225 | (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
226 |
227 | #define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
228 |
229 | #define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
230 |
231 | #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
232 |
233 | #if defined (GPIOG)
234 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
235 | ((__PORT__) == EXTI_GPIOB) || \
236 | ((__PORT__) == EXTI_GPIOC) || \
237 | ((__PORT__) == EXTI_GPIOD) || \
238 | ((__PORT__) == EXTI_GPIOE) || \
239 | ((__PORT__) == EXTI_GPIOF) || \
240 | ((__PORT__) == EXTI_GPIOG))
241 | #elif defined (GPIOF)
242 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
243 | ((__PORT__) == EXTI_GPIOB) || \
244 | ((__PORT__) == EXTI_GPIOC) || \
245 | ((__PORT__) == EXTI_GPIOD) || \
246 | ((__PORT__) == EXTI_GPIOE) || \
247 | ((__PORT__) == EXTI_GPIOF))
248 | #elif defined (GPIOE)
249 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
250 | ((__PORT__) == EXTI_GPIOB) || \
251 | ((__PORT__) == EXTI_GPIOC) || \
252 | ((__PORT__) == EXTI_GPIOD) || \
253 | ((__PORT__) == EXTI_GPIOE))
254 | #else
255 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
256 | ((__PORT__) == EXTI_GPIOB) || \
257 | ((__PORT__) == EXTI_GPIOC) || \
258 | ((__PORT__) == EXTI_GPIOD))
259 | #endif /* GPIOG */
260 |
261 | #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
262 |
263 | /**
264 | * @}
265 | */
266 |
267 | /* Exported functions --------------------------------------------------------*/
268 | /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
269 | * @brief EXTI Exported Functions
270 | * @{
271 | */
272 |
273 | /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
274 | * @brief Configuration functions
275 | * @{
276 | */
277 | /* Configuration functions ****************************************************/
278 | HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
279 | HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
280 | HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
281 | HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
282 | HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
283 | /**
284 | * @}
285 | */
286 |
287 | /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
288 | * @brief IO operation functions
289 | * @{
290 | */
291 | /* IO operation functions *****************************************************/
292 | void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
293 | uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
294 | void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
295 | void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
296 |
297 | /**
298 | * @}
299 | */
300 |
301 | /**
302 | * @}
303 | */
304 |
305 | /**
306 | * @}
307 | */
308 |
309 | /**
310 | * @}
311 | */
312 |
313 | #ifdef __cplusplus
314 | }
315 | #endif
316 |
317 | #endif /* STM32F1xx_HAL_EXTI_H */
318 |
319 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_pwr.h
4 | * @author MCD Application Team
5 | * @brief Header file of PWR HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file
13 | * in the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 |
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __STM32F1xx_HAL_PWR_H
21 | #define __STM32F1xx_HAL_PWR_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "stm32f1xx_hal_def.h"
29 |
30 | /** @addtogroup STM32F1xx_HAL_Driver
31 | * @{
32 | */
33 |
34 | /** @addtogroup PWR
35 | * @{
36 | */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 |
40 | /** @defgroup PWR_Exported_Types PWR Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief PWR PVD configuration structure definition
46 | */
47 | typedef struct
48 | {
49 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
50 | This parameter can be a value of @ref PWR_PVD_detection_level */
51 |
52 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
53 | This parameter can be a value of @ref PWR_PVD_Mode */
54 | }PWR_PVDTypeDef;
55 |
56 |
57 | /**
58 | * @}
59 | */
60 |
61 |
62 | /* Internal constants --------------------------------------------------------*/
63 |
64 | /** @addtogroup PWR_Private_Constants
65 | * @{
66 | */
67 |
68 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 |
75 | /* Exported constants --------------------------------------------------------*/
76 |
77 | /** @defgroup PWR_Exported_Constants PWR Exported Constants
78 | * @{
79 | */
80 |
81 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level
82 | * @{
83 | */
84 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
85 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
86 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
87 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
88 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
89 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
90 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
91 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
92 |
93 | /**
94 | * @}
95 | */
96 |
97 | /** @defgroup PWR_PVD_Mode PWR PVD Mode
98 | * @{
99 | */
100 | #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
101 | #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
102 | #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
103 | #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
104 | #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
105 | #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
106 | #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
107 |
108 | /**
109 | * @}
110 | */
111 |
112 |
113 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
114 | * @{
115 | */
116 |
117 | #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
118 |
119 | /**
120 | * @}
121 | */
122 |
123 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
124 | * @{
125 | */
126 | #define PWR_MAINREGULATOR_ON 0x00000000U
127 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
128 |
129 | /**
130 | * @}
131 | */
132 |
133 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
134 | * @{
135 | */
136 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
137 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
138 |
139 | /**
140 | * @}
141 | */
142 |
143 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
144 | * @{
145 | */
146 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
147 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
148 |
149 | /**
150 | * @}
151 | */
152 |
153 | /** @defgroup PWR_Flag PWR Flag
154 | * @{
155 | */
156 | #define PWR_FLAG_WU PWR_CSR_WUF
157 | #define PWR_FLAG_SB PWR_CSR_SBF
158 | #define PWR_FLAG_PVDO PWR_CSR_PVDO
159 |
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | /**
166 | * @}
167 | */
168 |
169 | /* Exported macro ------------------------------------------------------------*/
170 | /** @defgroup PWR_Exported_Macros PWR Exported Macros
171 | * @{
172 | */
173 |
174 | /** @brief Check PWR flag is set or not.
175 | * @param __FLAG__: specifies the flag to check.
176 | * This parameter can be one of the following values:
177 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
178 | * was received from the WKUP pin or from the RTC alarm
179 | * An additional wakeup event is detected if the WKUP pin is enabled
180 | * (by setting the EWUP bit) when the WKUP pin level is already high.
181 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
182 | * resumed from StandBy mode.
183 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
184 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
185 | * For this reason, this bit is equal to 0 after Standby or reset
186 | * until the PVDE bit is set.
187 | * @retval The new state of __FLAG__ (TRUE or FALSE).
188 | */
189 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
190 |
191 | /** @brief Clear the PWR's pending flags.
192 | * @param __FLAG__: specifies the flag to clear.
193 | * This parameter can be one of the following values:
194 | * @arg PWR_FLAG_WU: Wake Up flag
195 | * @arg PWR_FLAG_SB: StandBy flag
196 | */
197 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
198 |
199 | /**
200 | * @brief Enable interrupt on PVD Exti Line 16.
201 | * @retval None.
202 | */
203 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
204 |
205 | /**
206 | * @brief Disable interrupt on PVD Exti Line 16.
207 | * @retval None.
208 | */
209 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
210 |
211 | /**
212 | * @brief Enable event on PVD Exti Line 16.
213 | * @retval None.
214 | */
215 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
216 |
217 | /**
218 | * @brief Disable event on PVD Exti Line 16.
219 | * @retval None.
220 | */
221 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
222 |
223 |
224 | /**
225 | * @brief PVD EXTI line configuration: set falling edge trigger.
226 | * @retval None.
227 | */
228 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
229 |
230 |
231 | /**
232 | * @brief Disable the PVD Extended Interrupt Falling Trigger.
233 | * @retval None.
234 | */
235 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
236 |
237 |
238 | /**
239 | * @brief PVD EXTI line configuration: set rising edge trigger.
240 | * @retval None.
241 | */
242 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
243 |
244 | /**
245 | * @brief Disable the PVD Extended Interrupt Rising Trigger.
246 | * This parameter can be:
247 | * @retval None.
248 | */
249 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
250 |
251 | /**
252 | * @brief PVD EXTI line configuration: set rising & falling edge trigger.
253 | * @retval None.
254 | */
255 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
256 |
257 | /**
258 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
259 | * This parameter can be:
260 | * @retval None.
261 | */
262 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
263 |
264 |
265 |
266 | /**
267 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
268 | * @retval EXTI PVD Line Status.
269 | */
270 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
271 |
272 | /**
273 | * @brief Clear the PVD EXTI flag.
274 | * @retval None.
275 | */
276 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
277 |
278 | /**
279 | * @brief Generate a Software interrupt on selected EXTI line.
280 | * @retval None.
281 | */
282 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
283 | /**
284 | * @}
285 | */
286 |
287 | /* Private macro -------------------------------------------------------------*/
288 | /** @defgroup PWR_Private_Macros PWR Private Macros
289 | * @{
290 | */
291 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
292 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
293 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
294 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
295 |
296 |
297 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
298 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
299 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
300 | ((MODE) == PWR_PVD_MODE_NORMAL))
301 |
302 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
303 |
304 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
305 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
306 |
307 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
308 |
309 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
310 |
311 | /**
312 | * @}
313 | */
314 |
315 |
316 |
317 | /* Exported functions --------------------------------------------------------*/
318 |
319 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions
320 | * @{
321 | */
322 |
323 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
324 | * @{
325 | */
326 |
327 | /* Initialization and de-initialization functions *******************************/
328 | void HAL_PWR_DeInit(void);
329 | void HAL_PWR_EnableBkUpAccess(void);
330 | void HAL_PWR_DisableBkUpAccess(void);
331 |
332 | /**
333 | * @}
334 | */
335 |
336 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
337 | * @{
338 | */
339 |
340 | /* Peripheral Control functions ************************************************/
341 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
342 | /* #define HAL_PWR_ConfigPVD 12*/
343 | void HAL_PWR_EnablePVD(void);
344 | void HAL_PWR_DisablePVD(void);
345 |
346 | /* WakeUp pins configuration functions ****************************************/
347 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
348 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
349 |
350 | /* Low Power modes configuration functions ************************************/
351 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
352 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
353 | void HAL_PWR_EnterSTANDBYMode(void);
354 |
355 | void HAL_PWR_EnableSleepOnExit(void);
356 | void HAL_PWR_DisableSleepOnExit(void);
357 | void HAL_PWR_EnableSEVOnPend(void);
358 | void HAL_PWR_DisableSEVOnPend(void);
359 |
360 |
361 |
362 | void HAL_PWR_PVD_IRQHandler(void);
363 | void HAL_PWR_PVDCallback(void);
364 | /**
365 | * @}
366 | */
367 |
368 | /**
369 | * @}
370 | */
371 |
372 | /**
373 | * @}
374 | */
375 |
376 | /**
377 | * @}
378 | */
379 |
380 | #ifdef __cplusplus
381 | }
382 | #endif
383 |
384 |
385 | #endif /* __STM32F1xx_HAL_PWR_H */
386 |
--------------------------------------------------------------------------------
/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_dma_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of DMA HAL extension module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file in
13 | * the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 |
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __STM32F1xx_HAL_DMA_EX_H
21 | #define __STM32F1xx_HAL_DMA_EX_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "stm32f1xx_hal_def.h"
29 |
30 | /** @addtogroup STM32F1xx_HAL_Driver
31 | * @{
32 | */
33 |
34 | /** @defgroup DMAEx DMAEx
35 | * @{
36 | */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* Exported constants --------------------------------------------------------*/
40 | /* Exported macro ------------------------------------------------------------*/
41 | /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
42 | * @{
43 | */
44 | /* Interrupt & Flag management */
45 | #if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
46 | defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
47 | /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
48 | * @{
49 | */
50 |
51 | /**
52 | * @brief Returns the current DMA Channel transfer complete flag.
53 | * @param __HANDLE__: DMA handle
54 | * @retval The specified transfer complete flag index.
55 | */
56 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
57 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
58 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
59 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
60 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
61 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
62 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
63 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
64 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
65 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
66 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
67 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
68 | DMA_FLAG_TC5)
69 |
70 | /**
71 | * @brief Returns the current DMA Channel half transfer complete flag.
72 | * @param __HANDLE__: DMA handle
73 | * @retval The specified half transfer complete flag index.
74 | */
75 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
76 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
77 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
78 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
79 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
80 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
81 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
82 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
83 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
84 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
85 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
86 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
87 | DMA_FLAG_HT5)
88 |
89 | /**
90 | * @brief Returns the current DMA Channel transfer error flag.
91 | * @param __HANDLE__: DMA handle
92 | * @retval The specified transfer error flag index.
93 | */
94 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
95 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
96 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
97 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
98 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
99 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
100 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
101 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
102 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
103 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
104 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
105 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
106 | DMA_FLAG_TE5)
107 |
108 | /**
109 | * @brief Return the current DMA Channel Global interrupt flag.
110 | * @param __HANDLE__: DMA handle
111 | * @retval The specified transfer error flag index.
112 | */
113 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
114 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
115 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
116 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
117 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
118 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
119 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
120 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
121 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
122 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
123 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
124 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
125 | DMA_FLAG_GL5)
126 |
127 | /**
128 | * @brief Get the DMA Channel pending flags.
129 | * @param __HANDLE__: DMA handle
130 | * @param __FLAG__: Get the specified flag.
131 | * This parameter can be any combination of the following values:
132 | * @arg DMA_FLAG_TCx: Transfer complete flag
133 | * @arg DMA_FLAG_HTx: Half transfer complete flag
134 | * @arg DMA_FLAG_TEx: Transfer error flag
135 | * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
136 | * @retval The state of FLAG (SET or RESET).
137 | */
138 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
139 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
140 | (DMA1->ISR & (__FLAG__)))
141 |
142 | /**
143 | * @brief Clears the DMA Channel pending flags.
144 | * @param __HANDLE__: DMA handle
145 | * @param __FLAG__: specifies the flag to clear.
146 | * This parameter can be any combination of the following values:
147 | * @arg DMA_FLAG_TCx: Transfer complete flag
148 | * @arg DMA_FLAG_HTx: Half transfer complete flag
149 | * @arg DMA_FLAG_TEx: Transfer error flag
150 | * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
151 | * @retval None
152 | */
153 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
154 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
155 | (DMA1->IFCR = (__FLAG__)))
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | #else
162 | /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
163 | * @{
164 | */
165 |
166 | /**
167 | * @brief Returns the current DMA Channel transfer complete flag.
168 | * @param __HANDLE__: DMA handle
169 | * @retval The specified transfer complete flag index.
170 | */
171 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
172 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
173 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
174 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
175 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
176 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
177 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
178 | DMA_FLAG_TC7)
179 |
180 | /**
181 | * @brief Return the current DMA Channel half transfer complete flag.
182 | * @param __HANDLE__: DMA handle
183 | * @retval The specified half transfer complete flag index.
184 | */
185 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
186 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
187 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
188 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
189 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
190 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
191 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
192 | DMA_FLAG_HT7)
193 |
194 | /**
195 | * @brief Return the current DMA Channel transfer error flag.
196 | * @param __HANDLE__: DMA handle
197 | * @retval The specified transfer error flag index.
198 | */
199 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
200 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
201 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
202 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
203 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
204 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
205 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
206 | DMA_FLAG_TE7)
207 |
208 | /**
209 | * @brief Return the current DMA Channel Global interrupt flag.
210 | * @param __HANDLE__: DMA handle
211 | * @retval The specified transfer error flag index.
212 | */
213 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
214 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
215 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
216 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
217 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
218 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
219 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
220 | DMA_FLAG_GL7)
221 |
222 | /**
223 | * @brief Get the DMA Channel pending flags.
224 | * @param __HANDLE__: DMA handle
225 | * @param __FLAG__: Get the specified flag.
226 | * This parameter can be any combination of the following values:
227 | * @arg DMA_FLAG_TCx: Transfer complete flag
228 | * @arg DMA_FLAG_HTx: Half transfer complete flag
229 | * @arg DMA_FLAG_TEx: Transfer error flag
230 | * @arg DMA_FLAG_GLx: Global interrupt flag
231 | * Where x can be 1_7 to select the DMA Channel flag.
232 | * @retval The state of FLAG (SET or RESET).
233 | */
234 |
235 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
236 |
237 | /**
238 | * @brief Clear the DMA Channel pending flags.
239 | * @param __HANDLE__: DMA handle
240 | * @param __FLAG__: specifies the flag to clear.
241 | * This parameter can be any combination of the following values:
242 | * @arg DMA_FLAG_TCx: Transfer complete flag
243 | * @arg DMA_FLAG_HTx: Half transfer complete flag
244 | * @arg DMA_FLAG_TEx: Transfer error flag
245 | * @arg DMA_FLAG_GLx: Global interrupt flag
246 | * Where x can be 1_7 to select the DMA Channel flag.
247 | * @retval None
248 | */
249 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
250 |
251 | /**
252 | * @}
253 | */
254 |
255 | #endif
256 |
257 | /**
258 | * @}
259 | */
260 |
261 | /**
262 | * @}
263 | */
264 |
265 | /**
266 | * @}
267 | */
268 |
269 | #ifdef __cplusplus
270 | }
271 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
272 | /* STM32F103xG || STM32F105xC || STM32F107xC */
273 |
274 | #endif /* __STM32F1xx_HAL_DMA_H */
275 |
276 |
--------------------------------------------------------------------------------
/Core/Src/system_stm32f1xx.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f1xx.c
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6 | *
7 | * 1. This file provides two functions and one global variable to be called from
8 | * user application:
9 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
10 | * factors, AHB/APBx prescalers and Flash settings).
11 | * This function is called at startup just after reset and
12 | * before branch to main program. This call is made inside
13 | * the "startup_stm32f1xx_xx.s" file.
14 | *
15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 | * by the user application to setup the SysTick
17 | * timer or configure other parameters.
18 | *
19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 | * be called whenever the core clock is changed
21 | * during program execution.
22 | *
23 | * 2. After each device reset the HSI (8 MHz) is used as system clock source.
24 | * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
25 | * configure the system clock before to branch to main program.
26 | *
27 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
28 | * the product used), refer to "HSE_VALUE".
29 | * When HSE is used as system clock source, directly or through PLL, and you
30 | * are using different crystal you have to adapt the HSE value to your own
31 | * configuration.
32 | *
33 | ******************************************************************************
34 | * @attention
35 | *
36 | * Copyright (c) 2017-2021 STMicroelectronics.
37 | * All rights reserved.
38 | *
39 | * This software is licensed under terms that can be found in the LICENSE file
40 | * in the root directory of this software component.
41 | * If no LICENSE file comes with this software, it is provided AS-IS.
42 | *
43 | ******************************************************************************
44 | */
45 |
46 | /** @addtogroup CMSIS
47 | * @{
48 | */
49 |
50 | /** @addtogroup stm32f1xx_system
51 | * @{
52 | */
53 |
54 | /** @addtogroup STM32F1xx_System_Private_Includes
55 | * @{
56 | */
57 |
58 | #include "stm32f1xx.h"
59 |
60 | /**
61 | * @}
62 | */
63 |
64 | /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
65 | * @{
66 | */
67 |
68 | /**
69 | * @}
70 | */
71 |
72 | /** @addtogroup STM32F1xx_System_Private_Defines
73 | * @{
74 | */
75 |
76 | #if !defined (HSE_VALUE)
77 | #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
78 | This value can be provided and adapted by the user application. */
79 | #endif /* HSE_VALUE */
80 |
81 | #if !defined (HSI_VALUE)
82 | #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
83 | This value can be provided and adapted by the user application. */
84 | #endif /* HSI_VALUE */
85 |
86 | /*!< Uncomment the following line if you need to use external SRAM */
87 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
88 | /* #define DATA_IN_ExtSRAM */
89 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
90 |
91 | /* Note: Following vector table addresses must be defined in line with linker
92 | configuration. */
93 | /*!< Uncomment the following line if you need to relocate the vector table
94 | anywhere in Flash or Sram, else the vector table is kept at the automatic
95 | remap of boot address selected */
96 | /* #define USER_VECT_TAB_ADDRESS */
97 |
98 | #if defined(USER_VECT_TAB_ADDRESS)
99 | /*!< Uncomment the following line if you need to relocate your vector Table
100 | in Sram else user remap will be done in Flash. */
101 | /* #define VECT_TAB_SRAM */
102 | #if defined(VECT_TAB_SRAM)
103 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
104 | This value must be a multiple of 0x200. */
105 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
106 | This value must be a multiple of 0x200. */
107 | #else
108 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
109 | This value must be a multiple of 0x200. */
110 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
111 | This value must be a multiple of 0x200. */
112 | #endif /* VECT_TAB_SRAM */
113 | #endif /* USER_VECT_TAB_ADDRESS */
114 |
115 | /******************************************************************************/
116 |
117 | /**
118 | * @}
119 | */
120 |
121 | /** @addtogroup STM32F1xx_System_Private_Macros
122 | * @{
123 | */
124 |
125 | /**
126 | * @}
127 | */
128 |
129 | /** @addtogroup STM32F1xx_System_Private_Variables
130 | * @{
131 | */
132 |
133 | /* This variable is updated in three ways:
134 | 1) by calling CMSIS function SystemCoreClockUpdate()
135 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
136 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
137 | Note: If you use this function to configure the system clock; then there
138 | is no need to call the 2 first functions listed above, since SystemCoreClock
139 | variable is updated automatically.
140 | */
141 | uint32_t SystemCoreClock = 16000000;
142 | const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
143 | const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
144 |
145 | /**
146 | * @}
147 | */
148 |
149 | /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
150 | * @{
151 | */
152 |
153 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
154 | #ifdef DATA_IN_ExtSRAM
155 | static void SystemInit_ExtMemCtl(void);
156 | #endif /* DATA_IN_ExtSRAM */
157 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
158 |
159 | /**
160 | * @}
161 | */
162 |
163 | /** @addtogroup STM32F1xx_System_Private_Functions
164 | * @{
165 | */
166 |
167 | /**
168 | * @brief Setup the microcontroller system
169 | * Initialize the Embedded Flash Interface, the PLL and update the
170 | * SystemCoreClock variable.
171 | * @note This function should be used only after reset.
172 | * @param None
173 | * @retval None
174 | */
175 | void SystemInit (void)
176 | {
177 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
178 | #ifdef DATA_IN_ExtSRAM
179 | SystemInit_ExtMemCtl();
180 | #endif /* DATA_IN_ExtSRAM */
181 | #endif
182 |
183 | /* Configure the Vector Table location -------------------------------------*/
184 | #if defined(USER_VECT_TAB_ADDRESS)
185 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
186 | #endif /* USER_VECT_TAB_ADDRESS */
187 | }
188 |
189 | /**
190 | * @brief Update SystemCoreClock variable according to Clock Register Values.
191 | * The SystemCoreClock variable contains the core clock (HCLK), it can
192 | * be used by the user application to setup the SysTick timer or configure
193 | * other parameters.
194 | *
195 | * @note Each time the core clock (HCLK) changes, this function must be called
196 | * to update SystemCoreClock variable value. Otherwise, any configuration
197 | * based on this variable will be incorrect.
198 | *
199 | * @note - The system frequency computed by this function is not the real
200 | * frequency in the chip. It is calculated based on the predefined
201 | * constant and the selected clock source:
202 | *
203 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
204 | *
205 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
206 | *
207 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
208 | * or HSI_VALUE(*) multiplied by the PLL factors.
209 | *
210 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
211 | * 8 MHz) but the real value may vary depending on the variations
212 | * in voltage and temperature.
213 | *
214 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
215 | * 8 MHz or 25 MHz, depending on the product used), user has to ensure
216 | * that HSE_VALUE is same as the real frequency of the crystal used.
217 | * Otherwise, this function may have wrong result.
218 | *
219 | * - The result of this function could be not correct when using fractional
220 | * value for HSE crystal.
221 | * @param None
222 | * @retval None
223 | */
224 | void SystemCoreClockUpdate (void)
225 | {
226 | uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
227 |
228 | #if defined(STM32F105xC) || defined(STM32F107xC)
229 | uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
230 | #endif /* STM32F105xC */
231 |
232 | #if defined(STM32F100xB) || defined(STM32F100xE)
233 | uint32_t prediv1factor = 0U;
234 | #endif /* STM32F100xB or STM32F100xE */
235 |
236 | /* Get SYSCLK source -------------------------------------------------------*/
237 | tmp = RCC->CFGR & RCC_CFGR_SWS;
238 |
239 | switch (tmp)
240 | {
241 | case 0x00U: /* HSI used as system clock */
242 | SystemCoreClock = HSI_VALUE;
243 | break;
244 | case 0x04U: /* HSE used as system clock */
245 | SystemCoreClock = HSE_VALUE;
246 | break;
247 | case 0x08U: /* PLL used as system clock */
248 |
249 | /* Get PLL clock source and multiplication factor ----------------------*/
250 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
251 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
252 |
253 | #if !defined(STM32F105xC) && !defined(STM32F107xC)
254 | pllmull = ( pllmull >> 18U) + 2U;
255 |
256 | if (pllsource == 0x00U)
257 | {
258 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
259 | SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
260 | }
261 | else
262 | {
263 | #if defined(STM32F100xB) || defined(STM32F100xE)
264 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
265 | /* HSE oscillator clock selected as PREDIV1 clock entry */
266 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
267 | #else
268 | /* HSE selected as PLL clock entry */
269 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
270 | {/* HSE oscillator clock divided by 2 */
271 | SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
272 | }
273 | else
274 | {
275 | SystemCoreClock = HSE_VALUE * pllmull;
276 | }
277 | #endif
278 | }
279 | #else
280 | pllmull = pllmull >> 18U;
281 |
282 | if (pllmull != 0x0DU)
283 | {
284 | pllmull += 2U;
285 | }
286 | else
287 | { /* PLL multiplication factor = PLL input clock * 6.5 */
288 | pllmull = 13U / 2U;
289 | }
290 |
291 | if (pllsource == 0x00U)
292 | {
293 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
294 | SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
295 | }
296 | else
297 | {/* PREDIV1 selected as PLL clock entry */
298 |
299 | /* Get PREDIV1 clock source and division factor */
300 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
301 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
302 |
303 | if (prediv1source == 0U)
304 | {
305 | /* HSE oscillator clock selected as PREDIV1 clock entry */
306 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
307 | }
308 | else
309 | {/* PLL2 clock selected as PREDIV1 clock entry */
310 |
311 | /* Get PREDIV2 division factor and PLL2 multiplication factor */
312 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
313 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
314 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
315 | }
316 | }
317 | #endif /* STM32F105xC */
318 | break;
319 |
320 | default:
321 | SystemCoreClock = HSI_VALUE;
322 | break;
323 | }
324 |
325 | /* Compute HCLK clock frequency ----------------*/
326 | /* Get HCLK prescaler */
327 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
328 | /* HCLK clock frequency */
329 | SystemCoreClock >>= tmp;
330 | }
331 |
332 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
333 | /**
334 | * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
335 | * before jump to __main
336 | * @param None
337 | * @retval None
338 | */
339 | #ifdef DATA_IN_ExtSRAM
340 | /**
341 | * @brief Setup the external memory controller.
342 | * Called in startup_stm32f1xx_xx.s/.c before jump to main.
343 | * This function configures the external SRAM mounted on STM3210E-EVAL
344 | * board (STM32 High density devices). This SRAM will be used as program
345 | * data memory (including heap and stack).
346 | * @param None
347 | * @retval None
348 | */
349 | void SystemInit_ExtMemCtl(void)
350 | {
351 | __IO uint32_t tmpreg;
352 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
353 | required, then adjust the Register Addresses */
354 |
355 | /* Enable FSMC clock */
356 | RCC->AHBENR = 0x00000114U;
357 |
358 | /* Delay after an RCC peripheral clock enabling */
359 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
360 |
361 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
362 | RCC->APB2ENR = 0x000001E0U;
363 |
364 | /* Delay after an RCC peripheral clock enabling */
365 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
366 |
367 | (void)(tmpreg);
368 |
369 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
370 | /*---------------- SRAM Address lines configuration -------------------------*/
371 | /*---------------- NOE and NWE configuration --------------------------------*/
372 | /*---------------- NE3 configuration ----------------------------------------*/
373 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/
374 |
375 | GPIOD->CRL = 0x44BB44BBU;
376 | GPIOD->CRH = 0xBBBBBBBBU;
377 |
378 | GPIOE->CRL = 0xB44444BBU;
379 | GPIOE->CRH = 0xBBBBBBBBU;
380 |
381 | GPIOF->CRL = 0x44BBBBBBU;
382 | GPIOF->CRH = 0xBBBB4444U;
383 |
384 | GPIOG->CRL = 0x44BBBBBBU;
385 | GPIOG->CRH = 0x444B4B44U;
386 |
387 | /*---------------- FSMC Configuration ---------------------------------------*/
388 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
389 |
390 | FSMC_Bank1->BTCR[4U] = 0x00001091U;
391 | FSMC_Bank1->BTCR[5U] = 0x00110212U;
392 | }
393 | #endif /* DATA_IN_ExtSRAM */
394 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
395 |
396 | /**
397 | * @}
398 | */
399 |
400 | /**
401 | * @}
402 | */
403 |
404 | /**
405 | * @}
406 | */
407 |
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