├── README.md └── src ├── clock.ucf ├── Makefile └── clock.v /README.md: -------------------------------------------------------------------------------- 1 | verilog-vga-controller 2 | ====================== 3 | 4 | A very simple VGA controller written in verilog -------------------------------------------------------------------------------- /src/clock.ucf: -------------------------------------------------------------------------------- 1 | # This is a "user constraints file" that describes 2 | # the pin-out of the Demand Peripherals Baseboard4. 3 | NET "clk50" LOC="P38"; 4 | NET "vsync_out" LOC="P92"; 5 | NET "hsync_out" LOC="P78"; 6 | NET "blue_out" LOC="P79"; 7 | NET "green_out" LOC="P94"; 8 | NET "red_out" LOC="P98"; 9 | 10 | # NET "SV1<0>" LOC = "P92" ; 11 | # NET "SV1<1>" LOC = "P78" ; 12 | # NET "SV1<2>" LOC = "P79" ; 13 | # NET "SV1<3>" LOC = "P94" ; 14 | # NET "SV1<4>" LOC = "P98" ; 15 | # NET "SV1<5>" LOC = "P83" ; 16 | # NET "SV1<6>" LOC = "P84" ; 17 | # NET "SV1<7>" LOC = "P85" ; 18 | -------------------------------------------------------------------------------- /src/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile to compile and download a simple Verilog program 2 | 3 | DEVICE=xc3s100e-4-vq100 4 | default: clock.bin 5 | 6 | clock.ngc: clock.v 7 | echo "run -ifn clock.v -ifmt Verilog -ofn clock -fsm_extract no -optimize_primitives NO -equivalent_register_removal NO -p \ 8 | $(DEVICE) -opt_mode Speed -opt_level 1 -top top" | xst 9 | 10 | clock.ngd: clock.ngc clock.ucf 11 | ngdbuild -p $(DEVICE) -uc clock.ucf clock.ngc 12 | 13 | clock.ncd: clock.ngd 14 | map -k 6 -detail -pr b clock.ngd 15 | 16 | clock.pcf: clock.ngd 17 | map -k 6 -detail -pr b clock.ngd 18 | 19 | parout.ncd: clock.ncd 20 | par -w clock.ncd parout.ncd clock.pcf 21 | 22 | clock.bit: parout.ncd 23 | bitgen -w -g CRC:Enable -g StartUpClk:CClk -g Compress \ 24 | parout.ncd clock.bit clock.pcf 25 | 26 | clock.bin: clock.bit 27 | promgen -w -p bin -o clock.bin -u 0 clock.bit 28 | 29 | install: clock.bin 30 | stty --file=/dev/ttyUSB0 -opost # We want raw output 31 | cat clock.bin > /dev/ttyUSB0 32 | 33 | clean: 34 | rm -rf clock.bgn clock.bin clock.bit clock.bld \ 35 | clock.drc clock.map clock_map.xrpt clock.mrp \ 36 | clock.ncd clock.ngc clock.ngd clock_ngdbuild.xrpt \ 37 | clock.ngm clock_par.xrpt clock.pcf clock.prm \ 38 | clock_summary.xml clock_usage.xml clock_xst.xrpt \ 39 | netlist.lst parout.ncd parout.pad parout_pad.csv \ 40 | parout_pad.txt parout.par parout.ptwx parout.unroutes \ 41 | parout.xpi xlnx_auto_0.ise xlnx_auto_0_xdb xst 42 | 43 | test: 44 | cat /dev/ttyUSB0 45 | -------------------------------------------------------------------------------- /src/clock.v: -------------------------------------------------------------------------------- 1 | module vsync(line_clk, vsync_out, blank_out); 2 | input line_clk; 3 | output vsync_out; 4 | output blank_out; 5 | 6 | reg [10:0] count = 10'b0000000000; 7 | reg vsync = 0; 8 | reg blank = 0; 9 | 10 | always @(posedge line_clk) 11 | if (count < 666) 12 | count <= count + 1; 13 | else 14 | count <= 0; 15 | 16 | always @(posedge line_clk) 17 | if (count < 600) 18 | blank <= 0; 19 | else 20 | blank <= 1; 21 | 22 | always @(posedge line_clk) 23 | begin 24 | if (count < 637) 25 | vsync <= 1; 26 | else if (count >= 637 && count < 643) 27 | vsync <= 0; 28 | else if (count >= 643) 29 | vsync <= 1; 30 | end 31 | 32 | assign vsync_out = vsync; 33 | assign blank_out = blank; 34 | 35 | endmodule // hsync 36 | 37 | module hsync(clk50, hsync_out, blank_out, newline_out); 38 | input clk50; 39 | output hsync_out, blank_out, newline_out; 40 | 41 | reg [10:0] count = 10'b0000000000; 42 | reg hsync = 0; 43 | reg blank = 0; 44 | reg newline = 0; 45 | 46 | always @(posedge clk50) 47 | begin 48 | if (count < 1040) 49 | count <= count + 1; 50 | else 51 | count <= 0; 52 | end 53 | 54 | always @(posedge clk50) 55 | begin 56 | if (count == 0) 57 | newline <= 1; 58 | else 59 | newline <= 0; 60 | end 61 | 62 | always @(posedge clk50) 63 | begin 64 | if (count >= 800) 65 | blank <= 1; 66 | else 67 | blank <= 0; 68 | end 69 | 70 | always @(posedge clk50) 71 | begin 72 | if (count < 856) // pixel data plus front porch 73 | hsync <= 1; 74 | else if (count >= 856 && count < 976) 75 | hsync <= 0; 76 | else if (count >= 976) 77 | hsync <= 1; 78 | end // always @ (posedge clk50) 79 | 80 | assign hsync_out = hsync; 81 | assign blank_out = blank; 82 | assign newline_out = newline; 83 | 84 | endmodule // hsync 85 | 86 | 87 | module color(clk, blank, red_out, green_out, blue_out); 88 | input clk, blank; 89 | output red_out, green_out, blue_out; 90 | 91 | reg [8:0] count; 92 | 93 | always @(posedge clk) 94 | begin 95 | if (blank) 96 | count <= 0; 97 | else 98 | count <= count + 1; 99 | end 100 | 101 | assign red_out = count[8]; 102 | assign green_out = count[7]; 103 | assign blue_out = count[6]; 104 | 105 | endmodule // color 106 | 107 | 108 | module top(clk50, hsync_out, vsync_out, red_out, blue_out, green_out); 109 | input clk50; 110 | output hsync_out, vsync_out, red_out, blue_out, green_out; 111 | wire line_clk, blank, hblank, vblank; 112 | 113 | hsync hs(clk50, hsync_out, hblank, line_clk); 114 | vsync vs(line_clk, vsync_out, vblank); 115 | color cg(clk50, blank, red_out, green_out, blue_out); 116 | 117 | assign blank = hblank || vblank; 118 | 119 | endmodule // top 120 | --------------------------------------------------------------------------------