├── .circleci └── config.yml ├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── extra └── antlr-4.10.1-complete.jar ├── pyproject.toml ├── setup.cfg ├── src └── antlr4_verilog │ ├── __init__.py │ ├── systemverilog │ ├── SystemVerilogLexer.interp │ ├── SystemVerilogLexer.py │ ├── SystemVerilogLexer.tokens │ ├── SystemVerilogParser.interp │ ├── SystemVerilogParser.py │ ├── SystemVerilogParser.tokens │ ├── SystemVerilogParserListener.py │ ├── SystemVerilogParserVisitor.py │ ├── SystemVerilogPreParser.interp │ ├── SystemVerilogPreParser.py │ ├── SystemVerilogPreParser.tokens │ ├── SystemVerilogPreParserListener.py │ ├── SystemVerilogPreParserVisitor.py │ └── __init__.py │ └── verilog │ ├── VerilogLexer.interp │ ├── VerilogLexer.py │ ├── VerilogLexer.tokens │ ├── VerilogParser.interp │ ├── VerilogParser.py │ ├── VerilogParser.tokens │ ├── VerilogParserListener.py │ ├── VerilogParserVisitor.py │ ├── VerilogPreParser.interp │ ├── VerilogPreParser.py │ ├── VerilogPreParser.tokens │ ├── VerilogPreParserListener.py │ ├── VerilogPreParserVisitor.py │ └── __init__.py └── test ├── __init__.py ├── test.py └── testrig ├── systemverilog.jar ├── systemverilog ├── SystemVerilogLexer.interp ├── SystemVerilogLexer.java ├── SystemVerilogLexer.tokens ├── SystemVerilogParser.interp ├── SystemVerilogParser.java ├── SystemVerilogParser.tokens ├── SystemVerilogParserBaseListener.java ├── SystemVerilogParserBaseVisitor.java ├── SystemVerilogParserListener.java ├── SystemVerilogParserVisitor.java ├── SystemVerilogPreParser.interp ├── SystemVerilogPreParser.java ├── SystemVerilogPreParser.tokens ├── SystemVerilogPreParserBaseListener.java ├── SystemVerilogPreParserBaseVisitor.java ├── SystemVerilogPreParserListener.java └── SystemVerilogPreParserVisitor.java ├── test.sv ├── test.sv.tree ├── test.v ├── test.v.tree ├── verilog.jar └── verilog ├── VerilogLexer.interp ├── VerilogLexer.java ├── VerilogLexer.tokens ├── VerilogParser.interp ├── VerilogParser.java ├── VerilogParser.tokens ├── VerilogParserBaseListener.java ├── VerilogParserBaseVisitor.java ├── VerilogParserListener.java ├── VerilogParserVisitor.java ├── VerilogPreParser.interp ├── VerilogPreParser.java ├── VerilogPreParser.tokens ├── VerilogPreParserBaseListener.java ├── VerilogPreParserBaseVisitor.java ├── VerilogPreParserListener.java └── VerilogPreParserVisitor.java /.circleci/config.yml: -------------------------------------------------------------------------------- 1 | # Use the latest 2.1 version of CircleCI pipeline process engine. 2 | # See: https://circleci.com/docs/2.0/configuration-reference 3 | version: 2.1 4 | 5 | # Define a job to be invoked later in a workflow. 6 | # See: https://circleci.com/docs/2.0/configuration-reference/#jobs 7 | jobs: 8 | build-test: 9 | # Specify the execution environment. You can specify an image from Dockerhub or use one of our Convenience Images from CircleCI's Developer Hub. 10 | # See: https://circleci.com/docs/2.0/configuration-reference/#docker-machine-macos-windows-executor 11 | docker: 12 | - image: cimg/python:3.6.15 13 | 14 | # Add steps to the job 15 | # See: https://circleci.com/docs/2.0/configuration-reference/#steps 16 | steps: 17 | - checkout 18 | - run: 19 | name: "Build Python package" 20 | command: | 21 | python3 -m venv venv 22 | . venv/bin/activate 23 | python3 -m pip install --upgrade build 24 | python3 -m build 25 | - run: 26 | name: "Run Python unit tests" 27 | command: | 28 | python3 -m venv venv 29 | . venv/bin/activate 30 | python3 -m pip install `ls -t dist/*.whl | head -1` 31 | python3 -m unittest test/test.py 32 | 33 | # Invoke jobs via workflows 34 | # See: https://circleci.com/docs/2.0/configuration-reference/#workflows 35 | workflows: 36 | build-test-workflow: 37 | jobs: 38 | - build-test 39 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | __pycache__/ 3 | dist/ 4 | env/ 5 | src/antlr4_verilog.egg-info 6 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "extra/grammars-v4"] 2 | path = extra/grammars-v4 3 | url = https://github.com/antlr/grammars-v4 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Marco Diniz Sousa 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ANTLR4-Verilog-Python 2 | Generated files from ANTLR4 for Verilog parsing in Python 3 | 4 | [![Build Status](https://img.shields.io/circleci/build/github/mtdsousa/antlr4-verilog-python?label=Continuous%20integration)](https://app.circleci.com/pipelines/github/mtdsousa/antlr4-verilog-python) 5 | ![PyPI version](https://img.shields.io/pypi/v/antlr4-verilog) 6 | 7 | ## Tutorial 8 | Install this Python package 9 | ``` 10 | python3 -m pip install antlr4_verilog 11 | ``` 12 | 13 | Use your own listener to walk through the AST: 14 | ```python 15 | from antlr4_verilog import InputStream, CommonTokenStream, ParseTreeWalker 16 | from antlr4_verilog.verilog import VerilogLexer, VerilogParser, VerilogParserListener 17 | 18 | design = ''' 19 | module ha(a, b, sum, c); 20 | input a, b; 21 | output sum, c; 22 | 23 | assign sum = a ^ b; 24 | assign c = a & b; 25 | endmodule 26 | ''' 27 | 28 | class ModuleIdentifierListener(VerilogParserListener): 29 | def exitModule_declaration(self, ctx): 30 | self.identifier = ctx.module_identifier().getText() 31 | 32 | lexer = VerilogLexer(InputStream(design)) 33 | stream = CommonTokenStream(lexer) 34 | parser = VerilogParser(stream) 35 | 36 | tree = parser.source_text() 37 | listener = ModuleIdentifierListener() 38 | walker = ParseTreeWalker() 39 | walker.walk(listener, tree) 40 | print(listener.identifier) # 'ha' 41 | ``` 42 | > Take a look at other listener methods for [Verilog](src/antlr4_verilog/verilog/VerilogParserListener.py) and [SystemVerilog](src/antlr4_verilog/systemverilog/SystemVerilogParserListener.py) 43 | 44 | > You may find more examples in the [test file](test/test.py) 45 | 46 | ## How to generate those files 47 | 48 | System requirements (Ubuntu): 49 | ``` 50 | sudo apt-get install -y default-jre 51 | sudo apt-get install -y default-jdk 52 | sudo apt-get install -y curl 53 | ``` 54 | 55 | 1. Get ANTLR4: 56 | ```bash 57 | curl https://www.antlr.org/download/antlr-4.10.1-complete.jar -o extra/antlr-4.10.1-complete.jar 58 | ``` 59 | 60 | 2. Get ANTLR grammars: 61 | ``` 62 | git clone https://github.com/antlr/grammars-v4.git extra/grammars-v4 63 | ``` 64 | 65 | 3. Call ANTLR for Verilog grammar: 66 | ``` 67 | java -Xmx500M -cp "extra/antlr-4.10.1-complete.jar:${CLASSPATH}" org.antlr.v4.Tool -Dlanguage=Python3 -visitor `pwd`/extra/grammars-v4/verilog/verilog/VerilogLexer.g4 `pwd`/extra/grammars-v4/verilog/verilog/VerilogParser.g4 `pwd`/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 -o src/antlr4_verilog/verilog 68 | ``` 69 | 70 | 3. Call ANTLR for SystemVerilog grammar: 71 | ``` 72 | java -Xmx500M -cp "extra/antlr-4.10.1-complete.jar:${CLASSPATH}" org.antlr.v4.Tool -Dlanguage=Python3 -visitor `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogLexer.g4 `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogParser.g4 `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogPreParser.g4 -o src/antlr4_verilog/systemverilog 73 | ``` 74 | 75 | ## How to test the grammar 76 | 77 | 1. Generate Java files: 78 | ``` 79 | java -Xmx500M -cp "extra/antlr-4.10.1-complete.jar:${CLASSPATH}" org.antlr.v4.Tool -Dlanguage=Java -visitor `pwd`/extra/grammars-v4/verilog/verilog/VerilogLexer.g4 `pwd`/extra/grammars-v4/verilog/verilog/VerilogParser.g4 `pwd`/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 -o test/testrig/verilog 80 | ``` 81 | ``` 82 | java -Xmx500M -cp "extra/antlr-4.10.1-complete.jar:${CLASSPATH}" org.antlr.v4.Tool -Dlanguage=Java -visitor `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogLexer.g4 `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogParser.g4 `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogPreParser.g4 -o test/testrig/systemverilog 83 | ``` 84 | 85 | 2. Compile these recently generated files: 86 | ``` 87 | javac -cp "extra/antlr-4.10.1-complete.jar:${CLASSPATH}" test/testrig/verilog/*.java 88 | ``` 89 | ``` 90 | javac -cp "extra/antlr-4.10.1-complete.jar:${CLASSPATH}" test/testrig/systemverilog/*.java 91 | ``` 92 | 93 | 3. Create JAR files: 94 | ``` 95 | jar cf test/testrig/verilog.jar -C test/testrig/verilog . 96 | ``` 97 | ``` 98 | jar cf test/testrig/systemverilog.jar -C test/testrig/systemverilog . 99 | ``` 100 | 101 | 4. Finally, for `test.v` and `test.sv` files: 102 | ``` 103 | java -Xmx500M -cp "extra/antlr-4.10.1-complete.jar:test/testrig/verilog.jar:${CLASSPATH}" org.antlr.v4.gui.TestRig Verilog source_text test/testrig/test.v -tree 104 | ``` 105 | ``` 106 | java -Xmx500M -cp "extra/antlr-4.10.1-complete.jar:test/testrig/systemverilog.jar:${CLASSPATH}" org.antlr.v4.gui.TestRig SystemVerilog source_text test/testrig/test.sv -tree 107 | ``` 108 | > You can use `-gui` to test it interactively 109 | 110 | ## Acknowledgement 111 | We would like to appreciate the work from the ANTLR team and the Verilog/SystemVerilog grammar written by [Mustafa Said Ağca](https://github.com/msagca). 112 | -------------------------------------------------------------------------------- /extra/antlr-4.10.1-complete.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mtdsousa/antlr4-verilog-python/e078ccafc5d83ea179b5e6f4b4373f5b5de57872/extra/antlr-4.10.1-complete.jar -------------------------------------------------------------------------------- /pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = [ 3 | "setuptools>=42", 4 | "wheel" 5 | ] 6 | build-backend = "setuptools.build_meta" -------------------------------------------------------------------------------- /setup.cfg: -------------------------------------------------------------------------------- 1 | [metadata] 2 | name = antlr4-verilog 3 | version = 4.0.0 4 | author = Marco Diniz Sousa 5 | author_email = mtdsousa@gmail.com 6 | description = Generated files from ANTLR4 for Verilog parsing 7 | long_description = file: README.md 8 | long_description_content_type = text/markdown 9 | url = https://github.com/mtdsousa/antlr4-verilog-python 10 | project_urls = 11 | Bug Tracker = https://github.com/mtdsousa/antlr4-verilog-python/issues 12 | classifiers = 13 | Programming Language :: Python :: 3 14 | License :: OSI Approved :: MIT License 15 | Operating System :: OS Independent 16 | 17 | [options] 18 | package_dir = 19 | = src 20 | packages = find: 21 | python_requires = >=3.6 22 | install_requires = 23 | antlr4-python3-runtime==4.10 24 | 25 | [options.packages.find] 26 | where = src 27 | -------------------------------------------------------------------------------- /src/antlr4_verilog/__init__.py: -------------------------------------------------------------------------------- 1 | ''' 2 | Copyright (c) 2022 Marco Diniz Sousa 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | ''' 15 | 16 | from antlr4 import * 17 | 18 | -------------------------------------------------------------------------------- /src/antlr4_verilog/systemverilog/SystemVerilogPreParserListener.py: -------------------------------------------------------------------------------- 1 | # Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/systemverilog/SystemVerilogPreParser.g4 by ANTLR 4.10.1 2 | from antlr4 import * 3 | if __name__ is not None and "." in __name__: 4 | from .SystemVerilogPreParser import SystemVerilogPreParser 5 | else: 6 | from SystemVerilogPreParser import SystemVerilogPreParser 7 | 8 | # This class defines a complete listener for a parse tree produced by SystemVerilogPreParser. 9 | class SystemVerilogPreParserListener(ParseTreeListener): 10 | 11 | # Enter a parse tree produced by SystemVerilogPreParser#source_text. 12 | def enterSource_text(self, ctx:SystemVerilogPreParser.Source_textContext): 13 | pass 14 | 15 | # Exit a parse tree produced by SystemVerilogPreParser#source_text. 16 | def exitSource_text(self, ctx:SystemVerilogPreParser.Source_textContext): 17 | pass 18 | 19 | 20 | # Enter a parse tree produced by SystemVerilogPreParser#compiler_directive. 21 | def enterCompiler_directive(self, ctx:SystemVerilogPreParser.Compiler_directiveContext): 22 | pass 23 | 24 | # Exit a parse tree produced by SystemVerilogPreParser#compiler_directive. 25 | def exitCompiler_directive(self, ctx:SystemVerilogPreParser.Compiler_directiveContext): 26 | pass 27 | 28 | 29 | # Enter a parse tree produced by SystemVerilogPreParser#file_directive. 30 | def enterFile_directive(self, ctx:SystemVerilogPreParser.File_directiveContext): 31 | pass 32 | 33 | # Exit a parse tree produced by SystemVerilogPreParser#file_directive. 34 | def exitFile_directive(self, ctx:SystemVerilogPreParser.File_directiveContext): 35 | pass 36 | 37 | 38 | # Enter a parse tree produced by SystemVerilogPreParser#line_directive_. 39 | def enterLine_directive_(self, ctx:SystemVerilogPreParser.Line_directive_Context): 40 | pass 41 | 42 | # Exit a parse tree produced by SystemVerilogPreParser#line_directive_. 43 | def exitLine_directive_(self, ctx:SystemVerilogPreParser.Line_directive_Context): 44 | pass 45 | 46 | 47 | # Enter a parse tree produced by SystemVerilogPreParser#begin_keywords_directive. 48 | def enterBegin_keywords_directive(self, ctx:SystemVerilogPreParser.Begin_keywords_directiveContext): 49 | pass 50 | 51 | # Exit a parse tree produced by SystemVerilogPreParser#begin_keywords_directive. 52 | def exitBegin_keywords_directive(self, ctx:SystemVerilogPreParser.Begin_keywords_directiveContext): 53 | pass 54 | 55 | 56 | # Enter a parse tree produced by SystemVerilogPreParser#celldefine_directive. 57 | def enterCelldefine_directive(self, ctx:SystemVerilogPreParser.Celldefine_directiveContext): 58 | pass 59 | 60 | # Exit a parse tree produced by SystemVerilogPreParser#celldefine_directive. 61 | def exitCelldefine_directive(self, ctx:SystemVerilogPreParser.Celldefine_directiveContext): 62 | pass 63 | 64 | 65 | # Enter a parse tree produced by SystemVerilogPreParser#default_nettype_directive. 66 | def enterDefault_nettype_directive(self, ctx:SystemVerilogPreParser.Default_nettype_directiveContext): 67 | pass 68 | 69 | # Exit a parse tree produced by SystemVerilogPreParser#default_nettype_directive. 70 | def exitDefault_nettype_directive(self, ctx:SystemVerilogPreParser.Default_nettype_directiveContext): 71 | pass 72 | 73 | 74 | # Enter a parse tree produced by SystemVerilogPreParser#endcelldefine_directive. 75 | def enterEndcelldefine_directive(self, ctx:SystemVerilogPreParser.Endcelldefine_directiveContext): 76 | pass 77 | 78 | # Exit a parse tree produced by SystemVerilogPreParser#endcelldefine_directive. 79 | def exitEndcelldefine_directive(self, ctx:SystemVerilogPreParser.Endcelldefine_directiveContext): 80 | pass 81 | 82 | 83 | # Enter a parse tree produced by SystemVerilogPreParser#end_keywords_directive. 84 | def enterEnd_keywords_directive(self, ctx:SystemVerilogPreParser.End_keywords_directiveContext): 85 | pass 86 | 87 | # Exit a parse tree produced by SystemVerilogPreParser#end_keywords_directive. 88 | def exitEnd_keywords_directive(self, ctx:SystemVerilogPreParser.End_keywords_directiveContext): 89 | pass 90 | 91 | 92 | # Enter a parse tree produced by SystemVerilogPreParser#ifdef_directive. 93 | def enterIfdef_directive(self, ctx:SystemVerilogPreParser.Ifdef_directiveContext): 94 | pass 95 | 96 | # Exit a parse tree produced by SystemVerilogPreParser#ifdef_directive. 97 | def exitIfdef_directive(self, ctx:SystemVerilogPreParser.Ifdef_directiveContext): 98 | pass 99 | 100 | 101 | # Enter a parse tree produced by SystemVerilogPreParser#ifndef_directive. 102 | def enterIfndef_directive(self, ctx:SystemVerilogPreParser.Ifndef_directiveContext): 103 | pass 104 | 105 | # Exit a parse tree produced by SystemVerilogPreParser#ifndef_directive. 106 | def exitIfndef_directive(self, ctx:SystemVerilogPreParser.Ifndef_directiveContext): 107 | pass 108 | 109 | 110 | # Enter a parse tree produced by SystemVerilogPreParser#include_directive. 111 | def enterInclude_directive(self, ctx:SystemVerilogPreParser.Include_directiveContext): 112 | pass 113 | 114 | # Exit a parse tree produced by SystemVerilogPreParser#include_directive. 115 | def exitInclude_directive(self, ctx:SystemVerilogPreParser.Include_directiveContext): 116 | pass 117 | 118 | 119 | # Enter a parse tree produced by SystemVerilogPreParser#line_directive. 120 | def enterLine_directive(self, ctx:SystemVerilogPreParser.Line_directiveContext): 121 | pass 122 | 123 | # Exit a parse tree produced by SystemVerilogPreParser#line_directive. 124 | def exitLine_directive(self, ctx:SystemVerilogPreParser.Line_directiveContext): 125 | pass 126 | 127 | 128 | # Enter a parse tree produced by SystemVerilogPreParser#nounconnected_drive_directive. 129 | def enterNounconnected_drive_directive(self, ctx:SystemVerilogPreParser.Nounconnected_drive_directiveContext): 130 | pass 131 | 132 | # Exit a parse tree produced by SystemVerilogPreParser#nounconnected_drive_directive. 133 | def exitNounconnected_drive_directive(self, ctx:SystemVerilogPreParser.Nounconnected_drive_directiveContext): 134 | pass 135 | 136 | 137 | # Enter a parse tree produced by SystemVerilogPreParser#pragma_directive. 138 | def enterPragma_directive(self, ctx:SystemVerilogPreParser.Pragma_directiveContext): 139 | pass 140 | 141 | # Exit a parse tree produced by SystemVerilogPreParser#pragma_directive. 142 | def exitPragma_directive(self, ctx:SystemVerilogPreParser.Pragma_directiveContext): 143 | pass 144 | 145 | 146 | # Enter a parse tree produced by SystemVerilogPreParser#resetall_directive. 147 | def enterResetall_directive(self, ctx:SystemVerilogPreParser.Resetall_directiveContext): 148 | pass 149 | 150 | # Exit a parse tree produced by SystemVerilogPreParser#resetall_directive. 151 | def exitResetall_directive(self, ctx:SystemVerilogPreParser.Resetall_directiveContext): 152 | pass 153 | 154 | 155 | # Enter a parse tree produced by SystemVerilogPreParser#text_macro_definition. 156 | def enterText_macro_definition(self, ctx:SystemVerilogPreParser.Text_macro_definitionContext): 157 | pass 158 | 159 | # Exit a parse tree produced by SystemVerilogPreParser#text_macro_definition. 160 | def exitText_macro_definition(self, ctx:SystemVerilogPreParser.Text_macro_definitionContext): 161 | pass 162 | 163 | 164 | # Enter a parse tree produced by SystemVerilogPreParser#text_macro_usage. 165 | def enterText_macro_usage(self, ctx:SystemVerilogPreParser.Text_macro_usageContext): 166 | pass 167 | 168 | # Exit a parse tree produced by SystemVerilogPreParser#text_macro_usage. 169 | def exitText_macro_usage(self, ctx:SystemVerilogPreParser.Text_macro_usageContext): 170 | pass 171 | 172 | 173 | # Enter a parse tree produced by SystemVerilogPreParser#timescale_directive. 174 | def enterTimescale_directive(self, ctx:SystemVerilogPreParser.Timescale_directiveContext): 175 | pass 176 | 177 | # Exit a parse tree produced by SystemVerilogPreParser#timescale_directive. 178 | def exitTimescale_directive(self, ctx:SystemVerilogPreParser.Timescale_directiveContext): 179 | pass 180 | 181 | 182 | # Enter a parse tree produced by SystemVerilogPreParser#unconnected_drive_directive. 183 | def enterUnconnected_drive_directive(self, ctx:SystemVerilogPreParser.Unconnected_drive_directiveContext): 184 | pass 185 | 186 | # Exit a parse tree produced by SystemVerilogPreParser#unconnected_drive_directive. 187 | def exitUnconnected_drive_directive(self, ctx:SystemVerilogPreParser.Unconnected_drive_directiveContext): 188 | pass 189 | 190 | 191 | # Enter a parse tree produced by SystemVerilogPreParser#undef_directive. 192 | def enterUndef_directive(self, ctx:SystemVerilogPreParser.Undef_directiveContext): 193 | pass 194 | 195 | # Exit a parse tree produced by SystemVerilogPreParser#undef_directive. 196 | def exitUndef_directive(self, ctx:SystemVerilogPreParser.Undef_directiveContext): 197 | pass 198 | 199 | 200 | # Enter a parse tree produced by SystemVerilogPreParser#undefineall_directive. 201 | def enterUndefineall_directive(self, ctx:SystemVerilogPreParser.Undefineall_directiveContext): 202 | pass 203 | 204 | # Exit a parse tree produced by SystemVerilogPreParser#undefineall_directive. 205 | def exitUndefineall_directive(self, ctx:SystemVerilogPreParser.Undefineall_directiveContext): 206 | pass 207 | 208 | 209 | # Enter a parse tree produced by SystemVerilogPreParser#elsif_directive. 210 | def enterElsif_directive(self, ctx:SystemVerilogPreParser.Elsif_directiveContext): 211 | pass 212 | 213 | # Exit a parse tree produced by SystemVerilogPreParser#elsif_directive. 214 | def exitElsif_directive(self, ctx:SystemVerilogPreParser.Elsif_directiveContext): 215 | pass 216 | 217 | 218 | # Enter a parse tree produced by SystemVerilogPreParser#else_directive. 219 | def enterElse_directive(self, ctx:SystemVerilogPreParser.Else_directiveContext): 220 | pass 221 | 222 | # Exit a parse tree produced by SystemVerilogPreParser#else_directive. 223 | def exitElse_directive(self, ctx:SystemVerilogPreParser.Else_directiveContext): 224 | pass 225 | 226 | 227 | # Enter a parse tree produced by SystemVerilogPreParser#endif_directive. 228 | def enterEndif_directive(self, ctx:SystemVerilogPreParser.Endif_directiveContext): 229 | pass 230 | 231 | # Exit a parse tree produced by SystemVerilogPreParser#endif_directive. 232 | def exitEndif_directive(self, ctx:SystemVerilogPreParser.Endif_directiveContext): 233 | pass 234 | 235 | 236 | # Enter a parse tree produced by SystemVerilogPreParser#text_macro_identifier. 237 | def enterText_macro_identifier(self, ctx:SystemVerilogPreParser.Text_macro_identifierContext): 238 | pass 239 | 240 | # Exit a parse tree produced by SystemVerilogPreParser#text_macro_identifier. 241 | def exitText_macro_identifier(self, ctx:SystemVerilogPreParser.Text_macro_identifierContext): 242 | pass 243 | 244 | 245 | # Enter a parse tree produced by SystemVerilogPreParser#ifdef_group_of_lines. 246 | def enterIfdef_group_of_lines(self, ctx:SystemVerilogPreParser.Ifdef_group_of_linesContext): 247 | pass 248 | 249 | # Exit a parse tree produced by SystemVerilogPreParser#ifdef_group_of_lines. 250 | def exitIfdef_group_of_lines(self, ctx:SystemVerilogPreParser.Ifdef_group_of_linesContext): 251 | pass 252 | 253 | 254 | # Enter a parse tree produced by SystemVerilogPreParser#ifndef_group_of_lines. 255 | def enterIfndef_group_of_lines(self, ctx:SystemVerilogPreParser.Ifndef_group_of_linesContext): 256 | pass 257 | 258 | # Exit a parse tree produced by SystemVerilogPreParser#ifndef_group_of_lines. 259 | def exitIfndef_group_of_lines(self, ctx:SystemVerilogPreParser.Ifndef_group_of_linesContext): 260 | pass 261 | 262 | 263 | # Enter a parse tree produced by SystemVerilogPreParser#elsif_group_of_lines. 264 | def enterElsif_group_of_lines(self, ctx:SystemVerilogPreParser.Elsif_group_of_linesContext): 265 | pass 266 | 267 | # Exit a parse tree produced by SystemVerilogPreParser#elsif_group_of_lines. 268 | def exitElsif_group_of_lines(self, ctx:SystemVerilogPreParser.Elsif_group_of_linesContext): 269 | pass 270 | 271 | 272 | # Enter a parse tree produced by SystemVerilogPreParser#else_group_of_lines. 273 | def enterElse_group_of_lines(self, ctx:SystemVerilogPreParser.Else_group_of_linesContext): 274 | pass 275 | 276 | # Exit a parse tree produced by SystemVerilogPreParser#else_group_of_lines. 277 | def exitElse_group_of_lines(self, ctx:SystemVerilogPreParser.Else_group_of_linesContext): 278 | pass 279 | 280 | 281 | # Enter a parse tree produced by SystemVerilogPreParser#macro_text. 282 | def enterMacro_text(self, ctx:SystemVerilogPreParser.Macro_textContext): 283 | pass 284 | 285 | # Exit a parse tree produced by SystemVerilogPreParser#macro_text. 286 | def exitMacro_text(self, ctx:SystemVerilogPreParser.Macro_textContext): 287 | pass 288 | 289 | 290 | 291 | del SystemVerilogPreParser -------------------------------------------------------------------------------- /src/antlr4_verilog/systemverilog/SystemVerilogPreParserVisitor.py: -------------------------------------------------------------------------------- 1 | # Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/systemverilog/SystemVerilogPreParser.g4 by ANTLR 4.10.1 2 | from antlr4 import * 3 | if __name__ is not None and "." in __name__: 4 | from .SystemVerilogPreParser import SystemVerilogPreParser 5 | else: 6 | from SystemVerilogPreParser import SystemVerilogPreParser 7 | 8 | # This class defines a complete generic visitor for a parse tree produced by SystemVerilogPreParser. 9 | 10 | class SystemVerilogPreParserVisitor(ParseTreeVisitor): 11 | 12 | # Visit a parse tree produced by SystemVerilogPreParser#source_text. 13 | def visitSource_text(self, ctx:SystemVerilogPreParser.Source_textContext): 14 | return self.visitChildren(ctx) 15 | 16 | 17 | # Visit a parse tree produced by SystemVerilogPreParser#compiler_directive. 18 | def visitCompiler_directive(self, ctx:SystemVerilogPreParser.Compiler_directiveContext): 19 | return self.visitChildren(ctx) 20 | 21 | 22 | # Visit a parse tree produced by SystemVerilogPreParser#file_directive. 23 | def visitFile_directive(self, ctx:SystemVerilogPreParser.File_directiveContext): 24 | return self.visitChildren(ctx) 25 | 26 | 27 | # Visit a parse tree produced by SystemVerilogPreParser#line_directive_. 28 | def visitLine_directive_(self, ctx:SystemVerilogPreParser.Line_directive_Context): 29 | return self.visitChildren(ctx) 30 | 31 | 32 | # Visit a parse tree produced by SystemVerilogPreParser#begin_keywords_directive. 33 | def visitBegin_keywords_directive(self, ctx:SystemVerilogPreParser.Begin_keywords_directiveContext): 34 | return self.visitChildren(ctx) 35 | 36 | 37 | # Visit a parse tree produced by SystemVerilogPreParser#celldefine_directive. 38 | def visitCelldefine_directive(self, ctx:SystemVerilogPreParser.Celldefine_directiveContext): 39 | return self.visitChildren(ctx) 40 | 41 | 42 | # Visit a parse tree produced by SystemVerilogPreParser#default_nettype_directive. 43 | def visitDefault_nettype_directive(self, ctx:SystemVerilogPreParser.Default_nettype_directiveContext): 44 | return self.visitChildren(ctx) 45 | 46 | 47 | # Visit a parse tree produced by SystemVerilogPreParser#endcelldefine_directive. 48 | def visitEndcelldefine_directive(self, ctx:SystemVerilogPreParser.Endcelldefine_directiveContext): 49 | return self.visitChildren(ctx) 50 | 51 | 52 | # Visit a parse tree produced by SystemVerilogPreParser#end_keywords_directive. 53 | def visitEnd_keywords_directive(self, ctx:SystemVerilogPreParser.End_keywords_directiveContext): 54 | return self.visitChildren(ctx) 55 | 56 | 57 | # Visit a parse tree produced by SystemVerilogPreParser#ifdef_directive. 58 | def visitIfdef_directive(self, ctx:SystemVerilogPreParser.Ifdef_directiveContext): 59 | return self.visitChildren(ctx) 60 | 61 | 62 | # Visit a parse tree produced by SystemVerilogPreParser#ifndef_directive. 63 | def visitIfndef_directive(self, ctx:SystemVerilogPreParser.Ifndef_directiveContext): 64 | return self.visitChildren(ctx) 65 | 66 | 67 | # Visit a parse tree produced by SystemVerilogPreParser#include_directive. 68 | def visitInclude_directive(self, ctx:SystemVerilogPreParser.Include_directiveContext): 69 | return self.visitChildren(ctx) 70 | 71 | 72 | # Visit a parse tree produced by SystemVerilogPreParser#line_directive. 73 | def visitLine_directive(self, ctx:SystemVerilogPreParser.Line_directiveContext): 74 | return self.visitChildren(ctx) 75 | 76 | 77 | # Visit a parse tree produced by SystemVerilogPreParser#nounconnected_drive_directive. 78 | def visitNounconnected_drive_directive(self, ctx:SystemVerilogPreParser.Nounconnected_drive_directiveContext): 79 | return self.visitChildren(ctx) 80 | 81 | 82 | # Visit a parse tree produced by SystemVerilogPreParser#pragma_directive. 83 | def visitPragma_directive(self, ctx:SystemVerilogPreParser.Pragma_directiveContext): 84 | return self.visitChildren(ctx) 85 | 86 | 87 | # Visit a parse tree produced by SystemVerilogPreParser#resetall_directive. 88 | def visitResetall_directive(self, ctx:SystemVerilogPreParser.Resetall_directiveContext): 89 | return self.visitChildren(ctx) 90 | 91 | 92 | # Visit a parse tree produced by SystemVerilogPreParser#text_macro_definition. 93 | def visitText_macro_definition(self, ctx:SystemVerilogPreParser.Text_macro_definitionContext): 94 | return self.visitChildren(ctx) 95 | 96 | 97 | # Visit a parse tree produced by SystemVerilogPreParser#text_macro_usage. 98 | def visitText_macro_usage(self, ctx:SystemVerilogPreParser.Text_macro_usageContext): 99 | return self.visitChildren(ctx) 100 | 101 | 102 | # Visit a parse tree produced by SystemVerilogPreParser#timescale_directive. 103 | def visitTimescale_directive(self, ctx:SystemVerilogPreParser.Timescale_directiveContext): 104 | return self.visitChildren(ctx) 105 | 106 | 107 | # Visit a parse tree produced by SystemVerilogPreParser#unconnected_drive_directive. 108 | def visitUnconnected_drive_directive(self, ctx:SystemVerilogPreParser.Unconnected_drive_directiveContext): 109 | return self.visitChildren(ctx) 110 | 111 | 112 | # Visit a parse tree produced by SystemVerilogPreParser#undef_directive. 113 | def visitUndef_directive(self, ctx:SystemVerilogPreParser.Undef_directiveContext): 114 | return self.visitChildren(ctx) 115 | 116 | 117 | # Visit a parse tree produced by SystemVerilogPreParser#undefineall_directive. 118 | def visitUndefineall_directive(self, ctx:SystemVerilogPreParser.Undefineall_directiveContext): 119 | return self.visitChildren(ctx) 120 | 121 | 122 | # Visit a parse tree produced by SystemVerilogPreParser#elsif_directive. 123 | def visitElsif_directive(self, ctx:SystemVerilogPreParser.Elsif_directiveContext): 124 | return self.visitChildren(ctx) 125 | 126 | 127 | # Visit a parse tree produced by SystemVerilogPreParser#else_directive. 128 | def visitElse_directive(self, ctx:SystemVerilogPreParser.Else_directiveContext): 129 | return self.visitChildren(ctx) 130 | 131 | 132 | # Visit a parse tree produced by SystemVerilogPreParser#endif_directive. 133 | def visitEndif_directive(self, ctx:SystemVerilogPreParser.Endif_directiveContext): 134 | return self.visitChildren(ctx) 135 | 136 | 137 | # Visit a parse tree produced by SystemVerilogPreParser#text_macro_identifier. 138 | def visitText_macro_identifier(self, ctx:SystemVerilogPreParser.Text_macro_identifierContext): 139 | return self.visitChildren(ctx) 140 | 141 | 142 | # Visit a parse tree produced by SystemVerilogPreParser#ifdef_group_of_lines. 143 | def visitIfdef_group_of_lines(self, ctx:SystemVerilogPreParser.Ifdef_group_of_linesContext): 144 | return self.visitChildren(ctx) 145 | 146 | 147 | # Visit a parse tree produced by SystemVerilogPreParser#ifndef_group_of_lines. 148 | def visitIfndef_group_of_lines(self, ctx:SystemVerilogPreParser.Ifndef_group_of_linesContext): 149 | return self.visitChildren(ctx) 150 | 151 | 152 | # Visit a parse tree produced by SystemVerilogPreParser#elsif_group_of_lines. 153 | def visitElsif_group_of_lines(self, ctx:SystemVerilogPreParser.Elsif_group_of_linesContext): 154 | return self.visitChildren(ctx) 155 | 156 | 157 | # Visit a parse tree produced by SystemVerilogPreParser#else_group_of_lines. 158 | def visitElse_group_of_lines(self, ctx:SystemVerilogPreParser.Else_group_of_linesContext): 159 | return self.visitChildren(ctx) 160 | 161 | 162 | # Visit a parse tree produced by SystemVerilogPreParser#macro_text. 163 | def visitMacro_text(self, ctx:SystemVerilogPreParser.Macro_textContext): 164 | return self.visitChildren(ctx) 165 | 166 | 167 | 168 | del SystemVerilogPreParser -------------------------------------------------------------------------------- /src/antlr4_verilog/systemverilog/__init__.py: -------------------------------------------------------------------------------- 1 | ''' 2 | Copyright (c) 2022 Marco Diniz Sousa 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | ''' 15 | 16 | from antlr4_verilog.systemverilog.SystemVerilogLexer import SystemVerilogLexer 17 | from antlr4_verilog.systemverilog.SystemVerilogParser import SystemVerilogParser 18 | from antlr4_verilog.systemverilog.SystemVerilogParserListener import SystemVerilogParserListener 19 | from antlr4_verilog.systemverilog.SystemVerilogParserVisitor import SystemVerilogParserVisitor 20 | from antlr4_verilog.systemverilog.SystemVerilogPreParser import SystemVerilogPreParser 21 | from antlr4_verilog.systemverilog.SystemVerilogPreParserListener import SystemVerilogPreParserListener 22 | from antlr4_verilog.systemverilog.SystemVerilogPreParserVisitor import SystemVerilogPreParserVisitor 23 | -------------------------------------------------------------------------------- /src/antlr4_verilog/verilog/VerilogLexer.tokens: -------------------------------------------------------------------------------- 1 | EM=1 2 | EMEQ=2 3 | EMEQEQ=3 4 | DQ=4 5 | HA=5 6 | DL=6 7 | DLFULLSKEW=7 8 | DLHOLD=8 9 | DLNOCHANGE=9 10 | DLPERIOD=10 11 | DLRECOVERY=11 12 | DLRECREM=12 13 | DLREMOVAL=13 14 | DLSETUP=14 15 | DLSETUPHOLD=15 16 | DLSKEW=16 17 | DLTIMESKEW=17 18 | DLWIDTH=18 19 | MO=19 20 | AM=20 21 | AMAM=21 22 | AMAMAM=22 23 | AP=23 24 | LP=24 25 | RP=25 26 | AS=26 27 | ASAS=27 28 | ASSL=28 29 | ASGT=29 30 | PL=30 31 | PLCL=31 32 | CO=32 33 | MI=33 34 | MICL=34 35 | MIGT=35 36 | DT=36 37 | SL=37 38 | SLAS=38 39 | SLSL=39 40 | CL=40 41 | SC=41 42 | LT=42 43 | LTLT=43 44 | LTLTLT=44 45 | LTEQ=45 46 | EQ=46 47 | EQEQ=47 48 | EQEQEQ=48 49 | EQGT=49 50 | GT=50 51 | GTEQ=51 52 | GTGT=52 53 | GTGTGT=53 54 | QM=54 55 | AT=55 56 | PATHPULSEDL=56 57 | LB=57 58 | RB=58 59 | CA=59 60 | CATI=60 61 | GA=61 62 | ALWAYS=62 63 | AND=63 64 | ASSIGN=64 65 | AUTOMATIC=65 66 | BEGIN=66 67 | BUF=67 68 | BUFIFZERO=68 69 | BUFIFONE=69 70 | CASE=70 71 | CASEX=71 72 | CASEZ=72 73 | CELL=73 74 | CMOS=74 75 | CONFIG=75 76 | DEASSIGN=76 77 | DEFAULT=77 78 | DEFPARAM=78 79 | DESIGN=79 80 | DISABLE=80 81 | EDGE=81 82 | ELSE=82 83 | END=83 84 | ENDCASE=84 85 | ENDCONFIG=85 86 | ENDFUNCTION=86 87 | ENDGENERATE=87 88 | ENDMODULE=88 89 | ENDPRIMITIVE=89 90 | ENDSPECIFY=90 91 | ENDTABLE=91 92 | ENDTASK=92 93 | EVENT=93 94 | FOR=94 95 | FORCE=95 96 | FOREVER=96 97 | FORK=97 98 | FUNCTION=98 99 | GENERATE=99 100 | GENVAR=100 101 | HIGHZZERO=101 102 | HIGHZONE=102 103 | IF=103 104 | IFNONE=104 105 | INCLUDE=105 106 | INITIAL=106 107 | INOUT=107 108 | INPUT=108 109 | INSTANCE=109 110 | INTEGER=110 111 | JOIN=111 112 | LARGE=112 113 | LIBLIST=113 114 | LIBRARY=114 115 | LOCALPARAM=115 116 | MACROMODULE=116 117 | MEDIUM=117 118 | MODULE=118 119 | NAND=119 120 | NEGEDGE=120 121 | NMOS=121 122 | NOR=122 123 | NOSHOWCANCELLED=123 124 | NOT=124 125 | NOTIFZERO=125 126 | NOTIFONE=126 127 | OR=127 128 | OUTPUT=128 129 | PARAMETER=129 130 | PMOS=130 131 | POSEDGE=131 132 | PRIMITIVE=132 133 | PULLZERO=133 134 | PULLONE=134 135 | PULLDOWN=135 136 | PULLUP=136 137 | PULSESTYLE_ONDETECT=137 138 | PULSESTYLE_ONEVENT=138 139 | RCMOS=139 140 | REAL=140 141 | REALTIME=141 142 | REG=142 143 | RELEASE=143 144 | REPEAT=144 145 | RNMOS=145 146 | RPMOS=146 147 | RTRAN=147 148 | RTRANIFZERO=148 149 | RTRANIFONE=149 150 | SCALARED=150 151 | SHOWCANCELLED=151 152 | SIGNED=152 153 | SMALL=153 154 | SPECIFY=154 155 | SPECPARAM=155 156 | STRONGZERO=156 157 | STRONGONE=157 158 | SUPPLYZERO=158 159 | SUPPLYONE=159 160 | TABLE=160 161 | TASK=161 162 | TIME=162 163 | TRAN=163 164 | TRANIFZERO=164 165 | TRANIFONE=165 166 | TRI=166 167 | TRIZERO=167 168 | TRIONE=168 169 | TRIAND=169 170 | TRIOR=170 171 | TRIREG=171 172 | USE=172 173 | UWIRE=173 174 | VECTORED=174 175 | WAIT=175 176 | WAND=176 177 | WEAKZERO=177 178 | WEAKONE=178 179 | WHILE=179 180 | WIRE=180 181 | WOR=181 182 | XNOR=182 183 | XOR=183 184 | LC=184 185 | VL=185 186 | VLVL=186 187 | RC=187 188 | TI=188 189 | TIAM=189 190 | TICA=190 191 | TIVL=191 192 | DECIMAL_NUMBER=192 193 | BINARY_NUMBER=193 194 | OCTAL_NUMBER=194 195 | HEX_NUMBER=195 196 | REAL_NUMBER=196 197 | STRING=197 198 | COMMENT=198 199 | ESCAPED_IDENTIFIER=199 200 | SIMPLE_IDENTIFIER=200 201 | SYSTEM_TF_IDENTIFIER=201 202 | WHITE_SPACE=202 203 | MIINCDIR=203 204 | FILE_PATH_SPEC=204 205 | OUTPUT_OR_LEVEL_SYMBOL=205 206 | LEVEL_ONLY_SYMBOL=206 207 | EDGE_SYMBOL=207 208 | EDGE_DESCRIPTOR=208 209 | BEGIN_KEYWORDS_DIRECTIVE=209 210 | CELLDEFINE_DIRECTIVE=210 211 | DEFAULT_NETTYPE_DIRECTIVE=211 212 | DEFINE_DIRECTIVE=212 213 | ELSE_DIRECTIVE=213 214 | ELSIF_DIRECTIVE=214 215 | END_KEYWORDS_DIRECTIVE=215 216 | ENDCELLDEFINE_DIRECTIVE=216 217 | ENDIF_DIRECTIVE=217 218 | IFDEF_DIRECTIVE=218 219 | IFNDEF_DIRECTIVE=219 220 | INCLUDE_DIRECTIVE=220 221 | LINE_DIRECTIVE=221 222 | NOUNCONNECTED_DRIVE_DIRECTIVE=222 223 | PRAGMA_DIRECTIVE=223 224 | RESETALL_DIRECTIVE=224 225 | TIMESCALE_DIRECTIVE=225 226 | UNCONNECTED_DRIVE_DIRECTIVE=226 227 | UNDEF_DIRECTIVE=227 228 | MACRO_USAGE=228 229 | DIRECTIVE_TEXT=229 230 | DIRECTIVE_IDENTIFIER=230 231 | DIRECTIVE_COMMENT=231 232 | DIRECTIVE_WHITE_SPACE=232 233 | DIRECTIVE_NEWLINE=233 234 | MACRO_TEXT=234 235 | MACRO_ESC_NEWLINE=235 236 | SOURCE_TEXT=236 237 | '!'=1 238 | '!='=2 239 | '!=='=3 240 | '"'=4 241 | '#'=5 242 | '$'=6 243 | '$fullskew'=7 244 | '$hold'=8 245 | '$nochange'=9 246 | '$period'=10 247 | '$recovery'=11 248 | '$recrem'=12 249 | '$removal'=13 250 | '$setup'=14 251 | '$setuphold'=15 252 | '$skew'=16 253 | '$timeskew'=17 254 | '$width'=18 255 | '%'=19 256 | '&'=20 257 | '&&'=21 258 | '&&&'=22 259 | '\''=23 260 | '('=24 261 | ')'=25 262 | '*'=26 263 | '**'=27 264 | '*/'=28 265 | '*>'=29 266 | '+'=30 267 | '+:'=31 268 | ','=32 269 | '-'=33 270 | '-:'=34 271 | '->'=35 272 | '.'=36 273 | '/'=37 274 | '/*'=38 275 | '//'=39 276 | ':'=40 277 | ';'=41 278 | '<'=42 279 | '<<'=43 280 | '<<<'=44 281 | '<='=45 282 | '='=46 283 | '=='=47 284 | '==='=48 285 | '=>'=49 286 | '>'=50 287 | '>='=51 288 | '>>'=52 289 | '>>>'=53 290 | '?'=54 291 | '@'=55 292 | 'PATHPULSE$'=56 293 | '['=57 294 | ']'=58 295 | '^'=59 296 | '^~'=60 297 | 'always'=62 298 | 'and'=63 299 | 'assign'=64 300 | 'automatic'=65 301 | 'begin'=66 302 | 'buf'=67 303 | 'bufif0'=68 304 | 'bufif1'=69 305 | 'case'=70 306 | 'casex'=71 307 | 'casez'=72 308 | 'cell'=73 309 | 'cmos'=74 310 | 'config'=75 311 | 'deassign'=76 312 | 'default'=77 313 | 'defparam'=78 314 | 'design'=79 315 | 'disable'=80 316 | 'edge'=81 317 | 'else'=82 318 | 'end'=83 319 | 'endcase'=84 320 | 'endconfig'=85 321 | 'endfunction'=86 322 | 'endgenerate'=87 323 | 'endmodule'=88 324 | 'endprimitive'=89 325 | 'endspecify'=90 326 | 'endtable'=91 327 | 'endtask'=92 328 | 'event'=93 329 | 'for'=94 330 | 'force'=95 331 | 'forever'=96 332 | 'fork'=97 333 | 'function'=98 334 | 'generate'=99 335 | 'genvar'=100 336 | 'highz0'=101 337 | 'highz1'=102 338 | 'if'=103 339 | 'ifnone'=104 340 | 'include'=105 341 | 'initial'=106 342 | 'inout'=107 343 | 'input'=108 344 | 'instance'=109 345 | 'integer'=110 346 | 'join'=111 347 | 'large'=112 348 | 'liblist'=113 349 | 'library'=114 350 | 'localparam'=115 351 | 'macromodule'=116 352 | 'medium'=117 353 | 'module'=118 354 | 'nand'=119 355 | 'negedge'=120 356 | 'nmos'=121 357 | 'nor'=122 358 | 'noshowcancelled'=123 359 | 'not'=124 360 | 'notif0'=125 361 | 'notif1'=126 362 | 'or'=127 363 | 'output'=128 364 | 'parameter'=129 365 | 'pmos'=130 366 | 'posedge'=131 367 | 'primitive'=132 368 | 'pull0'=133 369 | 'pull1'=134 370 | 'pulldown'=135 371 | 'pullup'=136 372 | 'pulsestyle_ondetect'=137 373 | 'pulsestyle_onevent'=138 374 | 'rcmos'=139 375 | 'real'=140 376 | 'realtime'=141 377 | 'reg'=142 378 | 'release'=143 379 | 'repeat'=144 380 | 'rnmos'=145 381 | 'rpmos'=146 382 | 'rtran'=147 383 | 'rtranif0'=148 384 | 'rtranif1'=149 385 | 'scalared'=150 386 | 'showcancelled'=151 387 | 'signed'=152 388 | 'small'=153 389 | 'specify'=154 390 | 'specparam'=155 391 | 'strong0'=156 392 | 'strong1'=157 393 | 'supply0'=158 394 | 'supply1'=159 395 | 'table'=160 396 | 'task'=161 397 | 'time'=162 398 | 'tran'=163 399 | 'tranif0'=164 400 | 'tranif1'=165 401 | 'tri'=166 402 | 'tri0'=167 403 | 'tri1'=168 404 | 'triand'=169 405 | 'trior'=170 406 | 'trireg'=171 407 | 'use'=172 408 | 'uwire'=173 409 | 'vectored'=174 410 | 'wait'=175 411 | 'wand'=176 412 | 'weak0'=177 413 | 'weak1'=178 414 | 'while'=179 415 | 'wire'=180 416 | 'wor'=181 417 | 'xnor'=182 418 | 'xor'=183 419 | '{'=184 420 | '|'=185 421 | '||'=186 422 | '}'=187 423 | '~'=188 424 | '~&'=189 425 | '~^'=190 426 | '~|'=191 427 | '-incdir'=203 428 | 'celldefine'=210 429 | 'end_keywords'=215 430 | 'endcelldefine'=216 431 | 'nounconnected_drive'=222 432 | 'resetall'=224 433 | -------------------------------------------------------------------------------- /src/antlr4_verilog/verilog/VerilogParser.tokens: -------------------------------------------------------------------------------- 1 | EM=1 2 | EMEQ=2 3 | EMEQEQ=3 4 | DQ=4 5 | HA=5 6 | DL=6 7 | DLFULLSKEW=7 8 | DLHOLD=8 9 | DLNOCHANGE=9 10 | DLPERIOD=10 11 | DLRECOVERY=11 12 | DLRECREM=12 13 | DLREMOVAL=13 14 | DLSETUP=14 15 | DLSETUPHOLD=15 16 | DLSKEW=16 17 | DLTIMESKEW=17 18 | DLWIDTH=18 19 | MO=19 20 | AM=20 21 | AMAM=21 22 | AMAMAM=22 23 | AP=23 24 | LP=24 25 | RP=25 26 | AS=26 27 | ASAS=27 28 | ASSL=28 29 | ASGT=29 30 | PL=30 31 | PLCL=31 32 | CO=32 33 | MI=33 34 | MICL=34 35 | MIGT=35 36 | DT=36 37 | SL=37 38 | SLAS=38 39 | SLSL=39 40 | CL=40 41 | SC=41 42 | LT=42 43 | LTLT=43 44 | LTLTLT=44 45 | LTEQ=45 46 | EQ=46 47 | EQEQ=47 48 | EQEQEQ=48 49 | EQGT=49 50 | GT=50 51 | GTEQ=51 52 | GTGT=52 53 | GTGTGT=53 54 | QM=54 55 | AT=55 56 | PATHPULSEDL=56 57 | LB=57 58 | RB=58 59 | CA=59 60 | CATI=60 61 | GA=61 62 | ALWAYS=62 63 | AND=63 64 | ASSIGN=64 65 | AUTOMATIC=65 66 | BEGIN=66 67 | BUF=67 68 | BUFIFZERO=68 69 | BUFIFONE=69 70 | CASE=70 71 | CASEX=71 72 | CASEZ=72 73 | CELL=73 74 | CMOS=74 75 | CONFIG=75 76 | DEASSIGN=76 77 | DEFAULT=77 78 | DEFPARAM=78 79 | DESIGN=79 80 | DISABLE=80 81 | EDGE=81 82 | ELSE=82 83 | END=83 84 | ENDCASE=84 85 | ENDCONFIG=85 86 | ENDFUNCTION=86 87 | ENDGENERATE=87 88 | ENDMODULE=88 89 | ENDPRIMITIVE=89 90 | ENDSPECIFY=90 91 | ENDTABLE=91 92 | ENDTASK=92 93 | EVENT=93 94 | FOR=94 95 | FORCE=95 96 | FOREVER=96 97 | FORK=97 98 | FUNCTION=98 99 | GENERATE=99 100 | GENVAR=100 101 | HIGHZZERO=101 102 | HIGHZONE=102 103 | IF=103 104 | IFNONE=104 105 | INCLUDE=105 106 | INITIAL=106 107 | INOUT=107 108 | INPUT=108 109 | INSTANCE=109 110 | INTEGER=110 111 | JOIN=111 112 | LARGE=112 113 | LIBLIST=113 114 | LIBRARY=114 115 | LOCALPARAM=115 116 | MACROMODULE=116 117 | MEDIUM=117 118 | MODULE=118 119 | NAND=119 120 | NEGEDGE=120 121 | NMOS=121 122 | NOR=122 123 | NOSHOWCANCELLED=123 124 | NOT=124 125 | NOTIFZERO=125 126 | NOTIFONE=126 127 | OR=127 128 | OUTPUT=128 129 | PARAMETER=129 130 | PMOS=130 131 | POSEDGE=131 132 | PRIMITIVE=132 133 | PULLZERO=133 134 | PULLONE=134 135 | PULLDOWN=135 136 | PULLUP=136 137 | PULSESTYLE_ONDETECT=137 138 | PULSESTYLE_ONEVENT=138 139 | RCMOS=139 140 | REAL=140 141 | REALTIME=141 142 | REG=142 143 | RELEASE=143 144 | REPEAT=144 145 | RNMOS=145 146 | RPMOS=146 147 | RTRAN=147 148 | RTRANIFZERO=148 149 | RTRANIFONE=149 150 | SCALARED=150 151 | SHOWCANCELLED=151 152 | SIGNED=152 153 | SMALL=153 154 | SPECIFY=154 155 | SPECPARAM=155 156 | STRONGZERO=156 157 | STRONGONE=157 158 | SUPPLYZERO=158 159 | SUPPLYONE=159 160 | TABLE=160 161 | TASK=161 162 | TIME=162 163 | TRAN=163 164 | TRANIFZERO=164 165 | TRANIFONE=165 166 | TRI=166 167 | TRIZERO=167 168 | TRIONE=168 169 | TRIAND=169 170 | TRIOR=170 171 | TRIREG=171 172 | USE=172 173 | UWIRE=173 174 | VECTORED=174 175 | WAIT=175 176 | WAND=176 177 | WEAKZERO=177 178 | WEAKONE=178 179 | WHILE=179 180 | WIRE=180 181 | WOR=181 182 | XNOR=182 183 | XOR=183 184 | LC=184 185 | VL=185 186 | VLVL=186 187 | RC=187 188 | TI=188 189 | TIAM=189 190 | TICA=190 191 | TIVL=191 192 | DECIMAL_NUMBER=192 193 | BINARY_NUMBER=193 194 | OCTAL_NUMBER=194 195 | HEX_NUMBER=195 196 | REAL_NUMBER=196 197 | STRING=197 198 | COMMENT=198 199 | ESCAPED_IDENTIFIER=199 200 | SIMPLE_IDENTIFIER=200 201 | SYSTEM_TF_IDENTIFIER=201 202 | WHITE_SPACE=202 203 | MIINCDIR=203 204 | FILE_PATH_SPEC=204 205 | OUTPUT_OR_LEVEL_SYMBOL=205 206 | LEVEL_ONLY_SYMBOL=206 207 | EDGE_SYMBOL=207 208 | EDGE_DESCRIPTOR=208 209 | BEGIN_KEYWORDS_DIRECTIVE=209 210 | CELLDEFINE_DIRECTIVE=210 211 | DEFAULT_NETTYPE_DIRECTIVE=211 212 | DEFINE_DIRECTIVE=212 213 | ELSE_DIRECTIVE=213 214 | ELSIF_DIRECTIVE=214 215 | END_KEYWORDS_DIRECTIVE=215 216 | ENDCELLDEFINE_DIRECTIVE=216 217 | ENDIF_DIRECTIVE=217 218 | IFDEF_DIRECTIVE=218 219 | IFNDEF_DIRECTIVE=219 220 | INCLUDE_DIRECTIVE=220 221 | LINE_DIRECTIVE=221 222 | NOUNCONNECTED_DRIVE_DIRECTIVE=222 223 | PRAGMA_DIRECTIVE=223 224 | RESETALL_DIRECTIVE=224 225 | TIMESCALE_DIRECTIVE=225 226 | UNCONNECTED_DRIVE_DIRECTIVE=226 227 | UNDEF_DIRECTIVE=227 228 | MACRO_USAGE=228 229 | DIRECTIVE_TEXT=229 230 | DIRECTIVE_IDENTIFIER=230 231 | DIRECTIVE_COMMENT=231 232 | DIRECTIVE_WHITE_SPACE=232 233 | DIRECTIVE_NEWLINE=233 234 | MACRO_TEXT=234 235 | MACRO_ESC_NEWLINE=235 236 | SOURCE_TEXT=236 237 | '!'=1 238 | '!='=2 239 | '!=='=3 240 | '"'=4 241 | '#'=5 242 | '$'=6 243 | '$fullskew'=7 244 | '$hold'=8 245 | '$nochange'=9 246 | '$period'=10 247 | '$recovery'=11 248 | '$recrem'=12 249 | '$removal'=13 250 | '$setup'=14 251 | '$setuphold'=15 252 | '$skew'=16 253 | '$timeskew'=17 254 | '$width'=18 255 | '%'=19 256 | '&'=20 257 | '&&'=21 258 | '&&&'=22 259 | '\''=23 260 | '('=24 261 | ')'=25 262 | '*'=26 263 | '**'=27 264 | '*/'=28 265 | '*>'=29 266 | '+'=30 267 | '+:'=31 268 | ','=32 269 | '-'=33 270 | '-:'=34 271 | '->'=35 272 | '.'=36 273 | '/'=37 274 | '/*'=38 275 | '//'=39 276 | ':'=40 277 | ';'=41 278 | '<'=42 279 | '<<'=43 280 | '<<<'=44 281 | '<='=45 282 | '='=46 283 | '=='=47 284 | '==='=48 285 | '=>'=49 286 | '>'=50 287 | '>='=51 288 | '>>'=52 289 | '>>>'=53 290 | '?'=54 291 | '@'=55 292 | 'PATHPULSE$'=56 293 | '['=57 294 | ']'=58 295 | '^'=59 296 | '^~'=60 297 | 'always'=62 298 | 'and'=63 299 | 'assign'=64 300 | 'automatic'=65 301 | 'begin'=66 302 | 'buf'=67 303 | 'bufif0'=68 304 | 'bufif1'=69 305 | 'case'=70 306 | 'casex'=71 307 | 'casez'=72 308 | 'cell'=73 309 | 'cmos'=74 310 | 'config'=75 311 | 'deassign'=76 312 | 'default'=77 313 | 'defparam'=78 314 | 'design'=79 315 | 'disable'=80 316 | 'edge'=81 317 | 'else'=82 318 | 'end'=83 319 | 'endcase'=84 320 | 'endconfig'=85 321 | 'endfunction'=86 322 | 'endgenerate'=87 323 | 'endmodule'=88 324 | 'endprimitive'=89 325 | 'endspecify'=90 326 | 'endtable'=91 327 | 'endtask'=92 328 | 'event'=93 329 | 'for'=94 330 | 'force'=95 331 | 'forever'=96 332 | 'fork'=97 333 | 'function'=98 334 | 'generate'=99 335 | 'genvar'=100 336 | 'highz0'=101 337 | 'highz1'=102 338 | 'if'=103 339 | 'ifnone'=104 340 | 'include'=105 341 | 'initial'=106 342 | 'inout'=107 343 | 'input'=108 344 | 'instance'=109 345 | 'integer'=110 346 | 'join'=111 347 | 'large'=112 348 | 'liblist'=113 349 | 'library'=114 350 | 'localparam'=115 351 | 'macromodule'=116 352 | 'medium'=117 353 | 'module'=118 354 | 'nand'=119 355 | 'negedge'=120 356 | 'nmos'=121 357 | 'nor'=122 358 | 'noshowcancelled'=123 359 | 'not'=124 360 | 'notif0'=125 361 | 'notif1'=126 362 | 'or'=127 363 | 'output'=128 364 | 'parameter'=129 365 | 'pmos'=130 366 | 'posedge'=131 367 | 'primitive'=132 368 | 'pull0'=133 369 | 'pull1'=134 370 | 'pulldown'=135 371 | 'pullup'=136 372 | 'pulsestyle_ondetect'=137 373 | 'pulsestyle_onevent'=138 374 | 'rcmos'=139 375 | 'real'=140 376 | 'realtime'=141 377 | 'reg'=142 378 | 'release'=143 379 | 'repeat'=144 380 | 'rnmos'=145 381 | 'rpmos'=146 382 | 'rtran'=147 383 | 'rtranif0'=148 384 | 'rtranif1'=149 385 | 'scalared'=150 386 | 'showcancelled'=151 387 | 'signed'=152 388 | 'small'=153 389 | 'specify'=154 390 | 'specparam'=155 391 | 'strong0'=156 392 | 'strong1'=157 393 | 'supply0'=158 394 | 'supply1'=159 395 | 'table'=160 396 | 'task'=161 397 | 'time'=162 398 | 'tran'=163 399 | 'tranif0'=164 400 | 'tranif1'=165 401 | 'tri'=166 402 | 'tri0'=167 403 | 'tri1'=168 404 | 'triand'=169 405 | 'trior'=170 406 | 'trireg'=171 407 | 'use'=172 408 | 'uwire'=173 409 | 'vectored'=174 410 | 'wait'=175 411 | 'wand'=176 412 | 'weak0'=177 413 | 'weak1'=178 414 | 'while'=179 415 | 'wire'=180 416 | 'wor'=181 417 | 'xnor'=182 418 | 'xor'=183 419 | '{'=184 420 | '|'=185 421 | '||'=186 422 | '}'=187 423 | '~'=188 424 | '~&'=189 425 | '~^'=190 426 | '~|'=191 427 | '-incdir'=203 428 | 'celldefine'=210 429 | 'end_keywords'=215 430 | 'endcelldefine'=216 431 | 'nounconnected_drive'=222 432 | 'resetall'=224 433 | -------------------------------------------------------------------------------- /src/antlr4_verilog/verilog/VerilogPreParser.interp: -------------------------------------------------------------------------------- 1 | token literal names: 2 | null 3 | '!' 4 | '!=' 5 | '!==' 6 | '"' 7 | '#' 8 | '$' 9 | '$fullskew' 10 | '$hold' 11 | '$nochange' 12 | '$period' 13 | '$recovery' 14 | '$recrem' 15 | '$removal' 16 | '$setup' 17 | '$setuphold' 18 | '$skew' 19 | '$timeskew' 20 | '$width' 21 | '%' 22 | '&' 23 | '&&' 24 | '&&&' 25 | '\'' 26 | '(' 27 | ')' 28 | '*' 29 | '**' 30 | '*/' 31 | '*>' 32 | '+' 33 | '+:' 34 | ',' 35 | '-' 36 | '-:' 37 | '->' 38 | '.' 39 | '/' 40 | '/*' 41 | '//' 42 | ':' 43 | ';' 44 | '<' 45 | '<<' 46 | '<<<' 47 | '<=' 48 | '=' 49 | '==' 50 | '===' 51 | '=>' 52 | '>' 53 | '>=' 54 | '>>' 55 | '>>>' 56 | '?' 57 | '@' 58 | 'PATHPULSE$' 59 | '[' 60 | ']' 61 | '^' 62 | '^~' 63 | null 64 | 'always' 65 | 'and' 66 | 'assign' 67 | 'automatic' 68 | 'begin' 69 | 'buf' 70 | 'bufif0' 71 | 'bufif1' 72 | 'case' 73 | 'casex' 74 | 'casez' 75 | 'cell' 76 | 'cmos' 77 | 'config' 78 | 'deassign' 79 | 'default' 80 | 'defparam' 81 | 'design' 82 | 'disable' 83 | 'edge' 84 | 'else' 85 | 'end' 86 | 'endcase' 87 | 'endconfig' 88 | 'endfunction' 89 | 'endgenerate' 90 | 'endmodule' 91 | 'endprimitive' 92 | 'endspecify' 93 | 'endtable' 94 | 'endtask' 95 | 'event' 96 | 'for' 97 | 'force' 98 | 'forever' 99 | 'fork' 100 | 'function' 101 | 'generate' 102 | 'genvar' 103 | 'highz0' 104 | 'highz1' 105 | 'if' 106 | 'ifnone' 107 | 'include' 108 | 'initial' 109 | 'inout' 110 | 'input' 111 | 'instance' 112 | 'integer' 113 | 'join' 114 | 'large' 115 | 'liblist' 116 | 'library' 117 | 'localparam' 118 | 'macromodule' 119 | 'medium' 120 | 'module' 121 | 'nand' 122 | 'negedge' 123 | 'nmos' 124 | 'nor' 125 | 'noshowcancelled' 126 | 'not' 127 | 'notif0' 128 | 'notif1' 129 | 'or' 130 | 'output' 131 | 'parameter' 132 | 'pmos' 133 | 'posedge' 134 | 'primitive' 135 | 'pull0' 136 | 'pull1' 137 | 'pulldown' 138 | 'pullup' 139 | 'pulsestyle_ondetect' 140 | 'pulsestyle_onevent' 141 | 'rcmos' 142 | 'real' 143 | 'realtime' 144 | 'reg' 145 | 'release' 146 | 'repeat' 147 | 'rnmos' 148 | 'rpmos' 149 | 'rtran' 150 | 'rtranif0' 151 | 'rtranif1' 152 | 'scalared' 153 | 'showcancelled' 154 | 'signed' 155 | 'small' 156 | 'specify' 157 | 'specparam' 158 | 'strong0' 159 | 'strong1' 160 | 'supply0' 161 | 'supply1' 162 | 'table' 163 | 'task' 164 | 'time' 165 | 'tran' 166 | 'tranif0' 167 | 'tranif1' 168 | 'tri' 169 | 'tri0' 170 | 'tri1' 171 | 'triand' 172 | 'trior' 173 | 'trireg' 174 | 'use' 175 | 'uwire' 176 | 'vectored' 177 | 'wait' 178 | 'wand' 179 | 'weak0' 180 | 'weak1' 181 | 'while' 182 | 'wire' 183 | 'wor' 184 | 'xnor' 185 | 'xor' 186 | '{' 187 | '|' 188 | '||' 189 | '}' 190 | '~' 191 | '~&' 192 | '~^' 193 | '~|' 194 | null 195 | null 196 | null 197 | null 198 | null 199 | null 200 | null 201 | null 202 | null 203 | null 204 | null 205 | '-incdir' 206 | null 207 | null 208 | null 209 | null 210 | null 211 | null 212 | 'celldefine' 213 | null 214 | null 215 | null 216 | null 217 | 'end_keywords' 218 | 'endcelldefine' 219 | null 220 | null 221 | null 222 | null 223 | null 224 | 'nounconnected_drive' 225 | null 226 | 'resetall' 227 | null 228 | null 229 | null 230 | null 231 | null 232 | null 233 | null 234 | null 235 | null 236 | null 237 | null 238 | null 239 | 240 | token symbolic names: 241 | null 242 | EM 243 | EMEQ 244 | EMEQEQ 245 | DQ 246 | HA 247 | DL 248 | DLFULLSKEW 249 | DLHOLD 250 | DLNOCHANGE 251 | DLPERIOD 252 | DLRECOVERY 253 | DLRECREM 254 | DLREMOVAL 255 | DLSETUP 256 | DLSETUPHOLD 257 | DLSKEW 258 | DLTIMESKEW 259 | DLWIDTH 260 | MO 261 | AM 262 | AMAM 263 | AMAMAM 264 | AP 265 | LP 266 | RP 267 | AS 268 | ASAS 269 | ASSL 270 | ASGT 271 | PL 272 | PLCL 273 | CO 274 | MI 275 | MICL 276 | MIGT 277 | DT 278 | SL 279 | SLAS 280 | SLSL 281 | CL 282 | SC 283 | LT 284 | LTLT 285 | LTLTLT 286 | LTEQ 287 | EQ 288 | EQEQ 289 | EQEQEQ 290 | EQGT 291 | GT 292 | GTEQ 293 | GTGT 294 | GTGTGT 295 | QM 296 | AT 297 | PATHPULSEDL 298 | LB 299 | RB 300 | CA 301 | CATI 302 | GA 303 | ALWAYS 304 | AND 305 | ASSIGN 306 | AUTOMATIC 307 | BEGIN 308 | BUF 309 | BUFIFZERO 310 | BUFIFONE 311 | CASE 312 | CASEX 313 | CASEZ 314 | CELL 315 | CMOS 316 | CONFIG 317 | DEASSIGN 318 | DEFAULT 319 | DEFPARAM 320 | DESIGN 321 | DISABLE 322 | EDGE 323 | ELSE 324 | END 325 | ENDCASE 326 | ENDCONFIG 327 | ENDFUNCTION 328 | ENDGENERATE 329 | ENDMODULE 330 | ENDPRIMITIVE 331 | ENDSPECIFY 332 | ENDTABLE 333 | ENDTASK 334 | EVENT 335 | FOR 336 | FORCE 337 | FOREVER 338 | FORK 339 | FUNCTION 340 | GENERATE 341 | GENVAR 342 | HIGHZZERO 343 | HIGHZONE 344 | IF 345 | IFNONE 346 | INCLUDE 347 | INITIAL 348 | INOUT 349 | INPUT 350 | INSTANCE 351 | INTEGER 352 | JOIN 353 | LARGE 354 | LIBLIST 355 | LIBRARY 356 | LOCALPARAM 357 | MACROMODULE 358 | MEDIUM 359 | MODULE 360 | NAND 361 | NEGEDGE 362 | NMOS 363 | NOR 364 | NOSHOWCANCELLED 365 | NOT 366 | NOTIFZERO 367 | NOTIFONE 368 | OR 369 | OUTPUT 370 | PARAMETER 371 | PMOS 372 | POSEDGE 373 | PRIMITIVE 374 | PULLZERO 375 | PULLONE 376 | PULLDOWN 377 | PULLUP 378 | PULSESTYLE_ONDETECT 379 | PULSESTYLE_ONEVENT 380 | RCMOS 381 | REAL 382 | REALTIME 383 | REG 384 | RELEASE 385 | REPEAT 386 | RNMOS 387 | RPMOS 388 | RTRAN 389 | RTRANIFZERO 390 | RTRANIFONE 391 | SCALARED 392 | SHOWCANCELLED 393 | SIGNED 394 | SMALL 395 | SPECIFY 396 | SPECPARAM 397 | STRONGZERO 398 | STRONGONE 399 | SUPPLYZERO 400 | SUPPLYONE 401 | TABLE 402 | TASK 403 | TIME 404 | TRAN 405 | TRANIFZERO 406 | TRANIFONE 407 | TRI 408 | TRIZERO 409 | TRIONE 410 | TRIAND 411 | TRIOR 412 | TRIREG 413 | USE 414 | UWIRE 415 | VECTORED 416 | WAIT 417 | WAND 418 | WEAKZERO 419 | WEAKONE 420 | WHILE 421 | WIRE 422 | WOR 423 | XNOR 424 | XOR 425 | LC 426 | VL 427 | VLVL 428 | RC 429 | TI 430 | TIAM 431 | TICA 432 | TIVL 433 | DECIMAL_NUMBER 434 | BINARY_NUMBER 435 | OCTAL_NUMBER 436 | HEX_NUMBER 437 | REAL_NUMBER 438 | STRING 439 | COMMENT 440 | ESCAPED_IDENTIFIER 441 | SIMPLE_IDENTIFIER 442 | SYSTEM_TF_IDENTIFIER 443 | WHITE_SPACE 444 | MIINCDIR 445 | FILE_PATH_SPEC 446 | OUTPUT_OR_LEVEL_SYMBOL 447 | LEVEL_ONLY_SYMBOL 448 | EDGE_SYMBOL 449 | EDGE_DESCRIPTOR 450 | BEGIN_KEYWORDS_DIRECTIVE 451 | CELLDEFINE_DIRECTIVE 452 | DEFAULT_NETTYPE_DIRECTIVE 453 | DEFINE_DIRECTIVE 454 | ELSE_DIRECTIVE 455 | ELSIF_DIRECTIVE 456 | END_KEYWORDS_DIRECTIVE 457 | ENDCELLDEFINE_DIRECTIVE 458 | ENDIF_DIRECTIVE 459 | IFDEF_DIRECTIVE 460 | IFNDEF_DIRECTIVE 461 | INCLUDE_DIRECTIVE 462 | LINE_DIRECTIVE 463 | NOUNCONNECTED_DRIVE_DIRECTIVE 464 | PRAGMA_DIRECTIVE 465 | RESETALL_DIRECTIVE 466 | TIMESCALE_DIRECTIVE 467 | UNCONNECTED_DRIVE_DIRECTIVE 468 | UNDEF_DIRECTIVE 469 | MACRO_USAGE 470 | DIRECTIVE_TEXT 471 | DIRECTIVE_IDENTIFIER 472 | DIRECTIVE_COMMENT 473 | DIRECTIVE_WHITE_SPACE 474 | DIRECTIVE_NEWLINE 475 | MACRO_TEXT 476 | MACRO_ESC_NEWLINE 477 | SOURCE_TEXT 478 | 479 | rule names: 480 | source_text 481 | compiler_directive 482 | begin_keywords_directive 483 | celldefine_directive 484 | default_nettype_directive 485 | endcelldefine_directive 486 | end_keywords_directive 487 | ifdef_directive 488 | ifndef_directive 489 | include_directive 490 | line_directive 491 | nounconnected_drive_directive 492 | pragma_directive 493 | resetall_directive 494 | text_macro_definition 495 | text_macro_usage 496 | timescale_directive 497 | unconnected_drive_directive 498 | undef_directive 499 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0, 0, 0, 191, 192, 1, 0, 0, 0, 192, 49, 1, 0, 0, 0, 193, 191, 1, 0, 0, 0, 194, 197, 5, 236, 0, 0, 195, 197, 3, 2, 1, 0, 196, 194, 1, 0, 0, 0, 196, 195, 1, 0, 0, 0, 197, 200, 1, 0, 0, 0, 198, 196, 1, 0, 0, 0, 198, 199, 1, 0, 0, 0, 199, 51, 1, 0, 0, 0, 200, 198, 1, 0, 0, 0, 201, 204, 5, 236, 0, 0, 202, 204, 3, 2, 1, 0, 203, 201, 1, 0, 0, 0, 203, 202, 1, 0, 0, 0, 204, 207, 1, 0, 0, 0, 205, 203, 1, 0, 0, 0, 205, 206, 1, 0, 0, 0, 206, 53, 1, 0, 0, 0, 207, 205, 1, 0, 0, 0, 208, 210, 7, 0, 0, 0, 209, 208, 1, 0, 0, 0, 210, 213, 1, 0, 0, 0, 211, 209, 1, 0, 0, 0, 211, 212, 1, 0, 0, 0, 212, 55, 1, 0, 0, 0, 213, 211, 1, 0, 0, 0, 15, 59, 79, 105, 109, 120, 124, 182, 184, 189, 191, 196, 198, 203, 205, 211] -------------------------------------------------------------------------------- /src/antlr4_verilog/verilog/VerilogPreParser.tokens: -------------------------------------------------------------------------------- 1 | EM=1 2 | EMEQ=2 3 | EMEQEQ=3 4 | DQ=4 5 | HA=5 6 | DL=6 7 | DLFULLSKEW=7 8 | DLHOLD=8 9 | DLNOCHANGE=9 10 | DLPERIOD=10 11 | DLRECOVERY=11 12 | DLRECREM=12 13 | DLREMOVAL=13 14 | DLSETUP=14 15 | DLSETUPHOLD=15 16 | DLSKEW=16 17 | DLTIMESKEW=17 18 | DLWIDTH=18 19 | MO=19 20 | AM=20 21 | AMAM=21 22 | AMAMAM=22 23 | AP=23 24 | LP=24 25 | RP=25 26 | AS=26 27 | ASAS=27 28 | ASSL=28 29 | ASGT=29 30 | PL=30 31 | PLCL=31 32 | CO=32 33 | MI=33 34 | MICL=34 35 | MIGT=35 36 | DT=36 37 | SL=37 38 | SLAS=38 39 | SLSL=39 40 | CL=40 41 | SC=41 42 | LT=42 43 | LTLT=43 44 | LTLTLT=44 45 | LTEQ=45 46 | EQ=46 47 | EQEQ=47 48 | EQEQEQ=48 49 | EQGT=49 50 | GT=50 51 | GTEQ=51 52 | GTGT=52 53 | GTGTGT=53 54 | QM=54 55 | AT=55 56 | PATHPULSEDL=56 57 | LB=57 58 | RB=58 59 | CA=59 60 | CATI=60 61 | GA=61 62 | ALWAYS=62 63 | AND=63 64 | ASSIGN=64 65 | AUTOMATIC=65 66 | BEGIN=66 67 | BUF=67 68 | BUFIFZERO=68 69 | BUFIFONE=69 70 | CASE=70 71 | CASEX=71 72 | CASEZ=72 73 | CELL=73 74 | CMOS=74 75 | CONFIG=75 76 | DEASSIGN=76 77 | DEFAULT=77 78 | DEFPARAM=78 79 | DESIGN=79 80 | DISABLE=80 81 | EDGE=81 82 | ELSE=82 83 | END=83 84 | ENDCASE=84 85 | ENDCONFIG=85 86 | ENDFUNCTION=86 87 | ENDGENERATE=87 88 | ENDMODULE=88 89 | ENDPRIMITIVE=89 90 | ENDSPECIFY=90 91 | ENDTABLE=91 92 | ENDTASK=92 93 | EVENT=93 94 | FOR=94 95 | FORCE=95 96 | FOREVER=96 97 | FORK=97 98 | FUNCTION=98 99 | GENERATE=99 100 | GENVAR=100 101 | HIGHZZERO=101 102 | HIGHZONE=102 103 | IF=103 104 | IFNONE=104 105 | INCLUDE=105 106 | INITIAL=106 107 | INOUT=107 108 | INPUT=108 109 | INSTANCE=109 110 | INTEGER=110 111 | JOIN=111 112 | LARGE=112 113 | LIBLIST=113 114 | LIBRARY=114 115 | LOCALPARAM=115 116 | MACROMODULE=116 117 | MEDIUM=117 118 | MODULE=118 119 | NAND=119 120 | NEGEDGE=120 121 | NMOS=121 122 | NOR=122 123 | NOSHOWCANCELLED=123 124 | NOT=124 125 | NOTIFZERO=125 126 | NOTIFONE=126 127 | OR=127 128 | OUTPUT=128 129 | PARAMETER=129 130 | PMOS=130 131 | POSEDGE=131 132 | PRIMITIVE=132 133 | PULLZERO=133 134 | PULLONE=134 135 | PULLDOWN=135 136 | PULLUP=136 137 | PULSESTYLE_ONDETECT=137 138 | PULSESTYLE_ONEVENT=138 139 | RCMOS=139 140 | REAL=140 141 | REALTIME=141 142 | REG=142 143 | RELEASE=143 144 | REPEAT=144 145 | RNMOS=145 146 | RPMOS=146 147 | RTRAN=147 148 | RTRANIFZERO=148 149 | RTRANIFONE=149 150 | SCALARED=150 151 | SHOWCANCELLED=151 152 | SIGNED=152 153 | SMALL=153 154 | SPECIFY=154 155 | SPECPARAM=155 156 | STRONGZERO=156 157 | STRONGONE=157 158 | SUPPLYZERO=158 159 | SUPPLYONE=159 160 | TABLE=160 161 | TASK=161 162 | TIME=162 163 | TRAN=163 164 | TRANIFZERO=164 165 | TRANIFONE=165 166 | TRI=166 167 | TRIZERO=167 168 | TRIONE=168 169 | TRIAND=169 170 | TRIOR=170 171 | TRIREG=171 172 | USE=172 173 | UWIRE=173 174 | VECTORED=174 175 | WAIT=175 176 | WAND=176 177 | WEAKZERO=177 178 | WEAKONE=178 179 | WHILE=179 180 | WIRE=180 181 | WOR=181 182 | XNOR=182 183 | XOR=183 184 | LC=184 185 | VL=185 186 | VLVL=186 187 | RC=187 188 | TI=188 189 | TIAM=189 190 | TICA=190 191 | TIVL=191 192 | DECIMAL_NUMBER=192 193 | BINARY_NUMBER=193 194 | OCTAL_NUMBER=194 195 | HEX_NUMBER=195 196 | REAL_NUMBER=196 197 | STRING=197 198 | COMMENT=198 199 | ESCAPED_IDENTIFIER=199 200 | SIMPLE_IDENTIFIER=200 201 | SYSTEM_TF_IDENTIFIER=201 202 | WHITE_SPACE=202 203 | MIINCDIR=203 204 | FILE_PATH_SPEC=204 205 | OUTPUT_OR_LEVEL_SYMBOL=205 206 | LEVEL_ONLY_SYMBOL=206 207 | EDGE_SYMBOL=207 208 | EDGE_DESCRIPTOR=208 209 | BEGIN_KEYWORDS_DIRECTIVE=209 210 | CELLDEFINE_DIRECTIVE=210 211 | DEFAULT_NETTYPE_DIRECTIVE=211 212 | DEFINE_DIRECTIVE=212 213 | ELSE_DIRECTIVE=213 214 | ELSIF_DIRECTIVE=214 215 | END_KEYWORDS_DIRECTIVE=215 216 | ENDCELLDEFINE_DIRECTIVE=216 217 | ENDIF_DIRECTIVE=217 218 | IFDEF_DIRECTIVE=218 219 | IFNDEF_DIRECTIVE=219 220 | INCLUDE_DIRECTIVE=220 221 | LINE_DIRECTIVE=221 222 | NOUNCONNECTED_DRIVE_DIRECTIVE=222 223 | PRAGMA_DIRECTIVE=223 224 | RESETALL_DIRECTIVE=224 225 | TIMESCALE_DIRECTIVE=225 226 | UNCONNECTED_DRIVE_DIRECTIVE=226 227 | UNDEF_DIRECTIVE=227 228 | MACRO_USAGE=228 229 | DIRECTIVE_TEXT=229 230 | DIRECTIVE_IDENTIFIER=230 231 | DIRECTIVE_COMMENT=231 232 | DIRECTIVE_WHITE_SPACE=232 233 | DIRECTIVE_NEWLINE=233 234 | MACRO_TEXT=234 235 | MACRO_ESC_NEWLINE=235 236 | SOURCE_TEXT=236 237 | '!'=1 238 | '!='=2 239 | '!=='=3 240 | '"'=4 241 | '#'=5 242 | '$'=6 243 | '$fullskew'=7 244 | '$hold'=8 245 | '$nochange'=9 246 | '$period'=10 247 | '$recovery'=11 248 | '$recrem'=12 249 | '$removal'=13 250 | '$setup'=14 251 | '$setuphold'=15 252 | '$skew'=16 253 | '$timeskew'=17 254 | '$width'=18 255 | '%'=19 256 | '&'=20 257 | '&&'=21 258 | '&&&'=22 259 | '\''=23 260 | '('=24 261 | ')'=25 262 | '*'=26 263 | '**'=27 264 | '*/'=28 265 | '*>'=29 266 | '+'=30 267 | '+:'=31 268 | ','=32 269 | '-'=33 270 | '-:'=34 271 | '->'=35 272 | '.'=36 273 | '/'=37 274 | '/*'=38 275 | '//'=39 276 | ':'=40 277 | ';'=41 278 | '<'=42 279 | '<<'=43 280 | '<<<'=44 281 | '<='=45 282 | '='=46 283 | '=='=47 284 | '==='=48 285 | '=>'=49 286 | '>'=50 287 | '>='=51 288 | '>>'=52 289 | '>>>'=53 290 | '?'=54 291 | '@'=55 292 | 'PATHPULSE$'=56 293 | '['=57 294 | ']'=58 295 | '^'=59 296 | '^~'=60 297 | 'always'=62 298 | 'and'=63 299 | 'assign'=64 300 | 'automatic'=65 301 | 'begin'=66 302 | 'buf'=67 303 | 'bufif0'=68 304 | 'bufif1'=69 305 | 'case'=70 306 | 'casex'=71 307 | 'casez'=72 308 | 'cell'=73 309 | 'cmos'=74 310 | 'config'=75 311 | 'deassign'=76 312 | 'default'=77 313 | 'defparam'=78 314 | 'design'=79 315 | 'disable'=80 316 | 'edge'=81 317 | 'else'=82 318 | 'end'=83 319 | 'endcase'=84 320 | 'endconfig'=85 321 | 'endfunction'=86 322 | 'endgenerate'=87 323 | 'endmodule'=88 324 | 'endprimitive'=89 325 | 'endspecify'=90 326 | 'endtable'=91 327 | 'endtask'=92 328 | 'event'=93 329 | 'for'=94 330 | 'force'=95 331 | 'forever'=96 332 | 'fork'=97 333 | 'function'=98 334 | 'generate'=99 335 | 'genvar'=100 336 | 'highz0'=101 337 | 'highz1'=102 338 | 'if'=103 339 | 'ifnone'=104 340 | 'include'=105 341 | 'initial'=106 342 | 'inout'=107 343 | 'input'=108 344 | 'instance'=109 345 | 'integer'=110 346 | 'join'=111 347 | 'large'=112 348 | 'liblist'=113 349 | 'library'=114 350 | 'localparam'=115 351 | 'macromodule'=116 352 | 'medium'=117 353 | 'module'=118 354 | 'nand'=119 355 | 'negedge'=120 356 | 'nmos'=121 357 | 'nor'=122 358 | 'noshowcancelled'=123 359 | 'not'=124 360 | 'notif0'=125 361 | 'notif1'=126 362 | 'or'=127 363 | 'output'=128 364 | 'parameter'=129 365 | 'pmos'=130 366 | 'posedge'=131 367 | 'primitive'=132 368 | 'pull0'=133 369 | 'pull1'=134 370 | 'pulldown'=135 371 | 'pullup'=136 372 | 'pulsestyle_ondetect'=137 373 | 'pulsestyle_onevent'=138 374 | 'rcmos'=139 375 | 'real'=140 376 | 'realtime'=141 377 | 'reg'=142 378 | 'release'=143 379 | 'repeat'=144 380 | 'rnmos'=145 381 | 'rpmos'=146 382 | 'rtran'=147 383 | 'rtranif0'=148 384 | 'rtranif1'=149 385 | 'scalared'=150 386 | 'showcancelled'=151 387 | 'signed'=152 388 | 'small'=153 389 | 'specify'=154 390 | 'specparam'=155 391 | 'strong0'=156 392 | 'strong1'=157 393 | 'supply0'=158 394 | 'supply1'=159 395 | 'table'=160 396 | 'task'=161 397 | 'time'=162 398 | 'tran'=163 399 | 'tranif0'=164 400 | 'tranif1'=165 401 | 'tri'=166 402 | 'tri0'=167 403 | 'tri1'=168 404 | 'triand'=169 405 | 'trior'=170 406 | 'trireg'=171 407 | 'use'=172 408 | 'uwire'=173 409 | 'vectored'=174 410 | 'wait'=175 411 | 'wand'=176 412 | 'weak0'=177 413 | 'weak1'=178 414 | 'while'=179 415 | 'wire'=180 416 | 'wor'=181 417 | 'xnor'=182 418 | 'xor'=183 419 | '{'=184 420 | '|'=185 421 | '||'=186 422 | '}'=187 423 | '~'=188 424 | '~&'=189 425 | '~^'=190 426 | '~|'=191 427 | '-incdir'=203 428 | 'celldefine'=210 429 | 'end_keywords'=215 430 | 'endcelldefine'=216 431 | 'nounconnected_drive'=222 432 | 'resetall'=224 433 | -------------------------------------------------------------------------------- /src/antlr4_verilog/verilog/VerilogPreParserListener.py: -------------------------------------------------------------------------------- 1 | # Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 by ANTLR 4.10.1 2 | from antlr4 import * 3 | if __name__ is not None and "." in __name__: 4 | from .VerilogPreParser import VerilogPreParser 5 | else: 6 | from VerilogPreParser import VerilogPreParser 7 | 8 | # This class defines a complete listener for a parse tree produced by VerilogPreParser. 9 | class VerilogPreParserListener(ParseTreeListener): 10 | 11 | # Enter a parse tree produced by VerilogPreParser#source_text. 12 | def enterSource_text(self, ctx:VerilogPreParser.Source_textContext): 13 | pass 14 | 15 | # Exit a parse tree produced by VerilogPreParser#source_text. 16 | def exitSource_text(self, ctx:VerilogPreParser.Source_textContext): 17 | pass 18 | 19 | 20 | # Enter a parse tree produced by VerilogPreParser#compiler_directive. 21 | def enterCompiler_directive(self, ctx:VerilogPreParser.Compiler_directiveContext): 22 | pass 23 | 24 | # Exit a parse tree produced by VerilogPreParser#compiler_directive. 25 | def exitCompiler_directive(self, ctx:VerilogPreParser.Compiler_directiveContext): 26 | pass 27 | 28 | 29 | # Enter a parse tree produced by VerilogPreParser#begin_keywords_directive. 30 | def enterBegin_keywords_directive(self, ctx:VerilogPreParser.Begin_keywords_directiveContext): 31 | pass 32 | 33 | # Exit a parse tree produced by VerilogPreParser#begin_keywords_directive. 34 | def exitBegin_keywords_directive(self, ctx:VerilogPreParser.Begin_keywords_directiveContext): 35 | pass 36 | 37 | 38 | # Enter a parse tree produced by VerilogPreParser#celldefine_directive. 39 | def enterCelldefine_directive(self, ctx:VerilogPreParser.Celldefine_directiveContext): 40 | pass 41 | 42 | # Exit a parse tree produced by VerilogPreParser#celldefine_directive. 43 | def exitCelldefine_directive(self, ctx:VerilogPreParser.Celldefine_directiveContext): 44 | pass 45 | 46 | 47 | # Enter a parse tree produced by VerilogPreParser#default_nettype_directive. 48 | def enterDefault_nettype_directive(self, ctx:VerilogPreParser.Default_nettype_directiveContext): 49 | pass 50 | 51 | # Exit a parse tree produced by VerilogPreParser#default_nettype_directive. 52 | def exitDefault_nettype_directive(self, ctx:VerilogPreParser.Default_nettype_directiveContext): 53 | pass 54 | 55 | 56 | # Enter a parse tree produced by VerilogPreParser#endcelldefine_directive. 57 | def enterEndcelldefine_directive(self, ctx:VerilogPreParser.Endcelldefine_directiveContext): 58 | pass 59 | 60 | # Exit a parse tree produced by VerilogPreParser#endcelldefine_directive. 61 | def exitEndcelldefine_directive(self, ctx:VerilogPreParser.Endcelldefine_directiveContext): 62 | pass 63 | 64 | 65 | # Enter a parse tree produced by VerilogPreParser#end_keywords_directive. 66 | def enterEnd_keywords_directive(self, ctx:VerilogPreParser.End_keywords_directiveContext): 67 | pass 68 | 69 | # Exit a parse tree produced by VerilogPreParser#end_keywords_directive. 70 | def exitEnd_keywords_directive(self, ctx:VerilogPreParser.End_keywords_directiveContext): 71 | pass 72 | 73 | 74 | # Enter a parse tree produced by VerilogPreParser#ifdef_directive. 75 | def enterIfdef_directive(self, ctx:VerilogPreParser.Ifdef_directiveContext): 76 | pass 77 | 78 | # Exit a parse tree produced by VerilogPreParser#ifdef_directive. 79 | def exitIfdef_directive(self, ctx:VerilogPreParser.Ifdef_directiveContext): 80 | pass 81 | 82 | 83 | # Enter a parse tree produced by VerilogPreParser#ifndef_directive. 84 | def enterIfndef_directive(self, ctx:VerilogPreParser.Ifndef_directiveContext): 85 | pass 86 | 87 | # Exit a parse tree produced by VerilogPreParser#ifndef_directive. 88 | def exitIfndef_directive(self, ctx:VerilogPreParser.Ifndef_directiveContext): 89 | pass 90 | 91 | 92 | # Enter a parse tree produced by VerilogPreParser#include_directive. 93 | def enterInclude_directive(self, ctx:VerilogPreParser.Include_directiveContext): 94 | pass 95 | 96 | # Exit a parse tree produced by VerilogPreParser#include_directive. 97 | def exitInclude_directive(self, ctx:VerilogPreParser.Include_directiveContext): 98 | pass 99 | 100 | 101 | # Enter a parse tree produced by VerilogPreParser#line_directive. 102 | def enterLine_directive(self, ctx:VerilogPreParser.Line_directiveContext): 103 | pass 104 | 105 | # Exit a parse tree produced by VerilogPreParser#line_directive. 106 | def exitLine_directive(self, ctx:VerilogPreParser.Line_directiveContext): 107 | pass 108 | 109 | 110 | # Enter a parse tree produced by VerilogPreParser#nounconnected_drive_directive. 111 | def enterNounconnected_drive_directive(self, ctx:VerilogPreParser.Nounconnected_drive_directiveContext): 112 | pass 113 | 114 | # Exit a parse tree produced by VerilogPreParser#nounconnected_drive_directive. 115 | def exitNounconnected_drive_directive(self, ctx:VerilogPreParser.Nounconnected_drive_directiveContext): 116 | pass 117 | 118 | 119 | # Enter a parse tree produced by VerilogPreParser#pragma_directive. 120 | def enterPragma_directive(self, ctx:VerilogPreParser.Pragma_directiveContext): 121 | pass 122 | 123 | # Exit a parse tree produced by VerilogPreParser#pragma_directive. 124 | def exitPragma_directive(self, ctx:VerilogPreParser.Pragma_directiveContext): 125 | pass 126 | 127 | 128 | # Enter a parse tree produced by VerilogPreParser#resetall_directive. 129 | def enterResetall_directive(self, ctx:VerilogPreParser.Resetall_directiveContext): 130 | pass 131 | 132 | # Exit a parse tree produced by VerilogPreParser#resetall_directive. 133 | def exitResetall_directive(self, ctx:VerilogPreParser.Resetall_directiveContext): 134 | pass 135 | 136 | 137 | # Enter a parse tree produced by VerilogPreParser#text_macro_definition. 138 | def enterText_macro_definition(self, ctx:VerilogPreParser.Text_macro_definitionContext): 139 | pass 140 | 141 | # Exit a parse tree produced by VerilogPreParser#text_macro_definition. 142 | def exitText_macro_definition(self, ctx:VerilogPreParser.Text_macro_definitionContext): 143 | pass 144 | 145 | 146 | # Enter a parse tree produced by VerilogPreParser#text_macro_usage. 147 | def enterText_macro_usage(self, ctx:VerilogPreParser.Text_macro_usageContext): 148 | pass 149 | 150 | # Exit a parse tree produced by VerilogPreParser#text_macro_usage. 151 | def exitText_macro_usage(self, ctx:VerilogPreParser.Text_macro_usageContext): 152 | pass 153 | 154 | 155 | # Enter a parse tree produced by VerilogPreParser#timescale_directive. 156 | def enterTimescale_directive(self, ctx:VerilogPreParser.Timescale_directiveContext): 157 | pass 158 | 159 | # Exit a parse tree produced by VerilogPreParser#timescale_directive. 160 | def exitTimescale_directive(self, ctx:VerilogPreParser.Timescale_directiveContext): 161 | pass 162 | 163 | 164 | # Enter a parse tree produced by VerilogPreParser#unconnected_drive_directive. 165 | def enterUnconnected_drive_directive(self, ctx:VerilogPreParser.Unconnected_drive_directiveContext): 166 | pass 167 | 168 | # Exit a parse tree produced by VerilogPreParser#unconnected_drive_directive. 169 | def exitUnconnected_drive_directive(self, ctx:VerilogPreParser.Unconnected_drive_directiveContext): 170 | pass 171 | 172 | 173 | # Enter a parse tree produced by VerilogPreParser#undef_directive. 174 | def enterUndef_directive(self, ctx:VerilogPreParser.Undef_directiveContext): 175 | pass 176 | 177 | # Exit a parse tree produced by VerilogPreParser#undef_directive. 178 | def exitUndef_directive(self, ctx:VerilogPreParser.Undef_directiveContext): 179 | pass 180 | 181 | 182 | # Enter a parse tree produced by VerilogPreParser#elsif_directive. 183 | def enterElsif_directive(self, ctx:VerilogPreParser.Elsif_directiveContext): 184 | pass 185 | 186 | # Exit a parse tree produced by VerilogPreParser#elsif_directive. 187 | def exitElsif_directive(self, ctx:VerilogPreParser.Elsif_directiveContext): 188 | pass 189 | 190 | 191 | # Enter a parse tree produced by VerilogPreParser#else_directive. 192 | def enterElse_directive(self, ctx:VerilogPreParser.Else_directiveContext): 193 | pass 194 | 195 | # Exit a parse tree produced by VerilogPreParser#else_directive. 196 | def exitElse_directive(self, ctx:VerilogPreParser.Else_directiveContext): 197 | pass 198 | 199 | 200 | # Enter a parse tree produced by VerilogPreParser#endif_directive. 201 | def enterEndif_directive(self, ctx:VerilogPreParser.Endif_directiveContext): 202 | pass 203 | 204 | # Exit a parse tree produced by VerilogPreParser#endif_directive. 205 | def exitEndif_directive(self, ctx:VerilogPreParser.Endif_directiveContext): 206 | pass 207 | 208 | 209 | # Enter a parse tree produced by VerilogPreParser#text_macro_identifier. 210 | def enterText_macro_identifier(self, ctx:VerilogPreParser.Text_macro_identifierContext): 211 | pass 212 | 213 | # Exit a parse tree produced by VerilogPreParser#text_macro_identifier. 214 | def exitText_macro_identifier(self, ctx:VerilogPreParser.Text_macro_identifierContext): 215 | pass 216 | 217 | 218 | # Enter a parse tree produced by VerilogPreParser#ifdef_group_of_lines. 219 | def enterIfdef_group_of_lines(self, ctx:VerilogPreParser.Ifdef_group_of_linesContext): 220 | pass 221 | 222 | # Exit a parse tree produced by VerilogPreParser#ifdef_group_of_lines. 223 | def exitIfdef_group_of_lines(self, ctx:VerilogPreParser.Ifdef_group_of_linesContext): 224 | pass 225 | 226 | 227 | # Enter a parse tree produced by VerilogPreParser#ifndef_group_of_lines. 228 | def enterIfndef_group_of_lines(self, ctx:VerilogPreParser.Ifndef_group_of_linesContext): 229 | pass 230 | 231 | # Exit a parse tree produced by VerilogPreParser#ifndef_group_of_lines. 232 | def exitIfndef_group_of_lines(self, ctx:VerilogPreParser.Ifndef_group_of_linesContext): 233 | pass 234 | 235 | 236 | # Enter a parse tree produced by VerilogPreParser#elsif_group_of_lines. 237 | def enterElsif_group_of_lines(self, ctx:VerilogPreParser.Elsif_group_of_linesContext): 238 | pass 239 | 240 | # Exit a parse tree produced by VerilogPreParser#elsif_group_of_lines. 241 | def exitElsif_group_of_lines(self, ctx:VerilogPreParser.Elsif_group_of_linesContext): 242 | pass 243 | 244 | 245 | # Enter a parse tree produced by VerilogPreParser#else_group_of_lines. 246 | def enterElse_group_of_lines(self, ctx:VerilogPreParser.Else_group_of_linesContext): 247 | pass 248 | 249 | # Exit a parse tree produced by VerilogPreParser#else_group_of_lines. 250 | def exitElse_group_of_lines(self, ctx:VerilogPreParser.Else_group_of_linesContext): 251 | pass 252 | 253 | 254 | # Enter a parse tree produced by VerilogPreParser#macro_text. 255 | def enterMacro_text(self, ctx:VerilogPreParser.Macro_textContext): 256 | pass 257 | 258 | # Exit a parse tree produced by VerilogPreParser#macro_text. 259 | def exitMacro_text(self, ctx:VerilogPreParser.Macro_textContext): 260 | pass 261 | 262 | 263 | 264 | del VerilogPreParser -------------------------------------------------------------------------------- /src/antlr4_verilog/verilog/VerilogPreParserVisitor.py: -------------------------------------------------------------------------------- 1 | # Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 by ANTLR 4.10.1 2 | from antlr4 import * 3 | if __name__ is not None and "." in __name__: 4 | from .VerilogPreParser import VerilogPreParser 5 | else: 6 | from VerilogPreParser import VerilogPreParser 7 | 8 | # This class defines a complete generic visitor for a parse tree produced by VerilogPreParser. 9 | 10 | class VerilogPreParserVisitor(ParseTreeVisitor): 11 | 12 | # Visit a parse tree produced by VerilogPreParser#source_text. 13 | def visitSource_text(self, ctx:VerilogPreParser.Source_textContext): 14 | return self.visitChildren(ctx) 15 | 16 | 17 | # Visit a parse tree produced by VerilogPreParser#compiler_directive. 18 | def visitCompiler_directive(self, ctx:VerilogPreParser.Compiler_directiveContext): 19 | return self.visitChildren(ctx) 20 | 21 | 22 | # Visit a parse tree produced by VerilogPreParser#begin_keywords_directive. 23 | def visitBegin_keywords_directive(self, ctx:VerilogPreParser.Begin_keywords_directiveContext): 24 | return self.visitChildren(ctx) 25 | 26 | 27 | # Visit a parse tree produced by VerilogPreParser#celldefine_directive. 28 | def visitCelldefine_directive(self, ctx:VerilogPreParser.Celldefine_directiveContext): 29 | return self.visitChildren(ctx) 30 | 31 | 32 | # Visit a parse tree produced by VerilogPreParser#default_nettype_directive. 33 | def visitDefault_nettype_directive(self, ctx:VerilogPreParser.Default_nettype_directiveContext): 34 | return self.visitChildren(ctx) 35 | 36 | 37 | # Visit a parse tree produced by VerilogPreParser#endcelldefine_directive. 38 | def visitEndcelldefine_directive(self, ctx:VerilogPreParser.Endcelldefine_directiveContext): 39 | return self.visitChildren(ctx) 40 | 41 | 42 | # Visit a parse tree produced by VerilogPreParser#end_keywords_directive. 43 | def visitEnd_keywords_directive(self, ctx:VerilogPreParser.End_keywords_directiveContext): 44 | return self.visitChildren(ctx) 45 | 46 | 47 | # Visit a parse tree produced by VerilogPreParser#ifdef_directive. 48 | def visitIfdef_directive(self, ctx:VerilogPreParser.Ifdef_directiveContext): 49 | return self.visitChildren(ctx) 50 | 51 | 52 | # Visit a parse tree produced by VerilogPreParser#ifndef_directive. 53 | def visitIfndef_directive(self, ctx:VerilogPreParser.Ifndef_directiveContext): 54 | return self.visitChildren(ctx) 55 | 56 | 57 | # Visit a parse tree produced by VerilogPreParser#include_directive. 58 | def visitInclude_directive(self, ctx:VerilogPreParser.Include_directiveContext): 59 | return self.visitChildren(ctx) 60 | 61 | 62 | # Visit a parse tree produced by VerilogPreParser#line_directive. 63 | def visitLine_directive(self, ctx:VerilogPreParser.Line_directiveContext): 64 | return self.visitChildren(ctx) 65 | 66 | 67 | # Visit a parse tree produced by VerilogPreParser#nounconnected_drive_directive. 68 | def visitNounconnected_drive_directive(self, ctx:VerilogPreParser.Nounconnected_drive_directiveContext): 69 | return self.visitChildren(ctx) 70 | 71 | 72 | # Visit a parse tree produced by VerilogPreParser#pragma_directive. 73 | def visitPragma_directive(self, ctx:VerilogPreParser.Pragma_directiveContext): 74 | return self.visitChildren(ctx) 75 | 76 | 77 | # Visit a parse tree produced by VerilogPreParser#resetall_directive. 78 | def visitResetall_directive(self, ctx:VerilogPreParser.Resetall_directiveContext): 79 | return self.visitChildren(ctx) 80 | 81 | 82 | # Visit a parse tree produced by VerilogPreParser#text_macro_definition. 83 | def visitText_macro_definition(self, ctx:VerilogPreParser.Text_macro_definitionContext): 84 | return self.visitChildren(ctx) 85 | 86 | 87 | # Visit a parse tree produced by VerilogPreParser#text_macro_usage. 88 | def visitText_macro_usage(self, ctx:VerilogPreParser.Text_macro_usageContext): 89 | return self.visitChildren(ctx) 90 | 91 | 92 | # Visit a parse tree produced by VerilogPreParser#timescale_directive. 93 | def visitTimescale_directive(self, ctx:VerilogPreParser.Timescale_directiveContext): 94 | return self.visitChildren(ctx) 95 | 96 | 97 | # Visit a parse tree produced by VerilogPreParser#unconnected_drive_directive. 98 | def visitUnconnected_drive_directive(self, ctx:VerilogPreParser.Unconnected_drive_directiveContext): 99 | return self.visitChildren(ctx) 100 | 101 | 102 | # Visit a parse tree produced by VerilogPreParser#undef_directive. 103 | def visitUndef_directive(self, ctx:VerilogPreParser.Undef_directiveContext): 104 | return self.visitChildren(ctx) 105 | 106 | 107 | # Visit a parse tree produced by VerilogPreParser#elsif_directive. 108 | def visitElsif_directive(self, ctx:VerilogPreParser.Elsif_directiveContext): 109 | return self.visitChildren(ctx) 110 | 111 | 112 | # Visit a parse tree produced by VerilogPreParser#else_directive. 113 | def visitElse_directive(self, ctx:VerilogPreParser.Else_directiveContext): 114 | return self.visitChildren(ctx) 115 | 116 | 117 | # Visit a parse tree produced by VerilogPreParser#endif_directive. 118 | def visitEndif_directive(self, ctx:VerilogPreParser.Endif_directiveContext): 119 | return self.visitChildren(ctx) 120 | 121 | 122 | # Visit a parse tree produced by VerilogPreParser#text_macro_identifier. 123 | def visitText_macro_identifier(self, ctx:VerilogPreParser.Text_macro_identifierContext): 124 | return self.visitChildren(ctx) 125 | 126 | 127 | # Visit a parse tree produced by VerilogPreParser#ifdef_group_of_lines. 128 | def visitIfdef_group_of_lines(self, ctx:VerilogPreParser.Ifdef_group_of_linesContext): 129 | return self.visitChildren(ctx) 130 | 131 | 132 | # Visit a parse tree produced by VerilogPreParser#ifndef_group_of_lines. 133 | def visitIfndef_group_of_lines(self, ctx:VerilogPreParser.Ifndef_group_of_linesContext): 134 | return self.visitChildren(ctx) 135 | 136 | 137 | # Visit a parse tree produced by VerilogPreParser#elsif_group_of_lines. 138 | def visitElsif_group_of_lines(self, ctx:VerilogPreParser.Elsif_group_of_linesContext): 139 | return self.visitChildren(ctx) 140 | 141 | 142 | # Visit a parse tree produced by VerilogPreParser#else_group_of_lines. 143 | def visitElse_group_of_lines(self, ctx:VerilogPreParser.Else_group_of_linesContext): 144 | return self.visitChildren(ctx) 145 | 146 | 147 | # Visit a parse tree produced by VerilogPreParser#macro_text. 148 | def visitMacro_text(self, ctx:VerilogPreParser.Macro_textContext): 149 | return self.visitChildren(ctx) 150 | 151 | 152 | 153 | del VerilogPreParser -------------------------------------------------------------------------------- /src/antlr4_verilog/verilog/__init__.py: -------------------------------------------------------------------------------- 1 | ''' 2 | Copyright (c) 2022 Marco Diniz Sousa 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | ''' 15 | 16 | from antlr4_verilog.verilog.VerilogLexer import VerilogLexer 17 | from antlr4_verilog.verilog.VerilogParser import VerilogParser 18 | from antlr4_verilog.verilog.VerilogParserListener import VerilogParserListener 19 | from antlr4_verilog.verilog.VerilogParserVisitor import VerilogParserVisitor 20 | from antlr4_verilog.verilog.VerilogPreParser import VerilogPreParser 21 | from antlr4_verilog.verilog.VerilogPreParserListener import VerilogPreParserListener 22 | from antlr4_verilog.verilog.VerilogPreParserVisitor import VerilogPreParserVisitor 23 | -------------------------------------------------------------------------------- /test/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mtdsousa/antlr4-verilog-python/e078ccafc5d83ea179b5e6f4b4373f5b5de57872/test/__init__.py -------------------------------------------------------------------------------- /test/test.py: -------------------------------------------------------------------------------- 1 | ''' 2 | Copyright (c) 2022 Marco Diniz Sousa 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | ''' 15 | import unittest 16 | 17 | from antlr4_verilog import InputStream, CommonTokenStream, ParseTreeWalker 18 | from antlr4_verilog.verilog import VerilogLexer, VerilogParser, VerilogParserListener 19 | from antlr4_verilog.systemverilog import SystemVerilogLexer, SystemVerilogParser, SystemVerilogParserListener 20 | 21 | class TestVerilog(unittest.TestCase): 22 | def setUp(self): 23 | design = ''' 24 | module ha(a, b, sum, c); 25 | input a, b; 26 | output sum, c; 27 | 28 | assign sum = a ^ b; 29 | assign c = a & b; 30 | endmodule 31 | ''' 32 | lexer = VerilogLexer(InputStream(design)) 33 | stream = CommonTokenStream(lexer) 34 | parser = VerilogParser(stream) 35 | self.tree = parser.source_text() 36 | self.walker = ParseTreeWalker() 37 | 38 | def test_module_identifier(self): 39 | class ModuleIdentifierListener(VerilogParserListener): 40 | def exitModule_declaration(self, ctx): 41 | self.identifier = ctx.module_identifier().getText() 42 | 43 | listener = ModuleIdentifierListener() 44 | self.walker.walk(listener, self.tree) 45 | self.assertEqual(listener.identifier, 'ha') 46 | 47 | def test_module_inputs(self): 48 | class ModuleInputListener(VerilogParserListener): 49 | def __init__(self): 50 | self.declarations = [] 51 | def exitInput_declaration(self, ctx): 52 | for child in ctx.list_of_port_identifiers().getChildren(): 53 | if isinstance(child, VerilogParser.Port_identifierContext): 54 | self.declarations.append(child.identifier().getText()) 55 | 56 | 57 | listener = ModuleInputListener() 58 | self.walker.walk(listener, self.tree) 59 | self.assertEqual(listener.declarations, ['a', 'b']) 60 | 61 | class TestSystemVerilog(unittest.TestCase): 62 | def setUp(self): 63 | design = ''' 64 | module hello; 65 | string s = "Hello"; 66 | initial begin 67 | $display("%s", s); 68 | end 69 | endmodule 70 | ''' 71 | lexer = SystemVerilogLexer(InputStream(design)) 72 | stream = CommonTokenStream(lexer) 73 | parser = SystemVerilogParser(stream) 74 | self.tree = parser.source_text() 75 | self.walker = ParseTreeWalker() 76 | 77 | def test_module_identifier(self): 78 | class ModuleIdentifierListener(SystemVerilogParserListener): 79 | def exitModule_declaration(self, ctx): 80 | self.identifier = ctx.module_ansi_header().module_identifier().getText() 81 | 82 | listener = ModuleIdentifierListener() 83 | self.walker.walk(listener, self.tree) 84 | self.assertEqual(listener.identifier, 'hello') 85 | 86 | def test_variable_assignment(self): 87 | class VariableAssignmentListener(SystemVerilogParserListener): 88 | def exitVariable_decl_assignment(self, ctx): 89 | self.identifier = ctx.variable_identifier().getText() 90 | self.expression = ctx.expression().getText() 91 | 92 | listener = VariableAssignmentListener() 93 | self.walker.walk(listener, self.tree) 94 | self.assertEqual(listener.identifier, 's') 95 | self.assertEqual(listener.expression, '"Hello"') 96 | 97 | def test_system_task(self): 98 | class SystemTaskListener(SystemVerilogParserListener): 99 | def exitSystem_tf_call(self, ctx): 100 | self.identifier = ctx.system_tf_identifier().getText() 101 | 102 | listener = SystemTaskListener() 103 | self.walker.walk(listener, self.tree) 104 | self.assertEqual(listener.identifier, '$display') 105 | 106 | if __name__ == '__main__': 107 | unittest.main() 108 | -------------------------------------------------------------------------------- /test/testrig/systemverilog.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mtdsousa/antlr4-verilog-python/e078ccafc5d83ea179b5e6f4b4373f5b5de57872/test/testrig/systemverilog.jar -------------------------------------------------------------------------------- /test/testrig/systemverilog/SystemVerilogLexer.tokens: -------------------------------------------------------------------------------- 1 | EM=1 2 | EMEQ=2 3 | EMEQEQ=3 4 | EMEQQM=4 5 | DQ=5 6 | DQDPIDQ=6 7 | DQDPIMICDQ=7 8 | HA=8 9 | HAHA=9 10 | HAMIHA=10 11 | HAEQHA=11 12 | DL=12 13 | DLERROR=13 14 | DLFATAL=14 15 | DLFULLSKEW=15 16 | DLHOLD=16 17 | DLINFO=17 18 | DLNOCHANGE=18 19 | DLPERIOD=19 20 | DLRECOVERY=20 21 | DLRECREM=21 22 | DLREMOVAL=22 23 | DLROOTDT=23 24 | DLSETUP=24 25 | DLSETUPHOLD=25 26 | DLSKEW=26 27 | DLTIMESKEW=27 28 | DLUNIT=28 29 | DLWARNING=29 30 | DLWIDTH=30 31 | MO=31 32 | MOEQ=32 33 | AM=33 34 | AMAM=34 35 | AMAMAM=35 36 | AMEQ=36 37 | AP=37 38 | LP=38 39 | RP=39 40 | AS=40 41 | ASAS=41 42 | ASSL=42 43 | ASCLCLAS=43 44 | ASEQ=44 45 | ASGT=45 46 | PL=46 47 | PLPL=47 48 | PLCL=48 49 | PLEQ=49 50 | CO=50 51 | MI=51 52 | MIMI=52 53 | MICL=53 54 | MIEQ=54 55 | MIGT=55 56 | MIGTGT=56 57 | DT=57 58 | DTAS=58 59 | SL=59 60 | SLAS=60 61 | SLSL=61 62 | SLEQ=62 63 | ONESTEP=63 64 | CL=64 65 | CLSL=65 66 | CLCL=66 67 | CLEQ=67 68 | SC=68 69 | LT=69 70 | LTMIGT=70 71 | LTLT=71 72 | LTLTLT=72 73 | LTLTLTEQ=73 74 | LTLTEQ=74 75 | LTEQ=75 76 | EQ=76 77 | EQEQ=77 78 | EQEQEQ=78 79 | EQEQQM=79 80 | EQGT=80 81 | GT=81 82 | GTEQ=82 83 | GTGT=83 84 | GTGTEQ=84 85 | GTGTGT=85 86 | GTGTGTEQ=86 87 | QM=87 88 | AT=88 89 | ATAT=89 90 | PATHPULSEDL=90 91 | LB=91 92 | RB=92 93 | CA=93 94 | CAEQ=94 95 | CATI=95 96 | GA=96 97 | ACCEPT_ON=97 98 | ALIAS=98 99 | ALWAYS=99 100 | ALWAYS_COMB=100 101 | ALWAYS_FF=101 102 | ALWAYS_LATCH=102 103 | AND=103 104 | ASSERT=104 105 | ASSIGN=105 106 | ASSUME=106 107 | AUTOMATIC=107 108 | BEFORE=108 109 | BEGIN=109 110 | BIND=110 111 | BINS=111 112 | BINSOF=112 113 | BIT=113 114 | BREAK=114 115 | BUF=115 116 | BUFIFZERO=116 117 | BUFIFONE=117 118 | BYTE=118 119 | CASE=119 120 | CASEX=120 121 | CASEZ=121 122 | CELL=122 123 | CHANDLE=123 124 | CHECKER=124 125 | CLASS=125 126 | CLOCKING=126 127 | CMOS=127 128 | CONFIG=128 129 | CONST=129 130 | CONSTRAINT=130 131 | CONTEXT=131 132 | CONTINUE=132 133 | COVER=133 134 | COVERGROUP=134 135 | COVERPOINT=135 136 | CROSS=136 137 | DEASSIGN=137 138 | DEFAULT=138 139 | DEFPARAM=139 140 | DESIGN=140 141 | DISABLE=141 142 | DIST=142 143 | DO=143 144 | EDGE=144 145 | ELSE=145 146 | END=146 147 | ENDCASE=147 148 | ENDCHECKER=148 149 | ENDCLASS=149 150 | ENDCLOCKING=150 151 | ENDCONFIG=151 152 | ENDFUNCTION=152 153 | ENDGENERATE=153 154 | ENDGROUP=154 155 | ENDINTERFACE=155 156 | ENDMODULE=156 157 | ENDPACKAGE=157 158 | ENDPRIMITIVE=158 159 | ENDPROGRAM=159 160 | ENDPROPERTY=160 161 | ENDSEQUENCE=161 162 | ENDSPECIFY=162 163 | ENDTABLE=163 164 | ENDTASK=164 165 | ENUM=165 166 | EVENT=166 167 | EXPECT=167 168 | EXPORT=168 169 | EXTENDS=169 170 | EXTERN=170 171 | FINAL=171 172 | FIRST_MATCH=172 173 | FOR=173 174 | FORCE=174 175 | FOREACH=175 176 | FOREVER=176 177 | FORK=177 178 | FORKJOIN=178 179 | FUNCTION=179 180 | GENERATE=180 181 | GENVAR=181 182 | GLOBAL=182 183 | HIGHZZERO=183 184 | HIGHZONE=184 185 | IF=185 186 | IFF=186 187 | IFNONE=187 188 | IGNORE_BINS=188 189 | ILLEGAL_BINS=189 190 | IMPLEMENTS=190 191 | IMPLIES=191 192 | IMPORT=192 193 | INCLUDE=193 194 | INITIAL=194 195 | INOUT=195 196 | INPUT=196 197 | INSIDE=197 198 | INSTANCE=198 199 | INT=199 200 | INTEGER=200 201 | INTERCONNECT=201 202 | INTERFACE=202 203 | INTERSECT=203 204 | JOIN=204 205 | JOIN_ANY=205 206 | JOIN_NONE=206 207 | LARGE=207 208 | LET=208 209 | LIBLIST=209 210 | LIBRARY=210 211 | LOCAL=211 212 | LOCALPARAM=212 213 | LOGIC=213 214 | LONGINT=214 215 | MACROMODULE=215 216 | MATCHES=216 217 | MEDIUM=217 218 | MODPORT=218 219 | MODULE=219 220 | NAND=220 221 | NEGEDGE=221 222 | NETTYPE=222 223 | NEW=223 224 | NEXTTIME=224 225 | NMOS=225 226 | NOR=226 227 | NOSHOWCANCELLED=227 228 | NOT=228 229 | NOTIFZERO=229 230 | NOTIFONE=230 231 | NULL=231 232 | OPTIONDT=232 233 | OR=233 234 | OUTPUT=234 235 | PACKAGE=235 236 | PACKED=236 237 | PARAMETER=237 238 | PMOS=238 239 | POSEDGE=239 240 | PRIMITIVE=240 241 | PRIORITY=241 242 | PROGRAM=242 243 | PROPERTY=243 244 | PROTECTED=244 245 | PULLZERO=245 246 | PULLONE=246 247 | PULLDOWN=247 248 | PULLUP=248 249 | PULSESTYLE_ONDETECT=249 250 | PULSESTYLE_ONEVENT=250 251 | PURE=251 252 | RAND=252 253 | RANDC=253 254 | RANDCASE=254 255 | RANDOMIZE=255 256 | RANDSEQUENCE=256 257 | RCMOS=257 258 | REAL=258 259 | REALTIME=259 260 | REF=260 261 | REG=261 262 | REJECT_ON=262 263 | RELEASE=263 264 | REPEAT=264 265 | RESTRICT=265 266 | RETURN=266 267 | RNMOS=267 268 | RPMOS=268 269 | RTRAN=269 270 | RTRANIFZERO=270 271 | RTRANIFONE=271 272 | S_ALWAYS=272 273 | S_EVENTUALLY=273 274 | S_NEXTTIME=274 275 | S_UNTIL=275 276 | S_UNTIL_WITH=276 277 | SAMPLE=277 278 | SCALARED=278 279 | SEQUENCE=279 280 | SHORTINT=280 281 | SHORTREAL=281 282 | SHOWCANCELLED=282 283 | SIGNED=283 284 | SMALL=284 285 | SOFT=285 286 | SOLVE=286 287 | SPECIFY=287 288 | SPECPARAM=288 289 | STATIC=289 290 | STD=290 291 | STRING=291 292 | STRONG=292 293 | STRONGZERO=293 294 | STRONGONE=294 295 | STRUCT=295 296 | SUPER=296 297 | SUPPLYZERO=297 298 | SUPPLYONE=298 299 | SYNC_ACCEPT_ON=299 300 | SYNC_REJECT_ON=300 301 | TABLE=301 302 | TAGGED=302 303 | TASK=303 304 | THIS=304 305 | THROUGHOUT=305 306 | TIME=306 307 | TIMEPRECISION=307 308 | TIMEUNIT=308 309 | TRAN=309 310 | TRANIFZERO=310 311 | TRANIFONE=311 312 | TRI=312 313 | TRIZERO=313 314 | TRIONE=314 315 | TRIAND=315 316 | TRIOR=316 317 | TRIREG=317 318 | TYPE=318 319 | TYPE_OPTIONDT=319 320 | TYPEDEF=320 321 | UNION=321 322 | UNIQUE=322 323 | UNIQUEZERO=323 324 | UNSIGNED=324 325 | UNTIL=325 326 | UNTIL_WITH=326 327 | UNTYPED=327 328 | USE=328 329 | UWIRE=329 330 | VAR=330 331 | VECTORED=331 332 | VIRTUAL=332 333 | VOID=333 334 | WAIT=334 335 | WAIT_ORDER=335 336 | WAND=336 337 | WEAK=337 338 | WEAKZERO=338 339 | WEAKONE=339 340 | WHILE=340 341 | WILDCARD=341 342 | WIRE=342 343 | WITH=343 344 | WITHIN=344 345 | WOR=345 346 | XNOR=346 347 | XOR=347 348 | LC=348 349 | VL=349 350 | VLMIGT=350 351 | VLEQ=351 352 | VLEQGT=352 353 | VLVL=353 354 | RC=354 355 | TI=355 356 | TIAM=356 357 | TICA=357 358 | TIVL=358 359 | TIME_LITERAL=359 360 | DECIMAL_NUMBER=360 361 | BINARY_NUMBER=361 362 | OCTAL_NUMBER=362 363 | HEX_NUMBER=363 364 | REAL_NUMBER=364 365 | UNBASED_UNSIZED_LITERAL=365 366 | STRING_LITERAL=366 367 | COMMENT=367 368 | ESCAPED_IDENTIFIER=368 369 | SIMPLE_IDENTIFIER=369 370 | SYSTEM_TF_IDENTIFIER=370 371 | WHITE_SPACE=371 372 | ZERO_OR_ONE_Z_OR_X=372 373 | MIINCDIR=373 374 | FILE_PATH_SPEC=374 375 | OUTPUT_OR_LEVEL_SYMBOL=375 376 | LEVEL_ONLY_SYMBOL=376 377 | EDGE_SYMBOL=377 378 | FILE_DIRECTIVE=378 379 | LINE_DIRECTIVE_=379 380 | BEGIN_KEYWORDS_DIRECTIVE=380 381 | CELLDEFINE_DIRECTIVE=381 382 | DEFAULT_NETTYPE_DIRECTIVE=382 383 | DEFINE_DIRECTIVE=383 384 | ELSE_DIRECTIVE=384 385 | ELSIF_DIRECTIVE=385 386 | END_KEYWORDS_DIRECTIVE=386 387 | ENDCELLDEFINE_DIRECTIVE=387 388 | ENDIF_DIRECTIVE=388 389 | IFDEF_DIRECTIVE=389 390 | IFNDEF_DIRECTIVE=390 391 | INCLUDE_DIRECTIVE=391 392 | LINE_DIRECTIVE=392 393 | NOUNCONNECTED_DRIVE_DIRECTIVE=393 394 | PRAGMA_DIRECTIVE=394 395 | RESETALL_DIRECTIVE=395 396 | TIMESCALE_DIRECTIVE=396 397 | UNCONNECTED_DRIVE_DIRECTIVE=397 398 | UNDEF_DIRECTIVE=398 399 | UNDEFINEALL_DIRECTIVE=399 400 | MACRO_USAGE=400 401 | DIRECTIVE_TEXT=401 402 | DIRECTIVE_IDENTIFIER=402 403 | DIRECTIVE_COMMENT=403 404 | DIRECTIVE_WHITE_SPACE=404 405 | DIRECTIVE_NEWLINE=405 406 | MACRO_TEXT=406 407 | MACRO_ESC_NEWLINE=407 408 | SOURCE_TEXT=408 409 | '!'=1 410 | '!='=2 411 | '!=='=3 412 | '!=?'=4 413 | '"'=5 414 | '"DPI"'=6 415 | '"DPI-C"'=7 416 | '#'=8 417 | '##'=9 418 | '#-#'=10 419 | '#=#'=11 420 | '$'=12 421 | '$error'=13 422 | '$fatal'=14 423 | '$fullskew'=15 424 | '$hold'=16 425 | '$info'=17 426 | '$nochange'=18 427 | '$period'=19 428 | '$recovery'=20 429 | '$recrem'=21 430 | '$removal'=22 431 | '$root.'=23 432 | '$setup'=24 433 | '$setuphold'=25 434 | '$skew'=26 435 | '$timeskew'=27 436 | '$unit'=28 437 | '$warning'=29 438 | '$width'=30 439 | '%'=31 440 | '%='=32 441 | '&'=33 442 | '&&'=34 443 | '&&&'=35 444 | '&='=36 445 | '\''=37 446 | '('=38 447 | ')'=39 448 | '*'=40 449 | '**'=41 450 | '*/'=42 451 | '*::*'=43 452 | '*='=44 453 | '*>'=45 454 | '+'=46 455 | '++'=47 456 | '+:'=48 457 | '+='=49 458 | ','=50 459 | '-'=51 460 | '--'=52 461 | '-:'=53 462 | '-='=54 463 | '->'=55 464 | '->>'=56 465 | '.'=57 466 | '.*'=58 467 | '/'=59 468 | '/*'=60 469 | '//'=61 470 | '/='=62 471 | '1step'=63 472 | ':'=64 473 | ':/'=65 474 | '::'=66 475 | ':='=67 476 | ';'=68 477 | '<'=69 478 | '<->'=70 479 | '<<'=71 480 | '<<<'=72 481 | '<<<='=73 482 | '<<='=74 483 | '<='=75 484 | '='=76 485 | '=='=77 486 | '==='=78 487 | '==?'=79 488 | '=>'=80 489 | '>'=81 490 | '>='=82 491 | '>>'=83 492 | '>>='=84 493 | '>>>'=85 494 | '>>>='=86 495 | '?'=87 496 | '@'=88 497 | '@@'=89 498 | 'PATHPULSE$'=90 499 | '['=91 500 | ']'=92 501 | '^'=93 502 | '^='=94 503 | '^~'=95 504 | 'accept_on'=97 505 | 'alias'=98 506 | 'always'=99 507 | 'always_comb'=100 508 | 'always_ff'=101 509 | 'always_latch'=102 510 | 'and'=103 511 | 'assert'=104 512 | 'assign'=105 513 | 'assume'=106 514 | 'automatic'=107 515 | 'before'=108 516 | 'begin'=109 517 | 'bind'=110 518 | 'bins'=111 519 | 'binsof'=112 520 | 'bit'=113 521 | 'break'=114 522 | 'buf'=115 523 | 'bufif0'=116 524 | 'bufif1'=117 525 | 'byte'=118 526 | 'case'=119 527 | 'casex'=120 528 | 'casez'=121 529 | 'cell'=122 530 | 'chandle'=123 531 | 'checker'=124 532 | 'class'=125 533 | 'clocking'=126 534 | 'cmos'=127 535 | 'config'=128 536 | 'const'=129 537 | 'constraint'=130 538 | 'context'=131 539 | 'continue'=132 540 | 'cover'=133 541 | 'covergroup'=134 542 | 'coverpoint'=135 543 | 'cross'=136 544 | 'deassign'=137 545 | 'default'=138 546 | 'defparam'=139 547 | 'design'=140 548 | 'disable'=141 549 | 'dist'=142 550 | 'do'=143 551 | 'edge'=144 552 | 'else'=145 553 | 'end'=146 554 | 'endcase'=147 555 | 'endchecker'=148 556 | 'endclass'=149 557 | 'endclocking'=150 558 | 'endconfig'=151 559 | 'endfunction'=152 560 | 'endgenerate'=153 561 | 'endgroup'=154 562 | 'endinterface'=155 563 | 'endmodule'=156 564 | 'endpackage'=157 565 | 'endprimitive'=158 566 | 'endprogram'=159 567 | 'endproperty'=160 568 | 'endsequence'=161 569 | 'endspecify'=162 570 | 'endtable'=163 571 | 'endtask'=164 572 | 'enum'=165 573 | 'event'=166 574 | 'expect'=167 575 | 'export'=168 576 | 'extends'=169 577 | 'extern'=170 578 | 'final'=171 579 | 'first_match'=172 580 | 'for'=173 581 | 'force'=174 582 | 'foreach'=175 583 | 'forever'=176 584 | 'fork'=177 585 | 'forkjoin'=178 586 | 'function'=179 587 | 'generate'=180 588 | 'genvar'=181 589 | 'global'=182 590 | 'highz0'=183 591 | 'highz1'=184 592 | 'if'=185 593 | 'iff'=186 594 | 'ifnone'=187 595 | 'ignore_bins'=188 596 | 'illegal_bins'=189 597 | 'implements'=190 598 | 'implies'=191 599 | 'import'=192 600 | 'include'=193 601 | 'initial'=194 602 | 'inout'=195 603 | 'input'=196 604 | 'inside'=197 605 | 'instance'=198 606 | 'int'=199 607 | 'integer'=200 608 | 'interconnect'=201 609 | 'interface'=202 610 | 'intersect'=203 611 | 'join'=204 612 | 'join_any'=205 613 | 'join_none'=206 614 | 'large'=207 615 | 'let'=208 616 | 'liblist'=209 617 | 'library'=210 618 | 'local'=211 619 | 'localparam'=212 620 | 'logic'=213 621 | 'longint'=214 622 | 'macromodule'=215 623 | 'matches'=216 624 | 'medium'=217 625 | 'modport'=218 626 | 'module'=219 627 | 'nand'=220 628 | 'negedge'=221 629 | 'nettype'=222 630 | 'new'=223 631 | 'nexttime'=224 632 | 'nmos'=225 633 | 'nor'=226 634 | 'noshowcancelled'=227 635 | 'not'=228 636 | 'notif0'=229 637 | 'notif1'=230 638 | 'null'=231 639 | 'option.'=232 640 | 'or'=233 641 | 'output'=234 642 | 'package'=235 643 | 'packed'=236 644 | 'parameter'=237 645 | 'pmos'=238 646 | 'posedge'=239 647 | 'primitive'=240 648 | 'priority'=241 649 | 'program'=242 650 | 'property'=243 651 | 'protected'=244 652 | 'pull0'=245 653 | 'pull1'=246 654 | 'pulldown'=247 655 | 'pullup'=248 656 | 'pulsestyle_ondetect'=249 657 | 'pulsestyle_onevent'=250 658 | 'pure'=251 659 | 'rand'=252 660 | 'randc'=253 661 | 'randcase'=254 662 | 'randomize'=255 663 | 'randsequence'=256 664 | 'rcmos'=257 665 | 'real'=258 666 | 'realtime'=259 667 | 'ref'=260 668 | 'reg'=261 669 | 'reject_on'=262 670 | 'release'=263 671 | 'repeat'=264 672 | 'restrict'=265 673 | 'return'=266 674 | 'rnmos'=267 675 | 'rpmos'=268 676 | 'rtran'=269 677 | 'rtranif0'=270 678 | 'rtranif1'=271 679 | 's_always'=272 680 | 's_eventually'=273 681 | 's_nexttime'=274 682 | 's_until'=275 683 | 's_until_with'=276 684 | 'sample'=277 685 | 'scalared'=278 686 | 'sequence'=279 687 | 'shortint'=280 688 | 'shortreal'=281 689 | 'showcancelled'=282 690 | 'signed'=283 691 | 'small'=284 692 | 'soft'=285 693 | 'solve'=286 694 | 'specify'=287 695 | 'specparam'=288 696 | 'static'=289 697 | 'std'=290 698 | 'string'=291 699 | 'strong'=292 700 | 'strong0'=293 701 | 'strong1'=294 702 | 'struct'=295 703 | 'super'=296 704 | 'supply0'=297 705 | 'supply1'=298 706 | 'sync_accept_on'=299 707 | 'sync_reject_on'=300 708 | 'table'=301 709 | 'tagged'=302 710 | 'task'=303 711 | 'this'=304 712 | 'throughout'=305 713 | 'time'=306 714 | 'timeprecision'=307 715 | 'timeunit'=308 716 | 'tran'=309 717 | 'tranif0'=310 718 | 'tranif1'=311 719 | 'tri'=312 720 | 'tri0'=313 721 | 'tri1'=314 722 | 'triand'=315 723 | 'trior'=316 724 | 'trireg'=317 725 | 'type'=318 726 | 'type_option.'=319 727 | 'typedef'=320 728 | 'union'=321 729 | 'unique'=322 730 | 'unique0'=323 731 | 'unsigned'=324 732 | 'until'=325 733 | 'until_with'=326 734 | 'untyped'=327 735 | 'use'=328 736 | 'uwire'=329 737 | 'var'=330 738 | 'vectored'=331 739 | 'virtual'=332 740 | 'void'=333 741 | 'wait'=334 742 | 'wait_order'=335 743 | 'wand'=336 744 | 'weak'=337 745 | 'weak0'=338 746 | 'weak1'=339 747 | 'while'=340 748 | 'wildcard'=341 749 | 'wire'=342 750 | 'with'=343 751 | 'within'=344 752 | 'wor'=345 753 | 'xnor'=346 754 | 'xor'=347 755 | '{'=348 756 | '|'=349 757 | '|->'=350 758 | '|='=351 759 | '|=>'=352 760 | '||'=353 761 | '}'=354 762 | '~'=355 763 | '~&'=356 764 | '~^'=357 765 | '~|'=358 766 | '-incdir'=373 767 | '__FILE__'=378 768 | '__LINE__'=379 769 | 'celldefine'=381 770 | 'end_keywords'=386 771 | 'endcelldefine'=387 772 | 'nounconnected_drive'=393 773 | 'resetall'=395 774 | 'undefineall'=399 775 | -------------------------------------------------------------------------------- /test/testrig/systemverilog/SystemVerilogParser.tokens: -------------------------------------------------------------------------------- 1 | EM=1 2 | EMEQ=2 3 | EMEQEQ=3 4 | EMEQQM=4 5 | DQ=5 6 | DQDPIDQ=6 7 | DQDPIMICDQ=7 8 | HA=8 9 | HAHA=9 10 | HAMIHA=10 11 | HAEQHA=11 12 | DL=12 13 | DLERROR=13 14 | DLFATAL=14 15 | DLFULLSKEW=15 16 | DLHOLD=16 17 | DLINFO=17 18 | DLNOCHANGE=18 19 | DLPERIOD=19 20 | DLRECOVERY=20 21 | DLRECREM=21 22 | DLREMOVAL=22 23 | DLROOTDT=23 24 | DLSETUP=24 25 | DLSETUPHOLD=25 26 | DLSKEW=26 27 | DLTIMESKEW=27 28 | DLUNIT=28 29 | DLWARNING=29 30 | DLWIDTH=30 31 | MO=31 32 | MOEQ=32 33 | AM=33 34 | AMAM=34 35 | AMAMAM=35 36 | AMEQ=36 37 | AP=37 38 | LP=38 39 | RP=39 40 | AS=40 41 | ASAS=41 42 | ASSL=42 43 | ASCLCLAS=43 44 | ASEQ=44 45 | ASGT=45 46 | PL=46 47 | PLPL=47 48 | PLCL=48 49 | PLEQ=49 50 | CO=50 51 | MI=51 52 | MIMI=52 53 | MICL=53 54 | MIEQ=54 55 | MIGT=55 56 | MIGTGT=56 57 | DT=57 58 | DTAS=58 59 | SL=59 60 | SLAS=60 61 | SLSL=61 62 | SLEQ=62 63 | ONESTEP=63 64 | CL=64 65 | CLSL=65 66 | CLCL=66 67 | CLEQ=67 68 | SC=68 69 | LT=69 70 | LTMIGT=70 71 | LTLT=71 72 | LTLTLT=72 73 | LTLTLTEQ=73 74 | LTLTEQ=74 75 | LTEQ=75 76 | EQ=76 77 | EQEQ=77 78 | EQEQEQ=78 79 | EQEQQM=79 80 | EQGT=80 81 | GT=81 82 | GTEQ=82 83 | GTGT=83 84 | GTGTEQ=84 85 | GTGTGT=85 86 | GTGTGTEQ=86 87 | QM=87 88 | AT=88 89 | ATAT=89 90 | PATHPULSEDL=90 91 | LB=91 92 | RB=92 93 | CA=93 94 | CAEQ=94 95 | CATI=95 96 | GA=96 97 | ACCEPT_ON=97 98 | ALIAS=98 99 | ALWAYS=99 100 | ALWAYS_COMB=100 101 | ALWAYS_FF=101 102 | ALWAYS_LATCH=102 103 | AND=103 104 | ASSERT=104 105 | ASSIGN=105 106 | ASSUME=106 107 | AUTOMATIC=107 108 | BEFORE=108 109 | BEGIN=109 110 | BIND=110 111 | BINS=111 112 | BINSOF=112 113 | BIT=113 114 | BREAK=114 115 | BUF=115 116 | BUFIFZERO=116 117 | BUFIFONE=117 118 | BYTE=118 119 | CASE=119 120 | CASEX=120 121 | CASEZ=121 122 | CELL=122 123 | CHANDLE=123 124 | CHECKER=124 125 | CLASS=125 126 | CLOCKING=126 127 | CMOS=127 128 | CONFIG=128 129 | CONST=129 130 | CONSTRAINT=130 131 | CONTEXT=131 132 | CONTINUE=132 133 | COVER=133 134 | COVERGROUP=134 135 | COVERPOINT=135 136 | CROSS=136 137 | DEASSIGN=137 138 | DEFAULT=138 139 | DEFPARAM=139 140 | DESIGN=140 141 | DISABLE=141 142 | DIST=142 143 | DO=143 144 | EDGE=144 145 | ELSE=145 146 | END=146 147 | ENDCASE=147 148 | ENDCHECKER=148 149 | ENDCLASS=149 150 | ENDCLOCKING=150 151 | ENDCONFIG=151 152 | ENDFUNCTION=152 153 | ENDGENERATE=153 154 | ENDGROUP=154 155 | ENDINTERFACE=155 156 | ENDMODULE=156 157 | ENDPACKAGE=157 158 | ENDPRIMITIVE=158 159 | ENDPROGRAM=159 160 | ENDPROPERTY=160 161 | ENDSEQUENCE=161 162 | ENDSPECIFY=162 163 | ENDTABLE=163 164 | ENDTASK=164 165 | ENUM=165 166 | EVENT=166 167 | EXPECT=167 168 | EXPORT=168 169 | EXTENDS=169 170 | EXTERN=170 171 | FINAL=171 172 | FIRST_MATCH=172 173 | FOR=173 174 | FORCE=174 175 | FOREACH=175 176 | FOREVER=176 177 | FORK=177 178 | FORKJOIN=178 179 | FUNCTION=179 180 | GENERATE=180 181 | GENVAR=181 182 | GLOBAL=182 183 | HIGHZZERO=183 184 | HIGHZONE=184 185 | IF=185 186 | IFF=186 187 | IFNONE=187 188 | IGNORE_BINS=188 189 | ILLEGAL_BINS=189 190 | IMPLEMENTS=190 191 | IMPLIES=191 192 | IMPORT=192 193 | INCLUDE=193 194 | INITIAL=194 195 | INOUT=195 196 | INPUT=196 197 | INSIDE=197 198 | INSTANCE=198 199 | INT=199 200 | INTEGER=200 201 | INTERCONNECT=201 202 | INTERFACE=202 203 | INTERSECT=203 204 | JOIN=204 205 | JOIN_ANY=205 206 | JOIN_NONE=206 207 | LARGE=207 208 | LET=208 209 | LIBLIST=209 210 | LIBRARY=210 211 | LOCAL=211 212 | LOCALPARAM=212 213 | LOGIC=213 214 | LONGINT=214 215 | MACROMODULE=215 216 | MATCHES=216 217 | MEDIUM=217 218 | MODPORT=218 219 | MODULE=219 220 | NAND=220 221 | NEGEDGE=221 222 | NETTYPE=222 223 | NEW=223 224 | NEXTTIME=224 225 | NMOS=225 226 | NOR=226 227 | NOSHOWCANCELLED=227 228 | NOT=228 229 | NOTIFZERO=229 230 | NOTIFONE=230 231 | NULL=231 232 | OPTIONDT=232 233 | OR=233 234 | OUTPUT=234 235 | PACKAGE=235 236 | PACKED=236 237 | PARAMETER=237 238 | PMOS=238 239 | POSEDGE=239 240 | PRIMITIVE=240 241 | PRIORITY=241 242 | PROGRAM=242 243 | PROPERTY=243 244 | PROTECTED=244 245 | PULLZERO=245 246 | PULLONE=246 247 | PULLDOWN=247 248 | PULLUP=248 249 | PULSESTYLE_ONDETECT=249 250 | PULSESTYLE_ONEVENT=250 251 | PURE=251 252 | RAND=252 253 | RANDC=253 254 | RANDCASE=254 255 | RANDOMIZE=255 256 | RANDSEQUENCE=256 257 | RCMOS=257 258 | REAL=258 259 | REALTIME=259 260 | REF=260 261 | REG=261 262 | REJECT_ON=262 263 | RELEASE=263 264 | REPEAT=264 265 | RESTRICT=265 266 | RETURN=266 267 | RNMOS=267 268 | RPMOS=268 269 | RTRAN=269 270 | RTRANIFZERO=270 271 | RTRANIFONE=271 272 | S_ALWAYS=272 273 | S_EVENTUALLY=273 274 | S_NEXTTIME=274 275 | S_UNTIL=275 276 | S_UNTIL_WITH=276 277 | SAMPLE=277 278 | SCALARED=278 279 | SEQUENCE=279 280 | SHORTINT=280 281 | SHORTREAL=281 282 | SHOWCANCELLED=282 283 | SIGNED=283 284 | SMALL=284 285 | SOFT=285 286 | SOLVE=286 287 | SPECIFY=287 288 | SPECPARAM=288 289 | STATIC=289 290 | STD=290 291 | STRING=291 292 | STRONG=292 293 | STRONGZERO=293 294 | STRONGONE=294 295 | STRUCT=295 296 | SUPER=296 297 | SUPPLYZERO=297 298 | SUPPLYONE=298 299 | SYNC_ACCEPT_ON=299 300 | SYNC_REJECT_ON=300 301 | TABLE=301 302 | TAGGED=302 303 | TASK=303 304 | THIS=304 305 | THROUGHOUT=305 306 | TIME=306 307 | TIMEPRECISION=307 308 | TIMEUNIT=308 309 | TRAN=309 310 | TRANIFZERO=310 311 | TRANIFONE=311 312 | TRI=312 313 | TRIZERO=313 314 | TRIONE=314 315 | TRIAND=315 316 | TRIOR=316 317 | TRIREG=317 318 | TYPE=318 319 | TYPE_OPTIONDT=319 320 | TYPEDEF=320 321 | UNION=321 322 | UNIQUE=322 323 | UNIQUEZERO=323 324 | UNSIGNED=324 325 | UNTIL=325 326 | UNTIL_WITH=326 327 | UNTYPED=327 328 | USE=328 329 | UWIRE=329 330 | VAR=330 331 | VECTORED=331 332 | VIRTUAL=332 333 | VOID=333 334 | WAIT=334 335 | WAIT_ORDER=335 336 | WAND=336 337 | WEAK=337 338 | WEAKZERO=338 339 | WEAKONE=339 340 | WHILE=340 341 | WILDCARD=341 342 | WIRE=342 343 | WITH=343 344 | WITHIN=344 345 | WOR=345 346 | XNOR=346 347 | XOR=347 348 | LC=348 349 | VL=349 350 | VLMIGT=350 351 | VLEQ=351 352 | VLEQGT=352 353 | VLVL=353 354 | RC=354 355 | TI=355 356 | TIAM=356 357 | TICA=357 358 | TIVL=358 359 | TIME_LITERAL=359 360 | DECIMAL_NUMBER=360 361 | BINARY_NUMBER=361 362 | OCTAL_NUMBER=362 363 | HEX_NUMBER=363 364 | REAL_NUMBER=364 365 | UNBASED_UNSIZED_LITERAL=365 366 | STRING_LITERAL=366 367 | COMMENT=367 368 | ESCAPED_IDENTIFIER=368 369 | SIMPLE_IDENTIFIER=369 370 | SYSTEM_TF_IDENTIFIER=370 371 | WHITE_SPACE=371 372 | ZERO_OR_ONE_Z_OR_X=372 373 | MIINCDIR=373 374 | FILE_PATH_SPEC=374 375 | OUTPUT_OR_LEVEL_SYMBOL=375 376 | LEVEL_ONLY_SYMBOL=376 377 | EDGE_SYMBOL=377 378 | FILE_DIRECTIVE=378 379 | LINE_DIRECTIVE_=379 380 | BEGIN_KEYWORDS_DIRECTIVE=380 381 | CELLDEFINE_DIRECTIVE=381 382 | DEFAULT_NETTYPE_DIRECTIVE=382 383 | DEFINE_DIRECTIVE=383 384 | ELSE_DIRECTIVE=384 385 | ELSIF_DIRECTIVE=385 386 | END_KEYWORDS_DIRECTIVE=386 387 | ENDCELLDEFINE_DIRECTIVE=387 388 | ENDIF_DIRECTIVE=388 389 | IFDEF_DIRECTIVE=389 390 | IFNDEF_DIRECTIVE=390 391 | INCLUDE_DIRECTIVE=391 392 | LINE_DIRECTIVE=392 393 | NOUNCONNECTED_DRIVE_DIRECTIVE=393 394 | PRAGMA_DIRECTIVE=394 395 | RESETALL_DIRECTIVE=395 396 | TIMESCALE_DIRECTIVE=396 397 | UNCONNECTED_DRIVE_DIRECTIVE=397 398 | UNDEF_DIRECTIVE=398 399 | UNDEFINEALL_DIRECTIVE=399 400 | MACRO_USAGE=400 401 | DIRECTIVE_TEXT=401 402 | DIRECTIVE_IDENTIFIER=402 403 | DIRECTIVE_COMMENT=403 404 | DIRECTIVE_WHITE_SPACE=404 405 | DIRECTIVE_NEWLINE=405 406 | MACRO_TEXT=406 407 | MACRO_ESC_NEWLINE=407 408 | SOURCE_TEXT=408 409 | '!'=1 410 | '!='=2 411 | '!=='=3 412 | '!=?'=4 413 | '"'=5 414 | '"DPI"'=6 415 | '"DPI-C"'=7 416 | '#'=8 417 | '##'=9 418 | '#-#'=10 419 | '#=#'=11 420 | '$'=12 421 | '$error'=13 422 | '$fatal'=14 423 | '$fullskew'=15 424 | '$hold'=16 425 | '$info'=17 426 | '$nochange'=18 427 | '$period'=19 428 | '$recovery'=20 429 | '$recrem'=21 430 | '$removal'=22 431 | '$root.'=23 432 | '$setup'=24 433 | '$setuphold'=25 434 | '$skew'=26 435 | '$timeskew'=27 436 | '$unit'=28 437 | '$warning'=29 438 | '$width'=30 439 | '%'=31 440 | '%='=32 441 | '&'=33 442 | '&&'=34 443 | '&&&'=35 444 | '&='=36 445 | '\''=37 446 | '('=38 447 | ')'=39 448 | '*'=40 449 | '**'=41 450 | '*/'=42 451 | '*::*'=43 452 | '*='=44 453 | '*>'=45 454 | '+'=46 455 | '++'=47 456 | '+:'=48 457 | '+='=49 458 | ','=50 459 | '-'=51 460 | '--'=52 461 | '-:'=53 462 | '-='=54 463 | '->'=55 464 | '->>'=56 465 | '.'=57 466 | '.*'=58 467 | '/'=59 468 | '/*'=60 469 | '//'=61 470 | '/='=62 471 | '1step'=63 472 | ':'=64 473 | ':/'=65 474 | '::'=66 475 | ':='=67 476 | ';'=68 477 | '<'=69 478 | '<->'=70 479 | '<<'=71 480 | '<<<'=72 481 | '<<<='=73 482 | '<<='=74 483 | '<='=75 484 | '='=76 485 | '=='=77 486 | '==='=78 487 | '==?'=79 488 | '=>'=80 489 | '>'=81 490 | '>='=82 491 | '>>'=83 492 | '>>='=84 493 | '>>>'=85 494 | '>>>='=86 495 | '?'=87 496 | '@'=88 497 | '@@'=89 498 | 'PATHPULSE$'=90 499 | '['=91 500 | ']'=92 501 | '^'=93 502 | '^='=94 503 | '^~'=95 504 | 'accept_on'=97 505 | 'alias'=98 506 | 'always'=99 507 | 'always_comb'=100 508 | 'always_ff'=101 509 | 'always_latch'=102 510 | 'and'=103 511 | 'assert'=104 512 | 'assign'=105 513 | 'assume'=106 514 | 'automatic'=107 515 | 'before'=108 516 | 'begin'=109 517 | 'bind'=110 518 | 'bins'=111 519 | 'binsof'=112 520 | 'bit'=113 521 | 'break'=114 522 | 'buf'=115 523 | 'bufif0'=116 524 | 'bufif1'=117 525 | 'byte'=118 526 | 'case'=119 527 | 'casex'=120 528 | 'casez'=121 529 | 'cell'=122 530 | 'chandle'=123 531 | 'checker'=124 532 | 'class'=125 533 | 'clocking'=126 534 | 'cmos'=127 535 | 'config'=128 536 | 'const'=129 537 | 'constraint'=130 538 | 'context'=131 539 | 'continue'=132 540 | 'cover'=133 541 | 'covergroup'=134 542 | 'coverpoint'=135 543 | 'cross'=136 544 | 'deassign'=137 545 | 'default'=138 546 | 'defparam'=139 547 | 'design'=140 548 | 'disable'=141 549 | 'dist'=142 550 | 'do'=143 551 | 'edge'=144 552 | 'else'=145 553 | 'end'=146 554 | 'endcase'=147 555 | 'endchecker'=148 556 | 'endclass'=149 557 | 'endclocking'=150 558 | 'endconfig'=151 559 | 'endfunction'=152 560 | 'endgenerate'=153 561 | 'endgroup'=154 562 | 'endinterface'=155 563 | 'endmodule'=156 564 | 'endpackage'=157 565 | 'endprimitive'=158 566 | 'endprogram'=159 567 | 'endproperty'=160 568 | 'endsequence'=161 569 | 'endspecify'=162 570 | 'endtable'=163 571 | 'endtask'=164 572 | 'enum'=165 573 | 'event'=166 574 | 'expect'=167 575 | 'export'=168 576 | 'extends'=169 577 | 'extern'=170 578 | 'final'=171 579 | 'first_match'=172 580 | 'for'=173 581 | 'force'=174 582 | 'foreach'=175 583 | 'forever'=176 584 | 'fork'=177 585 | 'forkjoin'=178 586 | 'function'=179 587 | 'generate'=180 588 | 'genvar'=181 589 | 'global'=182 590 | 'highz0'=183 591 | 'highz1'=184 592 | 'if'=185 593 | 'iff'=186 594 | 'ifnone'=187 595 | 'ignore_bins'=188 596 | 'illegal_bins'=189 597 | 'implements'=190 598 | 'implies'=191 599 | 'import'=192 600 | 'include'=193 601 | 'initial'=194 602 | 'inout'=195 603 | 'input'=196 604 | 'inside'=197 605 | 'instance'=198 606 | 'int'=199 607 | 'integer'=200 608 | 'interconnect'=201 609 | 'interface'=202 610 | 'intersect'=203 611 | 'join'=204 612 | 'join_any'=205 613 | 'join_none'=206 614 | 'large'=207 615 | 'let'=208 616 | 'liblist'=209 617 | 'library'=210 618 | 'local'=211 619 | 'localparam'=212 620 | 'logic'=213 621 | 'longint'=214 622 | 'macromodule'=215 623 | 'matches'=216 624 | 'medium'=217 625 | 'modport'=218 626 | 'module'=219 627 | 'nand'=220 628 | 'negedge'=221 629 | 'nettype'=222 630 | 'new'=223 631 | 'nexttime'=224 632 | 'nmos'=225 633 | 'nor'=226 634 | 'noshowcancelled'=227 635 | 'not'=228 636 | 'notif0'=229 637 | 'notif1'=230 638 | 'null'=231 639 | 'option.'=232 640 | 'or'=233 641 | 'output'=234 642 | 'package'=235 643 | 'packed'=236 644 | 'parameter'=237 645 | 'pmos'=238 646 | 'posedge'=239 647 | 'primitive'=240 648 | 'priority'=241 649 | 'program'=242 650 | 'property'=243 651 | 'protected'=244 652 | 'pull0'=245 653 | 'pull1'=246 654 | 'pulldown'=247 655 | 'pullup'=248 656 | 'pulsestyle_ondetect'=249 657 | 'pulsestyle_onevent'=250 658 | 'pure'=251 659 | 'rand'=252 660 | 'randc'=253 661 | 'randcase'=254 662 | 'randomize'=255 663 | 'randsequence'=256 664 | 'rcmos'=257 665 | 'real'=258 666 | 'realtime'=259 667 | 'ref'=260 668 | 'reg'=261 669 | 'reject_on'=262 670 | 'release'=263 671 | 'repeat'=264 672 | 'restrict'=265 673 | 'return'=266 674 | 'rnmos'=267 675 | 'rpmos'=268 676 | 'rtran'=269 677 | 'rtranif0'=270 678 | 'rtranif1'=271 679 | 's_always'=272 680 | 's_eventually'=273 681 | 's_nexttime'=274 682 | 's_until'=275 683 | 's_until_with'=276 684 | 'sample'=277 685 | 'scalared'=278 686 | 'sequence'=279 687 | 'shortint'=280 688 | 'shortreal'=281 689 | 'showcancelled'=282 690 | 'signed'=283 691 | 'small'=284 692 | 'soft'=285 693 | 'solve'=286 694 | 'specify'=287 695 | 'specparam'=288 696 | 'static'=289 697 | 'std'=290 698 | 'string'=291 699 | 'strong'=292 700 | 'strong0'=293 701 | 'strong1'=294 702 | 'struct'=295 703 | 'super'=296 704 | 'supply0'=297 705 | 'supply1'=298 706 | 'sync_accept_on'=299 707 | 'sync_reject_on'=300 708 | 'table'=301 709 | 'tagged'=302 710 | 'task'=303 711 | 'this'=304 712 | 'throughout'=305 713 | 'time'=306 714 | 'timeprecision'=307 715 | 'timeunit'=308 716 | 'tran'=309 717 | 'tranif0'=310 718 | 'tranif1'=311 719 | 'tri'=312 720 | 'tri0'=313 721 | 'tri1'=314 722 | 'triand'=315 723 | 'trior'=316 724 | 'trireg'=317 725 | 'type'=318 726 | 'type_option.'=319 727 | 'typedef'=320 728 | 'union'=321 729 | 'unique'=322 730 | 'unique0'=323 731 | 'unsigned'=324 732 | 'until'=325 733 | 'until_with'=326 734 | 'untyped'=327 735 | 'use'=328 736 | 'uwire'=329 737 | 'var'=330 738 | 'vectored'=331 739 | 'virtual'=332 740 | 'void'=333 741 | 'wait'=334 742 | 'wait_order'=335 743 | 'wand'=336 744 | 'weak'=337 745 | 'weak0'=338 746 | 'weak1'=339 747 | 'while'=340 748 | 'wildcard'=341 749 | 'wire'=342 750 | 'with'=343 751 | 'within'=344 752 | 'wor'=345 753 | 'xnor'=346 754 | 'xor'=347 755 | '{'=348 756 | '|'=349 757 | '|->'=350 758 | '|='=351 759 | '|=>'=352 760 | '||'=353 761 | '}'=354 762 | '~'=355 763 | '~&'=356 764 | '~^'=357 765 | '~|'=358 766 | '-incdir'=373 767 | '__FILE__'=378 768 | '__LINE__'=379 769 | 'celldefine'=381 770 | 'end_keywords'=386 771 | 'endcelldefine'=387 772 | 'nounconnected_drive'=393 773 | 'resetall'=395 774 | 'undefineall'=399 775 | -------------------------------------------------------------------------------- /test/testrig/systemverilog/SystemVerilogPreParserBaseVisitor.java: -------------------------------------------------------------------------------- 1 | // Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/systemverilog/SystemVerilogPreParser.g4 by ANTLR 4.10.1 2 | import org.antlr.v4.runtime.tree.AbstractParseTreeVisitor; 3 | 4 | /** 5 | * This class provides an empty implementation of {@link SystemVerilogPreParserVisitor}, 6 | * which can be extended to create a visitor which only needs to handle a subset 7 | * of the available methods. 8 | * 9 | * @param The return type of the visit operation. Use {@link Void} for 10 | * operations with no return type. 11 | */ 12 | public class SystemVerilogPreParserBaseVisitor extends AbstractParseTreeVisitor implements SystemVerilogPreParserVisitor { 13 | /** 14 | * {@inheritDoc} 15 | * 16 | *

The default implementation returns the result of calling 17 | * {@link #visitChildren} on {@code ctx}.

18 | */ 19 | @Override public T visitSource_text(SystemVerilogPreParser.Source_textContext ctx) { return visitChildren(ctx); } 20 | /** 21 | * {@inheritDoc} 22 | * 23 | *

The default implementation returns the result of calling 24 | * {@link #visitChildren} on {@code ctx}.

25 | */ 26 | @Override public T visitCompiler_directive(SystemVerilogPreParser.Compiler_directiveContext ctx) { return visitChildren(ctx); } 27 | /** 28 | * {@inheritDoc} 29 | * 30 | *

The default implementation returns the result of calling 31 | * {@link #visitChildren} on {@code ctx}.

32 | */ 33 | @Override public T visitFile_directive(SystemVerilogPreParser.File_directiveContext ctx) { return visitChildren(ctx); } 34 | /** 35 | * {@inheritDoc} 36 | * 37 | *

The default implementation returns the result of calling 38 | * {@link #visitChildren} on {@code ctx}.

39 | */ 40 | @Override public T visitLine_directive_(SystemVerilogPreParser.Line_directive_Context ctx) { return visitChildren(ctx); } 41 | /** 42 | * {@inheritDoc} 43 | * 44 | *

The default implementation returns the result of calling 45 | * {@link #visitChildren} on {@code ctx}.

46 | */ 47 | @Override public T visitBegin_keywords_directive(SystemVerilogPreParser.Begin_keywords_directiveContext ctx) { return visitChildren(ctx); } 48 | /** 49 | * {@inheritDoc} 50 | * 51 | *

The default implementation returns the result of calling 52 | * {@link #visitChildren} on {@code ctx}.

53 | */ 54 | @Override public T visitCelldefine_directive(SystemVerilogPreParser.Celldefine_directiveContext ctx) { return visitChildren(ctx); } 55 | /** 56 | * {@inheritDoc} 57 | * 58 | *

The default implementation returns the result of calling 59 | * {@link #visitChildren} on {@code ctx}.

60 | */ 61 | @Override public T visitDefault_nettype_directive(SystemVerilogPreParser.Default_nettype_directiveContext ctx) { return visitChildren(ctx); } 62 | /** 63 | * {@inheritDoc} 64 | * 65 | *

The default implementation returns the result of calling 66 | * {@link #visitChildren} on {@code ctx}.

67 | */ 68 | @Override public T visitEndcelldefine_directive(SystemVerilogPreParser.Endcelldefine_directiveContext ctx) { return visitChildren(ctx); } 69 | /** 70 | * {@inheritDoc} 71 | * 72 | *

The default implementation returns the result of calling 73 | * {@link #visitChildren} on {@code ctx}.

74 | */ 75 | @Override public T visitEnd_keywords_directive(SystemVerilogPreParser.End_keywords_directiveContext ctx) { return visitChildren(ctx); } 76 | /** 77 | * {@inheritDoc} 78 | * 79 | *

The default implementation returns the result of calling 80 | * {@link #visitChildren} on {@code ctx}.

81 | */ 82 | @Override public T visitIfdef_directive(SystemVerilogPreParser.Ifdef_directiveContext ctx) { return visitChildren(ctx); } 83 | /** 84 | * {@inheritDoc} 85 | * 86 | *

The default implementation returns the result of calling 87 | * {@link #visitChildren} on {@code ctx}.

88 | */ 89 | @Override public T visitIfndef_directive(SystemVerilogPreParser.Ifndef_directiveContext ctx) { return visitChildren(ctx); } 90 | /** 91 | * {@inheritDoc} 92 | * 93 | *

The default implementation returns the result of calling 94 | * {@link #visitChildren} on {@code ctx}.

95 | */ 96 | @Override public T visitInclude_directive(SystemVerilogPreParser.Include_directiveContext ctx) { return visitChildren(ctx); } 97 | /** 98 | * {@inheritDoc} 99 | * 100 | *

The default implementation returns the result of calling 101 | * {@link #visitChildren} on {@code ctx}.

102 | */ 103 | @Override public T visitLine_directive(SystemVerilogPreParser.Line_directiveContext ctx) { return visitChildren(ctx); } 104 | /** 105 | * {@inheritDoc} 106 | * 107 | *

The default implementation returns the result of calling 108 | * {@link #visitChildren} on {@code ctx}.

109 | */ 110 | @Override public T visitNounconnected_drive_directive(SystemVerilogPreParser.Nounconnected_drive_directiveContext ctx) { return visitChildren(ctx); } 111 | /** 112 | * {@inheritDoc} 113 | * 114 | *

The default implementation returns the result of calling 115 | * {@link #visitChildren} on {@code ctx}.

116 | */ 117 | @Override public T visitPragma_directive(SystemVerilogPreParser.Pragma_directiveContext ctx) { return visitChildren(ctx); } 118 | /** 119 | * {@inheritDoc} 120 | * 121 | *

The default implementation returns the result of calling 122 | * {@link #visitChildren} on {@code ctx}.

123 | */ 124 | @Override public T visitResetall_directive(SystemVerilogPreParser.Resetall_directiveContext ctx) { return visitChildren(ctx); } 125 | /** 126 | * {@inheritDoc} 127 | * 128 | *

The default implementation returns the result of calling 129 | * {@link #visitChildren} on {@code ctx}.

130 | */ 131 | @Override public T visitText_macro_definition(SystemVerilogPreParser.Text_macro_definitionContext ctx) { return visitChildren(ctx); } 132 | /** 133 | * {@inheritDoc} 134 | * 135 | *

The default implementation returns the result of calling 136 | * {@link #visitChildren} on {@code ctx}.

137 | */ 138 | @Override public T visitText_macro_usage(SystemVerilogPreParser.Text_macro_usageContext ctx) { return visitChildren(ctx); } 139 | /** 140 | * {@inheritDoc} 141 | * 142 | *

The default implementation returns the result of calling 143 | * {@link #visitChildren} on {@code ctx}.

144 | */ 145 | @Override public T visitTimescale_directive(SystemVerilogPreParser.Timescale_directiveContext ctx) { return visitChildren(ctx); } 146 | /** 147 | * {@inheritDoc} 148 | * 149 | *

The default implementation returns the result of calling 150 | * {@link #visitChildren} on {@code ctx}.

151 | */ 152 | @Override public T visitUnconnected_drive_directive(SystemVerilogPreParser.Unconnected_drive_directiveContext ctx) { return visitChildren(ctx); } 153 | /** 154 | * {@inheritDoc} 155 | * 156 | *

The default implementation returns the result of calling 157 | * {@link #visitChildren} on {@code ctx}.

158 | */ 159 | @Override public T visitUndef_directive(SystemVerilogPreParser.Undef_directiveContext ctx) { return visitChildren(ctx); } 160 | /** 161 | * {@inheritDoc} 162 | * 163 | *

The default implementation returns the result of calling 164 | * {@link #visitChildren} on {@code ctx}.

165 | */ 166 | @Override public T visitUndefineall_directive(SystemVerilogPreParser.Undefineall_directiveContext ctx) { return visitChildren(ctx); } 167 | /** 168 | * {@inheritDoc} 169 | * 170 | *

The default implementation returns the result of calling 171 | * {@link #visitChildren} on {@code ctx}.

172 | */ 173 | @Override public T visitElsif_directive(SystemVerilogPreParser.Elsif_directiveContext ctx) { return visitChildren(ctx); } 174 | /** 175 | * {@inheritDoc} 176 | * 177 | *

The default implementation returns the result of calling 178 | * {@link #visitChildren} on {@code ctx}.

179 | */ 180 | @Override public T visitElse_directive(SystemVerilogPreParser.Else_directiveContext ctx) { return visitChildren(ctx); } 181 | /** 182 | * {@inheritDoc} 183 | * 184 | *

The default implementation returns the result of calling 185 | * {@link #visitChildren} on {@code ctx}.

186 | */ 187 | @Override public T visitEndif_directive(SystemVerilogPreParser.Endif_directiveContext ctx) { return visitChildren(ctx); } 188 | /** 189 | * {@inheritDoc} 190 | * 191 | *

The default implementation returns the result of calling 192 | * {@link #visitChildren} on {@code ctx}.

193 | */ 194 | @Override public T visitText_macro_identifier(SystemVerilogPreParser.Text_macro_identifierContext ctx) { return visitChildren(ctx); } 195 | /** 196 | * {@inheritDoc} 197 | * 198 | *

The default implementation returns the result of calling 199 | * {@link #visitChildren} on {@code ctx}.

200 | */ 201 | @Override public T visitIfdef_group_of_lines(SystemVerilogPreParser.Ifdef_group_of_linesContext ctx) { return visitChildren(ctx); } 202 | /** 203 | * {@inheritDoc} 204 | * 205 | *

The default implementation returns the result of calling 206 | * {@link #visitChildren} on {@code ctx}.

207 | */ 208 | @Override public T visitIfndef_group_of_lines(SystemVerilogPreParser.Ifndef_group_of_linesContext ctx) { return visitChildren(ctx); } 209 | /** 210 | * {@inheritDoc} 211 | * 212 | *

The default implementation returns the result of calling 213 | * {@link #visitChildren} on {@code ctx}.

214 | */ 215 | @Override public T visitElsif_group_of_lines(SystemVerilogPreParser.Elsif_group_of_linesContext ctx) { return visitChildren(ctx); } 216 | /** 217 | * {@inheritDoc} 218 | * 219 | *

The default implementation returns the result of calling 220 | * {@link #visitChildren} on {@code ctx}.

221 | */ 222 | @Override public T visitElse_group_of_lines(SystemVerilogPreParser.Else_group_of_linesContext ctx) { return visitChildren(ctx); } 223 | /** 224 | * {@inheritDoc} 225 | * 226 | *

The default implementation returns the result of calling 227 | * {@link #visitChildren} on {@code ctx}.

228 | */ 229 | @Override public T visitMacro_text(SystemVerilogPreParser.Macro_textContext ctx) { return visitChildren(ctx); } 230 | } -------------------------------------------------------------------------------- /test/testrig/systemverilog/SystemVerilogPreParserVisitor.java: -------------------------------------------------------------------------------- 1 | // Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/systemverilog/SystemVerilogPreParser.g4 by ANTLR 4.10.1 2 | import org.antlr.v4.runtime.tree.ParseTreeVisitor; 3 | 4 | /** 5 | * This interface defines a complete generic visitor for a parse tree produced 6 | * by {@link SystemVerilogPreParser}. 7 | * 8 | * @param The return type of the visit operation. Use {@link Void} for 9 | * operations with no return type. 10 | */ 11 | public interface SystemVerilogPreParserVisitor extends ParseTreeVisitor { 12 | /** 13 | * Visit a parse tree produced by {@link SystemVerilogPreParser#source_text}. 14 | * @param ctx the parse tree 15 | * @return the visitor result 16 | */ 17 | T visitSource_text(SystemVerilogPreParser.Source_textContext ctx); 18 | /** 19 | * Visit a parse tree produced by {@link SystemVerilogPreParser#compiler_directive}. 20 | * @param ctx the parse tree 21 | * @return the visitor result 22 | */ 23 | T visitCompiler_directive(SystemVerilogPreParser.Compiler_directiveContext ctx); 24 | /** 25 | * Visit a parse tree produced by {@link SystemVerilogPreParser#file_directive}. 26 | * @param ctx the parse tree 27 | * @return the visitor result 28 | */ 29 | T visitFile_directive(SystemVerilogPreParser.File_directiveContext ctx); 30 | /** 31 | * Visit a parse tree produced by {@link SystemVerilogPreParser#line_directive_}. 32 | * @param ctx the parse tree 33 | * @return the visitor result 34 | */ 35 | T visitLine_directive_(SystemVerilogPreParser.Line_directive_Context ctx); 36 | /** 37 | * Visit a parse tree produced by {@link SystemVerilogPreParser#begin_keywords_directive}. 38 | * @param ctx the parse tree 39 | * @return the visitor result 40 | */ 41 | T visitBegin_keywords_directive(SystemVerilogPreParser.Begin_keywords_directiveContext ctx); 42 | /** 43 | * Visit a parse tree produced by {@link SystemVerilogPreParser#celldefine_directive}. 44 | * @param ctx the parse tree 45 | * @return the visitor result 46 | */ 47 | T visitCelldefine_directive(SystemVerilogPreParser.Celldefine_directiveContext ctx); 48 | /** 49 | * Visit a parse tree produced by {@link SystemVerilogPreParser#default_nettype_directive}. 50 | * @param ctx the parse tree 51 | * @return the visitor result 52 | */ 53 | T visitDefault_nettype_directive(SystemVerilogPreParser.Default_nettype_directiveContext ctx); 54 | /** 55 | * Visit a parse tree produced by {@link SystemVerilogPreParser#endcelldefine_directive}. 56 | * @param ctx the parse tree 57 | * @return the visitor result 58 | */ 59 | T visitEndcelldefine_directive(SystemVerilogPreParser.Endcelldefine_directiveContext ctx); 60 | /** 61 | * Visit a parse tree produced by {@link SystemVerilogPreParser#end_keywords_directive}. 62 | * @param ctx the parse tree 63 | * @return the visitor result 64 | */ 65 | T visitEnd_keywords_directive(SystemVerilogPreParser.End_keywords_directiveContext ctx); 66 | /** 67 | * Visit a parse tree produced by {@link SystemVerilogPreParser#ifdef_directive}. 68 | * @param ctx the parse tree 69 | * @return the visitor result 70 | */ 71 | T visitIfdef_directive(SystemVerilogPreParser.Ifdef_directiveContext ctx); 72 | /** 73 | * Visit a parse tree produced by {@link SystemVerilogPreParser#ifndef_directive}. 74 | * @param ctx the parse tree 75 | * @return the visitor result 76 | */ 77 | T visitIfndef_directive(SystemVerilogPreParser.Ifndef_directiveContext ctx); 78 | /** 79 | * Visit a parse tree produced by {@link SystemVerilogPreParser#include_directive}. 80 | * @param ctx the parse tree 81 | * @return the visitor result 82 | */ 83 | T visitInclude_directive(SystemVerilogPreParser.Include_directiveContext ctx); 84 | /** 85 | * Visit a parse tree produced by {@link SystemVerilogPreParser#line_directive}. 86 | * @param ctx the parse tree 87 | * @return the visitor result 88 | */ 89 | T visitLine_directive(SystemVerilogPreParser.Line_directiveContext ctx); 90 | /** 91 | * Visit a parse tree produced by {@link SystemVerilogPreParser#nounconnected_drive_directive}. 92 | * @param ctx the parse tree 93 | * @return the visitor result 94 | */ 95 | T visitNounconnected_drive_directive(SystemVerilogPreParser.Nounconnected_drive_directiveContext ctx); 96 | /** 97 | * Visit a parse tree produced by {@link SystemVerilogPreParser#pragma_directive}. 98 | * @param ctx the parse tree 99 | * @return the visitor result 100 | */ 101 | T visitPragma_directive(SystemVerilogPreParser.Pragma_directiveContext ctx); 102 | /** 103 | * Visit a parse tree produced by {@link SystemVerilogPreParser#resetall_directive}. 104 | * @param ctx the parse tree 105 | * @return the visitor result 106 | */ 107 | T visitResetall_directive(SystemVerilogPreParser.Resetall_directiveContext ctx); 108 | /** 109 | * Visit a parse tree produced by {@link SystemVerilogPreParser#text_macro_definition}. 110 | * @param ctx the parse tree 111 | * @return the visitor result 112 | */ 113 | T visitText_macro_definition(SystemVerilogPreParser.Text_macro_definitionContext ctx); 114 | /** 115 | * Visit a parse tree produced by {@link SystemVerilogPreParser#text_macro_usage}. 116 | * @param ctx the parse tree 117 | * @return the visitor result 118 | */ 119 | T visitText_macro_usage(SystemVerilogPreParser.Text_macro_usageContext ctx); 120 | /** 121 | * Visit a parse tree produced by {@link SystemVerilogPreParser#timescale_directive}. 122 | * @param ctx the parse tree 123 | * @return the visitor result 124 | */ 125 | T visitTimescale_directive(SystemVerilogPreParser.Timescale_directiveContext ctx); 126 | /** 127 | * Visit a parse tree produced by {@link SystemVerilogPreParser#unconnected_drive_directive}. 128 | * @param ctx the parse tree 129 | * @return the visitor result 130 | */ 131 | T visitUnconnected_drive_directive(SystemVerilogPreParser.Unconnected_drive_directiveContext ctx); 132 | /** 133 | * Visit a parse tree produced by {@link SystemVerilogPreParser#undef_directive}. 134 | * @param ctx the parse tree 135 | * @return the visitor result 136 | */ 137 | T visitUndef_directive(SystemVerilogPreParser.Undef_directiveContext ctx); 138 | /** 139 | * Visit a parse tree produced by {@link SystemVerilogPreParser#undefineall_directive}. 140 | * @param ctx the parse tree 141 | * @return the visitor result 142 | */ 143 | T visitUndefineall_directive(SystemVerilogPreParser.Undefineall_directiveContext ctx); 144 | /** 145 | * Visit a parse tree produced by {@link SystemVerilogPreParser#elsif_directive}. 146 | * @param ctx the parse tree 147 | * @return the visitor result 148 | */ 149 | T visitElsif_directive(SystemVerilogPreParser.Elsif_directiveContext ctx); 150 | /** 151 | * Visit a parse tree produced by {@link SystemVerilogPreParser#else_directive}. 152 | * @param ctx the parse tree 153 | * @return the visitor result 154 | */ 155 | T visitElse_directive(SystemVerilogPreParser.Else_directiveContext ctx); 156 | /** 157 | * Visit a parse tree produced by {@link SystemVerilogPreParser#endif_directive}. 158 | * @param ctx the parse tree 159 | * @return the visitor result 160 | */ 161 | T visitEndif_directive(SystemVerilogPreParser.Endif_directiveContext ctx); 162 | /** 163 | * Visit a parse tree produced by {@link SystemVerilogPreParser#text_macro_identifier}. 164 | * @param ctx the parse tree 165 | * @return the visitor result 166 | */ 167 | T visitText_macro_identifier(SystemVerilogPreParser.Text_macro_identifierContext ctx); 168 | /** 169 | * Visit a parse tree produced by {@link SystemVerilogPreParser#ifdef_group_of_lines}. 170 | * @param ctx the parse tree 171 | * @return the visitor result 172 | */ 173 | T visitIfdef_group_of_lines(SystemVerilogPreParser.Ifdef_group_of_linesContext ctx); 174 | /** 175 | * Visit a parse tree produced by {@link SystemVerilogPreParser#ifndef_group_of_lines}. 176 | * @param ctx the parse tree 177 | * @return the visitor result 178 | */ 179 | T visitIfndef_group_of_lines(SystemVerilogPreParser.Ifndef_group_of_linesContext ctx); 180 | /** 181 | * Visit a parse tree produced by {@link SystemVerilogPreParser#elsif_group_of_lines}. 182 | * @param ctx the parse tree 183 | * @return the visitor result 184 | */ 185 | T visitElsif_group_of_lines(SystemVerilogPreParser.Elsif_group_of_linesContext ctx); 186 | /** 187 | * Visit a parse tree produced by {@link SystemVerilogPreParser#else_group_of_lines}. 188 | * @param ctx the parse tree 189 | * @return the visitor result 190 | */ 191 | T visitElse_group_of_lines(SystemVerilogPreParser.Else_group_of_linesContext ctx); 192 | /** 193 | * Visit a parse tree produced by {@link SystemVerilogPreParser#macro_text}. 194 | * @param ctx the parse tree 195 | * @return the visitor result 196 | */ 197 | T visitMacro_text(SystemVerilogPreParser.Macro_textContext ctx); 198 | } -------------------------------------------------------------------------------- /test/testrig/test.sv: -------------------------------------------------------------------------------- 1 | module hello; 2 | string s = "Hello"; 3 | initial begin 4 | $display("%s", s); 5 | end 6 | endmodule 7 | -------------------------------------------------------------------------------- /test/testrig/test.sv.tree: -------------------------------------------------------------------------------- 1 | (source_text (description (module_declaration (module_ansi_header (module_keyword module) (module_identifier (identifier (simple_identifier hello))) ;) (non_port_module_item (module_or_generate_item (module_common_item (module_or_generate_item_declaration (package_or_generate_item_declaration (data_declaration (data_type_or_implicit (data_type string)) (list_of_variable_decl_assignments (variable_decl_assignment (variable_identifier (identifier (simple_identifier s))) = (expression (primary (primary_literal (string_literal "Hello")))))) ;)))))) (non_port_module_item (module_or_generate_item (module_common_item (initial_construct initial (statement_or_null (statement (statement_item (seq_block begin (statement_or_null (statement (statement_item (subroutine_call_statement (subroutine_call (system_tf_call (system_tf_identifier $display) ( (list_of_arguments (expression (primary (primary_literal (string_literal "%s")))) , (expression (primary class_qualifier (hierarchical_identifier (identifier (simple_identifier s))) (select_ bit_select)))) ))) ;)))) end)))))))) endmodule)) ) 2 | -------------------------------------------------------------------------------- /test/testrig/test.v: -------------------------------------------------------------------------------- 1 | module ha(a, b, sum, c); 2 | input a, b; 3 | output sum, c; 4 | 5 | assign sum = a ^ b; 6 | assign c = a & b; 7 | endmodule 8 | -------------------------------------------------------------------------------- /test/testrig/test.v.tree: -------------------------------------------------------------------------------- 1 | (source_text (description (module_declaration (module_keyword module) (module_identifier (identifier (simple_identifier ha))) (list_of_ports ( (port (port_expression (port_reference (port_identifier (identifier (simple_identifier a)))))) , (port (port_expression (port_reference (port_identifier (identifier (simple_identifier b)))))) , (port (port_expression (port_reference (port_identifier (identifier (simple_identifier sum)))))) , (port (port_expression (port_reference (port_identifier (identifier (simple_identifier c)))))) )) ; (module_item (port_declaration (input_declaration input (list_of_port_identifiers (port_identifier (identifier (simple_identifier a))) , (port_identifier (identifier (simple_identifier b)))))) ;) (module_item (port_declaration (output_declaration output (list_of_port_identifiers (port_identifier (identifier (simple_identifier sum))) , (port_identifier (identifier (simple_identifier c)))))) ;) (module_item (non_port_module_item (module_or_generate_item (continuous_assign assign (list_of_net_assignments (net_assignment (net_lvalue (hierarchical_net_identifier (hierarchical_identifier (identifier (simple_identifier sum))))) = (expression (expression (primary (hierarchical_identifier (identifier (simple_identifier a))))) (binary_operator ^) (expression (primary (hierarchical_identifier (identifier (simple_identifier b)))))))) ;)))) (module_item (non_port_module_item (module_or_generate_item (continuous_assign assign (list_of_net_assignments (net_assignment (net_lvalue (hierarchical_net_identifier (hierarchical_identifier (identifier (simple_identifier c))))) = (expression (expression (primary (hierarchical_identifier (identifier (simple_identifier a))))) (binary_operator &) (expression (primary (hierarchical_identifier (identifier (simple_identifier b)))))))) ;)))) endmodule)) ) 2 | -------------------------------------------------------------------------------- /test/testrig/verilog.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mtdsousa/antlr4-verilog-python/e078ccafc5d83ea179b5e6f4b4373f5b5de57872/test/testrig/verilog.jar -------------------------------------------------------------------------------- /test/testrig/verilog/VerilogLexer.tokens: -------------------------------------------------------------------------------- 1 | EM=1 2 | EMEQ=2 3 | EMEQEQ=3 4 | DQ=4 5 | HA=5 6 | DL=6 7 | DLFULLSKEW=7 8 | DLHOLD=8 9 | DLNOCHANGE=9 10 | DLPERIOD=10 11 | DLRECOVERY=11 12 | DLRECREM=12 13 | DLREMOVAL=13 14 | DLSETUP=14 15 | DLSETUPHOLD=15 16 | DLSKEW=16 17 | DLTIMESKEW=17 18 | DLWIDTH=18 19 | MO=19 20 | AM=20 21 | AMAM=21 22 | AMAMAM=22 23 | AP=23 24 | LP=24 25 | RP=25 26 | AS=26 27 | ASAS=27 28 | ASSL=28 29 | ASGT=29 30 | PL=30 31 | PLCL=31 32 | CO=32 33 | MI=33 34 | MICL=34 35 | MIGT=35 36 | DT=36 37 | SL=37 38 | SLAS=38 39 | SLSL=39 40 | CL=40 41 | SC=41 42 | LT=42 43 | LTLT=43 44 | LTLTLT=44 45 | LTEQ=45 46 | EQ=46 47 | EQEQ=47 48 | EQEQEQ=48 49 | EQGT=49 50 | GT=50 51 | GTEQ=51 52 | GTGT=52 53 | GTGTGT=53 54 | QM=54 55 | AT=55 56 | PATHPULSEDL=56 57 | LB=57 58 | RB=58 59 | CA=59 60 | CATI=60 61 | GA=61 62 | ALWAYS=62 63 | AND=63 64 | ASSIGN=64 65 | AUTOMATIC=65 66 | BEGIN=66 67 | BUF=67 68 | BUFIFZERO=68 69 | BUFIFONE=69 70 | CASE=70 71 | CASEX=71 72 | CASEZ=72 73 | CELL=73 74 | CMOS=74 75 | CONFIG=75 76 | DEASSIGN=76 77 | DEFAULT=77 78 | DEFPARAM=78 79 | DESIGN=79 80 | DISABLE=80 81 | EDGE=81 82 | ELSE=82 83 | END=83 84 | ENDCASE=84 85 | ENDCONFIG=85 86 | ENDFUNCTION=86 87 | ENDGENERATE=87 88 | ENDMODULE=88 89 | ENDPRIMITIVE=89 90 | ENDSPECIFY=90 91 | ENDTABLE=91 92 | ENDTASK=92 93 | EVENT=93 94 | FOR=94 95 | FORCE=95 96 | FOREVER=96 97 | FORK=97 98 | FUNCTION=98 99 | GENERATE=99 100 | GENVAR=100 101 | HIGHZZERO=101 102 | HIGHZONE=102 103 | IF=103 104 | IFNONE=104 105 | INCLUDE=105 106 | INITIAL=106 107 | INOUT=107 108 | INPUT=108 109 | INSTANCE=109 110 | INTEGER=110 111 | JOIN=111 112 | LARGE=112 113 | LIBLIST=113 114 | LIBRARY=114 115 | LOCALPARAM=115 116 | MACROMODULE=116 117 | MEDIUM=117 118 | MODULE=118 119 | NAND=119 120 | NEGEDGE=120 121 | NMOS=121 122 | NOR=122 123 | NOSHOWCANCELLED=123 124 | NOT=124 125 | NOTIFZERO=125 126 | NOTIFONE=126 127 | OR=127 128 | OUTPUT=128 129 | PARAMETER=129 130 | PMOS=130 131 | POSEDGE=131 132 | PRIMITIVE=132 133 | PULLZERO=133 134 | PULLONE=134 135 | PULLDOWN=135 136 | PULLUP=136 137 | PULSESTYLE_ONDETECT=137 138 | PULSESTYLE_ONEVENT=138 139 | RCMOS=139 140 | REAL=140 141 | REALTIME=141 142 | REG=142 143 | RELEASE=143 144 | REPEAT=144 145 | RNMOS=145 146 | RPMOS=146 147 | RTRAN=147 148 | RTRANIFZERO=148 149 | RTRANIFONE=149 150 | SCALARED=150 151 | SHOWCANCELLED=151 152 | SIGNED=152 153 | SMALL=153 154 | SPECIFY=154 155 | SPECPARAM=155 156 | STRONGZERO=156 157 | STRONGONE=157 158 | SUPPLYZERO=158 159 | SUPPLYONE=159 160 | TABLE=160 161 | TASK=161 162 | TIME=162 163 | TRAN=163 164 | TRANIFZERO=164 165 | TRANIFONE=165 166 | TRI=166 167 | TRIZERO=167 168 | TRIONE=168 169 | TRIAND=169 170 | TRIOR=170 171 | TRIREG=171 172 | USE=172 173 | UWIRE=173 174 | VECTORED=174 175 | WAIT=175 176 | WAND=176 177 | WEAKZERO=177 178 | WEAKONE=178 179 | WHILE=179 180 | WIRE=180 181 | WOR=181 182 | XNOR=182 183 | XOR=183 184 | LC=184 185 | VL=185 186 | VLVL=186 187 | RC=187 188 | TI=188 189 | TIAM=189 190 | TICA=190 191 | TIVL=191 192 | DECIMAL_NUMBER=192 193 | BINARY_NUMBER=193 194 | OCTAL_NUMBER=194 195 | HEX_NUMBER=195 196 | REAL_NUMBER=196 197 | STRING=197 198 | COMMENT=198 199 | ESCAPED_IDENTIFIER=199 200 | SIMPLE_IDENTIFIER=200 201 | SYSTEM_TF_IDENTIFIER=201 202 | WHITE_SPACE=202 203 | MIINCDIR=203 204 | FILE_PATH_SPEC=204 205 | OUTPUT_OR_LEVEL_SYMBOL=205 206 | LEVEL_ONLY_SYMBOL=206 207 | EDGE_SYMBOL=207 208 | EDGE_DESCRIPTOR=208 209 | BEGIN_KEYWORDS_DIRECTIVE=209 210 | CELLDEFINE_DIRECTIVE=210 211 | DEFAULT_NETTYPE_DIRECTIVE=211 212 | DEFINE_DIRECTIVE=212 213 | ELSE_DIRECTIVE=213 214 | ELSIF_DIRECTIVE=214 215 | END_KEYWORDS_DIRECTIVE=215 216 | ENDCELLDEFINE_DIRECTIVE=216 217 | ENDIF_DIRECTIVE=217 218 | IFDEF_DIRECTIVE=218 219 | IFNDEF_DIRECTIVE=219 220 | INCLUDE_DIRECTIVE=220 221 | LINE_DIRECTIVE=221 222 | NOUNCONNECTED_DRIVE_DIRECTIVE=222 223 | PRAGMA_DIRECTIVE=223 224 | RESETALL_DIRECTIVE=224 225 | TIMESCALE_DIRECTIVE=225 226 | UNCONNECTED_DRIVE_DIRECTIVE=226 227 | UNDEF_DIRECTIVE=227 228 | MACRO_USAGE=228 229 | DIRECTIVE_TEXT=229 230 | DIRECTIVE_IDENTIFIER=230 231 | DIRECTIVE_COMMENT=231 232 | DIRECTIVE_WHITE_SPACE=232 233 | DIRECTIVE_NEWLINE=233 234 | MACRO_TEXT=234 235 | MACRO_ESC_NEWLINE=235 236 | SOURCE_TEXT=236 237 | '!'=1 238 | '!='=2 239 | '!=='=3 240 | '"'=4 241 | '#'=5 242 | '$'=6 243 | '$fullskew'=7 244 | '$hold'=8 245 | '$nochange'=9 246 | '$period'=10 247 | '$recovery'=11 248 | '$recrem'=12 249 | '$removal'=13 250 | '$setup'=14 251 | '$setuphold'=15 252 | '$skew'=16 253 | '$timeskew'=17 254 | '$width'=18 255 | '%'=19 256 | '&'=20 257 | '&&'=21 258 | '&&&'=22 259 | '\''=23 260 | '('=24 261 | ')'=25 262 | '*'=26 263 | '**'=27 264 | '*/'=28 265 | '*>'=29 266 | '+'=30 267 | '+:'=31 268 | ','=32 269 | '-'=33 270 | '-:'=34 271 | '->'=35 272 | '.'=36 273 | '/'=37 274 | '/*'=38 275 | '//'=39 276 | ':'=40 277 | ';'=41 278 | '<'=42 279 | '<<'=43 280 | '<<<'=44 281 | '<='=45 282 | '='=46 283 | '=='=47 284 | '==='=48 285 | '=>'=49 286 | '>'=50 287 | '>='=51 288 | '>>'=52 289 | '>>>'=53 290 | '?'=54 291 | '@'=55 292 | 'PATHPULSE$'=56 293 | '['=57 294 | ']'=58 295 | '^'=59 296 | '^~'=60 297 | 'always'=62 298 | 'and'=63 299 | 'assign'=64 300 | 'automatic'=65 301 | 'begin'=66 302 | 'buf'=67 303 | 'bufif0'=68 304 | 'bufif1'=69 305 | 'case'=70 306 | 'casex'=71 307 | 'casez'=72 308 | 'cell'=73 309 | 'cmos'=74 310 | 'config'=75 311 | 'deassign'=76 312 | 'default'=77 313 | 'defparam'=78 314 | 'design'=79 315 | 'disable'=80 316 | 'edge'=81 317 | 'else'=82 318 | 'end'=83 319 | 'endcase'=84 320 | 'endconfig'=85 321 | 'endfunction'=86 322 | 'endgenerate'=87 323 | 'endmodule'=88 324 | 'endprimitive'=89 325 | 'endspecify'=90 326 | 'endtable'=91 327 | 'endtask'=92 328 | 'event'=93 329 | 'for'=94 330 | 'force'=95 331 | 'forever'=96 332 | 'fork'=97 333 | 'function'=98 334 | 'generate'=99 335 | 'genvar'=100 336 | 'highz0'=101 337 | 'highz1'=102 338 | 'if'=103 339 | 'ifnone'=104 340 | 'include'=105 341 | 'initial'=106 342 | 'inout'=107 343 | 'input'=108 344 | 'instance'=109 345 | 'integer'=110 346 | 'join'=111 347 | 'large'=112 348 | 'liblist'=113 349 | 'library'=114 350 | 'localparam'=115 351 | 'macromodule'=116 352 | 'medium'=117 353 | 'module'=118 354 | 'nand'=119 355 | 'negedge'=120 356 | 'nmos'=121 357 | 'nor'=122 358 | 'noshowcancelled'=123 359 | 'not'=124 360 | 'notif0'=125 361 | 'notif1'=126 362 | 'or'=127 363 | 'output'=128 364 | 'parameter'=129 365 | 'pmos'=130 366 | 'posedge'=131 367 | 'primitive'=132 368 | 'pull0'=133 369 | 'pull1'=134 370 | 'pulldown'=135 371 | 'pullup'=136 372 | 'pulsestyle_ondetect'=137 373 | 'pulsestyle_onevent'=138 374 | 'rcmos'=139 375 | 'real'=140 376 | 'realtime'=141 377 | 'reg'=142 378 | 'release'=143 379 | 'repeat'=144 380 | 'rnmos'=145 381 | 'rpmos'=146 382 | 'rtran'=147 383 | 'rtranif0'=148 384 | 'rtranif1'=149 385 | 'scalared'=150 386 | 'showcancelled'=151 387 | 'signed'=152 388 | 'small'=153 389 | 'specify'=154 390 | 'specparam'=155 391 | 'strong0'=156 392 | 'strong1'=157 393 | 'supply0'=158 394 | 'supply1'=159 395 | 'table'=160 396 | 'task'=161 397 | 'time'=162 398 | 'tran'=163 399 | 'tranif0'=164 400 | 'tranif1'=165 401 | 'tri'=166 402 | 'tri0'=167 403 | 'tri1'=168 404 | 'triand'=169 405 | 'trior'=170 406 | 'trireg'=171 407 | 'use'=172 408 | 'uwire'=173 409 | 'vectored'=174 410 | 'wait'=175 411 | 'wand'=176 412 | 'weak0'=177 413 | 'weak1'=178 414 | 'while'=179 415 | 'wire'=180 416 | 'wor'=181 417 | 'xnor'=182 418 | 'xor'=183 419 | '{'=184 420 | '|'=185 421 | '||'=186 422 | '}'=187 423 | '~'=188 424 | '~&'=189 425 | '~^'=190 426 | '~|'=191 427 | '-incdir'=203 428 | 'celldefine'=210 429 | 'end_keywords'=215 430 | 'endcelldefine'=216 431 | 'nounconnected_drive'=222 432 | 'resetall'=224 433 | -------------------------------------------------------------------------------- /test/testrig/verilog/VerilogParser.tokens: -------------------------------------------------------------------------------- 1 | EM=1 2 | EMEQ=2 3 | EMEQEQ=3 4 | DQ=4 5 | HA=5 6 | DL=6 7 | DLFULLSKEW=7 8 | DLHOLD=8 9 | DLNOCHANGE=9 10 | DLPERIOD=10 11 | DLRECOVERY=11 12 | DLRECREM=12 13 | DLREMOVAL=13 14 | DLSETUP=14 15 | DLSETUPHOLD=15 16 | DLSKEW=16 17 | DLTIMESKEW=17 18 | DLWIDTH=18 19 | MO=19 20 | AM=20 21 | AMAM=21 22 | AMAMAM=22 23 | AP=23 24 | LP=24 25 | RP=25 26 | AS=26 27 | ASAS=27 28 | ASSL=28 29 | ASGT=29 30 | PL=30 31 | PLCL=31 32 | CO=32 33 | MI=33 34 | MICL=34 35 | MIGT=35 36 | DT=36 37 | SL=37 38 | SLAS=38 39 | SLSL=39 40 | CL=40 41 | SC=41 42 | LT=42 43 | LTLT=43 44 | LTLTLT=44 45 | LTEQ=45 46 | EQ=46 47 | EQEQ=47 48 | EQEQEQ=48 49 | EQGT=49 50 | GT=50 51 | GTEQ=51 52 | GTGT=52 53 | GTGTGT=53 54 | QM=54 55 | AT=55 56 | PATHPULSEDL=56 57 | LB=57 58 | RB=58 59 | CA=59 60 | CATI=60 61 | GA=61 62 | ALWAYS=62 63 | AND=63 64 | ASSIGN=64 65 | AUTOMATIC=65 66 | BEGIN=66 67 | BUF=67 68 | BUFIFZERO=68 69 | BUFIFONE=69 70 | CASE=70 71 | CASEX=71 72 | CASEZ=72 73 | CELL=73 74 | CMOS=74 75 | CONFIG=75 76 | DEASSIGN=76 77 | DEFAULT=77 78 | DEFPARAM=78 79 | DESIGN=79 80 | DISABLE=80 81 | EDGE=81 82 | ELSE=82 83 | END=83 84 | ENDCASE=84 85 | ENDCONFIG=85 86 | ENDFUNCTION=86 87 | ENDGENERATE=87 88 | ENDMODULE=88 89 | ENDPRIMITIVE=89 90 | ENDSPECIFY=90 91 | ENDTABLE=91 92 | ENDTASK=92 93 | EVENT=93 94 | FOR=94 95 | FORCE=95 96 | FOREVER=96 97 | FORK=97 98 | FUNCTION=98 99 | GENERATE=99 100 | GENVAR=100 101 | HIGHZZERO=101 102 | HIGHZONE=102 103 | IF=103 104 | IFNONE=104 105 | INCLUDE=105 106 | INITIAL=106 107 | INOUT=107 108 | INPUT=108 109 | INSTANCE=109 110 | INTEGER=110 111 | JOIN=111 112 | LARGE=112 113 | LIBLIST=113 114 | LIBRARY=114 115 | LOCALPARAM=115 116 | MACROMODULE=116 117 | MEDIUM=117 118 | MODULE=118 119 | NAND=119 120 | NEGEDGE=120 121 | NMOS=121 122 | NOR=122 123 | NOSHOWCANCELLED=123 124 | NOT=124 125 | NOTIFZERO=125 126 | NOTIFONE=126 127 | OR=127 128 | OUTPUT=128 129 | PARAMETER=129 130 | PMOS=130 131 | POSEDGE=131 132 | PRIMITIVE=132 133 | PULLZERO=133 134 | PULLONE=134 135 | PULLDOWN=135 136 | PULLUP=136 137 | PULSESTYLE_ONDETECT=137 138 | PULSESTYLE_ONEVENT=138 139 | RCMOS=139 140 | REAL=140 141 | REALTIME=141 142 | REG=142 143 | RELEASE=143 144 | REPEAT=144 145 | RNMOS=145 146 | RPMOS=146 147 | RTRAN=147 148 | RTRANIFZERO=148 149 | RTRANIFONE=149 150 | SCALARED=150 151 | SHOWCANCELLED=151 152 | SIGNED=152 153 | SMALL=153 154 | SPECIFY=154 155 | SPECPARAM=155 156 | STRONGZERO=156 157 | STRONGONE=157 158 | SUPPLYZERO=158 159 | SUPPLYONE=159 160 | TABLE=160 161 | TASK=161 162 | TIME=162 163 | TRAN=163 164 | TRANIFZERO=164 165 | TRANIFONE=165 166 | TRI=166 167 | TRIZERO=167 168 | TRIONE=168 169 | TRIAND=169 170 | TRIOR=170 171 | TRIREG=171 172 | USE=172 173 | UWIRE=173 174 | VECTORED=174 175 | WAIT=175 176 | WAND=176 177 | WEAKZERO=177 178 | WEAKONE=178 179 | WHILE=179 180 | WIRE=180 181 | WOR=181 182 | XNOR=182 183 | XOR=183 184 | LC=184 185 | VL=185 186 | VLVL=186 187 | RC=187 188 | TI=188 189 | TIAM=189 190 | TICA=190 191 | TIVL=191 192 | DECIMAL_NUMBER=192 193 | BINARY_NUMBER=193 194 | OCTAL_NUMBER=194 195 | HEX_NUMBER=195 196 | REAL_NUMBER=196 197 | STRING=197 198 | COMMENT=198 199 | ESCAPED_IDENTIFIER=199 200 | SIMPLE_IDENTIFIER=200 201 | SYSTEM_TF_IDENTIFIER=201 202 | WHITE_SPACE=202 203 | MIINCDIR=203 204 | FILE_PATH_SPEC=204 205 | OUTPUT_OR_LEVEL_SYMBOL=205 206 | LEVEL_ONLY_SYMBOL=206 207 | EDGE_SYMBOL=207 208 | EDGE_DESCRIPTOR=208 209 | BEGIN_KEYWORDS_DIRECTIVE=209 210 | CELLDEFINE_DIRECTIVE=210 211 | DEFAULT_NETTYPE_DIRECTIVE=211 212 | DEFINE_DIRECTIVE=212 213 | ELSE_DIRECTIVE=213 214 | ELSIF_DIRECTIVE=214 215 | END_KEYWORDS_DIRECTIVE=215 216 | ENDCELLDEFINE_DIRECTIVE=216 217 | ENDIF_DIRECTIVE=217 218 | IFDEF_DIRECTIVE=218 219 | IFNDEF_DIRECTIVE=219 220 | INCLUDE_DIRECTIVE=220 221 | LINE_DIRECTIVE=221 222 | NOUNCONNECTED_DRIVE_DIRECTIVE=222 223 | PRAGMA_DIRECTIVE=223 224 | RESETALL_DIRECTIVE=224 225 | TIMESCALE_DIRECTIVE=225 226 | UNCONNECTED_DRIVE_DIRECTIVE=226 227 | UNDEF_DIRECTIVE=227 228 | MACRO_USAGE=228 229 | DIRECTIVE_TEXT=229 230 | DIRECTIVE_IDENTIFIER=230 231 | DIRECTIVE_COMMENT=231 232 | DIRECTIVE_WHITE_SPACE=232 233 | DIRECTIVE_NEWLINE=233 234 | MACRO_TEXT=234 235 | MACRO_ESC_NEWLINE=235 236 | SOURCE_TEXT=236 237 | '!'=1 238 | '!='=2 239 | '!=='=3 240 | '"'=4 241 | '#'=5 242 | '$'=6 243 | '$fullskew'=7 244 | '$hold'=8 245 | '$nochange'=9 246 | '$period'=10 247 | '$recovery'=11 248 | '$recrem'=12 249 | '$removal'=13 250 | '$setup'=14 251 | '$setuphold'=15 252 | '$skew'=16 253 | '$timeskew'=17 254 | '$width'=18 255 | '%'=19 256 | '&'=20 257 | '&&'=21 258 | '&&&'=22 259 | '\''=23 260 | '('=24 261 | ')'=25 262 | '*'=26 263 | '**'=27 264 | '*/'=28 265 | '*>'=29 266 | '+'=30 267 | '+:'=31 268 | ','=32 269 | '-'=33 270 | '-:'=34 271 | '->'=35 272 | '.'=36 273 | '/'=37 274 | '/*'=38 275 | '//'=39 276 | ':'=40 277 | ';'=41 278 | '<'=42 279 | '<<'=43 280 | '<<<'=44 281 | '<='=45 282 | '='=46 283 | '=='=47 284 | '==='=48 285 | '=>'=49 286 | '>'=50 287 | '>='=51 288 | '>>'=52 289 | '>>>'=53 290 | '?'=54 291 | '@'=55 292 | 'PATHPULSE$'=56 293 | '['=57 294 | ']'=58 295 | '^'=59 296 | '^~'=60 297 | 'always'=62 298 | 'and'=63 299 | 'assign'=64 300 | 'automatic'=65 301 | 'begin'=66 302 | 'buf'=67 303 | 'bufif0'=68 304 | 'bufif1'=69 305 | 'case'=70 306 | 'casex'=71 307 | 'casez'=72 308 | 'cell'=73 309 | 'cmos'=74 310 | 'config'=75 311 | 'deassign'=76 312 | 'default'=77 313 | 'defparam'=78 314 | 'design'=79 315 | 'disable'=80 316 | 'edge'=81 317 | 'else'=82 318 | 'end'=83 319 | 'endcase'=84 320 | 'endconfig'=85 321 | 'endfunction'=86 322 | 'endgenerate'=87 323 | 'endmodule'=88 324 | 'endprimitive'=89 325 | 'endspecify'=90 326 | 'endtable'=91 327 | 'endtask'=92 328 | 'event'=93 329 | 'for'=94 330 | 'force'=95 331 | 'forever'=96 332 | 'fork'=97 333 | 'function'=98 334 | 'generate'=99 335 | 'genvar'=100 336 | 'highz0'=101 337 | 'highz1'=102 338 | 'if'=103 339 | 'ifnone'=104 340 | 'include'=105 341 | 'initial'=106 342 | 'inout'=107 343 | 'input'=108 344 | 'instance'=109 345 | 'integer'=110 346 | 'join'=111 347 | 'large'=112 348 | 'liblist'=113 349 | 'library'=114 350 | 'localparam'=115 351 | 'macromodule'=116 352 | 'medium'=117 353 | 'module'=118 354 | 'nand'=119 355 | 'negedge'=120 356 | 'nmos'=121 357 | 'nor'=122 358 | 'noshowcancelled'=123 359 | 'not'=124 360 | 'notif0'=125 361 | 'notif1'=126 362 | 'or'=127 363 | 'output'=128 364 | 'parameter'=129 365 | 'pmos'=130 366 | 'posedge'=131 367 | 'primitive'=132 368 | 'pull0'=133 369 | 'pull1'=134 370 | 'pulldown'=135 371 | 'pullup'=136 372 | 'pulsestyle_ondetect'=137 373 | 'pulsestyle_onevent'=138 374 | 'rcmos'=139 375 | 'real'=140 376 | 'realtime'=141 377 | 'reg'=142 378 | 'release'=143 379 | 'repeat'=144 380 | 'rnmos'=145 381 | 'rpmos'=146 382 | 'rtran'=147 383 | 'rtranif0'=148 384 | 'rtranif1'=149 385 | 'scalared'=150 386 | 'showcancelled'=151 387 | 'signed'=152 388 | 'small'=153 389 | 'specify'=154 390 | 'specparam'=155 391 | 'strong0'=156 392 | 'strong1'=157 393 | 'supply0'=158 394 | 'supply1'=159 395 | 'table'=160 396 | 'task'=161 397 | 'time'=162 398 | 'tran'=163 399 | 'tranif0'=164 400 | 'tranif1'=165 401 | 'tri'=166 402 | 'tri0'=167 403 | 'tri1'=168 404 | 'triand'=169 405 | 'trior'=170 406 | 'trireg'=171 407 | 'use'=172 408 | 'uwire'=173 409 | 'vectored'=174 410 | 'wait'=175 411 | 'wand'=176 412 | 'weak0'=177 413 | 'weak1'=178 414 | 'while'=179 415 | 'wire'=180 416 | 'wor'=181 417 | 'xnor'=182 418 | 'xor'=183 419 | '{'=184 420 | '|'=185 421 | '||'=186 422 | '}'=187 423 | '~'=188 424 | '~&'=189 425 | '~^'=190 426 | '~|'=191 427 | '-incdir'=203 428 | 'celldefine'=210 429 | 'end_keywords'=215 430 | 'endcelldefine'=216 431 | 'nounconnected_drive'=222 432 | 'resetall'=224 433 | -------------------------------------------------------------------------------- /test/testrig/verilog/VerilogPreParser.interp: -------------------------------------------------------------------------------- 1 | token literal names: 2 | null 3 | '!' 4 | '!=' 5 | '!==' 6 | '"' 7 | '#' 8 | '$' 9 | '$fullskew' 10 | '$hold' 11 | '$nochange' 12 | '$period' 13 | '$recovery' 14 | '$recrem' 15 | '$removal' 16 | '$setup' 17 | '$setuphold' 18 | '$skew' 19 | '$timeskew' 20 | '$width' 21 | '%' 22 | '&' 23 | '&&' 24 | '&&&' 25 | '\'' 26 | '(' 27 | ')' 28 | '*' 29 | '**' 30 | '*/' 31 | '*>' 32 | '+' 33 | '+:' 34 | ',' 35 | '-' 36 | '-:' 37 | '->' 38 | '.' 39 | '/' 40 | '/*' 41 | '//' 42 | ':' 43 | ';' 44 | '<' 45 | '<<' 46 | '<<<' 47 | '<=' 48 | '=' 49 | '==' 50 | '===' 51 | '=>' 52 | '>' 53 | '>=' 54 | '>>' 55 | '>>>' 56 | '?' 57 | '@' 58 | 'PATHPULSE$' 59 | '[' 60 | ']' 61 | '^' 62 | '^~' 63 | null 64 | 'always' 65 | 'and' 66 | 'assign' 67 | 'automatic' 68 | 'begin' 69 | 'buf' 70 | 'bufif0' 71 | 'bufif1' 72 | 'case' 73 | 'casex' 74 | 'casez' 75 | 'cell' 76 | 'cmos' 77 | 'config' 78 | 'deassign' 79 | 'default' 80 | 'defparam' 81 | 'design' 82 | 'disable' 83 | 'edge' 84 | 'else' 85 | 'end' 86 | 'endcase' 87 | 'endconfig' 88 | 'endfunction' 89 | 'endgenerate' 90 | 'endmodule' 91 | 'endprimitive' 92 | 'endspecify' 93 | 'endtable' 94 | 'endtask' 95 | 'event' 96 | 'for' 97 | 'force' 98 | 'forever' 99 | 'fork' 100 | 'function' 101 | 'generate' 102 | 'genvar' 103 | 'highz0' 104 | 'highz1' 105 | 'if' 106 | 'ifnone' 107 | 'include' 108 | 'initial' 109 | 'inout' 110 | 'input' 111 | 'instance' 112 | 'integer' 113 | 'join' 114 | 'large' 115 | 'liblist' 116 | 'library' 117 | 'localparam' 118 | 'macromodule' 119 | 'medium' 120 | 'module' 121 | 'nand' 122 | 'negedge' 123 | 'nmos' 124 | 'nor' 125 | 'noshowcancelled' 126 | 'not' 127 | 'notif0' 128 | 'notif1' 129 | 'or' 130 | 'output' 131 | 'parameter' 132 | 'pmos' 133 | 'posedge' 134 | 'primitive' 135 | 'pull0' 136 | 'pull1' 137 | 'pulldown' 138 | 'pullup' 139 | 'pulsestyle_ondetect' 140 | 'pulsestyle_onevent' 141 | 'rcmos' 142 | 'real' 143 | 'realtime' 144 | 'reg' 145 | 'release' 146 | 'repeat' 147 | 'rnmos' 148 | 'rpmos' 149 | 'rtran' 150 | 'rtranif0' 151 | 'rtranif1' 152 | 'scalared' 153 | 'showcancelled' 154 | 'signed' 155 | 'small' 156 | 'specify' 157 | 'specparam' 158 | 'strong0' 159 | 'strong1' 160 | 'supply0' 161 | 'supply1' 162 | 'table' 163 | 'task' 164 | 'time' 165 | 'tran' 166 | 'tranif0' 167 | 'tranif1' 168 | 'tri' 169 | 'tri0' 170 | 'tri1' 171 | 'triand' 172 | 'trior' 173 | 'trireg' 174 | 'use' 175 | 'uwire' 176 | 'vectored' 177 | 'wait' 178 | 'wand' 179 | 'weak0' 180 | 'weak1' 181 | 'while' 182 | 'wire' 183 | 'wor' 184 | 'xnor' 185 | 'xor' 186 | '{' 187 | '|' 188 | '||' 189 | '}' 190 | '~' 191 | '~&' 192 | '~^' 193 | '~|' 194 | null 195 | null 196 | null 197 | null 198 | null 199 | null 200 | null 201 | null 202 | null 203 | null 204 | null 205 | '-incdir' 206 | null 207 | null 208 | null 209 | null 210 | null 211 | null 212 | 'celldefine' 213 | null 214 | null 215 | null 216 | null 217 | 'end_keywords' 218 | 'endcelldefine' 219 | null 220 | null 221 | null 222 | null 223 | null 224 | 'nounconnected_drive' 225 | null 226 | 'resetall' 227 | null 228 | null 229 | null 230 | null 231 | null 232 | null 233 | null 234 | null 235 | null 236 | null 237 | null 238 | null 239 | 240 | token symbolic names: 241 | null 242 | EM 243 | EMEQ 244 | EMEQEQ 245 | DQ 246 | HA 247 | DL 248 | DLFULLSKEW 249 | DLHOLD 250 | DLNOCHANGE 251 | DLPERIOD 252 | DLRECOVERY 253 | DLRECREM 254 | DLREMOVAL 255 | DLSETUP 256 | DLSETUPHOLD 257 | DLSKEW 258 | DLTIMESKEW 259 | DLWIDTH 260 | MO 261 | AM 262 | AMAM 263 | AMAMAM 264 | AP 265 | LP 266 | RP 267 | AS 268 | ASAS 269 | ASSL 270 | ASGT 271 | PL 272 | PLCL 273 | CO 274 | MI 275 | MICL 276 | MIGT 277 | DT 278 | SL 279 | SLAS 280 | SLSL 281 | CL 282 | SC 283 | LT 284 | LTLT 285 | LTLTLT 286 | LTEQ 287 | EQ 288 | EQEQ 289 | EQEQEQ 290 | EQGT 291 | GT 292 | GTEQ 293 | GTGT 294 | GTGTGT 295 | QM 296 | AT 297 | PATHPULSEDL 298 | LB 299 | RB 300 | CA 301 | CATI 302 | GA 303 | ALWAYS 304 | AND 305 | ASSIGN 306 | AUTOMATIC 307 | BEGIN 308 | BUF 309 | BUFIFZERO 310 | BUFIFONE 311 | CASE 312 | CASEX 313 | CASEZ 314 | CELL 315 | CMOS 316 | CONFIG 317 | DEASSIGN 318 | DEFAULT 319 | DEFPARAM 320 | DESIGN 321 | DISABLE 322 | EDGE 323 | ELSE 324 | END 325 | ENDCASE 326 | ENDCONFIG 327 | ENDFUNCTION 328 | ENDGENERATE 329 | ENDMODULE 330 | ENDPRIMITIVE 331 | ENDSPECIFY 332 | ENDTABLE 333 | ENDTASK 334 | EVENT 335 | FOR 336 | FORCE 337 | FOREVER 338 | FORK 339 | FUNCTION 340 | GENERATE 341 | GENVAR 342 | HIGHZZERO 343 | HIGHZONE 344 | IF 345 | IFNONE 346 | INCLUDE 347 | INITIAL 348 | INOUT 349 | INPUT 350 | INSTANCE 351 | INTEGER 352 | JOIN 353 | LARGE 354 | LIBLIST 355 | LIBRARY 356 | LOCALPARAM 357 | MACROMODULE 358 | MEDIUM 359 | MODULE 360 | NAND 361 | NEGEDGE 362 | NMOS 363 | NOR 364 | NOSHOWCANCELLED 365 | NOT 366 | NOTIFZERO 367 | NOTIFONE 368 | OR 369 | OUTPUT 370 | PARAMETER 371 | PMOS 372 | POSEDGE 373 | PRIMITIVE 374 | PULLZERO 375 | PULLONE 376 | PULLDOWN 377 | PULLUP 378 | PULSESTYLE_ONDETECT 379 | PULSESTYLE_ONEVENT 380 | RCMOS 381 | REAL 382 | REALTIME 383 | REG 384 | RELEASE 385 | REPEAT 386 | RNMOS 387 | RPMOS 388 | RTRAN 389 | RTRANIFZERO 390 | RTRANIFONE 391 | SCALARED 392 | SHOWCANCELLED 393 | SIGNED 394 | SMALL 395 | SPECIFY 396 | SPECPARAM 397 | STRONGZERO 398 | STRONGONE 399 | SUPPLYZERO 400 | SUPPLYONE 401 | TABLE 402 | TASK 403 | TIME 404 | TRAN 405 | TRANIFZERO 406 | TRANIFONE 407 | TRI 408 | TRIZERO 409 | TRIONE 410 | TRIAND 411 | TRIOR 412 | TRIREG 413 | USE 414 | UWIRE 415 | VECTORED 416 | WAIT 417 | WAND 418 | WEAKZERO 419 | WEAKONE 420 | WHILE 421 | WIRE 422 | WOR 423 | XNOR 424 | XOR 425 | LC 426 | VL 427 | VLVL 428 | RC 429 | TI 430 | TIAM 431 | TICA 432 | TIVL 433 | DECIMAL_NUMBER 434 | BINARY_NUMBER 435 | OCTAL_NUMBER 436 | HEX_NUMBER 437 | REAL_NUMBER 438 | STRING 439 | COMMENT 440 | ESCAPED_IDENTIFIER 441 | SIMPLE_IDENTIFIER 442 | SYSTEM_TF_IDENTIFIER 443 | WHITE_SPACE 444 | MIINCDIR 445 | FILE_PATH_SPEC 446 | OUTPUT_OR_LEVEL_SYMBOL 447 | LEVEL_ONLY_SYMBOL 448 | EDGE_SYMBOL 449 | EDGE_DESCRIPTOR 450 | BEGIN_KEYWORDS_DIRECTIVE 451 | CELLDEFINE_DIRECTIVE 452 | DEFAULT_NETTYPE_DIRECTIVE 453 | DEFINE_DIRECTIVE 454 | ELSE_DIRECTIVE 455 | ELSIF_DIRECTIVE 456 | END_KEYWORDS_DIRECTIVE 457 | ENDCELLDEFINE_DIRECTIVE 458 | ENDIF_DIRECTIVE 459 | IFDEF_DIRECTIVE 460 | IFNDEF_DIRECTIVE 461 | INCLUDE_DIRECTIVE 462 | LINE_DIRECTIVE 463 | NOUNCONNECTED_DRIVE_DIRECTIVE 464 | PRAGMA_DIRECTIVE 465 | RESETALL_DIRECTIVE 466 | TIMESCALE_DIRECTIVE 467 | UNCONNECTED_DRIVE_DIRECTIVE 468 | UNDEF_DIRECTIVE 469 | MACRO_USAGE 470 | DIRECTIVE_TEXT 471 | DIRECTIVE_IDENTIFIER 472 | DIRECTIVE_COMMENT 473 | DIRECTIVE_WHITE_SPACE 474 | DIRECTIVE_NEWLINE 475 | MACRO_TEXT 476 | MACRO_ESC_NEWLINE 477 | SOURCE_TEXT 478 | 479 | rule names: 480 | source_text 481 | compiler_directive 482 | begin_keywords_directive 483 | celldefine_directive 484 | default_nettype_directive 485 | endcelldefine_directive 486 | end_keywords_directive 487 | ifdef_directive 488 | ifndef_directive 489 | include_directive 490 | line_directive 491 | nounconnected_drive_directive 492 | pragma_directive 493 | resetall_directive 494 | text_macro_definition 495 | text_macro_usage 496 | timescale_directive 497 | unconnected_drive_directive 498 | undef_directive 499 | elsif_directive 500 | else_directive 501 | endif_directive 502 | text_macro_identifier 503 | ifdef_group_of_lines 504 | ifndef_group_of_lines 505 | elsif_group_of_lines 506 | else_group_of_lines 507 | macro_text 508 | 509 | 510 | atn: 511 | [4, 1, 236, 215, 2, 0, 7, 0, 2, 1, 7, 1, 2, 2, 7, 2, 2, 3, 7, 3, 2, 4, 7, 4, 2, 5, 7, 5, 2, 6, 7, 6, 2, 7, 7, 7, 2, 8, 7, 8, 2, 9, 7, 9, 2, 10, 7, 10, 2, 11, 7, 11, 2, 12, 7, 12, 2, 13, 7, 13, 2, 14, 7, 14, 2, 15, 7, 15, 2, 16, 7, 16, 2, 17, 7, 17, 2, 18, 7, 18, 2, 19, 7, 19, 2, 20, 7, 20, 2, 21, 7, 21, 2, 22, 7, 22, 2, 23, 7, 23, 2, 24, 7, 24, 2, 25, 7, 25, 2, 26, 7, 26, 2, 27, 7, 27, 1, 0, 5, 0, 58, 8, 0, 10, 0, 12, 0, 61, 9, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 80, 8, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 3, 1, 3, 1, 3, 1, 4, 1, 4, 1, 4, 1, 4, 1, 5, 1, 5, 1, 5, 1, 6, 1, 6, 1, 6, 1, 7, 1, 7, 1, 7, 1, 7, 1, 7, 5, 7, 104, 8, 7, 10, 7, 12, 7, 107, 9, 7, 1, 7, 3, 7, 110, 8, 7, 1, 7, 1, 7, 1, 8, 1, 8, 1, 8, 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0, 0, 192, 49, 1, 0, 0, 0, 193, 191, 1, 0, 0, 0, 194, 197, 5, 236, 0, 0, 195, 197, 3, 2, 1, 0, 196, 194, 1, 0, 0, 0, 196, 195, 1, 0, 0, 0, 197, 200, 1, 0, 0, 0, 198, 196, 1, 0, 0, 0, 198, 199, 1, 0, 0, 0, 199, 51, 1, 0, 0, 0, 200, 198, 1, 0, 0, 0, 201, 204, 5, 236, 0, 0, 202, 204, 3, 2, 1, 0, 203, 201, 1, 0, 0, 0, 203, 202, 1, 0, 0, 0, 204, 207, 1, 0, 0, 0, 205, 203, 1, 0, 0, 0, 205, 206, 1, 0, 0, 0, 206, 53, 1, 0, 0, 0, 207, 205, 1, 0, 0, 0, 208, 210, 7, 0, 0, 0, 209, 208, 1, 0, 0, 0, 210, 213, 1, 0, 0, 0, 211, 209, 1, 0, 0, 0, 211, 212, 1, 0, 0, 0, 212, 55, 1, 0, 0, 0, 213, 211, 1, 0, 0, 0, 15, 59, 79, 105, 109, 120, 124, 182, 184, 189, 191, 196, 198, 203, 205, 211] -------------------------------------------------------------------------------- /test/testrig/verilog/VerilogPreParser.tokens: -------------------------------------------------------------------------------- 1 | EM=1 2 | EMEQ=2 3 | EMEQEQ=3 4 | DQ=4 5 | HA=5 6 | DL=6 7 | DLFULLSKEW=7 8 | DLHOLD=8 9 | DLNOCHANGE=9 10 | DLPERIOD=10 11 | DLRECOVERY=11 12 | DLRECREM=12 13 | DLREMOVAL=13 14 | DLSETUP=14 15 | DLSETUPHOLD=15 16 | DLSKEW=16 17 | DLTIMESKEW=17 18 | DLWIDTH=18 19 | MO=19 20 | AM=20 21 | AMAM=21 22 | AMAMAM=22 23 | AP=23 24 | LP=24 25 | RP=25 26 | AS=26 27 | ASAS=27 28 | ASSL=28 29 | ASGT=29 30 | PL=30 31 | PLCL=31 32 | CO=32 33 | MI=33 34 | MICL=34 35 | MIGT=35 36 | DT=36 37 | SL=37 38 | SLAS=38 39 | SLSL=39 40 | CL=40 41 | SC=41 42 | LT=42 43 | LTLT=43 44 | LTLTLT=44 45 | LTEQ=45 46 | EQ=46 47 | EQEQ=47 48 | EQEQEQ=48 49 | EQGT=49 50 | GT=50 51 | GTEQ=51 52 | GTGT=52 53 | GTGTGT=53 54 | QM=54 55 | AT=55 56 | PATHPULSEDL=56 57 | LB=57 58 | RB=58 59 | CA=59 60 | CATI=60 61 | GA=61 62 | ALWAYS=62 63 | AND=63 64 | ASSIGN=64 65 | AUTOMATIC=65 66 | BEGIN=66 67 | BUF=67 68 | BUFIFZERO=68 69 | BUFIFONE=69 70 | CASE=70 71 | CASEX=71 72 | CASEZ=72 73 | CELL=73 74 | CMOS=74 75 | CONFIG=75 76 | DEASSIGN=76 77 | DEFAULT=77 78 | DEFPARAM=78 79 | DESIGN=79 80 | DISABLE=80 81 | EDGE=81 82 | ELSE=82 83 | END=83 84 | ENDCASE=84 85 | ENDCONFIG=85 86 | ENDFUNCTION=86 87 | ENDGENERATE=87 88 | ENDMODULE=88 89 | ENDPRIMITIVE=89 90 | ENDSPECIFY=90 91 | ENDTABLE=91 92 | ENDTASK=92 93 | EVENT=93 94 | FOR=94 95 | FORCE=95 96 | FOREVER=96 97 | FORK=97 98 | FUNCTION=98 99 | GENERATE=99 100 | GENVAR=100 101 | HIGHZZERO=101 102 | HIGHZONE=102 103 | IF=103 104 | IFNONE=104 105 | INCLUDE=105 106 | INITIAL=106 107 | INOUT=107 108 | INPUT=108 109 | INSTANCE=109 110 | INTEGER=110 111 | JOIN=111 112 | LARGE=112 113 | LIBLIST=113 114 | LIBRARY=114 115 | LOCALPARAM=115 116 | MACROMODULE=116 117 | MEDIUM=117 118 | MODULE=118 119 | NAND=119 120 | NEGEDGE=120 121 | NMOS=121 122 | NOR=122 123 | NOSHOWCANCELLED=123 124 | NOT=124 125 | NOTIFZERO=125 126 | NOTIFONE=126 127 | OR=127 128 | OUTPUT=128 129 | PARAMETER=129 130 | PMOS=130 131 | POSEDGE=131 132 | PRIMITIVE=132 133 | PULLZERO=133 134 | PULLONE=134 135 | PULLDOWN=135 136 | PULLUP=136 137 | PULSESTYLE_ONDETECT=137 138 | PULSESTYLE_ONEVENT=138 139 | RCMOS=139 140 | REAL=140 141 | REALTIME=141 142 | REG=142 143 | RELEASE=143 144 | REPEAT=144 145 | RNMOS=145 146 | RPMOS=146 147 | RTRAN=147 148 | RTRANIFZERO=148 149 | RTRANIFONE=149 150 | SCALARED=150 151 | SHOWCANCELLED=151 152 | SIGNED=152 153 | SMALL=153 154 | SPECIFY=154 155 | SPECPARAM=155 156 | STRONGZERO=156 157 | STRONGONE=157 158 | SUPPLYZERO=158 159 | SUPPLYONE=159 160 | TABLE=160 161 | TASK=161 162 | TIME=162 163 | TRAN=163 164 | TRANIFZERO=164 165 | TRANIFONE=165 166 | TRI=166 167 | TRIZERO=167 168 | TRIONE=168 169 | TRIAND=169 170 | TRIOR=170 171 | TRIREG=171 172 | USE=172 173 | UWIRE=173 174 | VECTORED=174 175 | WAIT=175 176 | WAND=176 177 | WEAKZERO=177 178 | WEAKONE=178 179 | WHILE=179 180 | WIRE=180 181 | WOR=181 182 | XNOR=182 183 | XOR=183 184 | LC=184 185 | VL=185 186 | VLVL=186 187 | RC=187 188 | TI=188 189 | TIAM=189 190 | TICA=190 191 | TIVL=191 192 | DECIMAL_NUMBER=192 193 | BINARY_NUMBER=193 194 | OCTAL_NUMBER=194 195 | HEX_NUMBER=195 196 | REAL_NUMBER=196 197 | STRING=197 198 | COMMENT=198 199 | ESCAPED_IDENTIFIER=199 200 | SIMPLE_IDENTIFIER=200 201 | SYSTEM_TF_IDENTIFIER=201 202 | WHITE_SPACE=202 203 | MIINCDIR=203 204 | FILE_PATH_SPEC=204 205 | OUTPUT_OR_LEVEL_SYMBOL=205 206 | LEVEL_ONLY_SYMBOL=206 207 | EDGE_SYMBOL=207 208 | EDGE_DESCRIPTOR=208 209 | BEGIN_KEYWORDS_DIRECTIVE=209 210 | CELLDEFINE_DIRECTIVE=210 211 | DEFAULT_NETTYPE_DIRECTIVE=211 212 | DEFINE_DIRECTIVE=212 213 | ELSE_DIRECTIVE=213 214 | ELSIF_DIRECTIVE=214 215 | END_KEYWORDS_DIRECTIVE=215 216 | ENDCELLDEFINE_DIRECTIVE=216 217 | ENDIF_DIRECTIVE=217 218 | IFDEF_DIRECTIVE=218 219 | IFNDEF_DIRECTIVE=219 220 | INCLUDE_DIRECTIVE=220 221 | LINE_DIRECTIVE=221 222 | NOUNCONNECTED_DRIVE_DIRECTIVE=222 223 | PRAGMA_DIRECTIVE=223 224 | RESETALL_DIRECTIVE=224 225 | TIMESCALE_DIRECTIVE=225 226 | UNCONNECTED_DRIVE_DIRECTIVE=226 227 | UNDEF_DIRECTIVE=227 228 | MACRO_USAGE=228 229 | DIRECTIVE_TEXT=229 230 | DIRECTIVE_IDENTIFIER=230 231 | DIRECTIVE_COMMENT=231 232 | DIRECTIVE_WHITE_SPACE=232 233 | DIRECTIVE_NEWLINE=233 234 | MACRO_TEXT=234 235 | MACRO_ESC_NEWLINE=235 236 | SOURCE_TEXT=236 237 | '!'=1 238 | '!='=2 239 | '!=='=3 240 | '"'=4 241 | '#'=5 242 | '$'=6 243 | '$fullskew'=7 244 | '$hold'=8 245 | '$nochange'=9 246 | '$period'=10 247 | '$recovery'=11 248 | '$recrem'=12 249 | '$removal'=13 250 | '$setup'=14 251 | '$setuphold'=15 252 | '$skew'=16 253 | '$timeskew'=17 254 | '$width'=18 255 | '%'=19 256 | '&'=20 257 | '&&'=21 258 | '&&&'=22 259 | '\''=23 260 | '('=24 261 | ')'=25 262 | '*'=26 263 | '**'=27 264 | '*/'=28 265 | '*>'=29 266 | '+'=30 267 | '+:'=31 268 | ','=32 269 | '-'=33 270 | '-:'=34 271 | '->'=35 272 | '.'=36 273 | '/'=37 274 | '/*'=38 275 | '//'=39 276 | ':'=40 277 | ';'=41 278 | '<'=42 279 | '<<'=43 280 | '<<<'=44 281 | '<='=45 282 | '='=46 283 | '=='=47 284 | '==='=48 285 | '=>'=49 286 | '>'=50 287 | '>='=51 288 | '>>'=52 289 | '>>>'=53 290 | '?'=54 291 | '@'=55 292 | 'PATHPULSE$'=56 293 | '['=57 294 | ']'=58 295 | '^'=59 296 | '^~'=60 297 | 'always'=62 298 | 'and'=63 299 | 'assign'=64 300 | 'automatic'=65 301 | 'begin'=66 302 | 'buf'=67 303 | 'bufif0'=68 304 | 'bufif1'=69 305 | 'case'=70 306 | 'casex'=71 307 | 'casez'=72 308 | 'cell'=73 309 | 'cmos'=74 310 | 'config'=75 311 | 'deassign'=76 312 | 'default'=77 313 | 'defparam'=78 314 | 'design'=79 315 | 'disable'=80 316 | 'edge'=81 317 | 'else'=82 318 | 'end'=83 319 | 'endcase'=84 320 | 'endconfig'=85 321 | 'endfunction'=86 322 | 'endgenerate'=87 323 | 'endmodule'=88 324 | 'endprimitive'=89 325 | 'endspecify'=90 326 | 'endtable'=91 327 | 'endtask'=92 328 | 'event'=93 329 | 'for'=94 330 | 'force'=95 331 | 'forever'=96 332 | 'fork'=97 333 | 'function'=98 334 | 'generate'=99 335 | 'genvar'=100 336 | 'highz0'=101 337 | 'highz1'=102 338 | 'if'=103 339 | 'ifnone'=104 340 | 'include'=105 341 | 'initial'=106 342 | 'inout'=107 343 | 'input'=108 344 | 'instance'=109 345 | 'integer'=110 346 | 'join'=111 347 | 'large'=112 348 | 'liblist'=113 349 | 'library'=114 350 | 'localparam'=115 351 | 'macromodule'=116 352 | 'medium'=117 353 | 'module'=118 354 | 'nand'=119 355 | 'negedge'=120 356 | 'nmos'=121 357 | 'nor'=122 358 | 'noshowcancelled'=123 359 | 'not'=124 360 | 'notif0'=125 361 | 'notif1'=126 362 | 'or'=127 363 | 'output'=128 364 | 'parameter'=129 365 | 'pmos'=130 366 | 'posedge'=131 367 | 'primitive'=132 368 | 'pull0'=133 369 | 'pull1'=134 370 | 'pulldown'=135 371 | 'pullup'=136 372 | 'pulsestyle_ondetect'=137 373 | 'pulsestyle_onevent'=138 374 | 'rcmos'=139 375 | 'real'=140 376 | 'realtime'=141 377 | 'reg'=142 378 | 'release'=143 379 | 'repeat'=144 380 | 'rnmos'=145 381 | 'rpmos'=146 382 | 'rtran'=147 383 | 'rtranif0'=148 384 | 'rtranif1'=149 385 | 'scalared'=150 386 | 'showcancelled'=151 387 | 'signed'=152 388 | 'small'=153 389 | 'specify'=154 390 | 'specparam'=155 391 | 'strong0'=156 392 | 'strong1'=157 393 | 'supply0'=158 394 | 'supply1'=159 395 | 'table'=160 396 | 'task'=161 397 | 'time'=162 398 | 'tran'=163 399 | 'tranif0'=164 400 | 'tranif1'=165 401 | 'tri'=166 402 | 'tri0'=167 403 | 'tri1'=168 404 | 'triand'=169 405 | 'trior'=170 406 | 'trireg'=171 407 | 'use'=172 408 | 'uwire'=173 409 | 'vectored'=174 410 | 'wait'=175 411 | 'wand'=176 412 | 'weak0'=177 413 | 'weak1'=178 414 | 'while'=179 415 | 'wire'=180 416 | 'wor'=181 417 | 'xnor'=182 418 | 'xor'=183 419 | '{'=184 420 | '|'=185 421 | '||'=186 422 | '}'=187 423 | '~'=188 424 | '~&'=189 425 | '~^'=190 426 | '~|'=191 427 | '-incdir'=203 428 | 'celldefine'=210 429 | 'end_keywords'=215 430 | 'endcelldefine'=216 431 | 'nounconnected_drive'=222 432 | 'resetall'=224 433 | -------------------------------------------------------------------------------- /test/testrig/verilog/VerilogPreParserBaseListener.java: -------------------------------------------------------------------------------- 1 | // Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 by ANTLR 4.10.1 2 | 3 | import org.antlr.v4.runtime.ParserRuleContext; 4 | import org.antlr.v4.runtime.tree.ErrorNode; 5 | import org.antlr.v4.runtime.tree.TerminalNode; 6 | 7 | /** 8 | * This class provides an empty implementation of {@link VerilogPreParserListener}, 9 | * which can be extended to create a listener which only needs to handle a subset 10 | * of the available methods. 11 | */ 12 | public class VerilogPreParserBaseListener implements VerilogPreParserListener { 13 | /** 14 | * {@inheritDoc} 15 | * 16 | *

The default implementation does nothing.

17 | */ 18 | @Override public void enterSource_text(VerilogPreParser.Source_textContext ctx) { } 19 | /** 20 | * {@inheritDoc} 21 | * 22 | *

The default implementation does nothing.

23 | */ 24 | @Override public void exitSource_text(VerilogPreParser.Source_textContext ctx) { } 25 | /** 26 | * {@inheritDoc} 27 | * 28 | *

The default implementation does nothing.

29 | */ 30 | @Override public void enterCompiler_directive(VerilogPreParser.Compiler_directiveContext ctx) { } 31 | /** 32 | * {@inheritDoc} 33 | * 34 | *

The default implementation does nothing.

35 | */ 36 | @Override public void exitCompiler_directive(VerilogPreParser.Compiler_directiveContext ctx) { } 37 | /** 38 | * {@inheritDoc} 39 | * 40 | *

The default implementation does nothing.

41 | */ 42 | @Override public void enterBegin_keywords_directive(VerilogPreParser.Begin_keywords_directiveContext ctx) { } 43 | /** 44 | * {@inheritDoc} 45 | * 46 | *

The default implementation does nothing.

47 | */ 48 | @Override public void exitBegin_keywords_directive(VerilogPreParser.Begin_keywords_directiveContext ctx) { } 49 | /** 50 | * {@inheritDoc} 51 | * 52 | *

The default implementation does nothing.

53 | */ 54 | @Override public void enterCelldefine_directive(VerilogPreParser.Celldefine_directiveContext ctx) { } 55 | /** 56 | * {@inheritDoc} 57 | * 58 | *

The default implementation does nothing.

59 | */ 60 | @Override public void exitCelldefine_directive(VerilogPreParser.Celldefine_directiveContext ctx) { } 61 | /** 62 | * {@inheritDoc} 63 | * 64 | *

The default implementation does nothing.

65 | */ 66 | @Override public void enterDefault_nettype_directive(VerilogPreParser.Default_nettype_directiveContext ctx) { } 67 | /** 68 | * {@inheritDoc} 69 | * 70 | *

The default implementation does nothing.

71 | */ 72 | @Override public void exitDefault_nettype_directive(VerilogPreParser.Default_nettype_directiveContext ctx) { } 73 | /** 74 | * {@inheritDoc} 75 | * 76 | *

The default implementation does nothing.

77 | */ 78 | @Override public void enterEndcelldefine_directive(VerilogPreParser.Endcelldefine_directiveContext ctx) { } 79 | /** 80 | * {@inheritDoc} 81 | * 82 | *

The default implementation does nothing.

83 | */ 84 | @Override public void exitEndcelldefine_directive(VerilogPreParser.Endcelldefine_directiveContext ctx) { } 85 | /** 86 | * {@inheritDoc} 87 | * 88 | *

The default implementation does nothing.

89 | */ 90 | @Override public void enterEnd_keywords_directive(VerilogPreParser.End_keywords_directiveContext ctx) { } 91 | /** 92 | * {@inheritDoc} 93 | * 94 | *

The default implementation does nothing.

95 | */ 96 | @Override public void exitEnd_keywords_directive(VerilogPreParser.End_keywords_directiveContext ctx) { } 97 | /** 98 | * {@inheritDoc} 99 | * 100 | *

The default implementation does nothing.

101 | */ 102 | @Override public void enterIfdef_directive(VerilogPreParser.Ifdef_directiveContext ctx) { } 103 | /** 104 | * {@inheritDoc} 105 | * 106 | *

The default implementation does nothing.

107 | */ 108 | @Override public void exitIfdef_directive(VerilogPreParser.Ifdef_directiveContext ctx) { } 109 | /** 110 | * {@inheritDoc} 111 | * 112 | *

The default implementation does nothing.

113 | */ 114 | @Override public void enterIfndef_directive(VerilogPreParser.Ifndef_directiveContext ctx) { } 115 | /** 116 | * {@inheritDoc} 117 | * 118 | *

The default implementation does nothing.

119 | */ 120 | @Override public void exitIfndef_directive(VerilogPreParser.Ifndef_directiveContext ctx) { } 121 | /** 122 | * {@inheritDoc} 123 | * 124 | *

The default implementation does nothing.

125 | */ 126 | @Override public void enterInclude_directive(VerilogPreParser.Include_directiveContext ctx) { } 127 | /** 128 | * {@inheritDoc} 129 | * 130 | *

The default implementation does nothing.

131 | */ 132 | @Override public void exitInclude_directive(VerilogPreParser.Include_directiveContext ctx) { } 133 | /** 134 | * {@inheritDoc} 135 | * 136 | *

The default implementation does nothing.

137 | */ 138 | @Override public void enterLine_directive(VerilogPreParser.Line_directiveContext ctx) { } 139 | /** 140 | * {@inheritDoc} 141 | * 142 | *

The default implementation does nothing.

143 | */ 144 | @Override public void exitLine_directive(VerilogPreParser.Line_directiveContext ctx) { } 145 | /** 146 | * {@inheritDoc} 147 | * 148 | *

The default implementation does nothing.

149 | */ 150 | @Override public void enterNounconnected_drive_directive(VerilogPreParser.Nounconnected_drive_directiveContext ctx) { } 151 | /** 152 | * {@inheritDoc} 153 | * 154 | *

The default implementation does nothing.

155 | */ 156 | @Override public void exitNounconnected_drive_directive(VerilogPreParser.Nounconnected_drive_directiveContext ctx) { } 157 | /** 158 | * {@inheritDoc} 159 | * 160 | *

The default implementation does nothing.

161 | */ 162 | @Override public void enterPragma_directive(VerilogPreParser.Pragma_directiveContext ctx) { } 163 | /** 164 | * {@inheritDoc} 165 | * 166 | *

The default implementation does nothing.

167 | */ 168 | @Override public void exitPragma_directive(VerilogPreParser.Pragma_directiveContext ctx) { } 169 | /** 170 | * {@inheritDoc} 171 | * 172 | *

The default implementation does nothing.

173 | */ 174 | @Override public void enterResetall_directive(VerilogPreParser.Resetall_directiveContext ctx) { } 175 | /** 176 | * {@inheritDoc} 177 | * 178 | *

The default implementation does nothing.

179 | */ 180 | @Override public void exitResetall_directive(VerilogPreParser.Resetall_directiveContext ctx) { } 181 | /** 182 | * {@inheritDoc} 183 | * 184 | *

The default implementation does nothing.

185 | */ 186 | @Override public void enterText_macro_definition(VerilogPreParser.Text_macro_definitionContext ctx) { } 187 | /** 188 | * {@inheritDoc} 189 | * 190 | *

The default implementation does nothing.

191 | */ 192 | @Override public void exitText_macro_definition(VerilogPreParser.Text_macro_definitionContext ctx) { } 193 | /** 194 | * {@inheritDoc} 195 | * 196 | *

The default implementation does nothing.

197 | */ 198 | @Override public void enterText_macro_usage(VerilogPreParser.Text_macro_usageContext ctx) { } 199 | /** 200 | * {@inheritDoc} 201 | * 202 | *

The default implementation does nothing.

203 | */ 204 | @Override public void exitText_macro_usage(VerilogPreParser.Text_macro_usageContext ctx) { } 205 | /** 206 | * {@inheritDoc} 207 | * 208 | *

The default implementation does nothing.

209 | */ 210 | @Override public void enterTimescale_directive(VerilogPreParser.Timescale_directiveContext ctx) { } 211 | /** 212 | * {@inheritDoc} 213 | * 214 | *

The default implementation does nothing.

215 | */ 216 | @Override public void exitTimescale_directive(VerilogPreParser.Timescale_directiveContext ctx) { } 217 | /** 218 | * {@inheritDoc} 219 | * 220 | *

The default implementation does nothing.

221 | */ 222 | @Override public void enterUnconnected_drive_directive(VerilogPreParser.Unconnected_drive_directiveContext ctx) { } 223 | /** 224 | * {@inheritDoc} 225 | * 226 | *

The default implementation does nothing.

227 | */ 228 | @Override public void exitUnconnected_drive_directive(VerilogPreParser.Unconnected_drive_directiveContext ctx) { } 229 | /** 230 | * {@inheritDoc} 231 | * 232 | *

The default implementation does nothing.

233 | */ 234 | @Override public void enterUndef_directive(VerilogPreParser.Undef_directiveContext ctx) { } 235 | /** 236 | * {@inheritDoc} 237 | * 238 | *

The default implementation does nothing.

239 | */ 240 | @Override public void exitUndef_directive(VerilogPreParser.Undef_directiveContext ctx) { } 241 | /** 242 | * {@inheritDoc} 243 | * 244 | *

The default implementation does nothing.

245 | */ 246 | @Override public void enterElsif_directive(VerilogPreParser.Elsif_directiveContext ctx) { } 247 | /** 248 | * {@inheritDoc} 249 | * 250 | *

The default implementation does nothing.

251 | */ 252 | @Override public void exitElsif_directive(VerilogPreParser.Elsif_directiveContext ctx) { } 253 | /** 254 | * {@inheritDoc} 255 | * 256 | *

The default implementation does nothing.

257 | */ 258 | @Override public void enterElse_directive(VerilogPreParser.Else_directiveContext ctx) { } 259 | /** 260 | * {@inheritDoc} 261 | * 262 | *

The default implementation does nothing.

263 | */ 264 | @Override public void exitElse_directive(VerilogPreParser.Else_directiveContext ctx) { } 265 | /** 266 | * {@inheritDoc} 267 | * 268 | *

The default implementation does nothing.

269 | */ 270 | @Override public void enterEndif_directive(VerilogPreParser.Endif_directiveContext ctx) { } 271 | /** 272 | * {@inheritDoc} 273 | * 274 | *

The default implementation does nothing.

275 | */ 276 | @Override public void exitEndif_directive(VerilogPreParser.Endif_directiveContext ctx) { } 277 | /** 278 | * {@inheritDoc} 279 | * 280 | *

The default implementation does nothing.

281 | */ 282 | @Override public void enterText_macro_identifier(VerilogPreParser.Text_macro_identifierContext ctx) { } 283 | /** 284 | * {@inheritDoc} 285 | * 286 | *

The default implementation does nothing.

287 | */ 288 | @Override public void exitText_macro_identifier(VerilogPreParser.Text_macro_identifierContext ctx) { } 289 | /** 290 | * {@inheritDoc} 291 | * 292 | *

The default implementation does nothing.

293 | */ 294 | @Override public void enterIfdef_group_of_lines(VerilogPreParser.Ifdef_group_of_linesContext ctx) { } 295 | /** 296 | * {@inheritDoc} 297 | * 298 | *

The default implementation does nothing.

299 | */ 300 | @Override public void exitIfdef_group_of_lines(VerilogPreParser.Ifdef_group_of_linesContext ctx) { } 301 | /** 302 | * {@inheritDoc} 303 | * 304 | *

The default implementation does nothing.

305 | */ 306 | @Override public void enterIfndef_group_of_lines(VerilogPreParser.Ifndef_group_of_linesContext ctx) { } 307 | /** 308 | * {@inheritDoc} 309 | * 310 | *

The default implementation does nothing.

311 | */ 312 | @Override public void exitIfndef_group_of_lines(VerilogPreParser.Ifndef_group_of_linesContext ctx) { } 313 | /** 314 | * {@inheritDoc} 315 | * 316 | *

The default implementation does nothing.

317 | */ 318 | @Override public void enterElsif_group_of_lines(VerilogPreParser.Elsif_group_of_linesContext ctx) { } 319 | /** 320 | * {@inheritDoc} 321 | * 322 | *

The default implementation does nothing.

323 | */ 324 | @Override public void exitElsif_group_of_lines(VerilogPreParser.Elsif_group_of_linesContext ctx) { } 325 | /** 326 | * {@inheritDoc} 327 | * 328 | *

The default implementation does nothing.

329 | */ 330 | @Override public void enterElse_group_of_lines(VerilogPreParser.Else_group_of_linesContext ctx) { } 331 | /** 332 | * {@inheritDoc} 333 | * 334 | *

The default implementation does nothing.

335 | */ 336 | @Override public void exitElse_group_of_lines(VerilogPreParser.Else_group_of_linesContext ctx) { } 337 | /** 338 | * {@inheritDoc} 339 | * 340 | *

The default implementation does nothing.

341 | */ 342 | @Override public void enterMacro_text(VerilogPreParser.Macro_textContext ctx) { } 343 | /** 344 | * {@inheritDoc} 345 | * 346 | *

The default implementation does nothing.

347 | */ 348 | @Override public void exitMacro_text(VerilogPreParser.Macro_textContext ctx) { } 349 | 350 | /** 351 | * {@inheritDoc} 352 | * 353 | *

The default implementation does nothing.

354 | */ 355 | @Override public void enterEveryRule(ParserRuleContext ctx) { } 356 | /** 357 | * {@inheritDoc} 358 | * 359 | *

The default implementation does nothing.

360 | */ 361 | @Override public void exitEveryRule(ParserRuleContext ctx) { } 362 | /** 363 | * {@inheritDoc} 364 | * 365 | *

The default implementation does nothing.

366 | */ 367 | @Override public void visitTerminal(TerminalNode node) { } 368 | /** 369 | * {@inheritDoc} 370 | * 371 | *

The default implementation does nothing.

372 | */ 373 | @Override public void visitErrorNode(ErrorNode node) { } 374 | } -------------------------------------------------------------------------------- /test/testrig/verilog/VerilogPreParserBaseVisitor.java: -------------------------------------------------------------------------------- 1 | // Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 by ANTLR 4.10.1 2 | import org.antlr.v4.runtime.tree.AbstractParseTreeVisitor; 3 | 4 | /** 5 | * This class provides an empty implementation of {@link VerilogPreParserVisitor}, 6 | * which can be extended to create a visitor which only needs to handle a subset 7 | * of the available methods. 8 | * 9 | * @param The return type of the visit operation. Use {@link Void} for 10 | * operations with no return type. 11 | */ 12 | public class VerilogPreParserBaseVisitor extends AbstractParseTreeVisitor implements VerilogPreParserVisitor { 13 | /** 14 | * {@inheritDoc} 15 | * 16 | *

The default implementation returns the result of calling 17 | * {@link #visitChildren} on {@code ctx}.

18 | */ 19 | @Override public T visitSource_text(VerilogPreParser.Source_textContext ctx) { return visitChildren(ctx); } 20 | /** 21 | * {@inheritDoc} 22 | * 23 | *

The default implementation returns the result of calling 24 | * {@link #visitChildren} on {@code ctx}.

25 | */ 26 | @Override public T visitCompiler_directive(VerilogPreParser.Compiler_directiveContext ctx) { return visitChildren(ctx); } 27 | /** 28 | * {@inheritDoc} 29 | * 30 | *

The default implementation returns the result of calling 31 | * {@link #visitChildren} on {@code ctx}.

32 | */ 33 | @Override public T visitBegin_keywords_directive(VerilogPreParser.Begin_keywords_directiveContext ctx) { return visitChildren(ctx); } 34 | /** 35 | * {@inheritDoc} 36 | * 37 | *

The default implementation returns the result of calling 38 | * {@link #visitChildren} on {@code ctx}.

39 | */ 40 | @Override public T visitCelldefine_directive(VerilogPreParser.Celldefine_directiveContext ctx) { return visitChildren(ctx); } 41 | /** 42 | * {@inheritDoc} 43 | * 44 | *

The default implementation returns the result of calling 45 | * {@link #visitChildren} on {@code ctx}.

46 | */ 47 | @Override public T visitDefault_nettype_directive(VerilogPreParser.Default_nettype_directiveContext ctx) { return visitChildren(ctx); } 48 | /** 49 | * {@inheritDoc} 50 | * 51 | *

The default implementation returns the result of calling 52 | * {@link #visitChildren} on {@code ctx}.

53 | */ 54 | @Override public T visitEndcelldefine_directive(VerilogPreParser.Endcelldefine_directiveContext ctx) { return visitChildren(ctx); } 55 | /** 56 | * {@inheritDoc} 57 | * 58 | *

The default implementation returns the result of calling 59 | * {@link #visitChildren} on {@code ctx}.

60 | */ 61 | @Override public T visitEnd_keywords_directive(VerilogPreParser.End_keywords_directiveContext ctx) { return visitChildren(ctx); } 62 | /** 63 | * {@inheritDoc} 64 | * 65 | *

The default implementation returns the result of calling 66 | * {@link #visitChildren} on {@code ctx}.

67 | */ 68 | @Override public T visitIfdef_directive(VerilogPreParser.Ifdef_directiveContext ctx) { return visitChildren(ctx); } 69 | /** 70 | * {@inheritDoc} 71 | * 72 | *

The default implementation returns the result of calling 73 | * {@link #visitChildren} on {@code ctx}.

74 | */ 75 | @Override public T visitIfndef_directive(VerilogPreParser.Ifndef_directiveContext ctx) { return visitChildren(ctx); } 76 | /** 77 | * {@inheritDoc} 78 | * 79 | *

The default implementation returns the result of calling 80 | * {@link #visitChildren} on {@code ctx}.

81 | */ 82 | @Override public T visitInclude_directive(VerilogPreParser.Include_directiveContext ctx) { return visitChildren(ctx); } 83 | /** 84 | * {@inheritDoc} 85 | * 86 | *

The default implementation returns the result of calling 87 | * {@link #visitChildren} on {@code ctx}.

88 | */ 89 | @Override public T visitLine_directive(VerilogPreParser.Line_directiveContext ctx) { return visitChildren(ctx); } 90 | /** 91 | * {@inheritDoc} 92 | * 93 | *

The default implementation returns the result of calling 94 | * {@link #visitChildren} on {@code ctx}.

95 | */ 96 | @Override public T visitNounconnected_drive_directive(VerilogPreParser.Nounconnected_drive_directiveContext ctx) { return visitChildren(ctx); } 97 | /** 98 | * {@inheritDoc} 99 | * 100 | *

The default implementation returns the result of calling 101 | * {@link #visitChildren} on {@code ctx}.

102 | */ 103 | @Override public T visitPragma_directive(VerilogPreParser.Pragma_directiveContext ctx) { return visitChildren(ctx); } 104 | /** 105 | * {@inheritDoc} 106 | * 107 | *

The default implementation returns the result of calling 108 | * {@link #visitChildren} on {@code ctx}.

109 | */ 110 | @Override public T visitResetall_directive(VerilogPreParser.Resetall_directiveContext ctx) { return visitChildren(ctx); } 111 | /** 112 | * {@inheritDoc} 113 | * 114 | *

The default implementation returns the result of calling 115 | * {@link #visitChildren} on {@code ctx}.

116 | */ 117 | @Override public T visitText_macro_definition(VerilogPreParser.Text_macro_definitionContext ctx) { return visitChildren(ctx); } 118 | /** 119 | * {@inheritDoc} 120 | * 121 | *

The default implementation returns the result of calling 122 | * {@link #visitChildren} on {@code ctx}.

123 | */ 124 | @Override public T visitText_macro_usage(VerilogPreParser.Text_macro_usageContext ctx) { return visitChildren(ctx); } 125 | /** 126 | * {@inheritDoc} 127 | * 128 | *

The default implementation returns the result of calling 129 | * {@link #visitChildren} on {@code ctx}.

130 | */ 131 | @Override public T visitTimescale_directive(VerilogPreParser.Timescale_directiveContext ctx) { return visitChildren(ctx); } 132 | /** 133 | * {@inheritDoc} 134 | * 135 | *

The default implementation returns the result of calling 136 | * {@link #visitChildren} on {@code ctx}.

137 | */ 138 | @Override public T visitUnconnected_drive_directive(VerilogPreParser.Unconnected_drive_directiveContext ctx) { return visitChildren(ctx); } 139 | /** 140 | * {@inheritDoc} 141 | * 142 | *

The default implementation returns the result of calling 143 | * {@link #visitChildren} on {@code ctx}.

144 | */ 145 | @Override public T visitUndef_directive(VerilogPreParser.Undef_directiveContext ctx) { return visitChildren(ctx); } 146 | /** 147 | * {@inheritDoc} 148 | * 149 | *

The default implementation returns the result of calling 150 | * {@link #visitChildren} on {@code ctx}.

151 | */ 152 | @Override public T visitElsif_directive(VerilogPreParser.Elsif_directiveContext ctx) { return visitChildren(ctx); } 153 | /** 154 | * {@inheritDoc} 155 | * 156 | *

The default implementation returns the result of calling 157 | * {@link #visitChildren} on {@code ctx}.

158 | */ 159 | @Override public T visitElse_directive(VerilogPreParser.Else_directiveContext ctx) { return visitChildren(ctx); } 160 | /** 161 | * {@inheritDoc} 162 | * 163 | *

The default implementation returns the result of calling 164 | * {@link #visitChildren} on {@code ctx}.

165 | */ 166 | @Override public T visitEndif_directive(VerilogPreParser.Endif_directiveContext ctx) { return visitChildren(ctx); } 167 | /** 168 | * {@inheritDoc} 169 | * 170 | *

The default implementation returns the result of calling 171 | * {@link #visitChildren} on {@code ctx}.

172 | */ 173 | @Override public T visitText_macro_identifier(VerilogPreParser.Text_macro_identifierContext ctx) { return visitChildren(ctx); } 174 | /** 175 | * {@inheritDoc} 176 | * 177 | *

The default implementation returns the result of calling 178 | * {@link #visitChildren} on {@code ctx}.

179 | */ 180 | @Override public T visitIfdef_group_of_lines(VerilogPreParser.Ifdef_group_of_linesContext ctx) { return visitChildren(ctx); } 181 | /** 182 | * {@inheritDoc} 183 | * 184 | *

The default implementation returns the result of calling 185 | * {@link #visitChildren} on {@code ctx}.

186 | */ 187 | @Override public T visitIfndef_group_of_lines(VerilogPreParser.Ifndef_group_of_linesContext ctx) { return visitChildren(ctx); } 188 | /** 189 | * {@inheritDoc} 190 | * 191 | *

The default implementation returns the result of calling 192 | * {@link #visitChildren} on {@code ctx}.

193 | */ 194 | @Override public T visitElsif_group_of_lines(VerilogPreParser.Elsif_group_of_linesContext ctx) { return visitChildren(ctx); } 195 | /** 196 | * {@inheritDoc} 197 | * 198 | *

The default implementation returns the result of calling 199 | * {@link #visitChildren} on {@code ctx}.

200 | */ 201 | @Override public T visitElse_group_of_lines(VerilogPreParser.Else_group_of_linesContext ctx) { return visitChildren(ctx); } 202 | /** 203 | * {@inheritDoc} 204 | * 205 | *

The default implementation returns the result of calling 206 | * {@link #visitChildren} on {@code ctx}.

207 | */ 208 | @Override public T visitMacro_text(VerilogPreParser.Macro_textContext ctx) { return visitChildren(ctx); } 209 | } -------------------------------------------------------------------------------- /test/testrig/verilog/VerilogPreParserListener.java: -------------------------------------------------------------------------------- 1 | // Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 by ANTLR 4.10.1 2 | import org.antlr.v4.runtime.tree.ParseTreeListener; 3 | 4 | /** 5 | * This interface defines a complete listener for a parse tree produced by 6 | * {@link VerilogPreParser}. 7 | */ 8 | public interface VerilogPreParserListener extends ParseTreeListener { 9 | /** 10 | * Enter a parse tree produced by {@link VerilogPreParser#source_text}. 11 | * @param ctx the parse tree 12 | */ 13 | void enterSource_text(VerilogPreParser.Source_textContext ctx); 14 | /** 15 | * Exit a parse tree produced by {@link VerilogPreParser#source_text}. 16 | * @param ctx the parse tree 17 | */ 18 | void exitSource_text(VerilogPreParser.Source_textContext ctx); 19 | /** 20 | * Enter a parse tree produced by {@link VerilogPreParser#compiler_directive}. 21 | * @param ctx the parse tree 22 | */ 23 | void enterCompiler_directive(VerilogPreParser.Compiler_directiveContext ctx); 24 | /** 25 | * Exit a parse tree produced by {@link VerilogPreParser#compiler_directive}. 26 | * @param ctx the parse tree 27 | */ 28 | void exitCompiler_directive(VerilogPreParser.Compiler_directiveContext ctx); 29 | /** 30 | * Enter a parse tree produced by {@link VerilogPreParser#begin_keywords_directive}. 31 | * @param ctx the parse tree 32 | */ 33 | void enterBegin_keywords_directive(VerilogPreParser.Begin_keywords_directiveContext ctx); 34 | /** 35 | * Exit a parse tree produced by {@link VerilogPreParser#begin_keywords_directive}. 36 | * @param ctx the parse tree 37 | */ 38 | void exitBegin_keywords_directive(VerilogPreParser.Begin_keywords_directiveContext ctx); 39 | /** 40 | * Enter a parse tree produced by {@link VerilogPreParser#celldefine_directive}. 41 | * @param ctx the parse tree 42 | */ 43 | void enterCelldefine_directive(VerilogPreParser.Celldefine_directiveContext ctx); 44 | /** 45 | * Exit a parse tree produced by {@link VerilogPreParser#celldefine_directive}. 46 | * @param ctx the parse tree 47 | */ 48 | void exitCelldefine_directive(VerilogPreParser.Celldefine_directiveContext ctx); 49 | /** 50 | * Enter a parse tree produced by {@link VerilogPreParser#default_nettype_directive}. 51 | * @param ctx the parse tree 52 | */ 53 | void enterDefault_nettype_directive(VerilogPreParser.Default_nettype_directiveContext ctx); 54 | /** 55 | * Exit a parse tree produced by {@link VerilogPreParser#default_nettype_directive}. 56 | * @param ctx the parse tree 57 | */ 58 | void exitDefault_nettype_directive(VerilogPreParser.Default_nettype_directiveContext ctx); 59 | /** 60 | * Enter a parse tree produced by {@link VerilogPreParser#endcelldefine_directive}. 61 | * @param ctx the parse tree 62 | */ 63 | void enterEndcelldefine_directive(VerilogPreParser.Endcelldefine_directiveContext ctx); 64 | /** 65 | * Exit a parse tree produced by {@link VerilogPreParser#endcelldefine_directive}. 66 | * @param ctx the parse tree 67 | */ 68 | void exitEndcelldefine_directive(VerilogPreParser.Endcelldefine_directiveContext ctx); 69 | /** 70 | * Enter a parse tree produced by {@link VerilogPreParser#end_keywords_directive}. 71 | * @param ctx the parse tree 72 | */ 73 | void enterEnd_keywords_directive(VerilogPreParser.End_keywords_directiveContext ctx); 74 | /** 75 | * Exit a parse tree produced by {@link VerilogPreParser#end_keywords_directive}. 76 | * @param ctx the parse tree 77 | */ 78 | void exitEnd_keywords_directive(VerilogPreParser.End_keywords_directiveContext ctx); 79 | /** 80 | * Enter a parse tree produced by {@link VerilogPreParser#ifdef_directive}. 81 | * @param ctx the parse tree 82 | */ 83 | void enterIfdef_directive(VerilogPreParser.Ifdef_directiveContext ctx); 84 | /** 85 | * Exit a parse tree produced by {@link VerilogPreParser#ifdef_directive}. 86 | * @param ctx the parse tree 87 | */ 88 | void exitIfdef_directive(VerilogPreParser.Ifdef_directiveContext ctx); 89 | /** 90 | * Enter a parse tree produced by {@link VerilogPreParser#ifndef_directive}. 91 | * @param ctx the parse tree 92 | */ 93 | void enterIfndef_directive(VerilogPreParser.Ifndef_directiveContext ctx); 94 | /** 95 | * Exit a parse tree produced by {@link VerilogPreParser#ifndef_directive}. 96 | * @param ctx the parse tree 97 | */ 98 | void exitIfndef_directive(VerilogPreParser.Ifndef_directiveContext ctx); 99 | /** 100 | * Enter a parse tree produced by {@link VerilogPreParser#include_directive}. 101 | * @param ctx the parse tree 102 | */ 103 | void enterInclude_directive(VerilogPreParser.Include_directiveContext ctx); 104 | /** 105 | * Exit a parse tree produced by {@link VerilogPreParser#include_directive}. 106 | * @param ctx the parse tree 107 | */ 108 | void exitInclude_directive(VerilogPreParser.Include_directiveContext ctx); 109 | /** 110 | * Enter a parse tree produced by {@link VerilogPreParser#line_directive}. 111 | * @param ctx the parse tree 112 | */ 113 | void enterLine_directive(VerilogPreParser.Line_directiveContext ctx); 114 | /** 115 | * Exit a parse tree produced by {@link VerilogPreParser#line_directive}. 116 | * @param ctx the parse tree 117 | */ 118 | void exitLine_directive(VerilogPreParser.Line_directiveContext ctx); 119 | /** 120 | * Enter a parse tree produced by {@link VerilogPreParser#nounconnected_drive_directive}. 121 | * @param ctx the parse tree 122 | */ 123 | void enterNounconnected_drive_directive(VerilogPreParser.Nounconnected_drive_directiveContext ctx); 124 | /** 125 | * Exit a parse tree produced by {@link VerilogPreParser#nounconnected_drive_directive}. 126 | * @param ctx the parse tree 127 | */ 128 | void exitNounconnected_drive_directive(VerilogPreParser.Nounconnected_drive_directiveContext ctx); 129 | /** 130 | * Enter a parse tree produced by {@link VerilogPreParser#pragma_directive}. 131 | * @param ctx the parse tree 132 | */ 133 | void enterPragma_directive(VerilogPreParser.Pragma_directiveContext ctx); 134 | /** 135 | * Exit a parse tree produced by {@link VerilogPreParser#pragma_directive}. 136 | * @param ctx the parse tree 137 | */ 138 | void exitPragma_directive(VerilogPreParser.Pragma_directiveContext ctx); 139 | /** 140 | * Enter a parse tree produced by {@link VerilogPreParser#resetall_directive}. 141 | * @param ctx the parse tree 142 | */ 143 | void enterResetall_directive(VerilogPreParser.Resetall_directiveContext ctx); 144 | /** 145 | * Exit a parse tree produced by {@link VerilogPreParser#resetall_directive}. 146 | * @param ctx the parse tree 147 | */ 148 | void exitResetall_directive(VerilogPreParser.Resetall_directiveContext ctx); 149 | /** 150 | * Enter a parse tree produced by {@link VerilogPreParser#text_macro_definition}. 151 | * @param ctx the parse tree 152 | */ 153 | void enterText_macro_definition(VerilogPreParser.Text_macro_definitionContext ctx); 154 | /** 155 | * Exit a parse tree produced by {@link VerilogPreParser#text_macro_definition}. 156 | * @param ctx the parse tree 157 | */ 158 | void exitText_macro_definition(VerilogPreParser.Text_macro_definitionContext ctx); 159 | /** 160 | * Enter a parse tree produced by {@link VerilogPreParser#text_macro_usage}. 161 | * @param ctx the parse tree 162 | */ 163 | void enterText_macro_usage(VerilogPreParser.Text_macro_usageContext ctx); 164 | /** 165 | * Exit a parse tree produced by {@link VerilogPreParser#text_macro_usage}. 166 | * @param ctx the parse tree 167 | */ 168 | void exitText_macro_usage(VerilogPreParser.Text_macro_usageContext ctx); 169 | /** 170 | * Enter a parse tree produced by {@link VerilogPreParser#timescale_directive}. 171 | * @param ctx the parse tree 172 | */ 173 | void enterTimescale_directive(VerilogPreParser.Timescale_directiveContext ctx); 174 | /** 175 | * Exit a parse tree produced by {@link VerilogPreParser#timescale_directive}. 176 | * @param ctx the parse tree 177 | */ 178 | void exitTimescale_directive(VerilogPreParser.Timescale_directiveContext ctx); 179 | /** 180 | * Enter a parse tree produced by {@link VerilogPreParser#unconnected_drive_directive}. 181 | * @param ctx the parse tree 182 | */ 183 | void enterUnconnected_drive_directive(VerilogPreParser.Unconnected_drive_directiveContext ctx); 184 | /** 185 | * Exit a parse tree produced by {@link VerilogPreParser#unconnected_drive_directive}. 186 | * @param ctx the parse tree 187 | */ 188 | void exitUnconnected_drive_directive(VerilogPreParser.Unconnected_drive_directiveContext ctx); 189 | /** 190 | * Enter a parse tree produced by {@link VerilogPreParser#undef_directive}. 191 | * @param ctx the parse tree 192 | */ 193 | void enterUndef_directive(VerilogPreParser.Undef_directiveContext ctx); 194 | /** 195 | * Exit a parse tree produced by {@link VerilogPreParser#undef_directive}. 196 | * @param ctx the parse tree 197 | */ 198 | void exitUndef_directive(VerilogPreParser.Undef_directiveContext ctx); 199 | /** 200 | * Enter a parse tree produced by {@link VerilogPreParser#elsif_directive}. 201 | * @param ctx the parse tree 202 | */ 203 | void enterElsif_directive(VerilogPreParser.Elsif_directiveContext ctx); 204 | /** 205 | * Exit a parse tree produced by {@link VerilogPreParser#elsif_directive}. 206 | * @param ctx the parse tree 207 | */ 208 | void exitElsif_directive(VerilogPreParser.Elsif_directiveContext ctx); 209 | /** 210 | * Enter a parse tree produced by {@link VerilogPreParser#else_directive}. 211 | * @param ctx the parse tree 212 | */ 213 | void enterElse_directive(VerilogPreParser.Else_directiveContext ctx); 214 | /** 215 | * Exit a parse tree produced by {@link VerilogPreParser#else_directive}. 216 | * @param ctx the parse tree 217 | */ 218 | void exitElse_directive(VerilogPreParser.Else_directiveContext ctx); 219 | /** 220 | * Enter a parse tree produced by {@link VerilogPreParser#endif_directive}. 221 | * @param ctx the parse tree 222 | */ 223 | void enterEndif_directive(VerilogPreParser.Endif_directiveContext ctx); 224 | /** 225 | * Exit a parse tree produced by {@link VerilogPreParser#endif_directive}. 226 | * @param ctx the parse tree 227 | */ 228 | void exitEndif_directive(VerilogPreParser.Endif_directiveContext ctx); 229 | /** 230 | * Enter a parse tree produced by {@link VerilogPreParser#text_macro_identifier}. 231 | * @param ctx the parse tree 232 | */ 233 | void enterText_macro_identifier(VerilogPreParser.Text_macro_identifierContext ctx); 234 | /** 235 | * Exit a parse tree produced by {@link VerilogPreParser#text_macro_identifier}. 236 | * @param ctx the parse tree 237 | */ 238 | void exitText_macro_identifier(VerilogPreParser.Text_macro_identifierContext ctx); 239 | /** 240 | * Enter a parse tree produced by {@link VerilogPreParser#ifdef_group_of_lines}. 241 | * @param ctx the parse tree 242 | */ 243 | void enterIfdef_group_of_lines(VerilogPreParser.Ifdef_group_of_linesContext ctx); 244 | /** 245 | * Exit a parse tree produced by {@link VerilogPreParser#ifdef_group_of_lines}. 246 | * @param ctx the parse tree 247 | */ 248 | void exitIfdef_group_of_lines(VerilogPreParser.Ifdef_group_of_linesContext ctx); 249 | /** 250 | * Enter a parse tree produced by {@link VerilogPreParser#ifndef_group_of_lines}. 251 | * @param ctx the parse tree 252 | */ 253 | void enterIfndef_group_of_lines(VerilogPreParser.Ifndef_group_of_linesContext ctx); 254 | /** 255 | * Exit a parse tree produced by {@link VerilogPreParser#ifndef_group_of_lines}. 256 | * @param ctx the parse tree 257 | */ 258 | void exitIfndef_group_of_lines(VerilogPreParser.Ifndef_group_of_linesContext ctx); 259 | /** 260 | * Enter a parse tree produced by {@link VerilogPreParser#elsif_group_of_lines}. 261 | * @param ctx the parse tree 262 | */ 263 | void enterElsif_group_of_lines(VerilogPreParser.Elsif_group_of_linesContext ctx); 264 | /** 265 | * Exit a parse tree produced by {@link VerilogPreParser#elsif_group_of_lines}. 266 | * @param ctx the parse tree 267 | */ 268 | void exitElsif_group_of_lines(VerilogPreParser.Elsif_group_of_linesContext ctx); 269 | /** 270 | * Enter a parse tree produced by {@link VerilogPreParser#else_group_of_lines}. 271 | * @param ctx the parse tree 272 | */ 273 | void enterElse_group_of_lines(VerilogPreParser.Else_group_of_linesContext ctx); 274 | /** 275 | * Exit a parse tree produced by {@link VerilogPreParser#else_group_of_lines}. 276 | * @param ctx the parse tree 277 | */ 278 | void exitElse_group_of_lines(VerilogPreParser.Else_group_of_linesContext ctx); 279 | /** 280 | * Enter a parse tree produced by {@link VerilogPreParser#macro_text}. 281 | * @param ctx the parse tree 282 | */ 283 | void enterMacro_text(VerilogPreParser.Macro_textContext ctx); 284 | /** 285 | * Exit a parse tree produced by {@link VerilogPreParser#macro_text}. 286 | * @param ctx the parse tree 287 | */ 288 | void exitMacro_text(VerilogPreParser.Macro_textContext ctx); 289 | } -------------------------------------------------------------------------------- /test/testrig/verilog/VerilogPreParserVisitor.java: -------------------------------------------------------------------------------- 1 | // Generated from /home/mtdsousa/workspace/antlr4-verilog-python/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 by ANTLR 4.10.1 2 | import org.antlr.v4.runtime.tree.ParseTreeVisitor; 3 | 4 | /** 5 | * This interface defines a complete generic visitor for a parse tree produced 6 | * by {@link VerilogPreParser}. 7 | * 8 | * @param The return type of the visit operation. Use {@link Void} for 9 | * operations with no return type. 10 | */ 11 | public interface VerilogPreParserVisitor extends ParseTreeVisitor { 12 | /** 13 | * Visit a parse tree produced by {@link VerilogPreParser#source_text}. 14 | * @param ctx the parse tree 15 | * @return the visitor result 16 | */ 17 | T visitSource_text(VerilogPreParser.Source_textContext ctx); 18 | /** 19 | * Visit a parse tree produced by {@link VerilogPreParser#compiler_directive}. 20 | * @param ctx the parse tree 21 | * @return the visitor result 22 | */ 23 | T visitCompiler_directive(VerilogPreParser.Compiler_directiveContext ctx); 24 | /** 25 | * Visit a parse tree produced by {@link VerilogPreParser#begin_keywords_directive}. 26 | * @param ctx the parse tree 27 | * @return the visitor result 28 | */ 29 | T visitBegin_keywords_directive(VerilogPreParser.Begin_keywords_directiveContext ctx); 30 | /** 31 | * Visit a parse tree produced by {@link VerilogPreParser#celldefine_directive}. 32 | * @param ctx the parse tree 33 | * @return the visitor result 34 | */ 35 | T visitCelldefine_directive(VerilogPreParser.Celldefine_directiveContext ctx); 36 | /** 37 | * Visit a parse tree produced by {@link VerilogPreParser#default_nettype_directive}. 38 | * @param ctx the parse tree 39 | * @return the visitor result 40 | */ 41 | T visitDefault_nettype_directive(VerilogPreParser.Default_nettype_directiveContext ctx); 42 | /** 43 | * Visit a parse tree produced by {@link VerilogPreParser#endcelldefine_directive}. 44 | * @param ctx the parse tree 45 | * @return the visitor result 46 | */ 47 | T visitEndcelldefine_directive(VerilogPreParser.Endcelldefine_directiveContext ctx); 48 | /** 49 | * Visit a parse tree produced by {@link VerilogPreParser#end_keywords_directive}. 50 | * @param ctx the parse tree 51 | * @return the visitor result 52 | */ 53 | T visitEnd_keywords_directive(VerilogPreParser.End_keywords_directiveContext ctx); 54 | /** 55 | * Visit a parse tree produced by {@link VerilogPreParser#ifdef_directive}. 56 | * @param ctx the parse tree 57 | * @return the visitor result 58 | */ 59 | T visitIfdef_directive(VerilogPreParser.Ifdef_directiveContext ctx); 60 | /** 61 | * Visit a parse tree produced by {@link VerilogPreParser#ifndef_directive}. 62 | * @param ctx the parse tree 63 | * @return the visitor result 64 | */ 65 | T visitIfndef_directive(VerilogPreParser.Ifndef_directiveContext ctx); 66 | /** 67 | * Visit a parse tree produced by {@link VerilogPreParser#include_directive}. 68 | * @param ctx the parse tree 69 | * @return the visitor result 70 | */ 71 | T visitInclude_directive(VerilogPreParser.Include_directiveContext ctx); 72 | /** 73 | * Visit a parse tree produced by {@link VerilogPreParser#line_directive}. 74 | * @param ctx the parse tree 75 | * @return the visitor result 76 | */ 77 | T visitLine_directive(VerilogPreParser.Line_directiveContext ctx); 78 | /** 79 | * Visit a parse tree produced by {@link VerilogPreParser#nounconnected_drive_directive}. 80 | * @param ctx the parse tree 81 | * @return the visitor result 82 | */ 83 | T visitNounconnected_drive_directive(VerilogPreParser.Nounconnected_drive_directiveContext ctx); 84 | /** 85 | * Visit a parse tree produced by {@link VerilogPreParser#pragma_directive}. 86 | * @param ctx the parse tree 87 | * @return the visitor result 88 | */ 89 | T visitPragma_directive(VerilogPreParser.Pragma_directiveContext ctx); 90 | /** 91 | * Visit a parse tree produced by {@link VerilogPreParser#resetall_directive}. 92 | * @param ctx the parse tree 93 | * @return the visitor result 94 | */ 95 | T visitResetall_directive(VerilogPreParser.Resetall_directiveContext ctx); 96 | /** 97 | * Visit a parse tree produced by {@link VerilogPreParser#text_macro_definition}. 98 | * @param ctx the parse tree 99 | * @return the visitor result 100 | */ 101 | T visitText_macro_definition(VerilogPreParser.Text_macro_definitionContext ctx); 102 | /** 103 | * Visit a parse tree produced by {@link VerilogPreParser#text_macro_usage}. 104 | * @param ctx the parse tree 105 | * @return the visitor result 106 | */ 107 | T visitText_macro_usage(VerilogPreParser.Text_macro_usageContext ctx); 108 | /** 109 | * Visit a parse tree produced by {@link VerilogPreParser#timescale_directive}. 110 | * @param ctx the parse tree 111 | * @return the visitor result 112 | */ 113 | T visitTimescale_directive(VerilogPreParser.Timescale_directiveContext ctx); 114 | /** 115 | * Visit a parse tree produced by {@link VerilogPreParser#unconnected_drive_directive}. 116 | * @param ctx the parse tree 117 | * @return the visitor result 118 | */ 119 | T visitUnconnected_drive_directive(VerilogPreParser.Unconnected_drive_directiveContext ctx); 120 | /** 121 | * Visit a parse tree produced by {@link VerilogPreParser#undef_directive}. 122 | * @param ctx the parse tree 123 | * @return the visitor result 124 | */ 125 | T visitUndef_directive(VerilogPreParser.Undef_directiveContext ctx); 126 | /** 127 | * Visit a parse tree produced by {@link VerilogPreParser#elsif_directive}. 128 | * @param ctx the parse tree 129 | * @return the visitor result 130 | */ 131 | T visitElsif_directive(VerilogPreParser.Elsif_directiveContext ctx); 132 | /** 133 | * Visit a parse tree produced by {@link VerilogPreParser#else_directive}. 134 | * @param ctx the parse tree 135 | * @return the visitor result 136 | */ 137 | T visitElse_directive(VerilogPreParser.Else_directiveContext ctx); 138 | /** 139 | * Visit a parse tree produced by {@link VerilogPreParser#endif_directive}. 140 | * @param ctx the parse tree 141 | * @return the visitor result 142 | */ 143 | T visitEndif_directive(VerilogPreParser.Endif_directiveContext ctx); 144 | /** 145 | * Visit a parse tree produced by {@link VerilogPreParser#text_macro_identifier}. 146 | * @param ctx the parse tree 147 | * @return the visitor result 148 | */ 149 | T visitText_macro_identifier(VerilogPreParser.Text_macro_identifierContext ctx); 150 | /** 151 | * Visit a parse tree produced by {@link VerilogPreParser#ifdef_group_of_lines}. 152 | * @param ctx the parse tree 153 | * @return the visitor result 154 | */ 155 | T visitIfdef_group_of_lines(VerilogPreParser.Ifdef_group_of_linesContext ctx); 156 | /** 157 | * Visit a parse tree produced by {@link VerilogPreParser#ifndef_group_of_lines}. 158 | * @param ctx the parse tree 159 | * @return the visitor result 160 | */ 161 | T visitIfndef_group_of_lines(VerilogPreParser.Ifndef_group_of_linesContext ctx); 162 | /** 163 | * Visit a parse tree produced by {@link VerilogPreParser#elsif_group_of_lines}. 164 | * @param ctx the parse tree 165 | * @return the visitor result 166 | */ 167 | T visitElsif_group_of_lines(VerilogPreParser.Elsif_group_of_linesContext ctx); 168 | /** 169 | * Visit a parse tree produced by {@link VerilogPreParser#else_group_of_lines}. 170 | * @param ctx the parse tree 171 | * @return the visitor result 172 | */ 173 | T visitElse_group_of_lines(VerilogPreParser.Else_group_of_linesContext ctx); 174 | /** 175 | * Visit a parse tree produced by {@link VerilogPreParser#macro_text}. 176 | * @param ctx the parse tree 177 | * @return the visitor result 178 | */ 179 | T visitMacro_text(VerilogPreParser.Macro_textContext ctx); 180 | } --------------------------------------------------------------------------------