├── LICENSE ├── README.md ├── constraints └── timing_constraints.xdc ├── images └── hft-fpga-png-output.png ├── src ├── axi_stream_if.v ├── custom_ip_core.v ├── ethernet_layer.v ├── ip_layer.v ├── order_matching_engine.v ├── risk_management.v ├── tcp_ip_stack.v ├── tcp_layer.v └── top_level.v └── testbenches ├── tb_custom_ip_core.v ├── tb_order_matching_engine.v ├── tb_risk_management.v ├── tb_tcp_ip_stack.v └── tb_top_level.v /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/README.md -------------------------------------------------------------------------------- /constraints/timing_constraints.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/constraints/timing_constraints.xdc -------------------------------------------------------------------------------- /images/hft-fpga-png-output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/images/hft-fpga-png-output.png -------------------------------------------------------------------------------- /src/axi_stream_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/axi_stream_if.v -------------------------------------------------------------------------------- /src/custom_ip_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/custom_ip_core.v -------------------------------------------------------------------------------- /src/ethernet_layer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/ethernet_layer.v -------------------------------------------------------------------------------- /src/ip_layer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/ip_layer.v -------------------------------------------------------------------------------- /src/order_matching_engine.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/order_matching_engine.v -------------------------------------------------------------------------------- /src/risk_management.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/risk_management.v -------------------------------------------------------------------------------- /src/tcp_ip_stack.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/tcp_ip_stack.v -------------------------------------------------------------------------------- /src/tcp_layer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/tcp_layer.v -------------------------------------------------------------------------------- /src/top_level.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/src/top_level.v -------------------------------------------------------------------------------- /testbenches/tb_custom_ip_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/testbenches/tb_custom_ip_core.v -------------------------------------------------------------------------------- /testbenches/tb_order_matching_engine.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/testbenches/tb_order_matching_engine.v -------------------------------------------------------------------------------- /testbenches/tb_risk_management.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/testbenches/tb_risk_management.v -------------------------------------------------------------------------------- /testbenches/tb_tcp_ip_stack.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/testbenches/tb_tcp_ip_stack.v -------------------------------------------------------------------------------- /testbenches/tb_top_level.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muditbhargava66/High-Frequency-Trading-FPGA-System/HEAD/testbenches/tb_top_level.v --------------------------------------------------------------------------------