├── README.md ├── [1] PLL System Level (VerilogAMS - Matlab) ├── EE230HW#3_Description.pdf ├── EE230HW#3_PLL_System_(VerilogA&Matlab).pdf ├── Figures │ ├── ClosedLoopTF.bmp │ ├── OpenLoopTF.bmp │ ├── OpenLoop_TB_Blk.png │ ├── OpenLoop_TB_Color.png │ ├── PLL_Locked.bmp │ ├── PLL_TB_Blk.png │ ├── PLL_TB_Color.png │ ├── Ref_Lag.bmp │ ├── Ref_Lead.bmp │ ├── VCO_TB_Blk.png │ ├── VCO_TB_Color.png │ └── VCO_output.bmp ├── Hand Analysis - Type 2 PLL.pdf ├── Matlab │ └── PLL_Closed_and_Open_together.m ├── Simulation References │ ├── VCO_CharacteristicLine.jpg │ └── VerilogAMS_Simulation_in_Cadence(by Ashley).pdf ├── VerilogA Codes │ ├── CP_VerilogA.txt │ ├── Divider_VerilogA.txt │ ├── PFD_VerilogA.txt │ └── VCO_VerilogA.txt └── VerilogA References (for PLLs) │ ├── A Top-Down Verilog-A Design on the Digital Phase-Locked Loop .pdf │ └── VCO_verilogA_ECE546_UIUC.pdf ├── [2] PLL Circuit Design ├── EE230_PLL_project_description_2018.pdf ├── Figures │ ├── CP_Blk.bmp │ ├── CP_Blk2.bmp │ ├── CP_OpAmp_Blk.png │ ├── CP_OpAmp_color.png │ ├── CP_color.bmp │ ├── CP_wth_LF.png │ ├── Corners │ │ ├── Adding corners in ADEXL.png │ │ ├── Corners.bmp │ │ ├── Corners_FF_-40_0.9.bmp │ │ ├── Corners_FF_-40_1.1.png │ │ ├── Corners_FF_125_0.9.bmp │ │ ├── Corners_FF_125_1.1.bmp │ │ ├── Corners_Nom.bmp │ │ ├── Corners_SS_-40_0.9.bmp │ │ ├── Corners_SS_-40_1.1.png │ │ ├── Corners_SS_125_0.9.bmp │ │ ├── Corners_SS_125_1.1.bmp │ │ └── Setup.png │ ├── Divider_Blk.bmp │ ├── Divider_CMOS_Blk.bmp │ ├── Divider_CMOS_color.bmp │ ├── Divider_TSPC_Blk.bmp │ ├── Divider_TSPC_color.bmp │ ├── Jitter │ │ ├── Using Current-Starved Ring │ │ │ ├── Jitter_PkPk_Ring_1K1G.bmp │ │ │ └── Jitter_RMS_Ring_1K1G.bmp │ │ └── Using LC VCO │ │ │ ├── Jitter_PkPk_LCVCO_1K1G.bmp │ │ │ └── Jitter_RMS_LCVCO_1K1G.bmp │ ├── LC VCO curves │ │ ├── VCO_NMOS_0.bmp │ │ ├── VCO_NMOS_1.bmp │ │ └── VCO_NMOS_2.bmp │ ├── LF_Blk.bmp │ ├── PFD_Blk.bmp │ ├── PFD_NAND_Blk.bmp │ ├── PFD_NAND_color.bmp │ ├── PFD_NOR_Blk.bmp │ ├── PFD_NOR_color.bmp │ ├── PFD_color.bmp │ ├── PLL Locking │ │ ├── Using Current-Starved Ring │ │ │ └── PLL_Lock.bmp │ │ └── Using LC VCO │ │ │ ├── PLL_Locked_vcontrol_0.7.bmp │ │ │ └── PLL_Locked_vcontrol_0.bmp │ ├── PLL_WholeSystem_Blk.bmp │ ├── PLL_WholeSystem_color.bmp │ ├── VCO_Blk.bmp │ ├── VCO_Blk2.bmp │ ├── VCO_Ring_Blk.bmp │ ├── VCO_Ring_color.bmp │ └── VCO_color.bmp ├── References │ ├── Jitter measurement using SpectreRF Application Note.pdf │ ├── PLL_Jitter_measurment_in_Spectre.pdf │ ├── Ratan_MS_THESIS_UIUC_2014.pdf │ ├── VLSI2014_PLL_v7.pdf │ └── spectre_rfmanual.pdf ├── Sam Palermo Lec Notes │ ├── Sam Palermo Lectures.txt │ ├── lecture07_SamPalermo_pfd.pdf │ ├── lecture08_SamPalermo_cp.pdf │ ├── lecture09_loop_filters.pdf │ ├── lecture10_SamPalermo_vcos.pdf │ └── lecture12_SamPalermo_dividers.pdf ├── Simulation Files │ ├── EE230Group8.tbz2 │ ├── EE230_PLL.zip │ ├── Setup_PLL.png │ ├── Setup_PLL_DesignVariables.png │ └── Setup_VCO_NMOS.png └── Simulation Notes │ ├── Convergence Problem.pptx │ ├── How to Display important DC parameters │ ├── Annotation 0.png │ ├── Annotation 1.png │ ├── Annotation 2.png │ └── Annotation 3.png │ └── Steps for finding the Jitter for the PLL project.pptx ├── [PPT] EE230_PLL_Project.pdf └── [Report] EE230_PLL_Project.pdf /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system/HEAD/README.md -------------------------------------------------------------------------------- /[1] PLL System Level (VerilogAMS - Matlab)/EE230HW#3_Description.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system/HEAD/[1] PLL System Level (VerilogAMS - Matlab)/EE230HW#3_Description.pdf -------------------------------------------------------------------------------- /[1] PLL System Level (VerilogAMS - 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