├── - References ├── Application Notes │ ├── MT-021 ADC Architectures II_ Successive Approximation ADCs.pdf │ ├── The operation of the SAR-ADC based on charge distribution.pdf │ ├── Understanding the Successive Approximation Register ADC - Technical Articles.pdf │ └── links.txt ├── Lecture Notes │ ├── (Lec) Systematic Design for a Successive Aproximation ADC.pdf │ ├── SJSU_EE288_lecture18_SAR_ADC.pdf │ └── SJSU_EE288_project_description_May_11.pdf ├── Papers │ ├── - Ref4_2011_JSSC_Harpe_A 26 ++W 8 bit 10 Msps asynchronous SAR ADC for low energy radios.pdf │ ├── 2008_ISSCC_Nauta_Comparator_paper_V12_04nn.pdf │ ├── 2010_JSSC_Liu__A 10-bit 50-MSs SAR ADC With a Monotonic Capacitor Switching.pdf │ ├── 2011_JSSC_Harpe_A 26 ++W 8 bit 10 Msps asynchronous SAR ADC for low energy radios.pdf │ ├── 2015_JSSC_Liu_10bit 320MSps SAR for 80211ac in 20 nm CMOS(1).pdf │ └── 2015_JSSC_Liu_10bit 320MSps SAR for 80211ac in 20 nm CMOS.pdf └── Theses │ ├── MS_Thesis_Asynchronous_SAR_UTAustin_KARDONIK-MASTERSREPORT-2013.pdf │ └── MS_Thesis_SAR_Pipeine_Texas_Austin_gandara_report_20129.pdf ├── Block Diagrams.pptx ├── Circuit_Schematics ├── 0_WholeSystem_mono.png ├── 1_0_ClkGenerator_mono.png ├── 1_1_DelayCell_mono.png ├── 1_2_NAND_mono.png ├── 1_3_INV_mono.png ├── 1_4_MUX_mono.png ├── 2_0_Comparator_mono.png ├── 2_1_StrongArmLatch_mono.png ├── 2_2_RSLatch_mono.png ├── 2_3_XOR_mono.png ├── 3_0_DAC_mono.png ├── 3_1_SwitchNW_mono.png ├── 3_2_TGswitch_mono.png ├── 3_3_BootstrappedSwitch_mono.png ├── 4_0_SARlogic_mono.png ├── 4_1_TSPC_mono.png ├── 5_0_OutputRegister_mono.png ├── 5_1_CMOS_FF_mono.png └── 6_0_IdealDAC_mono.png ├── Circuits_Testbenches ├── 1_VerilogA_Models │ ├── 0_VerilogA_Synchronous_SAR.pdf │ ├── 1_VerilogA_Asynchronous_SAR.pdf │ ├── Asynchronous_SAR │ │ ├── ASync_SAR_clkgen.png │ │ ├── ASync_SAR_clkgen_blk.png │ │ ├── ASync_SAR_clkgen_mono.png │ │ ├── ASync_SAR_logic.png │ │ ├── ASync_SAR_logic_blk.png │ │ ├── ASync_SAR_logic_mono.png │ │ ├── ASync_SAR_system.png │ │ ├── ASync_SAR_system_blk.png │ │ ├── ASync_SAR_system_mono.png │ │ ├── simulation0.bmp │ │ ├── simulation1.bmp │ │ └── simulation2.bmp │ └── Synchronous_SAR │ │ ├── Sync_SAR_logic.png │ │ ├── Sync_SAR_logic_blk.png │ │ ├── Sync_SAR_logic_mono.png │ │ ├── Sync_SAR_system.png │ │ ├── Sync_SAR_system_blk.png │ │ ├── Sync_SAR_system_mono.png │ │ ├── simulation0.bmp │ │ ├── simulation1.bmp │ │ └── simulation2.bmp ├── 2_Comparator │ ├── (Final) Comparator - StrongArm │ │ ├── Comp_Overdrive_10mdiff.bmp │ │ ├── Comp_Overdrive_300udiff.bmp │ │ ├── StrongArm Comparator │ │ │ ├── MWSCAS2018_A High Speed Dynamic StrongARM Latch Comparator.pdf │ │ │ ├── Razavi_StrongArm Latch.pdf │ │ │ └── lecture13_ee689_rx_circuits.pdf │ │ ├── TB.png │ │ ├── comp_params.png │ │ ├── trans.bmp │ │ └── trans_zoomed.bmp │ ├── 1_PreAmp │ │ └── Preamp_tb.png │ ├── 2_CompWithDAC │ │ ├── CompWithDAC_0p7mVinDiff.png │ │ ├── CompWithDAC_15mVinDiff.png │ │ ├── CompWithDAC_1mVinDiff.png │ │ └── CompWithDAC_TB.png │ ├── SAR_Comparator_2stage.pdf │ ├── blocks_and_simulations │ │ ├── Latch.png │ │ ├── Preamp.png │ │ ├── Preamp_ac.bmp │ │ ├── Preamp_dc.png │ │ ├── RS_Latch.png │ │ ├── Vin_100mV.bmp │ │ ├── Vin_10mV.bmp │ │ ├── Vin_1mV.bmp │ │ ├── WholeComparator.png │ │ ├── testbench.png │ │ └── xor.png │ └── modifications │ │ ├── Latch.png │ │ ├── Preamp.png │ │ └── Vin_1mV.bmp ├── 3_SAR_Logic │ ├── SAR_DigitalLogic.pdf │ ├── comp_0.bmp │ ├── comp_1.bmp │ ├── dff.png │ ├── logic.png │ └── tb_logic.png ├── 4_Capacitive_DAC │ ├── DAC (Final) │ │ ├── DAC_2fF.bmp │ │ ├── DAC_6fF.bmp │ │ ├── TB.png │ │ └── trans.bmp │ ├── DAC_SW_Network.png │ ├── DAC_Schematics.png │ ├── DAC_TB.png │ └── SAR_CapacitiveDAC.pdf └── 5_Bootstrapped_Switch │ ├── BootstrapedSW (Final) │ ├── TB.png │ ├── trans.bmp │ └── trans_zoomed.bmp │ ├── Bootstraped_Circuit.png │ ├── Bootstraped_Circuit_b.png │ ├── For_Spectrum_Measurement.jpg │ ├── Results.png │ ├── Results_Spectrum.bmp │ ├── Results_Transient(zoomedin).bmp │ ├── Results_Transient.bmp │ ├── SAR_BootstrappedSW.pdf │ ├── Testbench.png │ ├── Testbench_.png │ └── Testbench_b.png ├── FinalSystem_Results ├── 0_WholeSystem_mono.png ├── Results.png ├── Spectrum.bmp ├── Transient.bmp ├── Transient_1cycle.bmp ├── Transient_1inputperiod.bmp ├── Transient_2cycles.bmp ├── parameters_and_powers.png └── spectrum_analysis.jpg ├── README.md ├── SAR_Project_2020_09_27.tbz2 ├── VerilogA_files ├── Ideal_Asynchronous │ ├── ClockedComparator.va │ ├── DAC_8bit.va │ ├── D_flipflop.va │ ├── Gate_1ns_delaycell.va │ ├── Gate_2to1Mux.va │ ├── Gate_INV.va │ ├── Gate_XOR.va │ ├── Ideal_SAR_logic.png │ ├── Register_8bit.va │ ├── SampleAndHold.va │ └── clk_generator.png ├── Ideal_Synchronous │ ├── ClockedComparator.va │ ├── DAC_8bit.va │ ├── Register_8bit.va │ ├── SAR_logic.va │ └── SampleAndHold.va └── Schematics_And_Resuts │ ├── SAR_asynchronous.png │ ├── SAR_asynchronous_trans.bmp │ ├── SAR_asynchronous_trans_zoomed.bmp │ ├── SAR_asynchronous_trans_zoomed1.bmp │ ├── SAR_synchronous.png │ ├── SAR_synchronous_trans.bmp │ ├── SAR_synchronous_trans_zoomed.bmp │ └── SAR_synchronous_trans_zoomed1.bmp ├── [PPT] Design of a Low-Power Asynchronous SAR ADC in 45 nm CMOS Technology.pdf ├── [Poster] Design of a Low-Power Asynchronous SAR ADC in 45 nm CMOS Technology.pdf └── [Report] Design of a Low-Power Asynchronous SAR ADC in 45 nm CMOS Technology.pdf /- References/Application Notes/MT-021 ADC Architectures II_ Successive Approximation ADCs.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC/HEAD/- References/Application Notes/MT-021 ADC Architectures II_ Successive Approximation ADCs.pdf -------------------------------------------------------------------------------- /- References/Application Notes/The operation of the SAR-ADC based on charge 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