├── axi_tb_files ├── readme ├── top │ ├── readme.txt │ └── axi4_top.sv ├── test │ ├── readme.txt │ └── axi_test.sv ├── axi_slave │ ├── readme.txt │ ├── axi_slave_sequencer.sv │ ├── axi_slave_driver.sv │ ├── axi_slave_base_seq.sv │ ├── axi_slave_agent.sv │ ├── axi_slave_trans.sv │ └── axi_slave_monitor.sv ├── env │ ├── readme.txt │ ├── axi_env_config.sv │ ├── axi_virtual_seqr.sv │ ├── axi_package.sv │ ├── axi_env.sv │ ├── axi_virt_seq.sv │ └── master_coverage.sv ├── axi_master │ ├── readme.txt │ ├── axi_master_agent_config.sv │ ├── axi_master_sequencer.sv │ ├── axi_master_agent.sv │ ├── axi_master_trans.sv │ ├── axi_base_sequence.sv │ ├── axi_master_monitor.sv │ └── axi_master_driver.sv ├── sim │ └── Makefile ├── AXI4_OOO_Scoreboard.sv ├── AXI4_Scoreboard.sv └── src │ └── axi_interface.sv ├── doc ├── readme.txt ├── AXItestplan.xls ├── axi4_assertion.xlsx ├── axi_transaction.docx ├── AXI_Interface_testplan.xlsx └── AXI_Verification_DOC_draft.docx ├── README.md ├── CONTRIBUTING.md ├── axi_env_config.sv ├── axi_virtual_seqr.sv ├── axi_env.sv ├── CODE_OF_CONDUCT.md ├── axi_virt_seq.sv ├── axi_test.sv ├── LICENSE └── assertions └── axi_assertion.sv /axi_tb_files/readme: -------------------------------------------------------------------------------- 1 | testbench directory created 2 | -------------------------------------------------------------------------------- /doc/readme.txt: -------------------------------------------------------------------------------- 1 | All the documents to be updated 2 | -------------------------------------------------------------------------------- /axi_tb_files/top/readme.txt: -------------------------------------------------------------------------------- 1 | This directory has the top level files 2 | -------------------------------------------------------------------------------- /axi_tb_files/test/readme.txt: -------------------------------------------------------------------------------- 1 | This directory has all the tests for the axi 4 2 | -------------------------------------------------------------------------------- /axi_tb_files/axi_slave/readme.txt: -------------------------------------------------------------------------------- 1 | This directory consists of all the files for slave 2 | -------------------------------------------------------------------------------- /axi_tb_files/env/readme.txt: -------------------------------------------------------------------------------- 1 | this is the environment directory 2 | env and config class 3 | -------------------------------------------------------------------------------- /axi_tb_files/axi_master/readme.txt: -------------------------------------------------------------------------------- 1 | This directory consists of all the files with respect to master 2 | -------------------------------------------------------------------------------- /doc/AXItestplan.xls: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muneebullashariff/axi4_vip/HEAD/doc/AXItestplan.xls -------------------------------------------------------------------------------- /doc/axi4_assertion.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muneebullashariff/axi4_vip/HEAD/doc/axi4_assertion.xlsx -------------------------------------------------------------------------------- /doc/axi_transaction.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muneebullashariff/axi4_vip/HEAD/doc/axi_transaction.docx -------------------------------------------------------------------------------- /doc/AXI_Interface_testplan.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muneebullashariff/axi4_vip/HEAD/doc/AXI_Interface_testplan.xlsx -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # axi4_vip 2 | Verification IP for AXI protocol 3 | Issue created to track ststus 4 | Creating a testbench directory 5 | -------------------------------------------------------------------------------- /doc/AXI_Verification_DOC_draft.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/muneebullashariff/axi4_vip/HEAD/doc/AXI_Verification_DOC_draft.docx -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | First off, thanks for taking the time to contribute! 2 | 3 | Please follow the below guidelines for contributing to the project: 4 | 5 | Coding Guidelines: 6 | https://github.com/muneebullashariff/Best-Coding-Practices-/blob/master/coding_guidelines.sv 7 | 8 | Coding Template: 9 | https://github.com/muneebullashariff/Best-Coding-Practices-/blob/master/coding_template.sv 10 | 11 | Basic .vimrc file and required .vim/folders: 12 | https://github.com/muneebullashariff/Best-Coding-Practices-/tree/master/vim_root_folder 13 | 14 | Git and Github guidelines: 15 | https://github.com/muneebullashariff/Best-Coding-Practices-/blob/master/git_github_guidelines.sv 16 | -------------------------------------------------------------------------------- /axi_tb_files/sim/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for uvm test bench of AXI VIP 2 | 3 | INC = +incdir+../axi_master +incdir+../axi_slave +incdir+../env +incdir+../test +incdir+../top 4 | TOP = ../top/axi4_top.sv 5 | PKG = ../env/axi_package.sv 6 | TEST= ../test/axi_test.sv 7 | #COVOP= -dbg -coverage sba 8 | 9 | work = work 10 | VSIMOPT= +access +r -sva 11 | VSIMBATCH = -acdb_file mem_cov.acdb 12 | VSIMBATCH1 = -c -acdb_file mem_cov2.acdb -do "log -rec *;run -all;exit" 13 | lib: 14 | vlib $(work) 15 | vmap work $(work) 16 | 17 | sv_cmp:clean lib comp0 18 | 19 | 20 | gui: 21 | vsim& 22 | 23 | comp0: 24 | vcs -uvm $(INC) $(PKG) $(TOP) 25 | 26 | run_test: 27 | vcs -V -R $(INC) $(PKG) $(TOP) -full64 -ntb_opts uvm-1.2 -sverilog +v2k -debug_access+all -debug_pp +ntb_random_seed_automatic -override_timescale=1ps/1ps 28 | 29 | #----------E.O.F---------- 30 | -------------------------------------------------------------------------------- /axi_env_config.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //Environment Config Class 23 | class axi_env_config extends uvm_object; 24 | 25 | `uvm_object_utils (axi_env_config) 26 | 27 | int has_ooo_scoreboard = 1; 28 | int has_scoreboard = 1; 29 | 30 | function new(string name = "axi_env_config"); 31 | super.new(name); 32 | endfunction 33 | 34 | endclass -------------------------------------------------------------------------------- /axi_tb_files/env/axi_env_config.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //Environment Config Class 23 | class axi_env_config extends uvm_object; 24 | 25 | `uvm_object_utils (axi_env_config) 26 | 27 | int has_ooo_scoreboard = 1; 28 | int has_scoreboard = 1; 29 | 30 | function new(string name = "axi_env_config"); 31 | super.new(name); 32 | endfunction 33 | 34 | endclass -------------------------------------------------------------------------------- /axi_virtual_seqr.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | class axi_virtual_seqr extends uvm_sequencer #(axi_seq_item); 23 | 24 | axi_master_sequencer mstr_vseqr_h; 25 | axi_slave_sequencer slv_vseqr_h; 26 | 27 | //Fatory Registration 28 | `uvm_component_utils(axi_virtual_seqr) 29 | 30 | //Constructor 31 | function new(string name = "axi_env", uvm_component parent); 32 | super.new(name, parent); 33 | endfunction 34 | 35 | function void build_phase (uvm_phase phase); 36 | super.build_phase(phase); 37 | endfunction 38 | 39 | endclass -------------------------------------------------------------------------------- /axi_tb_files/env/axi_virtual_seqr.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | class axi_virtual_seqr extends uvm_sequencer #(axi_seq_item); 23 | 24 | axi_master_sequencer mstr_vseqr_h; 25 | axi_slave_sequencer slv_vseqr_h; 26 | 27 | //Fatory Registration 28 | `uvm_component_utils(axi_virtual_seqr) 29 | 30 | //Constructor 31 | function new(string name = "axi_env", uvm_component parent); 32 | super.new(name, parent); 33 | endfunction 34 | 35 | function void build_phase (uvm_phase phase); 36 | super.build_phase(phase); 37 | endfunction 38 | 39 | endclass -------------------------------------------------------------------------------- /axi_tb_files/top/axi4_top.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI4_TOP_SV 23 | `define AXI4_TOP_SV 24 | 25 | //----------------------------------------------------------------------------- 26 | //Module : axi4_top 27 | //Description : 28 | //Top module to generate the clock frequency and invoking the test cases. 29 | //----------------------------------------------------------------------------- 30 | 31 | module top; 32 | 33 | //Import Packages 34 | import uvm_pkg::*; 35 | import axi_pkg::*; 36 | 37 | bit clock; 38 | 39 | axi_if i_f(clock); 40 | 41 | //Clock Generation 42 | always 43 | #20 clock = ~clock; 44 | 45 | //Invoking Test cases 46 | initial begin 47 | uvm_config_db #(virtual axi_if)::set(null,"*","vif",i_f); 48 | run_test("base_test"); 49 | end 50 | 51 | endmodule 52 | 53 | `endif 54 | 55 | //----E.O.F------ 56 | -------------------------------------------------------------------------------- /axi_tb_files/axi_slave/axi_slave_sequencer.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //----------------------------------------------------------------------------- 23 | // Class : AXI Slave sequencer 24 | // Description of the class : Axi slave sequencer 25 | // FILE NAME: axi_slave_sequencer.sv 26 | //----------------------------------------------------------------------------- 27 | 28 | `ifndef AXI_SLAVE_SEQUENCER_SV 29 | `define AXI_SLAVE_SEQUENCER_SV 30 | 31 | class AXI_slave_sequencer extends uvm_sequencer #(AXI_transfer); 32 | 33 | `uvm_component_utils_begin(AXI_slave_sequencer) 34 | `uvm_component_utils_end 35 | 36 | // Constructor - required syntax for UVM automation and utilities 37 | function new (string name, uvm_component parent); 38 | super.new(name, parent); 39 | endfunction : new 40 | 41 | virtual function void build_phase(uvm_phase phase); 42 | super.build_phase(phase); 43 | endfunction : build_phase 44 | 45 | endclass : AXI_slave_sequencer 46 | 47 | `endif // AXI_slave_sequencer 48 | -------------------------------------------------------------------------------- /axi_tb_files/env/axi_package.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI_PACKAGE_SV 23 | `define AXI_PACKAGE_SV 24 | 25 | 26 | package axi_pkg; 27 | 28 | import uvm_pkg::*; 29 | 30 | `include "uvm_macros.svh" 31 | 32 | //----------Including MASTER files---------- 33 | `include "axi_base_sequence.sv" 34 | `include "axi_master_agent.sv" 35 | `include "axi_master_agent_config.sv" 36 | `include "axi_master_driver.sv" 37 | `include "axi_master_monitor.sv" 38 | `include "axi_master_sequencer.sv" 39 | `include "axi_master_trans.sv" 40 | 41 | //----------Including SLAVE files---------- 42 | `include "axi_slave_agent.sv" 43 | `include "axi_slave_base_seq.sv" 44 | `include "axi_slave_driver.sv" 45 | `include "axi_slave_monitor.sv" 46 | `include "axi_slave_sequencer.sv" 47 | `include "axi_slave_trans.sv" 48 | 49 | //----------Including ENV files---------- 50 | `include "axi_env.sv" 51 | `include "axi_env_config.sv" 52 | `include "axi_virt_seq.sv" 53 | `include "axi_virtual_seqr.sv" 54 | 55 | //----------Including INTERFACE files---------- 56 | `include "axi_interface.sv" 57 | 58 | //----------Including TEST files---------- 59 | `include "axi_test.sv" 60 | `include "AXI4_OOO_Scoreboard.sv" 61 | `include "AXI4_Scoreboard.sv" 62 | 63 | //----------Including ASSERTION files---------- 64 | `include "axi_assertion.sv" 65 | 66 | endpackage 67 | 68 | `endif 69 | 70 | //-------E.O.F------- 71 | -------------------------------------------------------------------------------- /axi_env.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //Base test 23 | class axi_env extends uvm_env; 24 | 25 | //Factory registration 26 | `uvm_component_utils (axi_env) 27 | 28 | axi_master_agent master_agent; 29 | axi_slave_agent slave_agent; 30 | axi_scoreboard scoreboard; 31 | AXI_OOO_scoreboard ooo_scoreboard; 32 | axi_tb_config tb_cfg; 33 | axi_virtual_seqr v_seqr; 34 | 35 | //Constructor 36 | function new(string name = "axi_env", uvm_component parent); 37 | super.new(name, parent); 38 | endfunction 39 | 40 | 41 | //Building components 42 | function void build_phase (uvm_phase phase); 43 | 44 | master_agent = axi_master_agent::typeid::create("master_agent", this); 45 | slave_agent = axi_slave_agent::typeid::create("slave_agent", this); 46 | 47 | if(!uvm_config_db #(axi_tb_config)::get(this, "", "axi_tb_config", tb_cfg)) 48 | `uvm_fatal("CONFIG DB", "Cannot access Testbench Config DB"); 49 | 50 | if(env_cfg.has_ooo_scoreboard) 51 | ooo_scoreboard = AXI_OOO_scoreboard::typeid::create("ooo_scoreboard", this); 52 | if(env_cfg.has_scoreboard) 53 | scoreboard = axi_scoreboard::typeid::create("scoreboard", this); 54 | 55 | super.build_phase(phase); 56 | endfunction 57 | 58 | //Connecting components 59 | function void connect_phase (uvm_phase phase); 60 | 61 | v_seqr.mstr_vseqr_h = master_agent.m_sequencer; 62 | v_seqr.slv_vseqr_h = slave_agent.s_sequencer; 63 | 64 | endfunction 65 | endclass 66 | 67 | -------------------------------------------------------------------------------- /axi_tb_files/env/axi_env.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //Base test 23 | class axi_env extends uvm_env; 24 | 25 | //Factory registration 26 | `uvm_component_utils (axi_env) 27 | 28 | axi_master_agent master_agent; 29 | axi_slave_agent slave_agent; 30 | axi_scoreboard scoreboard; 31 | AXI_OOO_scoreboard ooo_scoreboard; 32 | axi_tb_config tb_cfg; 33 | axi_virtual_seqr v_seqr; 34 | 35 | //Constructor 36 | function new(string name = "axi_env", uvm_component parent); 37 | super.new(name, parent); 38 | endfunction 39 | 40 | 41 | //Building components 42 | function void build_phase (uvm_phase phase); 43 | 44 | master_agent = axi_master_agent::typeid::create("master_agent", this); 45 | slave_agent = axi_slave_agent::typeid::create("slave_agent", this); 46 | 47 | if(!uvm_config_db #(axi_tb_config)::get(this, "", "axi_tb_config", tb_cfg)) 48 | `uvm_fatal("CONFIG DB", "Cannot access Testbench Config DB"); 49 | 50 | if(env_cfg.has_ooo_scoreboard) 51 | ooo_scoreboard = AXI_OOO_scoreboard::typeid::create("ooo_scoreboard", this); 52 | if(env_cfg.has_scoreboard) 53 | scoreboard = axi_scoreboard::typeid::create("scoreboard", this); 54 | 55 | super.build_phase(phase); 56 | endfunction 57 | 58 | //Connecting components 59 | function void connect_phase (uvm_phase phase); 60 | 61 | v_seqr.mstr_vseqr_h = master_agent.m_sequencer; 62 | v_seqr.slv_vseqr_h = slave_agent.s_sequencer; 63 | 64 | endfunction 65 | endclass 66 | 67 | -------------------------------------------------------------------------------- /axi_tb_files/axi_master/axi_master_agent_config.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI_MASTER_AGENT_CONFIG_INCLUDED 23 | `define AXI_MASTER_AGENT_CONFIG_INCLUDED 24 | 25 | //----------------------------------------------------------------------------- 26 | // Class: master_agent_config 27 | // Description of the class 28 | // configures the agent as active or passive 29 | //------------------------------------------------------------------------------ 30 | 31 | class axi_master_agent_config extends uvm_object; 32 | 33 | //factory registration 34 | `uvm_object_utils(axi_master_agent_config) 35 | 36 | //declaring agent is active or passive 37 | uvm_active_passive_enum is_active=UVM_ACTIVE; 38 | 39 | //declare handles for virtual interface 40 | virtual axi_if vif; 41 | 42 | //--------------------------------------------- 43 | // Externally defined tasks and functions 44 | //--------------------------------------------- 45 | extern function new(string name = "axi_master_agent_config"); 46 | 47 | endclass: axi_master_agent_config 48 | 49 | //----------------------------------------------------------------------------- 50 | // Constructor: new 51 | // Initializes the master_agent_config class component 52 | // 53 | // Parameters: 54 | // name - instance name of the config 55 | //----------------------------------------------------------------------------- 56 | 57 | function axi_master_agent_config::new(string name="axi_master_agent_config"); 58 | super.new(name); 59 | endfunction:new 60 | 61 | //----------------------------------------------------------------------------- 62 | `endif 63 | 64 | -------------------------------------------------------------------------------- /axi_tb_files/axi_slave/axi_slave_driver.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //----------------------------------------------------------------------------- 23 | // Class : AXI Slave Driver 24 | // Description of the class : Axi slave driver class to drive to master 25 | // FILE NAME: axi_slave_driver.sv 26 | //----------------------------------------------------------------------------- 27 | 28 | `ifndef AXI_SLAVE_DRIVER_SV 29 | `define AXI_SLAVE_DRIVER_SV 30 | 31 | class AXI_slave_driver extends uvm_driver #(AXI_transfer); 32 | 33 | virtual interface AXI_vif ms_vif; 34 | 35 | 36 | // component macro 37 | `uvm_component_utils(AXI_slave_driver) 38 | 39 | // Constructor - required syntax for UVM automation and utilities 40 | function new (string name, uvm_component parent); 41 | super.new(name, parent); 42 | endfunction : new 43 | 44 | function void build_phase(uvm_phase phase); 45 | if (!axi_vif_config::get(this,"","ms_vif", ms_vif)) 46 | `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".ms_vif"}) 47 | endfunction: build_phase 48 | 49 | // start_of_simulation 50 | function void start_of_simulation_phase(uvm_phase phase); 51 | `uvm_info(get_type_name(), {"start of simulation for ", get_full_name()}, UVM_HIGH) 52 | endfunction : start_of_simulation_phase 53 | 54 | // UVM run_phase 55 | task run_phase(uvm_phase phase); 56 | get_and_drive(); 57 | endtask : run_phase 58 | 59 | 60 | 61 | // Gets packets from the sequencer and passes them to the driver. 62 | task get_and_drive(); 63 | ms_vif.AXI_AWREADY <= 1'b1; 64 | ms_vif.AXI_WREADY <= 1'b1; 65 | ms_vif.AXI_BRESP <= OKAY; 66 | ms_vif.AXI_BVALID <= 1; 67 | ms_vif.AXI_BID <= 1; 68 | endtask : get_and_drive 69 | 70 | endclass 71 | `endif 72 | -------------------------------------------------------------------------------- /axi_tb_files/axi_slave/axi_slave_base_seq.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //----------------------------------------------------------------------------- 23 | // Class : AXI Slave base sequence 24 | // Description of the class : sequence for slave basic read 25 | // FILE NAME: axi_slave_base_seq.sv 26 | //----------------------------------------------------------------------------- 27 | 28 | `ifndef AXI_SLAVE_BASE_SEQ_SV 29 | `define AXI_SLAVE_BASE_SEQ_SV 30 | 31 | class axi_slave_base_seq extends uvm_sequence#(AXI_transfer); 32 | 33 | // Required macro for sequences automation 34 | `uvm_object_utils(axi_slave_base_seq) 35 | 36 | // Constructor 37 | function new(string name="axi_slave_base_seq"); 38 | super.new(name); 39 | endfunction 40 | 41 | task pre_body(); 42 | starting_phase.raise_objection(this, get_type_name()); 43 | `uvm_info(get_type_name(), "raise objection", UVM_MEDIUM) 44 | endtask : pre_body 45 | 46 | task post_body(); 47 | starting_phase.drop_objection(this, get_type_name()); 48 | `uvm_info(get_type_name(), "drop objection", UVM_MEDIUM) 49 | endtask : post_body 50 | 51 | endclass : axi_slave_base_seq 52 | 53 | 54 | class axi_basic_rd_seq extends axi_slave_base_seq; 55 | 56 | // Required macro for sequences automation 57 | `uvm_object_utils(axi_basic_rd_seq) 58 | 59 | // Constructor 60 | function new(string name="axi_basic_rd_seq"); 61 | super.new(name); 62 | endfunction 63 | 64 | // Sequence body definition 65 | virtual task body(); 66 | `uvm_info(get_type_name(), "Executing axi_basic_rd_seq", UVM_LOW) 67 | repeat(20) 68 | `uvm_do_with(req,{req.addr == 500;req.itype == 0; req.rw == 0;}) 69 | endtask 70 | 71 | endclass : axi_basic_rd_seq 72 | `endif 73 | 74 | 75 | -------------------------------------------------------------------------------- /axi_tb_files/axi_slave/axi_slave_agent.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //----------------------------------------------------------------------------- 23 | // Class : AXI Slave Agent 24 | // Description of the class : Active/Passive AXI Slave Agent 25 | // FILE NAME: axi_slave_agent.sv 26 | //----------------------------------------------------------------------------- 27 | `ifndef AXI_SLAVE_AGENT_SV 28 | `define AXI_SLAVE_AGENT_SV 29 | 30 | class AXI_slave_agent extends uvm_agent; 31 | 32 | // This field determines whether an agent is active or passive. 33 | protected uvm_active_passive_enum is_active = UVM_ACTIVE; 34 | 35 | AXI_slave_driver s_driver; 36 | AXI_slave_sequencer s_sequencer; 37 | AXI_slave_monitor s_monitor; 38 | 39 | // reserve fields 40 | `uvm_component_utils_begin(AXI_slave_agent) 41 | `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_ALL_ON) 42 | `uvm_component_utils_end 43 | 44 | 45 | // constructor 46 | function new(string name, uvm_component parent); 47 | super.new(name, parent); 48 | endfunction : new 49 | 50 | 51 | // build phase 52 | virtual function void build_phase(uvm_phase phase); 53 | super.build_phase(phase); 54 | 55 | s_monitor = AXI_slave_monitor::type_id::create("s_monitor", this); 56 | 57 | if (is_active == UVM_ACTIVE) begin 58 | s_driver = AXI_slave_driver::type_id::create("s_driver", this); 59 | s_sequencer = AXI_slave_sequencer::type_id::create("s_sequencer", this); 60 | end 61 | 62 | endfunction : build_phase 63 | 64 | 65 | // connect phase 66 | virtual function void connect_phase(uvm_phase phase); 67 | if (is_active == UVM_ACTIVE) begin 68 | s_driver.seq_item_port.connect(s_sequencer.seq_item_export); 69 | end 70 | endfunction : connect_phase 71 | 72 | endclass : AXI_slave_agent 73 | 74 | 75 | `endif // AXI_slave_agent 76 | 77 | -------------------------------------------------------------------------------- /axi_tb_files/axi_master/axi_master_sequencer.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI_MASTER_SEQUENCER_SV 23 | `define AXI_MASTER_SEQUENCER_SV 24 | 25 | //----------------------------------------------------------------------------- 26 | // Class : AXI Master sequencer 27 | // Description of the class : routes the seq_item to driver 28 | //----------------------------------------------------------------------------- 29 | 30 | class axi_master_sequencer extends uvm_sequencer#(axi_master_trans); 31 | 32 | //Factory registration 33 | `uvm_component_utils(axi_master_sequencer) 34 | 35 | //--------------------------------------------- 36 | // Externally defined tasks and functions 37 | //--------------------------------------------- 38 | extern function new(string name="axi_master_sequencer", uvm_component parent); 39 | extern function void build_phase(uvm_phase phase); 40 | 41 | endclass : axi_master_sequencer 42 | 43 | //----------------------------------------------------------------------------- 44 | // Constructor: new 45 | // Initializes the master_sequencer class component 46 | // 47 | // Parameters: 48 | // name - instance name of the config_template 49 | // parent - parent under which this component is created 50 | //----------------------------------------------------------------------------- 51 | 52 | function axi_master_sequencer::new (string name="axi_master_sequencer", uvm_component parent); 53 | super.new(name, parent); 54 | endfunction : new 55 | 56 | //----------------------------------------------------------------------------- 57 | // Function: build_phase 58 | // Creates the required components 59 | // 60 | // Parameters: 61 | // phase - stores the current phase 62 | //----------------------------------------------------------------------------- 63 | 64 | function void axi_master_sequencer::build_phase(uvm_phase phase); 65 | super.build_phase(phase); 66 | endfunction : build_phase 67 | 68 | //////////////////////////////////////////////////////////////// 69 | `endif 70 | 71 | -------------------------------------------------------------------------------- /CODE_OF_CONDUCT.md: -------------------------------------------------------------------------------- 1 | # Contributor Covenant Code of Conduct 2 | 3 | ## Our Pledge 4 | 5 | In the interest of fostering an open and welcoming environment, we as 6 | contributors and maintainers pledge to making participation in our project and 7 | our community a harassment-free experience for everyone, regardless of age, body 8 | size, disability, ethnicity, sex characteristics, gender identity and expression, 9 | level of experience, education, socio-economic status, nationality, personal 10 | appearance, race, religion, or sexual identity and orientation. 11 | 12 | ## Our Standards 13 | 14 | Examples of behavior that contributes to creating a positive environment 15 | include: 16 | 17 | * Using welcoming and inclusive language 18 | * Being respectful of differing viewpoints and experiences 19 | * Gracefully accepting constructive criticism 20 | * Focusing on what is best for the community 21 | * Showing empathy towards other community members 22 | 23 | Examples of unacceptable behavior by participants include: 24 | 25 | * The use of sexualized language or imagery and unwelcome sexual attention or 26 | advances 27 | * Trolling, insulting/derogatory comments, and personal or political attacks 28 | * Public or private harassment 29 | * Publishing others' private information, such as a physical or electronic 30 | address, without explicit permission 31 | * Other conduct which could reasonably be considered inappropriate in a 32 | professional setting 33 | 34 | ## Our Responsibilities 35 | 36 | Project maintainers are responsible for clarifying the standards of acceptable 37 | behavior and are expected to take appropriate and fair corrective action in 38 | response to any instances of unacceptable behavior. 39 | 40 | Project maintainers have the right and responsibility to remove, edit, or 41 | reject comments, commits, code, wiki edits, issues, and other contributions 42 | that are not aligned to this Code of Conduct, or to ban temporarily or 43 | permanently any contributor for other behaviors that they deem inappropriate, 44 | threatening, offensive, or harmful. 45 | 46 | ## Scope 47 | 48 | This Code of Conduct applies both within project spaces and in public spaces 49 | when an individual is representing the project or its community. Examples of 50 | representing a project or community include using an official project e-mail 51 | address, posting via an official social media account, or acting as an appointed 52 | representative at an online or offline event. Representation of a project may be 53 | further defined and clarified by project maintainers. 54 | 55 | ## Enforcement 56 | 57 | Instances of abusive, harassing, or otherwise unacceptable behavior may be 58 | reported by contacting the project team at muneebullashariff@gmail.com. All 59 | complaints will be reviewed and investigated and will result in a response that 60 | is deemed necessary and appropriate to the circumstances. The project team is 61 | obligated to maintain confidentiality with regard to the reporter of an incident. 62 | Further details of specific enforcement policies may be posted separately. 63 | 64 | Project maintainers who do not follow or enforce the Code of Conduct in good 65 | faith may face temporary or permanent repercussions as determined by other 66 | members of the project's leadership. 67 | 68 | ## Attribution 69 | 70 | This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, 71 | available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html 72 | 73 | [homepage]: https://www.contributor-covenant.org 74 | 75 | For answers to common questions about this code of conduct, see 76 | https://www.contributor-covenant.org/faq 77 | -------------------------------------------------------------------------------- /axi_virt_seq.sv: -------------------------------------------------------------------------------- 1 | 2 | // ########################################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | // ########################################################################### 22 | 23 | //Virtual Sequence base class 24 | class axi_virtual_seq_base extends uvm_sequence #(axi_seq_item); 25 | 26 | //Factory Registration 27 | `uvm_object_utils(axi_virtual_seq_base) 28 | 29 | bit addr [31:0]; 30 | axi_master_wr_exclsv_seq wr_exclsv_seq; 31 | axi_master_rd_exclsv_seq rd_exclsv_seq; 32 | axi_virtual_sequencer v_seqr; 33 | axi_master_sequencer mstr_sqr; 34 | axi_slave_sequencer slv_sqr; 35 | 36 | //Constructor 37 | 38 | function new(string name = "axi_virtual_seq_base"); 39 | super.new(name); 40 | endfunction 41 | 42 | //Body Method 43 | 44 | task body(); 45 | 46 | if(!$cast(v_seqr, m_sequencer)) 47 | begin 48 | `uvm_error (get_full_name(), "CASTING FAILED"); 49 | end 50 | mstr_sqr = v_seqr.mstr_vseqr_h; 51 | slv_sqr = v_seqr.slv_vseqr_h; 52 | 53 | endtask 54 | endclass 55 | 56 | 57 | //Sequence 1 : Exclusive read followed by Exclusive write 58 | class exclsv_rd_wr_vseq extends axi_virtual_seq_base; 59 | 60 | //Factory Registration 61 | `uvm_object_utils (exclsv_rd_wr_vseq) 62 | 63 | //Constructor 64 | function new(string name = "exclsv_rd_wr_vseq"); 65 | super.new(name); 66 | endfunction 67 | 68 | //Body method 69 | virtual task body(); 70 | `uvm_info (get_type_name(), "********Exclusive Read followed by Exclusive Write started********", UVM_LOW) 71 | 72 | `uvm_do_on (rd_exclsv_seq, master_seqr) 73 | addr = rd_exclsv_seq.exclsv_addr; 74 | `uvm_do_on_with (wr_exclsv_seq, master_seqr,{exclsv_addr == addr;}) 75 | 76 | `uvm_info (get_type_name(), "*******Exclusive Read followed by Exclusive Write ended********", UVM_LOW) 77 | 78 | endtask 79 | endclass 80 | 81 | 82 | //Scenario 2 : Exclusive read followed by Normal write 83 | class exclsv_rd_normal_wr_vseq extends axi_virtual_seq_base; 84 | 85 | //Factory Registration 86 | `uvm_object_utils (exclsv_rd_normal_wr_vseq) 87 | 88 | //Constructor 89 | function new(string name = "exclsv_rd_normal_wr_vseq"); 90 | super.new(name); 91 | endfunction 92 | 93 | //Body method 94 | virtual task body(); 95 | `uvm_info (get_type_name(), "********Exclusive Read followed by Normal Write started********", UVM_LOW) 96 | 97 | `uvm_do_on (rd_exclsv_seq, master_seqr) 98 | addr = rd_exclsv_seq.exclsv_addr; 99 | `uvm_do_on_with (wr_seq, master_seqr,{exclsv_addr == addr;}) //To be fixed by normal write sequence 100 | 101 | `uvm_info (get_type_name(), "*******Exclusive Read followed by Normal Write ended********", UVM_LOW) 102 | 103 | endtask 104 | endclass 105 | -------------------------------------------------------------------------------- /axi_tb_files/env/axi_virt_seq.sv: -------------------------------------------------------------------------------- 1 | 2 | // ########################################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | // ########################################################################### 22 | 23 | //Virtual Sequence base class 24 | class axi_virtual_seq_base extends uvm_sequence #(axi_seq_item); 25 | 26 | //Factory Registration 27 | `uvm_object_utils(axi_virtual_seq_base) 28 | 29 | bit addr [31:0]; 30 | axi_master_wr_exclsv_seq wr_exclsv_seq; 31 | axi_master_rd_exclsv_seq rd_exclsv_seq; 32 | axi_virtual_sequencer v_seqr; 33 | axi_master_sequencer mstr_sqr; 34 | axi_slave_sequencer slv_sqr; 35 | 36 | //Constructor 37 | 38 | function new(string name = "axi_virtual_seq_base"); 39 | super.new(name); 40 | endfunction 41 | 42 | //Body Method 43 | 44 | task body(); 45 | 46 | if(!$cast(v_seqr, m_sequencer)) 47 | begin 48 | `uvm_error (get_full_name(), "CASTING FAILED"); 49 | end 50 | mstr_sqr = v_seqr.mstr_vseqr_h; 51 | slv_sqr = v_seqr.slv_vseqr_h; 52 | 53 | endtask 54 | endclass 55 | 56 | 57 | //Sequence 1 : Exclusive read followed by Exclusive write 58 | class exclsv_rd_wr_vseq extends axi_virtual_seq_base; 59 | 60 | //Factory Registration 61 | `uvm_object_utils (exclsv_rd_wr_vseq) 62 | 63 | //Constructor 64 | function new(string name = "exclsv_rd_wr_vseq"); 65 | super.new(name); 66 | endfunction 67 | 68 | //Body method 69 | virtual task body(); 70 | `uvm_info (get_type_name(), "********Exclusive Read followed by Exclusive Write started********", UVM_LOW) 71 | 72 | `uvm_do_on (rd_exclsv_seq, master_seqr) 73 | addr = rd_exclsv_seq.exclsv_addr; 74 | `uvm_do_on_with (wr_exclsv_seq, master_seqr,{exclsv_addr == addr;}) 75 | 76 | `uvm_info (get_type_name(), "*******Exclusive Read followed by Exclusive Write ended********", UVM_LOW) 77 | 78 | endtask 79 | endclass 80 | 81 | 82 | //Scenario 2 : Exclusive read followed by Normal write 83 | class exclsv_rd_normal_wr_vseq extends axi_virtual_seq_base; 84 | 85 | //Factory Registration 86 | `uvm_object_utils (exclsv_rd_normal_wr_vseq) 87 | 88 | //Constructor 89 | function new(string name = "exclsv_rd_normal_wr_vseq"); 90 | super.new(name); 91 | endfunction 92 | 93 | //Body method 94 | virtual task body(); 95 | `uvm_info (get_type_name(), "********Exclusive Read followed by Normal Write started********", UVM_LOW) 96 | 97 | `uvm_do_on (rd_exclsv_seq, master_seqr) 98 | addr = rd_exclsv_seq.exclsv_addr; 99 | `uvm_do_on_with (wr_seq, master_seqr,{exclsv_addr == addr;}) //To be fixed by normal write sequence 100 | 101 | `uvm_info (get_type_name(), "*******Exclusive Read followed by Normal Write ended********", UVM_LOW) 102 | 103 | endtask 104 | endclass 105 | -------------------------------------------------------------------------------- /axi_tb_files/axi_slave/axi_slave_trans.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | class axi_slave_trans extends uvm_sequence_item; 23 | 24 | typedef enum logic [1:0] {FIXED, INCR, WRAP, RESERVED} burst_t; 25 | typedef enum bit [1:0] {OKAY, EXOKAY, SLVERR, DECERR} resp_t; 26 | 27 | //Write address signal 28 | logic AWVALID; 29 | rand bit AWREADY; 30 | logic [31:0] AWADDR; 31 | logic [2:0] AWPROT; 32 | logic [3:0] AWID; 33 | logic [3:0] AWLEN; 34 | logic [2:0] AWSIZE; 35 | burst_t AWBURST; 36 | logic [1:0] AWLOCK; 37 | logic [3:0] AWCACHE; 38 | 39 | //Write data signal 40 | logic WVALID; 41 | rand bit WREADY; 42 | logic [31:0] WDATA; 43 | logic [3:0] WSTRB; 44 | logic [3:0] WID; 45 | logic WLAST; 46 | 47 | //Write response signal 48 | rand bit BVLAID; 49 | logic BREADY; 50 | rand resp_t BRESP; 51 | rand bit [3:0] BID; 52 | 53 | //Read address signal 54 | logic ARVALID; 55 | rand bit ARREADY; 56 | logic [31:0] ARADDR; 57 | logic [2:0] ARPROT; 58 | logic [3:0] ARID; 59 | logic [3:0] ARLEN; 60 | logic [2:0] ARSIZE; 61 | burst_t ARBURST; 62 | logic [1:0] ARLOCK; 63 | logic [3:0] ARCACHE; 64 | 65 | //Read data signal 66 | rand bit RVALID; 67 | logic RREADY; 68 | rand bit [31:0] RDATA; 69 | rand resp_t RRESP; 70 | rand bit RLAST; 71 | rand bit [3:0] RID; 72 | 73 | /////////////////////////////////// 74 | //Constraints to be added 75 | //////////////////////////////////// 76 | 77 | function new(string name="axi_slave_trans"); 78 | super.new(name); 79 | endfunction 80 | 81 | 82 | `uvm_object_utils_begin(axi_slave_trans) 83 | `uvm_field_int(AWADDR,UVM_ALL_ON) 84 | `uvm_field_int(AWVALID,UVM_ALL_ON) 85 | `uvm_field_int(AWREADY,UVM_ALL_ON) 86 | `uvm_field_int(AWPROT,UVM_ALL_ON) 87 | `uvm_field_int(AWID,UVM_ALL_ON) 88 | `uvm_field_int(AWLEN,UVM_ALL_ON) 89 | `uvm_field_int(AWSIZE,UVM_ALL_ON) 90 | `uvm_field_int(AWBURST,UVM_ALL_ON) 91 | `uvm_field_int(AWLOCK,UVM_ALL_ON) 92 | `uvm_field_int(AWCACHE,UVM_ALL_ON) 93 | `uvm_field_int(WREADY,UVM_ALL_ON) 94 | `uvm_field_int(WDATA,UVM_ALL_ON) 95 | `uvm_field_int(WVALID,UVM_ALL_ON) 96 | `uvm_field_int(WLAST,UVM_ALL_ON) 97 | `uvm_field_int(WSTRB,UVM_ALL_ON) 98 | `uvm_field_int(BVALID,UVM_ALL_ON) 99 | `uvm_field_int(BREADY,UVM_ALL_ON) 100 | `uvm_field_int(BRESP,UVM_ALL_ON) 101 | `uvm_field_int(BID,UVM_ALL_ON) 102 | `uvm_field_int(ARADDR,UVM_ALL_ON) 103 | `uvm_field_int(ARVALID,UVM_ALL_ON) 104 | `uvm_field_int(ARREADY,UVM_ALL_ON) 105 | `uvm_field_int(ARPROT,UVM_ALL_ON) 106 | `uvm_field_int(ARID,UVM_ALL_ON) 107 | `uvm_field_int(ARLEN,UVM_ALL_ON) 108 | `uvm_field_int(ARBURST,UVM_ALL_ON) 109 | `uvm_field_int(ARSIZE,UVM_ALL_ON) 110 | `uvm_field_int(ARLOCK,UVM_ALL_ON) 111 | `uvm_field_int(ARCACHE,UVM_ALL_ON) 112 | `uvm_field_int(RVALID,UVM_ALL_ON) 113 | `uvm_field_int(RREADY,UVM_ALL_ON) 114 | `uvm_field_int(RDATA,UVM_ALL_ON) 115 | `uvm_field_int(RRESP,UVM_ALL_ON) 116 | `uvm_field_int(RID,UVM_ALL_ON) 117 | `uvm_field_int(RLAST,UVM_ALL_ON) 118 | 119 | `uvm_object_utils_end 120 | 121 | endclass 122 | -------------------------------------------------------------------------------- /axi_test.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //Base test 23 | class axi_test extends uvm_test; 24 | 25 | axi_env env; 26 | 27 | //Factory registration 28 | `uvm_component_utils (axi_test) 29 | 30 | //Constructor 31 | function new(string name = "axi_test", uvm_component parent); 32 | super.new(name, parent); 33 | endfunction 34 | 35 | 36 | //Building test component 37 | function void build_phase (uvm_phase phase); 38 | env = axi_env::typeid::create ("env", this); 39 | 40 | //**** "Getting Interface****// 41 | if (!uvm_config_db #(virtual axi_if)::get(this, "", vif, i_f)) 42 | `uvm_error ("AXI_INTERFACE", "Cannot get interface") 43 | 44 | //**** Setting Environment Config*****// 45 | uvm_config_db #(axi_tb_config)::set(this, "*", "axi_tb_config", tb_cfg); 46 | 47 | super.build_phase(phase); 48 | endfunction 49 | 50 | //Printing the topology/heirarchy of the TB components 51 | function void end_of_elaboration_phase (uvm_phase phase); 52 | uvm_top.print_topology(); 53 | endfunction 54 | 55 | endclass 56 | 57 | 58 | //Test 1: Write Sequence 59 | class axi_write_test extends axi_test; 60 | 61 | axi_write_sequence wr_sequence; 62 | 63 | //Factory registration 64 | `uvm_component_utils (axi_write_test) 65 | 66 | //Constructor 67 | function new(string name = "axi_write_test", uvm_component parent); 68 | super.new(name, parent); 69 | endfunction 70 | 71 | function void build_phase (uvm_phase phase); 72 | super.build_phase(phase); 73 | endfunction 74 | 75 | function run_phase (uvm_phase phase); 76 | 77 | wr_sequence = axi_write_sequence::typeid::create("wr_sequence"); 78 | phase.raise_objection(this); 79 | wr_sequence.start(env.v_seqr); 80 | #100; 81 | phase.drop_objection(this); 82 | 83 | endfunction 84 | endclass 85 | 86 | 87 | //Test 2 : Exclusive Sequence (Exclsv Read followed by Exclsv Write to same address) 88 | 89 | class axi_exclsv_rd_wr_test extends axi_test; 90 | 91 | exclsv_rd_wr_vseq exclsv_rd_wr;; 92 | 93 | //Factory registration 94 | `uvm_component_utils (axi_exclsv_rd_wr_test) 95 | 96 | //Constructor 97 | function new(string name = "axi_exclsv_rd_wr_test;", uvm_component parent); 98 | super.new(name, parent); 99 | endfunction 100 | 101 | function void build_phase (uvm_phase phase); 102 | super.build_phase(phase); 103 | endfunction 104 | 105 | function run_phase (uvm_phase phase); 106 | 107 | exclsv_rd_wr = exclsv_rd_wr_vseq::typeid::create("exclsv_rd_wr"); 108 | phase.raise_objection(this); 109 | exclsv_rd_wr.start(env.v_seqr); 110 | #100; 111 | phase.drop_objection(this); 112 | 113 | endfunction 114 | endclass 115 | 116 | //Test 3 : Exclusive Sequence (Exclsv Read followed by Normal Write to same address) 117 | 118 | class axi_exclsv_rd_normal_wr_test extends axi_test; 119 | 120 | exclsv_rd_nor_wr_vseq exclsv_rd_nor_wr;; 121 | 122 | //Factory registration 123 | `uvm_component_utils (axi_exclsv_rd_normal_wr_test) 124 | 125 | //Constructor 126 | function new(string name = "axi_exclsv_rd_normal_wr_test;", uvm_component parent); 127 | super.new(name, parent); 128 | endfunction 129 | 130 | function void build_phase (uvm_phase phase); 131 | super.build_phase(phase); 132 | endfunction 133 | 134 | function run_phase (uvm_phase phase); 135 | 136 | exclsv_rd_nor_wr = exclsv_rd_nor_wr_vseq::typeid::create("exclsv_rd_nor_wr"); 137 | phase.raise_objection(this); 138 | exclsv_rd_nor_wr.start(env.v_seqr); 139 | #100; 140 | phase.drop_objection(this); 141 | 142 | endfunction 143 | endclass 144 | -------------------------------------------------------------------------------- /axi_tb_files/axi_master/axi_master_agent.sv: -------------------------------------------------------------------------------- 1 | // ################################################################################################ 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one or more contributor license 4 | // agreements. See the NOTICE file distributed with this work for additional information 5 | // regarding copyright ownership. The ASF licenses this file to you under the Apache License, 6 | // Version 2.0 (the"License"); you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software distributed under the 12 | // License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 13 | // either express or implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | // 16 | // ################################################################################################ 17 | 18 | `ifndef AXI_MASTER_AGENT_INCLUDED 19 | `define AXI_MASTER_AGENT_INCLUDED 20 | 21 | //------------------------------------------------------------------------------------------------// 22 | // Class: axi_master_agent 23 | // axi_master_agent is extended from uvm_agent, uvm_agent is inherited by uvm_component. 24 | // An agent typically contains: a driver,sequencer, and monitor. Agents can be configured either 25 | // active or passive. 26 | //------------------------------------------------------------------------------------------------// 27 | 28 | class axi_master_agent extends uvm_agent; 29 | 30 | //Factory registration 31 | `uvm_component_utils(axi_master_agent) 32 | 33 | //declare handle of master_agent_config which is extended from the configuration class 34 | axi_master_agent_config m_agt_cfg; 35 | 36 | //Handles for the driver, monitor, sequencer 37 | axi_master_driver m_drvh; 38 | axi_master_monitor m_monh; 39 | axi_master_sequencer m_sequencer; 40 | 41 | 42 | //--------------------------------------------- 43 | // Externally defined tasks and functions 44 | //--------------------------------------------- 45 | extern function new(string name="axi_master_agent", uvm_component parent); 46 | extern function void build_phase(uvm_phase phase); 47 | extern function void connect_phase (uvm_phase phase); 48 | 49 | endclass 50 | 51 | //----------------------------------------------------------------------------- 52 | // Constructor: new 53 | // Initializes the master_agent class component 54 | // 55 | // Parameters: 56 | // name - instance name of the config_template 57 | // parent - parent under which this component is created 58 | //----------------------------------------------------------------------------- 59 | 60 | function axi_master_agent::new(string name="axi_master_agent", uvm_component parent); 61 | super.new(name, parent); 62 | endfunction:new 63 | 64 | 65 | //----------------------------------------------------------------------------- 66 | // Function: build_phase 67 | // Creates the required components 68 | // 69 | // Parameters: 70 | // phase - stores the current phase 71 | //----------------------------------------------------------------------------- 72 | 73 | function void axi_master_agent::build_phase(uvm_phase phase); 74 | super.build_phase(phase); 75 | 76 | if(!uvm_config_db #(axi_master_agent_config)::get(this,"","axi_master_agent_config",m_agt_cfg)) 77 | `uvm_fatal("CONFIG", "cannot get() m_agt_cfg from uvm_config_db. Have you set it?") 78 | 79 | //For Active UVM Agent monitor class is created along with the Sequencer and Driver but for the 80 | //Passive UVM Agent only Monitor is created 81 | 82 | m_monh=axi_master_monitor::type_id::create("m_monh", this); 83 | 84 | if(m_agt_cfg.is_active==UVM_ACTIVE); 85 | begin 86 | m_drvh=axi_master_driver::type_id::create("m_drvh", this); 87 | m_sequencer=axi_master_sequencer::type_id::create("m_sequencer", this); 88 | end 89 | 90 | endfunction:build_phase 91 | 92 | 93 | //-----------------------------------------------------------------------------------------------// 94 | // Function: connect_phase 95 | // The connect phase is used to make TLM connections between components 96 | //------------------------------------------------------------------------------------------------// 97 | 98 | function void axi_master_agent::connect_phase(uvm_phase phase); 99 | if(m_agt_cfg.is_active==UVM_ACTIVE) 100 | m_drvh.seq_item_port.connect(m_sequencer.seq_item_export); 101 | endfunction:connect_phase 102 | 103 | ///////////////////////////////////////////////////////////////////////////////////////// 104 | `endif 105 | 106 | -------------------------------------------------------------------------------- /axi_tb_files/axi_slave/axi_slave_monitor.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //----------------------------------------------------------------------------- 23 | // Class : AXI Slave Monitor 24 | // Description of the class : axi slave monitor 25 | // FILE NAME: axi_slave_monitor.sv 26 | //----------------------------------------------------------------------------- 27 | 28 | `ifndef AXI_SLAVE_MONITOR_SV 29 | `define AXI_SLAVE_MONITOR_SV 30 | 31 | class AXI_slave_monitor extends uvm_monitor; 32 | 33 | virtual interface AXI_vif ms_vif; 34 | 35 | AXI_transfer t_trx; 36 | 37 | // component macro 38 | `uvm_component_utils(AXI_slave_monitor) 39 | 40 | // component constructor - required syntax for UVM automation and utilities 41 | function new (string name, uvm_component parent); 42 | super.new(name, parent); 43 | //t_trx = new(); 44 | endfunction : new 45 | 46 | function void build_phase(uvm_phase phase); 47 | if (!axi_vif_config::get(this,"","ms_vif", ms_vif)) 48 | `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".ms_vif"}) 49 | endfunction: build_phase 50 | 51 | function void start_of_simulation_phase(uvm_phase phase); 52 | `uvm_info(get_type_name(), {"start of simulation for ", get_full_name()}, UVM_HIGH); 53 | endfunction : start_of_simulation_phase 54 | 55 | extern virtual task run_phase(uvm_phase phase); 56 | extern virtual protected task collect_write_transfer(); 57 | extern virtual protected task collect_addr_write_trx(); 58 | extern virtual protected task collect_data_write_trx(); 59 | 60 | endclass : AXI_slave_monitor 61 | 62 | // UVM run_phase() 63 | task AXI_slave_monitor::run_phase(uvm_phase phase); 64 | `uvm_info(get_type_name(), "Inside the run_phase", UVM_MEDIUM); 65 | forever begin 66 | t_trx = AXI_transfer::type_id::create(); 67 | collect_write_transfer(); 68 | end 69 | endtask : run_phase 70 | 71 | task AXI_slave_monitor::collect_write_transfer(); 72 | fork 73 | collect_addr_write_trx(); 74 | collect_data_write_trx(); 75 | join 76 | endtask : collect_write_transfer 77 | 78 | // collect addr write @ pos edge 79 | task AXI_slave_monitor::collect_addr_write_trx(); 80 | 81 | // check write pool, if the W(id) is not found,then create a new one 82 | // and recored it's timing 83 | 84 | 85 | //forever begin 86 | while(ms_vif.AXI_AWVALID == 1'b1 && ms_vif.AXI_AWREADY == 1'b1) begin 87 | @(posedge ms_vif.AXI_ACLK); 88 | t_trx.rw = 1; 89 | t_trx.addr = ms_vif.AXI_AWADDR; 90 | t_trx.id = ms_vif.AXI_AWID; 91 | t_trx.len = ms_vif.AXI_AWLEN; 92 | t_trx.size = ms_vif.AXI_AWSIZE; 93 | t_trx.burst = ms_vif.AXI_AWBURST; 94 | t_trx.addr_done = `TRUE; 95 | end 96 | endtask : collect_addr_write_trx 97 | 98 | 99 | // collect data write @ pos edge 100 | task AXI_slave_monitor::collect_data_write_trx(); 101 | int j; 102 | bit [31:0] temp_data; 103 | bit [3:0] temp_strb; 104 | 105 | while(ms_vif.AXI_WVALID == 1'b1 && ms_vif.AXI_WREADY == 1'b1)begin 106 | @(posedge ms_vif.AXI_ACLK); 107 | t_trx.data.push_back(ms_vif.AXI_WDATA); 108 | t_trx.strb.push_back(ms_vif.AXI_WSTRB); 109 | t_trx.wid = ms_vif.AXI_WID; 110 | 111 | if (ms_vif.AXI_WLAST == 1'b1) begin 112 | t_trx.wlast = ms_vif.AXI_WLAST; 113 | t_trx.data_done = `TRUE; 114 | $display("From Slave Monitor @ %g",$time); 115 | t_trx.print(); 116 | j = t_trx.data.size(); 117 | foreach(t_trx.data[j]) begin 118 | temp_data = t_trx.data.pop_front(); 119 | temp_strb = t_trx.strb.pop_front(); 120 | end 121 | end 122 | end 123 | 124 | endtask : collect_data_write_trx 125 | 126 | `endif 127 | -------------------------------------------------------------------------------- /axi_tb_files/test/axi_test.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | //Base test 23 | class axi_test extends uvm_test; 24 | 25 | axi_env env; 26 | 27 | //Factory registration 28 | `uvm_component_utils (axi_test) 29 | 30 | //Constructor 31 | function new(string name = "axi_test", uvm_component parent); 32 | super.new(name, parent); 33 | endfunction 34 | 35 | 36 | //Building test component 37 | function void build_phase (uvm_phase phase); 38 | env = axi_env::typeid::create ("env", this); 39 | 40 | //**** "Getting Interface****// 41 | if (!uvm_config_db #(virtual axi_if)::get(this, "", vif, i_f)) 42 | `uvm_error ("AXI_INTERFACE", "Cannot get interface") 43 | 44 | //**** Setting Environment Config*****// 45 | uvm_config_db #(axi_tb_config)::set(this, "*", "axi_tb_config", tb_cfg); 46 | 47 | super.build_phase(phase); 48 | endfunction 49 | 50 | //Printing the topology/heirarchy of the TB components 51 | function void end_of_elaboration_phase (uvm_phase phase); 52 | uvm_top.print_topology(); 53 | endfunction 54 | 55 | endclass 56 | 57 | 58 | //Test 1: Write and Read sequence Test 59 | class axi_write_read_test extends axi_test; 60 | 61 | axi_write_sequence wr_sequence; 62 | axi_read_sequence rd_sequence; 63 | 64 | //Factory registration 65 | `uvm_component_utils (axi_write_test) 66 | 67 | //Constructor 68 | function new(string name = "axi_write_read_test", uvm_component parent); 69 | super.new(name, parent); 70 | endfunction 71 | 72 | function void build_phase (uvm_phase phase); 73 | super.build_phase(phase); 74 | endfunction 75 | 76 | function run_phase (uvm_phase phase); 77 | 78 | wr_sequence = axi_write_sequence::typeid::create("wr_sequence"); 79 | rd_sequence = axi_read_sequence::typeid::create("rd_sequence"); 80 | 81 | phase.raise_objection(this); 82 | wr_sequence.start(env.v_seqr); 83 | rd_sequence.start(env.v_seqr); 84 | #100; 85 | phase.drop_objection(this); 86 | 87 | endfunction 88 | endclass 89 | 90 | 91 | //Test 2 : Exclusive Sequence (Exclsv Read followed by Exclsv Write to same address) 92 | 93 | class axi_exclsv_rd_wr_test extends axi_test; 94 | 95 | exclsv_rd_wr_vseq exclsv_rd_wr;; 96 | 97 | //Factory registration 98 | `uvm_component_utils (axi_exclsv_rd_wr_test) 99 | 100 | //Constructor 101 | function new(string name = "axi_exclsv_rd_wr_test;", uvm_component parent); 102 | super.new(name, parent); 103 | endfunction 104 | 105 | function void build_phase (uvm_phase phase); 106 | super.build_phase(phase); 107 | endfunction 108 | 109 | function run_phase (uvm_phase phase); 110 | 111 | exclsv_rd_wr = exclsv_rd_wr_vseq::typeid::create("exclsv_rd_wr"); 112 | phase.raise_objection(this); 113 | exclsv_rd_wr.start(env.v_seqr); 114 | #100; 115 | phase.drop_objection(this); 116 | 117 | endfunction 118 | endclass 119 | 120 | //Test 3 : Exclusive Sequence (Exclsv Read followed by Normal Write to same address) 121 | 122 | class axi_exclsv_rd_normal_wr_test extends axi_test; 123 | 124 | exclsv_rd_nor_wr_vseq exclsv_rd_nor_wr;; 125 | 126 | //Factory registration 127 | `uvm_component_utils (axi_exclsv_rd_normal_wr_test) 128 | 129 | //Constructor 130 | function new(string name = "axi_exclsv_rd_normal_wr_test;", uvm_component parent); 131 | super.new(name, parent); 132 | endfunction 133 | 134 | function void build_phase (uvm_phase phase); 135 | super.build_phase(phase); 136 | endfunction 137 | 138 | function run_phase (uvm_phase phase); 139 | 140 | exclsv_rd_nor_wr = exclsv_rd_nor_wr_vseq::typeid::create("exclsv_rd_nor_wr"); 141 | phase.raise_objection(this); 142 | exclsv_rd_nor_wr.start(env.v_seqr); 143 | #100; 144 | phase.drop_objection(this); 145 | 146 | endfunction 147 | endclass 148 | -------------------------------------------------------------------------------- /axi_tb_files/AXI4_OOO_Scoreboard.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI_OOO_SCOREBOARD_INCLUDED_ 23 | `define AXI_OOO_SCOREBOARD_INCLUDED_ 24 | 25 | // declare the implementation ports for incoming transactions 26 | `uvm_analysis_imp_decl(_dut) // for more details about usage one can refer : http://www.testbench.in/UL_11_PHASE_8_SCOREBOARD.html 27 | `uvm_analysis_imp_decl(_ref) 28 | 29 | class AXI4_OOO_scoreboard extends uvm_component; //AXI4 out of order scoreboard 30 | `uvm_component_utils(AXI4_OOO_scoreboard) 31 | 32 | // implementation ports instances 33 | uvm_analysis_imp_dut#(my_trans, AXI4_OOO_scoreboard) dut_in_imp; //analysis port from DUT 34 | uvm_analysis_imp_ref#(my_trans, AXI4_OOO_scoreboard) ref_in_imp; //analysis port from REFERENCE Model 35 | 36 | // queues holding the transactions from different sources 37 | my_trans dut_q[$]; // one queue from Dut 38 | my_trans ref_q[$]; // another queue from REF 39 | 40 | 41 | //----------------------------------------------------------------------------- 42 | // Constructor: new 43 | // Initializes the axi_scoreboard class object 44 | // 45 | // Parameters: 46 | // name - instance name of the axi_scoreboard 47 | // parent - parent under which this component is created 48 | //----------------------------------------------------------------------------- 49 | 50 | function new(string name, uvm_component parent = null); 51 | super.new(name, parent); 52 | dut_in_imp = new("dut_in_imp", this); 53 | ref_in_imp = new("ref_in_imp", this); 54 | endfunction 55 | 56 | //--------------------------------------------------------------------------------- 57 | // Function :: write_dut 58 | // This function receives transactions from DUT through analysis port and calls another function search_and_compare() 59 | //--------------------------------------------------------------------------------- 60 | function void write_dut(my_trans dut_trans); 61 | search_and_compare(dut_trans, ref_q, dut_q); 62 | endfunction 63 | 64 | 65 | //--------------------------------------------------------------------------------- 66 | // Function :: write_ref 67 | // This function receives transactions from reference model through analysis port and calls another function search_and_compare() 68 | //--------------------------------------------------------------------------------- 69 | function void write_ref(my_trans ref_trans); 70 | search_and_compare(ref_trans, dut_q, ref_q); 71 | endfunction 72 | 73 | //---------------------------------------------------------------------------------- 74 | // Function :: search_and_compare 75 | // This function is the main logical function which compares master data which are out of order and compares that with slave data. 76 | // It further checks whether data(s) are matching or not and gives result accordingly. 77 | //----------------------------------------------------------------------------------- 78 | 79 | function void search_and_compare(my_trans a_trans, ref my_trans search_q[$], ref my_trans save_q[$]); 80 | int indexes[$]; 81 | 82 | indexes = search_q.find_first_index(it) with (a_trans.match(it)); // logic to find the index of the data to be compared 83 | 84 | if (indexes.size() == 0) begin 85 | save_q.push_back(a_trans); 86 | return; 87 | end 88 | 89 | // sample a_trans coverage 90 | search_q.delete(indexes[0]); 91 | endfunction 92 | 93 | // at the end of the test we need to check that the two queues are empty 94 | 95 | function void check_phase(uvm_phase phase); 96 | super.check_phase(phase); 97 | REF_Q_ERR : assert(ref_q.size() == 0) else 98 | `uvm_error("REF_Q_ERR", $sformatf("ref_q is not empty!!! It still contains %d transactions!", ref_q.size())) 99 | 100 | DUT_Q_ERR : assert(dut_q.size() == 0) else 101 | `uvm_error("DUT_Q_ERR", $sformatf("dut_q is not empty!!! It still contains %d transactions!", dut_q.size())) 102 | endfunction 103 | 104 | endclass 105 | 106 | 107 | `endif 108 | 109 | 110 | -------------------------------------------------------------------------------- /axi_tb_files/AXI4_Scoreboard.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI_SCOREBOARD_INCLUDED_ 23 | `define AXI_SCOREBOARD_INCLUDED_ 24 | 25 | //----------------------------------------------------------------------------- 26 | // Class: axi_scoreboard 27 | // Description of the class. For ex: 28 | // This class verifies the functionality of axi design which recieves transaction 29 | // level objects captured from interfaces of a DUT via TLM analysis Ports 30 | // (or fifos) 31 | //----------------------------------------------------------------------------- 32 | 33 | class axi_scoreboard extends uvm_scoreboard; 34 | `uvm_component_utils(axi_scoreboard) 35 | 36 | uvm_tlm_analysis_fifo #(write_xtn_master) fifo_master; // TLM analysis fifo for master 37 | uvm_tlm_analysis_fifo #(write_xtn_slave) fifo_slave; // TLM analysis fifo for slave 38 | 39 | write_xtn_master master_data; //Master write Transaction 40 | write_xtn_slave slave_data; //Slave write Transaction 41 | 42 | static int no_of_write_packet; //total number of transactions received from write monitor 43 | static int no_of_read_packet; //total number of transactions received from read monitor 44 | static int no_of_data_verification; //total number of data for verification (read + write) 45 | static int no_of_data_with_success; //total number of data verified with success i.e. matching 46 | static int no_of_data_with_failure; //total number of data verified with failure i.e. not matching 47 | 48 | //----------------------------------------------------------------------------- 49 | // Constructor: new 50 | // Initializes the axi_scoreboard class object 51 | // 52 | // Parameters: 53 | // name - instance name of the axi_scoreboard 54 | // parent - parent under which this component is created 55 | //----------------------------------------------------------------------------- 56 | 57 | function new(string name,uvm_component parent); 58 | super.new(name, parent); 59 | 60 | fifo_master=new("fifo_master",this); 61 | fifo_slave=new("fifo_slave",this); 62 | endfunction 63 | 64 | //----------------------------------------------------------------------------- 65 | // Task: run_phase 66 | // This is the main task that can consume simulation time in UVM and initiates the main data checking function i.e. check_phase() 67 | // 68 | // Parameters: 69 | // phase - stores the current phase 70 | //----------------------------------------------------------------------------- 71 | 72 | task run_phase(uvm_phase phase); 73 | forever 74 | begin 75 | fork 76 | begin 77 | fifo_master.get(master_data); 78 | $display("write_data_receive in sb at time %0t",$time); 79 | no_of_write_packet++; 80 | end 81 | 82 | begin 83 | fifo_slave.get(slave_data); 84 | $display("read_data_receive in sb at time %0t",$time); 85 | no_of_read_packet++; 86 | end 87 | join 88 | 89 | $display("checking*****SB got the wr and rd data at time %0t******......",$time); 90 | check_phase(); 91 | end 92 | endtask 93 | 94 | //--------------------------------------------------------------------------------- 95 | // Function: check_phase() 96 | // This function compares prints master data as well slave data. It further 97 | // checks whether data(s) are matching or not and gives result accordingly. 98 | // 99 | // -------------------------------------------------------------------------------- 100 | 101 | function void check_phase(); 102 | 103 | `uvm_info("scoreboard",$sformatf("wr_moniter at time %0t",$time),UVM_LOW) 104 | master_data.print; 105 | 106 | `uvm_info("scoreboard",$sformatf("rd_moniter at time %0t",$time),UVM_LOW) 107 | slave_data.print; 108 | 109 | foreach(master_data.MDATA[i]) 110 | begin 111 | if(master_data.MDATA[i] != slave_data.WDATA[i]) 112 | begin 113 | `uvm_info("axi_scoreboard",$sformatf("DATA mismatch[%0d]",i),UVM_LOW) 114 | no_of_data_with_failure++; 115 | no_of_data_verification++; 116 | end 117 | else 118 | begin 119 | `uvm_info("axi_scoreboard",$sformatf("DATA match[%0d]",i),UVM_LOW) 120 | no_of_data_with_success++; 121 | no_of_data_verification++; 122 | end 123 | end 124 | 125 | 126 | $display(" ***************************** SCOREBOARD RESULT FOR PACKET *************************************\n"); 127 | $display(" NO OF TRANS RECEIVED FROM WR_MONITOR: %0d ",no_of_write_packet); 128 | $display(" NO OF TRANS RECEIVED FROM RD_MONITOR: %0d ",no_of_read_packet); 129 | $display(" TOTAL NO OF DATA VERIFIED : %0d ", no_of_data_verification); 130 | $display(" TOTAL NO OF DATA VERIFIED WITH SUCCESS: %0d ", no_of_data_with_success); 131 | $display(" TOTAL NO OF DATA VERIFIED WITH FAILURE: %0d ", no_of_data_with_failure); 132 | 133 | endfunction 134 | endclass 135 | 136 | `endif 137 | 138 | -------------------------------------------------------------------------------- /axi_tb_files/axi_master/axi_master_trans.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | class axi_master_trans extends uvm_sequence_item; 23 | 24 | typedef enum bit [1:0] {FIXED, INCR, WRAP, RESERVED} burst_t; 25 | typedef enum logic [1:0] {OKAY, EXOKAY, SLVERR, DECERR} resp_t; 26 | 27 | //Write address signal 28 | rand bit AWVALID; 29 | logic AWREADY; 30 | rand bit [31:0] AWADDR; 31 | rand bit [2:0] AWPROT; 32 | rand bit [3:0] AWID; 33 | rand bit [3:0] AWLEN; 34 | rand bit [2:0] AWSIZE; 35 | rand burst_t AWBURST; 36 | rand bit [1:0] AWLOCK; 37 | rand bit [3:0] AWCACHE; 38 | 39 | //Write data signal 40 | rand bit WVALID; 41 | logic WREADY; 42 | rand bit [31:0] WDATA; 43 | rand bit [3:0] WSTRB; 44 | rand bit [3:0] WID; 45 | rand bit WLAST; 46 | 47 | //Write response signal 48 | logic BVLAID; 49 | rand bit BREADY; 50 | resp_t BRESP; 51 | logic [3:0] BID; 52 | 53 | //Read address signal 54 | rand bit ARVALID; 55 | logic ARREADY; 56 | rand bit [31:0] ARADDR; 57 | rand bit [2:0] ARPROT; 58 | rand bit [3:0] ARID; 59 | rand bit [3:0] ARLEN; 60 | rand bit [2:0] ARSIZE; 61 | rand burst_t ARBURST; 62 | rand bit [1:0] ARLOCK; 63 | rand bit [3:0] ARCACHE; 64 | 65 | //Read data signal 66 | logic RVALID; 67 | rand bit RREADY; 68 | logic [31:0] RDATA; 69 | resp_t RRESP; 70 | logic RLAST; 71 | logic [3:0] RID; 72 | 73 | 74 | constraint WALIGNADDR {AWADDR % 4==0;} //aligned address 75 | constraint RALIGNADDR {ARADDR % 4==0;} 76 | constraint STROBE {WSTRB == 4'b1111;} //write strobe for valid data 77 | constraint WDATA_SIZE {WDATA.size() == AWLEN+1;} //burst length 78 | constraint RDATA_SIZE {RDATA.size() == ARLEN+1;} 79 | 80 | constraint write_address_id_c { 81 | soft AWID == WID; 82 | } 83 | 84 | constraint write_address_c { 85 | soft AWBURST inside {[0:2]}; 86 | soft AWADDR inside {[0:4095]}; 87 | soft WDATA.size() == AWLEN+1; 88 | if (AWBURST == 2) { 89 | soft AWLEN inside {2, 4, 8, 16}; 90 | if (AWSIZE == 1) { 91 | soft AWADDR[0] == 1'b0; 92 | } else if (AWSIZE == 2) { 93 | soft AWADDR[1:0] == 2'b0; 94 | } else if (AWSIZE == 3) { 95 | soft AWADDR[2:0] == 3'b0; 96 | } else if (AWSIZE == 4) { 97 | soft AWADDR[3:0] == 4'b0; 98 | } else if (AWSIZE == 5) { 99 | soft AWADDR[4:0] == 5'b0; 100 | } else if (AWSIZE == 6) { 101 | soft AWADDR[5:0] == 6'b0; 102 | } else if (AWSIZE == 7) { 103 | soft AWADDR[6:0] == 7'b0; 104 | } 105 | } 106 | 107 | solve AWBUSRT before AWLEN; 108 | solve AWBUSRT before AWADDR; 109 | solve AWLEN before WDATA; 110 | solve AWLEN before WSTRB; 111 | } 112 | 113 | constraint read_address_c { 114 | ARBURST inside {[0:2]}; 115 | ARADDR inside {[0:4095]}; 116 | if (ARBURST == 2) { 117 | ARLEN inside {2, 4, 8, 16}; 118 | if (ARSIZE == 1) { 119 | ARADDR[0] == 1'b0; 120 | } else if (ARSIZE == 2) { 121 | ARADDR[1:0] == 2'b0; 122 | } else if (ARSIZE == 3) { 123 | ARADDR[2:0] == 3'b0; 124 | } else if (ARSIZE == 4) { 125 | ARADDR[3:0] == 4'b0; 126 | } else if (ARSIZE == 5) { 127 | ARADDR[4:0] == 5'b0; 128 | } else if (ARSIZE == 6) { 129 | ARADDR[5:0] == 6'b0; 130 | } else if (ARSIZE == 7) { 131 | ARADDR[6:0] == 7'b0; 132 | } 133 | } 134 | } 135 | 136 | constraint write_address_cache_c { 137 | soft (AWCACHE != 4 && AWCACHE != 5 && AWCACHE != 8 && AWCACHE != 9 && AWCACHE != 12 && AWCACHE != 13); //As per Table A4-5 Memory type encoding 138 | } 139 | 140 | constraint read_address_cache_c { 141 | soft (ARCACHE!= 4 && ARCACHE != 5 && ARCACHE != 8 && ARCACHE != 9 && ARCACHE != 12 && ARCACHE != 13); //As per Table A4-5 Memory type encoding 142 | } 143 | 144 | function post_randomize(); 145 | int i, j; 146 | WDATA = new[AWLEN+1]; 147 | WSTRB = new[AWLEN+1]; 148 | foreach (WDATA[i]) begin 149 | WDATA[i] = $urandom_range(((2**(8*(AWSIZE+1)))-1), 0); 150 | end 151 | 152 | foreach (WSTRB[j]) begin 153 | WSTRB[j] = $urandom_range(((2**(AWSIZE+1))-1), 0); 154 | end 155 | endfunction 156 | 157 | 158 | 159 | function new(string name="axi_master_trans"); 160 | super.new(name); 161 | endfunction 162 | 163 | 164 | `uvm_object_utils_begin(axi_master_trans) 165 | `uvm_field_int(AWADDR,UVM_ALL_ON) 166 | `uvm_field_int(AWVALID,UVM_ALL_ON) 167 | `uvm_field_int(AWREADY,UVM_ALL_ON) 168 | `uvm_field_int(AWPROT,UVM_ALL_ON) 169 | `uvm_field_int(AWID,UVM_ALL_ON) 170 | `uvm_field_int(AWLEN,UVM_ALL_ON) 171 | `uvm_field_int(AWSIZE,UVM_ALL_ON) 172 | `uvm_field_int(AWBURST,UVM_ALL_ON) 173 | `uvm_field_int(AWLOCK,UVM_ALL_ON) 174 | `uvm_field_int(AWCACHE,UVM_ALL_ON) 175 | `uvm_field_int(WREADY,UVM_ALL_ON) 176 | `uvm_field_int(WDATA,UVM_ALL_ON) 177 | `uvm_field_int(WVALID,UVM_ALL_ON) 178 | `uvm_field_int(WLAST,UVM_ALL_ON) 179 | `uvm_field_int(WSTRB,UVM_ALL_ON) 180 | `uvm_field_int(BVALID,UVM_ALL_ON) 181 | `uvm_field_int(BREADY,UVM_ALL_ON) 182 | `uvm_field_int(BRESP,UVM_ALL_ON) 183 | `uvm_field_int(BID,UVM_ALL_ON) 184 | `uvm_field_int(ARADDR,UVM_ALL_ON) 185 | `uvm_field_int(ARVALID,UVM_ALL_ON) 186 | `uvm_field_int(ARREADY,UVM_ALL_ON) 187 | `uvm_field_int(ARPROT,UVM_ALL_ON) 188 | `uvm_field_int(ARID,UVM_ALL_ON) 189 | `uvm_field_int(ARLEN,UVM_ALL_ON) 190 | `uvm_field_int(ARBURST,UVM_ALL_ON) 191 | `uvm_field_int(ARSIZE,UVM_ALL_ON) 192 | `uvm_field_int(ARLOCK,UVM_ALL_ON) 193 | `uvm_field_int(ARCACHE,UVM_ALL_ON) 194 | `uvm_field_int(RVALID,UVM_ALL_ON) 195 | `uvm_field_int(RREADY,UVM_ALL_ON) 196 | `uvm_field_int(RDATA,UVM_ALL_ON) 197 | `uvm_field_int(RRESP,UVM_ALL_ON) 198 | `uvm_field_int(RID,UVM_ALL_ON) 199 | `uvm_field_int(RLAST,UVM_ALL_ON) 200 | 201 | `uvm_object_utils_end 202 | 203 | endclass 204 | -------------------------------------------------------------------------------- /axi_tb_files/src/axi_interface.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI_INTF_INCLUDED_ 23 | `define AXI_INTF_INCLUDED_ 24 | 25 | //Inferface file for AXI4 protocol containing all the interface signals 26 | 27 | interface axi_if (input bit clk); 28 | 29 | logic [3:0] AWID; 30 | logic [31:0] AWADDR; 31 | logic [3:0] AWLEN; 32 | logic [2:0] AWSIZE; 33 | logic [1:0] AWBURST; 34 | logic AWLOCK; 35 | logic AWCACHE; 36 | logic AWPROT; 37 | logic AWQOS; 38 | logic AWREGION; 39 | logic AWUSER; 40 | logic AWVALID; 41 | logic AWREADY; 42 | 43 | logic [3:0] WID; 44 | logic [31:0] WDATA; 45 | logic [3:0] WSTRB; 46 | logic WLAST; 47 | logic WUSER; 48 | logic WVALID; 49 | logic WREADY; 50 | 51 | logic [3:0] BID; 52 | logic [1:0] BRESP; 53 | logic BUSER; 54 | logic BVALID; 55 | logic BREADY; 56 | 57 | logic [3:0] ARID; 58 | logic [31:0] ARADDR; 59 | logic [3:0] ARLEN; 60 | logic [2:0] ARSIZE; 61 | logic [1:0] ARBURST; 62 | logic ARLOCK; 63 | logic ARCACHE; 64 | logic ARPROT; 65 | logic ARQOS; 66 | logic ARREGION; 67 | logic ARUSER; 68 | logic ARVALID; 69 | logic ARREADY; 70 | 71 | logic [3:0] RID; 72 | logic [31:0] RDATA; 73 | logic [3:0] RRESP; 74 | logic RLAST; 75 | logic RUSER; 76 | logic RVALID; 77 | logic RREADY; 78 | 79 | // Master_driver clocking block 80 | clocking m_drv_cb @(posedge clk); 81 | default input #1 output #1; 82 | output AWID; 83 | output AWADDR; 84 | output AWLEN; 85 | output AWSIZE; 86 | output AWBURST; 87 | output AWLOCK; 88 | output AWCACHE; 89 | output AWPROT; 90 | output AWQOS; 91 | output AWREGION; 92 | output AWUSER; 93 | output AWVALID; 94 | input AWREADY; 95 | 96 | output WID; 97 | output WDATA; 98 | output WSTRB; 99 | output WLAST; 100 | output WUSER; 101 | output WVALID; 102 | input WREADY; 103 | 104 | input BID; 105 | input BRESP; 106 | input BUSER; 107 | input BVALID; 108 | output BREADY; 109 | 110 | output ARID; 111 | output ARADDR; 112 | output ARLEN; 113 | output ARSIZE; 114 | output ARBURST; 115 | output ARLOCK; 116 | output ARCACHE; 117 | output ARPROT; 118 | output ARQOS; 119 | output ARREGION; 120 | output ARUSER; 121 | output ARVALID; 122 | input ARREADY; 123 | 124 | input RID; 125 | input RDATA; 126 | input RRESP; 127 | input RLAST; 128 | input RUSER; 129 | input RVALID; 130 | output RREADY; 131 | 132 | endclocking 133 | 134 | //master_monitor clocking block 135 | clocking m_mon_cb @(posedge clk); 136 | default input #1 output #1; 137 | 138 | input AWID; 139 | input AWADDR; 140 | input AWLEN; 141 | input AWSIZE; 142 | input AWBURST; 143 | input AWLOCK; 144 | input AWCACHE; 145 | input AWPROT; 146 | input AWQOS; 147 | input AWREGION; 148 | input AWUSER; 149 | input AWVALID; 150 | input AWREADY; 151 | 152 | input WID; 153 | input WDATA; 154 | input WSTRB; 155 | input WLAST; 156 | input WUSER; 157 | input WVALID; 158 | input WREADY; 159 | 160 | input BID; 161 | input BRESP; 162 | input BUSER; 163 | input BVALID; 164 | input BREADY; 165 | 166 | input ARID; 167 | input ARADDR; 168 | input ARLEN; 169 | input ARSIZE; 170 | input ARBURST; 171 | input ARLOCK; 172 | input ARCACHE; 173 | input ARPROT; 174 | input ARQOS; 175 | input ARREGION; 176 | input ARUSER; 177 | input ARVALID; 178 | input ARREADY; 179 | 180 | input RID; 181 | input RDATA; 182 | input RRESP; 183 | input RLAST; 184 | input RUSER; 185 | input RVALID; 186 | input RREADY; 187 | 188 | endclocking 189 | 190 | //slave_driver clocking block 191 | clocking s_drv_cb @(posedge clk); 192 | default input #1 output #1; 193 | 194 | input AWID; 195 | input AWADDR; 196 | input AWLEN; 197 | input AWSIZE; 198 | input AWBURST; 199 | input AWLOCK; 200 | input AWCACHE; 201 | input AWPROT; 202 | input AWQOS; 203 | input AWREGION; 204 | input AWUSER; 205 | input AWVALID; 206 | output AWREADY; 207 | 208 | input WID; 209 | input WDATA; 210 | input WSTRB; 211 | input WLAST; 212 | input WUSER; 213 | input WVALID; 214 | output WREADY; 215 | 216 | output BID; 217 | output BRESP; 218 | output BUSER; 219 | output BVALID; 220 | input BREADY; 221 | 222 | input ARID; 223 | input ARADDR; 224 | input ARLEN; 225 | input ARSIZE; 226 | input ARBURST; 227 | input ARLOCK; 228 | input ARCACHE; 229 | input ARPROT; 230 | input ARQOS; 231 | input ARREGION; 232 | input ARUSER; 233 | input ARVALID; 234 | output ARREADY; 235 | 236 | output RID; 237 | output RDATA; 238 | output RRESP; 239 | output RLAST; 240 | output RUSER; 241 | output RVALID; 242 | input RREADY; 243 | 244 | endclocking 245 | 246 | //slave_monitor clocking block 247 | clocking s_mon_cb @(posedge clk); 248 | default input #1 output #1; 249 | 250 | input AWID; 251 | input AWADDR; 252 | input AWLEN; 253 | input AWSIZE; 254 | input AWBURST; 255 | input AWLOCK; 256 | input AWCACHE; 257 | input AWPROT; 258 | input AWQOS; 259 | input AWREGION; 260 | input AWUSER; 261 | input AWVALID; 262 | input AWREADY; 263 | 264 | input WID; 265 | input WDATA; 266 | input WSTRB; 267 | input WLAST; 268 | input WUSER; 269 | input WVALID; 270 | input WREADY; 271 | 272 | input BID; 273 | input BRESP; 274 | input BUSER; 275 | input BVALID; 276 | input BREADY; 277 | 278 | input ARID; 279 | input ARADDR; 280 | input ARLEN; 281 | input ARSIZE; 282 | input ARBURST; 283 | input ARLOCK; 284 | input ARCACHE; 285 | input ARPROT; 286 | input ARQOS; 287 | input ARREGION; 288 | input ARUSER; 289 | input ARVALID; 290 | input ARREADY; 291 | 292 | input RID; 293 | input RDATA; 294 | input RRESP; 295 | input RLAST; 296 | input RUSER; 297 | input RVALID; 298 | input RREADY; 299 | 300 | endclocking 301 | 302 | 303 | //modports 304 | 305 | modport M_DRV_MP(clocking m_drv_cb); 306 | modport M_MON_MP(clocking m_mon_cb); 307 | modport S_DRV_MP(clocking s_drv_cb); 308 | modport S_MON_MP(clocking s_mon_cb); 309 | 310 | endinterface 311 | 312 | `endif 313 | -------------------------------------------------------------------------------- /axi_tb_files/axi_master/axi_base_sequence.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI_BASE_SEQ_INCLUDED_ 23 | `define AXI_BASE_SEQ_INCLUDED_ 24 | 25 | //------------------------------------------------------------------------------ 26 | // Class: axi_base_sequence 27 | // Description of class. For ex: 28 | // This class is a base sequence class for axi which generates a series of sequence item(s). 29 | // It is parameterized with axi_seq_item, this defines the type of the item that sequence 30 | // will send/receive to/from the driver. 31 | // ----------------------------------------------------------------------------- 32 | 33 | class axi_base_sequence extends uvm_sequence#(axi_master_trans); 34 | 35 | `uvm_object_utils(axi_base_sequence) 36 | 37 | bit [31:0] exclsv_addr; 38 | //----------------------------------------------------------------------------- 39 | // Constructor: new 40 | // Initializes the axi_base_sequence class object 41 | // 42 | // Parameters: 43 | // name - instance name of the axi_base_sequence 44 | //----------------------------------------------------------------------------- 45 | 46 | function new(string name = "axi_base_sequence"); 47 | super.new(name); 48 | endfunction 49 | 50 | /* 51 | //------------------------------------------------------------------------------ 52 | // Method: body() 53 | // body method defines, what the sequence does. 54 | //------------------------------------------------------------------------------ 55 | 56 | virtual task body(); 57 | 58 | req = axi_master_trans::type_id::create("req"); 59 | 60 | wait_for_grant(); 61 | req.randomize(); 62 | send_request(req); 63 | wait_for_item_done(); 64 | endtask 65 | */ 66 | 67 | endclass : axi_base_sequence 68 | 69 | //********************************* WRITE SEQUENCE **************************************************// 70 | 71 | 72 | //`ifndef AXI_WRITE_SEQ_INCLUDED_ 73 | //`define AXI_WRITE_SEQ_INCLUDED_ 74 | 75 | //------------------------------------------------------------------------------ 76 | // Class: axi_write_sequence 77 | // Description of class. For ex: 78 | // This class is a write sequence class for axi which generates a series of sequence 79 | // item(s) for write channel. 80 | // It is extended from axi_base_sequence that will send/receive to/from the driver. 81 | // 82 | // ----------------------------------------------------------------------------- 83 | 84 | class axi_write_sequence extends axi_base_sequence; 85 | 86 | `uvm_object_utils(axi_write_sequence) 87 | 88 | //----------------------------------------------------------------------------- 89 | // Constructor: new 90 | // Initializes the axi_base_sequence class object 91 | // 92 | // Parameters: 93 | // name - instance name of the axi_base_sequence 94 | //----------------------------------------------------------------------------- 95 | 96 | function new(string name = "axi_write_sequence"); 97 | super.new(name); 98 | endfunction 99 | 100 | 101 | //------------------------------------------------------------------------------ 102 | // Method: body() 103 | // body method defines, what the sequence does. 104 | //------------------------------------------------------------------------------ 105 | 106 | virtual task body(); 107 | req = axi_master_trans::type_id::create("req"); 108 | 109 | `uvm_do_with(req,{req.AWVALID == 1; req.WVALID == 1; req.BREADY == 1;}) 110 | 111 | endtask 112 | 113 | endclass:axi_write_sequence 114 | 115 | //********************************* READ SEQUENCE **************************************************// 116 | 117 | //------------------------------------------------------------------------------ 118 | // Class: axi_read_sequence 119 | // Description of class. For ex: 120 | // This class is a read sequence class for axi which generates a series of sequence 121 | // item(s) for read channel. 122 | // It is extended from axi_base_sequence that will send/receive to/from the driver. 123 | // ----------------------------------------------------------------------------- 124 | 125 | class axi_read_sequence extends axi_base_sequence; 126 | 127 | `uvm_object_utils(axi_read_sequence) 128 | 129 | //----------------------------------------------------------------------------- 130 | // Constructor: new 131 | // Initializes the axi_base_sequence class object 132 | // 133 | // Parameters: 134 | // name - instance name of the axi_base_sequence 135 | //----------------------------------------------------------------------------- 136 | 137 | function new(string name = "axi_read_sequence"); 138 | super.new(name); 139 | endfunction 140 | 141 | 142 | //------------------------------------------------------------------------------ 143 | // Method: body() 144 | // body method defines, what the sequence does. 145 | //------------------------------------------------------------------------------ 146 | 147 | virtual task body(); 148 | req = axi_master_trans::type_id::create("req"); 149 | 150 | `uvm_do_with(req,{req.ARVALID == 1; req.RREADY == 1;}) 151 | 152 | endtask 153 | 154 | endclass:axi_read_sequence 155 | 156 | 157 | //******************** EXCLUSIVE WRITE ACCESS ***************************// 158 | 159 | //------------------------------------------------------- 160 | //Class: axi_master_wr_exclsv_seq 161 | //------------------------------------------------------- 162 | class axi_master_wr_exclsv_seq extends axi_base_sequence; 163 | 164 | //Factory Registration 165 | `uvm_object_utils (axi_master_wr_exclsv_seq) 166 | 167 | //Constructor 168 | function new(string name = "axi_master_wr_exclsv_seq"); 169 | super.new(name); 170 | endfunction 171 | 172 | //Body method 173 | virtual task body(); 174 | req = axi_master_trans::type_id::create("req"); 175 | `uvm_do_with(req,{req.AWID == 1; req.AWLOCK == 1; req.AWADDR == exclsv_addr;}) 176 | endtask 177 | 178 | endclass:axi_master_wr_exclsv_seq 179 | 180 | 181 | //******************** EXCLUSIVE READ ACCESS ***************************// 182 | 183 | //------------------------------------------------------- 184 | //Class: axi_master_rd_exclsv_seq 185 | //------------------------------------------------------- 186 | 187 | //Exclusive Read sequence 188 | class axi_master_rd_exclsv_seq extends axi_base_sequence; 189 | 190 | //Factory Registration 191 | `uvm_object_utils (axi_master_rd_exclsv_seq) 192 | 193 | //Constructor 194 | function new(string name = "axi_master_rd_exclsv_seq"); 195 | super.new(name); 196 | endfunction 197 | 198 | //Body method 199 | virtual task body(); 200 | req = axi_master_trans::type_id::create("req"); 201 | `uvm_do_with(req,{req.ARID == 1; req.ARLOCK == 1; req.ARADDR == exclsv_addr;}) 202 | endtask 203 | 204 | endclass:axi_master_rd_exclsv_seq 205 | 206 | ///////////////////////////////////////////////////////////////////////////////// 207 | `endif 208 | 209 | -------------------------------------------------------------------------------- /axi_tb_files/axi_master/axi_master_monitor.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | /////////////////////////////////////MASTER_MONITOR////////////////////////////////////////////////////// 22 | 23 | 24 | `ifndef AXI_MASTER_MONITOR_INCLUDED 25 | `define AXI_MASTER_MONITOR_INCLUDED 26 | 27 | //------------------------------------------------------------------------------------------------ 28 | //Class: master_monitor 29 | //A monitor is a passive entity that samples the DUT signals through the virtual interface and 30 | //converts the signal level activity to the transaction level. 31 | //------------------------------------------------------------------------------------------------ 32 | 33 | class axi_master_monitor extends uvm_monitor; 34 | 35 | //factory registration 36 | `uvm_component_utils(axi_master_monitor) 37 | 38 | //declare VI handle 39 | virtual axi_if vif; 40 | 41 | axi_master_trans m_trans; 42 | 43 | //tlm port 44 | uvm_analysis_port #(axi_xtn) mon2sb; 45 | 46 | //--------------------------------------------- 47 | // Externally defined tasks and functions 48 | //--------------------------------------------- 49 | 50 | extern function new(string name="axi_master_monitor",uvm_component parent); 51 | extern function void build_phase(uvm_phase phase); 52 | extern function void connect_phase(uvm_phase phase); 53 | extern task run_phase(uvm_phase phase); 54 | extern task write_add_xtn(); 55 | extern task write_data_xtn(); 56 | extern task write_resp_xtn(); 57 | extern task read_add_xtn(); 58 | extern task read_data_xtn(); 59 | 60 | endclass : axi_master_monitor 61 | 62 | //----------------------------------------------------------------------------- 63 | // Constructor: new 64 | // Initializes the master_monitor class component 65 | // 66 | // Parameters: 67 | // name - instance name of the config_template 68 | // parent - parent under which this component is created 69 | //----------------------------------------------------------------------------- 70 | function axi_master_monitor:: new(string name="axi_master_monitor",uvm_component parent); 71 | super.new(name,parent); 72 | mon2sb = new("mon2sb",this); 73 | endfunction: new 74 | 75 | //----------------------------------------------------------------------------- 76 | // Function: build_phase 77 | // Creates the required components 78 | // 79 | // Parameters: 80 | // phase - stores the current phase 81 | //----------------------------------------------------------------------------- 82 | function void axi_master_monitor:: build_phase(uvm_phase phase); 83 | super.build_phase(phase); 84 | 85 | m_trans=axi_master_trans::type_id::create("m_trans"); 86 | 87 | if(!uvm_config_db # (virtual axi_if)::get(this,"","vif",vif)) 88 | `uvm_fatal(get_type_name(),$sformatf("not able to get interface in master monitor")) 89 | 90 | endfunction:build_phase 91 | 92 | //----------------------------------------------------------------------------------------------- 93 | // Function: connect_phase 94 | // The connect phase is used to make TLM connections between components 95 | //------------------------------------------------------------------------------------------------ 96 | function void axi_master_monitor::connect_phase(uvm_phase phase); 97 | super.connect_phase(phase); 98 | endfunction:connect_phase 99 | 100 | //----------------------------------------------------------------------------------------------- 101 | //task:run_phase 102 | //The run phase is implemented as a task, and all uvm_component run tasks are executed in parallel. 103 | //------------------------------------------------------------------------------------------------ 104 | task axi_master_monitor::run_phase(uvm_phase phase); 105 | super.run_phase(phase); 106 | fork 107 | write_add_xtn(); 108 | write_data_xtn(); 109 | write_resp_xtn(); 110 | read_add_xtn(); 111 | read_data_xtn(); 112 | join 113 | endtask: run_phase 114 | 115 | ////////////////////////////////////////////////////////////// 116 | //collect write add @posedge 117 | ///////////////////////////////////////////////////////////// 118 | task axi_master_monitor::write_add_xtn(); 119 | axi_master_trans m_trans; 120 | 121 | forever 122 | begin 123 | @(posedge vif.ACLK) 124 | if(vif.m_mon_cb.AWVALID == 1'b1 && vif.m_mon_cb.AWREADY == 1'b1); 125 | begin 126 | m_trans.AWADDR = vif.m_mon_cb.AWADDR; 127 | m_trans.AWID = vif.m_mon_cb.AWID; 128 | m_trans.AWLEN = vif.m_mon_cb.AWLEN; 129 | m_trans.AWSIZE = vif.m_mon_cb.AWSIZE; 130 | m_trans.AWBURST = vif.m_mon_cb.AWBURST; 131 | m_trans.AWLOCK = vif.m_mon_cb.AWLOCK; 132 | m_trans.AWCACHE = vif.m_mon_cb.AWCACHE; 133 | m_trans.AWPROT = vif.m_mon_cb.AWPROT; 134 | end 135 | 136 | `uvm_info(get_type_name(), $sprintf("collected write addr addr : %h, len : %h", m_trans.AWADDR, m_trans.AWLEN), UVM_LOW) 137 | end 138 | endtask : write_add_xtn 139 | 140 | ///////////////////////////////////////////////////////// 141 | //collect write data 142 | ///////////////////////////////////////////////////////// 143 | task axi_master_monitor::write_data_xtn(); 144 | axi_master_trans m_trans; 145 | 146 | forever begin 147 | @(posedge vif.ACLK) 148 | if(vif.m_mon_cb.WVALID == 1'b1 && vif.m_mon_cb.WREADY == 1'b1); 149 | begin 150 | m_trans.WDATA = vif.m_mon_cb.WDATA; 151 | m_trans.WSTRB = vif.m_mon_cb.WSTRB; 152 | end 153 | 154 | `uvm_info(get_type_name(), $sprintf("collected write data data : %h", m_trans.WDATA), UVM_LOW) 155 | end 156 | endtask : write_data_xtn 157 | 158 | 159 | //////////////////////////////////////////////// 160 | //collect write resp 161 | //////////////////////////////////////////////// 162 | task axi_master_monitor::write_resp_xtn(); 163 | axi_master_trans m_trans; 164 | 165 | forever begin 166 | @(posedge vif.ACLK) 167 | if(vif.m_mon_cb.BVALID ==1'b1 && vif.m_mon_cb.BREADY ==1'b1); 168 | begin 169 | m_trans.BRESP = vif.m_mon_cb.BRESP; 170 | end 171 | 172 | // send transfer to scb 173 | mon2sb.write(m_trans); 174 | 175 | end 176 | endtask : write_resp_xtn 177 | 178 | ////////////////////////////////////////////////////////////// 179 | //collect read add @posedge 180 | ///////////////////////////////////////////////////////////// 181 | task axi_master_monitor::read_add_xtn(); 182 | axi_master_trans m_trans; 183 | 184 | forever 185 | begin 186 | @(posedge vif.ACLK) 187 | if(vif.m_mon_cb.ARVALID == 1'b1 && vif.m_mon_cb.ARREADY == 1'b1); 188 | begin 189 | m_trans.ARADDR = vif.m_mon_cb.ARADDR; 190 | m_trans.ARID = vif.m_mon_cb.ARID; 191 | m_trans.ARLEN = vif.m_mon_cb.ARLEN; 192 | m_trans.ARSIZE = vif.m_mon_cb.ARSIZE; 193 | m_trans.ARBURST = vif.m_mon_cb.ARBURST; 194 | m_trans.ARLOCK = vif.m_mon_cb.ARLOCK; 195 | m_trans.ARCACHE = vif.m_mon_cb.ARCACHE; 196 | m_trans.ARPROT = vif.m_mon_cb.ARPROT; 197 | end 198 | 199 | `uvm_info(get_type_name(), $sprintf("collected read addr addr : %h, len : %h", m_trans.ARADDR, m_trans.ARLEN), UVM_LOW) 200 | end 201 | endtask : read_add_xtn 202 | 203 | ///////////////////////////////////////////////////////// 204 | //collect read data & resp 205 | ///////////////////////////////////////////////////////// 206 | task axi_master_monitor::read_data_xtn(); 207 | axi_master_trans m_trans; 208 | 209 | forever begin 210 | @(posedge vif.ACLK) 211 | if(vif.m_mon_cb.RVALID == 1'b1 && vif.m_mon_cb.RREADY == 1'b1); 212 | begin 213 | m_trans.RDATA = vif.m_mon_cb.RDATA; 214 | m_trans.RRESP = vif.m_mon_cb.RRESP; 215 | end 216 | 217 | `uvm_info(get_type_name(), $sprintf("collected read data data : %h", m_trans.RDATA), UVM_LOW) 218 | 219 | // send transfer to scb 220 | mon2sb.write(m_trans); 221 | 222 | end 223 | 224 | endtask : read_data_xtn 225 | 226 | /////////////////////////////////////////////////////////////////////// 227 | `endif 228 | 229 | -------------------------------------------------------------------------------- /axi_tb_files/env/master_coverage.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | `ifndef AXI_MASTER_COVERAGE_SV 23 | `define AXI_MASTER_COVERAGE_SV 24 | 25 | ////////////////////////////////////////// 26 | //Class: axi_master_coverage 27 | //for master axi vip 28 | ///////////////////////////////////////// 29 | class axi_master_coverage extends uvm_subscriber #(axi_master_trans); 30 | 31 | //factory registration 32 | `uvm_component_utils(axi_master_coverage) 33 | 34 | //handle declaration 35 | axi_master_trans item; 36 | 37 | //externally defined task & function 38 | extern function new(string name, uvm_component parent); 39 | extern function void build_phase(uvm_phase phase); 40 | extern function void write(axi_master_trans t); //write method 41 | 42 | 43 | 44 | ////// Coverage for write address channel ///////////////// 45 | 46 | covergroup wr_addr_cg(axi_master_trans item); 47 | option.per_instance = 1; 48 | 49 | //write add coverpoint 50 | WRITEADDR: coverpoint item.AWADDR { 51 | bins awaddr_bin = default; 52 | } 53 | 54 | //WADDR ID coverpoint 55 | WADDR_ID: coverpoint item.AWID { 56 | bins awid_bin[] = {[0:$]}; //all possible values to be covered 57 | } 58 | 59 | //burst length coverpoint 60 | //for fixed burst 61 | AWLEN_FIXED: coverpoint item.AWLEN iff(item.burst_t == FIXED) { 62 | bins awlen_fixed_bin[] = {[0:15]}; 63 | } 64 | 65 | //for incr burst 66 | AWLEN_INCR: coverpoint item.AWLEN iff(item.burst_t == INCR) { 67 | bins awlen_incr_bin[] = {[0:$]}; 68 | } 69 | 70 | //for wrap burst 71 | AWLEN_WRAP: coverpoint item.AWLEN iff(item.burst_t == WRAP) { 72 | bins awlen_wrap_bin[] = {1, 3, 8, 15}; 73 | } 74 | 75 | //burst size coverpoint 76 | BURSTSIZE : coverpoint item.AWSIZE { 77 | bins 1BYTE = {3'b000}; //transfer 1byte per beat 78 | bins 2BYTES = {3'b001}; 79 | bins 4BYTES = {3'b010}; 80 | bins 8BYTES = {3'b011}; 81 | bins 16BYTES = {3'b100}; 82 | bins 32BYTES = {3'b101}; 83 | bins 64BYTES = {3'b110}; 84 | bins 128BYTES = {3'b111}; 85 | } 86 | 87 | //burst type coverpoint 88 | BURSTTYPE : coverpoint item.burst_t.AWBURST { 89 | bins FIXED_bin = {FIXED}; 90 | bins INCR_bin = {INCR}; 91 | bins WRAP_bin = {WRAP}; 92 | illegal_bins resvd_bin = {RESERVED}; 93 | } 94 | 95 | //lock type coverpoint 96 | LOCK: coverpoint item.AWLOCK { 97 | bins NORMAL_ACCESS_bin = {'b0}; 98 | bins EXCLUSIVE_ACCESS_bin = {'b1}; 99 | } 100 | 101 | endgroup: wr_addr_cg 102 | 103 | 104 | //////////////////// Coverage for Write data channel /////////////////// 105 | 106 | covergroup wr_data_cg(axi_master_trans item); 107 | option.per_instance = 1; 108 | 109 | //write data coverpoint 110 | WRITEDATA: coverpoint item.WDATA { 111 | bins wdata_bin = default; 112 | } 113 | 114 | //WDATA ID coverpoint 115 | WDATA_ID: coverpoint item.WID { 116 | bins wid_bin[] = {[0:$]}; //all possible values to be covered 117 | } 118 | 119 | //write strobe coverpoint 120 | WRITESTROBE: coverpoint item.WSTRB { 121 | bins wstrb_bin[] = {[0:$]}; //all possible values to be covered 122 | } 123 | 124 | //write last coverpoint 125 | WRITELAST: coverpoint item.WLAST { 126 | bins wlast_trans_bin = (0 => 1); 127 | } 128 | 129 | endgroup: wr_data_cg 130 | 131 | 132 | /////////////// Coverage for Write response channel //////////////////// 133 | 134 | covergroup wr_resp_cg(axi_master_trans item); 135 | 136 | option.per_instance = 1; 137 | 138 | //write response id coverpoint 139 | WRSP_ID: coverpoint item.BID { 140 | bins bid_bin[] = {[0: $]}; 141 | } 142 | 143 | //write response coverpoint 144 | WRITERESP: coverpoint item.resp_t.BRESP { 145 | bins okay_bin = {OKAY}; 146 | bins EXOKAY_bin = {EXOKAY}; 147 | bins SLVERR_bin = {SLVERR}; 148 | bins DECERR_bin = {DECERR}; 149 | } 150 | 151 | endgroup: wr_resp_cg 152 | 153 | ////////////// Coverage for read address channel /////////////// 154 | 155 | covergroup rd_addr_cg(axi_master_trans item); 156 | 157 | option.per_instance = 1; 158 | 159 | //read address coverpoint 160 | READADDR: coverpoint item.ARADDR { 161 | bins araddr_bin = default; 162 | } 163 | 164 | 165 | //read address id coverpoint 166 | RADDR_ID: coverpoint item.ARID { 167 | bins arid_bin[] = {[0: $]}; 168 | } 169 | 170 | //burst length coverpoint 171 | //for fixed burst 172 | ARLEN_FIXED: coverpoint item.ARLEN iff(item.burst_t == FIXED) { 173 | bins arlen_fixed_bin[] = {[0: 15]}; 174 | } 175 | 176 | //for incr burst 177 | ARLEN_INCR: coverpoint item.ARLEN iff(item.burst_t == INCR) { 178 | bins arlen_incr_bin[] = {[0: $]}; 179 | } 180 | //for wrap burst 181 | ARLEN_WRAP: coverpoint item.ARLEN iff(item.burst_t == WRAP { 182 | bins arlen_wrap_bin[] = {1, 3, 8, 15}; 183 | } 184 | 185 | //read burst type 186 | READBURST: coverpoint item.burst_t.ARBURST { 187 | bins fixed_bin = {FIXED}; 188 | bins incr_bin = {INCR}; 189 | bins wrap_bin = {WRAP}; 190 | illegal_bins reserved_bin = {RESERVED}; 191 | } 192 | 193 | //read burst size 194 | BURSTSIZE : coverpoint item.ARSIZE { 195 | bins 1BYTE = {3'b000}; 196 | bins 2BYTES = {3'b001}; 197 | bins 4BYTES = {3'b010}; 198 | bins 8BYTES = {3'b011}; 199 | bins 16BYTES = {3'b100}; 200 | bins 32BYTES = {3'b101}; 201 | bins 64BYTES = {3'b110}; 202 | bins 128BYTES ={3'b111}; 203 | } 204 | 205 | //read lock type 206 | READLOCK: coverpoint item.ARLOCK { 207 | bins NORMAL_ACCESS_bin = {'b0}; 208 | bins EXCLUSIVE_ACCESS_bin = {'b1}; 209 | } 210 | 211 | endgroup: rd_addr_cg 212 | 213 | //read data channel coverage specification 214 | covergroup rd_data_cg(axi_master_trans item); 215 | 216 | option.per_instance = 1; 217 | 218 | //read data coverpoint 219 | R_DATA : coverpoint item.RDATA{ 220 | bins rdata_bin = default; 221 | } 222 | 223 | 224 | //read last coverpoint 225 | RD_LAST: coverpoint item.RLAST { 226 | bins rlast_trans_bin = (0 => 1); 227 | } 228 | 229 | //read id coverpoint 230 | RD_ID: coverpoint item.RID { 231 | bins rid_bin[] = {[0: $]}; 232 | } 233 | 234 | //read response coverpoint 235 | RD_RESP: coverpoint item.resp_t.RRESP { 236 | bins okay_bin = {OKAY}; 237 | bins EXOKAY_bin = {EXOKAY}; 238 | bins SLVERR_bin = {SLVERR}; 239 | bins DECERR_bin = {DECERR}; 240 | } 241 | 242 | endgroup: rd_data_cg 243 | 244 | 245 | endclass : axi_master_coverage 246 | 247 | 248 | function axi_master_coverage::new(string name, uvm_component parent); 249 | super.new(name, parent); 250 | 251 | wr_addr_cg = new(); 252 | wr_data_cg = new(); 253 | wr_resp_cg = new(); 254 | rd_add_cg = new(); 255 | rd_data_cg = new(); 256 | 257 | endfunction : new 258 | 259 | function void axi_master_coverage::build_phase(uvm_phase phase); 260 | super.build_phase(phase); 261 | endfunction:build_phase 262 | 263 | 264 | ////////// sampling the coverage /////////////////// 265 | 266 | function void axi_master_coverage::write(axi_master_trans t); 267 | `uvm_info(this.get_type_name(), $sformatf("%s", t.convert2string()), UVM_HIGH) 268 | 269 | if(item.AWVALID && item.AWREADY) begin 270 | wr_addr_cg.sample(); 271 | end 272 | 273 | if(item.WVALID && item.WREADY) begin 274 | wr_data_cg.sample(); 275 | end 276 | 277 | if(item.BVALID && item.BREADY) begin 278 | wr_resp_cg.sample(); 279 | end 280 | 281 | if(item.ARVALID && item.ARREADY) begin 282 | rd_addr_cg.sample(); 283 | end 284 | 285 | if(item.RVALID && item.RREADY) begin 286 | rd_data_cg.sample(); 287 | end 288 | 289 | endfunction : write 290 | 291 | -------------------------------------------------------------------------------- /axi_tb_files/axi_master/axi_master_driver.sv: -------------------------------------------------------------------------------- 1 | // ########################################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | // ########################################################################### 21 | 22 | /////////////////////////////////////MASTER_DRIVER////////////////////////////////////////////////////// 23 | 24 | `ifndef AXI_MASTER_DRIVER_INCLUDED 25 | `define AXI_MASTER_DRIVER_INCLUDED 26 | 27 | //------------------------------------------------------------------------------------------------ 28 | //Class: master_driver 29 | //drives signal to dut 30 | //------------------------------------------------------------------------------------------------ 31 | 32 | class axi_master_driver extends uvm_driver #(axi_master_trans); 33 | 34 | //factory registration 35 | `uvm_component_utils(axi_master_driver) 36 | 37 | //handle declaration 38 | virtual axi_if vif; 39 | 40 | //axi_master_trans req; 41 | 42 | //--------------------------------------------- 43 | // Externally defined tasks and functions 44 | //--------------------------------------------- 45 | extern function new(string name="axi_master_driver",uvm_component parent); 46 | extern function void build_phase(uvm_phase phase); 47 | extern function void connect_phase(uvm_phase phase); 48 | 49 | endclass:axi_master_driver 50 | 51 | function axi_master_driver::new(string name="axi_master_driver",uvm_component parent); 52 | super.new(name,parent); 53 | endfunction 54 | 55 | function void axi_master_driver::build_phase(uvm_phase phase); 56 | super.build_phase(phase); 57 | if(!uvm_config_db #(virtual axi_if)::get(this,"","vif",vif)) 58 | begin 59 | `uvm_fatal(get_type_name(),"interface in master driver not found") 60 | end 61 | endfunction 62 | 63 | function void axi_master_driver::connect_phase(uvm_phase phase); 64 | super.connect_phase(phase); 65 | endfunction 66 | 67 | ///////////////////////////////////////// WRITE DRIVER //////////////////////////////////// 68 | 69 | class axi_wr_drvr extends axi_master_driver #(axi_master_trans); 70 | 71 | //factory registration 72 | `uvm_component_utils(axi_wr_drvr) 73 | 74 | axi_master_trans wr_trans; 75 | virtual axi_if vif; 76 | 77 | function new(string name = "axi_wr_drvr",uvm_component parent = null); 78 | super.new(name,parent); 79 | endfunction 80 | 81 | virtual function void build_phase(uvm_phase phase); 82 | begin 83 | if((!uvm_config_db #(virtual axi_if)::get(this," ","vif",vif))) 84 | `uvm_fatal("NOVIF","Virtual interface not found") 85 | 86 | end 87 | endfunction 88 | 89 | virtual task run_phase(uvm_phase phase); 90 | begin 91 | forever 92 | begin 93 | seq_item_port.get_next_item(req); 94 | wr_drive(req); 95 | seq_item_port.finish_item(req); 96 | end 97 | end 98 | endtask 99 | 100 | virtual task wr_drive(axi_master_trans wr_trans); 101 | begin 102 | fork 103 | addr_ch(wr_trans); //Task to drive address on address channel 104 | data_ch(wr_trans); //Task to drive data on write data channel 105 | join_none 106 | end 107 | endtask 108 | 109 | virtual task addr_ch(axi_master_trans wr_trans); //Task to drive address on address channel 110 | begin 111 | @(posedge vif.clk); 112 | begin 113 | if(!vif.reset) //reset condition 114 | begin 115 | vif.AWADDR <= 0; 116 | vif.AWVALID <= 0; 117 | vif.AWSIZE <= 0; 118 | vif.AWLEN <= 0; 119 | vif.AWBURST <= 0; 120 | vif.AWCACHE <= 0; 121 | vif.AWID <= 0; 122 | vif.AWLOCK <= 0; 123 | end 124 | 125 | else 126 | begin 127 | for(int r=0;r<(wr_trans.AWLEN.size());r++) 128 | begin 129 | vif.AWADDR <= wr_trans.AWADDR[r]; 130 | vif.AWVALID <= 1; 131 | vif.AWSIZE <= wr_trans.AWSIZE; 132 | vif.AWLEN <= wr_trans.AWLEN[r]; 133 | vif.AWBURST <= wr_trans.AWBURST; 134 | vif.AWCACHE <= wr_trans.AWCACHE; 135 | vif.AWID <= wr_trans.AWID[r]; 136 | vif.AWLOCK <= wr_trans.AWLOCK; 137 | wait(vif.AWREADY == 1); 138 | @(posedge vif.clk); 139 | end 140 | end 141 | end 142 | end 143 | endtask 144 | 145 | virtual task data_ch(axi_master_trans wr_trans); //Task to drive write data on data channel 146 | begin 147 | @(posedge vif.clk); 148 | begin 149 | if(!vif.reset) //reset condition 150 | begin 151 | vif.WDATA <= 0; 152 | vif.WVALID <= 0; 153 | vif.WSTRB <= 0; 154 | vif.WLAST <= 0; 155 | vif.BREADY <= 0; 156 | end 157 | 158 | else 159 | begin 160 | for(int r=0;r<(wr_trans.AWLEN.size());r++) 161 | begin 162 | if(AWLEN[r] == 0) //For single write 163 | begin 164 | vif.WDATA <= wr_trans.WDATA[r]; 165 | vif.WVALID <= 1; 166 | vif.WSTRB <= wr_trans.WSTRB[r]; 167 | wait(vif.WREADY == 1); 168 | end 169 | 170 | else //For burst write 171 | begin 172 | vif.WVALID <= 1; 173 | for(int f=0;f ##1 AWVALID; 101 | endproperty 102 | Write_Address_Valid_Ready: assert property (write_address); 103 | 104 | //Write_data (Handshake Signal) 105 | property write_data; 106 | @(posedge ACLK) disable iff (ARESETn) 107 | (WVALID && (!WREADY)) |-> ##1 WVALID; 108 | endproperty 109 | Write_Data_Valid_Ready: assert property (write_data); 110 | 111 | //Write_response (Handshake Signal) 112 | property write_response; 113 | @(posedge ACLK) disable iff (ARESETn) 114 | (BVALID && (!BREADY)) |-> ##1 BVALID; 115 | endproperty 116 | Write_Response_Valid_Ready: assert property (write_response); 117 | 118 | //Read_address (Handshake Signal) 119 | property read_address; 120 | @(posedge ACLK) disable iff (ARESETn) 121 | (ARVALID && (!ARREADY)) |-> ##1 ARVALID; 122 | endproperty 123 | Read_Address_Valid_Ready: assert property (read_address); 124 | 125 | //Read_data (Handshake Signal) 126 | property read_data; 127 | @(posedge ACLK) disable iff (ARESETn) 128 | (RVALID && (!RREADY)) |-> ##1 RVALID; 129 | endproperty 130 | Read_Data_Valid_Ready: assert property (read_data); 131 | 132 | 133 | 134 | /////////////////////////////////////////////////////////////////////////////////// 135 | WRITE ADDRESS CHANNEL 136 | ////////////////////////////////////////////////////////////////////////////////// 137 | 138 | // Following signal should not x or z when AWVALID is high 139 | 140 | AWID_X: assert property (@(posedge ACLK) AWVALID |-> (!$isunknown(AWID))); 141 | 142 | AWADDR_X: assert property (@(posedge ACLK) AWVALID |-> (!$isunknown(AWADDR))); 143 | 144 | AWLEN_X: assert property (@(posedge ACLK) AWVALID |-> (!$isunknown(AWLEN))); 145 | 146 | AWSIZE_X: assert property (@(posedge ACLK) AWVALID |-> (!$isunknown(AWSIZE))); 147 | 148 | AWBURST_X: assert property (@(posedge ACLK) AWVALID |-> (!$isunknown(AWBURST))); 149 | 150 | AWLOCK_X: assert property (@(posedge ACLK) AWVALID |-> (!$isunknown(AWLOCK))); 151 | 152 | AWCACHE_X: assert property (@(posedge ACLK) AWVALID |-> (!$isunknown(AWCACHE))); 153 | 154 | AWPROT_X: assert property (@(posedge ACLK) AWVALID |-> (!$isunknown(AWPROT))); 155 | 156 | //Following signals remain stable when AWVALID is asserted and AWREADY is LOW 157 | 158 | property writeaddr_stable; 159 | @(posedge ACLK) disable iff (ARESETn) 160 | (AWVALID && !AWREADY) |-> 161 | ##1 (AWADDR == $past(AWADDR)); 162 | endproperty 163 | AWADDR_STABLE: assert property (writeaddr_stable); 164 | 165 | property writeburstlength_stable; 166 | @(posedge ACLK) disable iff (ARESETn) 167 | (AWVALID && !AWREADY) |-> 168 | ##1 (AWLEN == $past(AWLEN)); 169 | endproperty 170 | AWLEN_STABLE: assert property (burstlength_stable); 171 | 172 | property writelock_stable; 173 | @(posedge ACLK) disable iff (ARESETn) 174 | (AWVALID && !AWREADY) |-> 175 | ##1 (AWLOCK == $past(AWLOCK)); 176 | endproperty 177 | AWLOCK_STABLE: assert property (writelock_stable); 178 | 179 | property writememory_stable; 180 | @(posedge ACLK) disable iff (ARESETn) 181 | (AWVALID && !AWREADY) |-> 182 | ##1 (AWCACHE == $past(AWCACHE)); 183 | endproperty 184 | AWCACHE_STABLE: assert property (writememory_stable); 185 | 186 | property writeprot_stable; 187 | @(posedge ACLK) disable iff (ARESETn) 188 | (AWVALID && !AWREADY) |-> 189 | ##1 (AWPROT == $past(AWPROT)); 190 | endproperty 191 | AWPROT_STABLE: assert property (writeprot_stable); 192 | 193 | property writeaddID_stable; 194 | @(posedge ACLK) disable iff (ARESETn) 195 | (AWVALID && !AWREADY) |-> 196 | ##1 (AWID == $past(AWID)); 197 | endproperty 198 | AWID_STABLE: assert property (writeaddID_stable); 199 | 200 | property writeburstsize_stable; 201 | @(posedge ACLK) disable iff (ARESETn) 202 | (AWVALID && !AWREADY) |-> 203 | ##1 (AWSIZE == $past(AWSIZE)); 204 | endproperty 205 | AWSIZE_STABLE: assert property (writeburstsize_stable); 206 | 207 | property writebursttype_stable; 208 | @(posedge ACLK) disable iff (ARESETn) 209 | (AWVALID && !AWREADY) |-> 210 | ##1 (AWBURST == $past(AWBURST)); 211 | endproperty 212 | AWBURST_STABLE: assert property (writebursttype_stable); 213 | 214 | // Write Burst Type can’t be 2’b11 as it is reserved 215 | property writeburst_reserved; 216 | @(posedge ACLK) disable iff(ARESETn) 217 | AWVALID |-> (AWBURST !=2’b11); 218 | endproperty 219 | AWBURST_RESVD: assert property (writeburst_reserved); 220 | 221 | 222 | //////////////////////////////////////////////////////////////////////////////////////// 223 | WRITE DATA CHANNEL 224 | ///////////////////////////////////////////////////////////////////////////////////// 225 | 226 | //Following signal remain stable when WVALID is asserted and WREADY is LOW 227 | 228 | property writedata_stable; 229 | @(posedge ACLK) disable iff(ARESETn) 230 | (WVALID && !WREADY) |-> $stable(WDATA); 231 | endproperty 232 | WDATA_STABLE:assert property(writedata_stable) 233 | 234 | 235 | property writestrobe_stable; 236 | @(posedge ACLK) disable iff(ARESETn) 237 | (WVALID && !WREADY) |-> $stable(WSTRB); 238 | endproperty 239 | WSTRB_STABLE:assert property(writestrobe_stable) 240 | 241 | 242 | property writelast_stable; 243 | @(posedge ACLK) disable iff(ARESETn) 244 | (WVALID && !WREADY) |-> $stable(WLAST); 245 | endproperty 246 | WLAST_STABLE:assert property(writelast_stable) 247 | 248 | // When WVALID is HIGH, value of X on following signal is not permitted 249 | 250 | WDATA_X: assert property (@(posedge ACLK) WVALID |-> (!$isunknown(WDATA))); 251 | 252 | WSTRB_X: assert property (@(posedge ACLK) WVALID |-> (!$isunknown(WSTRB))); 253 | 254 | WLAST_X: assert property (@(posedge ACLK) WVALID |-> (!$isunknown(WLAST))); 255 | 256 | 257 | //////////////////////////////////////////////////////////////////////// 258 | WRITE RESPONSE CHANNEL 259 | /////////////////////////////////////////////////////////////////////// 260 | 261 | // Following signal remain stable when BVALID is asserted and BREADY is LOW 262 | 263 | property writeresponse_stable; 264 | @(posedge ACLK) disable iff(ARESETn) 265 | (BVALID && !BREADY) |-> $stable(BRESP); 266 | endproperty 267 | BRESP_STABLE:assert property(writeresponse_stable) 268 | 269 | 270 | property writeresponseID_stable; 271 | @(posedge ACLK) disable iff(ARESETn) 272 | (BVALID && !BREADY) |-> $stable(BID); 273 | endproperty 274 | BID_STABLE:assert property(writeresponseID_stable) 275 | 276 | // When BVALID is HIGH, value of X on following signal is not permitted 277 | 278 | BID_X: assert property (@(posedge ACLK) BVALID |-> (!$isunknown(BID))); 279 | 280 | BRESP_X: assert property (@(posedge ACLK) BVALID |-> (!$isunknown(BRESP))); 281 | 282 | 283 | ///////////////////////////////////////////////////////////////////////////////// 284 | READ ADDRESS CHANNEL 285 | /////////////////////////////////////////////////////////////////////////////// 286 | 287 | // Following signal remain stable when BVALID is asserted and BREADY is LOW 288 | 289 | property readaddID_stable; 290 | @(posedge ACLK) disable iff(ARESETn) 291 | (ARVALID && !ARREADY) |-> $stable(ARID); 292 | endproperty 293 | ARID_STABLE:assert property(readaddID_stable) 294 | 295 | property readadd_stable; 296 | @(posedge ACLK) disable iff(ARESETn) 297 | (ARVALID && !ARREADY) |-> $stable(ARADDR); 298 | endproperty 299 | ARADDR_STABLE:assert property(readadd_stable) 300 | 301 | property readburstlength_stable; 302 | @(posedge ACLK) disable iff(ARESETn) 303 | (ARVALID && !ARREADY) |-> $stable(ARLEN); 304 | endproperty 305 | ARLEN_STABLE:assert property(readburstlength_stable) 306 | 307 | property readburstsize_stable; 308 | @(posedge ACLK) disable iff(ARESETn) 309 | (ARVALID && !ARREADY) |-> $stable(ARSIZE); 310 | endproperty 311 | ARSIZE_STABLE:assert property(readburstsize_stable) 312 | 313 | property readbursttype_stable; 314 | @(posedge ACLK) disable iff(ARESETn) 315 | (ARVALID && !ARREADY) |-> $stable(ARBURST); 316 | endproperty 317 | ARBURST_STABLE:assert property(readbursttype_stable) 318 | 319 | 320 | property readlock_stable; 321 | @(posedge ACLK) disable iff(ARESETn) 322 | (ARVALID && !ARREADY) |-> $stable(ARLOCK); 323 | endproperty 324 | ARLOCK_STABLE:assert property(readlock_stable) 325 | 326 | property readmem_stable; 327 | @(posedge ACLK) disable iff(ARESETn) 328 | (ARVALID && !ARREADY) |-> $stable(ARCACHE); 329 | endproperty 330 | ARCACHE_STABLE:assert property(readmem_stable) 331 | 332 | 333 | property readprot_stable; 334 | @(posedge ACLK) disable iff(ARESETn) 335 | (ARVALID && !ARREADY) |-> $stable(ARPROT); 336 | endproperty 337 | ARPROT_STABLE:assert property(readprot_stable) 338 | 339 | 340 | // When ARVALID is HIGH, value of X on following signal is not permitted 341 | 342 | ARID_X: assert property (@(posedge ACLK) ARVALID |-> (!$isunknown(ARID))); 343 | 344 | ARDDR_X: assert property (@(posedge ACLK) ARVALID |-> (!$isunknown(ARDDR))); 345 | 346 | ARLEN_X: assert property (@(posedge ACLK) ARVALID |-> (!$isunknown(ARLEN))); 347 | 348 | ARSIZE_X: assert property (@(posedge ACLK) ARVALID |-> (!$isunknown(ARSIZE))); 349 | 350 | ARBURST_X: assert property (@(posedge ACLK) ARVALID |-> (!$isunknown(ARBURST))); 351 | 352 | ARLOCK_X: assert property (@(posedge ACLK) ARVALID |-> (!$isunknown(ARLOCK))); 353 | 354 | ARCACHE_X: assert property (@(posedge ACLK) ARVALID |-> (!$isunknown(ARCACHE))); 355 | 356 | ARPROT_X: assert property (@(posedge ACLK) ARVALID |-> (!$isunknown(ARPROT))); 357 | 358 | // Read burst type can’t be reserved 359 | 360 | property readburst_reserved; 361 | @(posedge ACLK) disable iff(ARESETn) 362 | ARVALID |-> (ARBURST !=2’b11); 363 | endproperty 364 | ARBURST_RESVD: assert property (readburst_reserved); 365 | 366 | 367 | ///////////////////////////////////////////////////////////////////////////////////// 368 | READ DATA CHANNEL 369 | ////////////////////////////////////////////////////////////////////////////////// 370 | 371 | // Following signal remain stable when RVALID is asserted and RREADY is LOW 372 | 373 | property readID_stable; 374 | @(posedge ACLK) disable iff(ARESETn) 375 | (RVALID && !RREADY) |-> $stable(RID); 376 | endproperty 377 | RID_STABLE:assert property(readID_stable) 378 | 379 | 380 | property readdata_stable; 381 | @(posedge ACLK) disable iff(ARESETn) 382 | (RVALID && !RREADY) |-> $stable(RDATA); 383 | endproperty 384 | RDATA_STABLE:assert property(readdata_stable) 385 | 386 | 387 | property readresp_stable; 388 | @(posedge ACLK) disable iff(ARESETn) 389 | (RVALID && !RREADY) |-> $stable(RRESP); 390 | endproperty 391 | RRESP_STABLE:assert property(readresp_stable) 392 | 393 | property readlast_stable; 394 | @(posedge ACLK) disable iff(ARESETn) 395 | (RVALID && !RREADY) |-> $stable(RLAST); 396 | endproperty 397 | RLAST_STABLE:assert property(readlast_stable) 398 | 399 | 400 | // When RVALID is HIGH, value of X on following signal is not permitted 401 | 402 | RID_X: assert property (@(posedge ACLK) RVALID |-> (!$isunknown(RID))); 403 | 404 | 405 | RDATA_X: assert property (@(posedge ACLK) RVALID |-> (!$isunknown(RDATA))); 406 | 407 | 408 | RRESP_X: assert property (@(posedge ACLK) RVALID |-> (!$isunknown(RRESP))); 409 | 410 | 411 | RLAST_X: assert property (@(posedge ACLK) RVALID |-> (!$isunknown(RLAST))); 412 | 413 | endmodule 414 | 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | 424 | 425 | 426 | 427 | 428 | 429 | 430 | 431 | 432 | 433 | 434 | 435 | 436 | --------------------------------------------------------------------------------