├── OpenMIPS.runs ├── impl_1 │ ├── .vivado.end.rst │ ├── .init_design.end.rst │ ├── .opt_design.end.rst │ ├── .place_design.end.rst │ ├── .route_design.end.rst │ ├── .write_bitstream.end.rst │ ├── .Vivado_Implementation.queue.rst │ ├── vivado.pb │ ├── init_design.pb │ ├── opt_design.pb │ ├── place_design.pb │ ├── route_design.pb │ ├── write_bitstream.pb │ ├── openmips_min_sopc.bin │ ├── openmips_min_sopc.bit │ ├── openmips_min_sopc_opt.dcp │ ├── openmips_min_sopc_placed.dcp │ ├── openmips_min_sopc_routed.dcp │ ├── openmips_min_sopc_drc_routed.pb │ ├── openmips_min_sopc_route_status.pb │ ├── openmips_min_sopc_utilization_placed.pb │ ├── openmips_min_sopc_power_summary_routed.pb │ ├── openmips_min_sopc_timing_summary_routed.rpx │ ├── .init_design.begin.rst │ ├── .opt_design.begin.rst │ ├── .place_design.begin.rst │ ├── .route_design.begin.rst │ ├── .write_bitstream.begin.rst │ ├── runme.bat │ ├── .vivado.begin.rst │ ├── htr.txt │ ├── openmips_min_sopc_route_status.rpt │ ├── vivado.jou │ ├── vivado_4884.backup.jou │ ├── vivado_7428.backup.jou │ ├── vivado_8516.backup.jou │ ├── runme.sh │ ├── rundef.js │ ├── ISEWrap.sh │ ├── project.wdf │ ├── openmips_min_sopc.tcl │ ├── openmips_min_sopc_control_sets_placed.rpt │ ├── openmips_min_sopc_timing_summary_routed.rpt │ ├── ISEWrap.js │ ├── openmips_min_sopc_clock_utilization_routed.rpt │ ├── openmips_min_sopc_drc_opted.rpt │ └── openmips_min_sopc_drc_routed.rpt ├── synth_1 │ ├── .vivado.end.rst │ ├── .Vivado_Synthesis.queue.rst │ ├── vivado.pb │ ├── openmips_min_sopc.dcp │ ├── openmips_min_sopc_utilization_synth.pb │ ├── .vivado.begin.rst │ ├── runme.bat │ ├── htr.txt │ ├── vivado.jou │ ├── runme.sh │ ├── rundef.js │ ├── ISEWrap.sh │ ├── project.wdf │ ├── openmips_min_sopc.tcl │ ├── .Xil │ │ └── openmips_min_sopc_propImpl.xdc │ ├── gen_run.xml │ ├── openmips_min_sopc_utilization_synth.rpt │ └── ISEWrap.js └── .jobs │ ├── vrs_config_1.xml │ ├── vrs_config_2.xml │ ├── vrs_config_7.xml │ ├── vrs_config_8.xml │ ├── vrs_config_3.xml │ ├── vrs_config_9.xml │ ├── vrs_config_10.xml │ ├── vrs_config_5.xml │ ├── vrs_config_6.xml │ └── vrs_config_4.xml ├── OpenMIPS.sim └── sim_1 │ └── behav │ ├── xsim.dir │ ├── xsim.svtype │ ├── openmips_min_sopc_tb_behav │ │ ├── xsimcrash.log │ │ ├── xsim.type │ │ ├── TempBreakPointFile.txt │ │ ├── webtalk │ │ │ ├── .xsim_webtallk.info │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ └── usage_statistics_ext_xsim.html │ │ ├── xsim.dbg │ │ ├── xsim.mem │ │ ├── xsim.reloc │ │ ├── xsim.rtti │ │ ├── xsim.xdbg │ │ ├── xsimk.exe │ │ ├── xsim.svtype │ │ ├── Compile_Options.txt │ │ └── xsimkernel.log │ └── xil_defaultlib │ │ ├── div.sdb │ │ ├── ex.sdb │ │ ├── id.sdb │ │ ├── mem.sdb │ │ ├── ctrl.sdb │ │ ├── glbl.sdb │ │ ├── id_ex.sdb │ │ ├── if_id.sdb │ │ ├── clk_div.sdb │ │ ├── cp0_reg.sdb │ │ ├── data_ram.sdb │ │ ├── ex_mem.sdb │ │ ├── hilo_reg.sdb │ │ ├── inst_rom.sdb │ │ ├── mem_wb.sdb │ │ ├── openmips.sdb │ │ ├── pc_reg.sdb │ │ ├── regfile.sdb │ │ ├── @l@lbit_reg.sdb │ │ ├── regfile_display.sdb │ │ ├── openmips_min_sopc.sdb │ │ └── openmips_min_sopc_tb.sdb │ ├── simulate.log │ ├── xelab.pb │ ├── xvlog.pb │ ├── openmips_min_sopc_tb_behav.wdb │ ├── simulate.bat │ ├── compile.bat │ ├── elaborate.bat │ ├── openmips_min_sopc_tb.tcl │ ├── webtalk.jou │ ├── webtalk_6324.backup.jou │ ├── webtalk.log │ ├── webtalk_6324.backup.log │ ├── elaborate.log │ ├── glbl.v │ ├── openmips_min_sopc_tb_vlog.prj │ ├── compile.log │ └── xvlog.log ├── README.md ├── OpenMIPS.cache └── wt │ ├── synthesis_details.wdf │ ├── project.wpc │ ├── xsim.wdf │ ├── java_command_handlers.wdf │ ├── webtalk_pa.xml │ └── synthesis.wdf ├── OpenMIPS.ip_user_files └── README.txt ├── OpenMIPS.hw ├── OpenMIPS.lpr └── hw_1 │ └── hw.xml └── OpenMIPS.srcs └── sources_1 └── new ├── hilo_reg.v ├── LLbit_reg.v ├── if_id.v ├── pc_reg.v ├── regfile.v ├── ctrl.v ├── mem_wb.v ├── id_ex.v ├── ex_mem.v ├── wishbone_bus_if.v ├── div.v └── cp0_reg.v /OpenMIPS.runs/impl_1/.vivado.end.rst: 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/OpenMIPS.runs/.jobs/vrs_config_9.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /OpenMIPS.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /OpenMIPS.runs/.jobs/vrs_config_10.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /OpenMIPS.runs/.jobs/vrs_config_5.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /OpenMIPS.runs/.jobs/vrs_config_6.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /OpenMIPS.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:30:00:00 3 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:30:00:00 4 | eof:1674657513 5 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "bc1267a011e3447b9e44d7f1aa7d39ff" --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "openmips_min_sopc_tb_behav" "xil_defaultlib.openmips_min_sopc_tb" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /OpenMIPS.hw/OpenMIPS.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | set xv_path=D:\\Xilinx\\Vivado\\2015.4\\bin 3 | call %xv_path%/xsim openmips_min_sopc_tb_behav -key {Behavioral:sim_1:Functional:openmips_min_sopc_tb} -tclbatch openmips_min_sopc_tb.tcl -log simulate.log 4 | if "%errorlevel%"=="0" goto SUCCESS 5 | if "%errorlevel%"=="1" goto END 6 | :END 7 | exit 1 8 | :SUCCESS 9 | exit 0 10 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | set xv_path=D:\\Xilinx\\Vivado\\2015.4\\bin 3 | echo "xvlog -m64 --relax -prj openmips_min_sopc_tb_vlog.prj" 4 | call %xv_path%/xvlog -m64 --relax -prj openmips_min_sopc_tb_vlog.prj -log xvlog.log 5 | call type xvlog.log > compile.log 6 | if "%errorlevel%"=="1" goto END 7 | if "%errorlevel%"=="0" goto SUCCESS 8 | :END 9 | exit 1 10 | :SUCCESS 11 | exit 0 12 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/openmips_min_sopc_tb_behav/xsimk.exe -simmode gui -wdb openmips_min_sopc_tb_behav.wdb -simrunnum 0 -socket 16861 2 | Design successfully loaded 3 | Design Loading Memory Usage: 21076 KB (Peak: 21076 KB) 4 | Design Loading CPU Usage: 202 ms 5 | Simulation completed 6 | Simulation Memory Usage: 23096 KB (Peak: 23096 KB) 7 | Simulation CPU Usage: 374 ms 8 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log openmips_min_sopc.vds -m64 -mode batch -messageDb vivado.pb -notrace -source openmips_min_sopc.tcl 10 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log openmips_min_sopc.vdi -applog -m64 -messageDb vivado.pb -mode batch -source openmips_min_sopc.tcl -notrace 10 | -------------------------------------------------------------------------------- /OpenMIPS.runs/.jobs/vrs_config_4.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | set xv_path=D:\\Xilinx\\Vivado\\2015.4\\bin 3 | call %xv_path%/xelab -wto bc1267a011e3447b9e44d7f1aa7d39ff -m64 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot openmips_min_sopc_tb_behav xil_defaultlib.openmips_min_sopc_tb xil_defaultlib.glbl -log elaborate.log 4 | if "%errorlevel%"=="0" goto SUCCESS 5 | if "%errorlevel%"=="1" goto END 6 | :END 7 | exit 1 8 | :SUCCESS 9 | exit 0 10 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/openmips_min_sopc_tb.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/openmips_min_sopc_route_status.rpt: -------------------------------------------------------------------------------- 1 | Design Route Status 2 | : # nets : 3 | ------------------------------------------- : ----------- : 4 | # of logical nets.......................... : 3486 : 5 | # of nets not needing routing.......... : 992 : 6 | # of internally routed nets........ : 943 : 7 | # of nets with no loads............ : 49 : 8 | # of routable nets..................... : 2494 : 9 | # of fully routed nets............. : 2494 : 10 | # of nets with routing errors.......... : 0 : 11 | ------------------------------------------- : ----------- : 12 | 13 | -------------------------------------------------------------------------------- /OpenMIPS.hw/hw_1/hw.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Tue May 10 14:23:30 2016 6 | # Process ID: 6300 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/synth_1 8 | # Command line: vivado.exe -log openmips_min_sopc.vds -mode batch -messageDb vivado.pb -notrace -source openmips_min_sopc.tcl 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/synth_1/openmips_min_sopc.vds 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source openmips_min_sopc.tcl -notrace 13 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Tue May 10 14:31:12 2016 6 | # Process ID: 7788 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1 8 | # Command line: vivado.exe -log openmips_min_sopc.vdi -applog -messageDb vivado.pb -mode batch -source openmips_min_sopc.tcl -notrace 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1/openmips_min_sopc.vdi 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source openmips_min_sopc.tcl -notrace 13 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/vivado_4884.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Sun Apr 24 16:48:36 2016 6 | # Process ID: 4884 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1 8 | # Command line: vivado.exe -log openmips_min_sopc.vdi -applog -messageDb vivado.pb -mode batch -source openmips_min_sopc.tcl -notrace 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1/openmips_min_sopc.vdi 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source openmips_min_sopc.tcl -notrace 13 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/vivado_7428.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Tue May 10 14:27:40 2016 6 | # Process ID: 7428 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1 8 | # Command line: vivado.exe -log openmips_min_sopc.vdi -applog -messageDb vivado.pb -mode batch -source openmips_min_sopc.tcl -notrace 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1/openmips_min_sopc.vdi 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source openmips_min_sopc.tcl -notrace 13 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/vivado_8516.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Sun Apr 24 16:51:05 2016 6 | # Process ID: 8516 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1 8 | # Command line: vivado.exe -log openmips_min_sopc.vdi -applog -messageDb vivado.pb -mode batch -source openmips_min_sopc.tcl -notrace 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1/openmips_min_sopc.vdi 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source openmips_min_sopc.tcl -notrace 13 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/hilo_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 特殊寄存器HI、LO模块 4 | //****************************************************************************** 5 | 6 | `include "defines.v" 7 | 8 | module hilo_reg( 9 | input wire rst, 10 | input wire clk, 11 | 12 | //写端口 13 | input wire we, 14 | input wire[`RegBus] hi_i, 15 | input wire[`RegBus] lo_i, 16 | 17 | //读端口 18 | output reg[`RegBus] hi_o, 19 | output reg[`RegBus] lo_o 20 | ); 21 | 22 | always @ ( posedge clk ) begin 23 | if(rst == `RstEnable) begin 24 | hi_o <= `ZeroWord; 25 | lo_o <= `ZeroWord; 26 | end else if(we == `WriteEnable) begin 27 | hi_o <= hi_i; 28 | lo_o <= lo_i; 29 | end 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/LLbit_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // LLbit寄存器 4 | //****************************************************************************** 5 | 6 | `include "defines.v" 7 | 8 | module LLbit_reg( 9 | input wire rst, 10 | input wire clk, 11 | input wire flush, //异常是否发生，为1表示异常发生，为0表示没有异常 12 | input wire we, //是否要写LLbit寄存器 13 | input wire LLbit_i, //要写到LLbit寄存器的值 14 | output reg LLbit_o //读端口(LLbit值旁路返回到MEM模块) 15 | ); 16 | 17 | always @ ( posedge clk ) begin 18 | if(rst == `RstEnable) begin 19 | LLbit_o <= 1'b0; 20 | end else if(flush == 1'b1) begin //如果异常发生，设置LLbit_o为0 21 | LLbit_o <= 1'b0; 22 | end else if(we == `WriteEnable) begin 23 | LLbit_o <= LLbit_i; 24 | end 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Wed May 18 22:01:08 2016 6 | # Process ID: 2476 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/webtalk.log 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/webtalk_6324.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Wed May 18 21:54:43 2016 6 | # Process ID: 6324 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/webtalk.log 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Wed May 18 22:01:08 2016 6 | # Process ID: 2476 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/webtalk.log 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Wed May 18 22:01:08 2016... 14 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/webtalk_6324.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2015.4 (64-bit) 3 | # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 4 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 5 | # Start of session at: Wed May 18 21:54:43 2016 6 | # Process ID: 6324 7 | # Current directory: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/webtalk.log 10 | # Journal file: C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Wed May 18 21:54:46 2016... 14 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Xilinx/SDK/2015.4/bin;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2015.4/bin 15 | else 16 | PATH=D:/Xilinx/SDK/2015.4/bin;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2015.4/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log openmips_min_sopc.vds -m64 -mode batch -messageDb vivado.pb -notrace -source openmips_min_sopc.tcl 44 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Xilinx/SDK/2015.4/bin;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2015.4/bin 15 | else 16 | PATH=D:/Xilinx/SDK/2015.4/bin;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2015.4/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.runs/impl_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | # pre-commands: 44 | /bin/touch .write_bitstream.begin.rst 45 | EAStep vivado -log openmips_min_sopc.vdi -applog -m64 -messageDb vivado.pb -mode batch -source openmips_min_sopc.tcl -notrace 46 | 47 | 48 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Xilinx/SDK/2015.4/bin;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2015.4/bin;"; 12 | } else { 13 | PathVal = "D:/Xilinx/SDK/2015.4/bin;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2015.4/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log openmips_min_sopc.vds -m64 -mode batch -messageDb vivado.pb -notrace -source openmips_min_sopc.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Xilinx/SDK/2015.4/bin;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2015.4/bin;"; 12 | } else { 13 | PathVal = "D:/Xilinx/SDK/2015.4/bin;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2015.4/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2015.4/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | // pre-commands: 26 | ISETouchFile( "write_bitstream", "begin" ); 27 | ISEStep( "vivado", 28 | "-log openmips_min_sopc.vdi -applog -m64 -messageDb vivado.pb -mode batch -source openmips_min_sopc.tcl -notrace" ); 29 | 30 | 31 | 32 | 33 | 34 | function EAInclude( EAInclFilename ) { 35 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 36 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 37 | var EAIFContents = EAInclFile.ReadAll(); 38 | EAInclFile.Close(); 39 | return EAIFContents; 40 | } 41 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/if_id.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 暂时保存取指阶段取得的指令以及对应的指令地址，并在下一个时钟传递到译码阶段 4 | //****************************************************************************** 5 | 6 | `include "defines.v" 7 | 8 | module if_id( 9 | input wire rst, 10 | input wire clk, 11 | 12 | //来自取指阶段的信号 13 | input wire[`InstAddrBus] if_pc, 14 | input wire[`InstBus] if_inst, 15 | 16 | //送往译码阶段的信号 17 | output reg[`InstAddrBus] id_pc, 18 | output reg[`InstBus] id_inst, 19 | 20 | //来自ctrl的控制信号 21 | input wire[5:0] stall, 22 | input wire flush 23 | ); 24 | 25 | always @ ( posedge clk ) begin 26 | if(rst == `RstEnable) begin 27 | id_pc <= `ZeroWord; //复位时pc为0 28 | id_inst <= `ZeroWord; //复位时指令为0 29 | //flush为1表示异常发生，要清除流水线，所以复位id_pc、id_inst寄存器的值 30 | end else if(flush == 1'b1) begin 31 | id_pc <= `ZeroWord; 32 | id_inst <= `ZeroWord; 33 | //当stall[1]为Stop，stall[2]为NoStop时，表示取指阶段暂停，而译码阶段继续， 34 | //所以使用空指令作为下一个周期进入译码阶段的指令 35 | end else if(stall[1] == `Stop && stall[2] == `NoStop) begin 36 | id_pc <= `ZeroWord; 37 | id_inst <= `ZeroWord; 38 | //当stall[1]为NoStop时，取指阶段继续，取得的指令进入译码阶段 39 | end else if(stall[1] == `NoStop) begin 40 | id_pc <= if_pc; 41 | id_inst <= if_inst; 42 | end 43 | //其余情况下(流水线暂停)，保持译码阶段的寄存器id_pc、id_inst不变 44 | end 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /OpenMIPS.cache/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 |
11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
29 | 30 | 31 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2015.4 2 | Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved. 3 | Running: D:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto bc1267a011e3447b9e44d7f1aa7d39ff --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot openmips_min_sopc_tb_behav xil_defaultlib.openmips_min_sopc_tb xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | Completed static elaboration 7 | Starting simulation data flow analysis 8 | Completed simulation data flow analysis 9 | Time Resolution for simulation is 1ps 10 | Compiling module xil_defaultlib.pc_reg 11 | Compiling module xil_defaultlib.if_id 12 | Compiling module xil_defaultlib.id 13 | Compiling module xil_defaultlib.regfile 14 | Compiling module xil_defaultlib.id_ex 15 | Compiling module xil_defaultlib.ex 16 | Compiling module xil_defaultlib.ex_mem 17 | Compiling module xil_defaultlib.mem 18 | Compiling module xil_defaultlib.mem_wb 19 | Compiling module xil_defaultlib.hilo_reg 20 | Compiling module xil_defaultlib.ctrl 21 | Compiling module xil_defaultlib.div 22 | Compiling module xil_defaultlib.LLbit_reg 23 | Compiling module xil_defaultlib.cp0_reg 24 | Compiling module xil_defaultlib.openmips 25 | Compiling module xil_defaultlib.inst_rom 26 | Compiling module xil_defaultlib.data_ram 27 | Compiling module xil_defaultlib.clk_div 28 | Compiling module xil_defaultlib.regfile_display 29 | Compiling module xil_defaultlib.openmips_min_sopc 30 | Compiling module xil_defaultlib.openmips_min_sopc_tb 31 | Compiling module xil_defaultlib.glbl 32 | Built simulation snapshot openmips_min_sopc_tb_behav 33 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | 11 | //-------- STARTUP Globals -------------- 12 | wire GSR; 13 | wire GTS; 14 | wire GWE; 15 | wire PRLD; 16 | tri1 p_up_tmp; 17 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 18 | 19 | wire PROGB_GLBL; 20 | wire CCLKO_GLBL; 21 | wire FCSBO_GLBL; 22 | wire [3:0] DO_GLBL; 23 | wire [3:0] DI_GLBL; 24 | 25 | reg GSR_int; 26 | reg GTS_int; 27 | reg PRLD_int; 28 | 29 | //-------- JTAG Globals -------------- 30 | wire JTAG_TDO_GLBL; 31 | wire JTAG_TCK_GLBL; 32 | wire JTAG_TDI_GLBL; 33 | wire JTAG_TMS_GLBL; 34 | wire JTAG_TRST_GLBL; 35 | 36 | reg JTAG_CAPTURE_GLBL; 37 | reg JTAG_RESET_GLBL; 38 | reg JTAG_SHIFT_GLBL; 39 | reg JTAG_UPDATE_GLBL; 40 | reg JTAG_RUNTEST_GLBL; 41 | 42 | reg JTAG_SEL1_GLBL = 0; 43 | reg JTAG_SEL2_GLBL = 0 ; 44 | reg JTAG_SEL3_GLBL = 0; 45 | reg JTAG_SEL4_GLBL = 0; 46 | 47 | reg JTAG_USER_TDO1_GLBL = 1'bz; 48 | reg JTAG_USER_TDO2_GLBL = 1'bz; 49 | reg JTAG_USER_TDO3_GLBL = 1'bz; 50 | reg JTAG_USER_TDO4_GLBL = 1'bz; 51 | 52 | assign (weak1, weak0) GSR = GSR_int; 53 | assign (weak1, weak0) GTS = GTS_int; 54 | assign (weak1, weak0) PRLD = PRLD_int; 55 | 56 | initial begin 57 | GSR_int = 1'b1; 58 | PRLD_int = 1'b1; 59 | #(ROC_WIDTH) 60 | GSR_int = 1'b0; 61 | PRLD_int = 1'b0; 62 | end 63 | 64 | initial begin 65 | GTS_int = 1'b1; 66 | #(TOC_WIDTH) 67 | GTS_int = 1'b0; 68 | end 69 | 70 | endmodule 71 | `endif 72 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/pc_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 程序计数器PC，给出指令地址 4 | //****************************************************************************** 5 | 6 | `include "defines.v" 7 | 8 | module pc_reg( 9 | input wire rst, //复位信号 10 | input wire clk, //时钟信号 11 | 12 | output reg ce, //指令存储器访问请求信号 13 | output reg[`InstAddrBus] pc, //要读取的指令地址 14 | 15 | //来自控制模块ctrl 16 | input wire[5:0] stall, 17 | input wire flush, //流水线清除信号 18 | input wire[`InstAddrBus] new_pc, //异常处理例程入口地址 19 | 20 | //来自ID模块的信息(转移指令相关) 21 | input wire branch_flag_i, 22 | input wire[`InstAddrBus] branch_target_address_i 23 | ); 24 | 25 | always @ ( posedge clk ) begin 26 | if(rst == `RstEnable) begin 27 | ce <= `ChipDisable; 28 | end else begin 29 | ce <= `ChipEnable; 30 | end 31 | end 32 | 33 | 34 | always @ ( posedge clk ) begin 35 | //指令存储器禁用的时，PC为0 36 | if(ce == `ChipDisable) begin 37 | pc <= 32'h0000_0000; 38 | //指令存储器使能时 39 | end else begin 40 | //输入信号flush为1表示异常发生，将从CTRL模块给出的异常处理例程入口地址 41 | //new_pc处取指执行 42 | if(flush == 1'b1) begin 43 | pc <= new_pc; 44 | //当stall[0]为NoStop时，PC加4或跳转；否则保持PC不变(流水线暂停) 45 | end else if(stall[0] == `NoStop) begin 46 | if(branch_flag_i == `Branch) begin 47 | pc <= branch_target_address_i; 48 | end else begin 49 | pc <= (pc + 32'h4); 50 | end 51 | end//else if(stall[0] == `NoStop) 52 | end//else(ce == `ChipEnable) 53 | end//always 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/ISEWrap.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # ISEWrap.sh: Vivado Runs Script for UNIX 6 | # Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | HD_LOG=$1 10 | shift 11 | 12 | # CHECK for a STOP FILE 13 | if [ -f .stop.rst ] 14 | then 15 | echo "" >> $HD_LOG 16 | echo "*** Halting run - EA reset detected ***" >> $HD_LOG 17 | echo "" >> $HD_LOG 18 | exit 1 19 | fi 20 | 21 | ISE_STEP=$1 22 | shift 23 | 24 | # WRITE STEP HEADER to LOG 25 | echo "" >> $HD_LOG 26 | echo "*** Running $ISE_STEP" >> $HD_LOG 27 | echo " with args $@" >> $HD_LOG 28 | echo "" >> $HD_LOG 29 | 30 | # LAUNCH! 31 | $ISE_STEP "$@" >> $HD_LOG 2>&1 & 32 | 33 | # BEGIN file creation 34 | ISE_PID=$! 35 | if [ X != X$HOSTNAME ] 36 | then 37 | ISE_HOST=$HOSTNAME #bash 38 | else 39 | ISE_HOST=$HOST #csh 40 | fi 41 | ISE_USER=$USER 42 | ISE_BEGINFILE=.$ISE_STEP.begin.rst 43 | /bin/touch $ISE_BEGINFILE 44 | echo "" >> $ISE_BEGINFILE 45 | echo "" >> $ISE_BEGINFILE 46 | echo " " >> $ISE_BEGINFILE 47 | echo " " >> $ISE_BEGINFILE 48 | echo "" >> $ISE_BEGINFILE 49 | 50 | # WAIT for ISEStep to finish 51 | wait $ISE_PID 52 | 53 | # END/ERROR file creation 54 | RETVAL=$? 55 | if [ $RETVAL -eq 0 ] 56 | then 57 | /bin/touch .$ISE_STEP.end.rst 58 | else 59 | /bin/touch .$ISE_STEP.error.rst 60 | fi 61 | 62 | exit $RETVAL 63 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/ISEWrap.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # ISEWrap.sh: Vivado Runs Script for UNIX 6 | # Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | HD_LOG=$1 10 | shift 11 | 12 | # CHECK for a STOP FILE 13 | if [ -f .stop.rst ] 14 | then 15 | echo "" >> $HD_LOG 16 | echo "*** Halting run - EA reset detected ***" >> $HD_LOG 17 | echo "" >> $HD_LOG 18 | exit 1 19 | fi 20 | 21 | ISE_STEP=$1 22 | shift 23 | 24 | # WRITE STEP HEADER to LOG 25 | echo "" >> $HD_LOG 26 | echo "*** Running $ISE_STEP" >> $HD_LOG 27 | echo " with args $@" >> $HD_LOG 28 | echo "" >> $HD_LOG 29 | 30 | # LAUNCH! 31 | $ISE_STEP "$@" >> $HD_LOG 2>&1 & 32 | 33 | # BEGIN file creation 34 | ISE_PID=$! 35 | if [ X != X$HOSTNAME ] 36 | then 37 | ISE_HOST=$HOSTNAME #bash 38 | else 39 | ISE_HOST=$HOST #csh 40 | fi 41 | ISE_USER=$USER 42 | ISE_BEGINFILE=.$ISE_STEP.begin.rst 43 | /bin/touch $ISE_BEGINFILE 44 | echo "" >> $ISE_BEGINFILE 45 | echo "" >> $ISE_BEGINFILE 46 | echo " " >> $ISE_BEGINFILE 47 | echo " " >> $ISE_BEGINFILE 48 | echo "" >> $ISE_BEGINFILE 49 | 50 | # WAIT for ISEStep to finish 51 | wait $ISE_PID 52 | 53 | # END/ERROR file creation 54 | RETVAL=$? 55 | if [ $RETVAL -eq 0 ] 56 | then 57 | /bin/touch .$ISE_STEP.end.rst 58 | else 59 | /bin/touch .$ISE_STEP.error.rst 60 | fi 61 | 62 | exit $RETVAL 63 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/project.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3138:00:00 3 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 5 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:707270726f6a656374:66616c7365:00:00 6 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7265636f6e666967706172746974696f6e636f756e74:30:00:00 7 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7265636f6e6669676d6f64756c65636f756e74:30:00:00 8 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:686470726f6a656374:66616c7365:00:00 9 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:706172746974696f6e636f756e74:30:00:00 10 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 11 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 12 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 13 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 14 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 15 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 16 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 17 | 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6263313236376130313165333434376239653434643766316161376433396666:506172656e742050412070726f6a656374204944:00 18 | eof:3739588895 19 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/project.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3138:00:00 3 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 5 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:707270726f6a656374:66616c7365:00:00 6 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7265636f6e666967706172746974696f6e636f756e74:30:00:00 7 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7265636f6e6669676d6f64756c65636f756e74:30:00:00 8 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:686470726f6a656374:66616c7365:00:00 9 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:706172746974696f6e636f756e74:30:00:00 10 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 11 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 12 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 13 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 14 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 15 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 16 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 17 | 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6263313236376130313165333434376239653434643766316161376433396666:506172656e742050412070726f6a656374204944:00 18 | eof:3739588895 19 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/openmips_min_sopc.tcl: -------------------------------------------------------------------------------- 1 | proc start_step { step } { 2 | set stopFile ".stop.rst" 3 | if {[file isfile .stop.rst]} { 4 | puts "" 5 | puts "*** Halting run - EA reset detected ***" 6 | puts "" 7 | puts "" 8 | return -code error 9 | } 10 | set beginFile ".$step.begin.rst" 11 | set platform "$::tcl_platform(platform)" 12 | set user "$::tcl_platform(user)" 13 | set pid [pid] 14 | set host "" 15 | if { [string equal $platform unix] } { 16 | if { [info exist ::env(HOSTNAME)] } { 17 | set host $::env(HOSTNAME) 18 | } 19 | } else { 20 | if { [info exist ::env(COMPUTERNAME)] } { 21 | set host $::env(COMPUTERNAME) 22 | } 23 | } 24 | set ch [open $beginFile w] 25 | puts $ch "" 26 | puts $ch "" 27 | puts $ch " " 28 | puts $ch " " 29 | puts $ch "" 30 | close $ch 31 | } 32 | 33 | proc end_step { step } { 34 | set endFile ".$step.end.rst" 35 | set ch [open $endFile w] 36 | close $ch 37 | } 38 | 39 | proc step_failed { step } { 40 | set endFile ".$step.error.rst" 41 | set ch [open $endFile w] 42 | close $ch 43 | } 44 | 45 | set_msg_config -id {HDL 9-1061} -limit 100000 46 | set_msg_config -id {HDL 9-1654} -limit 100000 47 | 48 | start_step write_bitstream 49 | set rc [catch { 50 | create_msg_db write_bitstream.pb 51 | set_param simulator.modelsimInstallPath D:/modeltech64_10.4/win64 52 | open_checkpoint openmips_min_sopc_routed.dcp 53 | set_property webtalk.parent_dir C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.cache/wt [current_project] 54 | catch { write_mem_info -force openmips_min_sopc.mmi } 55 | write_bitstream -force openmips_min_sopc.bit -bin_file 56 | catch { write_sysdef -hwdef openmips_min_sopc.hwdef -bitfile openmips_min_sopc.bit -meminfo openmips_min_sopc.mmi -file openmips_min_sopc.sysdef } 57 | close_msg_db -file write_bitstream.pb 58 | } RESULT] 59 | if {$rc} { 60 | step_failed write_bitstream 61 | return -code error $RESULT 62 | } else { 63 | end_step write_bitstream 64 | } 65 | 66 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/openmips_min_sopc.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Synthesis run script generated by Vivado 3 | # 4 | 5 | set_param simulator.modelsimInstallPath D:/modeltech64_10.4/win64 6 | set_msg_config -id {HDL 9-1061} -limit 100000 7 | set_msg_config -id {HDL 9-1654} -limit 100000 8 | create_project -in_memory -part xc7a35ticpg236-1L 9 | 10 | set_param project.compositeFile.enableAutoGeneration 0 11 | set_param synth.vivado.isSynthRun true 12 | set_property webtalk.parent_dir C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.cache/wt [current_project] 13 | set_property parent.project_path C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.xpr [current_project] 14 | set_property default_lib xil_defaultlib [current_project] 15 | set_property target_language Verilog [current_project] 16 | set_property vhdl_version vhdl_2k [current_fileset] 17 | read_verilog -library xil_defaultlib { 18 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v 19 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/id.v 20 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/div.v 21 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ex.v 22 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ctrl.v 23 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/hilo_reg.v 24 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ex_mem.v 25 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/regfile.v 26 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/pc_reg.v 27 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/mem_wb.v 28 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/mem.v 29 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/if_id.v 30 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/id_ex.v 31 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/regfile_display.v 32 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/clk_div.v 33 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/inst_rom.v 34 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/openmips.v 35 | C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/openmips_min_sopc.v 36 | } 37 | read_xdc C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/constrs_1/new/openmips_display.xdc 38 | set_property used_in_implementation false [get_files C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/constrs_1/new/openmips_display.xdc] 39 | 40 | synth_design -top openmips_min_sopc -part xc7a35ticpg236-1L 41 | write_checkpoint -noxdef openmips_min_sopc.dcp 42 | catch { report_utilization -file openmips_min_sopc_utilization_synth.rpt -pb openmips_min_sopc_utilization_synth.pb } 43 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/usage_statistics_ext_xsim.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 |
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44 | 45 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/regfile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 32个32位通用整数寄存器，可以同时进行两个寄存器的读操作和一个寄存器的写操作 4 | //****************************************************************************** 5 | 6 | `include "defines.v" 7 | 8 | module regfile( 9 | input wire rst, 10 | input wire clk, 11 | 12 | //写端口 13 | input wire we, 14 | input wire[`RegAddrBus] waddr, 15 | input wire[`RegBus] wdata, 16 | 17 | //读端口1 18 | input wire re1, 19 | input wire[`RegAddrBus] raddr1, 20 | output reg[`RegBus] rdata1, 21 | 22 | //读端口2 23 | input wire re2, 24 | input wire[`RegAddrBus] raddr2, 25 | output reg[`RegBus] rdata2 26 | ); 27 | 28 | //****************************************************************************** 29 | // 第一段：定义32个32位通用寄存器 30 | //****************************************************************************** 31 | reg[`RegBus] regs[0:`RegNum-1]; 32 | 33 | //****************************************************************************** 34 | // 第二段：写操作(回写阶段也在此) 35 | // MIPS32架构规定$0的值为硬件连线至0，所以不要写入 36 | // 写操作是时序逻辑电路，发生在时钟信号上升沿 37 | //****************************************************************************** 38 | always @ ( posedge clk ) begin 39 | if(rst == `RstDisable) begin 40 | if((we == `WriteEnable) && (waddr != `RegNumLog2'b0)) begin 41 | regs[waddr] <= wdata; 42 | end 43 | end 44 | end 45 | 46 | //****************************************************************************** 47 | // 第三段：读端口1的读操作 48 | // 读寄存器操作是组合逻辑电路，也就是一旦输入的要读取寄存器地址raddr1或者raddr2发生变 49 | // 化，那么会立即给出新地址对应的寄存器的值 50 | //****************************************************************************** 51 | always @ ( * ) begin 52 | if(rst == `RstEnable) begin 53 | rdata1 <= `ZeroWord; 54 | end else if(raddr1 == `RegNumLog2'b0) begin 55 | rdata1 <= `ZeroWord; 56 | //此处解决了相隔两条指令的RAW数据相关 57 | end else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin 58 | rdata1 <= wdata; 59 | end else if(re1 == `ReadEnable) begin 60 | rdata1 <= regs[raddr1]; 61 | end else begin 62 | rdata1 <= `ZeroWord; 63 | end 64 | end 65 | 66 | //****************************************************************************** 67 | // 第四段：读端口2的读操作 68 | //****************************************************************************** 69 | always @ ( * ) begin 70 | if(rst == `RstEnable) begin 71 | rdata2 <= `ZeroWord; 72 | end else if(raddr2 == `RegNumLog2'b0) begin 73 | rdata2 <= `ZeroWord; 74 | //此处解决了相隔两条指令的RAW数据相关 75 | end else if((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `ReadEnable)) begin 76 | rdata2 <= wdata; 77 | end else if(re2 == `ReadEnable) begin 78 | rdata2 <= regs[raddr2]; 79 | end else begin 80 | rdata2 <= `ZeroWord; 81 | end 82 | end 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/xsim.dir/openmips_min_sopc_tb_behav/webtalk/usage_statistics_ext_xsim.html: -------------------------------------------------------------------------------- 1 | Device Usage Statistics Report 2 |

XSIM Usage Report


3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
software_version_and_target_device
date_generatedWed May 18 22:01:06 2016product_versionXSIM v2015.4 (64-bit)
build_version1412921os_platformWIN64
registration_idtool_flowxsim_vivado
betaFALSEroute_designFALSE
target_familynot_applicabletarget_devicenot_applicable
target_packagenot_applicabletarget_speednot_applicable
random_id8e4a189b77585e628e39afbd00ea1ca7project_idbc1267a011e3447b9e44d7f1aa7d39ff
project_iteration2

21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 |
user_environment
os_nameMicrosoft Windows 7 , 64-bitos_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHzcpu_speed2194 MHz
total_processors1system_ram4.000 GB

30 | 31 | 32 |
vivado_usage

33 | 34 | 35 | 41 | 51 |
xsim
36 | 37 | 38 | 39 |
command_line_options
command=xsim
40 |
42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 |
usage
trace_waveform=trueruntime=1 usiteration=1simulation_time=0.37_sec
simulation_memory=23096_KB
50 |

52 | 53 | 54 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/.Xil/openmips_min_sopc_propImpl.xdc: -------------------------------------------------------------------------------- 1 | set_property SRC_FILE_INFO {cfile:C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/constrs_1/new/openmips_display.xdc rfile:../../../OpenMIPS.srcs/constrs_1/new/openmips_display.xdc id:1} [current_design] 2 | set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] 3 | set_property PACKAGE_PIN W7 [get_ports {disp_a_to_g[0]}] 4 | set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] 5 | set_property PACKAGE_PIN W6 [get_ports {disp_a_to_g[1]}] 6 | set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] 7 | set_property PACKAGE_PIN U8 [get_ports {disp_a_to_g[2]}] 8 | set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] 9 | set_property PACKAGE_PIN V8 [get_ports {disp_a_to_g[3]}] 10 | set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] 11 | set_property PACKAGE_PIN U5 [get_ports {disp_a_to_g[4]}] 12 | set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] 13 | set_property PACKAGE_PIN V5 [get_ports {disp_a_to_g[5]}] 14 | set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] 15 | set_property PACKAGE_PIN U7 [get_ports {disp_a_to_g[6]}] 16 | set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] 17 | set_property PACKAGE_PIN V7 [get_ports dp] 18 | set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] 19 | set_property PACKAGE_PIN U2 [get_ports {disp_an[0]}] 20 | set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] 21 | set_property PACKAGE_PIN U4 [get_ports {disp_an[1]}] 22 | set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] 23 | set_property PACKAGE_PIN V4 [get_ports {disp_an[2]}] 24 | set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] 25 | set_property PACKAGE_PIN W4 [get_ports {disp_an[3]}] 26 | set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] 27 | set_property PACKAGE_PIN W15 [get_ports {sw[4]}] 28 | set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] 29 | set_property PACKAGE_PIN W17 [get_ports {sw[3]}] 30 | set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] 31 | set_property PACKAGE_PIN W16 [get_ports {sw[2]}] 32 | set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] 33 | set_property PACKAGE_PIN V16 [get_ports {sw[1]}] 34 | set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] 35 | set_property PACKAGE_PIN V17 [get_ports {sw[0]}] 36 | set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] 37 | set_property PACKAGE_PIN W5 [get_ports clk] 38 | set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] 39 | set_property PACKAGE_PIN T17 [get_ports rst] 40 | set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] 41 | set_property PACKAGE_PIN R2 [get_ports sw_HL] 42 | set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] 43 | set_property PACKAGE_PIN T1 [get_ports write] 44 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/ctrl.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 一、实现流水线暂停机制 4 | // 输出信号stall是一个宽度为6的信号 5 | // 1.stall[0]表示取指地址PC是否保持不变，为1表示保持不变 6 | // 2.stall[1]表示流水线取指阶段是否暂停，为1表示暂停 7 | // 3.stall[2]表示流水线译码阶段是否暂停，为1表示暂停 8 | // 4.stall[3]表示流水线执行阶段是否暂停，为1表示暂停 9 | // 5.stall[4]表示流水线访存阶段是否暂停，为1表示暂停 10 | // 6.stall[5]表示流水线取指阶段是否暂停，为1表示暂停 11 | // PC、IF/ID、ID/EX、EX/MEM、MEM/WB五个模块均接收全部六位stall信号 12 | // 二、依据异常类型，给出新的取指地址(异常处理例程入口地址)，同时决定是否要清除 13 | // 流水线 14 | // 15 | //****************************************************************************** 16 | 17 | `include "defines.v" 18 | 19 | module ctrl( 20 | input wire rst, 21 | 22 | //流水线暂停相关 23 | input wire stallreq_from_if, //来自取指阶段的暂停请求 24 | input wire stallreq_from_id, //来自译码阶段的暂停请求 25 | input wire stallreq_from_ex, //来自执行阶段的暂停请求 26 | input wire stallreq_from_mem, //来自访存阶段的暂停请求 27 | 28 | output reg[5:0] stall, 29 | 30 | //异常相关 31 | input wire[31:0] excepttype_i, //最终的异常类型，来自MEM模块 32 | input wire[`RegBus] cp0_epc_i, //EPC寄存器的最新值，来自MEM模块 33 | output reg[`InstAddrBus] new_pc, //异常处理入口地址 34 | 35 | output reg flush 36 | ); 37 | 38 | always @ ( * ) begin 39 | if(rst == `RstEnable) begin 40 | stall <= 6'b000000; 41 | flush <= 1'b0; 42 | new_pc <= `ZeroWord; 43 | end else if(excepttype_i != `ZeroWord) begin //不为0，表示发生异常 44 | flush <= 1'b1; 45 | stall <= 6'b000000; 46 | case(excepttype_i) 47 | 32'h0000_0001:begin //中断 48 | new_pc <= 32'h0000_0020; 49 | end 50 | 32'h0000_0008:begin //系统调用异常syscall 51 | new_pc <= 32'h0000_0040; 52 | end 53 | 32'h0000_000a:begin //无效指令异常 54 | new_pc <= 32'h0000_0040; 55 | end 56 | 32'h0000_000d:begin //自陷异常 57 | new_pc <= 32'h0000_0040; 58 | end 59 | 32'h0000_000c:begin //溢出异常 60 | new_pc <= 32'h0000_0040; 61 | end 62 | 32'h0000_000e:begin //异常返回指令eret 63 | new_pc <= cp0_epc_i; 64 | end 65 | default:begin 66 | end 67 | endcase 68 | end else if(stallreq_from_mem == `Stop) begin 69 | stall <= 6'b011111; 70 | flush <= 1'b0; 71 | end else if(stallreq_from_ex == `Stop) begin 72 | stall <= 6'b001111; 73 | flush <= 1'b0; 74 | end else if(stallreq_from_id == `Stop) begin 75 | stall <= 6'b000111; 76 | flush <= 1'b0; 77 | //取指阶段请求暂停，理论上应该只暂停取指阶段、保持PC不变，也就是设置stall为 78 | //6'b000011。但是考虑到一种特殊情况：假设译码阶段的指令是转移指令，那么此时 79 | //取指阶段将要取到的指令就是延迟槽指令，将译码阶段也暂停，保持了转移指令与延 80 | //迟槽指令在流水线中的相对位置，从而能够正确识别出延迟槽指令；如果取指阶段暂停， 81 | //而不使译码阶段暂停，那么转移指令会在下一周期进入执行阶段，同时在译码阶段会 82 | //填充空指令，这样就使得填充的空指令被误认为是延迟槽指令，从而出错。 83 | end else if(stallreq_from_if == `Stop) begin 84 | stall <= 6'b000111; 85 | flush <= 1'b0; 86 | end else begin 87 | stall <= 6'b000000; 88 | flush <= 1'b0; 89 | new_pc <= `ZeroWord; 90 | end 91 | end 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /OpenMIPS.cache/wt/synthesis.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 9 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 10 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 11 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 12 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 13 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 14 | 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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 21 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 22 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 23 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 24 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 25 | 73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30333a323673:00:00 26 | 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3739322e3636384d42:00:00 27 | 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3538332e3735344d42:00:00 28 | eof:3807714265 29 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/mem_wb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 将访存阶段的运算结果，在下一个时钟传递到回写阶段 4 | //****************************************************************************** 5 | 6 | `include "defines.v" 7 | 8 | module mem_wb( 9 | input wire rst, 10 | input wire clk, 11 | 12 | //来自ctrl模块的信息 13 | input wire[5:0] stall, 14 | input wire flush, 15 | 16 | //访存阶段的结果 17 | input wire mem_wreg, 18 | input wire[`RegAddrBus] mem_wd, 19 | input wire[`RegBus] mem_wdata, 20 | 21 | input wire[`RegBus] mem_hi, 22 | input wire[`RegBus] mem_lo, 23 | input wire mem_whilo, 24 | 25 | //送到回写阶段的信息 26 | output reg wb_wreg, 27 | output reg[`RegAddrBus] wb_wd, 28 | output reg[`RegBus] wb_wdata, 29 | 30 | output reg[`RegBus] wb_hi, 31 | output reg[`RegBus] wb_lo, 32 | output reg wb_whilo, 33 | 34 | //LLbit寄存器相关接口 35 | input wire mem_LLbit_we, 36 | input wire mem_LLbit_value, 37 | output reg wb_LLbit_we, 38 | output reg wb_LLbit_value, 39 | 40 | //协处理器访问指令相关接口 41 | input wire mem_cp0_reg_we, 42 | input wire[4:0] mem_cp0_reg_write_addr, 43 | input wire[`RegBus] mem_cp0_reg_data, 44 | output reg wb_cp0_reg_we, 45 | output reg[4:0] wb_cp0_reg_write_addr, 46 | output reg[`RegBus] wb_cp0_reg_data 47 | ); 48 | 49 | // 1)当stall[4]为Stop，stall[5]为NoStop时，表示访存阶段暂停，而回写阶段继续， 50 | // 所以用空指令作为下一个周期进入回写阶段的指令 51 | // 2)当stall[4]为NoStop时，访存阶段继续，访存后的指令进入回写阶段 52 | // 3)其余情况下，保持回写阶段寄存器wb_wd、wb_wreg、wb_wdata、wb_hi、wb_lo、 53 | // wb_whilo不变 54 | always @ ( posedge clk ) begin 55 | if(rst == `RstEnable) begin 56 | wb_wreg <= `WriteDisable; 57 | wb_wd <= `NOPRegAddr; 58 | wb_wdata <= `ZeroWord; 59 | 60 | wb_hi <= `ZeroWord; 61 | wb_lo <= `ZeroWord; 62 | wb_whilo <= `WriteDisable; 63 | 64 | wb_LLbit_we <= 1'b0; 65 | wb_LLbit_value <= 1'b0; 66 | 67 | wb_cp0_reg_we <= `WriteDisable; 68 | wb_cp0_reg_write_addr <= 5'b00000; 69 | wb_cp0_reg_data <= `ZeroWord; 70 | 71 | end else if(flush == 1'b1) begin 72 | wb_wreg <= `WriteDisable; 73 | wb_wd <= `NOPRegAddr; 74 | wb_wdata <= `ZeroWord; 75 | 76 | wb_hi <= `ZeroWord; 77 | wb_lo <= `ZeroWord; 78 | wb_whilo <= `WriteDisable; 79 | 80 | wb_LLbit_we <= 1'b0; 81 | wb_LLbit_value <= 1'b0; 82 | 83 | wb_cp0_reg_we <= `WriteDisable; 84 | wb_cp0_reg_write_addr <= 5'b00000; 85 | wb_cp0_reg_data <= `ZeroWord; 86 | 87 | end else if(stall[4] == `Stop && stall[5] == `NoStop) begin 88 | wb_wreg <= `WriteDisable; 89 | wb_wd <= `NOPRegAddr; 90 | wb_wdata <= `ZeroWord; 91 | 92 | wb_hi <= `ZeroWord; 93 | wb_lo <= `ZeroWord; 94 | wb_whilo <= `WriteDisable; 95 | 96 | wb_LLbit_we <= 1'b0; 97 | wb_LLbit_value <= 1'b0; 98 | 99 | wb_cp0_reg_we <= `WriteDisable; 100 | wb_cp0_reg_write_addr <= 5'b00000; 101 | wb_cp0_reg_data <= `ZeroWord; 102 | 103 | end else if(stall[4] == `NoStop) begin 104 | wb_wreg <= mem_wreg; 105 | wb_wd <= mem_wd; 106 | wb_wdata <= mem_wdata; 107 | 108 | wb_hi <= mem_hi; 109 | wb_lo <= mem_lo; 110 | wb_whilo <= mem_whilo; 111 | 112 | wb_LLbit_we <= mem_LLbit_we; 113 | wb_LLbit_value <= mem_LLbit_value; 114 | 115 | wb_cp0_reg_we <= mem_cp0_reg_we; 116 | wb_cp0_reg_write_addr <= mem_cp0_reg_write_addr; 117 | wb_cp0_reg_data <= mem_cp0_reg_data; 118 | end 119 | end 120 | endmodule 121 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/openmips_min_sopc_tb_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/ctrl.v" --include "../../../OpenMIPS.srcs/sources_1/new" 3 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/cp0_reg.v" --include "../../../OpenMIPS.srcs/sources_1/new" 4 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/mem.v" --include "../../../OpenMIPS.srcs/sources_1/new" 5 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/ex_mem.v" --include "../../../OpenMIPS.srcs/sources_1/new" 6 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/ex.v" --include "../../../OpenMIPS.srcs/sources_1/new" 7 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/id_ex.v" --include "../../../OpenMIPS.srcs/sources_1/new" 8 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/id.v" --include "../../../OpenMIPS.srcs/sources_1/new" 9 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/if_id.v" --include "../../../OpenMIPS.srcs/sources_1/new" 10 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/pc_reg.v" --include "../../../OpenMIPS.srcs/sources_1/new" 11 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/regfile.v" --include "../../../OpenMIPS.srcs/sources_1/new" 12 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/mem_wb.v" --include "../../../OpenMIPS.srcs/sources_1/new" 13 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/LLbit_reg.v" --include "../../../OpenMIPS.srcs/sources_1/new" 14 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/hilo_reg.v" --include "../../../OpenMIPS.srcs/sources_1/new" 15 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/div.v" --include "../../../OpenMIPS.srcs/sources_1/new" 16 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/openmips.v" --include "../../../OpenMIPS.srcs/sources_1/new" 17 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/inst_rom.v" --include "../../../OpenMIPS.srcs/sources_1/new" 18 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/data_ram.v" --include "../../../OpenMIPS.srcs/sources_1/new" 19 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/regfile_display.v" --include "../../../OpenMIPS.srcs/sources_1/new" 20 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/clk_div.v" --include "../../../OpenMIPS.srcs/sources_1/new" 21 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sources_1/new/openmips_min_sopc.v" --include "../../../OpenMIPS.srcs/sources_1/new" 22 | verilog xil_defaultlib "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" "../../../OpenMIPS.srcs/sim_1/new/openmips_min_sopc_tb.v" --include "../../../OpenMIPS.srcs/sources_1/new" 23 | 24 | # compile glbl module 25 | verilog xil_defaultlib "glbl.v" 26 | 27 | # Do not sort compile order 28 | nosort 29 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/id_ex.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 将译码阶段取得的运算类型、源操作数、要写的目的寄存器地址等结果，在下一个时钟传递到 4 | // 流水线执行 5 | //****************************************************************************** 6 | 7 | `include "defines.v" 8 | 9 | module id_ex( 10 | input wire rst, 11 | input wire clk, 12 | 13 | //来自ctrl模块的信息 14 | input wire[5:0] stall, 15 | input wire flush, 16 | 17 | //从译码阶段传递过来的信息 18 | input wire[`AluOpBus] id_aluop, //译码阶段指令运算子类型 19 | input wire[`AluSelBus] id_alusel, //译码阶段指令运算类型 20 | input wire[`RegBus] id_reg1, //译码阶段指令源操作数1 21 | input wire[`RegBus] id_reg2, //译码阶段指令源操作数2 22 | input wire id_wreg, //译码阶段指令是否有目的寄存器 23 | input wire[`RegAddrBus] id_wd, //译码阶段指令目的寄存器地址 24 | //转移指令及延迟槽相关信息 25 | input wire[`InstAddrBus] id_link_address, //处于译码阶段的转移指令要保存的返回地址 26 | input wire id_is_in_delayslot, //当前处于译码阶段的指令是否位于延迟槽 27 | input wire[`InstBus] id_inst, //指令传递 28 | //异常相关 29 | input wire[`InstAddrBus] id_current_inst_address, 30 | input wire[31:0] id_excepttype, 31 | 32 | 33 | //传递到执行阶段的信息 34 | output reg[`AluOpBus] ex_aluop, //执行阶段指令运算子类型 35 | output reg[`AluSelBus] ex_alusel, //执行阶段指令运算类型 36 | output reg[`RegBus] ex_reg1, //执行阶段指令源操作数1 37 | output reg[`RegBus] ex_reg2, //执行阶段指令源操作数2 38 | output reg ex_wreg, //执行阶段指令是否有目的寄存器 39 | output reg[`RegAddrBus] ex_wd, //执行阶段指令目的寄存器地址 40 | output reg[`InstAddrBus] ex_link_address, //处于执行阶段的转移指令要保存的返回地址 41 | output reg ex_is_in_delayslot, //当前处于执行阶段的指令是否位于延迟槽 42 | output reg[`InstBus] ex_inst, 43 | output reg[`InstAddrBus] ex_current_inst_address, 44 | output reg[31:0] ex_excepttype, 45 | 46 | 47 | //由ID模块输入next_inst_in_delayslot_i，再回传is_in_delayslot_o到ID模块， 48 | //实现对下一条指令是否是延迟槽指令的标记 49 | input wire next_inst_in_delayslot_i, //下一条进入译码阶段的指令是否位于延迟槽 50 | output reg is_in_delayslot_o //当前处于译码阶段的指令是否位于延迟槽 51 | ); 52 | 53 | // 1.当stall[2]为Stop，stall[3]为NoStop时，表示译码阶段暂停，而执行阶段 54 | // 继续，所以使用空指令作为下一个周期进入执行阶段的指令 55 | // 2.当stall[2]为NoStop时，译码阶段继续，译码后的指令进入执行阶段 56 | // 3.其余情况下，保持执行阶段的寄存器ex_aluop、ex_alusel、ex_reg1、ex_reg2、 57 | // ex_wd、ex_wreg不变 58 | always @ ( posedge clk ) begin 59 | if(rst == `RstEnable) begin 60 | ex_aluop <= `EXE_NOP_OP; 61 | ex_alusel <= `EXE_RES_NOP; 62 | ex_reg1 <= `ZeroWord; 63 | ex_reg2 <= `ZeroWord; 64 | ex_wreg <= `WriteDisable; 65 | ex_wd <= `NOPRegAddr; 66 | ex_link_address <= `ZeroWord; 67 | ex_is_in_delayslot <= `NotInDelaySlot; 68 | ex_inst <= `ZeroWord; 69 | ex_current_inst_address <= `ZeroWord; 70 | ex_excepttype <= `ZeroWord; 71 | 72 | is_in_delayslot_o <= `NotInDelaySlot; 73 | end else if(flush == 1'b1) begin 74 | ex_aluop <= `EXE_NOP_OP; 75 | ex_alusel <= `EXE_RES_NOP; 76 | ex_reg1 <= `ZeroWord; 77 | ex_reg2 <= `ZeroWord; 78 | ex_wreg <= `WriteDisable; 79 | ex_wd <= `NOPRegAddr; 80 | ex_link_address <= `ZeroWord; 81 | ex_is_in_delayslot <= `NotInDelaySlot; 82 | ex_inst <= `ZeroWord; 83 | ex_excepttype <= `ZeroWord; 84 | ex_current_inst_address <= `ZeroWord; 85 | 86 | is_in_delayslot_o <= `NotInDelaySlot; 87 | end else if(stall[2] == `Stop && stall[3] == `NoStop) begin 88 | ex_aluop <= `EXE_NOP_OP; 89 | ex_alusel <= `EXE_RES_NOP; 90 | ex_reg1 <= `ZeroWord; 91 | ex_reg2 <= `ZeroWord; 92 | ex_wreg <= `WriteDisable; 93 | ex_wd <= `NOPRegAddr; 94 | ex_link_address <= `ZeroWord; 95 | ex_is_in_delayslot <= `NotInDelaySlot; 96 | ex_inst <= `ZeroWord; 97 | ex_current_inst_address <= `ZeroWord; 98 | ex_excepttype <= `ZeroWord; 99 | end else if(stall[2] == `NoStop) begin 100 | ex_aluop <= id_aluop; 101 | ex_alusel <= id_alusel; 102 | ex_reg1 <= id_reg1; 103 | ex_reg2 <= id_reg2; 104 | ex_wreg <= id_wreg; 105 | ex_wd <= id_wd; 106 | ex_link_address <= id_link_address; 107 | ex_is_in_delayslot <= id_is_in_delayslot; 108 | ex_inst <= id_inst; 109 | ex_current_inst_address <= id_current_inst_address; 110 | ex_excepttype <= id_excepttype; 111 | 112 | is_in_delayslot_o <= next_inst_in_delayslot_i; 113 | end 114 | end 115 | 116 | endmodule 117 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/openmips_min_sopc_control_sets_placed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Tue May 10 14:28:48 2016 5 | | Host : LMX-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : report_control_sets -verbose -file openmips_min_sopc_control_sets_placed.rpt 7 | | Design : openmips_min_sopc 8 | | Device : xc7a35ti 9 | ---------------------------------------------------------------------------------------------- 10 | 11 | Control Set Information 12 | 13 | Table of Contents 14 | ----------------- 15 | 1. Summary 16 | 2. Flip-Flop Distribution 17 | 3. Detailed Control Set Information 18 | 19 | 1. Summary 20 | ---------- 21 | 22 | +-------------------------------------------------------------------+-------+ 23 | | Status | Count | 24 | +-------------------------------------------------------------------+-------+ 25 | | Number of unique control sets | 14 | 26 | | Minimum Number of register sites lost to control set restrictions | 28 | 27 | +-------------------------------------------------------------------+-------+ 28 | 29 | 30 | 2. Flip-Flop Distribution 31 | ------------------------- 32 | 33 | +--------------+-----------------------+------------------------+-----------------+--------------+ 34 | | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | 35 | +--------------+-----------------------+------------------------+-----------------+--------------+ 36 | | No | No | No | 3 | 2 | 37 | | No | No | Yes | 0 | 0 | 38 | | No | Yes | No | 139 | 60 | 39 | | Yes | No | No | 70 | 30 | 40 | | Yes | No | Yes | 0 | 0 | 41 | | Yes | Yes | No | 456 | 185 | 42 | +--------------+-----------------------+------------------------+-----------------+--------------+ 43 | 44 | 45 | 3. Detailed Control Set Information 46 | ----------------------------------- 47 | 48 | +--------------------------+-------------------------------------+-----------------------------------+------------------+----------------+ 49 | | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | 50 | +--------------------------+-------------------------------------+-----------------------------------+------------------+----------------+ 51 | | clk_IBUF_BUFG | | | 1 | 1 | 52 | | clk_div0/count_reg[1]_0 | | | 1 | 2 | 53 | | clk_IBUF_BUFG | openmips0/div0/cnt[5]_i_1_n_0 | | 2 | 6 | 54 | | clk_IBUF_BUFG | | clk_div0/count[0]_i_1_n_0 | 8 | 32 | 55 | | clk_IBUF_BUFG | openmips0/id_ex0/E[0] | | 16 | 32 | 56 | | clk_IBUF_BUFG | openmips0/id_ex0/sel | openmips0/pc_reg0/clear | 9 | 32 | 57 | | clk_IBUF_BUFG | openmips0/id_ex0/dividend_reg[64] | openmips0/id_ex0/dividend_reg[33] | 10 | 32 | 58 | | clk_IBUF_BUFG | openmips0/div0/divisor | | 12 | 32 | 59 | | clk_IBUF_BUFG | openmips0/mem_wb0/E[0] | rst_IBUF | 35 | 64 | 60 | | clk_IBUF_BUFG | openmips0/div0/result_o[63]_i_1_n_0 | rst_IBUF | 18 | 65 | 61 | | clk_IBUF_BUFG | openmips0/id_ex0/sel | openmips0/id_ex0/SR[0] | 59 | 103 | 62 | | clk_IBUF_BUFG | | rst_IBUF | 52 | 107 | 63 | | clk_IBUF_BUFG | openmips0/mem_wb0/ex_reg1_reg[31] | | 18 | 144 | 64 | | clk_IBUF_BUFG | openmips0/id_ex0/sel | rst_IBUF | 54 | 160 | 65 | +--------------------------+-------------------------------------+-----------------------------------+------------------+----------------+ 66 | 67 | 68 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/ex_mem.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 将执行阶段取得的运算结果，在下一个时钟传递到流水线访存阶段 4 | //****************************************************************************** 5 | 6 | `include "defines.v" 7 | 8 | module ex_mem( 9 | input wire rst, 10 | input wire clk, 11 | 12 | //来自ctrl的控制信息 13 | input wire[5:0] stall, 14 | input wire flush, 15 | 16 | //来自执行阶段的信息 17 | input wire ex_wreg, 18 | input wire[`RegAddrBus] ex_wd, 19 | input wire[`RegBus] ex_wdata, 20 | 21 | input wire[`RegBus] ex_hi, 22 | input wire[`RegBus] ex_lo, 23 | input wire ex_whilo, 24 | 25 | //送到访存阶段的信息 26 | output reg mem_wreg, 27 | output reg[`RegAddrBus] mem_wd, 28 | output reg[`RegBus] mem_wdata, 29 | 30 | output reg[`RegBus] mem_hi, 31 | output reg[`RegBus] mem_lo, 32 | output reg mem_whilo, 33 | 34 | //乘累加、乘累减运算数据接口：回传回EX模块 35 | input wire[`DoubleRegBus] hilo_i, 36 | input wire[1:0] cnt_i, 37 | output reg[`DoubleRegBus] hilo_o, 38 | output reg[1:0] cnt_o, 39 | 40 | //加载存储指令相关接口 41 | input wire[`AluOpBus] ex_aluop, 42 | input wire[`DataAddrBus] ex_mem_addr, 43 | input wire[`RegBus] ex_reg2, 44 | output reg[`AluOpBus] mem_aluop, 45 | output reg[`DataAddrBus] mem_mem_addr, 46 | output reg[`RegBus] mem_reg2, 47 | 48 | //协处理器访问指令相关接口 49 | input wire ex_cp0_reg_we, 50 | input wire[4:0] ex_cp0_reg_write_addr, 51 | input wire[`RegBus] ex_cp0_reg_data, 52 | output reg mem_cp0_reg_we, 53 | output reg[4:0] mem_cp0_reg_write_addr, 54 | output reg[`RegBus] mem_cp0_reg_data, 55 | 56 | //异常处理相关接口 57 | input wire[31:0] ex_excepttype, //译码执行阶段收集到的异常信息 58 | input wire ex_is_in_delayslot, //执行阶段指令是否是延迟槽指令 59 | input wire[`InstAddrBus] ex_current_inst_address, //执行阶段指令的地址 60 | output reg[31:0] mem_excepttype, //译码执行阶段收集到的异常信息 61 | output reg mem_is_in_delayslot, //访存阶段指令是否是延迟槽指令 62 | output reg[`InstAddrBus] mem_current_inst_address //访存阶段指令的地址 63 | ); 64 | 65 | // 1)当stall[3]为Stop，stall[4]为NoStop时，表示执行阶段暂停，而访存阶段 66 | // 继续，所以使用空指令作为下一个周期进入访存阶段的指令;在执行阶段暂停的时候， 67 | // 将输入信号hilo_i通过输出接口hilo_o送出，输入信号cnt_i通过输出接口cnt_o 68 | // 送出，其余时刻hilo_o、cnt_o为0 69 | // 2)当stall[3]为NoStop时，执行阶段继续，执行后的指令进入访存阶段 70 | // 3)其余情况下，保持访存阶段的寄存器mem_wb、mem_wreg、mem_wdata、mem_hi、 71 | // mem_lo、mem_whilo不变 72 | always @ ( posedge clk ) begin 73 | if(rst == `RstEnable) begin 74 | mem_wreg <= `WriteDisable; 75 | mem_wd <= `NOPRegAddr; 76 | mem_wdata <= `ZeroWord; 77 | 78 | mem_hi <= `ZeroWord; 79 | mem_lo <= `ZeroWord; 80 | mem_whilo <= `WriteDisable; 81 | 82 | hilo_o <= {`ZeroWord, `ZeroWord}; 83 | cnt_o <= 2'b00; 84 | 85 | mem_aluop <= `EXE_NOP_OP; 86 | mem_mem_addr <= `ZeroWord; 87 | mem_reg2 <= `ZeroWord; 88 | 89 | mem_cp0_reg_we <= `WriteDisable; 90 | mem_cp0_reg_write_addr <= 5'b00000; 91 | mem_cp0_reg_data <= `ZeroWord; 92 | 93 | mem_excepttype <= `ZeroWord; 94 | mem_is_in_delayslot <= `NotInDelaySlot; 95 | mem_current_inst_address <= `ZeroWord; 96 | 97 | end else if(flush == 1'b1) begin 98 | mem_wreg <= `WriteDisable; 99 | mem_wd <= `NOPRegAddr; 100 | mem_wdata <= `ZeroWord; 101 | 102 | mem_hi <= `ZeroWord; 103 | mem_lo <= `ZeroWord; 104 | mem_whilo <= `WriteDisable; 105 | 106 | hilo_o <= {`ZeroWord,`ZeroWord}; 107 | cnt_o <= 2'b00; 108 | 109 | mem_aluop <= `EXE_NOP_OP; 110 | mem_mem_addr <= `ZeroWord; 111 | mem_reg2 <= `ZeroWord; 112 | 113 | mem_cp0_reg_we <= `WriteDisable; 114 | mem_cp0_reg_write_addr <= 5'b00000; 115 | mem_cp0_reg_data <= `ZeroWord; 116 | 117 | mem_excepttype <= `ZeroWord; 118 | mem_is_in_delayslot <= `NotInDelaySlot; 119 | mem_current_inst_address <= `ZeroWord; 120 | 121 | end else if(stall[3] == `Stop && stall[4] == `NoStop) begin 122 | mem_wreg <= `WriteDisable; 123 | mem_wd <= `NOPRegAddr; 124 | mem_wdata <= `ZeroWord; 125 | 126 | mem_hi <= `ZeroWord; 127 | mem_lo <= `ZeroWord; 128 | mem_whilo <= `WriteDisable; 129 | 130 | //执行阶段暂停时，之后的阶段不暂停时，回传到EX模块用于乘累加、乘累减运算 131 | hilo_o <= hilo_i; 132 | cnt_o <= cnt_i; 133 | 134 | mem_aluop <= `EXE_NOP_OP; 135 | mem_mem_addr <= `ZeroWord; 136 | mem_reg2 <= `ZeroWord; 137 | 138 | mem_cp0_reg_we <= `WriteDisable; 139 | mem_cp0_reg_write_addr <= 5'b00000; 140 | mem_cp0_reg_data <= `ZeroWord; 141 | 142 | mem_excepttype <= `ZeroWord; 143 | mem_is_in_delayslot <= `NotInDelaySlot; 144 | mem_current_inst_address <= `ZeroWord; 145 | 146 | end else if(stall[3] == `NoStop) begin 147 | mem_wreg <= ex_wreg; 148 | mem_wd <= ex_wd; 149 | mem_wdata <= ex_wdata; 150 | 151 | mem_hi <= ex_hi; 152 | mem_lo <= ex_lo; 153 | mem_whilo <= ex_whilo; 154 | 155 | //流水线不暂停时，该信息不起作用，其他信息传到流水线下一阶段 156 | hilo_o <= {`ZeroWord, `ZeroWord}; 157 | cnt_o <= 2'b00; 158 | 159 | mem_aluop <= ex_aluop; 160 | mem_mem_addr <= ex_mem_addr; 161 | mem_reg2 <= ex_reg2; 162 | 163 | mem_cp0_reg_we <= ex_cp0_reg_we; 164 | mem_cp0_reg_write_addr <= ex_cp0_reg_write_addr; 165 | mem_cp0_reg_data <= ex_cp0_reg_data; 166 | 167 | mem_excepttype <= ex_excepttype; 168 | mem_is_in_delayslot <= ex_is_in_delayslot; 169 | mem_current_inst_address <= ex_current_inst_address; 170 | 171 | end else begin 172 | //流水线暂停时，回传到EX模块用于乘累加、乘累减运算 173 | hilo_o <= hilo_i; 174 | cnt_o <= cnt_i; 175 | end 176 | end 177 | 178 | endmodule 179 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/wishbone_bus_if.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // Wishbone总线接口模块 4 | // 整个模块可以分为两个部分：与CPU交互的组合逻辑电路部分，以及与外设交互的时序逻辑电路 5 | //部分，二者一并组成了Wishbone总线接口 6 | //****************************************************************************** 7 | 8 | `include "defines.v" 9 | 10 | module wishbone_bus_if( 11 | input wire rst, 12 | input wire clk, 13 | 14 | //与CTRL模块的接口 15 | input wire[5:0] stall_i, //CTRL模块传入的流水线暂停信号 16 | input wire flush_i, //CTRL模块传入的流水线清除信号 17 | output reg stallreq, //请求流水线暂停的信号 18 | 19 | //CPU侧接口 20 | input wire cpu_ce_i, //来自处理器的访问请求信号 21 | input wire cpu_we_i, //来自处理器的读写操作指示信号 22 | input wire[3:0] cpu_sel_i, //来自处理器的字节选择信号 23 | input wire[`RegBus] cpu_addr_i, //来自处理器的地址信号 24 | input wire[`RegBus] cpu_data_i, //来自处理器的数据 25 | output reg[`RegBus] cpu_data_o, //输出到处理器的数据 26 | 27 | //Wishbone侧接口 28 | output reg[`RegBus] wishbone_addr_o, //Wishbone总线输出的地址 29 | input wire[`RegBus] wishbone_data_i, //Wishbone总线输入的数据 30 | output reg[`RegBus] wishbone_data_o, //Wishbone总线输出的数据 31 | output reg wishbone_we_o, //Wishbone总线写使能信号 32 | output reg[3:0] wishbone_sel_o, //Wishbone总线字节选择信号 33 | output reg wishbone_cyc_o, //Wishbone总线周期信号 34 | output reg wishbone_stb_o, //Wishbone总线选通信号 35 | input wire wishbone_ack_i //Wishbone总线操作成功响应信号 36 | ); 37 | 38 | reg[1:0] wishbone_state; //保存Wishbone总线接口模块的状态 39 | reg[`RegBus] rd_buf; //寄存通过Wishbone总线访问到的数据(读缓存) 40 | 41 | //****************************************************************************** 42 | // 第一段：控制状态转化的时序电路(与外设的接口部分) 43 | //****************************************************************************** 44 | always @ ( posedge clk ) begin 45 | if(rst == `RstEnable) begin 46 | wishbone_state <= `WB_IDLE; //进入空闲状态 47 | wishbone_addr_o <= `ZeroWord; 48 | wishbone_data_o <= `ZeroWord; 49 | wishbone_we_o <= `WriteDisable; 50 | wishbone_sel_o <= 4'b0000; 51 | wishbone_cyc_o <= 1'b0; 52 | wishbone_stb_o <= 1'b0; 53 | rd_buf <= `ZeroWord; 54 | end else begin 55 | case(wishbone_state) 56 | `WB_IDLE:begin //空闲状态 57 | if((cpu_ce_i == 1'b1) && (flush_i == `False_v)) begin 58 | wishbone_addr_o <= cpu_addr_i; 59 | wishbone_data_o <= cpu_data_i; 60 | wishbone_we_o <= cpu_we_i; 61 | wishbone_sel_o <= cpu_sel_i; 62 | wishbone_cyc_o <= 1'b1; 63 | wishbone_stb_o <= 1'b1; 64 | rd_buf <= `ZeroWord; 65 | wishbone_state <= `WB_BUSY; //进入总线忙状态 66 | end 67 | end 68 | `WB_BUSY:begin //总线忙状态 69 | if(wishbone_ack_i == 1'b1) begin 70 | //从设备返回ACK为1时表示准备好数据，主设备检测到后采样数据， 71 | //撤销选通信号和总线周期信号，完成读数据的过程 72 | if(cpu_we_i == `WriteDisable) begin 73 | rd_buf <= wishbone_data_i; 74 | end 75 | //读写操作共有的过程 76 | wishbone_stb_o <= 1'b0; 77 | wishbone_cyc_o <= 1'b0; 78 | wishbone_addr_o <= `ZeroWord; 79 | wishbone_data_o <= `ZeroWord; 80 | wishbone_we_o <= `WriteDisable; 81 | wishbone_sel_o <= 4'b0000; 82 | //状态转换 83 | wishbone_state <= `WB_IDLE; //进入空闲状态 84 | if(stall_i != 6'b000000) begin 85 | wishbone_state <= `WB_WAIT_FOR_STALL; //进入等待暂停结束状态 86 | end 87 | //还没有收到总线响应时发生了异常，导致处理器要清除流水线 88 | end else if(flush_i == `True_v) begin 89 | wishbone_stb_o <= 1'b0; 90 | wishbone_cyc_o <= 1'b0; 91 | wishbone_addr_o <= `ZeroWord; 92 | wishbone_data_o <= `ZeroWord; 93 | wishbone_we_o <= `WriteDisable; 94 | wishbone_sel_o <= 4'b0000; 95 | rd_buf <= `ZeroWord; 96 | wishbone_state <= `WB_IDLE; //进入空闲状态 97 | end 98 | end 99 | `WB_WAIT_FOR_STALL:begin //进入等待暂停结束状态 100 | if(stall_i == 6'b000000) begin 101 | wishbone_state <= `WB_IDLE; //暂停结束进入空闲状态 102 | end 103 | end 104 | default:begin 105 | end 106 | endcase 107 | end//else 108 | end//always 109 | 110 | 111 | //****************************************************************************** 112 | // 第二段：给处理器接口信号赋值的组合电路(与CPU的接口部分) 113 | //****************************************************************************** 114 | always @ ( * ) begin 115 | if(rst == `RstEnable) begin 116 | stallreq <= `NoStop; 117 | cpu_data_o <= `ZeroWord; 118 | end else begin 119 | stallreq <= `NoStop; 120 | case(wishbone_state) 121 | `WB_IDLE:begin //空闲状态 122 | //需要暂停流水线以等待总线访问结束 123 | if((cpu_ce_i == 1'b1) && (flush_i == `False_v)) begin 124 | stallreq <= `Stop; 125 | cpu_data_o <= `ZeroWord; 126 | end 127 | end 128 | `WB_BUSY:begin //总线忙状态 129 | //收到从设备响应，表示总线访问结束，流水线继续 130 | if(wishbone_ack_i == 1'b1) begin 131 | stallreq <= `NoStop; 132 | //读操作 133 | if(wishbone_we_o == `WriteDisable) begin 134 | //这里应该是rd_buf???还是不需要暂停的读操作??? 135 | cpu_data_o <= wishbone_data_i; 136 | //写操作 137 | end else begin 138 | cpu_data_o <= `ZeroWord; 139 | end 140 | //未收到从设备响应，表示总线访问还未结束，保持流水线暂停 141 | end else begin 142 | stallreq <= `Stop; 143 | cpu_data_o <= `ZeroWord; 144 | end 145 | end 146 | `WB_WAIT_FOR_STALL:begin //等待暂停结束状态 147 | //此时总线访问已经结束，所以继续流水线 148 | stallreq <= `NoStop; 149 | cpu_data_o <= rd_buf; 150 | end 151 | default:begin 152 | end 153 | endcase 154 | end//else 155 | end//always 156 | 157 | endmodule 158 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/gen_run.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/compile.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 2 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ctrl.v" into library xil_defaultlib 3 | INFO: [VRFC 10-311] analyzing module ctrl 4 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/cp0_reg.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module cp0_reg 7 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 8 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/mem.v" into library xil_defaultlib 9 | INFO: [VRFC 10-311] analyzing module mem 10 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 11 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ex_mem.v" into library xil_defaultlib 12 | INFO: [VRFC 10-311] analyzing module ex_mem 13 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 14 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ex.v" into library xil_defaultlib 15 | INFO: [VRFC 10-311] analyzing module ex 16 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 17 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/id_ex.v" into library xil_defaultlib 18 | INFO: [VRFC 10-311] analyzing module id_ex 19 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 20 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/id.v" into library xil_defaultlib 21 | INFO: [VRFC 10-311] analyzing module id 22 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 23 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/if_id.v" into library xil_defaultlib 24 | INFO: [VRFC 10-311] analyzing module if_id 25 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 26 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/pc_reg.v" into library xil_defaultlib 27 | INFO: [VRFC 10-311] analyzing module pc_reg 28 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 29 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/regfile.v" into library xil_defaultlib 30 | INFO: [VRFC 10-311] analyzing module regfile 31 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 32 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/mem_wb.v" into library xil_defaultlib 33 | INFO: [VRFC 10-311] analyzing module mem_wb 34 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 35 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/LLbit_reg.v" into library xil_defaultlib 36 | INFO: [VRFC 10-311] analyzing module LLbit_reg 37 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 38 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/hilo_reg.v" into library xil_defaultlib 39 | INFO: [VRFC 10-311] analyzing module hilo_reg 40 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 41 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/div.v" into library xil_defaultlib 42 | INFO: [VRFC 10-311] analyzing module div 43 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 44 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/openmips.v" into library xil_defaultlib 45 | INFO: [VRFC 10-311] analyzing module openmips 46 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 47 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/inst_rom.v" into library xil_defaultlib 48 | INFO: [VRFC 10-311] analyzing module inst_rom 49 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 50 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/data_ram.v" into library xil_defaultlib 51 | INFO: [VRFC 10-311] analyzing module data_ram 52 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 53 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/regfile_display.v" into library xil_defaultlib 54 | INFO: [VRFC 10-311] analyzing module regfile_display 55 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 56 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/clk_div.v" into library xil_defaultlib 57 | INFO: [VRFC 10-311] analyzing module clk_div 58 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 59 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/openmips_min_sopc.v" into library xil_defaultlib 60 | INFO: [VRFC 10-311] analyzing module openmips_min_sopc 61 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 62 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sim_1/new/openmips_min_sopc_tb.v" into library xil_defaultlib 63 | INFO: [VRFC 10-311] analyzing module openmips_min_sopc_tb 64 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/glbl.v" into library xil_defaultlib 65 | INFO: [VRFC 10-311] analyzing module glbl 66 | -------------------------------------------------------------------------------- /OpenMIPS.sim/sim_1/behav/xvlog.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 2 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ctrl.v" into library xil_defaultlib 3 | INFO: [VRFC 10-311] analyzing module ctrl 4 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/cp0_reg.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module cp0_reg 7 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 8 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/mem.v" into library xil_defaultlib 9 | INFO: [VRFC 10-311] analyzing module mem 10 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 11 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ex_mem.v" into library xil_defaultlib 12 | INFO: [VRFC 10-311] analyzing module ex_mem 13 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 14 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/ex.v" into library xil_defaultlib 15 | INFO: [VRFC 10-311] analyzing module ex 16 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 17 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/id_ex.v" into library xil_defaultlib 18 | INFO: [VRFC 10-311] analyzing module id_ex 19 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 20 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/id.v" into library xil_defaultlib 21 | INFO: [VRFC 10-311] analyzing module id 22 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 23 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/if_id.v" into library xil_defaultlib 24 | INFO: [VRFC 10-311] analyzing module if_id 25 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 26 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/pc_reg.v" into library xil_defaultlib 27 | INFO: [VRFC 10-311] analyzing module pc_reg 28 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 29 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/regfile.v" into library xil_defaultlib 30 | INFO: [VRFC 10-311] analyzing module regfile 31 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 32 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/mem_wb.v" into library xil_defaultlib 33 | INFO: [VRFC 10-311] analyzing module mem_wb 34 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 35 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/LLbit_reg.v" into library xil_defaultlib 36 | INFO: [VRFC 10-311] analyzing module LLbit_reg 37 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 38 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/hilo_reg.v" into library xil_defaultlib 39 | INFO: [VRFC 10-311] analyzing module hilo_reg 40 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 41 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/div.v" into library xil_defaultlib 42 | INFO: [VRFC 10-311] analyzing module div 43 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 44 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/openmips.v" into library xil_defaultlib 45 | INFO: [VRFC 10-311] analyzing module openmips 46 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 47 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/inst_rom.v" into library xil_defaultlib 48 | INFO: [VRFC 10-311] analyzing module inst_rom 49 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 50 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/data_ram.v" into library xil_defaultlib 51 | INFO: [VRFC 10-311] analyzing module data_ram 52 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 53 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/regfile_display.v" into library xil_defaultlib 54 | INFO: [VRFC 10-311] analyzing module regfile_display 55 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 56 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/clk_div.v" into library xil_defaultlib 57 | INFO: [VRFC 10-311] analyzing module clk_div 58 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 59 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/openmips_min_sopc.v" into library xil_defaultlib 60 | INFO: [VRFC 10-311] analyzing module openmips_min_sopc 61 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sources_1/new/defines.v" into library xil_defaultlib 62 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.srcs/sim_1/new/openmips_min_sopc_tb.v" into library xil_defaultlib 63 | INFO: [VRFC 10-311] analyzing module openmips_min_sopc_tb 64 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/LMX/Desktop/MyProject/OpenMIPS/OpenMIPS.sim/sim_1/behav/glbl.v" into library xil_defaultlib 65 | INFO: [VRFC 10-311] analyzing module glbl 66 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/div.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //****************************************************************************** 3 | // 试商法实现除法模块 4 | //****************************************************************************** 5 | 6 | `include "defines.v" 7 | 8 | module div( 9 | input wire rst, 10 | input wire clk, 11 | 12 | input wire signed_div_i, //是否是有符号除法 13 | input wire[31:0] opdata1_i, //被除数 14 | input wire[31:0] opdata2_i, //除数 15 | input wire start_i, //是否开始除法运算 16 | input wire annul_i, //是否取消除法运算 17 | 18 | output reg[63:0] result_o, //除法运算结果 19 | output reg ready_o //除法运算是否结束 20 | ); 21 | 22 | wire[32:0] div_temp; 23 | reg[5:0] cnt; //记录试商法进行了几轮，32时结束 24 | reg[64:0] dividend; 25 | reg[1:0] state; 26 | reg[31:0] divisor; 27 | reg[31:0] temp_op1; 28 | reg[31:0] temp_op2; 29 | 30 | // dividend的低32位保存的是被除数、中间结果，第k次迭代结束的时候dividend[k:0]保存 31 | // 的就是当前得到的中间结果，dividend[31:k+1]保存的就是被除数中还没有参与运算的数 32 | // 据，dividend高32位是每次迭代时的被减数，所以dividend[63:32]就是被减数minuend， 33 | // divisor就是除数n，此处进行的就是(minuend - n)运算，结果保存在div_temp中 34 | assign div_temp = {1'b0,dividend[63:32]} - {1'b0,divisor}; 35 | 36 | always @ ( posedge clk ) begin 37 | if(rst == `RstEnable) begin 38 | state <= `DivFree; 39 | ready_o <= `DivResultNotReady; 40 | result_o <= {`ZeroWord,`ZeroWord}; 41 | end else begin 42 | case(state) 43 | //************************************************************** 44 | // DivFree状态 45 | // 分三种情况： 46 | // 1)开始除法运算，但除数为0，那么进入DivByZero状态 47 | // 2)开始除法运算，且除数不为0，那么进入DivOn状态，初始化cnt为0，如果 48 | // 是有符号除法，且被除数或者除数为负，那么对被除数或者除数取补码。除 49 | // 数保存到divisor中，将被除数的最高位保存到dividend的第32位，准备进 50 | // 行第一次迭代 51 | // 3)没有开始除法运算，保持ready_o为DivResultNotReady，保持result_o 52 | // 为0 53 | //************************************************************** 54 | `DivFree:begin 55 | if(start_i == `DivStart && annul_i == 1'b0) begin 56 | if(opdata2_i == `ZeroWord) begin //除数为0 57 | state <= `DivByZero; 58 | end else begin //除数不为0 59 | state <= `DivOn; 60 | cnt <= 6'b000000; 61 | if(signed_div_i == 1'b1 && opdata1_i[31] == 1'b1) begin 62 | temp_op1 = ~opdata1_i + 1; //被除数取补码 63 | end else begin 64 | temp_op1 = opdata1_i; 65 | end 66 | if(signed_div_i == 1'b1 && opdata2_i[31] == 1'b1) begin 67 | temp_op2 = ~opdata2_i + 1; //除数取补码 68 | end else begin 69 | temp_op2 = opdata2_i; 70 | end 71 | dividend <= {`ZeroWord,`ZeroWord}; 72 | dividend[32:1] <= temp_op1; 73 | divisor <= temp_op2; 74 | end//else 75 | end else begin //没有开始除法运算 76 | ready_o <= `DivResultNotReady; 77 | result_o <= {`ZeroWord,`ZeroWord}; 78 | end 79 | end//DivFree 80 | 81 | //************************************************************** 82 | // DivByZero状态 83 | // 如果进入DivByZero状态，那么直接进入DivEnd状态，除法结束，且结果为0 84 | //************************************************************** 85 | `DivByZero:begin 86 | dividend <= {`ZeroWord,`ZeroWord}; 87 | state <= `DivEnd; 88 | end//DivByZero 89 | 90 | //************************************************************** 91 | // DivOn状态 92 | // 分三种情况： 93 | // 1)如果输入信号annul_i为1，表示处理器取消除法运算，那么DIV模块直接 94 | // 回到DivFree状态 95 | // 2)如果annul_i为0，且cnt不为32，那么表示试商法还没有结束，此时如果 96 | // 减法结果div_temp为负，那么此次迭代结果是0；如果减法结果div_temp为 97 | // 正，那么此次迭代结果是1；dividend的最低位保存每次的迭代结果。同时 98 | // 保持DivOn状态，cnt加1 99 | // 3)如果annul_i为0，且cnt为32，那么表示试商法结束，如果是有符号除法， 100 | // 且被除数、除数一正一负，那么将试商法的结果取补码，得到最终的结果，此 101 | // 处的商、余数都要取补码。商保存在dividend的低32位，余数保存在dividend 102 | // 的高32位。同时进入DivEnd状态 103 | //************************************************************** 104 | `DivOn:begin 105 | if(annul_i == 1'b0) begin 106 | if(cnt != 6'b100000) begin 107 | if(div_temp[32] == 1'b1) begin 108 | // 如果div_temp[32]为1，表示(minuend-n)结果小于0， 109 | // 将dividend向左移一位，这样就将被除数还没有参与运 110 | // 算的最高位加入到下一次迭代的被减数中，同时将0追加 111 | // 到中间结果 112 | dividend <= {dividend[63:0],1'b0}; //左移一位 113 | end else begin 114 | // 如果div_temp[32]为0，表示(minuend-n)结果大于等 115 | // 于0，将减法的结果与被除数还没有参与运算的最高位加 116 | // 入到下一次迭代的被减数中，同时将1追加到中间结果 117 | dividend <= {div_temp[31:0],dividend[31:0],1'b1}; 118 | end 119 | cnt <= cnt + 1; 120 | end else begin //试商法结束 121 | if((signed_div_i == 1'b1) && //商取补码 122 | ((opdata1_i[31] ^ opdata2_i[31]) == 1'b1)) begin 123 | dividend[31:0] <= (~dividend[31:0] + 1); 124 | end 125 | if((signed_div_i == 1'b1) && //余数取补码,余数与被除数符号一致 126 | ((opdata1_i[31] ^ dividend[64]) == 1'b1)) begin 127 | dividend[64:33] <= (~dividend[64:33] + 1); 128 | end 129 | state <= `DivEnd; //进入DivEnd状态 130 | cnt <= 6'b000000; //cnt清零 131 | end//else 132 | end else begin //如果annul_i为1，直接回到DivFree状态 133 | state <= `DivFree; 134 | end 135 | end//DivOn 136 | 137 | //************************************************************** 138 | // DivEnd状态 139 | // 除法运算结束，result_o的宽度是64位，其高32位存储余数，低32位存储商， 140 | // 设置输出信号ready_o为DivResultReady，表示除法结束，然后等待EX模块 141 | // 送来DivStop信号，当EX模块送来DivStop信号时，DIV模块回到DivFree状态 142 | //************************************************************** 143 | `DivEnd:begin 144 | result_o <= {dividend[64:33],dividend[31:0]}; 145 | ready_o <= `DivResultReady; 146 | if(start_i == `DivStop) begin 147 | state <= `DivFree; 148 | ready_o <= `DivResultNotReady; 149 | result_o <= {`ZeroWord,`ZeroWord}; 150 | end 151 | end//DivEnd 152 | endcase//case(state) 153 | end//else 154 | end//always 155 | endmodule 156 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/openmips_min_sopc_timing_summary_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Tue May 10 14:29:49 2016 5 | | Host : LMX-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : report_timing_summary -warn_on_violation -max_paths 10 -file openmips_min_sopc_timing_summary_routed.rpt -rpx openmips_min_sopc_timing_summary_routed.rpx 7 | | Design : openmips_min_sopc 8 | | Device : 7a35ti-cpg236 9 | | Speed File : -1L PRODUCTION 1.14 2014-09-11 10 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 11 | 12 | Timing Summary Report 13 | 14 | ------------------------------------------------------------------------------------------------ 15 | | Timer Settings 16 | | -------------- 17 | ------------------------------------------------------------------------------------------------ 18 | 19 | Enable Multi Corner Analysis : Yes 20 | Enable Pessimism Removal : Yes 21 | Pessimism Removal Resolution : Nearest Common Node 22 | Enable Input Delay Default Clock : No 23 | Enable Preset / Clear Arcs : No 24 | Disable Flight Delays : No 25 | Ignore I/O Paths : No 26 | Timing Early Launch at Borrowing Latches : false 27 | 28 | Corner Analyze Analyze 29 | Name Max Paths Min Paths 30 | ------ --------- --------- 31 | Slow Yes Yes 32 | Fast Yes Yes 33 | 34 | 35 | 36 | check_timing report 37 | 38 | Table of Contents 39 | ----------------- 40 | 1. checking no_clock 41 | 2. checking constant_clock 42 | 3. checking pulse_width_clock 43 | 4. checking unconstrained_internal_endpoints 44 | 5. checking no_input_delay 45 | 6. checking no_output_delay 46 | 7. checking multiple_clock 47 | 8. checking generated_clocks 48 | 9. checking loops 49 | 10. checking partial_input_delay 50 | 11. checking partial_output_delay 51 | 12. checking latch_loops 52 | 53 | 1. checking no_clock 54 | -------------------- 55 | There are 810 register/latch pins with no clock driven by root clock pin: clk (HIGH) 56 | 57 | There are 2 register/latch pins with no clock driven by root clock pin: clk_div0/clk_div_reg/C (HIGH) 58 | 59 | 60 | 2. checking constant_clock 61 | -------------------------- 62 | There are 0 register/latch pins with constant_clock. 63 | 64 | 65 | 3. checking pulse_width_clock 66 | ----------------------------- 67 | There are 0 register/latch pins which need pulse_width check 68 | 69 | 70 | 4. checking unconstrained_internal_endpoints 71 | -------------------------------------------- 72 | There are 2748 pins that are not constrained for maximum delay. (HIGH) 73 | 74 | There are 0 pins that are not constrained for maximum delay due to constant clock. 75 | 76 | 77 | 5. checking no_input_delay 78 | -------------------------- 79 | There is 1 input port with no input delay specified. (HIGH) 80 | 81 | There are 0 input ports with no input delay but user has a false path constraint. 82 | 83 | 84 | 6. checking no_output_delay 85 | --------------------------- 86 | There are 11 ports with no output delay specified. (HIGH) 87 | 88 | There are 0 ports with no output delay but user has a false path constraint 89 | 90 | There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 91 | 92 | 93 | 7. checking multiple_clock 94 | -------------------------- 95 | There are 0 register/latch pins with multiple clocks. 96 | 97 | 98 | 8. checking generated_clocks 99 | ---------------------------- 100 | There are 0 generated clocks that are not connected to a clock source. 101 | 102 | 103 | 9. checking loops 104 | ----------------- 105 | There are 0 combinational loops in the design. 106 | 107 | 108 | 10. checking partial_input_delay 109 | -------------------------------- 110 | There are 0 input ports with partial input delay specified. 111 | 112 | 113 | 11. checking partial_output_delay 114 | --------------------------------- 115 | There are 0 ports with partial output delay specified. 116 | 117 | 118 | 12. checking latch_loops 119 | ------------------------ 120 | There are 0 combinational latch loops in the design through latch input 121 | 122 | 123 | 124 | ------------------------------------------------------------------------------------------------ 125 | | Design Timing Summary 126 | | --------------------- 127 | ------------------------------------------------------------------------------------------------ 128 | 129 | WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints 130 | ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 131 | NA NA NA NA NA NA NA NA NA NA NA NA 132 | 133 | 134 | There are no user specified timing constraints. 135 | 136 | 137 | ------------------------------------------------------------------------------------------------ 138 | | Clock Summary 139 | | ------------- 140 | ------------------------------------------------------------------------------------------------ 141 | 142 | 143 | ------------------------------------------------------------------------------------------------ 144 | | Intra Clock Table 145 | | ----------------- 146 | ------------------------------------------------------------------------------------------------ 147 | 148 | Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints 149 | ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 150 | 151 | 152 | ------------------------------------------------------------------------------------------------ 153 | | Inter Clock Table 154 | | ----------------- 155 | ------------------------------------------------------------------------------------------------ 156 | 157 | From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints 158 | ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- 159 | 160 | 161 | ------------------------------------------------------------------------------------------------ 162 | | Other Path Groups Table 163 | | ----------------------- 164 | ------------------------------------------------------------------------------------------------ 165 | 166 | Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints 167 | ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- 168 | 169 | 170 | ------------------------------------------------------------------------------------------------ 171 | | Timing Details 172 | | -------------- 173 | ------------------------------------------------------------------------------------------------ 174 | 175 | 176 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/openmips_min_sopc_utilization_synth.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ----------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Tue May 10 14:27:13 2016 5 | | Host : LMX-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : report_utilization -file openmips_min_sopc_utilization_synth.rpt -pb openmips_min_sopc_utilization_synth.pb 7 | | Design : openmips_min_sopc 8 | | Device : 7a35ticpg236-1L 9 | | Design State : Synthesized 10 | ----------------------------------------------------------------------------------------------------------------------------- 11 | 12 | Utilization Design Information 13 | 14 | Table of Contents 15 | ----------------- 16 | 1. Slice Logic 17 | 1.1 Summary of Registers by Type 18 | 2. Memory 19 | 3. DSP 20 | 4. IO and GT Specific 21 | 5. Clocking 22 | 6. Specific Feature 23 | 7. Primitives 24 | 8. Black Boxes 25 | 9. Instantiated Netlists 26 | 27 | 1. Slice Logic 28 | -------------- 29 | 30 | +----------------------------+------+-------+-----------+-------+ 31 | | Site Type | Used | Fixed | Available | Util% | 32 | +----------------------------+------+-------+-----------+-------+ 33 | | Slice LUTs* | 1761 | 0 | 20800 | 8.47 | 34 | | LUT as Logic | 1689 | 0 | 20800 | 8.12 | 35 | | LUT as Memory | 72 | 0 | 9600 | 0.75 | 36 | | LUT as Distributed RAM | 72 | 0 | | | 37 | | LUT as Shift Register | 0 | 0 | | | 38 | | Slice Registers | 668 | 0 | 41600 | 1.61 | 39 | | Register as Flip Flop | 668 | 0 | 41600 | 1.61 | 40 | | Register as Latch | 0 | 0 | 41600 | 0.00 | 41 | | F7 Muxes | 6 | 0 | 16300 | 0.04 | 42 | | F8 Muxes | 0 | 0 | 8150 | 0.00 | 43 | +----------------------------+------+-------+-----------+-------+ 44 | * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 45 | 46 | 47 | 1.1 Summary of Registers by Type 48 | -------------------------------- 49 | 50 | +-------+--------------+-------------+--------------+ 51 | | Total | Clock Enable | Synchronous | Asynchronous | 52 | +-------+--------------+-------------+--------------+ 53 | | 0 | _ | - | - | 54 | | 0 | _ | - | Set | 55 | | 0 | _ | - | Reset | 56 | | 0 | _ | Set | - | 57 | | 0 | _ | Reset | - | 58 | | 0 | Yes | - | - | 59 | | 0 | Yes | - | Set | 60 | | 0 | Yes | - | Reset | 61 | | 0 | Yes | Set | - | 62 | | 668 | Yes | Reset | - | 63 | +-------+--------------+-------------+--------------+ 64 | 65 | 66 | 2. Memory 67 | --------- 68 | 69 | +----------------+------+-------+-----------+-------+ 70 | | Site Type | Used | Fixed | Available | Util% | 71 | +----------------+------+-------+-----------+-------+ 72 | | Block RAM Tile | 0 | 0 | 50 | 0.00 | 73 | | RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | 74 | | RAMB18 | 0 | 0 | 100 | 0.00 | 75 | +----------------+------+-------+-----------+-------+ 76 | * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 77 | 78 | 79 | 3. DSP 80 | ------ 81 | 82 | +----------------+------+-------+-----------+-------+ 83 | | Site Type | Used | Fixed | Available | Util% | 84 | +----------------+------+-------+-----------+-------+ 85 | | DSPs | 4 | 0 | 90 | 4.44 | 86 | | DSP48E1 only | 4 | | | | 87 | +----------------+------+-------+-----------+-------+ 88 | 89 | 90 | 4. IO and GT Specific 91 | --------------------- 92 | 93 | +-----------------------------+------+-------+-----------+-------+ 94 | | Site Type | Used | Fixed | Available | Util% | 95 | +-----------------------------+------+-------+-----------+-------+ 96 | | Bonded IOB | 20 | 0 | 106 | 18.87 | 97 | | Bonded IPADs | 0 | 0 | 10 | 0.00 | 98 | | Bonded OPADs | 0 | 0 | 4 | 0.00 | 99 | | PHY_CONTROL | 0 | 0 | 5 | 0.00 | 100 | | PHASER_REF | 0 | 0 | 5 | 0.00 | 101 | | OUT_FIFO | 0 | 0 | 20 | 0.00 | 102 | | IN_FIFO | 0 | 0 | 20 | 0.00 | 103 | | IDELAYCTRL | 0 | 0 | 5 | 0.00 | 104 | | IBUFGDS | 0 | 0 | 104 | 0.00 | 105 | | GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | 106 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | 107 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | 108 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | 109 | | IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | 110 | | ILOGIC | 0 | 0 | 106 | 0.00 | 111 | | OLOGIC | 0 | 0 | 106 | 0.00 | 112 | +-----------------------------+------+-------+-----------+-------+ 113 | 114 | 115 | 5. Clocking 116 | ----------- 117 | 118 | +------------+------+-------+-----------+-------+ 119 | | Site Type | Used | Fixed | Available | Util% | 120 | +------------+------+-------+-----------+-------+ 121 | | BUFGCTRL | 1 | 0 | 32 | 3.13 | 122 | | BUFIO | 0 | 0 | 20 | 0.00 | 123 | | MMCME2_ADV | 0 | 0 | 5 | 0.00 | 124 | | PLLE2_ADV | 0 | 0 | 5 | 0.00 | 125 | | BUFMRCE | 0 | 0 | 10 | 0.00 | 126 | | BUFHCE | 0 | 0 | 72 | 0.00 | 127 | | BUFR | 0 | 0 | 20 | 0.00 | 128 | +------------+------+-------+-----------+-------+ 129 | 130 | 131 | 6. Specific Feature 132 | ------------------- 133 | 134 | +-------------+------+-------+-----------+-------+ 135 | | Site Type | Used | Fixed | Available | Util% | 136 | +-------------+------+-------+-----------+-------+ 137 | | BSCANE2 | 0 | 0 | 4 | 0.00 | 138 | | CAPTUREE2 | 0 | 0 | 1 | 0.00 | 139 | | DNA_PORT | 0 | 0 | 1 | 0.00 | 140 | | EFUSE_USR | 0 | 0 | 1 | 0.00 | 141 | | FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | 142 | | ICAPE2 | 0 | 0 | 2 | 0.00 | 143 | | PCIE_2_1 | 0 | 0 | 1 | 0.00 | 144 | | STARTUPE2 | 0 | 0 | 1 | 0.00 | 145 | | XADC | 0 | 0 | 1 | 0.00 | 146 | +-------------+------+-------+-----------+-------+ 147 | 148 | 149 | 7. Primitives 150 | ------------- 151 | 152 | +----------+------+---------------------+ 153 | | Ref Name | Used | Functional Category | 154 | +----------+------+---------------------+ 155 | | LUT6 | 720 | LUT | 156 | | FDRE | 668 | Flop & Latch | 157 | | LUT2 | 318 | LUT | 158 | | LUT5 | 302 | LUT | 159 | | LUT1 | 256 | LUT | 160 | | LUT4 | 203 | LUT | 161 | | LUT3 | 127 | LUT | 162 | | CARRY4 | 121 | CarryLogic | 163 | | RAMD32 | 108 | Distributed Memory | 164 | | RAMS32 | 36 | Distributed Memory | 165 | | OBUF | 12 | IO | 166 | | IBUF | 8 | IO | 167 | | MUXF7 | 6 | MuxFx | 168 | | DSP48E1 | 4 | Block Arithmetic | 169 | | BUFG | 1 | Clock | 170 | +----------+------+---------------------+ 171 | 172 | 173 | 8. Black Boxes 174 | -------------- 175 | 176 | +----------+------+ 177 | | Ref Name | Used | 178 | +----------+------+ 179 | 180 | 181 | 9. Instantiated Netlists 182 | ------------------------ 183 | 184 | +----------+------+ 185 | | Ref Name | Used | 186 | +----------+------+ 187 | 188 | 189 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/ISEWrap.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | // GLOBAL VARIABLES 8 | var ISEShell = new ActiveXObject( "WScript.Shell" ); 9 | var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); 10 | var ISERunDir = ""; 11 | var ISELogFile = "runme.log"; 12 | var ISELogFileStr = null; 13 | var ISELogEcho = true; 14 | var ISEOldVersionWSH = false; 15 | 16 | 17 | 18 | // BOOTSTRAP 19 | ISEInit(); 20 | 21 | 22 | 23 | // 24 | // ISE FUNCTIONS 25 | // 26 | function ISEInit() { 27 | 28 | // 1. RUN DIR setup 29 | var ISEScrFP = WScript.ScriptFullName; 30 | var ISEScrN = WScript.ScriptName; 31 | ISERunDir = 32 | ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); 33 | 34 | // 2. LOG file setup 35 | ISELogFileStr = ISEOpenFile( ISELogFile ); 36 | 37 | // 3. LOG echo? 38 | var ISEScriptArgs = WScript.Arguments; 39 | for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; 106 | ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); 107 | ISELogFileStr = ISEOpenFile( ISELogFile ); 108 | 109 | } else { // WSH 5.6 110 | 111 | // LAUNCH! 112 | ISEShell.CurrentDirectory = ISERunDir; 113 | 114 | // Redirect STDERR to STDOUT 115 | ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; 116 | var ISEProcess = ISEShell.Exec( ISECmdLine ); 117 | 118 | // BEGIN file creation 119 | var ISENetwork = WScript.CreateObject( "WScript.Network" ); 120 | var ISEHost = ISENetwork.ComputerName; 121 | var ISEUser = ISENetwork.UserName; 122 | var ISEPid = ISEProcess.ProcessID; 123 | var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); 124 | ISEBeginFile.WriteLine( "" ); 125 | ISEBeginFile.WriteLine( "" ); 126 | ISEBeginFile.WriteLine( " " ); 131 | ISEBeginFile.WriteLine( " " ); 132 | ISEBeginFile.WriteLine( "" ); 133 | ISEBeginFile.Close(); 134 | 135 | var ISEOutStr = ISEProcess.StdOut; 136 | var ISEErrStr = ISEProcess.StdErr; 137 | 138 | // WAIT for ISEStep to finish 139 | while ( ISEProcess.Status == 0 ) { 140 | 141 | // dump stdout then stderr - feels a little arbitrary 142 | while ( !ISEOutStr.AtEndOfStream ) { 143 | ISEStdOut( ISEOutStr.ReadLine() ); 144 | } 145 | 146 | WScript.Sleep( 100 ); 147 | } 148 | 149 | ISEExitCode = ISEProcess.ExitCode; 150 | } 151 | 152 | ISELogFileStr.Close(); 153 | 154 | // END/ERROR file creation 155 | if ( ISEExitCode != 0 ) { 156 | ISETouchFile( ISEStep, "error" ); 157 | 158 | } else { 159 | ISETouchFile( ISEStep, "end" ); 160 | } 161 | 162 | return ISEExitCode; 163 | } 164 | 165 | 166 | // 167 | // UTILITIES 168 | // 169 | function ISEStdOut( ISELine ) { 170 | 171 | ISELogFileStr.WriteLine( ISELine ); 172 | 173 | if ( ISELogEcho ) { 174 | WScript.StdOut.WriteLine( ISELine ); 175 | } 176 | } 177 | 178 | function ISEStdErr( ISELine ) { 179 | 180 | ISELogFileStr.WriteLine( ISELine ); 181 | 182 | if ( ISELogEcho ) { 183 | WScript.StdErr.WriteLine( ISELine ); 184 | } 185 | } 186 | 187 | function ISETouchFile( ISERoot, ISEStatus ) { 188 | 189 | var ISETFile = 190 | ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); 191 | ISETFile.Close(); 192 | } 193 | 194 | function ISEOpenFile( ISEFilename ) { 195 | 196 | // This function has been updated to deal with a problem seen in CR #870871. 197 | // In that case the user runs a script that runs impl_1, and then turns around 198 | // and runs impl_1 -to_step write_bitstream. That second run takes place in 199 | // the same directory, which means we may hit some of the same files, and in 200 | // particular, we will open the runme.log file. Even though this script closes 201 | // the file (now), we see cases where a subsequent attempt to open the file 202 | // fails. Perhaps the OS is slow to release the lock, or the disk comes into 203 | // play? In any case, we try to work around this by first waiting if the file 204 | // is already there for an arbitrary 5 seconds. Then we use a try-catch block 205 | // and try to open the file 10 times with a one second delay after each attempt. 206 | // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. 207 | // If there is an unrecognized exception when trying to open the file, we output 208 | // an error message and write details to an exception.log file. 209 | var ISEFullPath = ISERunDir + "/" + ISEFilename; 210 | if (ISEFileSys.FileExists(ISEFullPath)) { 211 | // File is already there. This could be a problem. Wait in case it is still in use. 212 | WScript.Sleep(5000); 213 | } 214 | var i; 215 | for (i = 0; i < 10; ++i) { 216 | try { 217 | return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); 218 | } catch (exception) { 219 | var error_code = exception.number & 0xFFFF; // The other bits are a facility code. 220 | if (error_code == 52) { // 52 is bad file name or number. 221 | // Wait a second and try again. 222 | WScript.Sleep(1000); 223 | continue; 224 | } else { 225 | WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 226 | var exceptionFilePath = ISERunDir + "/exception.log"; 227 | if (!ISEFileSys.FileExists(exceptionFilePath)) { 228 | WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); 229 | var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); 230 | exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 231 | exceptionFile.WriteLine("\tException name: " + exception.name); 232 | exceptionFile.WriteLine("\tException error code: " + error_code); 233 | exceptionFile.WriteLine("\tException message: " + exception.message); 234 | exceptionFile.Close(); 235 | } 236 | throw exception; 237 | } 238 | } 239 | } 240 | // If we reached this point, we failed to open the file after 10 attempts. 241 | // We need to error out. 242 | WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); 243 | WScript.Quit(1); 244 | } 245 | -------------------------------------------------------------------------------- /OpenMIPS.runs/synth_1/ISEWrap.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | // GLOBAL VARIABLES 8 | var ISEShell = new ActiveXObject( "WScript.Shell" ); 9 | var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); 10 | var ISERunDir = ""; 11 | var ISELogFile = "runme.log"; 12 | var ISELogFileStr = null; 13 | var ISELogEcho = true; 14 | var ISEOldVersionWSH = false; 15 | 16 | 17 | 18 | // BOOTSTRAP 19 | ISEInit(); 20 | 21 | 22 | 23 | // 24 | // ISE FUNCTIONS 25 | // 26 | function ISEInit() { 27 | 28 | // 1. RUN DIR setup 29 | var ISEScrFP = WScript.ScriptFullName; 30 | var ISEScrN = WScript.ScriptName; 31 | ISERunDir = 32 | ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); 33 | 34 | // 2. LOG file setup 35 | ISELogFileStr = ISEOpenFile( ISELogFile ); 36 | 37 | // 3. LOG echo? 38 | var ISEScriptArgs = WScript.Arguments; 39 | for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; 106 | ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); 107 | ISELogFileStr = ISEOpenFile( ISELogFile ); 108 | 109 | } else { // WSH 5.6 110 | 111 | // LAUNCH! 112 | ISEShell.CurrentDirectory = ISERunDir; 113 | 114 | // Redirect STDERR to STDOUT 115 | ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; 116 | var ISEProcess = ISEShell.Exec( ISECmdLine ); 117 | 118 | // BEGIN file creation 119 | var ISENetwork = WScript.CreateObject( "WScript.Network" ); 120 | var ISEHost = ISENetwork.ComputerName; 121 | var ISEUser = ISENetwork.UserName; 122 | var ISEPid = ISEProcess.ProcessID; 123 | var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); 124 | ISEBeginFile.WriteLine( "" ); 125 | ISEBeginFile.WriteLine( "" ); 126 | ISEBeginFile.WriteLine( " " ); 131 | ISEBeginFile.WriteLine( " " ); 132 | ISEBeginFile.WriteLine( "" ); 133 | ISEBeginFile.Close(); 134 | 135 | var ISEOutStr = ISEProcess.StdOut; 136 | var ISEErrStr = ISEProcess.StdErr; 137 | 138 | // WAIT for ISEStep to finish 139 | while ( ISEProcess.Status == 0 ) { 140 | 141 | // dump stdout then stderr - feels a little arbitrary 142 | while ( !ISEOutStr.AtEndOfStream ) { 143 | ISEStdOut( ISEOutStr.ReadLine() ); 144 | } 145 | 146 | WScript.Sleep( 100 ); 147 | } 148 | 149 | ISEExitCode = ISEProcess.ExitCode; 150 | } 151 | 152 | ISELogFileStr.Close(); 153 | 154 | // END/ERROR file creation 155 | if ( ISEExitCode != 0 ) { 156 | ISETouchFile( ISEStep, "error" ); 157 | 158 | } else { 159 | ISETouchFile( ISEStep, "end" ); 160 | } 161 | 162 | return ISEExitCode; 163 | } 164 | 165 | 166 | // 167 | // UTILITIES 168 | // 169 | function ISEStdOut( ISELine ) { 170 | 171 | ISELogFileStr.WriteLine( ISELine ); 172 | 173 | if ( ISELogEcho ) { 174 | WScript.StdOut.WriteLine( ISELine ); 175 | } 176 | } 177 | 178 | function ISEStdErr( ISELine ) { 179 | 180 | ISELogFileStr.WriteLine( ISELine ); 181 | 182 | if ( ISELogEcho ) { 183 | WScript.StdErr.WriteLine( ISELine ); 184 | } 185 | } 186 | 187 | function ISETouchFile( ISERoot, ISEStatus ) { 188 | 189 | var ISETFile = 190 | ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); 191 | ISETFile.Close(); 192 | } 193 | 194 | function ISEOpenFile( ISEFilename ) { 195 | 196 | // This function has been updated to deal with a problem seen in CR #870871. 197 | // In that case the user runs a script that runs impl_1, and then turns around 198 | // and runs impl_1 -to_step write_bitstream. That second run takes place in 199 | // the same directory, which means we may hit some of the same files, and in 200 | // particular, we will open the runme.log file. Even though this script closes 201 | // the file (now), we see cases where a subsequent attempt to open the file 202 | // fails. Perhaps the OS is slow to release the lock, or the disk comes into 203 | // play? In any case, we try to work around this by first waiting if the file 204 | // is already there for an arbitrary 5 seconds. Then we use a try-catch block 205 | // and try to open the file 10 times with a one second delay after each attempt. 206 | // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. 207 | // If there is an unrecognized exception when trying to open the file, we output 208 | // an error message and write details to an exception.log file. 209 | var ISEFullPath = ISERunDir + "/" + ISEFilename; 210 | if (ISEFileSys.FileExists(ISEFullPath)) { 211 | // File is already there. This could be a problem. Wait in case it is still in use. 212 | WScript.Sleep(5000); 213 | } 214 | var i; 215 | for (i = 0; i < 10; ++i) { 216 | try { 217 | return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); 218 | } catch (exception) { 219 | var error_code = exception.number & 0xFFFF; // The other bits are a facility code. 220 | if (error_code == 52) { // 52 is bad file name or number. 221 | // Wait a second and try again. 222 | WScript.Sleep(1000); 223 | continue; 224 | } else { 225 | WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 226 | var exceptionFilePath = ISERunDir + "/exception.log"; 227 | if (!ISEFileSys.FileExists(exceptionFilePath)) { 228 | WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); 229 | var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); 230 | exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 231 | exceptionFile.WriteLine("\tException name: " + exception.name); 232 | exceptionFile.WriteLine("\tException error code: " + error_code); 233 | exceptionFile.WriteLine("\tException message: " + exception.message); 234 | exceptionFile.Close(); 235 | } 236 | throw exception; 237 | } 238 | } 239 | } 240 | // If we reached this point, we failed to open the file after 10 attempts. 241 | // We need to error out. 242 | WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); 243 | WScript.Quit(1); 244 | } 245 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/openmips_min_sopc_clock_utilization_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Tue May 10 14:29:52 2016 5 | | Host : LMX-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : report_clock_utilization -file openmips_min_sopc_clock_utilization_routed.rpt 7 | | Design : openmips_min_sopc 8 | | Device : 7a35ti-cpg236 9 | | Speed File : -1L PRODUCTION 1.14 2014-09-11 10 | | Temperature Grade : C 11 | ---------------------------------------------------------------------------------------------------- 12 | 13 | Clock Utilization Report 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. Clock Primitive Utilization 18 | 2. Details of Global Clocks 19 | 3. Details of Regional Clocks 20 | 4. Details of Multi-Regional Clocks 21 | 5. Details of I/O Clocks 22 | 6. Details of Local Clocks 23 | 7. Clock Regions : Key Resource Utilization 24 | 8. Net wise resources used in clock region X0Y0 25 | 26 | 1. Clock Primitive Utilization 27 | ------------------------------ 28 | 29 | +-------+------+-----------+-----------+ 30 | | Type | Used | Available | Num Fixed | 31 | +-------+------+-----------+-----------+ 32 | | BUFG | 1 | 32 | 0 | 33 | | BUFH | 0 | 72 | 0 | 34 | | BUFIO | 0 | 20 | 0 | 35 | | MMCM | 0 | 5 | 0 | 36 | | PLL | 0 | 5 | 0 | 37 | | BUFR | 0 | 20 | 0 | 38 | | BUFMR | 0 | 10 | 0 | 39 | +-------+------+-----------+-----------+ 40 | 41 | 42 | 2. Details of Global Clocks 43 | --------------------------- 44 | 45 | +-------+--------------------+---------------+--------------+-------+ 46 | | | | | Num Loads | | 47 | +-------+--------------------+---------------+------+-------+-------+ 48 | | Index | BUFG Cell | Net Name | BELs | Sites | Fixed | 49 | +-------+--------------------+---------------+------+-------+-------+ 50 | | 1 | clk_IBUF_BUFG_inst | clk_IBUF_BUFG | 810 | 294 | no | 51 | +-------+--------------------+---------------+------+-------+-------+ 52 | 53 | 54 | 3. Details of Regional Clocks 55 | ----------------------------- 56 | 57 | 4. Details of Multi-Regional Clocks 58 | ----------------------------------- 59 | 60 | 5. Details of I/O Clocks 61 | ------------------------ 62 | 63 | 6. Details of Local Clocks 64 | -------------------------- 65 | 66 | +-------+----------------------+-------------------------+--------------+-------+ 67 | | | | | Num Loads | | 68 | +-------+----------------------+-------------------------+------+-------+-------+ 69 | | Index | Local Clk Src | Net Name | BELs | Sites | Fixed | 70 | +-------+----------------------+-------------------------+------+-------+-------+ 71 | | 1 | clk_div0/clk_div_reg | clk_div0/count_reg[1]_0 | 3 | 2 | no | 72 | +-------+----------------------+-------------------------+------+-------+-------+ 73 | 74 | 75 | 7. Clock Regions : Key Resource Utilization 76 | ------------------------------------------- 77 | 78 | +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ 79 | | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E1 | 80 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ 81 | | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | 82 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ 83 | | X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 666 | 9600 | 144 | 1600 | 0 | 20 | 0 | 10 | 4 | 20 | 84 | | X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2 | 12000 | 0 | 1800 | 0 | 40 | 0 | 20 | 0 | 20 | 85 | | X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 9600 | 0 | 1600 | 0 | 20 | 0 | 10 | 0 | 20 | 86 | | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 12000 | 0 | 1800 | 0 | 40 | 0 | 20 | 0 | 20 | 87 | | X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 14400 | 0 | 1600 | 0 | 20 | 0 | 10 | 0 | 20 | 88 | | X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 7600 | 0 | 1200 | 0 | 10 | 0 | 5 | 0 | 20 | 89 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ 90 | * RAMB36 site can be used as two RAMB18/FIFO18 sites. 91 | 92 | 93 | 8. Net wise resources used in clock region X0Y0 94 | ----------------------------------------------- 95 | 96 | +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ 97 | | Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | Clock Net Name | 98 | +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ 99 | | BUFG | BUFHCE_X0Y8 | no | 0 | 0 | 0 | 0 | 0 | 0 | 666 | 144 | 0 | clk_IBUF_BUFG | 100 | +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ 101 | 102 | 103 | 104 | # Location of BUFG Primitives 105 | set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] 106 | 107 | # Location of IO Clock Primitives 108 | 109 | # Location of MMCM Clock Primitives 110 | 111 | # Location of BUFH Clock Primitives 112 | 113 | # Location of BUFR Clock Primitives 114 | 115 | # Location of BUFMR Clock Primitives 116 | 117 | # Location of PLL Clock Primitives 118 | 119 | # Location of IO Primitives which is load of clock spine 120 | 121 | # Location of clock ports 122 | set_property LOC IOB_X1Y26 [get_ports clk] 123 | 124 | # Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" 125 | #startgroup 126 | create_pblock {CLKAG_clk_IBUF_BUFG} 127 | add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] 128 | resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} 129 | #endgroup 130 | 131 | # Clock net "clk_div0/count_reg[1]_0" driven by instance "clk_div0/clk_div_reg" located at site "SLICE_X30Y25" 132 | #startgroup 133 | create_pblock {CLKAG_clk_div0/count_reg[1]_0} 134 | add_cells_to_pblock [get_pblocks {CLKAG_clk_div0/count_reg[1]_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_div0/count_reg[1]_0"}]]] 135 | resize_pblock [get_pblocks {CLKAG_clk_div0/count_reg[1]_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} 136 | #endgroup 137 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/openmips_min_sopc_drc_opted.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Tue May 10 14:28:34 2016 5 | | Host : LMX-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : report_drc 7 | ------------------------------------------------------------------------------------ 8 | 9 | Report DRC 10 | 11 | Table of Contents 12 | ----------------- 13 | 1. REPORT SUMMARY 14 | 2. REPORT DETAILS 15 | 16 | 1. REPORT SUMMARY 17 | ----------------- 18 | Netlist: netlist 19 | Floorplan: design_1 20 | Design limits: 21 | Ruledeck: default 22 | Max violations: 23 | Violations found: 18 24 | 25 | 2. REPORT DETAILS 26 | ----------------- 27 | BUFC-1#1 Warning 28 | Input Buffer Connections 29 | Input buffer write_IBUF_inst has no loads. An input buffer must drive an internal load. 30 | Related violations: 31 | 32 | CFGBVS-1#1 Warning 33 | Missing CFGBVS and CONFIG_VOLTAGE Design Properties 34 | Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: 35 | 36 | set_property CFGBVS value1 [current_design] 37 | #where value1 is either VCCO or GND 38 | 39 | set_property CONFIG_VOLTAGE value2 [current_design] 40 | #where value2 is the voltage provided to configuration bank 0 41 | 42 | Refer to the device configuration user guide for more information. 43 | Related violations: 44 | 45 | DPIP-1#1 Warning 46 | Input pipelining 47 | DSP openmips0/ex0/hilo_temp__0 input openmips0/ex0/hilo_temp__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. 48 | Related violations: 49 | 50 | DPIP-1#2 Warning 51 | Input pipelining 52 | DSP openmips0/ex0/hilo_temp__0 input openmips0/ex0/hilo_temp__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 53 | Related violations: 54 | 55 | DPIP-1#3 Warning 56 | Input pipelining 57 | DSP openmips0/ex0/hilo_temp__0__0 input openmips0/ex0/hilo_temp__0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. 58 | Related violations: 59 | 60 | DPIP-1#4 Warning 61 | Input pipelining 62 | DSP openmips0/ex0/hilo_temp__0__0 input openmips0/ex0/hilo_temp__0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 63 | Related violations: 64 | 65 | DPIP-1#5 Warning 66 | Input pipelining 67 | DSP openmips0/ex0/hilo_temp__1 input openmips0/ex0/hilo_temp__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. 68 | Related violations: 69 | 70 | DPIP-1#6 Warning 71 | Input pipelining 72 | DSP openmips0/ex0/hilo_temp__1 input openmips0/ex0/hilo_temp__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 73 | Related violations: 74 | 75 | DPIP-1#7 Warning 76 | Input pipelining 77 | DSP openmips0/ex0/hilo_temp__2 input openmips0/ex0/hilo_temp__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. 78 | Related violations: 79 | 80 | DPIP-1#8 Warning 81 | Input pipelining 82 | DSP openmips0/ex0/hilo_temp__2 input openmips0/ex0/hilo_temp__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 83 | Related violations: 84 | 85 | DPOP-1#1 Warning 86 | PREG Output pipelining 87 | DSP openmips0/ex0/hilo_temp__0 output openmips0/ex0/hilo_temp__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 88 | Related violations: 89 | 90 | DPOP-1#2 Warning 91 | PREG Output pipelining 92 | DSP openmips0/ex0/hilo_temp__0__0 output openmips0/ex0/hilo_temp__0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 93 | Related violations: 94 | 95 | DPOP-1#3 Warning 96 | PREG Output pipelining 97 | DSP openmips0/ex0/hilo_temp__1 output openmips0/ex0/hilo_temp__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 98 | Related violations: 99 | 100 | DPOP-1#4 Warning 101 | PREG Output pipelining 102 | DSP openmips0/ex0/hilo_temp__2 output openmips0/ex0/hilo_temp__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 103 | Related violations: 104 | 105 | DPOP-2#1 Warning 106 | MREG Output pipelining 107 | DSP openmips0/ex0/hilo_temp__0 multiplier stage openmips0/ex0/hilo_temp__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. 108 | Related violations: 109 | 110 | DPOP-2#2 Warning 111 | MREG Output pipelining 112 | DSP openmips0/ex0/hilo_temp__0__0 multiplier stage openmips0/ex0/hilo_temp__0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. 113 | Related violations: 114 | 115 | DPOP-2#3 Warning 116 | MREG Output pipelining 117 | DSP openmips0/ex0/hilo_temp__1 multiplier stage openmips0/ex0/hilo_temp__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. 118 | Related violations: 119 | 120 | DPOP-2#4 Warning 121 | MREG Output pipelining 122 | DSP openmips0/ex0/hilo_temp__2 multiplier stage openmips0/ex0/hilo_temp__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. 123 | Related violations: 124 | 125 | 126 | -------------------------------------------------------------------------------- /OpenMIPS.runs/impl_1/openmips_min_sopc_drc_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Tue May 10 14:29:47 2016 5 | | Host : LMX-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : report_drc 7 | ------------------------------------------------------------------------------------ 8 | 9 | Report DRC 10 | 11 | Table of Contents 12 | ----------------- 13 | 1. REPORT SUMMARY 14 | 2. REPORT DETAILS 15 | 16 | 1. REPORT SUMMARY 17 | ----------------- 18 | Netlist: netlist 19 | Floorplan: design_1 20 | Design limits: 21 | Ruledeck: default 22 | Max violations: 23 | Violations found: 19 24 | 25 | 2. REPORT DETAILS 26 | ----------------- 27 | BUFC-1#1 Warning 28 | Input Buffer Connections 29 | Input buffer write_IBUF_inst has no loads. An input buffer must drive an internal load. 30 | Related violations: 31 | 32 | CFGBVS-1#1 Warning 33 | Missing CFGBVS and CONFIG_VOLTAGE Design Properties 34 | Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: 35 | 36 | set_property CFGBVS value1 [current_design] 37 | #where value1 is either VCCO or GND 38 | 39 | set_property CONFIG_VOLTAGE value2 [current_design] 40 | #where value2 is the voltage provided to configuration bank 0 41 | 42 | Refer to the device configuration user guide for more information. 43 | Related violations: 44 | 45 | DPIP-1#1 Warning 46 | Input pipelining 47 | DSP openmips0/ex0/hilo_temp__0 input openmips0/ex0/hilo_temp__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. 48 | Related violations: 49 | 50 | DPIP-1#2 Warning 51 | Input pipelining 52 | DSP openmips0/ex0/hilo_temp__0 input openmips0/ex0/hilo_temp__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 53 | Related violations: 54 | 55 | DPIP-1#3 Warning 56 | Input pipelining 57 | DSP openmips0/ex0/hilo_temp__0__0 input openmips0/ex0/hilo_temp__0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. 58 | Related violations: 59 | 60 | DPIP-1#4 Warning 61 | Input pipelining 62 | DSP openmips0/ex0/hilo_temp__0__0 input openmips0/ex0/hilo_temp__0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 63 | Related violations: 64 | 65 | DPIP-1#5 Warning 66 | Input pipelining 67 | DSP openmips0/ex0/hilo_temp__1 input openmips0/ex0/hilo_temp__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. 68 | Related violations: 69 | 70 | DPIP-1#6 Warning 71 | Input pipelining 72 | DSP openmips0/ex0/hilo_temp__1 input openmips0/ex0/hilo_temp__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 73 | Related violations: 74 | 75 | DPIP-1#7 Warning 76 | Input pipelining 77 | DSP openmips0/ex0/hilo_temp__2 input openmips0/ex0/hilo_temp__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. 78 | Related violations: 79 | 80 | DPIP-1#8 Warning 81 | Input pipelining 82 | DSP openmips0/ex0/hilo_temp__2 input openmips0/ex0/hilo_temp__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. 83 | Related violations: 84 | 85 | DPOP-1#1 Warning 86 | PREG Output pipelining 87 | DSP openmips0/ex0/hilo_temp__0 output openmips0/ex0/hilo_temp__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 88 | Related violations: 89 | 90 | DPOP-1#2 Warning 91 | PREG Output pipelining 92 | DSP openmips0/ex0/hilo_temp__0__0 output openmips0/ex0/hilo_temp__0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 93 | Related violations: 94 | 95 | DPOP-1#3 Warning 96 | PREG Output pipelining 97 | DSP openmips0/ex0/hilo_temp__1 output openmips0/ex0/hilo_temp__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 98 | Related violations: 99 | 100 | DPOP-1#4 Warning 101 | PREG Output pipelining 102 | DSP openmips0/ex0/hilo_temp__2 output openmips0/ex0/hilo_temp__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. 103 | Related violations: 104 | 105 | DPOP-2#1 Warning 106 | MREG Output pipelining 107 | DSP openmips0/ex0/hilo_temp__0 multiplier stage openmips0/ex0/hilo_temp__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. 108 | Related violations: 109 | 110 | DPOP-2#2 Warning 111 | MREG Output pipelining 112 | DSP openmips0/ex0/hilo_temp__0__0 multiplier stage openmips0/ex0/hilo_temp__0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. 113 | Related violations: 114 | 115 | DPOP-2#3 Warning 116 | MREG Output pipelining 117 | DSP openmips0/ex0/hilo_temp__1 multiplier stage openmips0/ex0/hilo_temp__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. 118 | Related violations: 119 | 120 | DPOP-2#4 Warning 121 | MREG Output pipelining 122 | DSP openmips0/ex0/hilo_temp__2 multiplier stage openmips0/ex0/hilo_temp__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. 123 | Related violations: 124 | 125 | RTSTAT-10#1 Warning 126 | No routable loads 127 | 1 net(s) have no routable loads. The problem bus(es) and/or net(s) are write_IBUF. 128 | Related violations: 129 | 130 | 131 | -------------------------------------------------------------------------------- /OpenMIPS.srcs/sources_1/new/cp0_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //****************************************************************************** 4 | // 协处理器CP0 5 | // 只实现了CP0中的Count、Compare、Status、Cause、EPC、PRId、Config7个寄存器的部分 6 | //功能 7 | //****************************************************************************** 8 | 9 | `include "defines.v" 10 | 11 | module cp0_reg( 12 | input wire rst, 13 | input wire clk, 14 | 15 | input wire we_i, //是否要写CP0中的寄存器 16 | input wire[4:0] waddr_i, //要写入的CP0寄存器的地址 17 | input wire[`RegBus] data_i, //要写入CP0中寄存器的数据 18 | 19 | input wire[4:0] raddr_i, //要读取的CP0寄存器的地址 20 | output reg[`RegBus] data_o, //读出的CP0某个寄存器的值 21 | 22 | //异常相关输入接口 23 | input wire[31:0] excepttype_i, //最终的异常类型 24 | input wire[5:0] int_i, //6个外部硬件中断输入 25 | input wire[`InstAddrBus] current_inst_addr_i, //发生异常的指令地址 26 | input wire is_in_delayslot_i, //发生异常的指令是否是延迟槽指令 27 | 28 | output reg[`RegBus] count_o, //Count寄存器的值 29 | output reg[`RegBus] compare_o, //Compare寄存器的值 30 | output reg[`RegBus] status_o, //Status寄存器的值 31 | output reg[`RegBus] cause_o, //Cause寄存器的值 32 | output reg[`RegBus] epc_o, //EPC寄存器的值 33 | output reg[`RegBus] config_o, //Config寄存器的值 34 | output reg[`RegBus] prid_o, //PRId寄存器的值 35 | 36 | output reg timer_int_o //是否有定时中断发生 37 | ); 38 | 39 | //****************************************************************************** 40 | // 对CP0中寄存器的写操作：时序逻辑 41 | // PRId、Config不可以写，Cause寄存器只有其中的IP[1:0]、IV、WP三个字段可写 42 | //****************************************************************************** 43 | always @ ( posedge clk ) begin 44 | if(rst == `RstEnable) begin 45 | 46 | //Count寄存器的初始值 47 | count_o <= `ZeroWord; 48 | 49 | //Compare寄存器的初始值 50 | compare_o <= `ZeroWord; 51 | 52 | //Status寄存器的初始值：其中CU字段为0001，表示协处理器CP0存在 53 | status_o <= 32'b0001_0000_0000_0000_0000_0000_0000_0000; 54 | 55 | //Cause寄存器的初始值 56 | cause_o <= `ZeroWord; 57 | 58 | //EPC寄存器的初始值 59 | epc_o <= `ZeroWord; 60 | 61 | //Config寄存器的初始值：其中BE字段为1，表示工作在大端模式(MSB) 62 | config_o <= 32'b0000_0000_0000_0000_1000_0000_0000_0000; 63 | 64 | //PRId寄存器的初始值：其中制作者是L，对应的是0x48(自行定义的)； 65 | //类型是0x1，表示是基本类型；版本号是1.0 66 | prid_o <= 32'b0000_0000_0100_1100_0000_0001_0000_0010; 67 | 68 | timer_int_o <= `InterruptNotAssert; 69 | 70 | end else begin 71 | 72 | count_o <= count_o + 1; //Count寄存器的值在每个时钟周期加1 73 | cause_o[15:10] <= int_i; //Cause寄存器的10-15位保存外部中断声明 74 | 75 | //当Compare寄存器不为0，且Count寄存器的值等于Compare寄存器的值时， 76 | //将输出信号timer_int_o置为1，表示时钟中断发生 77 | if(compare_o != `ZeroWord && count_o == compare_o) begin 78 | timer_int_o <= `InterruptAssert; 79 | end 80 | 81 | if(we_i == `WriteEnable) begin 82 | case(waddr_i) 83 | `CP0_REG_COUNT:begin //写Count寄存器 84 | count_o <= data_i; 85 | end 86 | `CP0_REG_COMPARE:begin //写Compare寄存器 87 | compare_o <= data_i; 88 | //表示取消时钟中断的声明 89 | timer_int_o <= `InterruptNotAssert; 90 | end 91 | `CP0_REG_STATUS:begin //写Status寄存器 92 | status_o <= data_i; 93 | end 94 | `CP0_REG_EPC:begin //写EPC寄存器 95 | epc_o <= data_i; 96 | end 97 | `CP0_REG_CAUSE:begin //写Cause寄存器 98 | //Cause寄存器只有IP[1:0]、IV、WP字段是可写的 99 | cause_o[9:8] <= data_i[9:8]; //IP[1:0] 100 | cause_o[23] <= data_i[23]; //IV 101 | cause_o[22] <= data_i[22]; //WP 102 | end 103 | endcase 104 | end//if(we_i == `WriteEnable) 105 | 106 | case(excepttype_i) 107 | 32'h0000_0001:begin //外部中断 108 | //已经在访存阶段判断了是否处于异常级 109 | if(is_in_delayslot_i == `InDelaySlot) begin 110 | epc_o <= current_inst_addr_i - 4; 111 | cause_o[31] <= 1'b1; //Cause寄存器的BD字段 112 | end else begin 113 | epc_o <= current_inst_addr_i; 114 | cause_o[31] <= 1'b0; 115 | end 116 | status_o[1] <= 1'b1; //Status寄存器的EXL字段 117 | cause_o[6:2] <= 5'b00000; //Cause寄存器的ExcCode字段 118 | end 119 | 32'h0000_0008:begin //系统调用异常syscall 120 | //Status[1]为EXL字段，表示是否处于异常级 121 | if(status_o[1] == 1'b0) begin 122 | if(is_in_delayslot_i == `InDelaySlot) begin 123 | epc_o <= current_inst_addr_i - 4; 124 | cause_o[31] <= 1'b1; 125 | end else begin 126 | epc_o <= current_inst_addr_i; 127 | cause_o[31] <= 1'b0; 128 | end 129 | end 130 | //如果EXL字段为1，表示当前已经处于异常级了，又发生了新的异常，那么 131 | //只需要将异常原因保存到Cause寄存器的ExcCode字段 132 | status_o[1] <= 1'b1; 133 | cause_o[6:2] <= 5'b01000; 134 | end 135 | 32'h0000_000a:begin //无效指令异常 136 | if(status_o[1] == 1'b0) begin 137 | if(is_in_delayslot_i == `InDelaySlot) begin 138 | epc_o <= current_inst_addr_i - 4; 139 | cause_o[31] <= 1'b1; 140 | end else begin 141 | epc_o <= current_inst_addr_i; 142 | cause_o[31] <= 1'b0; 143 | end 144 | end 145 | status_o[1] <= 1'b1; 146 | cause_o[6:2] <= 5'b01010; 147 | end 148 | 32'h0000_000d:begin //自陷异常 149 | if(status_o[1] == 1'b0) begin 150 | if(is_in_delayslot_i == `InDelaySlot) begin 151 | epc_o <= current_inst_addr_i - 4; 152 | cause_o[31] <= 1'b1; 153 | end else begin 154 | epc_o <= current_inst_addr_i; 155 | cause_o[31] <= 1'b0; 156 | end 157 | end 158 | status_o[1] <= 1'b1; 159 | cause_o[6:2] <= 5'b01101; 160 | end 161 | 32'h0000_000c:begin //溢出异常 162 | if(status_o[1] <= 1'b0) begin 163 | if(is_in_delayslot_i == `InDelaySlot) begin 164 | epc_o <= current_inst_addr_i - 4; 165 | cause_o[31] <= 1'b1; 166 | end else begin 167 | epc_o <= current_inst_addr_i; 168 | cause_o[31] <= 1'b0; 169 | end 170 | end 171 | status_o[1] <= 1'b1; 172 | cause_o[6:2] <= 5'b01100; 173 | end 174 | 32'h0000_000e:begin //异常返回指令eret 175 | status_o[1] <= 1'b0; 176 | end 177 | default:begin 178 | end 179 | endcase 180 | end//else 181 | end 182 | 183 | 184 | //****************************************************************************** 185 | // 对CP0中寄存器的读操作：组合逻辑 186 | //****************************************************************************** 187 | always @ ( * ) begin 188 | if(rst == `RstEnable) begin 189 | data_o <= `ZeroWord; 190 | end else begin 191 | case(raddr_i) 192 | `CP0_REG_COUNT:begin //读Count寄存器 193 | data_o <= count_o; 194 | end 195 | `CP0_REG_COMPARE:begin //读Compare寄存器 196 | data_o <= compare_o; 197 | end 198 | `CP0_REG_STATUS:begin //读Status寄存器 199 | data_o <= status_o; 200 | end 201 | `CP0_REG_CAUSE:begin //读Cause寄存器 202 | data_o <= cause_o; 203 | end 204 | `CP0_REG_EPC:begin //读EPC寄存器 205 | data_o <= epc_o; 206 | end 207 | `CP0_REG_PRId:begin //读PRId寄存器 208 | data_o <= prid_o; 209 | end 210 | `CP0_REG_CONFIG:begin //读Config寄存器 211 | data_o <= config_o; 212 | end 213 | default:begin 214 | end 215 | endcase 216 | end//else 217 | end 218 | 219 | endmodule 220 | --------------------------------------------------------------------------------