├── .gitattributes ├── .gitignore ├── .idea ├── other.xml └── vcs.xml ├── LICENSE ├── README.md ├── docs ├── logo.png ├── workflow.pdf ├── workflow.png ├── workflow.pptx └── worklow.pdf ├── in ├── csv │ ├── xc7z030ffg676pkg_IC44_IBERT_info.csv │ ├── xcku095ffvb2104pkg_IC39_IBERT_info.csv │ ├── xcvu160flgc2104pkg_IC15_IBERT_info.csv │ ├── xcvu160flgc2104pkg_IC4_IBERT_info.csv │ ├── xcvu9pflgc2104pkg_IC15_IBERT_info.csv │ └── xcvu9pflgc2104pkg_IC4_IBERT_info.csv ├── tcl │ ├── ScanRunTemplate.tcl │ └── SetIBERTRunTemplate.tcl └── tex │ ├── ScanTemplate.tex │ ├── figEyeSummaryTemplate01.tex │ ├── figEyeSummaryTemplate04.tex │ ├── figEyeSummaryTemplate08.tex │ ├── figEyeSummaryTemplate12.tex │ └── figEyeSummaryTemplate28.tex ├── latex ├── MUCTPI_links.pdf ├── ieeemask.png ├── not_found.docx ├── not_found.pdf ├── report.pdf └── report.tex ├── out ├── pdf │ ├── Horizontal PercentagePlotRateV1-12.8Gbps.pdf │ ├── Horizontal PercentagePlotRateV1-6.4Gbps.pdf │ ├── Horizontal PercentagePlotRateV2-12.8Gbps.pdf │ ├── Horizontal PercentagePlotRateV2-6.4Gbps.pdf │ ├── Horizontal PercentageRateV1-12.8Gbps.pdf │ ├── Horizontal PercentageRateV1-6.4Gbps.pdf │ ├── Horizontal PercentageRateV2-12.8Gbps.pdf │ ├── Horizontal PercentageRateV2-6.4Gbps.pdf │ ├── Open Area PercentagePlotRateV1-12.8Gbps.pdf │ ├── Open Area PercentagePlotRateV1-6.4Gbps.pdf │ ├── Open Area PercentagePlotRateV2-12.8Gbps.pdf │ ├── Open Area PercentagePlotRateV2-6.4Gbps.pdf │ ├── Open Area PercentageRateV1-12.8Gbps.pdf │ ├── Open Area PercentageRateV1-6.4Gbps.pdf │ ├── Open Area PercentageRateV2-12.8Gbps.pdf │ ├── Open Area PercentageRateV2-6.4Gbps.pdf │ ├── ScatterPlotRateV1-12.8.pdf │ ├── ScatterPlotRateV1-6.4.pdf │ ├── ScatterPlotRateV2-12.8.pdf │ ├── ScatterPlotRateV2-6.4.pdf │ ├── Vertical PercentagePlotRateV1-12.8Gbps.pdf │ ├── Vertical PercentagePlotRateV1-6.4Gbps.pdf │ ├── Vertical PercentagePlotRateV2-12.8Gbps.pdf │ ├── Vertical PercentagePlotRateV2-6.4Gbps.pdf │ ├── Vertical PercentageRateV1-12.8Gbps.pdf │ ├── Vertical PercentageRateV1-6.4Gbps.pdf │ ├── Vertical PercentageRateV2-12.8Gbps.pdf │ └── Vertical PercentageRateV2-6.4Gbps.pdf ├── tcl │ ├── ScanRun 0.tcl │ ├── ScanRun 1.tcl │ ├── ScanRun 2.tcl │ ├── ScanRun 3.tcl │ ├── ScanRun 4.tcl │ ├── SetIBERTRun 0.tcl │ ├── SetIBERTRun 1.tcl │ ├── SetIBERTRun 2.tcl │ ├── SetIBERTRun 3.tcl │ ├── SetIBERTRun 4.tcl │ ├── SetMSP Rx.tcl │ ├── create_links_IC39_IC15.tcl │ ├── create_links_IC39_IC4.tcl │ ├── create_links_J1_J1.tcl │ ├── create_links_J3_J3.tcl │ ├── create_links_TX1_RX11.tcl │ ├── create_links_TX1_RX13.tcl │ ├── create_links_TX1_RX16.tcl │ ├── create_links_TX1_RX18.tcl │ ├── create_links_TX2_RX10.tcl │ ├── create_links_TX2_RX12.tcl │ ├── create_links_TX2_RX15.tcl │ ├── create_links_TX2_RX17.tcl │ ├── create_links_TX3_RX2.tcl │ ├── create_links_TX3_RX4.tcl │ ├── create_links_TX3_RX7.tcl │ ├── create_links_TX3_RX9.tcl │ ├── create_links_TX4_RX1.tcl │ ├── create_links_TX4_RX3.tcl │ ├── create_links_TX4_RX6.tcl │ ├── create_links_TX4_RX8.tcl │ ├── create_links_TX5_RX14.tcl │ ├── create_links_TX5_RX5.tcl │ ├── flat_eq.tcl │ ├── gtytx_powerdown.tcl │ ├── mspa_set_polarity.tcl │ ├── mspc_set_polarity.tcl │ ├── power_down_gty_tx.tcl │ ├── prbs31_all.tcl │ ├── remove_links.tcl │ ├── reset_all.tcl │ ├── scan.tcl │ ├── stop_and_remove_scans.tcl │ ├── swing_and_term_all.tcl │ ├── trp_set_polarity.tcl │ └── z2t_float_rxterm.tcl └── tex │ ├── MSP_A_TRP_On_board_links_12.8-optimized.tex │ ├── MSP_A_TRP_On_board_links_6.4-optimized.tex │ ├── MSP_A_TRP_On_board_links_9.6-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX11_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX11_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX11_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX13_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX13_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX13_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX16_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX16_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX16_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX18_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX18_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_A_TX1_MSP_C_RX18_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX10_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX10_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX10_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX12_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX12_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX12_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX15_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX15_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX15_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX17_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX17_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_A_TX2_MSP_C_RX17_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_C_TRP_On_board_links_12.8-optimized.tex │ ├── MSP_C_TRP_On_board_links_6.4-optimized.tex │ ├── MSP_C_TRP_On_board_links_9.6-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX2_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX2_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX2_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX4_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX4_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX4_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX7_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX7_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX7_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX9_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX9_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_C_TX3_MSP_A_RX9_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX1_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX1_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX1_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX3_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX3_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX3_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX6_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX6_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX6_Minipod_Loopback_9.6-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX8_Minipod_Loopback_12.8-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX8_Minipod_Loopback_6.4-optimized.tex │ ├── MSP_C_TX4_MSP_A_RX8_Minipod_Loopback_9.6-optimized.tex │ ├── Partial_TRP_TX5_MSP_A_RX5_Minipod_Loopback_12.8-optimized.tex │ ├── Partial_TRP_TX5_MSP_A_RX5_Minipod_Loopback_6.4-optimized.tex │ ├── Partial_TRP_TX5_MSP_A_RX5_Minipod_Loopback_9.6-optimized.tex │ ├── Partial_TRP_TX5_MSP_C_RX14_Minipod_Loopback_12.8-optimized.tex │ ├── Partial_TRP_TX5_MSP_C_RX14_Minipod_Loopback_6.4-optimized.tex │ ├── Partial_TRP_TX5_MSP_C_RX14_Minipod_Loopback_9.6-optimized.tex │ ├── TRP_J1_QSFP_Loopback_12.8-optimized.tex │ ├── TRP_J1_QSFP_Loopback_6.4-optimized.tex │ ├── TRP_J1_QSFP_Loopback_9.6-optimized.tex │ ├── TRP_J3_SFP_Loopback_12.8-optimized.tex │ ├── TRP_J3_SFP_Loopback_6.4-optimized.tex │ └── TRP_J3_SFP_Loopback_9.6-optimized.tex └── python ├── copy_mdate.py ├── eyescan_plot.py ├── fix_mdate.py ├── gen_mask.py ├── generate_all_hists.py ├── generate_all_plots.py └── ibert_tcl_tex_generator.py /.gitattributes: -------------------------------------------------------------------------------- 1 | out/**/* linguist-vendored 2 | in/**/* linguist-vendored 3 | scans/**/* linguist-vendored 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Byte-compiled / optimized / DLL files 2 | __pycache__/ 3 | *.py[cod] 4 | *$py.class 5 | 6 | # C extensions 7 | *.so 8 | 9 | # Distribution / packaging 10 | .Python 11 | build/ 12 | develop-eggs/ 13 | dist/ 14 | downloads/ 15 | eggs/ 16 | .eggs/ 17 | lib/ 18 | lib64/ 19 | parts/ 20 | sdist/ 21 | var/ 22 | wheels/ 23 | *.egg-info/ 24 | .installed.cfg 25 | *.egg 26 | MANIFEST 27 | 28 | # PyInstaller 29 | # Usually these files are written by a python script from a template 30 | # before PyInstaller builds the exe, so as to inject date/other infos into it. 31 | *.manifest 32 | *.spec 33 | 34 | # Installer logs 35 | pip-log.txt 36 | pip-delete-this-directory.txt 37 | 38 | # Unit test / coverage reports 39 | htmlcov/ 40 | .tox/ 41 | .coverage 42 | .coverage.* 43 | .cache 44 | nosetests.xml 45 | coverage.xml 46 | *.cover 47 | .hypothesis/ 48 | .pytest_cache/ 49 | 50 | # Translations 51 | *.mo 52 | *.pot 53 | 54 | # Django stuff: 55 | *.log 56 | local_settings.py 57 | db.sqlite3 58 | 59 | # Flask stuff: 60 | instance/ 61 | .webassets-cache 62 | 63 | # Scrapy stuff: 64 | .scrapy 65 | 66 | # Sphinx documentation 67 | docs/_build/ 68 | 69 | # PyBuilder 70 | target/ 71 | 72 | # Jupyter Notebook 73 | .ipynb_checkpoints 74 | 75 | # pyenv 76 | .python-version 77 | 78 | # celery beat schedule file 79 | celerybeat-schedule 80 | 81 | # SageMath parsed files 82 | *.sage.py 83 | 84 | # Environments 85 | .env 86 | .venv 87 | env/ 88 | venv/ 89 | ENV/ 90 | env.bak/ 91 | venv.bak/ 92 | 93 | # Spyder project settings 94 | .spyderproject 95 | .spyproject 96 | 97 | # Rope project settings 98 | .ropeproject 99 | 100 | # mkdocs documentation 101 | /site 102 | 103 | # mypy 104 | .mypy_cache/ 105 | -------------------------------------------------------------------------------- /.idea/other.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | -------------------------------------------------------------------------------- /.idea/vcs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 mvsoliveira 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 |

2 | 3 |

4 | Python tool to manage Vivado IBERT tests by generating TCL scripts to automate the interconnection between links in Vivado, configuring their respective polarities, running the BER tests and eye-scan measurements, plotting eye-diagrams, running eye-mask checks, generating horizontal, vertical, and area opening histograms, and compile all the results into a PDF report 5 | 6 | # Workflow using PCBpy and IBERTpy 7 | ![Alt text](docs/workflow.png?raw=true "Workflow") 8 | If you do not have a Cadence Allegro Schematics, you can still use IBERTpy but you need to generate yourself the connectivity CSV files. 9 | 10 | # Inputs: 11 | 1) Connectivity CSV files (in/csv) generated by PCBpy for Cadence Allegro PCB projects https://github.com/mvsoliveira/PCBpy 12 | 2) TCL (in/tcl) and LaTeX (in/tex) template files 13 | 14 | # Outputs: 15 | 16 | After Step 2 (ibert_tcl_tex_generator.py): 17 | 1) TCL (out/tcl) files to configure IBERT links connectivity, polarity and run settings 18 | 2) TEX files to compile all the eye diagrams in a single PDF 19 | 20 | After steps 6: 21 | 1) PDF (out/pdf) files with summary scatter plots of eye openning (generate_all_hists.py) 22 | 2) PDF (scans/pdf) files with eye diagrams for every link in different configurations (generate_all_plots.py) 23 | 24 | After step 7: 25 | 1) PDF Report with all the eye diagrams (latex/report.tex). Example here. 26 | 27 | # Instructions: 28 | #### 1) Board netlist and FPGA package files 29 | 30 | 1) Generate board netlist files using PCBpy. 31 | See instructions here. 32 | 2) Get FPGA package files here.
33 | PCBpy reads only the Xilinx CSV files at the moment. 34 | 35 | #### 2) Generate IBERT TCL scripts and LaTeX report files 36 | 37 | A) Edit the ibert_tcl_tex_generator.py with the following information: 38 | 39 | 1) csvfiles: Relative files to CSV package files 40 | 2) schem_map: Dictionary of schematics reference designators to ibert instance and device name for the report 41 | 3) runs: Array of dictionaries listing the connectivity of each of the testing runs. Multiple runs are needed when all the inputs/outpus can't be connected simmultaneously. 42 | 4) tex_runs: Names for different set of runs. Used to distinguish in the report results from different data rates or different board versions. 43 | 5) link_tex_templates: Make sure a LaTeX template exists for all the summary pages you need. 44 | 6) Make sure in/tcl/SetIBERTRunTemplate.tcl contains the call for each of the tcl files carrying the link settings. Examples are: polarities, power-down, PRBS mode, swing, enphasis and others. The transceiver polarirty tcl scripts are automatically generated by PCBpy. 45 | 46 | B) Run ibert_tcl_tex_generator.py and check the results at out/tcl and out/tex
47 | IBERTpy checks if each of the scan csv files exist before generating the TeX files in order to avoid latex compiling errors.
48 | Therefore, after finishing all the scans, run ibert_tcl_tex_generator.py again to double check if any scan csv is missing.
49 | The following message is shown in case of missing scan csv files:
50 | `Skipping MSP_C_FPGA-IC39-00--IC15-00-TRP_FPGA because the file ../scans/csv/V3-12.8/MSP_C_FPGA-IC39-00--IC15-00-TRP_FPGA.csv was not found` 51 | 52 | #### 3, 4 and 5) Configure the links and get the CSV scan files 53 | 54 | 1) Configure the board 55 | 2) Open the Vivado Hardware Manager 56 | 3) Connect to the board 57 | 4) Make sure the TCL console is in the folder at which the out/tcl scripts are 58 | 5) Run the SetIBERT Run?.tcl corresponding to the run you are insterested to 59 | 6) Check the link settings and status 60 | 7) Make sure ../scans/csv/ path exists 61 | 8) Change run settings at scan.tcl file if needed 62 | 9) Run ScanRun ?.tcl 63 | 10) Wait until all the scans are finished, the scan files are placed at ../scans/csv/ 64 | 65 | #### 6) Generate eye-diagram and summary histogram PDF files 66 | 67 | 1) Organize the CSV scan files into a different folder for each of the different tex_runs listed in step 2.4 68 | 2) Make sure that the same folders exist at scans/pdf/ 69 | 3) Make sure matplitlib is installed in your python envinronment 70 | 4) Run generate_all_plots.py to generate a PDF file for each CSV file 71 | 5) Run generate_all_hists.py to generate summary histograms
72 | Make sure rates is set according to tex_runs defined in step 2.4.
The variable link_set is set to filter the CSV files of interest. 73 | 74 | #### 7) Generate LaTeX PDF report file 75 | 76 | The main LaTeX report.tex file is not generated automatically yet. However, all the summary and detailed pages are automatically generated.
77 | One can run LaTeX in the cloud, using services such as overleaf.com or locally using a LaTeX distribution of preference.
78 | Popular distributions are TeX Live (http://tug.org/texlive/) and MiKTeX (https://miktex.org/). 79 | 80 | 1) Edit the report.tex main TeX file accordingly. The output from genTexInputCalls(tex_files) method in ibert_tcl_tex_generator.py can be useful. 81 | 2) Make sure you LaTeX environment includes the packages used in the report.tex file 82 | 3) Compile the LaTex report file. You should expect to get a Table of Contents with entries for each summary and detailed pages. 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | -------------------------------------------------------------------------------- /docs/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mvsoliveira/IBERTpy/7d702ed87f0c8fbe90f4ef0445e2d4f77a79ec02/docs/logo.png -------------------------------------------------------------------------------- /docs/workflow.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mvsoliveira/IBERTpy/7d702ed87f0c8fbe90f4ef0445e2d4f77a79ec02/docs/workflow.pdf -------------------------------------------------------------------------------- /docs/workflow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mvsoliveira/IBERTpy/7d702ed87f0c8fbe90f4ef0445e2d4f77a79ec02/docs/workflow.png -------------------------------------------------------------------------------- /docs/workflow.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mvsoliveira/IBERTpy/7d702ed87f0c8fbe90f4ef0445e2d4f77a79ec02/docs/workflow.pptx -------------------------------------------------------------------------------- /docs/worklow.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/mvsoliveira/IBERTpy/7d702ed87f0c8fbe90f4ef0445e2d4f77a79ec02/docs/worklow.pdf -------------------------------------------------------------------------------- /in/csv/xc7z030ffg676pkg_IC44_IBERT_info.csv: -------------------------------------------------------------------------------- 1 | IBERT instance name,Dir,A part,A inst,A pin name,A pin,A net,Coupling cap,B part,B inst,B pin name,B pin,B net,IO# 2 | Quad_112/MGT_X0Y0,I,XC7Z030-2FFG676I,IC44,MGTXRXP0_112,AB4,GBESFP_RX_P,No,CON20P_SFP-1888247-1,J4,RD+,13,-,0 3 | Quad_112/MGT_X0Y0,O,XC7Z030-2FFG676I,IC44,MGTXTXP0_112,AA2,GBESFP_TX_P,No,CON20P_SFP-1888247-1,J4,TD+,18,-,0 4 | Quad_112/MGT_X0Y1,I,XC7Z030-2FFG676I,IC44,MGTXRXP1_112,Y4,T2Z_GT_P,No,XCKU095-1FFVB2104C,IC39,MGTYTXP3_124,AW40,-,0 5 | Quad_112/MGT_X0Y1,O,XC7Z030-2FFG676I,IC44,MGTXTXP1_112,W2,Z2T_GT_P,No,XCKU095-1FFVB2104C,IC39,MGTYRXP3_124,AV43,-,0 6 | Quad_112/MGT_X0Y2,I,XC7Z030-2FFG676I,IC44,MGTXRXP2_112,V4,A2Z_GT_P,No,XCVU160-H1FLGC2104,IC4,MGTYTXP3_133,A36,-,0 7 | Quad_112/MGT_X0Y2,O,XC7Z030-2FFG676I,IC44,MGTXTXP2_112,U2,-,-,-,-,-,-,-,- 8 | Quad_112/MGT_X0Y3,I,XC7Z030-2FFG676I,IC44,MGTXRXP3_112,T4,C2Z_GT_P,No,XCVU160-H1FLGC2104,IC15,MGTYTXP3_133,A36,-,0 9 | Quad_112/MGT_X0Y3,O,XC7Z030-2FFG676I,IC44,MGTXTXP3_112,R2,-,-,-,-,-,-,-,- 10 | -------------------------------------------------------------------------------- /in/tcl/ScanRunTemplate.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 9 | ## Last update: 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # stopping and removing existing scans 24 | source stop_and_remove_scans.tcl 25 | # sourcing scan procedure 26 | source scan.tcl 27 | # run scans 28 | -------------------------------------------------------------------------------- /in/tcl/SetIBERTRunTemplate.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 9 | ## Last update: 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # Setting up MGTs 24 | source z2t_float_rxterm.tcl 25 | source power_down_gty_tx.tcl 26 | source swing_and_term_all.tcl 27 | source mspa_set_polarity.tcl 28 | source mspc_set_polarity.tcl 29 | source trp_set_polarity.tcl 30 | source prbs31_all.tcl 31 | 32 | #removing existing links 33 | source remove_links.tcl 34 | 35 | # create links 36 | 37 | # reset the links 38 | source reset_all.tcl -------------------------------------------------------------------------------- /in/tex/ScanTemplate.tex: -------------------------------------------------------------------------------- 1 | 2 | \subsection{}\label{sec:} 3 | 4 | % Please add the following required packages to your document preamble: 5 | % \usepackage{booktabs} 6 | \begin{table}[h] 7 | \centering 8 | \caption{} 9 | \label{tab:} 10 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 11 | \toprule 12 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 13 | & & \multicolumn{2}{l|}{} & \multicolumn{2}{l|}{} \\ \midrule 14 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 15 | & & & \% & & \% \\ \midrule 16 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 17 | & & & & \multicolumn{2}{l|}{} \\ \bottomrule 18 | \end{tabular} 19 | \end{table} 20 | 21 | \begin{figure}[h] 22 | \includegraphicsmaybe{} 23 | \caption{} \label{fig:} 24 | \end{figure} 25 | 26 | Call back to summary Figure~\ref{fig:}. 27 | 28 | 29 | \clearpage 30 | \newpage 31 | 32 | -------------------------------------------------------------------------------- /in/tex/figEyeSummaryTemplate01.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{}\label{sec:<id><Tex run>} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{1\textwidth} 17 | \hyperref[sec:<fig00label><Tex run>]{\includegraphicsmaybe{<fig00>}} 18 | \end{subfigure} 19 | 20 | \caption{<title>} \label{fig:<id><Tex run>} 21 | \end{figure} 22 | 23 | A cross-reference to Figure~\ref{fig:<id><Tex run>}. 24 | <siblings> \\ 25 | Next summary Figure~\ref{fig:<id next><Tex run next>}. 26 | \clearpage 27 | % \end{document} -------------------------------------------------------------------------------- /in/tex/figEyeSummaryTemplate04.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{<title>}\label{sec:<id><Tex run>} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{0.5\textwidth} 17 | \hyperref[sec:<fig00label><Tex run>]{\includegraphicsmaybe{<fig00>}} 18 | \end{subfigure}\hspace*{\fill} 19 | \begin{subfigure}{0.5\textwidth} 20 | \hyperref[sec:<fig01label><Tex run>]{\includegraphicsmaybe{<fig01>}} 21 | \end{subfigure} 22 | 23 | \begin{subfigure}{0.5\textwidth} 24 | \hyperref[sec:<fig02label><Tex run>]{\includegraphicsmaybe{<fig02>}} 25 | \end{subfigure}\hspace*{\fill} 26 | \begin{subfigure}{0.5\textwidth} 27 | \hyperref[sec:<fig03label><Tex run>]{\includegraphicsmaybe{<fig03>}} 28 | \end{subfigure} 29 | 30 | \caption{<title>} \label{fig:<id><Tex run>} 31 | \end{figure} 32 | 33 | A cross-reference to Figure~\ref{fig:<id><Tex run>}. 34 | <siblings> \\ 35 | Next summary Figure~\ref{fig:<id next><Tex run next>}. 36 | \clearpage 37 | % \end{document} -------------------------------------------------------------------------------- /in/tex/figEyeSummaryTemplate08.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.4in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{<title>}\label{sec:<id><Tex run>} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \centering 17 | \begin{subfigure}{0.5\textwidth} 18 | \hyperref[sec:<fig00label><Tex run>]{\includegraphicsmaybe{<fig00>}} 19 | \end{subfigure}\hspace*{\fill} 20 | \begin{subfigure}{0.5\textwidth} 21 | \hyperref[sec:<fig01label><Tex run>]{\includegraphicsmaybe{<fig01>}} 22 | \end{subfigure} 23 | 24 | \begin{subfigure}{0.5\textwidth} 25 | \hyperref[sec:<fig02label><Tex run>]{\includegraphicsmaybe{<fig02>}} 26 | \end{subfigure}\hspace*{\fill} 27 | \begin{subfigure}{0.5\textwidth} 28 | \hyperref[sec:<fig03label><Tex run>]{\includegraphicsmaybe{<fig03>}} 29 | \end{subfigure} 30 | 31 | \begin{subfigure}{0.5\textwidth} 32 | \hyperref[sec:<fig04label><Tex run>]{\includegraphicsmaybe{<fig04>}} 33 | \end{subfigure}\hspace*{\fill} 34 | \begin{subfigure}{0.5\textwidth} 35 | \hyperref[sec:<fig05label><Tex run>]{\includegraphicsmaybe{<fig05>}} 36 | \end{subfigure} 37 | 38 | \begin{subfigure}{0.5\textwidth} 39 | \hyperref[sec:<fig06label><Tex run>]{\includegraphicsmaybe{<fig06>}} 40 | \end{subfigure}\hspace*{\fill} 41 | \begin{subfigure}{0.5\textwidth} 42 | \hyperref[sec:<fig07label><Tex run>]{\includegraphicsmaybe{<fig07>}} 43 | \end{subfigure} 44 | 45 | \caption{<title>} \label{fig:<id><Tex run>} 46 | \end{figure} 47 | 48 | A cross-reference to Figure~\ref{fig:<id><Tex run>}. 49 | <siblings> \\ 50 | Next summary Figure~\ref{fig:<id next><Tex run next>}. 51 | \clearpage 52 | % \end{document} -------------------------------------------------------------------------------- /in/tex/figEyeSummaryTemplate12.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{<title>}\label{sec:<id><Tex run>} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{0.33\textwidth} 17 | \hyperref[sec:<fig00label><Tex run>]{\includegraphicsmaybe{<fig00>}} 18 | \end{subfigure}\hspace*{\fill} 19 | \begin{subfigure}{0.33\textwidth} 20 | \hyperref[sec:<fig01label><Tex run>]{\includegraphicsmaybe{<fig01>}} 21 | \end{subfigure}\hspace*{\fill} 22 | \begin{subfigure}{0.33\textwidth} 23 | \hyperref[sec:<fig02label><Tex run>]{\includegraphicsmaybe{<fig02>}} 24 | \end{subfigure} 25 | 26 | \begin{subfigure}{0.33\textwidth} 27 | \hyperref[sec:<fig03label><Tex run>]{\includegraphicsmaybe{<fig03>}} 28 | \end{subfigure}\hspace*{\fill} 29 | \begin{subfigure}{0.33\textwidth} 30 | \hyperref[sec:<fig04label><Tex run>]{\includegraphicsmaybe{<fig04>}} 31 | \end{subfigure}\hspace*{\fill} 32 | \begin{subfigure}{0.33\textwidth} 33 | \hyperref[sec:<fig05label><Tex run>]{\includegraphicsmaybe{<fig05>}} 34 | \end{subfigure} 35 | 36 | \begin{subfigure}{0.33\textwidth} 37 | \hyperref[sec:<fig06label><Tex run>]{\includegraphicsmaybe{<fig06>}} 38 | \end{subfigure}\hspace*{\fill} 39 | \begin{subfigure}{0.33\textwidth} 40 | \hyperref[sec:<fig07label><Tex run>]{\includegraphicsmaybe{<fig07>}} 41 | \end{subfigure}\hspace*{\fill} 42 | \begin{subfigure}{0.33\textwidth} 43 | \hyperref[sec:<fig08label><Tex run>]{\includegraphicsmaybe{<fig08>}} 44 | \end{subfigure} 45 | 46 | \begin{subfigure}{0.33\textwidth} 47 | \hyperref[sec:<fig09label><Tex run>]{\includegraphicsmaybe{<fig09>}} 48 | \end{subfigure}\hspace*{\fill} 49 | \begin{subfigure}{0.33\textwidth} 50 | \hyperref[sec:<fig10label><Tex run>]{\includegraphicsmaybe{<fig10>}} 51 | \end{subfigure}\hspace*{\fill} 52 | \begin{subfigure}{0.33\textwidth} 53 | \hyperref[sec:<fig11label><Tex run>]{\includegraphicsmaybe{<fig11>}} 54 | \end{subfigure} 55 | 56 | \caption{<title>} \label{fig:<id><Tex run>} 57 | \end{figure} 58 | 59 | A cross-reference to Figure~\ref{fig:<id><Tex run>}. 60 | <siblings> \\ 61 | Next summary Figure~\ref{fig:<id next><Tex run next>}. 62 | \clearpage 63 | % \end{document} -------------------------------------------------------------------------------- /in/tex/figEyeSummaryTemplate28.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{<title>}\label{sec:<id><Tex run>} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{0.25\textwidth} 17 | \hyperref[sec:<fig00label><Tex run>]{\includegraphicsmaybe{<fig00>}} 18 | \end{subfigure}\hspace*{\fill} 19 | \begin{subfigure}{0.25\textwidth} 20 | \hyperref[sec:<fig01label><Tex run>]{\includegraphicsmaybe{<fig01>}} 21 | \end{subfigure}\hspace*{\fill} 22 | \begin{subfigure}{0.25\textwidth} 23 | \hyperref[sec:<fig02label><Tex run>]{\includegraphicsmaybe{<fig02>}} 24 | \end{subfigure}\hspace*{\fill} 25 | \begin{subfigure}{0.25\textwidth} 26 | \hyperref[sec:<fig03label><Tex run>]{\includegraphicsmaybe{<fig03>}} 27 | \end{subfigure} 28 | 29 | \begin{subfigure}{0.25\textwidth} 30 | \hyperref[sec:<fig04label><Tex run>]{\includegraphicsmaybe{<fig04>}} 31 | \end{subfigure}\hspace*{\fill} 32 | \begin{subfigure}{0.25\textwidth} 33 | \hyperref[sec:<fig05label><Tex run>]{\includegraphicsmaybe{<fig05>}} 34 | \end{subfigure}\hspace*{\fill} 35 | \begin{subfigure}{0.25\textwidth} 36 | \hyperref[sec:<fig06label><Tex run>]{\includegraphicsmaybe{<fig06>}} 37 | \end{subfigure}\hspace*{\fill} 38 | \begin{subfigure}{0.25\textwidth} 39 | \hyperref[sec:<fig07label><Tex run>]{\includegraphicsmaybe{<fig07>}} 40 | \end{subfigure} 41 | 42 | \begin{subfigure}{0.25\textwidth} 43 | \hyperref[sec:<fig08label><Tex run>]{\includegraphicsmaybe{<fig08>}} 44 | \end{subfigure}\hspace*{\fill} 45 | \begin{subfigure}{0.25\textwidth} 46 | \hyperref[sec:<fig09label><Tex run>]{\includegraphicsmaybe{<fig09>}} 47 | \end{subfigure}\hspace*{\fill} 48 | \begin{subfigure}{0.25\textwidth} 49 | \hyperref[sec:<fig10label><Tex run>]{\includegraphicsmaybe{<fig10>}} 50 | \end{subfigure}\hspace*{\fill} 51 | \begin{subfigure}{0.25\textwidth} 52 | \hyperref[sec:<fig11label><Tex run>]{\includegraphicsmaybe{<fig11>}} 53 | \end{subfigure} 54 | 55 | \begin{subfigure}{0.25\textwidth} 56 | \hyperref[sec:<fig12label><Tex run>]{\includegraphicsmaybe{<fig12>}} 57 | \end{subfigure}\hspace*{\fill} 58 | \begin{subfigure}{0.25\textwidth} 59 | \hyperref[sec:<fig13label><Tex run>]{\includegraphicsmaybe{<fig13>}} 60 | \end{subfigure}\hspace*{\fill} 61 | \begin{subfigure}{0.25\textwidth} 62 | \hyperref[sec:<fig14label><Tex run>]{\includegraphicsmaybe{<fig14>}} 63 | \end{subfigure}\hspace*{\fill} 64 | \begin{subfigure}{0.25\textwidth} 65 | \hyperref[sec:<fig15label><Tex run>]{\includegraphicsmaybe{<fig15>}} 66 | \end{subfigure} 67 | 68 | \begin{subfigure}{0.25\textwidth} 69 | \hyperref[sec:<fig16label><Tex run>]{\includegraphicsmaybe{<fig16>}} 70 | \end{subfigure}\hspace*{\fill} 71 | \begin{subfigure}{0.25\textwidth} 72 | \hyperref[sec:<fig17label><Tex run>]{\includegraphicsmaybe{<fig17>}} 73 | \end{subfigure}\hspace*{\fill} 74 | \begin{subfigure}{0.25\textwidth} 75 | \hyperref[sec:<fig18label><Tex run>]{\includegraphicsmaybe{<fig18>}} 76 | \end{subfigure}\hspace*{\fill} 77 | \begin{subfigure}{0.25\textwidth} 78 | \hyperref[sec:<fig19label><Tex run>]{\includegraphicsmaybe{<fig19>}} 79 | \end{subfigure} 80 | 81 | \begin{subfigure}{0.25\textwidth} 82 | \hyperref[sec:<fig20label><Tex run>]{\includegraphicsmaybe{<fig20>}} 83 | \end{subfigure}\hspace*{\fill} 84 | \begin{subfigure}{0.25\textwidth} 85 | \hyperref[sec:<fig21label><Tex run>]{\includegraphicsmaybe{<fig21>}} 86 | \end{subfigure}\hspace*{\fill} 87 | \begin{subfigure}{0.25\textwidth} 88 | \hyperref[sec:<fig22label><Tex run>]{\includegraphicsmaybe{<fig22>}} 89 | \end{subfigure}\hspace*{\fill} 90 | \begin{subfigure}{0.25\textwidth} 91 | \hyperref[sec:<fig23label><Tex run>]{\includegraphicsmaybe{<fig23>}} 92 | \end{subfigure} 93 | 94 | \begin{subfigure}{0.25\textwidth} 95 | \hyperref[sec:<fig24label><Tex run>]{\includegraphicsmaybe{<fig24>}} 96 | \end{subfigure}\hspace*{\fill} 97 | \begin{subfigure}{0.25\textwidth} 98 | \hyperref[sec:<fig25label><Tex run>]{\includegraphicsmaybe{<fig25>}} 99 | \end{subfigure}\hspace*{\fill} 100 | \begin{subfigure}{0.25\textwidth} 101 | \hyperref[sec:<fig26label><Tex run>]{\includegraphicsmaybe{<fig26>}} 102 | \end{subfigure}\hspace*{\fill} 103 | \begin{subfigure}{0.25\textwidth} 104 | \hyperref[sec:<fig27label><Tex run>]{\includegraphicsmaybe{<fig27>}} 105 | \end{subfigure} 106 | 107 | \caption{<title>} \label{fig:<id><Tex run>} 108 | \end{figure} 109 | 110 | A cross-reference to Figure~\ref{fig:<id><Tex run>}. 111 | <siblings> \\ 112 | Next summary Figure~\ref{fig:<id next><Tex run next>}. 113 | \clearpage 114 | % \end{document} -------------------------------------------------------------------------------- /latex/MUCTPI_links.pdf: -------------------------------------------------------------------------------- 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###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 0 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : ScanRun 0.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2018-09-28 9 | ## Last update: 2018-09-28 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2018 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2018-09-28 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # stopping and removing existing scans 24 | source stop_and_remove_scans.tcl 25 | # sourcing scan procedure 26 | source scan.tcl 27 | # run scans 28 | scan $MuctpiMSP_A_TX1_MSP_C_RX15_Minipod_LoopbackLinkList 29 | scan $MuctpiMSP_A_TX2_MSP_C_RX16_Minipod_LoopbackLinkList 30 | scan $MuctpiMSP_C_TX3_MSP_A_RX6_Minipod_LoopbackLinkList 31 | scan $MuctpiMSP_C_TX4_MSP_A_RX7_Minipod_LoopbackLinkList 32 | scan $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList 33 | scan $MuctpiTRP_J1_QSFP_LoopbackLinkList 34 | scan $MuctpiTRP_J3_SFP_LoopbackLinkList 35 | scan $MuctpiMSP_A_TRP_On_board_linksLinkList 36 | scan $MuctpiMSP_C_TRP_On_board_linksLinkList 37 | -------------------------------------------------------------------------------- /out/tcl/ScanRun 1.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 1 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : ScanRun 1.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2018-09-28 9 | ## Last update: 2018-09-28 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2018 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2018-09-28 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # stopping and removing existing scans 24 | source stop_and_remove_scans.tcl 25 | # sourcing scan procedure 26 | source scan.tcl 27 | # run scans 28 | scan $MuctpiMSP_A_TX1_MSP_C_RX17_Minipod_LoopbackLinkList 29 | scan $MuctpiMSP_A_TX2_MSP_C_RX18_Minipod_LoopbackLinkList 30 | scan $MuctpiMSP_C_TX3_MSP_A_RX8_Minipod_LoopbackLinkList 31 | scan $MuctpiMSP_C_TX4_MSP_A_RX9_Minipod_LoopbackLinkList 32 | scan $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList 33 | -------------------------------------------------------------------------------- /out/tcl/ScanRun 2.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 2 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : ScanRun 2.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2018-09-28 9 | ## Last update: 2018-09-28 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2018 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2018-09-28 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # stopping and removing existing scans 24 | source stop_and_remove_scans.tcl 25 | # sourcing scan procedure 26 | source scan.tcl 27 | # run scans 28 | scan $MuctpiMSP_A_TX1_MSP_C_RX10_Minipod_LoopbackLinkList 29 | scan $MuctpiMSP_A_TX2_MSP_C_RX11_Minipod_LoopbackLinkList 30 | scan $MuctpiMSP_C_TX3_MSP_A_RX1_Minipod_LoopbackLinkList 31 | scan $MuctpiMSP_C_TX4_MSP_A_RX2_Minipod_LoopbackLinkList 32 | -------------------------------------------------------------------------------- /out/tcl/ScanRun 3.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 3 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : ScanRun 3.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2018-09-28 9 | ## Last update: 2018-09-28 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2018 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2018-09-28 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # stopping and removing existing scans 24 | source stop_and_remove_scans.tcl 25 | # sourcing scan procedure 26 | source scan.tcl 27 | # run scans 28 | scan $MuctpiMSP_A_TX1_MSP_C_RX12_Minipod_LoopbackLinkList 29 | scan $MuctpiMSP_A_TX2_MSP_C_RX13_Minipod_LoopbackLinkList 30 | scan $MuctpiMSP_C_TX3_MSP_A_RX3_Minipod_LoopbackLinkList 31 | scan $MuctpiMSP_C_TX4_MSP_A_RX4_Minipod_LoopbackLinkList 32 | -------------------------------------------------------------------------------- /out/tcl/ScanRun 4.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 4 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : ScanRun 4.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2017-07-25 9 | ## Last update: 2017-07-25 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2017 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2017-07-25 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # stopping and removing existing scans 24 | source stop_and_remove_scans.tcl 25 | # sourcing scan procedure 26 | source scan.tcl 27 | # run scans 28 | scan $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList 29 | scan $MuctpiTRP_J1_QSFP_LoopbackLinkList 30 | scan $MuctpiMSP_A_TRP_On_board_linksLinkList 31 | scan $MuctpiMSP_C_TRP_On_board_linksLinkList 32 | -------------------------------------------------------------------------------- /out/tcl/SetIBERTRun 0.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 0 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : SetIBERTRun 0.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2018-09-28 9 | ## Last update: 2018-09-28 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2018 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2018-09-28 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # Setting up MGTs 24 | source z2t_float_rxterm.tcl 25 | source power_down_gty_tx.tcl 26 | source swing_and_term_all.tcl 27 | source mspa_set_polarity.tcl 28 | source mspc_set_polarity.tcl 29 | source trp_set_polarity.tcl 30 | source prbs31_all.tcl 31 | 32 | #removing existing links 33 | source remove_links.tcl 34 | 35 | # create links 36 | source create_links_TX1_RX15.tcl 37 | source create_links_TX2_RX16.tcl 38 | source create_links_TX3_RX6.tcl 39 | source create_links_TX4_RX7.tcl 40 | source create_links_TX5_RX5.tcl 41 | source create_links_J1_J1.tcl 42 | source create_links_J3_J3.tcl 43 | source create_links_IC39_IC4.tcl 44 | source create_links_IC39_IC15.tcl 45 | 46 | # reset the links 47 | source reset_all.tcl -------------------------------------------------------------------------------- /out/tcl/SetIBERTRun 1.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 1 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : SetIBERTRun 1.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2018-09-28 9 | ## Last update: 2018-09-28 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2018 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2018-09-28 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # Setting up MGTs 24 | source z2t_float_rxterm.tcl 25 | source power_down_gty_tx.tcl 26 | source swing_and_term_all.tcl 27 | source mspa_set_polarity.tcl 28 | source mspc_set_polarity.tcl 29 | source trp_set_polarity.tcl 30 | source prbs31_all.tcl 31 | 32 | #removing existing links 33 | source remove_links.tcl 34 | 35 | # create links 36 | source create_links_TX1_RX17.tcl 37 | source create_links_TX2_RX18.tcl 38 | source create_links_TX3_RX8.tcl 39 | source create_links_TX4_RX9.tcl 40 | source create_links_TX5_RX14.tcl 41 | 42 | # reset the links 43 | source reset_all.tcl -------------------------------------------------------------------------------- /out/tcl/SetIBERTRun 2.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 2 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : SetIBERTRun 2.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2018-09-28 9 | ## Last update: 2018-09-28 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2018 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2018-09-28 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # Setting up MGTs 24 | source z2t_float_rxterm.tcl 25 | source power_down_gty_tx.tcl 26 | source swing_and_term_all.tcl 27 | source mspa_set_polarity.tcl 28 | source mspc_set_polarity.tcl 29 | source trp_set_polarity.tcl 30 | source prbs31_all.tcl 31 | 32 | #removing existing links 33 | source remove_links.tcl 34 | 35 | # create links 36 | source create_links_TX1_RX10.tcl 37 | source create_links_TX2_RX11.tcl 38 | source create_links_TX3_RX1.tcl 39 | source create_links_TX4_RX2.tcl 40 | 41 | # reset the links 42 | source reset_all.tcl -------------------------------------------------------------------------------- /out/tcl/SetIBERTRun 3.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 3 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : SetIBERTRun 3.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2018-09-28 9 | ## Last update: 2018-09-28 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2018 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2018-09-28 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # Setting up MGTs 24 | source z2t_float_rxterm.tcl 25 | source power_down_gty_tx.tcl 26 | source swing_and_term_all.tcl 27 | source mspa_set_polarity.tcl 28 | source mspc_set_polarity.tcl 29 | source trp_set_polarity.tcl 30 | source prbs31_all.tcl 31 | 32 | #removing existing links 33 | source remove_links.tcl 34 | 35 | # create links 36 | source create_links_TX1_RX12.tcl 37 | source create_links_TX2_RX13.tcl 38 | source create_links_TX3_RX3.tcl 39 | source create_links_TX4_RX4.tcl 40 | 41 | # reset the links 42 | source reset_all.tcl -------------------------------------------------------------------------------- /out/tcl/SetIBERTRun 4.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MUCTPI IBERT for Run 4 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : SetIBERTRun 4.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2017-07-25 9 | ## Last update: 2017-07-25 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2017 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2017-07-25 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | 23 | # Setting up MGTs 24 | source z2t_float_rxterm.tcl 25 | source power_down_gty_tx.tcl 26 | source mspa_set_polarity.tcl 27 | source mspc_set_polarity.tcl 28 | source trp_set_polarity.tcl 29 | source prbs31_all.tcl 30 | 31 | #removing existing links 32 | source remove_links.tcl 33 | 34 | # create links 35 | source create_links_TX5_RX14.tcl 36 | source create_links_J1_J1.tcl 37 | source create_links_IC39_IC4.tcl 38 | source create_links_IC39_IC15.tcl 39 | 40 | # reset the links 41 | source reset_all.tcl -------------------------------------------------------------------------------- /out/tcl/SetMSP Rx.tcl: -------------------------------------------------------------------------------- 1 | ###################################################################################################################### 2 | ## Title : Setting MSP Rx 3 | ## Project : MUCTPI 4 | ###################################################################################################################### 5 | ## File : SetMSP Rx.tcl 6 | ## Author : Marcos Oliveira 7 | ## Company : CERN 8 | ## Created : 2017-07-24 9 | ## Last update: 2017-07-24 10 | ## Platform : Vivado 2017.2 11 | ## Standard : TCL 12 | ###################################################################################################################### 13 | ## Description: Automatically generated with ibert_tcl_generator 14 | ###################################################################################################################### 15 | ## Copyright (c) 2017 CERN 16 | ###################################################################################################################### 17 | ## Revisions : 18 | ## Date Version Author Description 19 | ## 2017-07-24 1.0 msilvaol Created 20 | ###################################################################################################################### 21 | 22 | cd /home/muctpi/work/ibert/scripts 23 | 24 | # Setting up MGTs 25 | # MSPA 26 | set_property PORT.TXPD 3 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/0_1_0_65/IBERT/Quad_1*/MGT_*] 27 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/0_1_0_65/IBERT/Quad_1*/MGT_*] 28 | # MSPC 29 | set_property PORT.TXPD 3 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/1_1_0_65/IBERT/Quad_1*/MGT_*] 30 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/1_1_0_65/IBERT/Quad_1*/MGT_*] 31 | source mspa_set_polarity.tcl 32 | source mspc_set_polarity.tcl 33 | source prbs31_all.tcl 34 | 35 | #removing existing links 36 | source remove_links.tcl 37 | 38 | # create links 39 | source create_links_TX1_RX16.tcl 40 | source create_links_TX2_RX15.tcl 41 | source create_links_TX3_RX2.tcl 42 | source create_links_TX4_RX1.tcl 43 | 44 | # reset the links 45 | source reset_all.tcl 46 | -------------------------------------------------------------------------------- /out/tcl/create_links_J1_J1.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_J1_J1.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiTRP_J1_QSFP_LoopbackLinkLinkList 3 | set MuctpiTRP_J1_QSFP_LoopbackLinkList [list] 4 | #Creating link: TRP_FPGA-J1-00--J1-00-TRP_FPGA 5 | set MuctpiTRP_J1_QSFP_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-J1-00--J1-00-TRP_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_224/MGT_X0Y0/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_224/MGT_X0Y0/RX] 0] ] 6 | lappend MuctpiTRP_J1_QSFP_LoopbackLinkList $MuctpiTRP_J1_QSFP_LoopbackLink 7 | #Creating link: TRP_FPGA-J1-01--J1-01-TRP_FPGA 8 | set MuctpiTRP_J1_QSFP_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-J1-01--J1-01-TRP_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_224/MGT_X0Y1/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_224/MGT_X0Y1/RX] 0] ] 9 | lappend MuctpiTRP_J1_QSFP_LoopbackLinkList $MuctpiTRP_J1_QSFP_LoopbackLink 10 | #Creating link: TRP_FPGA-J1-02--J1-02-TRP_FPGA 11 | set MuctpiTRP_J1_QSFP_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-J1-02--J1-02-TRP_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_224/MGT_X0Y2/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_224/MGT_X0Y2/RX] 0] ] 12 | lappend MuctpiTRP_J1_QSFP_LoopbackLinkList $MuctpiTRP_J1_QSFP_LoopbackLink 13 | #Creating link: TRP_FPGA-J1-03--J1-03-TRP_FPGA 14 | set MuctpiTRP_J1_QSFP_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-J1-03--J1-03-TRP_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_224/MGT_X0Y3/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_224/MGT_X0Y3/RX] 0] ] 15 | lappend MuctpiTRP_J1_QSFP_LoopbackLinkList $MuctpiTRP_J1_QSFP_LoopbackLink 16 | # Creating link group MuctpiTRP_J1_QSFP_LoopbackLinkGroupLinkGroup 17 | set MuctpiTRP_J1_QSFP_LoopbackLinkGroup [create_hw_sio_linkgroup -description {TRP J1 QSFP Loopback} [get_hw_sio_links $MuctpiTRP_J1_QSFP_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_J3_J3.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_J3_J3.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiTRP_J3_SFP_LoopbackLinkLinkList 3 | set MuctpiTRP_J3_SFP_LoopbackLinkList [list] 4 | #Creating link: TRP_FPGA-J3-00--J3-00-TRP_FPGA 5 | set MuctpiTRP_J3_SFP_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-J3-00--J3-00-TRP_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_124/MGT_X0Y0/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_124/MGT_X0Y0/RX] 0] ] 6 | lappend MuctpiTRP_J3_SFP_LoopbackLinkList $MuctpiTRP_J3_SFP_LoopbackLink 7 | # Creating link group MuctpiTRP_J3_SFP_LoopbackLinkGroupLinkGroup 8 | set MuctpiTRP_J3_SFP_LoopbackLinkGroup [create_hw_sio_linkgroup -description {TRP J3 SFP Loopback} [get_hw_sio_links $MuctpiTRP_J3_SFP_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX1_RX11.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX1_RX11.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_A_FPGA-TX1-05--RX11-05-MSP_C_FPGA 5 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-05--RX11-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y4/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_124/MGT_X*Y20/RX] 0] ] 6 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 7 | #Creating link: MSP_A_FPGA-TX1-03--RX11-03-MSP_C_FPGA 8 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-03--RX11-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y5/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_124/MGT_X*Y21/RX] 0] ] 9 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 10 | #Creating link: MSP_A_FPGA-TX1-07--RX11-07-MSP_C_FPGA 11 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-07--RX11-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y6/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_126/MGT_X*Y31/RX] 0] ] 12 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 13 | #Creating link: MSP_A_FPGA-TX1-00--RX11-00-MSP_C_FPGA 14 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-00--RX11-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y7/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_124/MGT_X*Y23/RX] 0] ] 15 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 16 | #Creating link: MSP_A_FPGA-TX1-09--RX11-09-MSP_C_FPGA 17 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-09--RX11-09-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y8/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_126/MGT_X*Y30/RX] 0] ] 18 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 19 | #Creating link: MSP_A_FPGA-TX1-01--RX11-01-MSP_C_FPGA 20 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-01--RX11-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y9/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_124/MGT_X*Y22/RX] 0] ] 21 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 22 | #Creating link: MSP_A_FPGA-TX1-02--RX11-02-MSP_C_FPGA 23 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-02--RX11-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y10/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_125/MGT_X*Y24/RX] 0] ] 24 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 25 | #Creating link: MSP_A_FPGA-TX1-11--RX11-11-MSP_C_FPGA 26 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-11--RX11-11-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y11/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_126/MGT_X*Y29/RX] 0] ] 27 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 28 | #Creating link: MSP_A_FPGA-TX1-10--RX11-10-MSP_C_FPGA 29 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-10--RX11-10-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y12/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_126/MGT_X*Y28/RX] 0] ] 30 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 31 | #Creating link: MSP_A_FPGA-TX1-04--RX11-04-MSP_C_FPGA 32 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-04--RX11-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y13/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_125/MGT_X*Y25/RX] 0] ] 33 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 34 | #Creating link: MSP_A_FPGA-TX1-08--RX11-08-MSP_C_FPGA 35 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-08--RX11-08-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y14/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_125/MGT_X*Y27/RX] 0] ] 36 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 37 | #Creating link: MSP_A_FPGA-TX1-06--RX11-06-MSP_C_FPGA 38 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-06--RX11-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y15/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_125/MGT_X*Y26/RX] 0] ] 39 | lappend MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_A TX1 MSP_C RX11 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_A_TX1_MSP_C_RX11_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX1_RX13.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX1_RX13.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_A_FPGA-TX1-05--RX13-05-MSP_C_FPGA 5 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-05--RX13-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y4/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_130/MGT_X*Y44/RX] 0] ] 6 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 7 | #Creating link: MSP_A_FPGA-TX1-03--RX13-03-MSP_C_FPGA 8 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-03--RX13-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y5/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_130/MGT_X*Y45/RX] 0] ] 9 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 10 | #Creating link: MSP_A_FPGA-TX1-07--RX13-07-MSP_C_FPGA 11 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-07--RX13-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y6/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_131/MGT_X*Y51/RX] 0] ] 12 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 13 | #Creating link: MSP_A_FPGA-TX1-00--RX13-00-MSP_C_FPGA 14 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-00--RX13-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y7/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_130/MGT_X*Y47/RX] 0] ] 15 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 16 | #Creating link: MSP_A_FPGA-TX1-09--RX13-09-MSP_C_FPGA 17 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-09--RX13-09-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y8/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_131/MGT_X*Y50/RX] 0] ] 18 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 19 | #Creating link: MSP_A_FPGA-TX1-01--RX13-01-MSP_C_FPGA 20 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-01--RX13-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y9/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_130/MGT_X*Y46/RX] 0] ] 21 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 22 | #Creating link: MSP_A_FPGA-TX1-02--RX13-02-MSP_C_FPGA 23 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-02--RX13-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y10/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_131/MGT_X*Y48/RX] 0] ] 24 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 25 | #Creating link: MSP_A_FPGA-TX1-11--RX13-11-MSP_C_FPGA 26 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-11--RX13-11-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y11/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_132/MGT_X*Y55/RX] 0] ] 27 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 28 | #Creating link: MSP_A_FPGA-TX1-10--RX13-10-MSP_C_FPGA 29 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-10--RX13-10-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y12/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_132/MGT_X*Y54/RX] 0] ] 30 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 31 | #Creating link: MSP_A_FPGA-TX1-04--RX13-04-MSP_C_FPGA 32 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-04--RX13-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y13/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_131/MGT_X*Y49/RX] 0] ] 33 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 34 | #Creating link: MSP_A_FPGA-TX1-08--RX13-08-MSP_C_FPGA 35 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-08--RX13-08-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y14/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_132/MGT_X*Y53/RX] 0] ] 36 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 37 | #Creating link: MSP_A_FPGA-TX1-06--RX13-06-MSP_C_FPGA 38 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-06--RX13-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y15/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_132/MGT_X*Y52/RX] 0] ] 39 | lappend MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_A TX1 MSP_C RX13 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_A_TX1_MSP_C_RX13_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX1_RX16.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX1_RX16.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_A_FPGA-TX1-05--RX16-05-MSP_C_FPGA 5 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-05--RX16-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y4/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y25/RX] 0] ] 6 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 7 | #Creating link: MSP_A_FPGA-TX1-03--RX16-03-MSP_C_FPGA 8 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-03--RX16-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y5/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y24/RX] 0] ] 9 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 10 | #Creating link: MSP_A_FPGA-TX1-07--RX16-07-MSP_C_FPGA 11 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-07--RX16-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y6/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y26/RX] 0] ] 12 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 13 | #Creating link: MSP_A_FPGA-TX1-00--RX16-00-MSP_C_FPGA 14 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-00--RX16-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y7/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y22/RX] 0] ] 15 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 16 | #Creating link: MSP_A_FPGA-TX1-09--RX16-09-MSP_C_FPGA 17 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-09--RX16-09-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y8/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y27/RX] 0] ] 18 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 19 | #Creating link: MSP_A_FPGA-TX1-01--RX16-01-MSP_C_FPGA 20 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-01--RX16-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y9/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y23/RX] 0] ] 21 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 22 | #Creating link: MSP_A_FPGA-TX1-02--RX16-02-MSP_C_FPGA 23 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-02--RX16-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y10/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y21/RX] 0] ] 24 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 25 | #Creating link: MSP_A_FPGA-TX1-11--RX16-11-MSP_C_FPGA 26 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-11--RX16-11-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y11/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y28/RX] 0] ] 27 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 28 | #Creating link: MSP_A_FPGA-TX1-10--RX16-10-MSP_C_FPGA 29 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-10--RX16-10-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y12/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y29/RX] 0] ] 30 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 31 | #Creating link: MSP_A_FPGA-TX1-04--RX16-04-MSP_C_FPGA 32 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-04--RX16-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y13/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y20/RX] 0] ] 33 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 34 | #Creating link: MSP_A_FPGA-TX1-08--RX16-08-MSP_C_FPGA 35 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-08--RX16-08-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y14/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y30/RX] 0] ] 36 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 37 | #Creating link: MSP_A_FPGA-TX1-06--RX16-06-MSP_C_FPGA 38 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-06--RX16-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y15/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y31/RX] 0] ] 39 | lappend MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_A TX1 MSP_C RX16 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_A_TX1_MSP_C_RX16_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX1_RX18.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX1_RX18.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_A_FPGA-TX1-05--RX18-05-MSP_C_FPGA 5 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-05--RX18-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y4/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_232/MGT_X*Y53/RX] 0] ] 6 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 7 | #Creating link: MSP_A_FPGA-TX1-03--RX18-03-MSP_C_FPGA 8 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-03--RX18-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y5/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_232/MGT_X*Y55/RX] 0] ] 9 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 10 | #Creating link: MSP_A_FPGA-TX1-07--RX18-07-MSP_C_FPGA 11 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-07--RX18-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y6/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_231/MGT_X*Y49/RX] 0] ] 12 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 13 | #Creating link: MSP_A_FPGA-TX1-00--RX18-00-MSP_C_FPGA 14 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-00--RX18-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y7/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_232/MGT_X*Y54/RX] 0] ] 15 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 16 | #Creating link: MSP_A_FPGA-TX1-09--RX18-09-MSP_C_FPGA 17 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-09--RX18-09-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y8/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_230/MGT_X*Y47/RX] 0] ] 18 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 19 | #Creating link: MSP_A_FPGA-TX1-01--RX18-01-MSP_C_FPGA 20 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-01--RX18-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y9/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_232/MGT_X*Y52/RX] 0] ] 21 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 22 | #Creating link: MSP_A_FPGA-TX1-02--RX18-02-MSP_C_FPGA 23 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-02--RX18-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y10/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_231/MGT_X*Y48/RX] 0] ] 24 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 25 | #Creating link: MSP_A_FPGA-TX1-11--RX18-11-MSP_C_FPGA 26 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-11--RX18-11-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y11/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_230/MGT_X*Y46/RX] 0] ] 27 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 28 | #Creating link: MSP_A_FPGA-TX1-10--RX18-10-MSP_C_FPGA 29 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-10--RX18-10-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y12/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_230/MGT_X*Y45/RX] 0] ] 30 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 31 | #Creating link: MSP_A_FPGA-TX1-04--RX18-04-MSP_C_FPGA 32 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-04--RX18-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y13/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_230/MGT_X*Y44/RX] 0] ] 33 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 34 | #Creating link: MSP_A_FPGA-TX1-08--RX18-08-MSP_C_FPGA 35 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-08--RX18-08-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y14/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_231/MGT_X*Y50/RX] 0] ] 36 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 37 | #Creating link: MSP_A_FPGA-TX1-06--RX18-06-MSP_C_FPGA 38 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX1-06--RX18-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y15/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_231/MGT_X*Y51/RX] 0] ] 39 | lappend MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_A TX1 MSP_C RX18 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_A_TX1_MSP_C_RX18_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX2_RX10.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX2_RX10.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_A_FPGA-TX2-03--RX10-03-MSP_C_FPGA 5 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-03--RX10-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_120/MGT_X*Y5/RX] 0] ] 6 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 7 | #Creating link: MSP_A_FPGA-TX2-01--RX10-01-MSP_C_FPGA 8 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-01--RX10-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_122/MGT_X*Y13/RX] 0] ] 9 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 10 | #Creating link: MSP_A_FPGA-TX2-05--RX10-05-MSP_C_FPGA 11 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-05--RX10-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_120/MGT_X*Y4/RX] 0] ] 12 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 13 | #Creating link: MSP_A_FPGA-TX2-00--RX10-00-MSP_C_FPGA 14 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-00--RX10-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_121/MGT_X*Y11/RX] 0] ] 15 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 16 | #Creating link: MSP_A_FPGA-TX2-07--RX10-07-MSP_C_FPGA 17 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-07--RX10-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_122/MGT_X*Y14/RX] 0] ] 18 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 19 | #Creating link: MSP_A_FPGA-TX2-09--RX10-09-MSP_C_FPGA 20 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-09--RX10-09-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_122/MGT_X*Y12/RX] 0] ] 21 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 22 | #Creating link: MSP_A_FPGA-TX2-02--RX10-02-MSP_C_FPGA 23 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-02--RX10-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_121/MGT_X*Y9/RX] 0] ] 24 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 25 | #Creating link: MSP_A_FPGA-TX2-11--RX10-11-MSP_C_FPGA 26 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-11--RX10-11-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_121/MGT_X*Y10/RX] 0] ] 27 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 28 | #Creating link: MSP_A_FPGA-TX2-10--RX10-10-MSP_C_FPGA 29 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-10--RX10-10-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y28/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_121/MGT_X*Y8/RX] 0] ] 30 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 31 | #Creating link: MSP_A_FPGA-TX2-04--RX10-04-MSP_C_FPGA 32 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-04--RX10-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y29/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_120/MGT_X*Y7/RX] 0] ] 33 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 34 | #Creating link: MSP_A_FPGA-TX2-08--RX10-08-MSP_C_FPGA 35 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-08--RX10-08-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y30/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_122/MGT_X*Y15/RX] 0] ] 36 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 37 | #Creating link: MSP_A_FPGA-TX2-06--RX10-06-MSP_C_FPGA 38 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-06--RX10-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y31/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_120/MGT_X*Y6/RX] 0] ] 39 | lappend MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_A TX2 MSP_C RX10 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_A_TX2_MSP_C_RX10_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX2_RX12.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX2_RX12.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_A_FPGA-TX2-03--RX12-03-MSP_C_FPGA 5 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-03--RX12-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_127/MGT_X*Y33/RX] 0] ] 6 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 7 | #Creating link: MSP_A_FPGA-TX2-01--RX12-01-MSP_C_FPGA 8 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-01--RX12-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_127/MGT_X*Y34/RX] 0] ] 9 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 10 | #Creating link: MSP_A_FPGA-TX2-05--RX12-05-MSP_C_FPGA 11 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-05--RX12-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_127/MGT_X*Y32/RX] 0] ] 12 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 13 | #Creating link: MSP_A_FPGA-TX2-00--RX12-00-MSP_C_FPGA 14 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-00--RX12-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_127/MGT_X*Y35/RX] 0] ] 15 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 16 | #Creating link: MSP_A_FPGA-TX2-07--RX12-07-MSP_C_FPGA 17 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-07--RX12-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_129/MGT_X*Y43/RX] 0] ] 18 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 19 | #Creating link: MSP_A_FPGA-TX2-09--RX12-09-MSP_C_FPGA 20 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-09--RX12-09-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_129/MGT_X*Y42/RX] 0] ] 21 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 22 | #Creating link: MSP_A_FPGA-TX2-02--RX12-02-MSP_C_FPGA 23 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-02--RX12-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_128/MGT_X*Y36/RX] 0] ] 24 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 25 | #Creating link: MSP_A_FPGA-TX2-11--RX12-11-MSP_C_FPGA 26 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-11--RX12-11-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_129/MGT_X*Y41/RX] 0] ] 27 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 28 | #Creating link: MSP_A_FPGA-TX2-10--RX12-10-MSP_C_FPGA 29 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-10--RX12-10-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y28/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_129/MGT_X*Y40/RX] 0] ] 30 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 31 | #Creating link: MSP_A_FPGA-TX2-04--RX12-04-MSP_C_FPGA 32 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-04--RX12-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y29/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_128/MGT_X*Y37/RX] 0] ] 33 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 34 | #Creating link: MSP_A_FPGA-TX2-08--RX12-08-MSP_C_FPGA 35 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-08--RX12-08-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y30/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_128/MGT_X*Y39/RX] 0] ] 36 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 37 | #Creating link: MSP_A_FPGA-TX2-06--RX12-06-MSP_C_FPGA 38 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-06--RX12-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y31/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_128/MGT_X*Y38/RX] 0] ] 39 | lappend MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_A TX2 MSP_C RX12 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_A_TX2_MSP_C_RX12_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX2_RX15.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX2_RX15.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_A_FPGA-TX2-03--RX15-03-MSP_C_FPGA 5 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-03--RX15-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y8/RX] 0] ] 6 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 7 | #Creating link: MSP_A_FPGA-TX2-01--RX15-01-MSP_C_FPGA 8 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-01--RX15-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y7/RX] 0] ] 9 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 10 | #Creating link: MSP_A_FPGA-TX2-05--RX15-05-MSP_C_FPGA 11 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-05--RX15-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y9/RX] 0] ] 12 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 13 | #Creating link: MSP_A_FPGA-TX2-00--RX15-00-MSP_C_FPGA 14 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-00--RX15-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y6/RX] 0] ] 15 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 16 | #Creating link: MSP_A_FPGA-TX2-07--RX15-07-MSP_C_FPGA 17 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-07--RX15-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y10/RX] 0] ] 18 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 19 | #Creating link: MSP_A_FPGA-TX2-09--RX15-09-MSP_C_FPGA 20 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-09--RX15-09-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y11/RX] 0] ] 21 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 22 | #Creating link: MSP_A_FPGA-TX2-02--RX15-02-MSP_C_FPGA 23 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-02--RX15-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y5/RX] 0] ] 24 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 25 | #Creating link: MSP_A_FPGA-TX2-11--RX15-11-MSP_C_FPGA 26 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-11--RX15-11-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y12/RX] 0] ] 27 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 28 | #Creating link: MSP_A_FPGA-TX2-10--RX15-10-MSP_C_FPGA 29 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-10--RX15-10-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y28/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y13/RX] 0] ] 30 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 31 | #Creating link: MSP_A_FPGA-TX2-04--RX15-04-MSP_C_FPGA 32 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-04--RX15-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y29/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y4/RX] 0] ] 33 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 34 | #Creating link: MSP_A_FPGA-TX2-08--RX15-08-MSP_C_FPGA 35 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-08--RX15-08-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y30/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y14/RX] 0] ] 36 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 37 | #Creating link: MSP_A_FPGA-TX2-06--RX15-06-MSP_C_FPGA 38 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-06--RX15-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y31/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y15/RX] 0] ] 39 | lappend MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_A TX2 MSP_C RX15 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_A_TX2_MSP_C_RX15_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX2_RX17.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX2_RX17.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_A_FPGA-TX2-03--RX17-03-MSP_C_FPGA 5 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-03--RX17-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_228/MGT_X*Y36/RX] 0] ] 6 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 7 | #Creating link: MSP_A_FPGA-TX2-01--RX17-01-MSP_C_FPGA 8 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-01--RX17-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_227/MGT_X*Y35/RX] 0] ] 9 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 10 | #Creating link: MSP_A_FPGA-TX2-05--RX17-05-MSP_C_FPGA 11 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-05--RX17-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_228/MGT_X*Y37/RX] 0] ] 12 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 13 | #Creating link: MSP_A_FPGA-TX2-00--RX17-00-MSP_C_FPGA 14 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-00--RX17-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_227/MGT_X*Y32/RX] 0] ] 15 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 16 | #Creating link: MSP_A_FPGA-TX2-07--RX17-07-MSP_C_FPGA 17 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-07--RX17-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_228/MGT_X*Y38/RX] 0] ] 18 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 19 | #Creating link: MSP_A_FPGA-TX2-09--RX17-09-MSP_C_FPGA 20 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-09--RX17-09-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_228/MGT_X*Y39/RX] 0] ] 21 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 22 | #Creating link: MSP_A_FPGA-TX2-02--RX17-02-MSP_C_FPGA 23 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-02--RX17-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_227/MGT_X*Y33/RX] 0] ] 24 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 25 | #Creating link: MSP_A_FPGA-TX2-11--RX17-11-MSP_C_FPGA 26 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-11--RX17-11-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_229/MGT_X*Y40/RX] 0] ] 27 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 28 | #Creating link: MSP_A_FPGA-TX2-10--RX17-10-MSP_C_FPGA 29 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-10--RX17-10-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y28/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_229/MGT_X*Y41/RX] 0] ] 30 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 31 | #Creating link: MSP_A_FPGA-TX2-04--RX17-04-MSP_C_FPGA 32 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-04--RX17-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y29/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_227/MGT_X*Y34/RX] 0] ] 33 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 34 | #Creating link: MSP_A_FPGA-TX2-08--RX17-08-MSP_C_FPGA 35 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-08--RX17-08-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y30/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_229/MGT_X*Y42/RX] 0] ] 36 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 37 | #Creating link: MSP_A_FPGA-TX2-06--RX17-06-MSP_C_FPGA 38 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_A_FPGA-TX2-06--RX17-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y31/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_229/MGT_X*Y43/RX] 0] ] 39 | lappend MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_A TX2 MSP_C RX17 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_A_TX2_MSP_C_RX17_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX3_RX2.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX3_RX2.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_C_FPGA-TX3-05--RX2-05-MSP_A_FPGA 5 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-05--RX2-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y4/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_124/MGT_X*Y20/RX] 0] ] 6 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 7 | #Creating link: MSP_C_FPGA-TX3-03--RX2-03-MSP_A_FPGA 8 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-03--RX2-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y5/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_124/MGT_X*Y21/RX] 0] ] 9 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 10 | #Creating link: MSP_C_FPGA-TX3-07--RX2-07-MSP_A_FPGA 11 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-07--RX2-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y6/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_126/MGT_X*Y31/RX] 0] ] 12 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 13 | #Creating link: MSP_C_FPGA-TX3-00--RX2-00-MSP_A_FPGA 14 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-00--RX2-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y7/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_124/MGT_X*Y23/RX] 0] ] 15 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 16 | #Creating link: MSP_C_FPGA-TX3-09--RX2-09-MSP_A_FPGA 17 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-09--RX2-09-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y8/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_126/MGT_X*Y30/RX] 0] ] 18 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 19 | #Creating link: MSP_C_FPGA-TX3-01--RX2-01-MSP_A_FPGA 20 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-01--RX2-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y9/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_124/MGT_X*Y22/RX] 0] ] 21 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 22 | #Creating link: MSP_C_FPGA-TX3-02--RX2-02-MSP_A_FPGA 23 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-02--RX2-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y10/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_125/MGT_X*Y24/RX] 0] ] 24 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 25 | #Creating link: MSP_C_FPGA-TX3-11--RX2-11-MSP_A_FPGA 26 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-11--RX2-11-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y11/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_126/MGT_X*Y29/RX] 0] ] 27 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 28 | #Creating link: MSP_C_FPGA-TX3-10--RX2-10-MSP_A_FPGA 29 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-10--RX2-10-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y12/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_126/MGT_X*Y28/RX] 0] ] 30 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 31 | #Creating link: MSP_C_FPGA-TX3-04--RX2-04-MSP_A_FPGA 32 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-04--RX2-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y13/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_125/MGT_X*Y25/RX] 0] ] 33 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 34 | #Creating link: MSP_C_FPGA-TX3-08--RX2-08-MSP_A_FPGA 35 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-08--RX2-08-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y14/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_125/MGT_X*Y27/RX] 0] ] 36 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 37 | #Creating link: MSP_C_FPGA-TX3-06--RX2-06-MSP_A_FPGA 38 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-06--RX2-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y15/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_125/MGT_X*Y26/RX] 0] ] 39 | lappend MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_C TX3 MSP_A RX2 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_C_TX3_MSP_A_RX2_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX3_RX4.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX3_RX4.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_C_FPGA-TX3-05--RX4-05-MSP_A_FPGA 5 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-05--RX4-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y4/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_130/MGT_X*Y44/RX] 0] ] 6 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 7 | #Creating link: MSP_C_FPGA-TX3-03--RX4-03-MSP_A_FPGA 8 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-03--RX4-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y5/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_130/MGT_X*Y45/RX] 0] ] 9 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 10 | #Creating link: MSP_C_FPGA-TX3-07--RX4-07-MSP_A_FPGA 11 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-07--RX4-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y6/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_131/MGT_X*Y51/RX] 0] ] 12 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 13 | #Creating link: MSP_C_FPGA-TX3-00--RX4-00-MSP_A_FPGA 14 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-00--RX4-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y7/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_130/MGT_X*Y47/RX] 0] ] 15 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 16 | #Creating link: MSP_C_FPGA-TX3-09--RX4-09-MSP_A_FPGA 17 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-09--RX4-09-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y8/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_131/MGT_X*Y50/RX] 0] ] 18 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 19 | #Creating link: MSP_C_FPGA-TX3-01--RX4-01-MSP_A_FPGA 20 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-01--RX4-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y9/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_130/MGT_X*Y46/RX] 0] ] 21 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 22 | #Creating link: MSP_C_FPGA-TX3-02--RX4-02-MSP_A_FPGA 23 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-02--RX4-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y10/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_131/MGT_X*Y48/RX] 0] ] 24 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 25 | #Creating link: MSP_C_FPGA-TX3-11--RX4-11-MSP_A_FPGA 26 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-11--RX4-11-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y11/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_132/MGT_X*Y55/RX] 0] ] 27 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 28 | #Creating link: MSP_C_FPGA-TX3-10--RX4-10-MSP_A_FPGA 29 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-10--RX4-10-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y12/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_132/MGT_X*Y54/RX] 0] ] 30 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 31 | #Creating link: MSP_C_FPGA-TX3-04--RX4-04-MSP_A_FPGA 32 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-04--RX4-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y13/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_131/MGT_X*Y49/RX] 0] ] 33 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 34 | #Creating link: MSP_C_FPGA-TX3-08--RX4-08-MSP_A_FPGA 35 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-08--RX4-08-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y14/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_132/MGT_X*Y53/RX] 0] ] 36 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 37 | #Creating link: MSP_C_FPGA-TX3-06--RX4-06-MSP_A_FPGA 38 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-06--RX4-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y15/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_132/MGT_X*Y52/RX] 0] ] 39 | lappend MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_C TX3 MSP_A RX4 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_C_TX3_MSP_A_RX4_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX3_RX7.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX3_RX7.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_C_FPGA-TX3-05--RX7-05-MSP_A_FPGA 5 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-05--RX7-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y4/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y25/RX] 0] ] 6 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 7 | #Creating link: MSP_C_FPGA-TX3-03--RX7-03-MSP_A_FPGA 8 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-03--RX7-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y5/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y24/RX] 0] ] 9 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 10 | #Creating link: MSP_C_FPGA-TX3-07--RX7-07-MSP_A_FPGA 11 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-07--RX7-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y6/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y26/RX] 0] ] 12 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 13 | #Creating link: MSP_C_FPGA-TX3-00--RX7-00-MSP_A_FPGA 14 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-00--RX7-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y7/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y22/RX] 0] ] 15 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 16 | #Creating link: MSP_C_FPGA-TX3-09--RX7-09-MSP_A_FPGA 17 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-09--RX7-09-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y8/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_225/MGT_X*Y27/RX] 0] ] 18 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 19 | #Creating link: MSP_C_FPGA-TX3-01--RX7-01-MSP_A_FPGA 20 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-01--RX7-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y9/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y23/RX] 0] ] 21 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 22 | #Creating link: MSP_C_FPGA-TX3-02--RX7-02-MSP_A_FPGA 23 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-02--RX7-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y10/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y21/RX] 0] ] 24 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 25 | #Creating link: MSP_C_FPGA-TX3-11--RX7-11-MSP_A_FPGA 26 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-11--RX7-11-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y11/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y28/RX] 0] ] 27 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 28 | #Creating link: MSP_C_FPGA-TX3-10--RX7-10-MSP_A_FPGA 29 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-10--RX7-10-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y12/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y29/RX] 0] ] 30 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 31 | #Creating link: MSP_C_FPGA-TX3-04--RX7-04-MSP_A_FPGA 32 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-04--RX7-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y13/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_224/MGT_X*Y20/RX] 0] ] 33 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 34 | #Creating link: MSP_C_FPGA-TX3-08--RX7-08-MSP_A_FPGA 35 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-08--RX7-08-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y14/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y30/RX] 0] ] 36 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 37 | #Creating link: MSP_C_FPGA-TX3-06--RX7-06-MSP_A_FPGA 38 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-06--RX7-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y15/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_226/MGT_X*Y31/RX] 0] ] 39 | lappend MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_C TX3 MSP_A RX7 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_C_TX3_MSP_A_RX7_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX3_RX9.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX3_RX9.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_C_FPGA-TX3-05--RX9-05-MSP_A_FPGA 5 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-05--RX9-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y4/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_232/MGT_X*Y53/RX] 0] ] 6 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 7 | #Creating link: MSP_C_FPGA-TX3-03--RX9-03-MSP_A_FPGA 8 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-03--RX9-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y5/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_232/MGT_X*Y55/RX] 0] ] 9 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 10 | #Creating link: MSP_C_FPGA-TX3-07--RX9-07-MSP_A_FPGA 11 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-07--RX9-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y6/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_231/MGT_X*Y49/RX] 0] ] 12 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 13 | #Creating link: MSP_C_FPGA-TX3-00--RX9-00-MSP_A_FPGA 14 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-00--RX9-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_220/MGT_X*Y7/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_232/MGT_X*Y54/RX] 0] ] 15 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 16 | #Creating link: MSP_C_FPGA-TX3-09--RX9-09-MSP_A_FPGA 17 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-09--RX9-09-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y8/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_230/MGT_X*Y47/RX] 0] ] 18 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 19 | #Creating link: MSP_C_FPGA-TX3-01--RX9-01-MSP_A_FPGA 20 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-01--RX9-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y9/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_232/MGT_X*Y52/RX] 0] ] 21 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 22 | #Creating link: MSP_C_FPGA-TX3-02--RX9-02-MSP_A_FPGA 23 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-02--RX9-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y10/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_231/MGT_X*Y48/RX] 0] ] 24 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 25 | #Creating link: MSP_C_FPGA-TX3-11--RX9-11-MSP_A_FPGA 26 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-11--RX9-11-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_221/MGT_X*Y11/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_230/MGT_X*Y46/RX] 0] ] 27 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 28 | #Creating link: MSP_C_FPGA-TX3-10--RX9-10-MSP_A_FPGA 29 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-10--RX9-10-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y12/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_230/MGT_X*Y45/RX] 0] ] 30 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 31 | #Creating link: MSP_C_FPGA-TX3-04--RX9-04-MSP_A_FPGA 32 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-04--RX9-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y13/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_230/MGT_X*Y44/RX] 0] ] 33 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 34 | #Creating link: MSP_C_FPGA-TX3-08--RX9-08-MSP_A_FPGA 35 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-08--RX9-08-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y14/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_231/MGT_X*Y50/RX] 0] ] 36 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 37 | #Creating link: MSP_C_FPGA-TX3-06--RX9-06-MSP_A_FPGA 38 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX3-06--RX9-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_222/MGT_X*Y15/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_231/MGT_X*Y51/RX] 0] ] 39 | lappend MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_C TX3 MSP_A RX9 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_C_TX3_MSP_A_RX9_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX4_RX1.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX4_RX1.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_C_FPGA-TX4-03--RX1-03-MSP_A_FPGA 5 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-03--RX1-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_120/MGT_X*Y5/RX] 0] ] 6 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 7 | #Creating link: MSP_C_FPGA-TX4-01--RX1-01-MSP_A_FPGA 8 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-01--RX1-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_122/MGT_X*Y13/RX] 0] ] 9 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 10 | #Creating link: MSP_C_FPGA-TX4-05--RX1-05-MSP_A_FPGA 11 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-05--RX1-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_120/MGT_X*Y4/RX] 0] ] 12 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 13 | #Creating link: MSP_C_FPGA-TX4-00--RX1-00-MSP_A_FPGA 14 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-00--RX1-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_121/MGT_X*Y11/RX] 0] ] 15 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 16 | #Creating link: MSP_C_FPGA-TX4-07--RX1-07-MSP_A_FPGA 17 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-07--RX1-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_122/MGT_X*Y14/RX] 0] ] 18 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 19 | #Creating link: MSP_C_FPGA-TX4-09--RX1-09-MSP_A_FPGA 20 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-09--RX1-09-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_122/MGT_X*Y12/RX] 0] ] 21 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 22 | #Creating link: MSP_C_FPGA-TX4-02--RX1-02-MSP_A_FPGA 23 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-02--RX1-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_121/MGT_X*Y9/RX] 0] ] 24 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 25 | #Creating link: MSP_C_FPGA-TX4-11--RX1-11-MSP_A_FPGA 26 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-11--RX1-11-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_121/MGT_X*Y10/RX] 0] ] 27 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 28 | #Creating link: MSP_C_FPGA-TX4-10--RX1-10-MSP_A_FPGA 29 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-10--RX1-10-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y28/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_121/MGT_X*Y8/RX] 0] ] 30 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 31 | #Creating link: MSP_C_FPGA-TX4-04--RX1-04-MSP_A_FPGA 32 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-04--RX1-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y29/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_120/MGT_X*Y7/RX] 0] ] 33 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 34 | #Creating link: MSP_C_FPGA-TX4-08--RX1-08-MSP_A_FPGA 35 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-08--RX1-08-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y30/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_122/MGT_X*Y15/RX] 0] ] 36 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 37 | #Creating link: MSP_C_FPGA-TX4-06--RX1-06-MSP_A_FPGA 38 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-06--RX1-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y31/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_120/MGT_X*Y6/RX] 0] ] 39 | lappend MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_C TX4 MSP_A RX1 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_C_TX4_MSP_A_RX1_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX4_RX3.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX4_RX3.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_C_FPGA-TX4-03--RX3-03-MSP_A_FPGA 5 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-03--RX3-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_127/MGT_X*Y33/RX] 0] ] 6 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 7 | #Creating link: MSP_C_FPGA-TX4-01--RX3-01-MSP_A_FPGA 8 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-01--RX3-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_127/MGT_X*Y34/RX] 0] ] 9 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 10 | #Creating link: MSP_C_FPGA-TX4-05--RX3-05-MSP_A_FPGA 11 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-05--RX3-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_127/MGT_X*Y32/RX] 0] ] 12 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 13 | #Creating link: MSP_C_FPGA-TX4-00--RX3-00-MSP_A_FPGA 14 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-00--RX3-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_127/MGT_X*Y35/RX] 0] ] 15 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 16 | #Creating link: MSP_C_FPGA-TX4-07--RX3-07-MSP_A_FPGA 17 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-07--RX3-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_129/MGT_X*Y43/RX] 0] ] 18 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 19 | #Creating link: MSP_C_FPGA-TX4-09--RX3-09-MSP_A_FPGA 20 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-09--RX3-09-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_129/MGT_X*Y42/RX] 0] ] 21 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 22 | #Creating link: MSP_C_FPGA-TX4-02--RX3-02-MSP_A_FPGA 23 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-02--RX3-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_128/MGT_X*Y36/RX] 0] ] 24 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 25 | #Creating link: MSP_C_FPGA-TX4-11--RX3-11-MSP_A_FPGA 26 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-11--RX3-11-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_129/MGT_X*Y41/RX] 0] ] 27 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 28 | #Creating link: MSP_C_FPGA-TX4-10--RX3-10-MSP_A_FPGA 29 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-10--RX3-10-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y28/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_129/MGT_X*Y40/RX] 0] ] 30 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 31 | #Creating link: MSP_C_FPGA-TX4-04--RX3-04-MSP_A_FPGA 32 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-04--RX3-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y29/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_128/MGT_X*Y37/RX] 0] ] 33 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 34 | #Creating link: MSP_C_FPGA-TX4-08--RX3-08-MSP_A_FPGA 35 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-08--RX3-08-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y30/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_128/MGT_X*Y39/RX] 0] ] 36 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 37 | #Creating link: MSP_C_FPGA-TX4-06--RX3-06-MSP_A_FPGA 38 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-06--RX3-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y31/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_128/MGT_X*Y38/RX] 0] ] 39 | lappend MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_C TX4 MSP_A RX3 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_C_TX4_MSP_A_RX3_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX4_RX6.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX4_RX6.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_C_FPGA-TX4-03--RX6-03-MSP_A_FPGA 5 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-03--RX6-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y8/RX] 0] ] 6 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 7 | #Creating link: MSP_C_FPGA-TX4-01--RX6-01-MSP_A_FPGA 8 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-01--RX6-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y7/RX] 0] ] 9 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 10 | #Creating link: MSP_C_FPGA-TX4-05--RX6-05-MSP_A_FPGA 11 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-05--RX6-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y9/RX] 0] ] 12 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 13 | #Creating link: MSP_C_FPGA-TX4-00--RX6-00-MSP_A_FPGA 14 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-00--RX6-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y6/RX] 0] ] 15 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 16 | #Creating link: MSP_C_FPGA-TX4-07--RX6-07-MSP_A_FPGA 17 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-07--RX6-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y10/RX] 0] ] 18 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 19 | #Creating link: MSP_C_FPGA-TX4-09--RX6-09-MSP_A_FPGA 20 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-09--RX6-09-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_221/MGT_X*Y11/RX] 0] ] 21 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 22 | #Creating link: MSP_C_FPGA-TX4-02--RX6-02-MSP_A_FPGA 23 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-02--RX6-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y5/RX] 0] ] 24 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 25 | #Creating link: MSP_C_FPGA-TX4-11--RX6-11-MSP_A_FPGA 26 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-11--RX6-11-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y12/RX] 0] ] 27 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 28 | #Creating link: MSP_C_FPGA-TX4-10--RX6-10-MSP_A_FPGA 29 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-10--RX6-10-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y28/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y13/RX] 0] ] 30 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 31 | #Creating link: MSP_C_FPGA-TX4-04--RX6-04-MSP_A_FPGA 32 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-04--RX6-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y29/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_220/MGT_X*Y4/RX] 0] ] 33 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 34 | #Creating link: MSP_C_FPGA-TX4-08--RX6-08-MSP_A_FPGA 35 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-08--RX6-08-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y30/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y14/RX] 0] ] 36 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 37 | #Creating link: MSP_C_FPGA-TX4-06--RX6-06-MSP_A_FPGA 38 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-06--RX6-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y31/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_222/MGT_X*Y15/RX] 0] ] 39 | lappend MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_C TX4 MSP_A RX6 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_C_TX4_MSP_A_RX6_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX4_RX8.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX4_RX8.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkLinkList 3 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList [list] 4 | #Creating link: MSP_C_FPGA-TX4-03--RX8-03-MSP_A_FPGA 5 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-03--RX8-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_228/MGT_X*Y36/RX] 0] ] 6 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 7 | #Creating link: MSP_C_FPGA-TX4-01--RX8-01-MSP_A_FPGA 8 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-01--RX8-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_227/MGT_X*Y35/RX] 0] ] 9 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 10 | #Creating link: MSP_C_FPGA-TX4-05--RX8-05-MSP_A_FPGA 11 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-05--RX8-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_228/MGT_X*Y37/RX] 0] ] 12 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 13 | #Creating link: MSP_C_FPGA-TX4-00--RX8-00-MSP_A_FPGA 14 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-00--RX8-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_224/MGT_X*Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_227/MGT_X*Y32/RX] 0] ] 15 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 16 | #Creating link: MSP_C_FPGA-TX4-07--RX8-07-MSP_A_FPGA 17 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-07--RX8-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_228/MGT_X*Y38/RX] 0] ] 18 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 19 | #Creating link: MSP_C_FPGA-TX4-09--RX8-09-MSP_A_FPGA 20 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-09--RX8-09-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_228/MGT_X*Y39/RX] 0] ] 21 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 22 | #Creating link: MSP_C_FPGA-TX4-02--RX8-02-MSP_A_FPGA 23 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-02--RX8-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_227/MGT_X*Y33/RX] 0] ] 24 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 25 | #Creating link: MSP_C_FPGA-TX4-11--RX8-11-MSP_A_FPGA 26 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-11--RX8-11-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_225/MGT_X*Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_229/MGT_X*Y40/RX] 0] ] 27 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 28 | #Creating link: MSP_C_FPGA-TX4-10--RX8-10-MSP_A_FPGA 29 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-10--RX8-10-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y28/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_229/MGT_X*Y41/RX] 0] ] 30 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 31 | #Creating link: MSP_C_FPGA-TX4-04--RX8-04-MSP_A_FPGA 32 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-04--RX8-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y29/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_227/MGT_X*Y34/RX] 0] ] 33 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 34 | #Creating link: MSP_C_FPGA-TX4-08--RX8-08-MSP_A_FPGA 35 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-08--RX8-08-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y30/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_229/MGT_X*Y42/RX] 0] ] 36 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 37 | #Creating link: MSP_C_FPGA-TX4-06--RX8-06-MSP_A_FPGA 38 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink [create_hw_sio_link -description {MSP_C_FPGA-TX4-06--RX8-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_226/MGT_X*Y31/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_229/MGT_X*Y43/RX] 0] ] 39 | lappend MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLink 40 | # Creating link group MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkGroupLinkGroup 41 | set MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {MSP_C TX4 MSP_A RX8 Minipod Loopback} [get_hw_sio_links $MuctpiMSP_C_TX4_MSP_A_RX8_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX5_RX14.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX5_RX14.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkLinkList 3 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList [list] 4 | #Creating link: TRP_FPGA-TX5-05--RX14-05-MSP_C_FPGA 5 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-05--RX14-05-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_133/MGT_X*Y56/RX] 0] ] 6 | lappend MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink 7 | #Creating link: TRP_FPGA-TX5-01--RX14-01-MSP_C_FPGA 8 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-01--RX14-01-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_133/MGT_X*Y57/RX] 0] ] 9 | lappend MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink 10 | #Creating link: TRP_FPGA-TX5-03--RX14-03-MSP_C_FPGA 11 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-03--RX14-03-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_133/MGT_X*Y58/RX] 0] ] 12 | lappend MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink 13 | #Creating link: TRP_FPGA-TX5-00--RX14-00-MSP_C_FPGA 14 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-00--RX14-00-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_133/MGT_X*Y59/RX] 0] ] 15 | lappend MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink 16 | #Creating link: TRP_FPGA-TX5-06--RX14-06-MSP_C_FPGA 17 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-06--RX14-06-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_233/MGT_X*Y56/RX] 0] ] 18 | lappend MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink 19 | #Creating link: TRP_FPGA-TX5-02--RX14-02-MSP_C_FPGA 20 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-02--RX14-02-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_233/MGT_X*Y57/RX] 0] ] 21 | lappend MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink 22 | #Creating link: TRP_FPGA-TX5-07--RX14-07-MSP_C_FPGA 23 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-07--RX14-07-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_233/MGT_X*Y58/RX] 0] ] 24 | lappend MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink 25 | #Creating link: TRP_FPGA-TX5-04--RX14-04-MSP_C_FPGA 26 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-04--RX14-04-MSP_C_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/1_1_0_*/IBERT/Quad_233/MGT_X*Y59/RX] 0] ] 27 | lappend MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLink 28 | # Creating link group MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkGroupLinkGroup 29 | set MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {Partial TRP TX5 MSP_C RX14 Minipod Loopback} [get_hw_sio_links $MuctpiPartial_TRP_TX5_MSP_C_RX14_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/create_links_TX5_RX5.tcl: -------------------------------------------------------------------------------- 1 | # MUCTPI IBERT ../out/tcl/create_links_TX5_RX5.tcl FILE. Automatically generated by ibert_tcl_generator with input data from MyPinoutUtils. Author: Marcos Oliveira. 2 | # Creating link list MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkLinkList 3 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList [list] 4 | #Creating link: TRP_FPGA-TX5-05--RX5-05-MSP_A_FPGA 5 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-05--RX5-05-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y24/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_133/MGT_X*Y56/RX] 0] ] 6 | lappend MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink 7 | #Creating link: TRP_FPGA-TX5-01--RX5-01-MSP_A_FPGA 8 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-01--RX5-01-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y22/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_133/MGT_X*Y57/RX] 0] ] 9 | lappend MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink 10 | #Creating link: TRP_FPGA-TX5-03--RX5-03-MSP_A_FPGA 11 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-03--RX5-03-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y23/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_133/MGT_X*Y58/RX] 0] ] 12 | lappend MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink 13 | #Creating link: TRP_FPGA-TX5-00--RX5-00-MSP_A_FPGA 14 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-00--RX5-00-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y21/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_133/MGT_X*Y59/RX] 0] ] 15 | lappend MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink 16 | #Creating link: TRP_FPGA-TX5-06--RX5-06-MSP_A_FPGA 17 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-06--RX5-06-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y26/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_233/MGT_X*Y56/RX] 0] ] 18 | lappend MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink 19 | #Creating link: TRP_FPGA-TX5-02--RX5-02-MSP_A_FPGA 20 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-02--RX5-02-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y20/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_233/MGT_X*Y57/RX] 0] ] 21 | lappend MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink 22 | #Creating link: TRP_FPGA-TX5-07--RX5-07-MSP_A_FPGA 23 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-07--RX5-07-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y27/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_233/MGT_X*Y58/RX] 0] ] 24 | lappend MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink 25 | #Creating link: TRP_FPGA-TX5-04--RX5-04-MSP_A_FPGA 26 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink [create_hw_sio_link -description {TRP_FPGA-TX5-04--RX5-04-MSP_A_FPGA} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y25/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/*/0_1_0_*/IBERT/Quad_233/MGT_X*Y59/RX] 0] ] 27 | lappend MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLink 28 | # Creating link group MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkGroupLinkGroup 29 | set MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkGroup [create_hw_sio_linkgroup -description {Partial TRP TX5 MSP_A RX5 Minipod Loopback} [get_hw_sio_links $MuctpiPartial_TRP_TX5_MSP_A_RX5_Minipod_LoopbackLinkList]] -------------------------------------------------------------------------------- /out/tcl/flat_eq.tcl: -------------------------------------------------------------------------------- 1 | set_property PORT.RXLPMHFHOLD 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 2 | set_property PORT.RXLPMHFOVRDEN 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 3 | set_property PORT.RXLPMLFHOLD 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 4 | set_property PORT.RXLPMLFKLOVRDEN 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 5 | set_property PORT.RXDFELPMRESET 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 6 | set_property PORT.RXDFELPMRESET 0 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 7 | -------------------------------------------------------------------------------- /out/tcl/gtytx_powerdown.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # power down GTY transmitters in MSP FPGAs 3 | # 4 | # MSPA 5 | set_property PORT.TXPD 3 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/0_1_0_65/IBERT/Quad_1*/MGT_*] 6 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/0_1_0_65/IBERT/Quad_1*/MGT_*] 7 | # MSPC 8 | set_property PORT.TXPD 3 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/1_1_0_65/IBERT/Quad_1*/MGT_*] 9 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/1_1_0_65/IBERT/Quad_1*/MGT_*] 10 | # TRP 11 | set_property PORT.TXPD 3 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_40/IBERT/Quad_1*/MGT_*] 12 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_40/IBERT/Quad_1*/MGT_*] 13 | -------------------------------------------------------------------------------- /out/tcl/power_down_gty_tx.tcl: -------------------------------------------------------------------------------- 1 | # MSPA 2 | set_property PORT.TXPD 3 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/0_1_0_*/IBERT/Quad_1*/MGT_*] 3 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/0_1_0_*/IBERT/Quad_1*/MGT_*] 4 | # MSPC 5 | set_property PORT.TXPD 3 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/1_1_0_*/IBERT/Quad_1*/MGT_*] 6 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/1_1_0_*/IBERT/Quad_1*/MGT_*] 7 | # TRP 8 | set_property PORT.TXPD 3 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_*/IBERT/Quad_1*/MGT_*] 9 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_*/IBERT/Quad_1*/MGT_*] 10 | # except Quad_124/MGT_X0Y0 (TTC SFP) 11 | set_property PORT.TXPD 0 [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_*/IBERT/Quad_124/MGT_X0Y0] 12 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_*/IBERT/Quad_124/MGT_X0Y0] 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /out/tcl/prbs31_all.tcl: -------------------------------------------------------------------------------- 1 | set_property RX_PATTERN {PRBS 31-bit} [get_hw_sio_gts *] 2 | commit_hw_sio [get_hw_sio_gts *] 3 | set_property TX_PATTERN {PRBS 31-bit} [get_hw_sio_gts *] 4 | commit_hw_sio [get_hw_sio_gts *] 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /out/tcl/remove_links.tcl: -------------------------------------------------------------------------------- 1 | remove_hw_sio_link [get_hw_sio_links *] 2 | 3 | -------------------------------------------------------------------------------- /out/tcl/reset_all.tcl: -------------------------------------------------------------------------------- 1 | set_property PORT.QPLL0RESET 1 [get_hw_sio_commons *];commit_hw_sio [list [get_hw_sio_commons {*}] ] 2 | set_property PORT.QPLL0RESET 0 [get_hw_sio_commons *];commit_hw_sio [list [get_hw_sio_commons {*}] ] 3 | set_property PORT.QPLL1RESET 1 [get_hw_sio_commons *];commit_hw_sio [list [get_hw_sio_commons {*}] ] 4 | set_property PORT.QPLL1RESET 0 [get_hw_sio_commons *];commit_hw_sio [list [get_hw_sio_commons {*}] ] 5 | set_property PORT.CPLLRESET 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 6 | set_property PORT.CPLLRESET 0 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 7 | set_property PORT.GTRXRESET 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 8 | set_property PORT.GTRXRESET 0 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 9 | set_property PORT.GTTXRESET 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 10 | set_property PORT.GTTXRESET 0 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 11 | set_property LOGIC.RX_RESET_DATAPATH 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 12 | set_property LOGIC.RX_RESET_DATAPATH 0 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 13 | set_property LOGIC.MGT_ERRCNT_RESET_CTRL 1 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 14 | set_property LOGIC.MGT_ERRCNT_RESET_CTRL 0 [get_hw_sio_gts *];commit_hw_sio [list [get_hw_sio_gts {*}] ] 15 | 16 | refresh_hw_sio [get_hw_sio_gts *] 17 | refresh_hw_sio [get_hw_sio_commons *] 18 | -------------------------------------------------------------------------------- /out/tcl/scan.tcl: -------------------------------------------------------------------------------- 1 | proc scan {links} { 2 | set h_inc 1 3 | set v_inc 1 4 | set d_ber 1e-6 5 | set length [llength $links] 6 | for {set i 0} {$i < $length} {incr i} { 7 | set description [get_property DESCRIPTION [get_hw_sio_links [lindex $links $i]]] 8 | puts "Creating & Running scan for link: $description" 9 | set scan_obj [create_hw_sio_scan -description $description 2d_full_eye [lindex [get_hw_sio_links [lindex $links $i]] 0 ]] 10 | set_property RESET_RX_AFTER_APPLYING_SETTINGS 1 [get_hw_sio_scans $scan_obj] 11 | set_property HORIZONTAL_INCREMENT $h_inc [get_hw_sio_scans $scan_obj] 12 | set_property VERTICAL_INCREMENT $v_inc [get_hw_sio_scans $scan_obj] 13 | set_property DWELL_BER $d_ber [get_hw_sio_scans $scan_obj] 14 | run_hw_sio_scan [get_hw_sio_scans $scan_obj] 15 | wait_on_hw_sio_scan [get_hw_sio_scans $scan_obj] 16 | write_hw_sio_scan -force [concat ../scans/csv/$description] [get_hw_sio_scans $scan_obj] 17 | #remove_hw_sio_scan [get_hw_sio_scans $scan_obj] 18 | } 19 | } -------------------------------------------------------------------------------- /out/tcl/stop_and_remove_scans.tcl: -------------------------------------------------------------------------------- 1 | stop_hw_sio_scan [get_hw_sio_scans *] 2 | remove_hw_sio_scan [get_hw_sio_scans *] -------------------------------------------------------------------------------- /out/tcl/swing_and_term_all.tcl: -------------------------------------------------------------------------------- 1 | # Rxterm 563 and txswing 660 for every link. The onboard links termination will not be affected because the termination is floating 2 | set_property TXDIFFSWING {933 mV (11111)} [get_hw_sio_txs *] 3 | set_property TXPOST {4.08 dB (01111)} [get_hw_sio_txs *] 4 | commit_hw_sio [get_hw_sio_txs *] 5 | set_property RXTERM {1100 mV} [get_hw_sio_rxs *] 6 | #set_property RXTERM {550 mV} [get_hw_sio_rxs *] 7 | commit_hw_sio [get_hw_sio_rxs *] 8 | # Fixing TTC tx 9 | set_property TXDIFFSWING {669 mV (10000)} [get_hw_sio_txs localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_40/IBERT/Quad_124/MGT_X0Y0/TX] 10 | commit_hw_sio [get_hw_sio_txs localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_40/IBERT/Quad_124/MGT_X0Y0/TX] 11 | set_property RXTERM {550 mV} [get_hw_sio_rxs localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_40/IBERT/Quad_124/MGT_X0Y0/RX] 12 | commit_hw_sio [get_hw_sio_rxs localhost:3121/xilinx_tcf/Xilinx/192.168.1.10:2542/2_1_0_40/IBERT/Quad_124/MGT_X0Y0/RX] 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /out/tcl/trp_set_polarity.tcl: -------------------------------------------------------------------------------- 1 | # pin_name: MGTHRXP3_231 | net_name: A2T_GT_N<0> 2 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_231/MGT_X0Y31] 3 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_231/MGT_X0Y31] 4 | # pin_name: MGTHRXP2_231 | net_name: A2T_GT_N<1> 5 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_231/MGT_X0Y30] 6 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_231/MGT_X0Y30] 7 | # pin_name: MGTHRXP1_231 | net_name: A2T_GT_N<2> 8 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_231/MGT_X0Y29] 9 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_231/MGT_X0Y29] 10 | # pin_name: MGTHRXP0_231 | net_name: A2T_GT_N<3> 11 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_231/MGT_X0Y28] 12 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_231/MGT_X0Y28] 13 | # pin_name: MGTHRXP3_230 | net_name: A2T_GT_N<4> 14 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y27] 15 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y27] 16 | # pin_name: MGTHRXP2_230 | net_name: A2T_GT_N<5> 17 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y26] 18 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y26] 19 | # pin_name: MGTHRXP1_230 | net_name: A2T_GT_N<6> 20 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y25] 21 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y25] 22 | # pin_name: MGTHRXP0_230 | net_name: A2T_GT_N<7> 23 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y24] 24 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_230/MGT_X0Y24] 25 | # pin_name: MGTHRXP3_229 | net_name: A2T_GT_N<8> 26 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y23] 27 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y23] 28 | # pin_name: MGTHRXP2_229 | net_name: A2T_GT_N<9> 29 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y22] 30 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y22] 31 | # pin_name: MGTHRXP1_229 | net_name: A2T_GT_N<10> 32 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y21] 33 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y21] 34 | # pin_name: MGTHRXP0_229 | net_name: A2T_GT_N<11> 35 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y20] 36 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_229/MGT_X0Y20] 37 | # pin_name: MGTHRXP3_228 | net_name: A2T_GT_N<12> 38 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_228/MGT_X0Y19] 39 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_228/MGT_X0Y19] 40 | # pin_name: MGTHRXP2_228 | net_name: A2T_GT_N<13> 41 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_228/MGT_X0Y18] 42 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_228/MGT_X0Y18] 43 | # pin_name: MGTYRXP0_125 | net_name: C2T_GT_N<0> 44 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_125/MGT_X0Y4] 45 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_125/MGT_X0Y4] 46 | # pin_name: MGTYRXP1_125 | net_name: C2T_GT_N<1> 47 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_125/MGT_X0Y5] 48 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_125/MGT_X0Y5] 49 | # pin_name: MGTYRXP2_125 | net_name: C2T_GT_N<2> 50 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_125/MGT_X0Y6] 51 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_125/MGT_X0Y6] 52 | # pin_name: MGTYRXP3_125 | net_name: C2T_GT_N<3> 53 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_125/MGT_X0Y7] 54 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_125/MGT_X0Y7] 55 | # pin_name: MGTYRXP0_126 | net_name: C2T_GT_N<4> 56 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_126/MGT_X0Y8] 57 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_126/MGT_X0Y8] 58 | # pin_name: MGTYRXP1_126 | net_name: C2T_GT_N<5> 59 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_126/MGT_X0Y9] 60 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_126/MGT_X0Y9] 61 | # pin_name: MGTYRXP2_126 | net_name: C2T_GT_N<6> 62 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_126/MGT_X0Y10] 63 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_126/MGT_X0Y10] 64 | # pin_name: MGTYRXP3_126 | net_name: C2T_GT_N<7> 65 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_126/MGT_X0Y11] 66 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_126/MGT_X0Y11] 67 | # pin_name: MGTYRXP0_127 | net_name: C2T_GT_N<8> 68 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_127/MGT_X0Y12] 69 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_127/MGT_X0Y12] 70 | # pin_name: MGTYRXP1_127 | net_name: C2T_GT_N<9> 71 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_127/MGT_X0Y13] 72 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_127/MGT_X0Y13] 73 | # pin_name: MGTYRXP2_127 | net_name: C2T_GT_N<10> 74 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_127/MGT_X0Y14] 75 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_127/MGT_X0Y14] 76 | # pin_name: MGTYRXP3_127 | net_name: C2T_GT_N<11> 77 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_127/MGT_X0Y15] 78 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_127/MGT_X0Y15] 79 | # pin_name: MGTYRXP0_128 | net_name: C2T_GT_N<12> 80 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_128/MGT_X0Y16] 81 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_128/MGT_X0Y16] 82 | # pin_name: MGTYRXP1_128 | net_name: C2T_GT_N<13> 83 | set_property PORT.RXPOLARITY 1 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_128/MGT_X0Y17] 84 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_128/MGT_X0Y17] 85 | -------------------------------------------------------------------------------- /out/tcl/z2t_float_rxterm.tcl: -------------------------------------------------------------------------------- 1 | set_property DRP.RX_CM_SEL 2 [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_124/MGT_X0Y3] 2 | commit_hw_sio [get_hw_sio_gts localhost:3121/xilinx_tcf/*/2_1_0_*/IBERT/Quad_124/MGT_X0Y3] 3 | -------------------------------------------------------------------------------- /out/tex/TRP_J1_QSFP_Loopback_6.4-optimized.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{TRP J1 QSFP Loopback}\label{sec:TRPJ1QSFPLoopback6.4-optimized} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{0.5\textwidth} 17 | \hyperref[sec:TRPFPGAJ100J100TRPFPGA6.4-optimized]{\includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J1-00--J1-00-TRP_FPGA.pdf}} 18 | \end{subfigure}\hspace*{\fill} 19 | \begin{subfigure}{0.5\textwidth} 20 | \hyperref[sec:TRPFPGAJ101J101TRPFPGA6.4-optimized]{\includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J1-01--J1-01-TRP_FPGA.pdf}} 21 | \end{subfigure} 22 | 23 | \begin{subfigure}{0.5\textwidth} 24 | \hyperref[sec:TRPFPGAJ102J102TRPFPGA6.4-optimized]{\includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J1-02--J1-02-TRP_FPGA.pdf}} 25 | \end{subfigure}\hspace*{\fill} 26 | \begin{subfigure}{0.5\textwidth} 27 | \hyperref[sec:TRPFPGAJ103J103TRPFPGA6.4-optimized]{\includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J1-03--J1-03-TRP_FPGA.pdf}} 28 | \end{subfigure} 29 | 30 | \caption{TRP J1 QSFP Loopback} \label{fig:TRPJ1QSFPLoopback6.4-optimized} 31 | \end{figure} 32 | 33 | A cross-reference to Figure~\ref{fig:TRPJ1QSFPLoopback6.4-optimized}. 34 | Sibling eye diagrams: \hyperref[sec:TRPJ1QSFPLoopback9.6-optimized]{9.6-optimized}, \hyperref[sec:TRPJ1QSFPLoopback12.8-optimized]{12.8-optimized}. \\ 35 | Next summary Figure~\ref{fig:TRPJ3SFPLoopback6.4-optimized}. 36 | \clearpage 37 | % \end{document} 38 | \subsection{TRP\_FPGA-J1-00--J1-00-TRP\_FPGA}\label{sec:TRPFPGAJ100J100TRPFPGA6.4-optimized} 39 | 40 | % Please add the following required packages to your document preamble: 41 | % \usepackage{booktabs} 42 | \begin{table}[h] 43 | \centering 44 | \caption{TRP\_FPGA-J1-00--J1-00-TRP\_FPGA} 45 | \label{tab:TRPFPGAJ100J100TRPFPGA6.4-optimized} 46 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 47 | \toprule 48 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 49 | 2017.2 & UltraScale GTH & \multicolumn{2}{l|}{2018-Jan-24 04:01:43} & \multicolumn{2}{l|}{2018-Jan-24 04:02:52} \\ \midrule 50 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 51 | true & 24091 & 109 & 84.50\% & 255 & 100.00\% \\ \midrule 52 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 53 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0xC002 SVN: 0} \\ \bottomrule 54 | \end{tabular} 55 | \end{table} 56 | 57 | \begin{figure}[h] 58 | \includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J1-00--J1-00-TRP_FPGA.pdf} 59 | \caption{TRP\_FPGA-J1-00--J1-00-TRP\_FPGA} \label{fig:TRPFPGAJ100J100TRPFPGA6.4-optimized} 60 | \end{figure} 61 | 62 | Call back to summary Figure~\ref{fig:TRPJ1QSFPLoopback6.4-optimized}. 63 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ100J100TRPFPGA9.6-optimized]{9.6-optimized}, \hyperref[sec:TRPFPGAJ100J100TRPFPGA12.8-optimized]{12.8-optimized}. 64 | 65 | \clearpage 66 | \newpage 67 | 68 | 69 | \subsection{TRP\_FPGA-J1-01--J1-01-TRP\_FPGA}\label{sec:TRPFPGAJ101J101TRPFPGA6.4-optimized} 70 | 71 | % Please add the following required packages to your document preamble: 72 | % \usepackage{booktabs} 73 | \begin{table}[h] 74 | \centering 75 | \caption{TRP\_FPGA-J1-01--J1-01-TRP\_FPGA} 76 | \label{tab:TRPFPGAJ101J101TRPFPGA6.4-optimized} 77 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 78 | \toprule 79 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 80 | 2017.2 & UltraScale GTH & \multicolumn{2}{l|}{2018-Jan-24 04:02:52} & \multicolumn{2}{l|}{2018-Jan-24 04:04:00} \\ \midrule 81 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 82 | true & 23169 & 108 & 83.72\% & 255 & 100.00\% \\ \midrule 83 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 84 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0xC002 SVN: 0} \\ \bottomrule 85 | \end{tabular} 86 | \end{table} 87 | 88 | \begin{figure}[h] 89 | \includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J1-01--J1-01-TRP_FPGA.pdf} 90 | \caption{TRP\_FPGA-J1-01--J1-01-TRP\_FPGA} \label{fig:TRPFPGAJ101J101TRPFPGA6.4-optimized} 91 | \end{figure} 92 | 93 | Call back to summary Figure~\ref{fig:TRPJ1QSFPLoopback6.4-optimized}. 94 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ101J101TRPFPGA9.6-optimized]{9.6-optimized}, \hyperref[sec:TRPFPGAJ101J101TRPFPGA12.8-optimized]{12.8-optimized}. 95 | 96 | \clearpage 97 | \newpage 98 | 99 | 100 | \subsection{TRP\_FPGA-J1-02--J1-02-TRP\_FPGA}\label{sec:TRPFPGAJ102J102TRPFPGA6.4-optimized} 101 | 102 | % Please add the following required packages to your document preamble: 103 | % \usepackage{booktabs} 104 | \begin{table}[h] 105 | \centering 106 | \caption{TRP\_FPGA-J1-02--J1-02-TRP\_FPGA} 107 | \label{tab:TRPFPGAJ102J102TRPFPGA6.4-optimized} 108 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 109 | \toprule 110 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 111 | 2017.2 & UltraScale GTH & \multicolumn{2}{l|}{2018-Jan-24 04:04:00} & \multicolumn{2}{l|}{2018-Jan-24 04:05:09} \\ \midrule 112 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 113 | true & 23460 & 109 & 84.50\% & 255 & 100.00\% \\ \midrule 114 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 115 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0xC002 SVN: 0} \\ \bottomrule 116 | \end{tabular} 117 | \end{table} 118 | 119 | \begin{figure}[h] 120 | \includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J1-02--J1-02-TRP_FPGA.pdf} 121 | \caption{TRP\_FPGA-J1-02--J1-02-TRP\_FPGA} \label{fig:TRPFPGAJ102J102TRPFPGA6.4-optimized} 122 | \end{figure} 123 | 124 | Call back to summary Figure~\ref{fig:TRPJ1QSFPLoopback6.4-optimized}. 125 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ102J102TRPFPGA9.6-optimized]{9.6-optimized}, \hyperref[sec:TRPFPGAJ102J102TRPFPGA12.8-optimized]{12.8-optimized}. 126 | 127 | \clearpage 128 | \newpage 129 | 130 | 131 | \subsection{TRP\_FPGA-J1-03--J1-03-TRP\_FPGA}\label{sec:TRPFPGAJ103J103TRPFPGA6.4-optimized} 132 | 133 | % Please add the following required packages to your document preamble: 134 | % \usepackage{booktabs} 135 | \begin{table}[h] 136 | \centering 137 | \caption{TRP\_FPGA-J1-03--J1-03-TRP\_FPGA} 138 | \label{tab:TRPFPGAJ103J103TRPFPGA6.4-optimized} 139 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 140 | \toprule 141 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 142 | 2017.2 & UltraScale GTH & \multicolumn{2}{l|}{2018-Jan-24 04:05:09} & \multicolumn{2}{l|}{2018-Jan-24 04:06:18} \\ \midrule 143 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 144 | true & 23051 & 108 & 83.72\% & 255 & 100.00\% \\ \midrule 145 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 146 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0xC002 SVN: 0} \\ \bottomrule 147 | \end{tabular} 148 | \end{table} 149 | 150 | \begin{figure}[h] 151 | \includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J1-03--J1-03-TRP_FPGA.pdf} 152 | \caption{TRP\_FPGA-J1-03--J1-03-TRP\_FPGA} \label{fig:TRPFPGAJ103J103TRPFPGA6.4-optimized} 153 | \end{figure} 154 | 155 | Call back to summary Figure~\ref{fig:TRPJ1QSFPLoopback6.4-optimized}. 156 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ103J103TRPFPGA9.6-optimized]{9.6-optimized}, \hyperref[sec:TRPFPGAJ103J103TRPFPGA12.8-optimized]{12.8-optimized}. 157 | 158 | \clearpage 159 | \newpage 160 | 161 | -------------------------------------------------------------------------------- /out/tex/TRP_J1_QSFP_Loopback_9.6-optimized.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{TRP J1 QSFP Loopback}\label{sec:TRPJ1QSFPLoopback9.6-optimized} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{0.5\textwidth} 17 | \hyperref[sec:TRPFPGAJ100J100TRPFPGA9.6-optimized]{\includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J1-00--J1-00-TRP_FPGA.pdf}} 18 | \end{subfigure}\hspace*{\fill} 19 | \begin{subfigure}{0.5\textwidth} 20 | \hyperref[sec:TRPFPGAJ101J101TRPFPGA9.6-optimized]{\includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J1-01--J1-01-TRP_FPGA.pdf}} 21 | \end{subfigure} 22 | 23 | \begin{subfigure}{0.5\textwidth} 24 | \hyperref[sec:TRPFPGAJ102J102TRPFPGA9.6-optimized]{\includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J1-02--J1-02-TRP_FPGA.pdf}} 25 | \end{subfigure}\hspace*{\fill} 26 | \begin{subfigure}{0.5\textwidth} 27 | \hyperref[sec:TRPFPGAJ103J103TRPFPGA9.6-optimized]{\includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J1-03--J1-03-TRP_FPGA.pdf}} 28 | \end{subfigure} 29 | 30 | \caption{TRP J1 QSFP Loopback} \label{fig:TRPJ1QSFPLoopback9.6-optimized} 31 | \end{figure} 32 | 33 | A cross-reference to Figure~\ref{fig:TRPJ1QSFPLoopback9.6-optimized}. 34 | Sibling eye diagrams: \hyperref[sec:TRPJ1QSFPLoopback6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPJ1QSFPLoopback12.8-optimized]{12.8-optimized}. \\ 35 | Next summary Figure~\ref{fig:TRPJ3SFPLoopback9.6-optimized}. 36 | \clearpage 37 | % \end{document} 38 | \subsection{TRP\_FPGA-J1-00--J1-00-TRP\_FPGA}\label{sec:TRPFPGAJ100J100TRPFPGA9.6-optimized} 39 | 40 | % Please add the following required packages to your document preamble: 41 | % \usepackage{booktabs} 42 | \begin{table}[h] 43 | \centering 44 | \caption{TRP\_FPGA-J1-00--J1-00-TRP\_FPGA} 45 | \label{tab:TRPFPGAJ100J100TRPFPGA9.6-optimized} 46 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 47 | \toprule 48 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 49 | 2017.2 & UltraScale GTH & \multicolumn{2}{l|}{2018-Jan-24 19:38:15} & \multicolumn{2}{l|}{2018-Jan-24 19:38:42} \\ \midrule 50 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 51 | true & 8833 & 49 & 75.38\% & 255 & 100.00\% \\ \midrule 52 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 53 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0xC002 SVN: 0} \\ \bottomrule 54 | \end{tabular} 55 | \end{table} 56 | 57 | \begin{figure}[h] 58 | \includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J1-00--J1-00-TRP_FPGA.pdf} 59 | \caption{TRP\_FPGA-J1-00--J1-00-TRP\_FPGA} \label{fig:TRPFPGAJ100J100TRPFPGA9.6-optimized} 60 | \end{figure} 61 | 62 | Call back to summary Figure~\ref{fig:TRPJ1QSFPLoopback9.6-optimized}. 63 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ100J100TRPFPGA6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPFPGAJ100J100TRPFPGA12.8-optimized]{12.8-optimized}. 64 | 65 | \clearpage 66 | \newpage 67 | 68 | 69 | \subsection{TRP\_FPGA-J1-01--J1-01-TRP\_FPGA}\label{sec:TRPFPGAJ101J101TRPFPGA9.6-optimized} 70 | 71 | % Please add the following required packages to your document preamble: 72 | % \usepackage{booktabs} 73 | \begin{table}[h] 74 | \centering 75 | \caption{TRP\_FPGA-J1-01--J1-01-TRP\_FPGA} 76 | \label{tab:TRPFPGAJ101J101TRPFPGA9.6-optimized} 77 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 78 | \toprule 79 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 80 | 2017.2 & UltraScale GTH & \multicolumn{2}{l|}{2018-Jan-24 19:38:43} & \multicolumn{2}{l|}{2018-Jan-24 19:39:10} \\ \midrule 81 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 82 | true & 8780 & 49 & 75.38\% & 255 & 100.00\% \\ \midrule 83 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 84 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0xC002 SVN: 0} \\ \bottomrule 85 | \end{tabular} 86 | \end{table} 87 | 88 | \begin{figure}[h] 89 | \includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J1-01--J1-01-TRP_FPGA.pdf} 90 | \caption{TRP\_FPGA-J1-01--J1-01-TRP\_FPGA} \label{fig:TRPFPGAJ101J101TRPFPGA9.6-optimized} 91 | \end{figure} 92 | 93 | Call back to summary Figure~\ref{fig:TRPJ1QSFPLoopback9.6-optimized}. 94 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ101J101TRPFPGA6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPFPGAJ101J101TRPFPGA12.8-optimized]{12.8-optimized}. 95 | 96 | \clearpage 97 | \newpage 98 | 99 | 100 | \subsection{TRP\_FPGA-J1-02--J1-02-TRP\_FPGA}\label{sec:TRPFPGAJ102J102TRPFPGA9.6-optimized} 101 | 102 | % Please add the following required packages to your document preamble: 103 | % \usepackage{booktabs} 104 | \begin{table}[h] 105 | \centering 106 | \caption{TRP\_FPGA-J1-02--J1-02-TRP\_FPGA} 107 | \label{tab:TRPFPGAJ102J102TRPFPGA9.6-optimized} 108 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 109 | \toprule 110 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 111 | 2017.2 & UltraScale GTH & \multicolumn{2}{l|}{2018-Jan-24 19:39:11} & \multicolumn{2}{l|}{2018-Jan-24 19:39:39} \\ \midrule 112 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 113 | true & 9207 & 47 & 72.31\% & 255 & 100.00\% \\ \midrule 114 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 115 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0xC002 SVN: 0} \\ \bottomrule 116 | \end{tabular} 117 | \end{table} 118 | 119 | \begin{figure}[h] 120 | \includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J1-02--J1-02-TRP_FPGA.pdf} 121 | \caption{TRP\_FPGA-J1-02--J1-02-TRP\_FPGA} \label{fig:TRPFPGAJ102J102TRPFPGA9.6-optimized} 122 | \end{figure} 123 | 124 | Call back to summary Figure~\ref{fig:TRPJ1QSFPLoopback9.6-optimized}. 125 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ102J102TRPFPGA6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPFPGAJ102J102TRPFPGA12.8-optimized]{12.8-optimized}. 126 | 127 | \clearpage 128 | \newpage 129 | 130 | 131 | \subsection{TRP\_FPGA-J1-03--J1-03-TRP\_FPGA}\label{sec:TRPFPGAJ103J103TRPFPGA9.6-optimized} 132 | 133 | % Please add the following required packages to your document preamble: 134 | % \usepackage{booktabs} 135 | \begin{table}[h] 136 | \centering 137 | \caption{TRP\_FPGA-J1-03--J1-03-TRP\_FPGA} 138 | \label{tab:TRPFPGAJ103J103TRPFPGA9.6-optimized} 139 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 140 | \toprule 141 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 142 | 2017.2 & UltraScale GTH & \multicolumn{2}{l|}{2018-Jan-24 19:39:39} & \multicolumn{2}{l|}{2018-Jan-24 19:40:06} \\ \midrule 143 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 144 | true & 8577 & 47 & 72.31\% & 255 & 100.00\% \\ \midrule 145 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 146 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0xC002 SVN: 0} \\ \bottomrule 147 | \end{tabular} 148 | \end{table} 149 | 150 | \begin{figure}[h] 151 | \includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J1-03--J1-03-TRP_FPGA.pdf} 152 | \caption{TRP\_FPGA-J1-03--J1-03-TRP\_FPGA} \label{fig:TRPFPGAJ103J103TRPFPGA9.6-optimized} 153 | \end{figure} 154 | 155 | Call back to summary Figure~\ref{fig:TRPJ1QSFPLoopback9.6-optimized}. 156 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ103J103TRPFPGA6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPFPGAJ103J103TRPFPGA12.8-optimized]{12.8-optimized}. 157 | 158 | \clearpage 159 | \newpage 160 | 161 | -------------------------------------------------------------------------------- /out/tex/TRP_J3_SFP_Loopback_12.8-optimized.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{TRP J3 SFP Loopback}\label{sec:TRPJ3SFPLoopback12.8-optimized} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{1\textwidth} 17 | \hyperref[sec:TRPFPGAJ300J300TRPFPGA12.8-optimized]{\includegraphicsmaybe{../scans/pdf/12.8-optimized/TRP_FPGA-J3-00--J3-00-TRP_FPGA.pdf}} 18 | \end{subfigure} 19 | 20 | \caption{TRP J3 SFP Loopback} \label{fig:TRPJ3SFPLoopback12.8-optimized} 21 | \end{figure} 22 | 23 | A cross-reference to Figure~\ref{fig:TRPJ3SFPLoopback12.8-optimized}. 24 | Sibling eye diagrams: \hyperref[sec:TRPJ3SFPLoopback6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPJ3SFPLoopback9.6-optimized]{9.6-optimized}. \\ 25 | Next summary Figure~\ref{fig:MSPATRPOnboardlinks12.8-optimized}. 26 | \clearpage 27 | % \end{document} 28 | \subsection{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA}\label{sec:TRPFPGAJ300J300TRPFPGA12.8-optimized} 29 | 30 | % Please add the following required packages to your document preamble: 31 | % \usepackage{booktabs} 32 | \begin{table}[h] 33 | \centering 34 | \caption{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA} 35 | \label{tab:TRPFPGAJ300J300TRPFPGA12.8-optimized} 36 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 37 | \toprule 38 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 39 | 2017.2 & UltraScale GTY & \multicolumn{2}{l|}{2018-Jan-23 23:50:00} & \multicolumn{2}{l|}{2018-Jan-23 23:50:20} \\ \midrule 40 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 41 | true & 6766 & 36 & 55.38\% & 255 & 99.61\% \\ \midrule 42 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 43 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0x4002 SVN: 0} \\ \bottomrule 44 | \end{tabular} 45 | \end{table} 46 | 47 | \begin{figure}[h] 48 | \includegraphicsmaybe{../scans/pdf/12.8-optimized/TRP_FPGA-J3-00--J3-00-TRP_FPGA.pdf} 49 | \caption{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA} \label{fig:TRPFPGAJ300J300TRPFPGA12.8-optimized} 50 | \end{figure} 51 | 52 | Call back to summary Figure~\ref{fig:TRPJ3SFPLoopback12.8-optimized}. 53 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ300J300TRPFPGA6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPFPGAJ300J300TRPFPGA9.6-optimized]{9.6-optimized}. 54 | 55 | \clearpage 56 | \newpage 57 | 58 | -------------------------------------------------------------------------------- /out/tex/TRP_J3_SFP_Loopback_6.4-optimized.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{TRP J3 SFP Loopback}\label{sec:TRPJ3SFPLoopback6.4-optimized} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{1\textwidth} 17 | \hyperref[sec:TRPFPGAJ300J300TRPFPGA6.4-optimized]{\includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J3-00--J3-00-TRP_FPGA.pdf}} 18 | \end{subfigure} 19 | 20 | \caption{TRP J3 SFP Loopback} \label{fig:TRPJ3SFPLoopback6.4-optimized} 21 | \end{figure} 22 | 23 | A cross-reference to Figure~\ref{fig:TRPJ3SFPLoopback6.4-optimized}. 24 | Sibling eye diagrams: \hyperref[sec:TRPJ3SFPLoopback9.6-optimized]{9.6-optimized}, \hyperref[sec:TRPJ3SFPLoopback12.8-optimized]{12.8-optimized}. \\ 25 | Next summary Figure~\ref{fig:MSPATRPOnboardlinks6.4-optimized}. 26 | \clearpage 27 | % \end{document} 28 | \subsection{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA}\label{sec:TRPFPGAJ300J300TRPFPGA6.4-optimized} 29 | 30 | % Please add the following required packages to your document preamble: 31 | % \usepackage{booktabs} 32 | \begin{table}[h] 33 | \centering 34 | \caption{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA} 35 | \label{tab:TRPFPGAJ300J300TRPFPGA6.4-optimized} 36 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 37 | \toprule 38 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 39 | 2017.2 & UltraScale GTY & \multicolumn{2}{l|}{2018-Jan-24 04:06:19} & \multicolumn{2}{l|}{2018-Jan-24 04:06:55} \\ \midrule 40 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 41 | true & 9895 & 45 & 69.23\% & 255 & 100.00\% \\ \midrule 42 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 43 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0x4002 SVN: 0} \\ \bottomrule 44 | \end{tabular} 45 | \end{table} 46 | 47 | \begin{figure}[h] 48 | \includegraphicsmaybe{../scans/pdf/6.4-optimized/TRP_FPGA-J3-00--J3-00-TRP_FPGA.pdf} 49 | \caption{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA} \label{fig:TRPFPGAJ300J300TRPFPGA6.4-optimized} 50 | \end{figure} 51 | 52 | Call back to summary Figure~\ref{fig:TRPJ3SFPLoopback6.4-optimized}. 53 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ300J300TRPFPGA9.6-optimized]{9.6-optimized}, \hyperref[sec:TRPFPGAJ300J300TRPFPGA12.8-optimized]{12.8-optimized}. 54 | 55 | \clearpage 56 | \newpage 57 | 58 | -------------------------------------------------------------------------------- /out/tex/TRP_J3_SFP_Loopback_9.6-optimized.tex: -------------------------------------------------------------------------------- 1 | % \documentclass{article} 2 | % \usepackage{graphicx} 3 | % \usepackage[a4paper, margin=0.5in]{geometry} 4 | % \usepackage{subcaption} 5 | % \usepackage{printlen} 6 | % \uselengthunit{cm} 7 | 8 | % \newlength\imageheight 9 | % \newlength\imagewidth 10 | 11 | % \begin{document} 12 | 13 | \section{TRP J3 SFP Loopback}\label{sec:TRPJ3SFPLoopback9.6-optimized} 14 | 15 | \begin{figure}[h] % "[t!]" placement specifier just for this example 16 | \begin{subfigure}{1\textwidth} 17 | \hyperref[sec:TRPFPGAJ300J300TRPFPGA9.6-optimized]{\includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J3-00--J3-00-TRP_FPGA.pdf}} 18 | \end{subfigure} 19 | 20 | \caption{TRP J3 SFP Loopback} \label{fig:TRPJ3SFPLoopback9.6-optimized} 21 | \end{figure} 22 | 23 | A cross-reference to Figure~\ref{fig:TRPJ3SFPLoopback9.6-optimized}. 24 | Sibling eye diagrams: \hyperref[sec:TRPJ3SFPLoopback6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPJ3SFPLoopback12.8-optimized]{12.8-optimized}. \\ 25 | Next summary Figure~\ref{fig:MSPATRPOnboardlinks9.6-optimized}. 26 | \clearpage 27 | % \end{document} 28 | \subsection{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA}\label{sec:TRPFPGAJ300J300TRPFPGA9.6-optimized} 29 | 30 | % Please add the following required packages to your document preamble: 31 | % \usepackage{booktabs} 32 | \begin{table}[h] 33 | \centering 34 | \caption{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA} 35 | \label{tab:TRPFPGAJ300J300TRPFPGA9.6-optimized} 36 | \begin{tabular}{@{}|l|l|l|l|l|l|@{}} 37 | \toprule 38 | \textbf{SW Version} & \textbf{GT Type} & \multicolumn{2}{l|}{\textbf{Date and Time Started}} & \multicolumn{2}{l|}{\textbf{Date and Time Ended}} \\ \midrule 39 | 2017.2 & UltraScale GTY & \multicolumn{2}{l|}{2018-Jan-24 19:40:06} & \multicolumn{2}{l|}{2018-Jan-24 19:40:36} \\ \midrule 40 | \textbf{Reset RX} & \textbf{OA} & \textbf{HO} & \textbf{HO (\%)} & \textbf{VO} & \textbf{VO (\%)} \\ \midrule 41 | true & 9224 & 43 & 66.15\% & 255 & 100.00\% \\ \midrule 42 | \textbf{Dwell Type} & \textbf{Dwell BER} & \textbf{Horizontal Increment} & \textbf{Vertical Increment} & \multicolumn{2}{l|}{\textbf{Misc Info}} \\ \midrule 43 | BER & 1e-7 & 1 & 1 & \multicolumn{2}{l|}{ELF Version: 0x4002 SVN: 0} \\ \bottomrule 44 | \end{tabular} 45 | \end{table} 46 | 47 | \begin{figure}[h] 48 | \includegraphicsmaybe{../scans/pdf/9.6-optimized/TRP_FPGA-J3-00--J3-00-TRP_FPGA.pdf} 49 | \caption{TRP\_FPGA-J3-00--J3-00-TRP\_FPGA} \label{fig:TRPFPGAJ300J300TRPFPGA9.6-optimized} 50 | \end{figure} 51 | 52 | Call back to summary Figure~\ref{fig:TRPJ3SFPLoopback9.6-optimized}. 53 | Sibling eye diagrams: \hyperref[sec:TRPFPGAJ300J300TRPFPGA6.4-optimized]{6.4-optimized}, \hyperref[sec:TRPFPGAJ300J300TRPFPGA12.8-optimized]{12.8-optimized}. 54 | 55 | \clearpage 56 | \newpage 57 | 58 | -------------------------------------------------------------------------------- /python/copy_mdate.py: -------------------------------------------------------------------------------- 1 | import glob 2 | import os 3 | import csv 4 | from stat import * 5 | import time 6 | from calendar import timegm 7 | 8 | rate_i = 'V2-opt-6.4' 9 | rate_o = 'V2-opt2-6.4' 10 | link_set = '*' 11 | 12 | filename_i_list = filter(os.path.isfile, glob.glob('..\scans\csv\*{0:s}\\{1:s}'.format(rate_i, link_set))) 13 | 14 | for i in filename_i_list: 15 | st = os.stat(i) 16 | print i 17 | o = i.replace(rate_i,rate_o) 18 | print o 19 | print st[ST_MTIME] 20 | os.utime(o, (st[ST_ATIME], st[ST_MTIME])) 21 | 22 | -------------------------------------------------------------------------------- /python/eyescan_plot.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | """ 3 | Created on Fri Jul 21 12:29:54 2017 4 | 5 | @author: msilvaol 6 | """ 7 | 8 | import matplotlib.pyplot as plt 9 | import matplotlib.ticker as ticker 10 | import numpy as np 11 | import csv 12 | import operator as op 13 | from matplotlib.colors import ListedColormap 14 | import matplotlib.pylab as pl 15 | import matplotlib as mpl 16 | 17 | 18 | def get_mb(two_points): 19 | m = np.true_divide(*reversed([np.subtract(*s) for s in zip(*two_points)])) 20 | b = two_points[0][1] - m * two_points[0][0] 21 | return [m,b] 22 | 23 | def gen_mask(size,two_points,operator, mask=[]): 24 | [m, b] = get_mb(two_points) 25 | if mask ==[]: 26 | mask = np.ones(list(reversed(size)), dtype=bool) 27 | for (y,x), value in np.ndenumerate(mask): 28 | mask[y][x] &= operator(y,m*x+b) 29 | return mask 30 | 31 | def plot_mask(mask): 32 | plt.figure(num=None, figsize=(10, 7), dpi=80, facecolor='w', edgecolor='k') 33 | plt.imshow(mask, interpolation='none', vmin=0, vmax=1, aspect='auto', alpha=1) 34 | plt.show() 35 | 36 | def gen_hexagon_mask(size,x1n,x2n,y1n): 37 | xm = size[0] 38 | ym = size[1] 39 | x1 = int(round(x1n*xm)) 40 | x2 = int(round(x2n*xm)) 41 | y1 = int(round(y1n*ym)) 42 | yhalf = int(round(0.5*ym)) 43 | points = [[x1,yhalf],[x2,ym-y1],[xm-x2,ym-y1],[xm-x1,yhalf],[xm-x2,y1],[x2,y1]] 44 | pairs = zip(points,points[1:]+[points[0]]) 45 | ops = [op.lt, op.lt, op.lt, op.gt, op.gt, op.gt] 46 | mask = [] 47 | for (p,o) in zip(pairs,ops): 48 | mask = gen_mask(size,p,o,mask) 49 | #plot_mask(mask) 50 | return mask 51 | 52 | def gen_decagon_mask(size, x1n, x2n, x3n, y1n, y2n): 53 | xm = size[0] 54 | ym = size[1] 55 | x1 = int(round(x1n * xm)) 56 | x2 = int(round(x2n * xm)) 57 | x3 = int(round(x3n * xm)) 58 | y1 = int(round(y1n * ym)) 59 | y2 = int(round(y2n * ym)) 60 | yhalf = int(round(0.5 * ym)) 61 | points = [[x1, yhalf], [x2, ym - y2], [x3, ym - y1], [xm - x3, ym - y1], [xm - x2, ym - y2], [xm - x1, yhalf], [xm - x2, y2], [xm - x3, y1], [x3, y1], [x2, y2]] 62 | pairs = zip(points, points[1:] + [points[0]]) 63 | ops = [op.lt, op.lt, op.lt, op.lt, op.lt, op.gt, op.gt, op.gt, op.gt, op.gt] 64 | mask = [] 65 | for (p, o) in zip(pairs, ops): 66 | mask = gen_mask(size, p, o, mask) 67 | # plot_mask(mask) 68 | return mask 69 | 70 | # function for getting eye data 71 | def get_eye(scan_list): 72 | eyedata = False 73 | yticks = [] 74 | img = [] 75 | for row in scan_list: 76 | if row[0].startswith('Scan End'): 77 | eyedata = False 78 | 79 | if eyedata: 80 | yticks.append(row[0]) 81 | img.append(row[1:]) 82 | 83 | if row[0].startswith('2d statistical'): 84 | xticks = row[1:] 85 | eyedata = True 86 | img = [[float(y) for y in x] for x in img] 87 | 88 | xticks = [int(x) for x in xticks] 89 | yticks = [int(y) for y in yticks] 90 | return [img, xticks, yticks] 91 | 92 | 93 | #Generate eyescan plots 94 | def eyescan_plot(filename_i, filename_o, minlog10ber, colorbar=True, xaxis=True, yaxis=True, xticks_f=[],yticks_f=[], mask_x1x2x3y1y2 = (0.25, 0.4, 0.45, 0.25, 0.28)): 95 | 96 | # opens the file 97 | with open(filename_i, 'rb') as f: 98 | reader = csv.reader(f) 99 | scan_list = list(reader) 100 | 101 | 102 | # getting eye data 103 | [img, xticks, yticks] = get_eye(scan_list) 104 | 105 | # Defining mask 106 | size = [len(xticks), len(yticks)] 107 | #mask = gen_hexagon_mask(size, 0.22, 0.375, 0.2) 108 | mask = gen_decagon_mask(size, *mask_x1x2x3y1y2) 109 | 110 | # testing Mask 111 | Passed = True 112 | for (y, x), value in np.ndenumerate(mask): 113 | if mask[y][x]: 114 | Passed &= img[y][x] < 1e-7 115 | 116 | # creating color map 117 | if Passed: 118 | color = 'green' 119 | else: 120 | color = 'red' 121 | cmap = mpl.colors.LinearSegmentedColormap.from_list('my_cmap', ['white', color], 2) 122 | my_cmap = cmap(np.arange(cmap.N)) 123 | my_cmap[:, -1] = np.linspace(0, 1, cmap.N) 124 | my_cmap = ListedColormap(my_cmap) 125 | 126 | # function for calculating x-y axis ranges in a such way that ticks is in the center of each entry 127 | def get_extent(xticks_n,yticks_r): 128 | xmin = xticks_n[0] 129 | xmax = xticks_n[-1] 130 | xstep = (xmax-xmin)/(len(xticks_n)-1) 131 | xmin_e = xmin-xstep/2 132 | xmax_e = xmax+xstep/2 133 | ymin = yticks_r[0] 134 | ymax = yticks_r[-1] 135 | ystep = (ymax-ymin)/(len(yticks_r)-1) 136 | ymin_e = ymin-ystep/2 137 | ymax_e = ymax+ystep/2 138 | return [xmin_e, xmax_e, ymin_e, ymax_e] 139 | 140 | 141 | # Generating, formating plot 142 | plt.figure(num=None, figsize=(10, 7), dpi=80, facecolor='w', edgecolor='k') 143 | xticks_n = [float(x)/(2*xticks[-1]) for x in xticks] 144 | yticks_r = [y for y in reversed(yticks)] 145 | myplot = plt.imshow(np.log10(img),interpolation='none', vmin = minlog10ber, vmax = 0, aspect='auto', extent = get_extent(xticks_n,yticks_r), cmap = 'jet') 146 | if not mask==[]: 147 | plt.imshow(mask, interpolation='none', vmin=0, vmax=1, aspect='auto', 148 | extent=get_extent(xticks_n, yticks_r), cmap=my_cmap, origin='lower', alpha=0.9) 149 | 150 | 151 | if xaxis: 152 | if not yticks: 153 | plt.xticks(xticks_n) 154 | else: 155 | plt.xticks(xticks_f) 156 | if yaxis: 157 | if not yticks: 158 | plt.yticks(yticks_r) 159 | else: 160 | plt.yticks(yticks_f) 161 | else: 162 | plt.yticks([]) 163 | 164 | # formating colorbar axis 165 | if colorbar: 166 | def fmt(x, pos): 167 | return '$10^{{{0:d}}}$'.format(x) 168 | plt.colorbar(myplot, format=ticker.FuncFormatter(fmt), ticks=range(minlog10ber,1,1)) 169 | # saving plot 170 | plt.savefig(filename_o,bbox_inches='tight') 171 | # showing plot if needed 172 | #plt.show() 173 | plt.close() -------------------------------------------------------------------------------- /python/fix_mdate.py: -------------------------------------------------------------------------------- 1 | import glob 2 | import os 3 | import csv 4 | from stat import * 5 | import time 6 | from calendar import timegm 7 | 8 | rate = '*' 9 | link_set = '*' 10 | 11 | def get_value_for_param(scan_list,param): 12 | for i in scan_list: 13 | if param in i: 14 | return i[1] 15 | 16 | def get_scan_list(i): 17 | with open(i, 'rb') as f: 18 | reader = csv.reader(f) 19 | scan_list = list(reader) 20 | return scan_list 21 | 22 | filename_i_list = filter(os.path.isfile, glob.glob('..\scans\csv\*{0:s}\\{1:s}'.format(rate, link_set))) 23 | #filename_i_list.sort(key=lambda x: os.path.getmtime(x)) 24 | 25 | for i in filename_i_list: 26 | slist = get_scan_list(i) 27 | mod_date = get_value_for_param(slist,'Date and Time Ended') 28 | utc_time = time.strptime(mod_date, "%Y-%b-%d %H:%M:%S") 29 | st = os.stat(i) 30 | print mod_date 31 | print timegm(utc_time), st[ST_MTIME] 32 | os.utime(i, (st[ST_ATIME], timegm(utc_time))) 33 | 34 | -------------------------------------------------------------------------------- /python/gen_mask.py: -------------------------------------------------------------------------------- 1 | import numpy as np 2 | import operator as op 3 | import matplotlib.pyplot as plt 4 | 5 | def get_mb(two_points): 6 | m = np.true_divide(*reversed([np.subtract(*s) for s in zip(*two_points)])) 7 | b = two_points[0][1] - m * two_points[0][0] 8 | return [m,b] 9 | 10 | def gen_mask(size,two_points,operator, mask=[]): 11 | [m, b] = get_mb(two_points) 12 | if mask ==[]: 13 | mask = np.ones(list(reversed(size)), dtype=bool) 14 | for (y,x), value in np.ndenumerate(mask): 15 | mask[y][x] &= operator(y,m*x+b) 16 | return mask 17 | 18 | def plot_mask(mask): 19 | plt.figure(num=None, figsize=(10, 7), dpi=80, facecolor='w', edgecolor='k') 20 | plt.imshow(mask, interpolation='none', vmin=0, vmax=1, aspect='auto', alpha=1) 21 | plt.show() 22 | 23 | def gen_hexagon_mask(size,x1n,x2n,y1n): 24 | xm = size[0] 25 | ym = size[1] 26 | x1 = int(round(x1n*xm)) 27 | x2 = int(round(x2n*xm)) 28 | y1 = int(round(y1n*ym)) 29 | yhalf = int(round(0.5*ym)) 30 | points = [[x1,yhalf],[x2,ym-y1],[xm-x2,ym-y1],[xm-x1,yhalf],[xm-x2,y1],[x2,y1]] 31 | pairs = zip(points,points[1:]+[points[0]]) 32 | ops = [op.lt, op.lt, op.lt, op.gt, op.gt, op.gt] 33 | mask = [] 34 | for (p,o) in zip(pairs,ops): 35 | mask = gen_mask(size,p,o,mask) 36 | plot_mask(mask) 37 | print p,o 38 | 39 | 40 | 41 | 42 | print points 43 | 44 | 45 | 46 | 47 | size = [129,255] 48 | two_points = [[1,1],[2,2]] 49 | mask = gen_mask(size,two_points,op.gt) 50 | print mask 51 | 52 | gen_hexagon_mask(size,0.2,0.35,0.2) 53 | 54 | 55 | 56 | 57 | 58 | -------------------------------------------------------------------------------- /python/generate_all_hists.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | """ 3 | Created on Fri Jul 21 16:40:12 2017 4 | 5 | @author: msilvaol 6 | """ 7 | 8 | 9 | import glob 10 | import os 11 | import numpy as np 12 | import csv 13 | 14 | import matplotlib.pyplot as plt 15 | from matplotlib.lines import Line2D 16 | from operator import itemgetter 17 | 18 | def get_all_styles(): 19 | markers = [] 20 | for m in Line2D.markers: 21 | try: 22 | if len(m) == 1 and m != ' ': 23 | markers.append(m) 24 | except TypeError: 25 | pass 26 | 27 | styles = markers + [ 28 | r'$\lambda$', 29 | r'$\bowtie$', 30 | r'$\circlearrowleft$', 31 | r'$\clubsuit$', 32 | r'$\checkmark$'] 33 | return styles 34 | 35 | styles = [u'D', 36 | u's', 37 | u'P', 38 | u'x', 39 | u'X', 40 | u'^', 41 | u'd', 42 | u'h', 43 | u'+', 44 | u'*', 45 | u'o', 46 | u'1', 47 | u'p', 48 | u'3', 49 | u'2', 50 | u'4', 51 | u'H', 52 | u'v', 53 | u'8', 54 | u'<', 55 | u'>', 56 | '$\\lambda$', 57 | '$\\bowtie$', 58 | '$\\circlearrowleft$', 59 | '$\\clubsuit$', 60 | '$\\checkmark$'] 61 | colors = ('b', 'g', 'r', 'c', 'm', 'y', 'k') 62 | 63 | 64 | 65 | def get_value_for_param(scan_list,param): 66 | for i in scan_list: 67 | if param in i: 68 | return i[1] 69 | 70 | def get_scan_list(i): 71 | with open(i, 'rb') as f: 72 | reader = csv.reader(f) 73 | scan_list = list(reader) 74 | return scan_list 75 | 76 | def get_eye(scan_list): 77 | eyedata = False 78 | yticks = [] 79 | img = [] 80 | for row in scan_list: 81 | if row[0].startswith('Scan End'): 82 | eyedata = False 83 | 84 | if eyedata: 85 | yticks.append(row[0]) 86 | img.append(row[1:]) 87 | 88 | if row[0].startswith('2d statistical'): 89 | xticks = row[1:] 90 | eyedata = True 91 | img = [[float(y) for y in x] for x in img] 92 | 93 | xticks = [int(x) for x in xticks] 94 | yticks = [int(y) for y in yticks] 95 | return [img, xticks, yticks] 96 | 97 | rates = ['V1-6.4', 'V1-12.8', 'V2-6.4', 'V2-12.8'] 98 | link_set = '*TX*' 99 | #link_set = '*' 100 | 101 | for rate in rates: 102 | 103 | print '\nRate {rate:s}\n'.format(rate=rate) 104 | 105 | plt.figure(num=None, figsize=(10, 8), dpi=80, facecolor='w', edgecolor='k') 106 | 107 | 108 | params = ['Scan Name', 'Horizontal Percentage', 'Vertical Percentage', 'Open Area'] 109 | histograms = ['Horizontal Percentage', 'Vertical Percentage', 'Open Area Percentage'] 110 | 111 | filename_i_list = filter(os.path.isfile, glob.glob('..\scans\csv\*{0:s}\\{1:s}'.format(rate,link_set))) 112 | filename_i_list.sort(key=lambda x: os.path.getmtime(x)) 113 | 114 | k=-1 115 | str = '' 116 | lname = '' 117 | vp = [] 118 | hp = [] 119 | oa = [] 120 | vph = [] 121 | hph = [] 122 | oah = [] 123 | for i in filename_i_list: 124 | slist = get_scan_list(i) 125 | [img, xticks, yticks] = get_eye(slist) 126 | #print img 127 | total_area = len(xticks)*len(yticks) 128 | str = '' 129 | for p in params: 130 | str += '{0:s} {1:s} '.format(p,get_value_for_param(slist,p)) 131 | rate = i.split('\\')[3] 132 | str += 'rate {0:s}'.format(rate) 133 | #print str 134 | name = get_value_for_param(slist,'Scan Name') 135 | name_red = '-'.join(list(itemgetter(0, 1, 4, 6)(name.split('-')))) 136 | 137 | hp.append(float(get_value_for_param(slist,'Horizontal Percentage'))) 138 | vp.append(float(get_value_for_param(slist,'Vertical Percentage'))) 139 | oa.append(100*float(get_value_for_param(slist, 'Open Area'))/total_area) 140 | print 'Name: {name:40s} | HP: {hp:6.2f} | VP: {vp:6.2f} | AP: {ap:6.2f}'.format(name=name,hp=hp[-1],vp=vp[-1],ap=oa[-1]) 141 | hph.append(hp[-1]) 142 | vph.append(vp[-1]) 143 | oah.append(oa[-1]) 144 | if lname != name_red or i == filename_i_list[-1]: 145 | if k > -1: 146 | color = colors[k % len(colors)] 147 | style = styles[k % len(styles)] 148 | plt.plot(hp[:-1],vp[:-1], linestyle='None', marker=style, color=color, markersize=10, label=lname) 149 | #print hp[:-1], vp [:-1], lname 150 | vp = [ vp[-1] ] 151 | hp = [ hp[-1] ] 152 | lname = name_red 153 | k+=1 154 | 155 | print 'Min AP: {minap:6.2f} Max AP: {maxap:6.2f} Average AP: {avap:6.2f}'.format(minap=min(oa),maxap=max(oa),avap=np.mean(oa)) 156 | plt.title('Horizontal and Vertical Opening Scatter Plot for Rate of {0:s} Gbps'.format(rate)) 157 | plt.ylabel('Vertical Opening Percentage') 158 | plt.xlabel('Horizontal Opening Percentage') 159 | 160 | plt.axis([40, 100, 40, 102]) 161 | 162 | plt.legend(bbox_to_anchor=(1.05, 1), loc=2, borderaxespad=0.) 163 | #plt.show() 164 | plt.savefig('../out/pdf/ScatterPlotRate{0:s}.pdf'.format(rate),bbox_inches='tight') 165 | plt.close() 166 | 167 | # histograms 168 | for t,d in zip(histograms,[hph,vph,oah]): 169 | plt.figure(num=None, figsize=(10, 4), dpi=80, facecolor='w', edgecolor='k') 170 | weights = np.ones_like(d)/float(len(d)) 171 | n, bins, patches = plt.hist(d, weights=weights, bins= 10, facecolor='green', alpha=0.75) 172 | plt.xlabel(t) 173 | plt.ylabel('Ratio') 174 | #plt.title('{1:s} Histogram for Rate of {0:s} Gbps'.format(rate,t)) 175 | plt.axis([20, 100, 0, 0.4]) 176 | plt.grid(True) 177 | plt.savefig('../out/pdf/{1:s}Rate{0:s}Gbps.pdf'.format(rate,t),bbox_inches='tight') 178 | plt.close() 179 | 180 | # plots 181 | for t,d in zip(histograms,[hph,vph,oah]): 182 | plt.figure(num=None, figsize=(10, 8), dpi=80, facecolor='w', edgecolor='k') 183 | plt.plot(range(0,len(d)),d, linestyle = 'None', marker = 'o') 184 | plt.xlabel('Channel') 185 | plt.ylabel(t) 186 | plt.grid(True) 187 | plt.axis([0, len(d), 0, 102]) 188 | plt.title('{1:s} Plot for Rate of {0:s} Gbps'.format(rate, t)) 189 | plt.savefig('../out/pdf/{1:s}PlotRate{0:s}Gbps.pdf'.format(rate, t), bbox_inches='tight') 190 | plt.close() 191 | 192 | 193 | 194 | 195 | #plt.plot([1,2,3], [1,2,3], 'go', label='line 1', linewidth=2) 196 | #plt.plot([1,2,3], [1,4,9], 'rs', label='line 2') 197 | #axis([0, 4, 0, 10]) 198 | #legend() 199 | #plt.show() 200 | -------------------------------------------------------------------------------- /python/generate_all_plots.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | """ 3 | Created on Fri Jul 21 16:40:12 2017 4 | 5 | @author: msilvaol 6 | """ 7 | 8 | from eyescan_plot import eyescan_plot 9 | from glob import glob 10 | import os.path 11 | import numpy as np 12 | 13 | minlog10ber = -8 14 | overwrite = True 15 | 16 | filename_i_list = glob('..\scans\csv\*\*') 17 | filename_o_list = [p.replace('csv','pdf') for p in filename_i_list] 18 | 19 | yticks = range(-127,0,16)+[0]+range(127,0,-16)[-1::-1] 20 | xticks = list(np.arange(-0.5,0.625,0.125)) 21 | k=1 22 | #if os.path.exists('..\scans\eyedata.csv'): 23 | # pass 24 | #else 25 | # eyedict 26 | 27 | for i,o in zip(filename_i_list, filename_o_list): 28 | print('Saving file {0:03d} out of {1:d}.'.format(k,len(filename_i_list))) 29 | if (not os.path.exists(o)) or overwrite: 30 | eyescan_plot(i, o, minlog10ber, colorbar=True, xaxis=True, yaxis=True, xticks_f=xticks, yticks_f=yticks, mask_x1x2x3y1y2=(0.25, 0.4, 0.45, 0.25, 0.28)) 31 | k += 1 32 | #break --------------------------------------------------------------------------------