├── .gitignore ├── work_dir ├── .gitignore ├── SRC │ ├── .gitignore │ ├── adder.sv │ ├── subtractor.sv │ ├── subtractor.vhdl │ └── tb.sv └── SIM │ ├── xsim_cfg.tcl │ ├── .gitignore │ ├── xsim_flow.sh │ └── Makefile ├── LICENSE └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /work_dir/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /work_dir/SRC/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /work_dir/SIM/xsim_cfg.tcl: -------------------------------------------------------------------------------- 1 | log_wave -recursive * 2 | run all 3 | exit 4 | -------------------------------------------------------------------------------- /work_dir/SIM/.gitignore: -------------------------------------------------------------------------------- 1 | .Xil 2 | xsim.dir 3 | *.wdb 4 | *.jou 5 | *.log 6 | *.pb 7 | -------------------------------------------------------------------------------- /work_dir/SRC/adder.sv: -------------------------------------------------------------------------------- 1 | // adder.sv 2 | // Module Description: superefficient ultraoptimized adder 3 | // Copyright Norbert Kremeris 2021 4 | // www.itsembedded.com 5 | 6 | module adder ( 7 | input logic [31:0] a, 8 | input logic [31:0] b, 9 | output logic [31:0] sum 10 | ); 11 | 12 | always_comb begin 13 | sum = a + b; 14 | end 15 | 16 | endmodule : adder 17 | -------------------------------------------------------------------------------- /work_dir/SRC/subtractor.sv: -------------------------------------------------------------------------------- 1 | // SystemVerilog basic subtractor 2 | // Copyright Norbertas Kremeris 2021 3 | // www.itsembedded.com 4 | 5 | module subtractor_systemverilog ( 6 | input logic [31:0] x, 7 | input logic [31:0] y, 8 | output logic [31:0] sub 9 | ); 10 | logic [31:0] y_comp2; 11 | always_comb begin 12 | y_comp2 = ~y + 32'b1; 13 | sub = x + y_comp2; 14 | end 15 | initial begin 16 | $display("Subtractor initial block, hell yeah!"); 17 | end 18 | endmodule : subtractor_systemverilog 19 | -------------------------------------------------------------------------------- /work_dir/SRC/subtractor.vhdl: -------------------------------------------------------------------------------- 1 | -- Basic VHDL subtractor 2 | -- Copyright Norbertas Kremeris 2021 3 | -- www.itsembedded.com 4 | 5 | library ieee; 6 | use ieee.std_logic_1164.all; 7 | use ieee.numeric_std.all; 8 | 9 | entity subtractor_vhdl is 10 | port ( 11 | x : in std_logic_vector(31 downto 0); 12 | y : in std_logic_vector(31 downto 0); 13 | sub : out std_logic_vector(31 downto 0) 14 | ); 15 | end entity subtractor_vhdl; 16 | 17 | architecture rtl of subtractor_vhdl is 18 | begin 19 | process(x, y) begin 20 | SUB <= std_logic_vector( signed(x) - signed(y) ); 21 | end process; 22 | end architecture rtl; 23 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Norbertas Kremeris 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # vivado-scripted-flow 2 | 3 | #### Tutorial series on Vivado Simulator Scripted Flow (Bash, Makefiles) 4 | * [Part I - Basic Vivado command-line tool usage](https://www.itsembedded.com/dhd/vivado_sim_1/) 5 | * [Part II - Introduction to Bash scripting with Vivado tools](https://www.itsembedded.com/dhd/vivado_sim_2/) 6 | * [Part III - Vivado Simulator flow using Makefiles](https://www.itsembedded.com/dhd/vivado_sim_3/) 7 | * Part IV - IP core and Block Design integration into scripted flow (coming soon) 8 | 9 | 10 | What you'll find in this repository: 11 | 12 | * **work_dir/SRC** <- VHDL/SystemVerilog source files 13 | * **work_dir/SRC/adder.sv** <- Example adder written in SystemVerilog 14 | * **work_dir/SRC/subtractor.sv** <- Example subtractor written in SystemVerilog 15 | * **work_dir/SRC/subtractor.vhdl** <- Example subtractor written in VHDL 16 | * **work_dir/SRC/tb.sv** Example testbench for verifying above three modules 17 | * **work_dir/SIM/** <- Directory for running simulations 18 | * **work_dir/SIM/xsim_flow.sh** <- Scripted flow using `Bash` 19 | * **work_dir/SIM/Makefile** <- Makefile for scripted flow using `make` 20 | * **work_dir/SIM/xsim_cfg.tcl** <- Configuration TCL file for Vivado Simulator to dump waves, run all and exit. 21 | 22 | -------------------------------------------------------------------------------- /work_dir/SIM/xsim_flow.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | GUI=-R 3 | if [ "$1" == "waves" ]; then 4 | GUI=--gui 5 | fi 6 | SOURCES_SV=" \ 7 | ../SRC/adder.sv \ 8 | ../SRC/subtractor.sv \ 9 | ../SRC/tb.sv \ 10 | " 11 | COMP_OPTS_SV=" \ 12 | --incr \ 13 | --relax 14 | " 15 | DEFINES_SV=" -d SUBTRACTOR_VHDL " 16 | SOURCES_VHDL=" ../SRC/subtractor.vhdl " 17 | COMP_OPTS_VHDL=" --incr --relax " 18 | 19 | echo 20 | echo "### COMPILING SYSTEMVERILOG ###" 21 | xvlog --sv $COMP_OPTS_SV $DEFINES_SV $SOURCES_SV 22 | if [ $? -ne 0 ]; then 23 | echo "### SYSTEMVERILOG COMPILATION FAILED ###" 24 | exit 10 25 | fi 26 | 27 | echo 28 | echo "### COMPILING VHDL ###" 29 | xvhdl $COMP_OPTS_VHDL $SOURCES_VHDL 30 | if [ $? -ne 0 ]; then 31 | echo "### VHDL COMPILATION FAILED ###" 32 | exit 11 33 | fi 34 | 35 | echo 36 | echo "### ELABORATING ###" 37 | xelab -debug all -top tb -snapshot adder_tb_snapshot 38 | if [ $? -ne 0 ]; then 39 | echo "### ELABORATION FAILED ###" 40 | exit 12 41 | fi 42 | 43 | echo 44 | echo "### RUNNING SIMULATION ###" 45 | xsim adder_tb_snapshot -tclbatch xsim_cfg.tcl 46 | 47 | if [ "$1" == "waves" ]; then 48 | echo 49 | echo "### OPENING WAVES ###" 50 | xsim --gui adder_tb_snapshot.wdb 51 | fi 52 | 53 | exit 0 54 | -------------------------------------------------------------------------------- /work_dir/SRC/tb.sv: -------------------------------------------------------------------------------- 1 | // Basic SystemVerilog mixed SV-VHDL testbench 2 | // Copyright Norbertas Kremeris 2021 3 | // www.itsembedded.com 4 | 5 | module tb (); 6 | logic [31:0] a, b, sum; // for the adder 7 | logic [31:0] x, y, sub; // for the subtractor 8 | 9 | adder DUT_adder(.*); //instantiate the amazing adder 10 | 11 | `ifdef SUBTRACTOR_VHDL 12 | subtractor_vhdl DUT_subtractor 13 | ( // wildcard (.*) connection not supported in XSIM for VHDL 14 | .x(x), 15 | .y(y), 16 | .sub(sub) 17 | ); 18 | `elsif SUBTRACTOR_SV 19 | subtractor_systemverilog DUT_subtractor(.*); 20 | `else 21 | $fatal(1, "Subtractor DUT not selected, please define SUBTRACTOR_VHDL or SUBTRACTOR_SV"); 22 | `endif 23 | 24 | initial begin 25 | `ifdef SUBTRACTOR_VHDL 26 | $display("$$$ TESTBENCH: Using VHDL subtractor"); 27 | `elsif SUBTRACTOR_SV 28 | $display("$$$ TESTBENCH: Using SystemVerilog subtractor"); 29 | `endif 30 | 31 | #1; 32 | a = 1; 33 | b = 2; 34 | x = 9; 35 | y = 3; 36 | #1; 37 | assert (sum == 3) else 38 | $fatal(1, "Adder failed"); 39 | assert (sub == 6) else 40 | $fatal(1, "Subtractor failed"); 41 | 42 | $display("TB passed, adder and subtractor ready to use in production"); 43 | end 44 | endmodule : tb 45 | -------------------------------------------------------------------------------- /work_dir/SIM/Makefile: -------------------------------------------------------------------------------- 1 | # Vivado Simulator Makefile based flow 2 | # Copyright Norbertas Kremeris 2021 3 | # www.itsembedded.com 4 | 5 | SOURCES_SV := \ 6 | ../SRC/adder.sv \ 7 | ../SRC/subtractor.sv \ 8 | ../SRC/tb.sv \ 9 | 10 | COMP_OPTS_SV := \ 11 | --incr \ 12 | --relax \ 13 | 14 | DEFINES_SV := 15 | SOURCES_VHDL := ../SRC/subtractor.vhdl 16 | COMP_OPTS_VHDL := --incr --relax 17 | 18 | TB_TOP := tb 19 | 20 | SUB ?= VHDL 21 | ifeq ($(SUB), VHDL) 22 | $(info Building with VHDL subtractor) 23 | DEFINES_SV := $(DEFINES_SV) -d SUBTRACTOR_VHDL 24 | else ifeq ($(SUB), SV) 25 | $(info Building with SYSTEMVERILOG subtractor) 26 | DEFINES_SV := $(DEFINES_SV) -d SUBTRACTOR_SV 27 | else 28 | $(info ) 29 | $(info BAD SUBTRACTOR TYPE) 30 | $(info Available options:) 31 | $(info make SUB=VHDL ) 32 | $(info make SUB=SV ) 33 | $(error ) 34 | endif 35 | 36 | #==== Default target - running simulation without drawing waveforms ====# 37 | .PHONY : simulate 38 | simulate : $(TB_TOP)_snapshot.wdb 39 | 40 | .PHONY : elaborate 41 | elaborate : .elab.timestamp 42 | 43 | .PHONY : compile 44 | compile : .comp_sv.timestamp .comp_v.timestamp .comp_vhdl.timestamp 45 | 46 | #==== WAVEFORM DRAWING ====# 47 | .PHONY : waves 48 | waves : $(TB_TOP)_snapshot.wdb 49 | @echo 50 | @echo "### OPENING WAVES ###" 51 | xsim --gui $(TB_TOP)_snapshot.wdb 52 | 53 | #==== SIMULATION ====# 54 | $(TB_TOP)_snapshot.wdb : .elab.timestamp 55 | @echo 56 | @echo "### RUNNING SIMULATION ###" 57 | xsim $(TB_TOP)_snapshot -tclbatch xsim_cfg.tcl 58 | 59 | #==== ELABORATION ====# 60 | .elab.timestamp : .comp_sv.timestamp .comp_v.timestamp .comp_vhdl.timestamp 61 | @echo 62 | @echo "### ELABORATING ###" 63 | xelab -debug all -top $(TB_TOP) -snapshot $(TB_TOP)_snapshot 64 | touch .elab.timestamp 65 | 66 | #==== COMPILING SYSTEMVERILOG ====# 67 | ifeq ($(SOURCES_SV),) 68 | .comp_sv.timestamp : 69 | @echo 70 | @echo "### NO SYSTEMVERILOG SOURCES GIVEN ###" 71 | @echo "### SKIPPED SYSTEMVERILOG COMPILATION ###" 72 | touch .comp_sv.timestamp 73 | else 74 | .comp_sv.timestamp : $(SOURCES_SV) .sub_$(SUB).timestamp 75 | @echo 76 | @echo "### COMPILING SYSTEMVERILOG ###" 77 | xvlog --sv $(COMP_OPTS_SV) $(DEFINES_SV) $(SOURCES_SV) 78 | touch .comp_sv.timestamp 79 | endif 80 | 81 | #==== COMPILING VERILOG ====# 82 | ifeq ($(SOURCES_V),) 83 | .comp_v.timestamp : 84 | @echo 85 | @echo "### NO VERILOG SOURCES GIVEN ###" 86 | @echo "### SKIPPED VERILOG COMPILATION ###" 87 | touch .comp_v.timestamp 88 | else 89 | .comp_v.timestamp : $(SOURCES_V) 90 | @echo 91 | @echo "### COMPILING VERILOG ###" 92 | xvlog $(COMP_OPTS_V) $(DEFINES_V) $(SOURCES_V) 93 | touch .comp_v.timestamp 94 | endif 95 | 96 | #==== COMPILING VHDL ====# 97 | ifeq ($(SOURCES_VHDL),) 98 | .comp_vhdl.timestamp : 99 | @echo 100 | @echo "### NO VHDL SOURCES GIVEN ###" 101 | @echo "### SKIPPED VHDL COMPILATION ###" 102 | touch .comp_vhdl.timestamp 103 | else 104 | .comp_vhdl.timestamp : $(SOURCES_VHDL) 105 | @echo 106 | @echo "### COMPILING VHDL ###" 107 | xvhdl $(COMP_OPTS_VHDL) $(SOURCES_VHDL) 108 | touch .comp_vhdl.timestamp 109 | endif 110 | 111 | .PHONY : clean 112 | clean : 113 | rm -rf *.jou *.log *.pb *.wdb xsim.dir 114 | rm -rf .*.timestamp 115 | 116 | #==== Subtractor type marker generation ===# 117 | .sub_$(SUB).timestamp : 118 | @rm -rf .sub_*.timestamp 119 | @touch .sub_$(SUB).timestamp 120 | --------------------------------------------------------------------------------