2 |
3 | Part G: ROM header information released on 1999-04-21
4 | ----------------------------------------------------------------------------
5 |
6 | * Mr Backup Z64 (.BIN or .Z64 files) uses a Low/High byte format
7 | (Big endian), wich is the "correct" format to read from.
8 |
9 | * Doctor V64 (.V64, .N64 or .U64 files) uses a High/Low byte format
10 | (Middle endian), so each word are byte flipped, like this:
11 | "ETTSNI G"
12 | When it should look like this:
13 | "TESTING "
14 | To solve this, rotate each word by 8 bits.
15 |
16 | ----------------------------------------------------------------------------
17 | The addresses below is only valid for ROM's in Low/High
18 | format, eg: Mr Backup Z64 ROM's. You have to byteswap Doctor
19 | V64 ROM's before you can read data that makes any sense.
20 | ----------------------------------------------------------------------------
21 | 0000h (1 byte): initial PI_BSB_DOM1_LAT_REG value (0x80)
22 | 0001h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x37)
23 | 0002h (1 byte): initial PI_BSB_DOM1_PWD_REG value (0x12)
24 | 0003h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x40)
25 | 0004h - 0007h (1 dword): ClockRate
26 | 0008h - 000Bh (1 dword): Program Counter (PC)
27 | 000Ch - 000Fh (1 dword): Release
28 | 0010h - 0013h (1 dword): CRC1
29 | 0014h - 0017h (1 dword): CRC2
30 | 0018h - 001Fh (2 dwords): Unknown (0x0000000000000000)
31 | 0020h - 0033h (20 bytes): Image name
32 | Padded with 0x00 or spaces (0x20)
33 | 0034h - 0037h (1 dword): Unknown (0x00000000)
34 | 0038h - 003Bh (1 dword): Manufacturer ID
35 | 0x0000004E = Nintendo ('N')
36 | 003Ch - 003Dh (1 word): Cartridge ID
37 | 003Eh - 003Fh (1 word): Country code
38 | 0x4400 = Germany ('D')
39 | 0x4500 = USA ('E')
40 | 0x4A00 = Japan ('J')
41 | 0x5000 = Europe ('P')
42 | 0x5500 = Australia ('U')
43 | 0040h - 0FFFh (1008 dwords): Boot code
44 |
45 |
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/n64ops/rcp.txt:
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1 | Note: This document contains some errors, please refer to n64ops#f.txt,
2 | n64ops#g.txt for information about the RSP opcodes, and n64ops#c.txt
3 | for the opcode matrix. /anarko
4 |
5 |
6 |
7 |
8 | =============================================================================
9 | RCP Technical Information - v1.0
10 | =============================================================================
11 |
12 |
13 | Overview
14 | --------
15 |
16 | This is the file which I am sure many a N64 emu programmer has been waiting
17 | for. I know I wanted it when I started but I had to compile this document
18 | myself.
19 |
20 | Please Note: This information is a compilation from many sources and it is
21 | possible that some of this may or may not be correct. However, I have
22 | endevoured to make sure that it is as accurate as possible.
23 |
24 | This document is also incomplete so I will be adding more information in
25 | future releases.
26 |
27 | So what is included in this document:
28 |
29 | * RSP Overview
30 | * RCP Opcode Encoding
31 | * RCP Vector Instruction Set
32 |
33 |
34 | RSP Overview
35 | ------------
36 |
37 | The RSP instruction set is essentially a 32-Bit subset of the MIPS R4000
38 | instruction set, with some extensions. Instructions which are not
39 | implemented include:
40 |
41 | * Any 64-bit Instruction
42 | * Mulitplies
43 | * Divides
44 | * Branch Likely
45 | * Most System Control Opcodes
46 |
47 | The RSP Vector Unit (VU) is implemented as a MIPS Coprocessor (COP2),
48 | with the machine language conforming to the MIPS Coprocessor definition.
49 | The RSP assembler uses a mnemonic syntax for each VU instruction.
50 |
51 | The RSP Registers are as follows:
52 |
53 | * 32 x 32 bit Scalar Registers (Normal MIPS set).
54 | * 32 Vector Registers, each with 8 x 16 bit entries.
55 | * No Scalar Multiplies or HI/LO registers.
56 | * 8 Vector ALUs. Each ALU appears to have a 'hidden' 32 bit accumulator
57 | and hidden flags registers.
58 |
59 | The RSP can only address it's 4K IMEM and 4K DMEM, everything else has to
60 | be done via DMA. The RCP DMA control registers are mapped to COP0
61 | registers.
62 |
63 | RSP Memory is as follows:
64 |
65 | * RSP DMEM Start 0x04000000
66 | * RSP DMEM End 0x04000FFF
67 | * RSP IMEM Start 0x04001000
68 | * RSP IMEM End 0x04001FFF
69 |
70 | The MUL/MAC instructions do 16 x 16 -> 32 and combine this with the hidden
71 | accumulator in various ways. The upshot is that it is possible to do
72 | 32 x 32 -> 32 multiplies in the following four instructions:
73 |
74 | * VMUDL
75 | * VMADM
76 | * VMADN
77 | * VMADH
78 |
79 | The COP2 control registers appear to be vector ALU flags, bit per element.
80 | (VCO, VCC, VCE)
81 |
82 | The vector opcodes are all 3 operand, and the second source can have a
83 | modifier allowing elements to be replicated in various ways:
84 |
85 | Instruction Elements of $v3 sent to ALUs
86 |
87 | vadd $v1, $v2, $v3 0 1 2 3 4 5 6 7
88 | vadd $v1, $v2, $v3[0q] 0 1 2 3 0 1 2 3
89 | vadd $v1, $v2, $v3[1q] 4 5 6 7 4 5 6 7
90 | vadd $v1, $v2, $v3[0h] 0 1 0 1 0 1 0 1
91 | vadd $v1, $v2, $v3[1h] 2 3 2 3 2 3 2 3
92 | vadd $v1, $v2, $v3[2h] 4 5 4 5 4 5 4 5
93 | vadd $v1, $v2, $v3[3h] 6 7 6 7 6 7 6 7
94 | vadd $v1, $v2, $v3[0] 0 0 0 0 0 0 0 0
95 | vadd $v1, $v2, $v3[1] 1 1 1 1 1 1 1 1
96 | vadd $v1, $v2, $v3[2] 2 2 2 2 2 2 2 2
97 | vadd $v1, $v2, $v3[3] 3 3 3 3 3 3 3 3
98 | vadd $v1, $v2, $v3[4] 4 4 4 4 4 4 4 4
99 | vadd $v1, $v2, $v3[5] 5 5 5 5 5 5 5 5
100 | vadd $v1, $v2, $v3[6] 6 6 6 6 6 6 6 6
101 | vadd $v1, $v2, $v3[7] 7 7 7 7 7 7 7 7
102 |
103 | Loads and stores can access byte, short, word, double word or quad word.
104 | For sizes less than quad word, the offset in the vector regsiter can be
105 | selected (on boundaries of that size). There are a whole bunch of 'fancy'
106 | loads and store which appear to shuffle the data on the way in out in
107 | useful ways. The offset for vector loads and vector stores is scaled
108 | depending on the element size.
109 |
110 | The 'guess' instructions (VRCP?, VRSQ?) are pipelined - result is derived
111 | from the previous instructions.
112 |
113 | With some of the Vector Multiply Instructions the Accumlator is a hidden
114 | 32 bit accumulator per element.
115 |
116 | * VMUDL: acc = (src1 * src2) >> 16, dest = acc & 0xffff
117 | * VMADL: acc += (src1 * src2) >> 16, dest = acc & 0xffff
118 | * VMUDM: acc = (src1 * src2), dest = acc >> 16
119 | * VMADM: acc += (src1 * src2), dest = acc >> 16
120 | * VMUDN: acc = (src1 * src2), dest = acc & 0xffff
121 | * VMADN: acc += (src1 * src2), dest = acc & 0xffff
122 | * VMUDH: acc = (src1 * src2) >> 16, dest = acc >> 16
123 | * VMADH: acc += (src1 * src2) >> 16, dest = acc >> 16
124 |
125 |
126 | RCP Opcode Encoding
127 | -------------------
128 |
129 | This section is still in it's preliminary stages.
130 |
131 |
132 | R-Type (Register) Instruction Format
133 |
134 | +-----------+---------+-------+-------+-------+-----------+
135 | | OP | RS | RT | RD | SA | Funct |
136 | +-----------+---------+-------+-------+-------+-----------+
137 | | 010010 | 10000 | ????? | ????? | ????? | ?????? |
138 | | | | | | | |
139 | | CP2 Instr | Sub OpC | VReg3 | VReg2 | VReg1 | CP2 Funct |
140 | +-----------+---------+-------+-------+-------+-----------+
141 |
142 |
143 | 2..0 COP2 Function
144 | 0 1 2 3 4 5 6 7
145 | 5..3 +-------+-------+-------+-------+-------+-------+-------+-------+
146 | 0 | VMULF | VMULU | VRNDP | VMULQ | VMUDL | VMUDM | VMUDN | VMUDH |
147 | +-------+-------+-------+-------+-------+-------+-------+-------+
148 | 1 | VMACF | VMACU | VRNDN | VMACQ | VMADL | VMADM | VMADN | VMADH |
149 | +-------+-------+-------+-------+-------+-------+-------+-------+
150 | 2 | VADD | VSUB | VSUT | VABS | VADDC | VSUBC | VADDB | VSUBB |
151 | +-------+-------+-------+-------+-------+-------+-------+-------+
152 | 3 | VACCB | VSUCB | VSAD | VSAC | VSUM | VSAW | | |
153 | +-------+-------+-------+-------+-------+-------+-------+-------+
154 | 4 | VLT | VEQ | VNE | VGE | VCL | VCH | VCR | VMRG |
155 | +-------+-------+-------+-------+-------+-------+-------+-------+
156 | 5 | VAND | VNAND | VOR | VNOR | VNXOR | | | |
157 | +-------+-------+-------+-------+-------+-------+-------+-------+
158 | 6 | | | | | | | | |
159 | +-------+-------+-------+-------+-------+-------+-------+-------+
160 | 7 | VEXTT | VEXTQ | VEXTN | VINST | VINSQ | VINSN | | |
161 | +-------+-------+-------+-------+-------+-------+-------+-------+
162 |
163 |
164 |
165 | RCP Vector Instruction Set
166 | --------------------------
167 |
168 | This section is still in it's preliminary stages. I have a lot more
169 | information about each instruction but have not had the time to write it
170 | all up yet.
171 |
172 |
173 | VMULF Vector (Frac) Multiply
174 | VMACF Vector (Frac) Multiply Accumulate
175 | VMULU Vector (Unsigned Frac) Multiply
176 | VMACU Vector (Unsigned Frac) Multiply Accumulate
177 | VRNDP Vector DCT Round (+)
178 | VRNDN Vector DCT Round (-)
179 | VMULQ Vector (Integer) Multiply
180 | VMACQ Vector (Integer) Multiply Accumulate
181 | VMUDH Vector (High) Multiply
182 | VMADH Vector (High) Multiply Accumulate
183 | VMUDM Vector (Mid-M) Multiply
184 | VMADM Vector (Mid-M) Multiply Accumulate
185 | VMUDN Vector (Mid-N) Multiply
186 | VMADN Vector (Mid-N) Multiply Accumulate
187 | VMUDL Vector (Low) Multiply
188 | VMADL Vector (Low) Multiply Accumulate
189 | VADD Vector Add
190 | VSUB Vector Subtract
191 | VSUT Vector SUT (vt - vs)
192 | VABS Vector Absolute Value
193 | VADDC Vector ADDC
194 | VSUBC Vector SUBC
195 | VADDB Vector Add Byte
196 | VSUBB Vector Subtract Byte
197 | VACCB Vector Add Byte/Add Accumulator
198 | VSUCB Vector Subtract Byte/Add Accumulator
199 | VSAD Vector SAD
200 | VSAC Vector SAC
201 | VSUM Vector SUM
202 | VSAW Vector SAW
203 | VLT Vector Less Than
204 | VEQ Vector Equal To
205 | VNE Vector Not Equal To
206 | VGE Vector Greater Than or Equal To
207 | VCL Vector Clip Low
208 | VCH Vector Clip High
209 | VCR Vector, 1's Complement Clip
210 | VMRG Vector Merge
211 | VAND Vector Logical AND
212 | VNAND Vector Logical NAND
213 | VOR Vector Logical OR
214 | VNOR Vector Logical NOR
215 | VXOR Vector Logical Exclusive OR
216 | VNXOR Vector Logical NOT Exclusive OR
217 | VNOOP Vector No-Operation
218 | VMOV Vector Scalar-Element Move
219 | VRCP Single Precision, Lookup Source, Write Result
220 | VRSQ Single Precision, Lookup Source, Write Result
221 | VRCPH Set Source, Write Previous Result
222 | VRSQH Set Source, Write Previous Result
223 | VRCPL Lookup Source and Previous, Write Result
224 | VRSQL Lookup Source and Previous, Write Result
225 | VINST Vector Insert Triple (5/5/5/1)
226 | VEXTT Vector Extract Triple (5/5/5/1)
227 | VINSQ Vector Insert Quad (4/4/4/4)
228 | VEXTQ Vector Extract Quad (4/4/4/4)
229 | VINSN Vector Insert Nibble (4/4/4/4) Sign-Extended
230 | VEXTN Vector Insert Nibble (4/4/4/4) Sign-Extended
231 |
232 |
233 | LBV Load Byte into Vector
234 | LSV Load Short into Vector
235 | LLV Load Word into Vector
236 | LDV Load Doubleword into Vector
237 | LQV Load Quadword into Vector
238 | LRV Load Rest Vector
239 | LPV Load Packed Vector
240 | LUV Load Unpack Vector
241 | LHV Load Half Vector
242 | LFV Load Fourth Vector
243 | LWV Load Wrap Vector
244 | LTV Load Transpose Vector
245 |
246 |
247 | SBV Store Byte from Vector
248 | SSV Store Short from Vector
249 | SLV Store Word from Vector
250 | SDV Store Doubleword from Vector
251 | SQV Store Quadword from Vector
252 | SRV Store Rest Vector
253 | SPV Store Packed Vector
254 | SUV Store Unpack Vector
255 | SHV Store Half Vector
256 | SFV Store Fourth Vector
257 | SWV Store Wrap Vector
258 | STV Store Transpose Vector
259 |
260 | I have not included the standard MIPS opcodes used in the RCP.
261 |
262 |
263 |
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/n64ops/sound.txt:
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1 | heres how one way to make sound on N64 :
2 | Crazy nation trainer (xtremeG version)
3 |
4 |
5 | [we tested button and its time to make sound!]
6 | lui $t4,8031 ;make pointer to 'yes' sound
7 | addiu $t4,$t4,4F10 ;80314f10 = start
8 | addiu $t5,$zero,4A71 ;4A71=length
9 | addiu $t6,$zero,1388 ;1388= DAC rate
10 | addiu $t7,$zero,0001 ;1=BIT rate
11 | jal here
12 | nop
13 | [draw yes]
14 | ......
15 |
16 | [we tested button and time to make 'no' sound]
17 | lui $t4,8031 ;make pointer to 'no' sound
18 | addiu $t4,$t4,12C4 ;803112C4
19 | addiu $t5,$zero,3C45 ;3C45=length
20 | addiu $t6,$zero,1388 ;DAC rate
21 | addiu $t7,$zero,0001 ;1=BIT rate
22 | jal here
23 | nop
24 | [draw no]
25 |
26 | .....
27 | [...initialize vid, audio]
28 | addiu $t4,$zero,0000 ;[blank out sound]
29 | addiu $t5,$zero,0000 ;initialize
30 | addiu $t6,$zero,0001
31 | addiu $t7,$zero,0001
32 | here: lui $t8,A450
33 | sw $t4,0000($t8) ;start RDRAM address
34 | sw $t5,0004($t8) ;length
35 | addiu $t9,$zero,0001
36 | sw $t9,0008($t8) ;1 = enable dma
37 | sw $t6,0010($t8) ;dac rate
38 | sw $t7,0014($t8) ;bit rate
39 | jr $ra
40 | nop
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/tutorial/day1n64.htm:
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1 |
2 |
3 | N64 ASM - Day 1
4 |
5 |
6 | Day 1
7 |
8 |
9 |
10 |
11 |
12 | Figuring out the Assembler
13 |
14 | First, there are several assemblers you could use for the N64, the one I've had
15 | the most luck using is ASMN6432.EXE from the PSY-Q devkit. Unfortunately, I can't tell
16 | you where to get the devkit (which does contain a C compiler, so if you're not macho enough
17 | to use assembler, you can go right ahead and use those illegal libs!), because many people
18 | would object to it. It's simple enough to find with a search on Google, I regularly loose
19 | the URL and then find it again in about 30 min. with Google. LEARN THE WAYS OF THE GOOGLE!
20 |
21 | The other assemblers that I've had some success with are the one by HalleysCometSoftware
22 | and Anarko's assembler (in that order). You can get HCS's assembler (and good demo code) from the link above.
23 | Anarko's assembler is on Dextrose.
24 |
25 | I recommend creating a directory like C:\n64asm\ , so that it has no spaces and you can just
26 | keep everything in there. Each one of these assemblers needs a different style command to assemble,
27 | they are: (On the DOS/CMD command-line)
28 |
29 | For ASMN6432.EXE:
30 | asmn6432 /p SOURCE,OUTPUTFILE.BIN
31 | copy HEADER /B+OUTPUTFILE.BIN OUTPUTFILE.N64
32 |
33 | For n64asm.exe (Anarko's):
34 | Look at the demo sources for the header puesdo-codes, and type n64asm by itself
35 | on the command-line for how to assemble.
36 |
37 | For n64.exe (HCS's):
38 | n64 SOURCE.ASM -r
39 |
40 | You may have noticed that ASMN6432 needs an extra command that adds the rom header, you can get
41 | that from HCS's zip file.
42 |
43 | Second, I must say that what I know about the N64 (everything I know at a certain time
44 | that can be applied toward a certain working code file will be eventually described in a "Day"),
45 | which isn't much as I write this, came from reading documents found on Dextrose and the web AND
46 | from HCS kindly putting up with my endless questions on Dextrose's Forum, this (hopefully to be
47 | these) document(hopefully (s)) would not have been possible without his help.
48 |
49 | Our First ROM
50 | From here on out, I assume you are using ASMN6432, but N64.exe (HCS's assembler) has
51 | almost the same syntax and, now that I think of it, Anarko's assembler is still quite similar, you'll just have
52 | to figure out how to use each one (and maybe tinker the code a little to get it to assemble on
53 | your chosen assembler.
54 |
55 | Here's our first code file:
56 |
57 | ;;---START OF CODE FILE---;;
58 | org $80000400
59 |
60 | li t1,8
61 | lui t0,$bfc0
62 | sw t1,$07fc(t0)
63 |
64 | infin:
65 | nop
66 | j infin
67 | ;;---END OF CODE FILE---;;
68 |
69 | Now to see what each line does:
70 |
71 | org $80000400
72 |
73 | This tells the assembler where the entry point of the code is in N64 memory ($80000400 is standard for ASM progs).
74 |
75 | li t1,8
76 | lui t0,$bfc0
77 | sw t1,$07fc(t0)
78 |
79 | These lines (which I got from HCS), stop the N64 from crashing in 5 secs. after your
80 | program starts (according to HCS, and some other people). I'm not going to explain
81 | them until later (because I don't what about them stops the N64 from crashing).
82 |
83 | infin:
84 |
85 | If you don't know what that is, I suggest you go read either the GBA or NES assembly sections (the
86 | GBA one is better written in my opinion). Here's a link for you.
87 |
88 | nop
89 |
90 | A Classic, it does nothing, that's right, nothing, except that you should put NOPs
91 | after labels, a spot appearantly known as a "Delay Slot", some assemblers get pissed off
92 | if you have anything but a NOP in the Delay Slot.
93 |
94 | j infin
95 |
96 | J is the jump instruction, J jumps to a label, like Goto in BASIC. In this case, J jumps to
97 | infin, creating an infinite loop like while(1); .
98 |
99 | Assemble your file like shown in the beginning, if you get no errors, you've done a good job.
100 | (I recommend (again) that you keep your assembler and code files in C:\n64asm\, and CD to that
101 | directory in DOS, when you want to assemble something)
102 |
103 | This Day In Review
104 |
105 | Tomorrow, we'll download an emulator and a plugin needed for the type of programming
106 | where using. Hopefully, we'll quickly get to setting up our VI (Video Interface) registers.
107 |
108 | Until Next Time,
109 | -Mike H a.k.a GbaGuy
110 |
111 | Intro - Day 2
112 |
113 |
114 |
115 |
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1 |
2 |
3 | N64 ASM - Day 2
4 |
5 |
6 | Day 2
7 |
8 |
9 |
10 |
11 |
12 | Some Instructions
13 |
14 | In the other tutorials, I may have sort of taught the assembly language
15 | and the system workings at the same time. I don't think that would be best this
16 | time around because of the N64 being somewhat more complex. So today, I'll just
17 | describe the registers and the instructions: LI,LA,LW,SW.
18 |
19 | Before We Get Started
20 | You're probably wondering how to run your ROM. Well, Nemu (which you can get from Zophar)
21 | has a pretty good debugger. To run the ROMs that we'll eventually get to making, you need this
22 | Plugin for Nemu to support the bitmap-mode
23 | drawing that we'll be doing (Thanks again to HCS, for pointing me to it).
24 |
25 | The R4300i
26 | The main processor that will be running all of our code for a while is a standard RISC MIPS R4300i,
27 | similar to the one in the PS1 (identical maybe?). It runs at ~93MHz. This thing has even more registers
28 | than the ARM7 in the GBA!! There are 32 registers, I'm still not positive what they all are for, but they are
29 | (in the order listed in Nemu's debugger):
30 |
31 | R0 - Special in that it is always zero, you can't change it.
32 | AT - Not entirely sure. Seems to be available to us.
33 | V0-V1 - Don't know.
34 | A0-A3 - Are used to pass parameters to subroutines.
35 | T0-T7 - Temporary data registers, what we should use for regular coding.
36 | S0-S7 - Called "Save" or "Saved" registers, preserved across subroutine calls??
37 | T8-T9 - Don't know, maybe same as other 'T' registers.
38 | K0-K1 - No Clue.
39 | GP - No Clue.
40 | SP - See AT
41 | S8 - No Clue.
42 | RA - Stores the Return Address for subroutine calls.
43 |
44 | If someone can email me and fill me in on the ones that I don't know or anything that's wrong that you
45 | ever see, please correct me. (I suppose I'll look at the MIPS tech docs and fill out the rest of the list)
46 |
47 | The LI,LA Instructions
48 | First, the LI instruction. The LI instruction takes 2 operands (parameters):
49 |
50 | li t0, 2 ; the register on the left will get the number on the right.
51 |
52 | simple enough.
53 |
54 | Now, the LA instruction. It also takes 2 operands:
55 |
56 | la t4, LABEL ; the register on the left will get the address of the label on the right.
57 |
58 | Easy, but there's another use. You can (have to with HCS's assembler) use it the same as LI also,
59 | so like this:
60 |
61 | la t0,2 ; register/left gets number/right
62 |
63 | Wow, that was way easier and shorter to explain than I thought it was going to be... (Did I miss something?)
64 |
65 | This Day In Review
66 |
67 | Hopefully tomorrow, we'll take a look at the Video Interface Mem. Registers.
68 | Nintendo seems to like memory mapping their initialization interfaces...
69 |
70 | Happy Learning!,
71 | - GbaGuy
72 |
73 | Intro - Day 3
74 |
75 |
76 |
77 |
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1 |
2 |
3 | N64 ASM - Day 3
4 |
5 |
6 | Day 3
7 |
8 |
9 |
10 |
11 |
12 | Video Interface Registers
13 |
14 | The VI (Video Interface) Memory Mapped Registers start at 0xA4400000 in N64 main memory
15 | and allow you to initialize the bitmapped screen in many different ways (See Anarko's N64OPS on Dextrose.
16 | Anarko's document lists them starting at 0x04400000, I don't know why. The Video Registers are:
17 | (As listed by Nemu's debugger):
18 |
19 | VI_STATUS_REG (0xA4400000) - Chooses color-depth, and some gamma/antialias/interlacing options
20 | VI_DRAM_ADDR_REG (0xA4400004) - The address of the currect framebuffer (set it to the memory you're going to
21 | use for the N64's bitmapped screen.)
22 | VI_H_WIDTH_REG (0xA4400008) - The Horizontal Resolution of the framebuffer.
23 | VI_V_INTR_REG (0xA440000C) - Not sure. Check out N64OPS.
24 | VI_V_CURRENT_LINE_REG (0xA4400010) - I think it gives the current line that is being drawn. (use it to check
25 | for VBlank??)
26 | VI_TIMING_REG (0xA4400014) - Not sure what it means that N64OPS says..
27 | VI_V_SYNC_REG (0xA4400018) - "number of half-lines per field", what the **** does that mean?
28 | VI_H_SYNC_REG (0xA440001C) - Don't know. See N64OPS.
29 | VI_H_SYNC_LEAP_REG (0xA4400020) - Don't know. See N64OPS.
30 | VI_H_VIDEO_REG (0xA4400024) - Ditto.
31 | VI_V_VIDEO_REG (0xA4400028) - Ditto.
32 | VI_V_BURST_REG (0xA440002C) - Ditto.
33 | VI_X_SCALE_REG (0xA4400030) - Seems obvious, but description is a little wierd, commonly seen at 0x200.
34 | VI_Y_SCALE_REG (0xA4400034) - Seems obvious, but description is a little wierd, commonly seen at 0x400.
35 |
36 | I'll fill out this chart as I figure out exactly what each one does. See Anarko's N64OPS for his
37 | description (which come almost straight from the comments from the official dev headers).
38 |
39 | If anyone has some more info on these, please email me (I'm going to be saying that alot, aren't I? :) )
40 |
41 | Before We Get Started
42 | You're probably wondering how to run your ROM. Well, Nemu (which you can get from Zophar)
43 | has a pretty good debugger. To run the ROMs that we'll eventually get to making, you need this
44 | Plugin for Nemu to support the bitmap-mode
45 | drawing that we'll be doing (Thanks again to HCS, for pointing me to it).
46 |
47 | Initialization of Video
48 | But first, there's 2 instructions we still need to learn: LW and SW. They work like so:
49 |
50 | LW Loads a 32-bit Word from memory like this:
51 | lw t1,0(t3) ; the 32-bit word at the address created by the memory location
52 | ; in t3 + zero in this case, will be put into t1.
53 | Here's another:
54 | lw t0,4(t1) ; the 32bit word at the address created by the memory location in t1 +4 will be put into
55 | ; t0. So if the address 0xA0200004 has 32 in it,
56 | ; and t1 has 0xA0200000 in it plus the 4 will be 0xA0200004 and then t0 will end up with
57 | ; the 32.
58 |
59 | I hope you understood that.
60 |
61 | SW works in precisely the same way except that it will store the register on the left into the memory address
62 | created by the register plus offset on the right. (The 4 and the zero in the examples are the offsets.)
63 |
64 | Here's our video initialization code:
65 | ;;---CODE START---;;
66 | ; I should mention that while I use 0x in this tutorial's text for hexadecimal numbers,
67 | ; ASMN6432.exe uses $.
68 | la t0,$A4400000 ; VI status register (start of VI reg. mem.)
69 | li t1, $103002 ; basically 16bit color and some other things
70 | sw t1,0(t0)
71 | la t1,0xa0200000 ; address of screen bitmap (framebuffer)
72 | sw t1,4(t0)
73 | li t1,320 ; width of screen (horizontal resolution?)
74 | sw t1,8(t0)
75 | li t1,$2 ; Don't know.
76 | sw t1,12(t0)
77 | li t1,$0 ; Ditto.
78 | sw t1,16(t0)
79 | li t1,$3e52239 ; Ditto until next comment
80 | sw t1,20(t0)
81 | li t1,$0000020d
82 | sw t1,24(t0)
83 | li t1,$00000c15
84 | sw t1,28(t0)
85 | li t1,$0c150c15
86 | sw t1,32(t0)
87 | li t1,$006c02ec
88 | sw t1,36(t0)
89 | li t1,$002501ff
90 | sw t1,40(t0)
91 | li t1,$000e0204
92 | sw t1,44(t0)
93 | li t1,$200 ; something about horizontal scaling?
94 | sw t1,48(t0)
95 | li t1,$400 ; something about vertical scaling?
96 | sw t1,52(t0)
97 | ;;---CODE END---;;
98 |
99 | It basically selects a 320x240 16 bit mode, and does some other stuff I don't know yet.
100 | (That code is essentailly the same as code that HCS was again, nice enough to show me, so
101 | now I use 320x240 16 bit mode.)
102 | It probably wouldn't be too hard to change that to 32 bit color, but I just don't feel like
103 | it (I think you'd have to change $103002 to $103003) and 16 bit color is plenty for most things.
104 | The offsets are not permanently added to the register in ()s, so in the code, the offsets just keep
105 | gaining by 4, for each VI register set.
106 |
107 | This Day In Review
108 |
109 | Tomorrow, we'll learn some math instructions and then the next day, we'll do some loops.
110 | Then, we'll put together a code file that clears the screen (with code that, yep, HCS showed me.)
111 |
112 | Hold on! We're getting there!,
113 | - GBAGuy
114 |
115 | Intro - Day 4
116 |
117 |
118 |
119 |
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1 |
2 |
3 | N64 ASM - Day 4
4 |
5 |
6 | Day 4
7 |
8 |
9 |
10 |
11 |
12 | Math
13 |
14 | Today is going to be all about the math instructions ADD and SUB.
15 |
16 | The ADD Instruction
17 | Now, reel in the fish slowly! Oops, ADD means ADDition, not Attension Deficit Disorder!
18 | What was I thinking!.
19 |
20 | Ok, now that the bad joke is out of the way, ADD works like this:
21 | ADD t1,t2,t3 ; t1 = t2 + t3; is just about the simplest way I can describe it.
22 |
23 | I've also seen:
24 | ADD t1, 2 ; which is supposed to be t1 += 2, appearantly. THIS DOESN'T ALWAYS WORK!
25 | ; alot of the time, an assembler either errors or interprets this as t1 += V0
26 |
27 | Which brings me to another point, a register's (in some assemblers) number can be used
28 | instead it it's t1,v0,a3 style name. See Nemu's debugger for as far as I know, is the correct order.
29 |
30 | The SUB Instruction
31 | INSERT BAD JOKE ABOUT SubWay HERE.
32 |
33 | The SUB Instruction works like so:
34 | SUB t0,t4,t5 ; t0 = t4 - t5; There's a chance I might have t4 and t5 in the wrong order,
35 | ; but I think I have it right.
36 |
37 | The "I've also seen" comment applies to SUB as well.
38 |
39 | The MUL/DIV Instruction
40 | The MUL and DIV Instructions work like this (as far as I can tell):
41 |
42 | MUL t0,t2,t4 ; t0 = t2 * t4;
43 |
44 | DIV t1,t0,t6 ; t1 = t0 / t6;
45 |
46 | Also note that all these math instructions use signed numbers.
47 |
48 | Comparison/Branch Instructions
49 | This would have been shorter than I wanted it to be, so I'll have to talk about Comparison/Branch Instructions
50 | also.
51 |
52 | The first instruction we'll learn is BNEZ, BNEZ is a psuedo-instruction that only Anarko's assembler doesn't
53 | support (along with LA). BNEZ is used like so:
54 |
55 | bnez t1, LABEL ; IF t1 not equal zero THEN GOTO LABEL
56 |
57 | For assemblers that don't support it, use:
58 |
59 | bne t1,$0,LABEL ; same as above, note that $0 is the special CPU register that is permanently zero.
60 |
61 | The other use for BNE (no Z) is:
62 |
63 | bne t1,t3,LABEL ; IF t1 not equal t3 THEN GOTO LABEL
64 |
65 | There is also:
66 |
67 | beq t1,t3,LABEL ; IF t1 == t3 THEN GOTO LABEL
68 |
69 | blt t0,t1,LABEL ; IF t0 less than t1 THEN GOTO LABEL
70 |
71 | bgt t0,t1,LABEL ; IF t0 greater then t1 THEN GOTO LABEL
72 |
73 | ble t2,t4,LABEL ; IF t2 less or = to t4 THEN GOTO LABEL
74 |
75 | bge t2,t4,LABEL ; IF t2 greater or = to t4 THEN GOTO LABEL
76 |
77 | Add a U to the end of the instruction (like BGEU) to compare unsigned numbers.
78 |
79 | This Day In Review
80 |
81 | Tomorrow, we'll either learn another set of instructions, or we'll do
82 | something else (maybe a pic on screen)!
83 |
84 | Until Next Time!,
85 | - Mike H a.k.a GbaGuy
86 |
87 | Intro - Day 5
88 |
89 |
90 |
91 |
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1 |
2 |
3 | N64 ASM - Day 5
4 |
5 |
6 | Day 5
7 |
8 |
9 |
10 |
11 |
12 | Subroutines
13 |
14 | Today is going to be short (maybe) and be about subroutines.
15 | The N64 CPU's subroutine call instruction is JAL (Jump And Link) it works
16 | like so:
17 |
18 | JAL LABEL ; jump to LABEL, putting return address in ra.
19 | NOP ; you should put a NOP after JALs also. Delay Slot?
20 |
21 | Then at LABEL you have:
22 |
23 | LABEL:
24 | NOP ; Delay Slot NOP
25 | JR ra ; Jump Register ra (that contains return address)
26 |
27 | Note that you can't nest subroutine calls, as a subroutine call will erase
28 | the old return value in ra. The GBA is also like that, the NES is not.
29 |
30 | It would help if there was a built-in stack. (Is there?)
31 |
32 | The LUI Instruction
33 | I'm not sure what the LUI instruction does, but I'm fairly sure
34 | that it loads the second 16bits of a register, like so:
35 |
36 | LI t1,0 ; t1 = $00000000
37 | LUI t1,$a440 ; after instruction, r1 = $a4400000
38 |
39 | Simple enough, if I didn't miss anything.
40 |
41 | This Day In Review
42 |
43 | Tomorrow, we'll definitely put a pic on the screen!
44 |
45 | I Can't Wait!,
46 | - GbaGuy
47 |
48 | Intro - Day 6
49 |
50 |
51 |
52 |
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1 |
2 |
3 | N64 ASM - Day 6
4 |
5 |
6 | Day 6
7 |
8 |
9 |
10 |
11 |
12 | See Screen, See Pic On Screen
13 |
14 | Today we'll put a picture on the screen.
15 |
16 | First
17 | Make a 320x240 bitmap in MSPaint, save in C:\n64asm\ as pic.bmp.
18 | Next, goto Dextrose and download the
19 | patch to the GroundZero Devkit, what we want is the BMP2N64 program. Copy
20 | BMP2N64.exe to your n64 assembly folder. Open a DOS Prompt and type:
21 |
22 | cd your assembly folder path
23 | bmp2n64 -in:pic.bmp -out:pic -label:pic -16
24 |
25 | Two files should be created, you can delete the .H file, but keep the .S file.
26 | The .S File may work as is, but I recommend you delete the lines before
27 | the label and replace all ".half"s with "dh" (no quotes).
28 |
29 | The Code
30 |
31 | The code for this isn't that much different than we've seen before
32 | or that you could have come up with on your own. So here we go (the whole thing):
33 |
34 | ;;---CODE START---;;
35 | org $80000400 ; starting point
36 |
37 | li t1,8 ; crash protection
38 | lui t0,$bfc0 ; I still don't know what this specifically does.
39 | sw t1,$07fc(t0)
40 |
41 | la t0,$A4400000 ; start of VI regs. ; this block initializes Video
42 | li t1, $103002
43 | sw t1,0(t0)
44 | la t1,$a0200000 ; the frame buffer address
45 | sw t1,4(t0)
46 | li t1,320
47 | sw t1,8(t0)
48 | li t1,$2
49 | sw t1,12(t0)
50 | li t1,$0
51 | sw t1,16(t0)
52 | li t1,$3e52239
53 | sw t1,20(t0)
54 | li t1,$0000020d
55 | sw t1,24(t0)
56 | li t1,$00000c15
57 | sw t1,28(t0)
58 | li t1,$0c150c15
59 | sw t1,32(t0)
60 | li t1,$006c02ec
61 | sw t1,36(t0)
62 | li t1,$002501ff
63 | sw t1,40(t0)
64 | li t1,$000e0204
65 | sw t1,44(t0)
66 | li t1,$200
67 | sw t1,48(t0)
68 | li t1,$400
69 | sw t1,52(t0)
70 |
71 | li t0,0xa0200000
72 | li t3,2
73 | la t2,MKImage ; MKImage should be the label in your .S file
74 | li t1,320*240*2-2
75 | drawImage:
76 | lh t4,0(t2)
77 | sh t4,0(t0) ; there's probably a better way, but oh well :)
78 | add t2,t2,t3
79 | add t0,t0,t3
80 | sub t1,t1,t3 ; there's a better place for this that'll be discussed later
81 | bnez t1,drawImage
82 |
83 | infin:
84 | nop
85 | j infin
86 |
87 | include MKImage.S ; MKImage.S should be the filename of your .S File
88 | ;;---CODE STOP---;;
89 |
90 | This Day In Review
91 |
92 | I hope you take the time to understand code and not just rip it :)!
93 |
94 | Until Next Time!,
95 | - Mike H a.k.a GbaGuy
96 |
97 | Intro - Day 7
98 |
99 |
100 |
101 |
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1 |
2 |
3 | N64 ASM - Day 7
4 |
5 |
6 | Day 7
7 |
8 |
9 |
10 |
11 |
12 | The Delay Slot
13 |
14 | This thing is so Evil and Cool at the same time, I can't come up
15 | seem to come up with even a good joke for the intro (I said "Slot!", maybe?).
16 |
17 | The Info
18 | This information is brought to you by HCS:
19 |
20 | The code for this isn't that much different than we've seen before
21 | or that you could have come up with on your own. So here we go (the whole thing):
22 | (It has been slightly edited)(HCS, I hope you don't mind.):
23 |
24 | This is the instruction immediately after a jump or branch instruction. It is executed during the jump (actually, while
25 | the instruction at the target is being fetched). For example, if we have
26 |
27 | code:--------------------------------------------------------------------------------
28 | jal dest
29 | addi t0,t0,1
30 | --------------------------------------------------------------------------------
31 |
32 | Both the jump and the addition will occur. There are some instructions which can't be in
33 | delay slots though (I don't have my manual with me right now and I don't remember what they are)
34 | and asmn64 checks for those. One good application for this is to make loops:
35 |
36 | code:--------------------------------------------------------------------------------
37 | li t0,7
38 | loop:
39 | ; something to be done 8 times
40 | bnez t0, loop
41 | addi t0,-1
42 | --------------------------------------------------------------------------------
43 |
44 | The increment (decrement in this case) is had for free, during time the processor would be
45 | otherwise wasting. It is important, whenever you code a jump, to put a NOP after it until
46 | you intend to use the delay slot, otherwise some other part of the code might execute
47 | accidentally. I believe that asmn64 has a command line switch to do this for you automatically.
48 |
49 | The exception to the delay slot execution is several branches called "likely". Actually, they still
50 | execute the instruction in the delay slot, but if the branch is not taken the delay instruction
51 | is skipped. This takes some extra time for the processor to ignore the instruction, so they
52 | should only be used when it is "likely" that the branch will be taken.
53 |
54 | This Day In Review
55 |
56 | It's always good to get the information from someone who knows what they're talking about!
57 |
58 | Important stuff!,
59 | - GbaGuy
60 |
61 | Intro - Day 8
62 |
63 |
64 |
65 |
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1 |
2 |
3 | N64 ASM - Day 8
4 |
5 |
6 | Day 8
7 |
8 |
9 |
10 |
11 |
12 |
13 | Getting Code Onto The RSP
14 |
15 | The RSP is M-a-g-i-c-a-l!
16 |
17 | Just keep saying that to yourself any time you can't figure why your code isn't working! :)
18 | Just kidding!
19 |
20 | The RSP
21 | First, read N64OPS#H.TXT (Anarko's N64OPS doc, which if you don't have by now, pretend I'm hitting
22 | you with a trout!!!) and look at the SP registers section.
23 |
24 | The RSP is like another processor and contains most of the instructions of the main R4300i. The RSP can
25 | only address main memory from 0xA4000000 To 0xA40FFFFF, if you want to access other parts of memory you
26 | have to use the SP Mem. Registers to DMA to other parts of main memory. Conveniently, the SP registers
27 | reside in the part of main memory that the RSP can access.
28 |
29 | There are two sections of the RSP's memory that are for Data and Code respectively, one is DMEM that
30 | stores Data and is at 0xA4000000 to 0xA4000FFF (small :( ). The other is IMEM and stores code for the RSP
31 | to execute and is at 0xA4001000 to 0xA4001FFF.
32 |
33 | The SP Registers
34 | The RSP Memory registers start at 0xA4040000 and are:
35 | (These aren't in order and are only the ones that we are going to need today.)
36 |
37 | SP_MEM_ADDR_REG (0xA4040000) - Location to DMEM or IMEM to write to, commonly zero. Bit 12 selects
38 | (1) IMEM or (0) DMEM.
39 | So to transfer to/from starting at 0 write 0x1000 for IMEM or 0x0 for DMEM
40 | to this register.
41 |
42 | SP_DRAM_ADDR_REG (0xA4040004) - Location in main memory to DMA to/from.
43 | SP_RD_LEN_REG (0xA4040008) - The length in bytes of data to read from main memory INTO the RSP.
44 | When you write to this register, DMA will start.
45 |
46 | SP_WR_LEN_REG (0xA404000C) - The length in bytes of data to read from RSP TO main memory.
47 | Writing to this register will also start DMA.
48 |
49 | SP_PC_REG (0xA4080000) - The Program Counter for the RSP, set it to 0x0 before starting the RSP.
50 |
51 | SP_STATUS_REG (0xA4040010) - Allows you to set breaks and halts and interrupts and stuff, you need to
52 | clear a bunch of that stuff in this register to start the RSP.
53 |
54 | Setting Up DMA
55 | Setting up DMA is quite simple, 3 steps:
56 |
57 | 1) Set SP_MEM_ADDR_REG.
58 | 2) Set SP_DRAM_ADDR_REG.
59 | 3) Set SP_RD_LEN_REG (SP_RD_LEN_REG is Main Mem. -> RSP)
60 |
61 | Writing to a length register causes to DMA to go.
62 |
63 | Making The RSP Go
64 | Making the RSP go is 2 steps:
65 |
66 | 1) Set SP_PC_REG (zero is just fine.)
67 | 2) Set SP_STATUS_REG (you need to clear almost everything that can be
68 | cleared in the first 9 bits (0-8) (See N64OPS#H.txt)
69 |
70 | After you clear the halts and breaks and stuff the RSP will start running it's code.
71 |
72 | The Code File
73 | Here's the code to get some code onto the RSP:
74 |
75 | ;;---CODE START---;;
76 | org $80000400
77 |
78 | li t1,8 ; that crash protection code
79 | lui t0,$bfc0
80 | sw t1,$07fc(t0)
81 |
82 | la t0,0xA4040000 ; SP_MEM_ADDR_REG
83 | li t1,0x1000 ; 0x1000 is the start of IMEM (remember as far as the RSP knows it's memory starts at zero,
84 | ; but we know it's memory really starts at 0xA4000000)
85 | sw t1,0(t0) ; SP memory address
86 |
87 | la t0,0xA4040004 ; SP_DRAM_ADDR_REG
88 | la t1,RCPCode ; address of our code to put in the RSP's IMEM.
89 | sw t1,0(t0)
90 |
91 | la t0,0xA4040008 ; SP_RD_LEN_REG
92 | li t1,72 ; length in bytes, to find this value, multiply the #lines of code that you're putting in the RSP * 8
93 | sw t1,0(t0) ; the DMA will start after this write is done.
94 |
95 | nop
96 | nop ;time for the emulator, I'll leave making a loop to wait until DMA is done an exercise to you (my kind reader.)
97 |
98 | la t0,0xA4080000 ; SP_PC_REG
99 | la t1,0x0 ; just set it to zero
100 | sw t1,0(t0)
101 |
102 | la t0,0xA4040010 ; SP_STATUS_REG
103 | li t1,%100101101 ; clears a bunch of things like halt and break. (See N64OPS#H.txt)
104 | sw t1,0(t0) ; and makes the code run
105 |
106 | infin:
107 | nop
108 | j infin
109 | nop
110 |
111 | RCPCode:
112 | obj 0x0 ; sets the base of the code so that jumps/branches will be correct.
113 | always:
114 | nop
115 | j always
116 | objend ; not sure if it's endobj on some assemblers...
117 | nop
118 | nop
119 | nop
120 | ;;---CODE END---;;
121 |
122 | I realize that the code doesn't do anything, I just wanted to get code onto the RSP.
123 | To verify that it works, take a look at Nemu's debugger under "Commands" and under the RSP tab,
124 | you should see just an infinite loop (a J instruction to the address above it).
125 |
126 | This Day In Review
127 |
128 | Hopefully I'll be able to do more with the RSP and therefore teach you more as time goes on.
129 |
130 | Happy coding!,
131 | - GbaGuy
132 |
133 | Intro - Day 9
134 |
135 |
136 |
137 |
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1 |
2 |
3 | N64 ASM - Day 9
4 |
5 |
6 | Day 9
7 |
8 |
9 |
10 |
11 |
12 |
13 | Using The Serial Interface
14 |
15 | The Serial Interface (a.k.a The SI Registers) is used for many things including reading controller
16 | data and writing to mempaks and using the Rumble. I recommend that you see LaC's hardware doc for the best
17 | info on using the SI.
18 |
19 | The Info
20 | The SI does DMA with a 64 byte command packet between PIH RAM and main memory (PIH RAM is in main
21 | memory, but it's like taboo to use normal writes with it...). The 64b command packet can be visualized like
22 | this (all diagrams adapted/copied from LaC's doc):
23 |
24 | [64byte block] at 0xbfc007c0 (1fc007c0)
25 | { Command : Results placed here when you DMA the data back to main memory
26 | ff 00 00 00 : 00 00 00 00 - 8 bytes
27 | ff 00 00 00 : 00 00 00 00 - 8 bytes
28 | ff 00 00 00 : 00 00 00 00 - 8 bytes
29 | ff 00 00 00 : 00 00 00 00 - 8 bytes
30 | ff 00 00 00 : 00 00 00 00 - 8 bytes
31 | ff 00 00 00 : 00 00 00 00 - 8 bytes
32 | ff 00 00 00 : 00 00 00 00 - 8 bytes
33 | ff 00 00 00 : 00 00 00 01 - 8 bytes
34 | } ^^pif status/control byte
35 |
36 | It will help for our purposes that the last byte, refered to by LaC as the control byte, always be 01.
37 | Although there's room for 4 bytes, most commands only use 3, so put the Reset command ($FF) in the first spot
38 | to align everything so you get the Results conveniently 4 byte aligned.
39 |
40 | This diagram describes the form of the 3 bytes of the command:
41 |
42 | Command Types:
43 |
44 | | Command | Description |t |r |
45 | +---------+--------------------------+-----+
46 | | 00 | request info (status) |01|03|
47 | | 01 | read button values |01|04|
48 | | 02 | read from mempack slot |03|21|
49 | | 03 | write to mempack slot |23|01|
50 | | 04 | read eeprom |02|08|
51 | | 05 | write eeprom |10|01|
52 | | ff | reset |01|03|
53 | NOTE: values are in hex
54 | t r Command
55 | Every command is in the form of (referring to the diagram): t r Command. So reading a controller is 0xFF010401 (that
56 | first 0xFF is the alignment thing from the first diagram.). The only thing that I understand how to do so far is read
57 | the controllers, the command packet for reading the controllers looks like this:
58 |
59 | [64byte block]
60 | { command data
61 | ff 010401 - ffffffff
62 | ff 010401 - ffffffff
63 | ff 010401 - ffffffff
64 | ff 010401 - ffffffff
65 | fe 000000 - 00000000
66 | 00 000000 - 00000000
67 | 00 000000 - 00000000
68 | 00 000000 - 00000001
69 | }
70 |
71 | The byte 0xFE means that there aren't any more commands, it can be left off if the packet is totally full of commands.
72 | Appearantly, the controller that we are reading changes by 1 with each controller read command, so the first one is
73 | controller 1, then #2,#3,and #4. Also, if you just read 1 controller, the reading resets between sending command packets,
74 | so you can't read each controller 1 at a time with 1 read command in each packet (I don't know why you'd do that, but you
75 | can't anyway...).
76 |
77 | Note that some commands aren't only 3 bytes long, that's because of the real meaning of t and r. t is how many bytes
78 | we are sending in this specific command not including the r byte (but including, appearantly, the Command byte that
79 | comes after r ). r is how many bytes we want returned as Results from the PIH. Also note that having more than 3
80 | bytes in the specific command makes the previous type of diagram out of alignment with where the results are going to
81 | end up. Results will always end up after the specific command, they just might not be perfectly aligned on those 4
82 | bytes...
83 |
84 | This Day In Review
85 |
86 | Most (more like all) of this information was edited from LaC's hardware document v0.8.
87 | Please note that this was just to explain SI (or atleast how I understand it, might not be correct.) and
88 | doing specific things like reading controllers and making the RumblePak go will be covered in separate "Day"s.
89 |
90 | Read The Docs!,
91 | - GBAGuy
92 |
93 | Intro - Day 10
94 |
95 |
96 |
97 |
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1 |
2 |
3 | N64 ASM Tutorial
4 |
5 |
6 | N64 ASM Tutorials
7 |
8 | This tutorial is about coding for the Nintendo 64 using
9 | your chosen assembler (see Day 1). The tutorial assumes basic assembly
10 | knowledge, so you would most likely want to come here after knowing GBA
11 | or NES assembly.
12 |
13 | The Extreme Basics (all I know :) )
14 | Day 1 - Figuring Out the Assembler
15 | Day 2 - Some Instructions
16 | Day 3 - Video Interface Registers
17 | Day 4 - Math
18 | Day 5 - Subroutines
19 | Day 6 - See Screen, See Pic On Screen
20 | Day 7 - The Delay Slot
21 | Day 8 - Getting Code onto The RSP
22 | Day 9 - Using The Serial Interface
23 |
50 |
51 |
52 |
53 | If anyone would like to donate something, such as an N64 or V64
54 | , please EMail Me. Also, don't
55 | hesitate to send comments or suggestions.
56 |
57 | If you came directly here, check out all the GBA and NES stuff
on the Home Page!
58 |
59 |
60 |
61 |
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/z64/z64_arch.txt:
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1 | The Z64 contains an ALi chip, which is far more than a 386: it is a
2 | more or less complete PC (memory, dma and timers, isa bus, keyboard
3 | and simple ISA-based IDE) with that chip, a clock generator and a few
4 | of DRAM chip you have a completely running system.
5 | The N64 interface is done (in HW1.x and 2.x) with a QuickLogic PLD,
6 | while in the 3.x hardware is implemented on-dice in the CPU (which ALi
7 | is able to customize up to a certain degree...) The "ROM" memory and
8 | the emulation interface is visible to the Z64 as a set of I/O ports.
9 |
10 | The Z64 has 512k of RAM (upgradable to 1Meg soldering in the
11 | appropriate chip) and 512K of flash memory (this memory is paged).
12 | it works at ~28MHz. The "ROM" is a 5V dual-bank EDO SIMM. A non-edo or 3.3V
13 | (5v tolerant) part WON'T work.
14 |
15 | the layout of the flash is as follows:
16 |
17 | 4k of "boot rom": the rom is structured as a ISA-EXTENSION bios (which
18 | makes the rest of the flash a bootable disk)
19 |
20 | 444k of a virtual drive (the Z64 sees this as 'A:') formatted as a
21 | normal MSDOS FAT12 floppy.
22 |
23 | 64k in which the bios for the x86 is stored two times.
24 |
25 | The Z64 uses Caldera's OpenDOS as operating system, but it works just
26 | fine with any MSDOS-Like OS (for example the EXCELLENT RxDOS, which
27 | became totally free recently).
28 |
29 | The internal bios is limited to CHS addressing for the hard drive, so
30 | you could have an hard disk of no more than 5xx megabytes, but OpenDOS
31 | has an even harder limitation: the rom'able version only supports
32 | 512 bytes (1 sector) clusters, so you can have only 32 megs as
33 | harddrive. This limitation is bypassed by the IOMega GUEST.EXE so it
34 | is possible to use a zip disk -- most probably using the GUEST.EXE of
35 | the 250M zip it should work fine.
36 |
37 | The Z64 user interface is a simple MSDOS program (the on-screen N64
38 | gui is done by sending to the N64 a special "ROM")
39 |
40 | The Flash-Rom in HW2 is a SST 28SF040
41 | On the SST site (http://www.ssti.com/) this chip is well documented.
42 | It's unlikely that software can fry this chip, but it can get in a non-accessible state.
43 | On the above site you can find instructions to exit this state.
44 |
45 | The CDROM is not a problem related to bios or cluster size: in fact
46 | the "cdrom.sys" driver and MSCDEX.EXE do handle all the accesses to
47 | the CD directly (the "cdrom.sys" generally hits the hardware directly
48 | exposing a known interface via a device for MSCDEX.EXE, which hooks
49 | itself to the int vectors and ADDS functionality to the existing BIOS
50 | and DOS). The problem is the Z64.EXE program, which makes certain
51 | assumptions regarding the environment in which he lives: first off the
52 | drive containing the roms must be writeable -- try to protect the zip
53 | with the zip tools on the pc -- second it assumes to detect
54 | insertion/removal of the disk using the ASPI interface (directly
55 | addressing a "ZIP 100" device. If these requirements are not met it
56 | behaves somewhat weirdly (don't understand why it still works with
57 | 250M zip, but it does, oddly enough)
58 |
59 |
60 |
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36 | ![[ Picture of the Cartridge Reader ]](../../images/socket.jpg)
![[ Picture of N64's bus with my cable ]](../../images/board.jpg)
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