├── .gitignore ├── .vscode └── settings.json ├── Go_Board_Clock_Constraint.sdc ├── Go_Board_Pin_Constraints.pcf ├── LICENSE ├── README.md ├── chapter02 ├── Switches_To_LEDs.v ├── Switches_To_LEDs.vhd ├── Switches_To_LEDs_Project_VHDL │ └── Switches_To_LEDs_Project_VHDL_sbt.project └── Switches_To_LEDs_Project_Verilog │ └── Switches_To_LEDs_Project_Verilog_sbt.project ├── chapter03 ├── And_Gate_Project.v ├── And_Gate_Project.vhd ├── And_Gate_Project_VHDL │ ├── And_Gate_Project_VHDL_sbt.project │ └── And_Gate_Project_VHDL_syn.prj └── And_Gate_Project_Verilog │ ├── And_Gate_Project_Verilog_sbt.project │ └── And_Gate_Project_Verilog_syn.prj ├── chapter04 ├── LED_Toggle_Project.v ├── LED_Toggle_Project.vhd ├── LED_Toggle_Project_VHDL │ ├── LED_Toggle_Project_VHDL_sbt.project │ └── LED_Toggle_Project_VHDL_syn.prj ├── LED_Toggle_Project_Verilog │ ├── LED_Toggle_Project_Verilog_sbt.project │ └── LED_Toggle_Project_Verilog_syn.prj ├── Latch.v └── Latch.vhd ├── chapter05 ├── And_Gate_TB │ ├── And_Gate_Self_Check_TB.sv │ ├── And_Gate_Self_Check_TB.vhd │ ├── And_Gate_TB.v │ └── And_Gate_TB.vhd ├── Debounce_Filter.v ├── Debounce_Filter.vhd ├── Debounce_Filter_TB.v ├── Debounce_Filter_TB.vhd ├── Debounce_Project_Top.v ├── Debounce_Project_Top.vhd ├── Debounce_Project_VHDL │ ├── Debounce_Project_VHDL_sbt.project │ └── Debounce_Project_VHDL_syn.prj └── Debounce_Project_Verilog │ ├── Debounce_Project_Verilog_sbt.project │ └── Debounce_Project_Verilog_syn.prj ├── chapter06 ├── Demux_Count_Project_VHDL │ ├── Count_And_Toggle.vhd │ ├── Demux_Count_Project_Top.vhd │ └── Demux_Count_Project_VHDL_sbt.project ├── Demux_Count_Project_Verilog │ ├── Count_And_Toggle.v │ ├── Demux_Count_Project_Top.v │ ├── Demux_Count_Project_Verilog_Implmnt │ │ └── sbt │ │ │ └── outputs │ │ │ └── bitmap │ │ │ └── Demux_Count_Project_Top_bitmap.bin │ └── Demux_Count_Project_Verilog_sbt.project ├── Demux_LFSR_Project_VHDL │ ├── Demux_LFSR_Project_Top.vhd │ ├── Demux_LFSR_Project_VHDL_Implmnt │ │ └── sbt │ │ │ └── outputs │ │ │ └── bitmap │ │ │ └── Demux_LFSR_Project_Top_bitmap.bin │ ├── Demux_LFSR_Project_VHDL_sbt.project │ └── LFSR_22.vhd ├── Demux_LFSR_Project_Verilog │ ├── Demux_LFSR_Project_Top.v │ ├── Demux_LFSR_Project_Verilog_Implmnt │ │ └── sbt │ │ │ └── outputs │ │ │ └── bitmap │ │ │ └── Demux_LFSR_Project_Top_bitmap.bin │ ├── Demux_LFSR_Project_Verilog_sbt.project │ └── LFSR_22.v ├── Mux_Demux │ ├── Demux_1_To_4.v │ ├── Demux_1_To_4.vhd │ ├── Demux_1_To_4_TB .vhd │ ├── Demux_1_To_4_TB.v │ ├── Mux_4_To_1.v │ ├── Mux_4_To_1.vhd │ ├── Mux_4_To_1_TB.v │ └── Mux_4_To_1_TB.vhd ├── lfsr │ ├── LICENSE │ ├── README.md │ ├── VHDL │ │ ├── sim │ │ │ └── LFSR_TB.vhd │ │ └── source │ │ │ └── LFSR.vhd │ └── Verilog │ │ ├── sim │ │ └── LFSR_TB.v │ │ └── source │ │ └── LFSR.v └── memory │ ├── .vscode │ └── settings.json │ ├── LICENSE │ ├── README.md │ ├── VHDL │ ├── sim │ │ ├── FIFO_TB.vhd │ │ ├── RAM_1Port_TB.vhd │ │ └── RAM_2Port_TB.vhd │ └── source │ │ ├── FIFO.vhd │ │ ├── RAM_1Port.vhd │ │ └── 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